diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.cproject b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.cproject new file mode 100644 index 00000000..abe11a2f --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.project b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.project new file mode 100644 index 00000000..4d2ff9df --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.project @@ -0,0 +1,61 @@ + + + Boot + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.ifx.xmc4000.xmc4000Nature + com.dave.common.daveBenchNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Core + 2 + OPENBLT_CORE + + + + + 1493816189331 + Core + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ARMCM4_XMC4 + + + + 1493816210232 + Core/ARMCM4_XMC4 + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + + + OPENBLT_CORE + $%7BPARENT-3-PROJECT_LOC%7D/Source + + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.settings/com.dave.mbs.xc800.prefs b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.settings/com.dave.mbs.xc800.prefs new file mode 100644 index 00000000..6b077dca --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.settings/com.dave.mbs.xc800.prefs @@ -0,0 +1,14 @@ +ACTIVE_CONFIG_NAME=Debug +AppCompatibilitySet=1 +DEVICE_DESC=Package\= LQFP144 \nROM\= 2 MB Flash \nRAM\= 352 KB RAM \nInOut\= 91 digital I/O \nADC\= 32 ADC Channels, 12-bit, Delta Sigma Demodulator \nDAC\= 2 DAC Channels, 12 bit \nTimed_InOut\= 26 Timer, 48 CAPCOM channels, 2 POSIF \nSerial\= 6 USIC channels, ETH, USB, CAN \nDMA\= 12 DMA channels, ETH DMA, USB DMA \nTouch\= Touch and LED matrix control \nEBU\= MUX, DEMUX, Burst, SDRAM \n +DEVICE_NAME=XMC4700-F144x2048 +DEVICE_PACKAGE=LQFP144 +DEVICE_PACK_VERSION=2.1.20 +DEVICE_PATH=/DeviceRoot/Microcontrollers/XMC4000/XMC4700 Series/XMC4700-F144x2048 +FLASH_SIZE=2048 +MBS_PROVIDER_ID_KEY=com.dave.mbs.xmc4000.xmc4000MbsFactory +SOFTWARE_ID=XMC4.7.00.F144.ALL +TEMPLATE_KEY=com.ifx.xmc4000.appEmptyMainTemplate +USED_DAVE_VERSIONS=4.3.2 +eclipse.preferences.version=1 +minDaveVersion=4.3.2 diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.settings/language.settings.xml b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.settings/language.settings.xml new file mode 100644 index 00000000..9255e366 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.settings/language.settings.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.settings/org.eclipse.cdt.core.prefs b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 00000000..d4995d0c --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,163 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.core.formatter.alignment_for_arguments_in_method_invocation=16 +org.eclipse.cdt.core.formatter.alignment_for_assignment=16 +org.eclipse.cdt.core.formatter.alignment_for_base_clause_in_type_declaration=80 +org.eclipse.cdt.core.formatter.alignment_for_binary_expression=16 +org.eclipse.cdt.core.formatter.alignment_for_compact_if=16 +org.eclipse.cdt.core.formatter.alignment_for_conditional_expression=34 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+S3150C001D10080000000000040C00000400090000008C +S3150C001D200000080C000004000A00000000000C0C67 +S3150C001D30000004000B0000000000100C0000040062 +S3150C001D400C0000000000140C000004000D00000044 +S3150C001D500000180C000004000E00000000001C0C13 +S3150C001D60000004000F000000433A2F576F726B2FD0 +S3150C001D70736F6674776172652F4F70656E424C5443 +S3150C001D802F5461726765742F536F757263652F419B +S3150C001D90524D434D345F584D43342F756172742E3A +S3110C001DA0630000004F70656E424C54004E +S3090C001DAC040000001D +S70508000201EF diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Include/cmsis_compiler.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 00000000..1003929e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,223 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.1 + * @date 30. January 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * ARM Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #include + + #ifndef __NO_RETURN + #define __NO_RETURN __noreturn + #endif + #ifndef __USED + #define __USED __root + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + __packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED __packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct + #endif + + +/* + * TI ARM Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Include/cmsis_gcc.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 00000000..a4ad21a0 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1899 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.1 + * @date 02. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; +#pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +//{ +// __ASM volatile ("nop"); +//} +#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +//{ +// __ASM volatile ("wfi"); +//} +#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +//{ +// __ASM volatile ("wfe"); +//} +#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +//{ +// __ASM volatile ("sev"); +//} +#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Include/core_cm4.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 00000000..38aee9de --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,2103 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 30. January 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Infineon/XMC4700_series/Include/XMC4700.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Infineon/XMC4700_series/Include/XMC4700.h new file mode 100644 index 00000000..d901cb6e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/CMSIS/Infineon/XMC4700_series/Include/XMC4700.h @@ -0,0 +1,17688 @@ +/********************************************************************************************************************* + * Copyright (c) 2015-2016, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + *********************************************************************************************************************/ + + +/****************************************************************************************************//** + * @file XMC4700.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * XMC4700 from Infineon. + * + * @version V1.3.0 (Reference Manual v1.3) + * @date 30. August 2016 + * + * @note Generated with SVDConv V2.87l + * from CMSIS SVD File 'XMC4700_Processed_SVD.xml' Version 1.3.0 (Reference Manual v1.3), + *******************************************************************************************************/ + + + +/** @addtogroup Infineon + * @{ + */ + +/** @addtogroup XMC4700 + * @{ + */ + +#ifndef XMC4700_H +#define XMC4700_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* --------------------- XMC4700 Specific Interrupt Numbers --------------------- */ + SCU_0_IRQn = 0, /*!< 0 System Control */ + ERU0_0_IRQn = 1, /*!< 1 External Request Unit 0 */ + ERU0_1_IRQn = 2, /*!< 2 External Request Unit 0 */ + ERU0_2_IRQn = 3, /*!< 3 External Request Unit 0 */ + ERU0_3_IRQn = 4, /*!< 4 External Request Unit 0 */ + ERU1_0_IRQn = 5, /*!< 5 External Request Unit 1 */ + ERU1_1_IRQn = 6, /*!< 6 External Request Unit 1 */ + ERU1_2_IRQn = 7, /*!< 7 External Request Unit 1 */ + ERU1_3_IRQn = 8, /*!< 8 External Request Unit 1 */ + PMU0_0_IRQn = 12, /*!< 12 Program Management Unit */ + VADC0_C0_0_IRQn = 14, /*!< 14 Analog to Digital Converter Common Block 0 */ + VADC0_C0_1_IRQn = 15, /*!< 15 Analog to Digital Converter Common Block 0 */ + VADC0_C0_2_IRQn = 16, /*!< 16 Analog to Digital Converter Common Block 0 */ + VADC0_C0_3_IRQn = 17, /*!< 17 Analog to Digital Converter Common Block 0 */ + VADC0_G0_0_IRQn = 18, /*!< 18 Analog to Digital Converter Group 0 */ + VADC0_G0_1_IRQn = 19, /*!< 19 Analog to Digital Converter Group 0 */ + VADC0_G0_2_IRQn = 20, /*!< 20 Analog to Digital Converter Group 0 */ + VADC0_G0_3_IRQn = 21, /*!< 21 Analog to Digital Converter Group 0 */ + VADC0_G1_0_IRQn = 22, /*!< 22 Analog to Digital Converter Group 1 */ + VADC0_G1_1_IRQn = 23, /*!< 23 Analog to Digital Converter Group 1 */ + VADC0_G1_2_IRQn = 24, /*!< 24 Analog to Digital Converter Group 1 */ + VADC0_G1_3_IRQn = 25, /*!< 25 Analog to Digital Converter Group 1 */ + VADC0_G2_0_IRQn = 26, /*!< 26 Analog to Digital Converter Group 2 */ + VADC0_G2_1_IRQn = 27, /*!< 27 Analog to Digital Converter Group 2 */ + VADC0_G2_2_IRQn = 28, /*!< 28 Analog to Digital Converter Group 2 */ + VADC0_G2_3_IRQn = 29, /*!< 29 Analog to Digital Converter Group 2 */ + VADC0_G3_0_IRQn = 30, /*!< 30 Analog to Digital Converter Group 3 */ + VADC0_G3_1_IRQn = 31, /*!< 31 Analog to Digital Converter Group 3 */ + VADC0_G3_2_IRQn = 32, /*!< 32 Analog to Digital Converter Group 3 */ + VADC0_G3_3_IRQn = 33, /*!< 33 Analog to Digital Converter Group 3 */ + DSD0_M_0_IRQn = 34, /*!< 34 Delta Sigma Demodulator Main */ + DSD0_M_1_IRQn = 35, /*!< 35 Delta Sigma Demodulator Main */ + DSD0_M_2_IRQn = 36, /*!< 36 Delta Sigma Demodulator Main */ + DSD0_M_3_IRQn = 37, /*!< 37 Delta Sigma Demodulator Main */ + DSD0_A_4_IRQn = 38, /*!< 38 Delta Sigma Demodulator Auxiliary */ + DSD0_A_5_IRQn = 39, /*!< 39 Delta Sigma Demodulator Auxiliary */ + DSD0_A_6_IRQn = 40, /*!< 40 Delta Sigma Demodulator Auxiliary */ + DSD0_A_7_IRQn = 41, /*!< 41 Delta Sigma Demodulator Auxiliary */ + DAC0_0_IRQn = 42, /*!< 42 Digital to Analog Converter */ + DAC0_1_IRQn = 43, /*!< 43 Digital to Analog Converter */ + CCU40_0_IRQn = 44, /*!< 44 Capture Compare Unit 4 (Module 0) */ + CCU40_1_IRQn = 45, /*!< 45 Capture Compare Unit 4 (Module 0) */ + CCU40_2_IRQn = 46, /*!< 46 Capture Compare Unit 4 (Module 0) */ + CCU40_3_IRQn = 47, /*!< 47 Capture Compare Unit 4 (Module 0) */ + CCU41_0_IRQn = 48, /*!< 48 Capture Compare Unit 4 (Module 1) */ + CCU41_1_IRQn = 49, /*!< 49 Capture Compare Unit 4 (Module 1) */ + CCU41_2_IRQn = 50, /*!< 50 Capture Compare Unit 4 (Module 1) */ + CCU41_3_IRQn = 51, /*!< 51 Capture Compare Unit 4 (Module 1) */ + CCU42_0_IRQn = 52, /*!< 52 Capture Compare Unit 4 (Module 2) */ + CCU42_1_IRQn = 53, /*!< 53 Capture Compare Unit 4 (Module 2) */ + CCU42_2_IRQn = 54, /*!< 54 Capture Compare Unit 4 (Module 2) */ + CCU42_3_IRQn = 55, /*!< 55 Capture Compare Unit 4 (Module 2) */ + CCU43_0_IRQn = 56, /*!< 56 Capture Compare Unit 4 (Module 3) */ + CCU43_1_IRQn = 57, /*!< 57 Capture Compare Unit 4 (Module 3) */ + CCU43_2_IRQn = 58, /*!< 58 Capture Compare Unit 4 (Module 3) */ + CCU43_3_IRQn = 59, /*!< 59 Capture Compare Unit 4 (Module 3) */ + CCU80_0_IRQn = 60, /*!< 60 Capture Compare Unit 8 (Module 0) */ + CCU80_1_IRQn = 61, /*!< 61 Capture Compare Unit 8 (Module 0) */ + CCU80_2_IRQn = 62, /*!< 62 Capture Compare Unit 8 (Module 0) */ + CCU80_3_IRQn = 63, /*!< 63 Capture Compare Unit 8 (Module 0) */ + CCU81_0_IRQn = 64, /*!< 64 Capture Compare Unit 8 (Module 1) */ + CCU81_1_IRQn = 65, /*!< 65 Capture Compare Unit 8 (Module 1) */ + CCU81_2_IRQn = 66, /*!< 66 Capture Compare Unit 8 (Module 1) */ + CCU81_3_IRQn = 67, /*!< 67 Capture Compare Unit 8 (Module 1) */ + POSIF0_0_IRQn = 68, /*!< 68 Position Interface (Module 0) */ + POSIF0_1_IRQn = 69, /*!< 69 Position Interface (Module 0) */ + POSIF1_0_IRQn = 70, /*!< 70 Position Interface (Module 1) */ + POSIF1_1_IRQn = 71, /*!< 71 Position Interface (Module 1) */ + CAN0_0_IRQn = 76, /*!< 76 MultiCAN */ + CAN0_1_IRQn = 77, /*!< 77 MultiCAN */ + CAN0_2_IRQn = 78, /*!< 78 MultiCAN */ + CAN0_3_IRQn = 79, /*!< 79 MultiCAN */ + CAN0_4_IRQn = 80, /*!< 80 MultiCAN */ + CAN0_5_IRQn = 81, /*!< 81 MultiCAN */ + CAN0_6_IRQn = 82, /*!< 82 MultiCAN */ + CAN0_7_IRQn = 83, /*!< 83 MultiCAN */ + USIC0_0_IRQn = 84, /*!< 84 Universal Serial Interface Channel (Module 0) */ + USIC0_1_IRQn = 85, /*!< 85 Universal Serial Interface Channel (Module 0) */ + USIC0_2_IRQn = 86, /*!< 86 Universal Serial Interface Channel (Module 0) */ + USIC0_3_IRQn = 87, /*!< 87 Universal Serial Interface Channel (Module 0) */ + USIC0_4_IRQn = 88, /*!< 88 Universal Serial Interface Channel (Module 0) */ + USIC0_5_IRQn = 89, /*!< 89 Universal Serial Interface Channel (Module 0) */ + USIC1_0_IRQn = 90, /*!< 90 Universal Serial Interface Channel (Module 1) */ + USIC1_1_IRQn = 91, /*!< 91 Universal Serial Interface Channel (Module 1) */ + USIC1_2_IRQn = 92, /*!< 92 Universal Serial Interface Channel (Module 1) */ + USIC1_3_IRQn = 93, /*!< 93 Universal Serial Interface Channel (Module 1) */ + USIC1_4_IRQn = 94, /*!< 94 Universal Serial Interface Channel (Module 1) */ + USIC1_5_IRQn = 95, /*!< 95 Universal Serial Interface Channel (Module 1) */ + USIC2_0_IRQn = 96, /*!< 96 Universal Serial Interface Channel (Module 2) */ + USIC2_1_IRQn = 97, /*!< 97 Universal Serial Interface Channel (Module 2) */ + USIC2_2_IRQn = 98, /*!< 98 Universal Serial Interface Channel (Module 2) */ + USIC2_3_IRQn = 99, /*!< 99 Universal Serial Interface Channel (Module 2) */ + USIC2_4_IRQn = 100, /*!< 100 Universal Serial Interface Channel (Module 2) */ + USIC2_5_IRQn = 101, /*!< 101 Universal Serial Interface Channel (Module 2) */ + LEDTS0_0_IRQn = 102, /*!< 102 LED and Touch Sense Control Unit (Module 0) */ + FCE0_0_IRQn = 104, /*!< 104 Flexible CRC Engine */ + GPDMA0_0_IRQn = 105, /*!< 105 General Purpose DMA Unit 0 */ + SDMMC0_0_IRQn = 106, /*!< 106 Multi Media Card Interface */ + USB0_0_IRQn = 107, /*!< 107 Universal Serial Bus (Module 0) */ + ETH0_0_IRQn = 108, /*!< 108 Ethernet (Module 0) */ + GPDMA1_0_IRQn = 110 /*!< 110 General Purpose DMA Unit 1 */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4700.h" /*!< XMC4700 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define OFI_FREQUENCY (24000000UL) /**< 24MHz Backup Clock (fOFI) frequency. */ +#define OSI_FREQUENCY (32768UL) /**< 32KHz Internal Slow Clock source (fOSI) frequency. */ + +/******************************************************************************* + * GLOBAL VARIABLES + *******************************************************************************/ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint8_t g_chipid[16]; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize the system + * + */ +void SystemInit(void); + +/** + * @brief Initialize CPU settings + * + */ +void SystemCoreSetup(void); + +/** + * @brief Initialize clock + * + */ +void SystemCoreClockSetup(void); + +/** + * @brief Update SystemCoreClock variable + * + */ +void SystemCoreClockUpdate(void); + +/** + * @brief Returns frequency of the high performace oscillator + * User needs to overload this function to return the correct oscillator frequency + */ +uint32_t OSCHP_GetFrequency(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/Newlib/syscalls.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/Newlib/syscalls.c new file mode 100644 index 00000000..0ce488cf --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/Newlib/syscalls.c @@ -0,0 +1,100 @@ +/********************************************************************************************************************* + * @file syscalls.c + * @brief Newlib stubs + * @version V1.6 + * @date 20 Apr 2017 + * + * @cond + ********************************************************************************************************************* + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * *************************** Change history ******************************** + * V0.1 : Initial version + * V0.2 : Label updates + * V1.0 : Made _sbrk device agnostic + * V1.1 : C++ support + * V1.2 : Restored compatibility with old project files + * V1.3 Jan 2014, PKB : Encapsulating everything in this file for use only with GCC + * V1.4 11 Dec 2015, JFT : Fix heap overflow + * V1.5 09 Mar 2016, JFT : Add dso_handle to support destructors call at exit + * V1.6 20 Apr 2017, JFT : Foward declaration of __sbrk to fix link time optimization (-flto) compilation errors + * @endcond + */ + +/* + * This file contains stubs for standard C library functionality that must + * typically be provided for the underlying platform. + * + */ +#if defined ( __GNUC__ ) + +#include +#include +#include + +/* Forward prototypes. */ +caddr_t _sbrk(int nbytes) __attribute__((externally_visible)); +void _init(void) __attribute__((externally_visible)); + +/* c++ destructor dynamic shared object needed if -fuse-cxa-atexit is used*/ +void *__dso_handle __attribute__ ((weak)); + +// defined in linker script +extern caddr_t Heap_Bank1_Start; +extern caddr_t Heap_Bank1_End; +caddr_t _sbrk(int nbytes) +{ + static caddr_t heap_ptr = NULL; + caddr_t base; + + if (heap_ptr == NULL) { + heap_ptr = (caddr_t)&Heap_Bank1_Start; + } + + base = heap_ptr; + + /* heap word alignment */ + nbytes = (nbytes + 3) & ~0x3U; + if ((caddr_t)&Heap_Bank1_End > (heap_ptr + nbytes)) + { + heap_ptr += nbytes; + return (base); + } + else + { + /* Heap overflow */ + errno = ENOMEM; + return ((caddr_t)-1); + } +} + +/* Init */ +void _init(void) +{} + +#endif /* __GNUC__ */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_ccu4_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_ccu4_map.h new file mode 100644 index 00000000..6dd7295f --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_ccu4_map.h @@ -0,0 +1,4976 @@ +/** + * @file xmc4_ccu4_map.h + * @date 2015-12-07 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-08-25: + * - Initial version + * + * 2015-12-07: + * - Add XMC4300 support + * + * @endcond + */ + +#ifndef XMC4_CCU4_MAP_H +#define XMC4_CCU4_MAP_H + +#define XMC_CCU4_SLICE_INPUT_A (0U) +#define XMC_CCU4_SLICE_INPUT_B (1U) +#define XMC_CCU4_SLICE_INPUT_C (2U) +#define XMC_CCU4_SLICE_INPUT_D (3U) +#define XMC_CCU4_SLICE_INPUT_E (4U) +#define XMC_CCU4_SLICE_INPUT_F (5U) +#define XMC_CCU4_SLICE_INPUT_G (6U) +#define XMC_CCU4_SLICE_INPUT_H (7U) +#define XMC_CCU4_SLICE_INPUT_I (8U) +#define XMC_CCU4_SLICE_INPUT_J (9U) +#define XMC_CCU4_SLICE_INPUT_K (10U) +#define XMC_CCU4_SLICE_INPUT_L (11U) +#define XMC_CCU4_SLICE_INPUT_M (12U) +#define XMC_CCU4_SLICE_INPUT_N (13U) +#define XMC_CCU4_SLICE_INPUT_O (14U) +#define XMC_CCU4_SLICE_INPUT_P (15U) + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_HRPWM0_QOUT3 7 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_HRPWM0_QOUT1 7 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_HRPWM0_QOUT2 7 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_HRPWM0_QOUT3 7 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_HRPWM0_QOUT1 7 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_HRPWM0_QOUT2 7 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_HRPWM0_QOUT3 7 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_HRPWM0_QOUT1 7 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_HRPWM0_QOUT2 7 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_HRPWM0_QOUT3 7 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_HRPWM0_QOUT1 7 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_HRPWM0_QOUT2 7 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + +#endif /* XMC4_CCU4_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_ccu8_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_ccu8_map.h new file mode 100644 index 00000000..33c53684 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_ccu8_map.h @@ -0,0 +1,2596 @@ +/** + * @file xmc4_ccu8_map.h + * @date 2015-12-07 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-08-25: + * - Initial version + * + * 2015-12-07: + * - Add XMC4300 support + * + * @endcond + */ + +#ifndef XMC4_CCU8_MAP_H +#define XMC4_CCU8_MAP_H + +#define XMC_CCU8_SLICE_INPUT_A (0U) +#define XMC_CCU8_SLICE_INPUT_B (1U) +#define XMC_CCU8_SLICE_INPUT_C (2U) +#define XMC_CCU8_SLICE_INPUT_D (3U) +#define XMC_CCU8_SLICE_INPUT_E (4U) +#define XMC_CCU8_SLICE_INPUT_F (5U) +#define XMC_CCU8_SLICE_INPUT_G (6U) +#define XMC_CCU8_SLICE_INPUT_H (7U) +#define XMC_CCU8_SLICE_INPUT_I (8U) +#define XMC_CCU8_SLICE_INPUT_J (9U) +#define XMC_CCU8_SLICE_INPUT_K (10U) +#define XMC_CCU8_SLICE_INPUT_L (11U) +#define XMC_CCU8_SLICE_INPUT_M (12U) +#define XMC_CCU8_SLICE_INPUT_N (13U) +#define XMC_CCU8_SLICE_INPUT_O (14U) +#define XMC_CCU8_SLICE_INPUT_P (15U) + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + +#endif /* XMC4_CCU8_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_eru_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_eru_map.h new file mode 100644 index 00000000..1959469e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_eru_map.h @@ -0,0 +1,2134 @@ +/** + * @file xmc4_eru_map.h + * @date 2016-10-27 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial version + * + * 2015-12-07: + * - Add XMC4300 support + * + * 2016-10-27: + * - Fixed: Remove incorrect ERU0_ETL1_INPUTB_P0_1 and replace it by ERU0_ETL1_INPUTB_SCU_HIB_SR1 + * + * @endcond + */ + +#ifndef XMC4_ERU_MAP_H +#define XMC4_ERU_MAP_H + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ +#define ERU0_ETL0 XMC_ERU0, 0 +#define ERU0_ETL1 XMC_ERU0, 1 +#define ERU0_ETL2 XMC_ERU0, 2 +#define ERU0_ETL3 XMC_ERU0, 3 + +#define ERU0_OGU0 XMC_ERU0, 0 +#define ERU0_OGU1 XMC_ERU0, 1 +#define ERU0_OGU2 XMC_ERU0, 2 +#define ERU0_OGU3 XMC_ERU0, 3 + +#define ERU1_ETL0 XMC_ERU1, 0 +#define ERU1_ETL1 XMC_ERU1, 1 +#define ERU1_ETL2 XMC_ERU1, 2 +#define ERU1_ETL3 XMC_ERU1, 3 + +#define ERU1_OGU0 XMC_ERU1, 0 +#define ERU1_OGU1 XMC_ERU1, 1 +#define ERU1_OGU2 XMC_ERU1, 2 +#define ERU1_OGU3 XMC_ERU1, 3 + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + +#endif /* XMC4_ERU_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_flash.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_flash.h new file mode 100644 index 00000000..3a9cd61e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_flash.h @@ -0,0 +1,705 @@ +/** + * @file xmc4_flash.h + * @date 2016-03-22 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2014-12-10: + * - Initial
+ * 2015-02-20: + * - Updated for Documentation related changes
+ * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * 2015-08-17: + * - Added the below API's to the public interface. + * 1. XMC_FLASH_Reset + * 2. XMC_FLASH_ErasePhysicalSector + * 3. XMC_FLASH_EraseUCB + * 4. XMC_FLASH_ResumeProtection + * 5. XMC_FLASH_RepairPhysicalSector + * - Added support for XMC4800/4700 devices + * 2015-12-07: + * - Fix XMC_FLASH_READ_ACCESS_TIME for XMC43, 47 and 48 devices + * 2016-03-18: + * - Fix implementation of XMC_PREFETCH_EnableInstructionBuffer and XMC_PREFETCH_DisableInstructionBuffer + * 2016-03-22: + * - Fix implementation of XMC_PREFETCH_InvalidateInstructionBuffer + * @endcond + * + */ + +#ifndef XMC4_FLASH_H +#define XMC4_FLASH_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_common.h" + +#if UC_FAMILY == XMC4 + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup FLASH + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_FLASH_UNCACHED_BASE (0x0C000000U) /**< Non cached flash starting address of for + XMC4 family of microcontrollers */ +#define XMC_FLASH_WORDS_PER_PAGE (64UL) /**< Number of words in a page (256 bytes / 4 bytes = 64 words)*/ +#define XMC_FLASH_BYTES_PER_PAGE (256UL) /**< Number of bytes in a page*/ + +#define XMC_FLASH_UCB0 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0000UL) /**< Starting address of User + Configurable Block 0*/ +#define XMC_FLASH_UCB1 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0400UL) /**< Starting address of User + Configurable Block 1*/ +#define XMC_FLASH_UCB2 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0800UL) /**< Starting address of User + Configurable Block 2*/ +#define XMC_FLASH_BYTES_PER_UCB (1024UL) /**< Number of bytes in a user configurable block*/ + +/**< Note : Total number of Sectors depends on the flash size of the controller. So while using these macros for flash + * operations ensure that sector is available, other may lead to flash error. + */ +#define XMC_FLASH_SECTOR_0 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x00000UL) /** + * + */ +typedef enum XMC_FLASH_PROTECTION +{ + XMC_FLASH_PROTECTION_WRITE_SECTOR_0 = 0x0001UL, /**< Sector 0 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_1 = 0x0002UL, /**< Sector 1 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_2 = 0x0004UL, /**< Sector 3 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_3 = 0x0008UL, /**< Sector 3 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_4 = 0x0010UL, /**< Sector 4 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_5 = 0x0020UL, /**< Sector 5 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_6 = 0x0040UL, /**< Sector 6 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_7 = 0x0080UL, /**< Sector 7 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_8 = 0x0100UL, /**< Sector 8 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_9 = 0x0200UL, /**< Sector 9 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTORS_10_11 = 0x0400UL, /**< Sector 10 and 11 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTORS_12_13 = 0x0800UL, /**< Sector 12 and 13 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTORS_14_15 = 0x1000UL, /**< Sector 14 and 15 write protection */ + XMC_FLASH_PROTECTION_READ_GLOBAL = 0x8000UL /**< Global read protection (Applicable for UserLevel0 alone)*/ +} XMC_FLASH_PROTECTION_t; + +/********************************************************************************************************************* + * API PROTOTYPES + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Enables the wait state for error correction.process, It enables one additional wait state for ECC by setting WSECPF + * bit of FCON register.\n + * + * \parRelated APIs:
+ * XMC_FLASH_DisableWaitStateForECC()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_EnableWaitStateForECC(void) +{ + FLASH0->FCON |= FLASH_FCON_WSECPF_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Disables the wait state for error correction.\n\n Removes additional wait state for ECC by resetting WSECPF bit of + * FCON register.\n + * + * \parRelated APIs:
+ * XMC_FLASH_EnableWaitStateForECC()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_DisableWaitStateForECC(void) +{ + FLASH0->FCON &= (uint32_t)~FLASH_FCON_WSECPF_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Enables dynamic idle mode feature to save power.\n\n It switches off the PFLASH read path when no read access is + * pending. Hence power is saved marginally. This slightly reduces the flash read performance because static + * pre-fetching is disabled.It sets the FCON register IDLE bit to enable this feature. + * + * \parRelated APIs:
+ * XMC_FLASH_DisableDynamicIdle()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_EnableDynamicIdle(void) +{ + FLASH0->FCON |= FLASH_FCON_IDLE_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Disables dynamic idle mode feature.\n\n It resets the FCON register IDLE bit to disable this feature. Hence normal + * flash read operation is selected. + * + * \parRelated APIs:
+ * XMC_FLASH_EnableDynamicIdle()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_DisableDynamicIdle(void) +{ + FLASH0->FCON &= (uint32_t)~FLASH_FCON_IDLE_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Enables sleep mode of the PFLASH.\n\n Sleep mode is enabled by setting the bit FCON.SLEEP. + * + * \parNote:
+ * fCPU must be equal or above 1 MHz when wake-up request is triggered. + * + * \parRelated APIs:
+ * XMC_FLASH_DisableSleepRequest()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_EnableSleepRequest(void) +{ + FLASH0->FCON |= (uint32_t)FLASH_FCON_SLEEP_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Wake-up the PFLASH from sleep.\n\n Wakes-up from sleep is done by clearing the bit FCON.SLEEP, if selected via this + * bit, or wake-up is initiated by releasing the external sleep signal from SCU. + * + * \parNote:
+ * fCPU must be equal or above 1 MHz when wake-up request is triggered. + * + * \parRelated APIs:
+ * XMC_FLASH_EnableSleepRequest()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_DisableSleepRequest(void) +{ + FLASH0->FCON &= (uint32_t)~FLASH_FCON_SLEEP_Msk; +} + +/** + * + * @param margin PFLASH margin selection. Use type @ref XMC_FLASH_MARGIN_t. + * + * @return None + * + * \parDescription:
+ * Sets the read margin levels for checking the healthiness of flash data.\n\n Configures the margin field of MARP + * MARP register with the specified \a margin level. It changes the margin levels for read operations to find + * problematic array bits. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_FLASH_SetMargin(const XMC_FLASH_MARGIN_t margin) +{ + FLASH0->MARP = (FLASH0->MARP & (uint32_t)~FLASH_MARP_MARGIN_Msk) | margin; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Enables double bit error trap.\n\n. It enables by setting MARP register bit TRAPDIS. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_FLASH_EnableDoubleBitErrorTrap(void) +{ + FLASH0->MARP &= (uint32_t)~FLASH_MARP_TRAPDIS_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Disables the trap generation for double bit error by clearing MARP register bit TRAPDIS.\n\n The double-bit error + * trap can be disabled for margin checks and also redirected to an error interrupt. Any time during the execution the + * double bit error trap can be enabled back by calling XMC_FLASH_EnableDoubleBitErrorTrap() API. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_FLASH_DisableDoubleBitErrorTrap(void) +{ + FLASH0->MARP |= FLASH_MARP_TRAPDIS_Msk; +} + +/** + * + * @param num_wait_states number of wait states for initial read access
Range: [0 to 15] + * + * @return None + * + * \parDescription:
+ * Configures the number of wait states for initial flash read access.\n\n Depending on the configured \a + * num_wait_states value into FCON resister \a WSPFLASH field, the read performance gets optimized . The wait cycles + * for the flash read access must be configured based on the CPU frequency (fCPU), in relation to the flash access + * time (\a ta) defined. The access time formula (\a WSPFLASH x (\a \a \a 1 / fCPU) \a >= \a ta) applies only for + * the values \a \a \a num_wait_states >0. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_FLASH_SetWaitStates(uint32_t num_wait_states) +{ + FLASH0->FCON = (FLASH0->FCON & (uint32_t)~FLASH_FCON_WSPFLASH_Msk) | + (num_wait_states << FLASH_FCON_WSPFLASH_Pos); +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Configures the cacheable accesses to use the instruction buffer by resetting the register bit PREF_PCON.IBYP. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_PREFETCH_EnableInstructionBuffer(void) +{ + PREF->PCON &= (uint32_t)~PREF_PCON_IBYP_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Bypasses the instruction buffer for cacheable accesses, by setting the register bit PREF_PCON.IBYP. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_PREFETCH_DisableInstructionBuffer(void) +{ + PREF->PCON |= PREF_PCON_IBYP_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Invalidates the instruction buffer by setting PREF_PCON register bit IINV.\n\n After system reset, the instruction + * buffer is automatically invalidated. + * + * \parNote:
+ * The complete invalidation operation is performed in a single cycle. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_PREFETCH_InvalidateInstructionBuffer(void) +{ + PREF->PCON |= PREF_PCON_IINV_Msk; + __DSB(); + __ISB(); + + PREF->PCON &= ~PREF_PCON_IINV_Msk; + __DSB(); + __ISB(); + +} + +/** + * + * @param user ID number of the user configuration block (UCB).
Range: [0 to 2] + * + * @param protection_mask ORed values of @ref XMC_FLASH_PROTECTION_t enum type, for which sectors the protection + * has to be enabled. + * @param password_0 First password for protection.
Range: [0 to 4294967295] + * @param password_1 Second password for protection.
Range: [0 to 4294967295] + * + * @return None + * + * \parDescription:
+ * Installs the global read and sector write protection.\n\n The installation starts by issuing the page mode entry + * command followed by the load page command. The load page command mode loads the required sectors intended for + * protection specified in \a protection_mask. It also loads the specified passwords \a password0 and \a password1 + * respectively. Finally, it issues the write page command for the specified \a user configuration block. Calling + * XMC_FLASH_ConfirmProtection() after this API completes the protection process by freezing the sectors forever. + * + * + * \parRelated APIs:
+ * XMC_FLASH_ConfirmProtection()
+ * XMC_FLASH_VerifyReadProtection()
+ */ +void XMC_FLASH_InstallProtection(uint8_t user, + uint32_t protection_mask, + uint32_t password_0, + uint32_t password_1); + +/** + * + * @param user ID number of the user configuration block (UCB).
Range: [0 to 2] + * + * @return None + * + * \parDescription:
+ * Confirms the protection, so that sectors specified under \a user configurable block are locked forever.\n\n The + * protection shall be installed by calling XMC_FLASH_InstallProtection() before calling this API. + * The confirmation starts by issuing the page mode entry command followed by the load page command. The load page + * command issues the confirmation protection command for the sectors on which the protection installation was done. + * It also loads the specified passwords \a password0 and \a password1 respectively. Finally, it issues the confirm + * protection command for the specified \a user configuration block so that the sectors will be protected forever. + * + * \parRelated APIs:
+ * XMC_FLASH_InstallProtection()
+ * + */ +void XMC_FLASH_ConfirmProtection(uint8_t user); + +/** + * + * @param password_0 First password used for protection.
Range: [0 to 4294967295] + * @param password_1 Second password used for protection.
Range: [0 to 4294967295] + * + * @return true if read protection installed properly else returns \a false. + * + * \parDescription:
+ * Verifies sector read protection is properly installed or not.\n\n Before entering into verify read protection + * process, it clears the error status bits inside status register. It temporarily disables the protection with + * passwords \a password0 and \a password1 respectively. It reads the FSR register and verifies the protection state. + * Resumption of read protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset. + * + * \parRelated APIs:
+ * XMC_FLASH_InstallProtection()
+ * XMC_FLASH_VerifyWriteProtection()
+ * XMC_FLASH_ResumeProtection()
+ */ +bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1); + +/** + * + * @param user ID number of the user configuration block (UCB).
Range: [0 to 2] + * + * @param protection_mask ORed values of @ref XMC_FLASH_PROTECTION_t enum type, for which sectors the protection + * has to be verified. + * @param password_0 First password used for protection.
Range: [0 to 4294967295] + * @param password_1 Second password used for protection.
Range: [0 to 4294967295] + * + * @return true if write protection installed properly else returns \a false. + * + * \parDescription:
+ * Verifies sector read protection is properly installed or not.\n\n Before entering into verify read protection + * process, it clears the error status bits inside status register. It temporarily disables the protection with + * passwords \a password0 and \a password1 respectively for the intended sectors specified in \a protection_mask. + * It reads the FSR register and verifies the write protection state. + * Resumption of write protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset. + * + * \parRelated APIs:
+ * XMC_FLASH_InstallProtection()
+ * XMC_FLASH_VerifyReadProtection()
+ * XMC_FLASH_ResumeProtection()
+ */ +bool XMC_FLASH_VerifyWriteProtection(uint32_t user, + uint32_t protection_mask, + uint32_t password_0, + uint32_t password_1); + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Resumes flash protection as it was configured before.\n\n + * It clears all the disable proection status flags FSR.WPRODISx and FSR.RPRODIS. But FSR.WPRODISx is not + * cleared when corresponding UCBx is not in the “confirmed” state. + * + * \parRelated APIs:
+ * None + */ +void XMC_FLASH_ResumeProtection(void); + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Repairs the physical sector "PS4".\n\n + * For selected devices, Erase Physical Sector can also be used for Sector Soft Repair, depending on the configuration + * of PROCON1.PSR. This command sequence is required to run an EEPROM emulation algorithm that cycles the logical + * sectors S4..S7 of PS4. This command sequence repairs the corrupted logical sectors inside the physical sector due to + * interrupted erase operation. + * + * \parRelated APIs:
+ * None + */ +void XMC_FLASH_RepairPhysicalSector(void); +/** + * + * @param sector_start_address Pointer to the starting address of physical sector. Use XMC_FLASH_SECTOR_x MACRO defined + * in xmc4_flash.h file. + * + * @return None + * + * \parDescription:
+ * Erases the physical sector "PSA".\n\n If "PSA" does not point to base address of a correct sector or an unavailable + * sector, it returns SQER. + * + * + * \parRelated APIs:
+ * None + */ +void XMC_FLASH_ErasePhysicalSector(uint32_t *sector_start_address); + +/** + * + * @param ucb_sector_start_address Pointer to the starting address of physical sector. Use XMC_FLASH_UCBx MACRO + * defined in xmc4_flash.h file. + * + * @return None + * + * \parDescription:
+ * The addressed user configuration block “UCB” is erased.\n\n + * Erases UCB whose startting address specified in the input parameter \a ucb_sector_start_address. When the UCB has + * an active write protection or the Flash module has an active global read protection the execution fails and + * PROER is set. The command fails with SQER when \a ucb_sector_start_address is not the start address of a valid UCB. + * Call \ref XMC_FLASH_GetStatus API after this API to verify the erase was proper ot not. + * + * \parRelated APIs:
+ * None + */ +void XMC_FLASH_EraseUCB(uint32_t *ucb_sector_start_address); + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Resets the command interpreter to its initial state.\n\n + * Reset to Read can cancel every command sequence before its last command cycle has been received. All error flags + * gets cleared by calling this API. + * \parNote:
+ * todo + * + * \parRelated APIs:
+ * None + */ +void XMC_FLASH_Reset(void); + + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif + +#endif + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_gpio.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_gpio.h new file mode 100644 index 00000000..3234782d --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_gpio.h @@ -0,0 +1,345 @@ +/** + * @file xmc4_gpio.h + * @date 2015-10-09 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-10-09: + * - Added PORT MACRO checks and definitions for XMC4800/4700 devices + * @endcond + * + */ + +#ifndef XMC4_GPIO_H +#define XMC4_GPIO_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_common.h" + +#if UC_FAMILY == XMC4 + +#include "xmc4_gpio_map.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup GPIO + * @{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +#if defined(PORT0) +#define XMC_GPIO_PORT0 ((XMC_GPIO_PORT_t *) PORT0_BASE) +#define XMC_GPIO_CHECK_PORT0(port) (port == XMC_GPIO_PORT0) +#else +#define XMC_GPIO_CHECK_PORT0(port) 0 +#endif + +#if defined(PORT1) +#define XMC_GPIO_PORT1 ((XMC_GPIO_PORT_t *) PORT1_BASE) +#define XMC_GPIO_CHECK_PORT1(port) (port == XMC_GPIO_PORT1) +#else +#define XMC_GPIO_CHECK_PORT1(port) 0 +#endif + +#if defined(PORT2) +#define XMC_GPIO_PORT2 ((XMC_GPIO_PORT_t *) PORT2_BASE) +#define XMC_GPIO_CHECK_PORT2(port) (port == XMC_GPIO_PORT2) +#else +#define XMC_GPIO_CHECK_PORT2(port) 0 +#endif + +#if defined(PORT3) +#define XMC_GPIO_PORT3 ((XMC_GPIO_PORT_t *) PORT3_BASE) +#define XMC_GPIO_CHECK_PORT3(port) (port == XMC_GPIO_PORT3) +#else +#define XMC_GPIO_CHECK_PORT3(port) 0 +#endif + +#if defined(PORT4) +#define XMC_GPIO_PORT4 ((XMC_GPIO_PORT_t *) PORT4_BASE) +#define XMC_GPIO_CHECK_PORT4(port) (port == XMC_GPIO_PORT4) +#else +#define XMC_GPIO_CHECK_PORT4(port) 0 +#endif + +#if defined(PORT5) +#define XMC_GPIO_PORT5 ((XMC_GPIO_PORT_t *) PORT5_BASE) +#define XMC_GPIO_CHECK_PORT5(port) (port == XMC_GPIO_PORT5) +#else +#define XMC_GPIO_CHECK_PORT5(port) 0 +#endif + +#if defined(PORT6) +#define XMC_GPIO_PORT6 ((XMC_GPIO_PORT_t *) PORT6_BASE) +#define XMC_GPIO_CHECK_PORT6(port) (port == XMC_GPIO_PORT6) +#else +#define XMC_GPIO_CHECK_PORT6(port) 0 +#endif + +#if defined(PORT7) +#define XMC_GPIO_PORT7 ((XMC_GPIO_PORT_t *) PORT7_BASE) +#define XMC_GPIO_CHECK_PORT7(port) (port == XMC_GPIO_PORT7) +#else +#define XMC_GPIO_CHECK_PORT7(port) 0 +#endif + +#if defined(PORT8) +#define XMC_GPIO_PORT8 ((XMC_GPIO_PORT_t *) PORT8_BASE) +#define XMC_GPIO_CHECK_PORT8(port) (port == XMC_GPIO_PORT8) +#else +#define XMC_GPIO_CHECK_PORT8(port) 0 +#endif + +#if defined(PORT9) +#define XMC_GPIO_PORT9 ((XMC_GPIO_PORT_t *) PORT9_BASE) +#define XMC_GPIO_CHECK_PORT9(port) (port == XMC_GPIO_PORT9) +#else +#define XMC_GPIO_CHECK_PORT9(port) 0 +#endif + +#if defined(PORT14) +#define XMC_GPIO_PORT14 ((XMC_GPIO_PORT_t *) PORT14_BASE) +#define XMC_GPIO_CHECK_PORT14(port) (port == XMC_GPIO_PORT14) +#else +#define XMC_GPIO_CHECK_PORT14(port) 0 +#endif + +#if defined(PORT15) +#define XMC_GPIO_PORT15 ((XMC_GPIO_PORT_t *) PORT15_BASE) +#define XMC_GPIO_CHECK_PORT15(port) (port == XMC_GPIO_PORT15) +#else +#define XMC_GPIO_CHECK_PORT15(port) 0 +#endif + +#define XMC_GPIO_CHECK_PORT(port) (XMC_GPIO_CHECK_PORT0(port) || \ + XMC_GPIO_CHECK_PORT1(port) || \ + XMC_GPIO_CHECK_PORT2(port) || \ + XMC_GPIO_CHECK_PORT3(port) || \ + XMC_GPIO_CHECK_PORT4(port) || \ + XMC_GPIO_CHECK_PORT5(port) || \ + XMC_GPIO_CHECK_PORT6(port) || \ + XMC_GPIO_CHECK_PORT7(port) || \ + XMC_GPIO_CHECK_PORT8(port) || \ + XMC_GPIO_CHECK_PORT9(port) || \ + XMC_GPIO_CHECK_PORT14(port) || \ + XMC_GPIO_CHECK_PORT15(port)) + +#define XMC_GPIO_CHECK_OUTPUT_PORT(port) (XMC_GPIO_CHECK_PORT0(port) || \ + XMC_GPIO_CHECK_PORT1(port) || \ + XMC_GPIO_CHECK_PORT2(port) || \ + XMC_GPIO_CHECK_PORT3(port) || \ + XMC_GPIO_CHECK_PORT4(port) || \ + XMC_GPIO_CHECK_PORT5(port) || \ + XMC_GPIO_CHECK_PORT6(port) || \ + XMC_GPIO_CHECK_PORT7(port) || \ + XMC_GPIO_CHECK_PORT8(port) || \ + XMC_GPIO_CHECK_PORT9(port)) + +#define XMC_GPIO_CHECK_ANALOG_PORT(port) (XMC_GPIO_CHECK_PORT14(port) || \ + XMC_GPIO_CHECK_PORT15(port)) + +#define XMC_GPIO_CHECK_OUTPUT_STRENGTH(strength) ((strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE) ||\ + (strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE) ||\ + (strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE) ||\ + (strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE) ||\ + (strength == XMC_GPIO_OUTPUT_STRENGTH_MEDIUM) ||\ + (strength == XMC_GPIO_OUTPUT_STRENGTH_WEAK)) + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + +/** + * Defines the direction and characteristics of a pin. Use type \a XMC_GPIO_MODE_t for this enum. For the operation + * with alternate functions, the port pins are directly connected to input or output functions of the on-chip periphery. + */ + +typedef enum XMC_GPIO_MODE +{ + XMC_GPIO_MODE_INPUT_TRISTATE = 0x0UL << PORT0_IOCR0_PC0_Pos, /**< No internal pull device active */ + XMC_GPIO_MODE_INPUT_PULL_DOWN = 0x1UL << PORT0_IOCR0_PC0_Pos, /**< Internal pull-down device active */ + XMC_GPIO_MODE_INPUT_PULL_UP = 0x2UL << PORT0_IOCR0_PC0_Pos, /**< Internal pull-up device active */ + XMC_GPIO_MODE_INPUT_SAMPLING = 0x3UL << PORT0_IOCR0_PC0_Pos, /**< No internal pull device active;Pn_OUTx continuously samples the input value */ + XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE = 0x4UL << PORT0_IOCR0_PC0_Pos, /**< Inverted no internal pull device active */ + XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN = 0x5UL << PORT0_IOCR0_PC0_Pos, /**< Inverted internal pull-down device active */ + XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP = 0x6UL << PORT0_IOCR0_PC0_Pos, /**< Inverted internal pull-up device active */ + XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING = 0x7UL << PORT0_IOCR0_PC0_Pos, /**< Inverted no internal pull device active; Pn_OUTx continuously samples the input value */ + XMC_GPIO_MODE_OUTPUT_PUSH_PULL = 0x80UL, /**< Push-pull general-purpose output */ + XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN = 0xc0UL, /**< Open-drain general-purpose output */ + XMC_GPIO_MODE_OUTPUT_ALT1 = 0x1UL << PORT0_IOCR0_PC0_Pos, + XMC_GPIO_MODE_OUTPUT_ALT2 = 0x2UL << PORT0_IOCR0_PC0_Pos, + XMC_GPIO_MODE_OUTPUT_ALT3 = 0x3UL << PORT0_IOCR0_PC0_Pos, + XMC_GPIO_MODE_OUTPUT_ALT4 = 0x4UL << PORT0_IOCR0_PC0_Pos, + XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT1, /**< Push-pull alternate output function 1 */ + XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT2, /**< Push-pull alternate output function 2 */ + XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT3, /**< Push-pull alternate output function 3 */ + XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT4, /**< Push-pull alternate output function 4 */ + XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT1, /**< Open drain alternate output function 1 */ + XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT2, /**< Open drain alternate output function 2 */ + XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT3, /**< Open drain alternate output function 3 */ + XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT4, /**< Open drain alternate output function 4 */ +} XMC_GPIO_MODE_t; + +/** + * Defines output strength and slew rate of a pin. Use type \a XMC_GPIO_OUTPUT_STRENGTH_t for this enum. + * + */ +typedef enum XMC_GPIO_OUTPUT_STRENGTH +{ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE = 0x0U, /**< Defines pad driver mode, for high speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE = 0x1U, /**< Defines pad driver mode, for high speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE = 0x2U, /**< Defines pad driver mode, medium speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE = 0x3U, /**< Defines pad driver mode, medium speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_MEDIUM = 0x4U, /**< Defines pad driver mode, for low speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_WEAK = 0x7U /**< Defines pad driver mode, low speed 3.3V LVTTL outputs */ +} XMC_GPIO_OUTPUT_STRENGTH_t; + + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ +/** + * Structure points port hardware registers. Use type XMC_GPIO_PORT_t for this structure. + */ + +typedef struct XMC_GPIO_PORT { + __IO uint32_t OUT; /**< The port output register determines the value of a GPIO pin when it is selected by + Pn_IOCRx as output */ + __O uint32_t OMR; /**< The port output modification register contains control bits that make it possible + to individually set, reset, or toggle the logic state of a single port line*/ + __I uint32_t RESERVED0[2]; + __IO uint32_t IOCR[4]; /**< The port input/output control registers select the digital output and input driver + functionality and characteristics of a GPIO port pin */ + __I uint32_t RESERVED1; + __I uint32_t IN; /**< The logic level of a GPIO pin can be read via the read-only port input register + Pn_IN */ + __I uint32_t RESERVED2[6]; + __IO uint32_t PDR[2]; /**< Pad Driver Mode Registers */ + + __I uint32_t RESERVED3[6]; + __IO uint32_t PDISC; /**< Pin Function Decision Control Register is to disable/enable the digital pad + structure in shared analog and digital ports*/ + __I uint32_t RESERVED4[3]; + __IO uint32_t PPS; /**< Pin Power Save Register */ + __IO uint32_t HWSEL; /**< Pin Hardware Select Register */ +} XMC_GPIO_PORT_t; + +/** + * Structure initializes port pin. Use type XMC_GPIO_CONFIG_t for this structure. + */ +typedef struct XMC_GPIO_CONFIG +{ + XMC_GPIO_MODE_t mode; /**< Defines the direction and characteristics of a pin */ + XMC_GPIO_OUTPUT_LEVEL_t output_level; /**< Defines output level of a pin */ + XMC_GPIO_OUTPUT_STRENGTH_t output_strength; /**< Defines pad driver mode of a pin */ +} XMC_GPIO_CONFIG_t; + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +__STATIC_INLINE bool XMC_GPIO_IsModeValid(XMC_GPIO_MODE_t mode) +{ + return ((mode == XMC_GPIO_MODE_INPUT_TRISTATE) || + (mode == XMC_GPIO_MODE_INPUT_PULL_DOWN) || + (mode == XMC_GPIO_MODE_INPUT_PULL_UP) || + (mode == XMC_GPIO_MODE_INPUT_SAMPLING) || + (mode == XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE) || + (mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN) || + (mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP) || + (mode == XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING) || + (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL) || + (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1) || + (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2) || + (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3) || + (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4) || + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN) || + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1) || + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2) || + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3) || + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4)); +} + +/** + * + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDR. + * @param pin Port pin number. + * @param strength Output driver mode selection. Refer data structure @ref XMC_GPIO_OUTPUT_STRENGTH_t for details. + * + * @return None + * + * \parDescription:
+ * Sets port pin output strength and slew rate. It configures hardware registers Pn_PDR. \a strength is initially + * configured during initialization in XMC_GPIO_Init(). Call this API to alter output driver mode as needed later in + * the program. + * + * \parRelated APIs:
+ * None + * + * \parNote:
+ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). + * + */ + +void XMC_GPIO_SetOutputStrength(XMC_GPIO_PORT_t *const port, const uint8_t pin, XMC_GPIO_OUTPUT_STRENGTH_t strength); + +/** + * @} (end addtogroup GPIO) + */ + +/** + * @} (end addtogroup XMClib) + */ + +#endif /* UC_FAMILY == XMC4 */ + +#endif /* XMC4_GPIO_H */ + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_gpio_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_gpio_map.h new file mode 100644 index 00000000..7397a381 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_gpio_map.h @@ -0,0 +1,7535 @@ +/** + * @file xmc4_gpio_map.h + * @date 2016-08-22 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * + * 2015-06-20: + * - Updated copyright information + * + * 2015-11-12: + * - Added XMC4800 + * + * 2015-06-20: + * - Missing CAN_N0_TXD connectivity + * - VADC_EMUXn_IN replaced by VADC_EMUX0xy + * - DSD_MCLKOUT replaced by DSD_MCLKx + * - Missing connectivity for XMC48/47 + * + * 2015-12-07: + * - Add XMC4300 support + * + * 2016-03-09: + * - Fixed SDMMC signals names + * - Added P2_0_AF_CAN_N0_TXD for XMC44xx + * - Added P1_9_AF_U0C0_SCLKOUT, P4_7_AF_U2C1_DOUT0, P6_6_AF_U2C0_DOUT0 for XMC47/48 BGA196 + * + * 2016-03-22: + * - Fixed EBU CS signal names + * + * 2016-08-22: + * - Added P2_0_AF_CAN_N0_TXD for XMC4300 + * + * @endcond + * + * @brief XMC pin mapping definitions + */ + +#ifndef XMC4_GPIO_MAP_H +#define XMC4_GPIO_MAP_H + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX22 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX22 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX22 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX22 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_6_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_11_AF_ECAT0_LED_STATE_RUN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_10_AF_ECAT0_SYNC1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_1_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_12_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_15_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_15_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_15_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_15_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P7_0 XMC_GPIO_PORT7, 0 +#define P7_1 XMC_GPIO_PORT7, 1 +#define P7_2 XMC_GPIO_PORT7, 2 +#define P7_3 XMC_GPIO_PORT7, 3 +#define P7_4 XMC_GPIO_PORT7, 4 +#define P7_5 XMC_GPIO_PORT7, 5 +#define P7_6 XMC_GPIO_PORT7, 6 +#define P7_7 XMC_GPIO_PORT7, 7 +#define P7_8 XMC_GPIO_PORT7, 8 +#define P7_9 XMC_GPIO_PORT7, 9 +#define P7_10 XMC_GPIO_PORT7, 10 +#define P7_11 XMC_GPIO_PORT7, 11 +#define P8_0 XMC_GPIO_PORT8, 0 +#define P8_1 XMC_GPIO_PORT8, 1 +#define P8_2 XMC_GPIO_PORT8, 2 +#define P8_3 XMC_GPIO_PORT8, 3 +#define P8_4 XMC_GPIO_PORT8, 4 +#define P8_5 XMC_GPIO_PORT8, 5 +#define P8_6 XMC_GPIO_PORT8, 6 +#define P8_7 XMC_GPIO_PORT8, 7 +#define P8_8 XMC_GPIO_PORT8, 8 +#define P8_9 XMC_GPIO_PORT8, 9 +#define P8_10 XMC_GPIO_PORT8, 10 +#define P8_11 XMC_GPIO_PORT8, 11 +#define P9_0 XMC_GPIO_PORT9, 0 +#define P9_1 XMC_GPIO_PORT9, 1 +#define P9_2 XMC_GPIO_PORT9, 2 +#define P9_3 XMC_GPIO_PORT9, 3 +#define P9_4 XMC_GPIO_PORT9, 4 +#define P9_5 XMC_GPIO_PORT9, 5 +#define P9_6 XMC_GPIO_PORT9, 6 +#define P9_7 XMC_GPIO_PORT9, 7 +#define P9_8 XMC_GPIO_PORT9, 8 +#define P9_9 XMC_GPIO_PORT9, 9 +#define P9_10 XMC_GPIO_PORT9, 10 +#define P9_11 XMC_GPIO_PORT9, 11 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_8_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_11_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_2_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_4_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_6_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_7_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_8_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_10_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_11_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_4_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_5_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_6_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_8_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P9_0_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_1_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_2_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_3_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_7_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_10_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_11_AF_U2C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P7_0_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_1_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_2_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_3_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_8_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_0_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_1_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_3_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_8_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_11_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P7_0 XMC_GPIO_PORT7, 0 +#define P7_1 XMC_GPIO_PORT7, 1 +#define P7_2 XMC_GPIO_PORT7, 2 +#define P7_3 XMC_GPIO_PORT7, 3 +#define P7_4 XMC_GPIO_PORT7, 4 +#define P7_5 XMC_GPIO_PORT7, 5 +#define P7_6 XMC_GPIO_PORT7, 6 +#define P7_7 XMC_GPIO_PORT7, 7 +#define P7_8 XMC_GPIO_PORT7, 8 +#define P7_9 XMC_GPIO_PORT7, 9 +#define P7_10 XMC_GPIO_PORT7, 10 +#define P7_11 XMC_GPIO_PORT7, 11 +#define P8_0 XMC_GPIO_PORT8, 0 +#define P8_1 XMC_GPIO_PORT8, 1 +#define P8_2 XMC_GPIO_PORT8, 2 +#define P8_3 XMC_GPIO_PORT8, 3 +#define P8_4 XMC_GPIO_PORT8, 4 +#define P8_5 XMC_GPIO_PORT8, 5 +#define P8_6 XMC_GPIO_PORT8, 6 +#define P8_7 XMC_GPIO_PORT8, 7 +#define P8_8 XMC_GPIO_PORT8, 8 +#define P8_9 XMC_GPIO_PORT8, 9 +#define P8_10 XMC_GPIO_PORT8, 10 +#define P8_11 XMC_GPIO_PORT8, 11 +#define P9_0 XMC_GPIO_PORT9, 0 +#define P9_1 XMC_GPIO_PORT9, 1 +#define P9_2 XMC_GPIO_PORT9, 2 +#define P9_3 XMC_GPIO_PORT9, 3 +#define P9_4 XMC_GPIO_PORT9, 4 +#define P9_5 XMC_GPIO_PORT9, 5 +#define P9_6 XMC_GPIO_PORT9, 6 +#define P9_7 XMC_GPIO_PORT9, 7 +#define P9_8 XMC_GPIO_PORT9, 8 +#define P9_9 XMC_GPIO_PORT9, 9 +#define P9_10 XMC_GPIO_PORT9, 10 +#define P9_11 XMC_GPIO_PORT9, 11 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_11_AF_ECAT0_LED_STATE_RUN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_10_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_10_AF_ECAT0_SYNC1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_0_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_1_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_8_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_11_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_5_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_6_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_0_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_1_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_2_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_2_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_3_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_4_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_6_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_7_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_8_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_8_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_10_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_11_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_0_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P8_1_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P8_2_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P8_3_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P8_4_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_5_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_6_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_8_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P8_9_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P9_0_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_0_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_1_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_1_AF_ECAT0_SYNC1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_2_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_2_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_3_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_3_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_4_AF_ECAT0_LED_STATE_RUN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P9_4_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_5_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_6_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_7_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_8_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_9_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_10_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_11_AF_U2C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_2_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P7_0_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_1_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_2_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_3_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_8_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_0_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_1_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_3_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P9_7_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_11_AF_ECAT0_LED_STATE_RUN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_10_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_10_AF_ECAT0_SYNC1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_0_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_1_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_11_AF_ECAT0_LED_STATE_RUN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_10_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_10_AF_ECAT0_SYNC1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_0_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_1_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_8_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_11_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_5_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_6_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_2_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#endif + +#endif /* XMC4_GPIO_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_rtc.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_rtc.h new file mode 100644 index 00000000..dd5f223a --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_rtc.h @@ -0,0 +1,142 @@ +/** + * @file xmc4_rtc.h + * @date 2015-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial + * + * 2015-05-20: + * - Documentation updates
+ * + * @endcond + * + */ + +#ifndef XMC4_RTC_H +#define XMC4_RTC_H + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup RTC + * @{ + */ + +/********************************************************************************************************************* + * ENUMS + *********************************************************************************************************************/ + +/** + * Wakeup events for RTC from hibernate domain + */ +typedef enum XMC_RTC_WAKEUP_EVENT +{ + XMC_RTC_WAKEUP_EVENT_ON_ALARM = RTC_CTR_TAE_Msk, /**< Wakeup from alarm event */ + XMC_RTC_WAKEUP_EVENT_ON_SECONDS = RTC_CTR_ESEC_Msk, /**< Wakeup from seconds event */ + XMC_RTC_WAKEUP_EVENT_ON_MINUTES = RTC_CTR_EMIC_Msk, /**< Wakeup from minutes event */ + XMC_RTC_WAKEUP_EVENT_ON_HOURS = RTC_CTR_EHOC_Msk, /**< Wakeup from hours event */ + XMC_RTC_WAKEUP_EVENT_ON_DAYS = RTC_CTR_EDAC_Msk, /**< Wakeup from days event */ + XMC_RTC_WAKEUP_EVENT_ON_MONTHS = RTC_CTR_EMOC_Msk, /**< Wakeup from months event */ + XMC_RTC_WAKEUP_EVENT_ON_YEARS = RTC_CTR_EYEC_Msk /**< Wakeup from years event */ +} XMC_RTC_WAKEUP_EVENT_t; + +/********************************************************************************************************************* + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param event A valid RTC Wakeup event (::XMC_RTC_WAKEUP_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Enable Wakeup from hibernate mode
+ * + * \par + * The function sets the bitfields of CTR register to enable wakeup from hibernate mode. + * Setting the masking value for the RTC wakeup events containing in the ::XMC_RTC_WAKEUP_EVENT_t + * leads to a wakeup from hibernate mode. + * + * \parRelated APIs:
+ * XMC_RTC_DisableHibernationWakeUp() + */ +__STATIC_INLINE void XMC_RTC_EnableHibernationWakeUp(const uint32_t event) +{ + RTC->CTR |= event; +} + +/** + * @param event A valid RTC Wakeup event (::XMC_RTC_WAKEUP_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Disable Wakeup from hibernate mode
+ * + * \par + * The function resets the bitfields of CTR register to disable wakeup from hibernate mode. + * Resetting the masking value for the RTC wakeup events containing in the ::XMC_RTC_WAKEUP_EVENT_t + * disables wakeup from hibernate mode. + * + * \parRelated APIs:
+ * XMC_RTC_EnableHibernationWakeUp() + */ +__STATIC_INLINE void XMC_RTC_DisableHibernationWakeUp(const uint32_t event) +{ + RTC->CTR &= ~event; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XMC4_RTC_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_scu.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_scu.h new file mode 100644 index 00000000..8ddaf6b0 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_scu.h @@ -0,0 +1,3418 @@ +/** + * @file xmc4_scu.h + * @date 2016-06-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial version + * - Documentation improved + * + * 2015-11-30: + * - Documentation improved + * + * 2016-03-09: + * - Added XMC_SCU_POWER_EnableMonitor/XMC_SCU_POWER_DisableMonitor + * XMC_SCU_POWER_GetEVRStatus, XMC_SCU_POWER_GetEVR13Voltage, XMC_SCU_POWER_GetEVR33Voltage + * - Added XMC_SCU_HIB_GetHibernateControlStatus, + * XMC_SCU_HIB_GetEventStatus, XMC_SCU_HIB_ClearEventStatus, XMC_SCU_HIB_TriggerEvent, + * XMC_SCU_HIB_EnableEvent, XMC_SCU_HIB_DisableEvent + * - Added XMC_SCU_HIB_SetWakeupTriggerInput, XMC_SCU_HIB_SetPinMode, XMC_SCU_HIB_SetOutputPinLevel, + * XMC_SCU_HIB_SetInput0, XMC_SCU_HIB_EnterHibernateState + * + * 2016-04-15: + * - Fixed naming of XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG peripheral clock. + * Added enable and disable for peripheral clocks + * + * 2016-05-19: + * - Added XMC_SCU_CLOCK_IsLowPowerOscillatorStable() and XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() + * - Added XMC_SCU_POWER_WaitForInterrupt() and XMC_SCU_POWER_WaitForEvent() + * - Added XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus() + * - Added XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus() + * - Removed XMC_SCU_INTERRUPT_EVENT_OSCULSTAT_UPDATED, XMC_SCU_INTERRUPT_EVENT_HDSTAT_UPDATED + * + * 2016-06-14: + * - Added XMC_SCU_HIB_IsWakeupEventDetected() and XMC_SCU_HIB_ClearWakeupEventDetectionStatus() + * + * 2016-06-15: + * - Added XMC_SCU_HIB_EnterHibernateStateEx() which allows to select between external or internal hibernate mode. This last mode only available in XMC44, XMC42 and XMC41 series. + * - Extended wakeup hibernate events using LPAC wakeup on events. Only available in XMC44, XMC42 and XMC41 series. + * - Added LPAC APIs. Only available in XMC44, XMC42 and XMC41 series. + * + * @endcond + * + */ + +#ifndef XMC4_SCU_H +#define XMC4_SCU_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_common.h" + +#if UC_FAMILY == XMC4 + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup SCU + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define PLL_PDIV_XTAL_8MHZ (1U) /* PDIV value for main PLL settings, fPLL = 120MHz with fOSC = 8MHz */ +#define PLL_NDIV_XTAL_8MHZ (89U) /* NDIV value for main PLL settings, fPLL = 120MHz with fOSC = 8MHz */ +#define PLL_K2DIV_XTAL_8MHZ (2U) /* K2DIV value for main PLL settings, fPLL = 120MHz with fOSC = 8MHz */ + +#define PLL_PDIV_XTAL_12MHZ (1U) /* PDIV value for main PLL settings, fPLL = 120MHz with fOSC = 12MHz */ +#define PLL_NDIV_XTAL_12MHZ (79U) /* NDIV value for main PLL settings, fPLL = 120MHz with fOSC = 12MHz */ +#define PLL_K2DIV_XTAL_12MHZ (3U) /* K2DIV value for main PLL settings, fPLL = 120MHz with fOSC = 12MHz */ + +#define PLL_PDIV_XTAL_16MHZ (1U) /* PDIV value for main PLL settings, fPLL = 120MHz with fOSC = 16MHz */ +#define PLL_NDIV_XTAL_16MHZ (59U) /* NDIV value for main PLL settings, fPLL = 120MHz with fOSC = 16MHz */ +#define PLL_K2DIV_XTAL_16MHZ (3U) /* K2DIV value for main PLL settings, fPLL = 120MHz with fOSC = 16MHz */ + +#define XMC_SCU_INTERRUPT_EVENT_WDT_WARN SCU_INTERRUPT_SRSTAT_PRWARN_Msk /**< Watchdog prewarning event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC SCU_INTERRUPT_SRSTAT_PI_Msk /**< RTC periodic interrupt. */ +#define XMC_SCU_INTERRUPT_EVENT_RTC_ALARM SCU_INTERRUPT_SRSTAT_AI_Msk /**< RTC alarm event. */ +#define XMC_SCU_INTERRUPT_EVENT_DLR_OVERRUN SCU_INTERRUPT_SRSTAT_DLROVR_Msk /**< DLR overrun event. */ +#if defined(SCU_INTERRUPT_SRSTAT_LPACCR_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACCR_UPDATED SCU_INTERRUPT_SRSTAT_LPACCR_Msk /**< LPAC Control register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_LPACTH0_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACTH0_UPDATED SCU_INTERRUPT_SRSTAT_LPACTH0_Msk /**< LPAC Threshold-0 register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_LPACTH1_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACTH1_UPDATED SCU_INTERRUPT_SRSTAT_LPACTH1_Msk /**< LPAC Threshold-1 register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_LPACST_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACST_UPDATED SCU_INTERRUPT_SRSTAT_LPACST_Msk /**< LPAC Status register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_LPACCLR_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACCLR_UPDATED SCU_INTERRUPT_SRSTAT_LPACCLR_Msk /**< LPAC event clear register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_LPACSET_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACSET_UPDATED SCU_INTERRUPT_SRSTAT_LPACSET_Msk /**< LPAC event set register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_HINTST_Msk) +#define XMC_SCU_INTERRUPT_EVENT_HINTST_UPDATED SCU_INTERRUPT_SRSTAT_HINTST_Msk /**< HIB HINTST register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_HINTCLR_Msk) +#define XMC_SCU_INTERRUPT_EVENT_HINTCLR_UPDATED SCU_INTERRUPT_SRSTAT_HINTCLR_Msk /**< HIB HINTCLR register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_HINTSET_Msk) +#define XMC_SCU_INTERRUPT_EVENT_HINTSET_UPDATED SCU_INTERRUPT_SRSTAT_HINTSET_Msk /**< HIB HINTSET register update event. */ +#endif +#define XMC_SCU_INTERRUPT_EVENT_HDCLR_UPDATED SCU_INTERRUPT_SRSTAT_HDCLR_Msk /**< HIB HDCLR register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_HDSET_UPDATED SCU_INTERRUPT_SRSTAT_HDSET_Msk /**< HIB HDSET register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_HDCR_UPDATED SCU_INTERRUPT_SRSTAT_HDCR_Msk /**< HIB HDCR register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_OSCSICTRL_UPDATED SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk /**< HIB OSCSICTRL register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_OSCULCTRL_UPDATED SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk /**< HIB OSCULCTRL register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk /**< HIB RTCCTR register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk /**< HIB RTCATIM0 register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk /**< HIB RTCATIM1 register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk /**< HIB TIM0 register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk /**< HIB TIM1 register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RMX_UPDATED SCU_INTERRUPT_SRSTAT_RMX_Msk /**< HIB RMX register update event. */ + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +/** + * Defines Capture/Compare unit timer slice trigger, that enables synchronous start function available on the \a SCU, + * CCUCON register. Use type \a XMC_SCU_CCU_TRIGGER_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CCU_TRIGGER +{ +#if defined(CCU40) + XMC_SCU_CCU_TRIGGER_CCU40 = SCU_GENERAL_CCUCON_GSC40_Msk, /**< Trigger mask used for Global Start Control of + CCU40 peripheral. */ +#endif +#if defined(CCU41) + XMC_SCU_CCU_TRIGGER_CCU41 = SCU_GENERAL_CCUCON_GSC41_Msk, /**< Trigger mask used for Global Start Control of + CCU41 peripheral. */ +#endif +#if defined(CCU42) + XMC_SCU_CCU_TRIGGER_CCU42 = SCU_GENERAL_CCUCON_GSC42_Msk, /**< Trigger mask used for Global Start Control of + CCU42 peripheral. */ +#endif +#if defined(CCU43) + XMC_SCU_CCU_TRIGGER_CCU43 = SCU_GENERAL_CCUCON_GSC43_Msk, /**< Trigger mask used for Global Start Control of + CCU43 peripheral. */ +#endif +#if defined(CCU80) + XMC_SCU_CCU_TRIGGER_CCU80 = SCU_GENERAL_CCUCON_GSC80_Msk, /**< Trigger mask used for Global Start Control of + CCU80 peripheral. */ +#endif +#if defined(CCU81) + XMC_SCU_CCU_TRIGGER_CCU81 = SCU_GENERAL_CCUCON_GSC81_Msk /**< Trigger mask used for Global Start Control of + CCU81 peripheral. */ +#endif +} XMC_SCU_CCU_TRIGGER_t; + +/** + * Defines enumerations representing the status of trap cause. The cause of the trap gets automatically stored in + * the \a TRAPSTAT register and can be checked by user software to determine the state of the system and for debug + * purpose. + * Use type \a XMC_SCU_TRAP_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_TRAP +{ + XMC_SCU_TRAP_OSC_WDG = SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk, /**< OSC_HP Oscillator Watchdog trap. */ + XMC_SCU_TRAP_VCO_LOCK = SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk, /**< PLL loss of lock trap. */ + XMC_SCU_TRAP_USB_VCO_LOCK = SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk, /**< USB PLL loss of lock trap. */ + XMC_SCU_TRAP_PARITY_ERROR = SCU_TRAP_TRAPSTAT_PET_Msk, /**< Memory Parity error trap. */ + XMC_SCU_TRAP_BROWNOUT = SCU_TRAP_TRAPSTAT_BRWNT_Msk, /**< Brownout trap. */ + XMC_SCU_TRAP_ULP_WDG = SCU_TRAP_TRAPSTAT_ULPWDGT_Msk, /**< Unstable 32KHz clock trap. */ + XMC_SCU_TRAP_PER_BRIDGE0 = SCU_TRAP_TRAPSTAT_BWERR0T_Msk, /**< Bad memory access of peripherals on Bridge-0. */ + XMC_SCU_TRAP_PER_BRIDGE1 = SCU_TRAP_TRAPSTAT_BWERR1T_Msk, /**< Bad memory access of peripherals on Bridge-1. */ +#if defined(SCU_TRAP_TRAPSTAT_TEMPHIT_Msk) + XMC_SCU_TRAP_DIETEMP_HIGH = SCU_TRAP_TRAPSTAT_TEMPHIT_Msk, /**< Die temperature higher than expected. */ +#endif +#if defined(SCU_TRAP_TRAPSTAT_TEMPLOT_Msk) + XMC_SCU_TRAP_DIETEMP_LOW = SCU_TRAP_TRAPSTAT_TEMPLOT_Msk, /**< Die temperature lower than expected. */ +#endif +#if defined(ECAT0) + XMC_SCU_TRAP_ECAT_RESET = SCU_TRAP_TRAPSTAT_ECAT0RST_Msk, /**< EtherCat Reset */ +#endif +} XMC_SCU_TRAP_t; + +/** + * Defines enumerations for different parity event generating modules that in turn generate a trap. + * Parity can be enabled with \a PETE register in order to get the trap flag reflected in \a TRAPRAW register. These enums are used to + * configure parity error trap generation mechanism bits of \a PETE register. + * All the enum items are tabulated as per bits present in \a PETE register. + * Use type \a XMC_SCU_PARITY_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_PARITY +{ + XMC_SCU_PARITY_PSRAM_MEM = SCU_PARITY_PEEN_PEENPS_Msk, /**< Program SRAM parity error trap. */ + XMC_SCU_PARITY_DSRAM1_MEM = SCU_PARITY_PEEN_PEENDS1_Msk, /**< Data SRAM-1 parity error trap. */ +#if defined(XMC_SCU_PARITY_DSRAM2_MEM) + XMC_SCU_PARITY_DSRAM2_MEM = SCU_PARITY_PEEN_PEENDS2_Msk, /**< Data SRAM-2 parity error trap. */ +#endif + XMC_SCU_PARITY_USIC0_MEM = SCU_PARITY_PEEN_PEENU0_Msk, /**< USIC0 memory parity error trap. */ +#if defined(XMC_SCU_PARITY_USIC1_MEM) + XMC_SCU_PARITY_USIC1_MEM = SCU_PARITY_PEEN_PEENU1_Msk, /**< USIC1 memory parity error trap. */ +#endif +#if defined(XMC_SCU_PARITY_USIC2_MEM) + XMC_SCU_PARITY_USIC2_MEM = SCU_PARITY_PEEN_PEENU2_Msk, /**< USIC2 memory parity error trap. */ +#endif + XMC_SCU_PARITY_MCAN_MEM = SCU_PARITY_PEEN_PEENMC_Msk, /**< CAN memory parity error trap. */ + XMC_SCU_PARITY_PMU_MEM = SCU_PARITY_PEEN_PEENPPRF_Msk, /**< PMU Prefetch memory parity error trap. */ + XMC_SCU_PARITY_USB_MEM = SCU_PARITY_PEEN_PEENUSB_Msk, /**< USB memory parity error trap. */ +#if defined(SCU_PARITY_PEEN_PEENETH0TX_Msk) + XMC_SCU_PARITY_ETH_TXMEM = SCU_PARITY_PEEN_PEENETH0TX_Msk, /**< Ethernet transmit memory parity error trap. */ +#endif +#if defined(SCU_PARITY_PEEN_PEENETH0RX_Msk) + XMC_SCU_PARITY_ETH_RXMEM = SCU_PARITY_PEEN_PEENETH0RX_Msk, /**< Ethernet receive memory parity error trap. */ +#endif +#if defined(SCU_PARITY_PEEN_PEENSD0_Msk) + XMC_SCU_PARITY_SDMMC_MEM0 = SCU_PARITY_PEEN_PEENSD0_Msk, /**< SDMMC Memory-0 parity error trap. */ +#endif +#if defined(SCU_PARITY_PEEN_PEENSD1_Msk) + XMC_SCU_PARITY_SDMMC_MEM1 = SCU_PARITY_PEEN_PEENSD1_Msk, /**< SDMMC Memory-1 parity error trap. */ +#endif +} XMC_SCU_PARITY_t; + +/** + * Defines the different causes for last reset. The cause of the last reset gets automatically stored in + * the \a SCU_RSTSTAT register and can be checked by user software to determine the state of the system and for debuggging + * purpose. All the enum items are tabulated as per bits present in \a SCU_RSTSTAT register. + * Use type \a XMC_SCU_RESET_REASON_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_RESET_REASON +{ + XMC_SCU_RESET_REASON_PORST = (1UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Power on reset. */ + XMC_SCU_RESET_REASON_SWD = (2UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Supply Watchdog reset. */ + XMC_SCU_RESET_REASON_PV = (4UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Power Validation reset. */ + XMC_SCU_RESET_REASON_SW = (8UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Software reset. */ + XMC_SCU_RESET_REASON_LOCKUP = (16UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to reset due to CPU lockup. */ + XMC_SCU_RESET_REASON_WATCHDOG = (32UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Watchdog timer initiated reset. */ + XMC_SCU_RESET_REASON_PARITY_ERROR = (128UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to reset due to memory parity error. */ +} XMC_SCU_RESET_REASON_t; + +/** + * Defines enumerations for events which can lead to interrupt. These enumeration values represent the + * status of one of the bits in \a SRSTAT register. + * Use type \a XMC_SCU_INTERRUPT_EVENT_t for accessing these enum parameters. + */ +typedef uint32_t XMC_SCU_INTERRUPT_EVENT_t; + + +/** + * Defines enumeration for the events that can generate non maskable interrupt(NMI). + * The NMI generation can be enabled with \a NMIREQEN register. The event will be reflected in \a SRSTAT or will be + * mirrored in the TRAPSTAT register. These enums can be used to configure NMI request generation bits of \a + * NMIREQEN register. Once configured, these events can generate non maskable interrupt. + * All the enum items are tabulated as per bits present in \a NMIREQEN register. + * Use type \a XMC_SCU_NMIREQ_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_NMIREQ +{ + XMC_SCU_NMIREQ_WDT_WARN = SCU_INTERRUPT_NMIREQEN_PRWARN_Msk, /**< Watchdog timer Pre-Warning event */ + XMC_SCU_NMIREQ_RTC_PI = SCU_INTERRUPT_NMIREQEN_PI_Msk, /**< RTC Periodic event */ + XMC_SCU_NMIREQ_RTC_AI = SCU_INTERRUPT_NMIREQEN_AI_Msk, /**< RTC Alarm event */ + XMC_SCU_NMIREQ_ERU0_0 = SCU_INTERRUPT_NMIREQEN_ERU00_Msk, /**< Channel 0 event of ERU0 */ + XMC_SCU_NMIREQ_ERU0_1 = SCU_INTERRUPT_NMIREQEN_ERU01_Msk, /**< Channel 1 event of ERU0 */ + XMC_SCU_NMIREQ_ERU0_2 = SCU_INTERRUPT_NMIREQEN_ERU02_Msk, /**< Channel 2 event of ERU0 */ + XMC_SCU_NMIREQ_ERU0_3 = SCU_INTERRUPT_NMIREQEN_ERU03_Msk /**< Channel 3 event of ERU0 */ +} XMC_SCU_NMIREQ_t; + + +/** + * Defines enumeration representing different peripheral reset bits in the \a PRSTAT registers. + * All the enum items are tabulated as per bits present in \a PRSTAT0, \a PRSTAT1, \a PRSTAT2, + * \a PRSTAT3 registers. Use type \a XMC_SCU_PERIPHERAL_RESET_t for accessing these enum parameters. + * Note: Release of reset should be prevented when the peripheral clock is gated in cases where kernel + * clock and bus interface clocks are shared, in order to avoid system hang-up. + */ +typedef enum XMC_SCU_PERIPHERAL_RESET +{ + XMC_SCU_PERIPHERAL_RESET_VADC = SCU_RESET_PRSTAT0_VADCRS_Msk, /**< VADC reset. */ +#if defined(DSD) + XMC_SCU_PERIPHERAL_RESET_DSD = SCU_RESET_PRSTAT0_DSDRS_Msk, /**< DSD reset. */ +#endif + XMC_SCU_PERIPHERAL_RESET_CCU40 = SCU_RESET_PRSTAT0_CCU40RS_Msk, /**< CCU40 reset. */ +#if defined(CCU41) + XMC_SCU_PERIPHERAL_RESET_CCU41 = SCU_RESET_PRSTAT0_CCU41RS_Msk, /**< CCU41 reset. */ +#endif +#if defined(CCU42) + XMC_SCU_PERIPHERAL_RESET_CCU42 = SCU_RESET_PRSTAT0_CCU42RS_Msk, /**< CCU42 reset. */ +#endif +#if defined(CCU80) + XMC_SCU_PERIPHERAL_RESET_CCU80 = SCU_RESET_PRSTAT0_CCU80RS_Msk, /**< CCU80 reset. */ +#endif +#if defined(CCU81) + XMC_SCU_PERIPHERAL_RESET_CCU81 = SCU_RESET_PRSTAT0_CCU81RS_Msk, /**< CCU81 reset. */ +#endif +#if defined(POSIF0) + XMC_SCU_PERIPHERAL_RESET_POSIF0 = SCU_RESET_PRSTAT0_POSIF0RS_Msk, /**< POSIF0 reset. */ +#endif +#if defined(POSIF1) + XMC_SCU_PERIPHERAL_RESET_POSIF1 = SCU_RESET_PRSTAT0_POSIF1RS_Msk, /**< POSIF1 reset.*/ +#endif + XMC_SCU_PERIPHERAL_RESET_USIC0 = SCU_RESET_PRSTAT0_USIC0RS_Msk, /**< USIC0 reset. */ + XMC_SCU_PERIPHERAL_RESET_ERU1 = SCU_RESET_PRSTAT0_ERU1RS_Msk, /**< ERU1 reset. */ +#if defined(HRPWM0) + XMC_SCU_PERIPHERAL_RESET_HRPWM0 = SCU_RESET_PRSTAT0_HRPWM0RS_Msk, /**< HRPWM0 reset. */ +#endif +#if defined(CCU43) + XMC_SCU_PERIPHERAL_RESET_CCU43 = (SCU_RESET_PRSTAT1_CCU43RS_Msk | 0x10000000UL), /**< CCU43 reset. */ +#endif +#if defined(LEDTS0) + XMC_SCU_PERIPHERAL_RESET_LEDTS0 = (SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk | 0x10000000UL), /**< LEDTS0 reset. */ +#endif +#if defined(CAN) + XMC_SCU_PERIPHERAL_RESET_MCAN = (SCU_RESET_PRSTAT1_MCAN0RS_Msk | 0x10000000UL), /**< MCAN reset. */ +#endif +#if defined(DAC) + XMC_SCU_PERIPHERAL_RESET_DAC = (SCU_RESET_PRSTAT1_DACRS_Msk | 0x10000000UL), /**< DAC reset. */ +#endif +#if defined(SDMMC) + XMC_SCU_PERIPHERAL_RESET_SDMMC = (SCU_RESET_PRSTAT1_MMCIRS_Msk | 0x10000000UL), /**< SDMMC reset. */ +#endif +#if defined(USIC1) + XMC_SCU_PERIPHERAL_RESET_USIC1 = (SCU_RESET_PRSTAT1_USIC1RS_Msk | 0x10000000UL), /**< USIC1 reset. */ +#endif +#if defined(USIC2) + XMC_SCU_PERIPHERAL_RESET_USIC2 = (SCU_RESET_PRSTAT1_USIC2RS_Msk | 0x10000000UL), /**< USIC2 reset. */ +#endif + XMC_SCU_PERIPHERAL_RESET_PORTS = (SCU_RESET_PRSTAT1_PPORTSRS_Msk | 0x10000000UL), /**< PORTS reset. */ + XMC_SCU_PERIPHERAL_RESET_WDT = (SCU_RESET_PRSTAT2_WDTRS_Msk | 0x20000000UL), /**< WDT reset. */ +#if defined(ETH0) + XMC_SCU_PERIPHERAL_RESET_ETH0 = (SCU_RESET_PRSTAT2_ETH0RS_Msk | 0x20000000UL), /**< ETH0 reset. */ +#endif + XMC_SCU_PERIPHERAL_RESET_GPDMA0 = (SCU_RESET_PRSTAT2_DMA0RS_Msk | 0x20000000UL), /**< DMA0 reset. */ +#if defined(GPDMA1) + XMC_SCU_PERIPHERAL_RESET_GPDMA1 = (SCU_RESET_PRSTAT2_DMA1RS_Msk | 0x20000000UL), /**< DMA1 reset. */ +#endif +#if defined(FCE) + XMC_SCU_PERIPHERAL_RESET_FCE = (SCU_RESET_PRSTAT2_FCERS_Msk | 0x20000000UL), /**< FCE reset. */ +#endif +#if defined(USB0) + XMC_SCU_PERIPHERAL_RESET_USB0 = (SCU_RESET_PRSTAT2_USBRS_Msk | 0x20000000UL), /**< USB0 reset. */ +#endif +#if defined(ECAT0) + XMC_SCU_PERIPHERAL_RESET_ECAT0 = (SCU_RESET_PRSTAT2_ECAT0RS_Msk | 0x20000000UL), /**< ECAT0 reset. */ +#endif +#if defined(EBU) + XMC_SCU_PERIPHERAL_RESET_EBU = (SCU_RESET_PRSTAT3_EBURS_Msk | 0x30000000UL) /**< EBU reset. */ +#endif +} XMC_SCU_PERIPHERAL_RESET_t; + +/** + * Defines enumerations for disabling the clocks sources of peripherals. Disabling of the peripheral + * clock is configured via the \a CLKCLR registers. + * Use type \a XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK +{ + XMC_SCU_CLOCK_USB = SCU_CLK_CLKCLR_USBCDI_Msk, /**< USB module clock. */ +#if defined(SDMMC) + XMC_SCU_CLOCK_MMC = SCU_CLK_CLKCLR_MMCCDI_Msk, /**< MMC module clock. */ +#endif +#if defined(ETH0) + XMC_SCU_CLOCK_ETH = SCU_CLK_CLKCLR_ETH0CDI_Msk, /**< Ethernet module clock. */ +#endif +#if defined(EBU) + XMC_SCU_CLOCK_EBU = SCU_CLK_CLKCLR_EBUCDI_Msk, /**< EBU module clock. */ +#endif + XMC_SCU_CLOCK_CCU = SCU_CLK_CLKCLR_CCUCDI_Msk, /**< CCU module clock. */ + XMC_SCU_CLOCK_WDT = SCU_CLK_CLKCLR_WDTCDI_Msk /**< WDT module clock. */ +} XMC_SCU_CLOCK_t; + +#if(UC_SERIES != XMC45) +/** + * Defines enumeration for peripherals that support clock gating. + * The enumerations can be used for gating or ungating the peripheral clocks. + * All the enum items are tabulated as per bits present in \a CGATSTAT0 register. + * Use type \a XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_PERIPHERAL_CLOCK +{ + XMC_SCU_PERIPHERAL_CLOCK_VADC = SCU_CLK_CGATSTAT0_VADC_Msk, /**< VADC peripheral gating. */ +#if defined(DSD) + XMC_SCU_PERIPHERAL_CLOCK_DSD = SCU_CLK_CGATSTAT0_DSD_Msk, /**< DSD peripheral gating. */ +#endif + XMC_SCU_PERIPHERAL_CLOCK_CCU40 = SCU_CLK_CGATSTAT0_CCU40_Msk, /**< CCU40 peripheral gating. */ +#if defined(CCU41) + XMC_SCU_PERIPHERAL_CLOCK_CCU41 = SCU_CLK_CGATSTAT0_CCU41_Msk, /**< CCU41 peripheral gating. */ +#endif +#if defined(CCU42) + XMC_SCU_PERIPHERAL_CLOCK_CCU42 = SCU_CLK_CGATSTAT0_CCU42_Msk, /**< CCU42 peripheral gating. */ +#endif +#if defined(CCU80) + XMC_SCU_PERIPHERAL_CLOCK_CCU80 = SCU_CLK_CGATSTAT0_CCU80_Msk, /**< CCU80 peripheral gating. */ +#endif +#if defined(CCU81) + XMC_SCU_PERIPHERAL_CLOCK_CCU81 = SCU_CLK_CGATSTAT0_CCU81_Msk, /**< CCU81 peripheral gating. */ +#endif +#if defined(POSIF0) + XMC_SCU_PERIPHERAL_CLOCK_POSIF0 = SCU_CLK_CGATSTAT0_POSIF0_Msk, /**< POSIF0 peripheral gating. */ +#endif +#if defined(POSIF1) + XMC_SCU_PERIPHERAL_CLOCK_POSIF1 = SCU_CLK_CGATSTAT0_POSIF1_Msk, /**< POSIF1 peripheral gating. */ +#endif + XMC_SCU_PERIPHERAL_CLOCK_USIC0 = SCU_CLK_CGATSTAT0_USIC0_Msk, /**< USIC0 peripheral gating. */ + XMC_SCU_PERIPHERAL_CLOCK_ERU1 = SCU_CLK_CGATSTAT0_ERU1_Msk, /**< ERU1 peripheral gating. */ +#if defined(HRPWM0) + XMC_SCU_PERIPHERAL_CLOCK_HRPWM0 = SCU_CLK_CGATSTAT0_HRPWM0_Msk, /**< HRPWM0 peripheral gating. */ +#endif +#if defined(CCU43) + XMC_SCU_PERIPHERAL_CLOCK_CCU43 = (SCU_CLK_CGATSTAT1_CCU43_Msk | 0x10000000UL), /**< CCU43 peripheral gating. */ +#endif +#if defined(LEDTS0) + XMC_SCU_PERIPHERAL_CLOCK_LEDTS0 = (SCU_CLK_CGATSTAT1_LEDTSCU0_Msk | 0x10000000UL), /**< LEDTS0 peripheral gating. */ +#endif +#if defined(CAN) + XMC_SCU_PERIPHERAL_CLOCK_MCAN = (SCU_CLK_CGATSTAT1_MCAN0_Msk | 0x10000000UL), /**< MCAN peripheral gating. */ +#endif +#if defined(DAC) + XMC_SCU_PERIPHERAL_CLOCK_DAC = (SCU_CLK_CGATSTAT1_DAC_Msk | 0x10000000UL), /**< DAC peripheral gating. */ +#endif +#if defined(SDMMC) + XMC_SCU_PERIPHERAL_CLOCK_SDMMC = (SCU_CLK_CGATSTAT1_MMCI_Msk | 0x10000000UL), /**< SDMMC peripheral gating. */ +#endif +#if defined(USIC1) + XMC_SCU_PERIPHERAL_CLOCK_USIC1 = (SCU_CLK_CGATSTAT1_USIC1_Msk | 0x10000000UL), /**< USIC1 peripheral gating. */ +#endif +#if defined(USIC2) + XMC_SCU_PERIPHERAL_CLOCK_USIC2 = (SCU_CLK_CGATSTAT1_USIC2_Msk | 0x10000000UL), /**< USIC2 peripheral gating. */ +#endif + XMC_SCU_PERIPHERAL_CLOCK_PORTS = (SCU_CLK_CGATSTAT1_PPORTS_Msk | 0x10000000UL), /**< PORTS peripheral gating. */ + XMC_SCU_PERIPHERAL_CLOCK_WDT = (SCU_CLK_CGATSTAT2_WDT_Msk | 0x20000000UL), /**< WDT peripheral gating. */ +#if defined(ETH0) + XMC_SCU_PERIPHERAL_CLOCK_ETH0 = (SCU_CLK_CGATSTAT2_ETH0_Msk | 0x20000000UL), /**< ETH0 peripheral gating. */ +#endif + XMC_SCU_PERIPHERAL_CLOCK_GPDMA0 = (SCU_CLK_CGATSTAT2_DMA0_Msk | 0x20000000UL), /**< DMA0 peripheral gating. */ +#if defined(GPDMA1) + XMC_SCU_PERIPHERAL_CLOCK_GPDMA1 = (SCU_CLK_CGATSTAT2_DMA1_Msk | 0x20000000UL), /**< DMA1 peripheral gating. */ +#endif +#if defined(FCE) + XMC_SCU_PERIPHERAL_CLOCK_FCE = (SCU_CLK_CGATSTAT2_FCE_Msk | 0x20000000UL), /**< FCE peripheral gating. */ +#endif +#if defined(USB0) + XMC_SCU_PERIPHERAL_CLOCK_USB0 = (SCU_CLK_CGATSTAT2_USB_Msk | 0x20000000UL), /**< USB0 peripheral gating. */ +#endif +#if defined(ECAT0) + XMC_SCU_PERIPHERAL_CLOCK_ECAT0 = (SCU_CLK_CGATSTAT2_ECAT0_Msk | 0x20000000UL), /**< ECAT0 peripheral gating. */ +#endif +#if defined(EBU) + XMC_SCU_PERIPHERAL_CLOCK_EBU = (SCU_CLK_CGATSTAT3_EBU_Msk | 0x30000000UL) /**< EBU peripheral gating. */ +#endif +} XMC_SCU_PERIPHERAL_CLOCK_t; +#endif + +/** + * Defines options for system clock (fSYS) source. These enums are used to configure \a SYSSEL bits of \a SYSCLKCR + * Clock Control Register. + * Use type \a XMC_SCU_CLOCK_SYSCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_SYSCLKSRC +{ + XMC_SCU_CLOCK_SYSCLKSRC_OFI = (0UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos), /**< Internal Fast Clock (fOFI) as a + source for system clock (fSYS). */ + XMC_SCU_CLOCK_SYSCLKSRC_PLL = (1UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos) /**< PLL output (fPLL) as a + source for system clock (fSYS). */ +} XMC_SCU_CLOCK_SYSCLKSRC_t; + +/** + * Defines options for selecting the P-Divider input frequency. These enums are used to configure \a PINSEL bits of \a PLLCON2 + * register. + * Use type \a XMC_SCU_CLOCK_OSCCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_SYSPLLCLKSRC +{ + XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP = 0UL, /**< External crystal oscillator + (fOHP) as the source for P-Divider. */ + XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI = SCU_PLL_PLLCON2_PINSEL_Msk | SCU_PLL_PLLCON2_K1INSEL_Msk /**< Backup clock(fOFI) + as the source for P-Divider. */ +} XMC_SCU_CLOCK_SYSPLLCLKSRC_t; + +/** + * Defines options for selecting the USB clock source(fUSB/fSDMMC). + * These enums are used to configure \a USBSEL bits of \a USBCLKCR + * register. User can choose either fPLL or fUSBPLL clock as a source for USB clock. + * Use type \a XMC_SCU_CLOCK_USBCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_USBCLKSRC +{ + XMC_SCU_CLOCK_USBCLKSRC_USBPLL = (0UL << SCU_CLK_USBCLKCR_USBSEL_Pos), /**< USB PLL(fUSB PLL) as a + source for USB clock (fUSB/fSDMMC). */ + XMC_SCU_CLOCK_USBCLKSRC_SYSPLL = (1UL << SCU_CLK_USBCLKCR_USBSEL_Pos) /**< Main PLL output (fPLL) as a + source for USB clock (fUSB/fSDMMC). */ +} XMC_SCU_CLOCK_USBCLKSRC_t; + +#if defined(ECAT0) +/** + * Defines options for selecting the ECAT clock source. + */ +typedef enum XMC_SCU_CLOCK_ECATCLKSRC +{ + XMC_SCU_CLOCK_ECATCLKSRC_USBPLL = (0UL << SCU_CLK_ECATCLKCR_ECATSEL_Pos), /**< USB PLL (fUSBPLL) as a source for ECAT clock. */ + XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL = (1UL << SCU_CLK_ECATCLKCR_ECATSEL_Pos) /**< Main PLL output (fPLL) as a source for ECAT clock. */ +} XMC_SCU_CLOCK_ECATCLKSRC_t; +#endif + +/** + * Defines options for selecting the source of WDT clock(fWDT). These enums are used to configure \a WDTSEL bits of \a WDTCLKCR + * register. User can choose either fOFI or fPLL or fSTDBY clock as a source for WDT clock. + * Use type \a XMC_SCU_CLOCK_USBCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_WDTCLKSRC +{ + XMC_SCU_CLOCK_WDTCLKSRC_OFI = (0UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos), /**< Internal Fast Clock + (fOFI) as the source for WDT clock (fWDT). */ + XMC_SCU_CLOCK_WDTCLKSRC_STDBY = (1UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos), /**< Standby clock + (fSTDBY) as the source for WDT clock (fWDT). */ + XMC_SCU_CLOCK_WDTCLKSRC_PLL = (2UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos) /**< PLL output (fPLL) as the + source for WDT clock (fWDT). */ +} XMC_SCU_CLOCK_WDTCLKSRC_t; + +/** + * Defines options for selecting the source of external clock out (fEXT). These enums are used to configure \a ECKSEL bits of \a EXTCLKCR + * register. User can choose either fSYS or fPLL or fUSBPLL clock as a source for external clock out (fEXT). + * Use type \a XMC_SCU_CLOCK_EXTOUTCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_EXTOUTCLKSRC +{ + XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS = (0UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< System clock (fSYS) as + the source for external clock out (fEXT). */ + XMC_SCU_CLOCK_EXTOUTCLKSRC_USB = (2UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< USB PLL output(fUSB PLL) as the + source for external clock out (fEXT). */ + XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL = (3UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< Main PLL output(fPLL) as the + source for external clock out (fEXT). */ +#if ((UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY = (4UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< Standby clock(fSTDBY) as the + source for external clock out (fEXT). */ +#endif +} XMC_SCU_CLOCK_EXTOUTCLKSRC_t; + +/** + * Defines options for selecting the source of RTC Clock (fRTC). These enums are used to configure \a RCS bit of \a HDCR register. + * User can choose either fOSI or fULP clock as a source for RTC Clock (fRTC). + * Use type \a XMC_SCU_HIB_RTCCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_HIB_RTCCLKSRC +{ + XMC_SCU_HIB_RTCCLKSRC_OSI = (0UL << SCU_HIBERNATE_HDCR_RCS_Pos), /**< Internal Slow Clock + (fOSI) as the source for RTC Clock (fRTC). */ + XMC_SCU_HIB_RTCCLKSRC_ULP = (1UL << SCU_HIBERNATE_HDCR_RCS_Pos) /**< Ultra Low Power Clock (fULP) + as the source for RTC Clock (fRTC). */ +} XMC_SCU_HIB_RTCCLKSRC_t; + +/** + * Defines options for selecting the source of Standby Clock (fSTDBY). These enums are used to configure \a STDBYSEL bit of \a HDCR + * register. User can choose either fOSI or fULP clock as a source for Standby Clock (fSTDBY). + * Use type \a XMC_SCU_HIB_STDBYCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_HIB_STDBYCLKSRC +{ + XMC_SCU_HIB_STDBYCLKSRC_OSI = (0UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos), /**< Internal Slow Clock + (fOSI) as the source for Standby Clock + (fSTDBY). */ + XMC_SCU_HIB_STDBYCLKSRC_OSCULP = (1UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos) /**< Ultra Low Power Clock + (fULP) as the source for Standby Clock + (fSTDBY). */ +} XMC_SCU_HIB_STDBYCLKSRC_t; + +/** + * Defines options for backup clock trimming. These enums are used to configure \a AOTREN \a FOTR bits of \a + * PLLCON0 register. Use type \a XMC_SCU_CLOCK_BACKUP_TRIM_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE +{ + XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY = 0UL, /**< Factory Oscillator Calibration: + Force adjustment of the internal oscillator with the firmware defined values.*/ + XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC = 1UL /**< Automatic Oscillator Calibration adjustment of the fOFI clock with fSTDBY clock. */ +} XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t; + + +/** + * Defines options for selecting device boot mode. These enums are used to configure \a SWCON bits of \a STCON register. + * User can choose among various boot modes by configuring SWCON bits. + * Use type \a XMC_SCU_BOOTMODE_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_BOOTMODE +{ + XMC_SCU_BOOTMODE_NORMAL = (0UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from start of flash. */ + XMC_SCU_BOOTMODE_ASC_BSL = (1UL << SCU_GENERAL_STCON_SWCON_Pos), /**< UART bootstrap. */ + XMC_SCU_BOOTMODE_BMI = (2UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot Mode Index - Customized boot + sequence. */ + XMC_SCU_BOOTMODE_CAN_BSL = (3UL << SCU_GENERAL_STCON_SWCON_Pos), /**< CAN bootstrap. */ + XMC_SCU_BOOTMODE_PSRAM_BOOT = (4UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from PSRAM. */ + XMC_SCU_BOOTMODE_ABM0 = (8UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from flash - fixed alternative + address 0. */ + XMC_SCU_BOOTMODE_ABM1 = (12UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from flash - fixed alternative + address 1. */ + XMC_SCU_BOOTMODE_FABM = (14UL << SCU_GENERAL_STCON_SWCON_Pos), /**< fallback Alternate Boot Mode (ABM) - + Try ABM-0 then try ABM-1. */ +} XMC_SCU_BOOTMODE_t; + + +/** + * Defines various PLL modes of operation. These enums are used to configure \a VCOBYP bit of \a PLLCON0 register. + * User can choose either normal or prescalar mode by configuring VCOBYP bit. + * Use type \a XMC_SCU_PLL_MODE_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_SYSPLL_MODE +{ + XMC_SCU_CLOCK_SYSPLL_MODE_DISABLED, /**< fPLL derived from fOSC and PLL operating in prescalar mode(i.e.VCO bypassed). */ + XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL, /**< fPLL derived from fVCO and PLL operating in normal mode. */ + XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR /**< fPLL derived from fOSC and PLL operating in prescalar mode(i.e.VCO bypassed). */ +} XMC_SCU_CLOCK_SYSPLL_MODE_t; + +/** + * Defines the source of the system clock and peripherals clock gating in SLEEP state. + * Use this enum as parameter of XMC_SCU_CLOCK_SetSleepConfig before going to SLEEP state. + * + * The SLEEP state of the system corresponds to the SLEEP state of the CPU. The state is + * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is + * stopped. Peripherals are only clocked when configured to stay enabled. + * + * Peripherals can continue to operate unaffected and eventually generate an event to + * wake-up the CPU. Any interrupt to the NVIC will bring the CPU back to operation. The + * clock tree upon exit from SLEEP state is restored to what it was before entry into SLEEP + * state. + * + */ +typedef enum XMC_SCU_CLOCK_SLEEP_MODE_CONFIG +{ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI = 0, /**< fOFI used as system clock source in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FPLL = SCU_CLK_SLEEPCR_SYSSEL_Msk, /**< fPLL used as system clock source in SLEEP state */ +#if defined(USB0) + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_USB = 0, /**< USB clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_USB = SCU_CLK_SLEEPCR_USBCR_Msk, /**< USB clock enabled in SLEEP state */ +#endif +#if defined(SDMMC) + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_SDMMC = 0,/**< SDMMC clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_SDMMC = SCU_CLK_SLEEPCR_MMCCR_Msk,/**< SDMMC clock enabled in SLEEP state */ +#endif +#if defined(ETH0) + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_ETH = 0, /**< ETH clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_ETH = SCU_CLK_SLEEPCR_ETH0CR_Msk, /**< ETH clock enabled in SLEEP state */ +#endif +#if defined(EBU) + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_EBU = 0, /**< EBU clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_EBU = SCU_CLK_SLEEPCR_EBUCR_Msk, /**< EBU clock enabled in SLEEP state */ +#endif + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_CCU = 0, /**< CCU clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_CCU = SCU_CLK_SLEEPCR_CCUCR_Msk, /**< CCU clock enabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_WDT = 0, /**< WDT clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_WDT = SCU_CLK_SLEEPCR_WDTCR_Msk, /**< WDT clock enabled in SLEEP state */ +} XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_t; + +/** + * Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state. + * In addition the state of FLASH, PLL and PLLVCO during DEEPSLEEP state. + * Use this enum as parameter of XMC_SCU_CLOCK_SetDeepSleepConfig before going to DEEPSLEEP state. + * + * The DEEPSLEEP state of the system corresponds to the DEEPSLEEP state of the CPU. The state is + * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is + * stopped. + * + * In Deep Sleep state the OSC_HP and the PLL may be switched off. The wake-up logic in the NVIC is still clocked + * by a free-running clock. Peripherals are only clocked when configured to stay enabled. + * Configuration of peripherals and any SRAM content is preserved. + * The Flash module can be put into low-power mode to achieve a further power reduction. + * On wake-up Flash module will be restarted again before instructions or data access is possible. + * Any interrupt will bring the system back to operation via the NVIC.The clock setup before + * entering Deep Sleep state is restored upon wake-up. + */ +typedef enum XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG +{ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FOFI = 0, /**< fOFI used as system clock source in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FPLL = SCU_CLK_DSLEEPCR_SYSSEL_Msk, /**< fPLL used as system clock source in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_FLASH_POWERDOWN = SCU_CLK_DSLEEPCR_FPDN_Msk,/**< Flash power down in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN = SCU_CLK_DSLEEPCR_PLLPDN_Msk, /**< Switch off main PLL in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_VCO_POWERDOWN = SCU_CLK_DSLEEPCR_VCOPDN_Msk, /**< Switch off VCO of main PLL in DEEPSLEEP state */ +#if defined(USB0) + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_USB = 0, /**< USB clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_USB = SCU_CLK_DSLEEPCR_USBCR_Msk, /**< USB clock enabled in DEEPSLEEP state */ +#endif +#if defined(SDMMC) + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_SDMMC = 0,/**< SDMMC clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_SDMMC = SCU_CLK_DSLEEPCR_MMCCR_Msk,/**< SDMMC clock enabled in DEEPSLEEP state */ +#endif +#if defined(ETH0) + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_ETH = 0, /**< ETH clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_ETH = SCU_CLK_DSLEEPCR_ETH0CR_Msk, /**< ETH clock enabled in DEEPSLEEP state */ +#endif +#if defined(EBU) + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_EBU = 0, /**< EBU clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_EBU = SCU_CLK_DSLEEPCR_EBUCR_Msk, /**< EBU clock enabled in DEEPSLEEP state */ +#endif + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_CCU = 0, /**< CCU clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_CCU = SCU_CLK_DSLEEPCR_CCUCR_Msk, /**< CCU clock enabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_WDT = 0, /**< WDT clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_WDT = SCU_CLK_DSLEEPCR_WDTCR_Msk, /**< WDT clock enabled in DEEPSLEEP state */ +} XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_t; + +/** + * Defines status of EVR13 regulator + */ +typedef enum XMC_SCU_POWER_EVR_STATUS +{ + XMC_SCU_POWER_EVR_STATUS_OK = 0, /**< EVR13 regulator No overvoltage condition */ + XMC_SCU_POWER_EVR_STATUS_EVR13_OVERVOLTAGE = SCU_POWER_EVRSTAT_OV13_Msk /**< EVR13 regulator is in overvoltage */ +} XMC_SCU_POWER_EVR_STATUS_t; + +/** + * Define status of external hibernate control + */ +typedef enum XMC_SCU_HIB_CTRL_STATUS +{ + XMC_SCU_HIB_CTRL_STATUS_NO_ACTIVE = 0, /**< Hibernate not driven active to pads */ + XMC_SCU_HIB_CTRL_STATUS_ACTIVE = SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk, /**< Hibernate driven active to pads */ +} XMC_SCU_HIB_CTRL_STATUS_t; + +/** + * Hibernate domain event status + */ +typedef enum XMC_SCU_HIB_EVENT +{ + XMC_SCU_HIB_EVENT_WAKEUP_ON_POS_EDGE = SCU_HIBERNATE_HDCR_WKPEP_Msk, /**< Wake-up on positive edge pin event */ + XMC_SCU_HIB_EVENT_WAKEUP_ON_NEG_EDGE = SCU_HIBERNATE_HDCR_WKPEN_Msk, /**< Wake-up on negative edge pin event */ + XMC_SCU_HIB_EVENT_WAKEUP_ON_RTC = SCU_HIBERNATE_HDCR_RTCE_Msk, /**< Wake-up on RTC event */ + XMC_SCU_HIB_EVENT_ULPWDG = SCU_HIBERNATE_HDCR_ULPWDGEN_Msk, /**< ULP watchdog alarm status */ +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE = SCU_HIBERNATE_HDSTAT_VBATPEV_Msk, /**< Wake-up on LPAC positive edge of VBAT threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */ + XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE = SCU_HIBERNATE_HDSTAT_VBATNEV_Msk, /**< Wake-up on LPAC negative edge of VBAT threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */ + XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Msk, /**< Wake-up on LPAC positive edge of HIB_IO_0 threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */ + XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Msk, /**< Wake-up on LPAC negative edge of HIB_IO_0 threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */ +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Msk, /**< Wake-up on LPAC positive edge of HIB_IO_1 threshold crossing. @note Only available in XMC44 series and LQFP100. */ + XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Msk, /**< Wake-up on LPAC negative edge of HIB_IO_1 threshold crossing. @note Only available in XMC44 series and LQFP100. */ +#endif +#endif +} XMC_SCU_HIB_EVENT_t; + +/** + * Hibernate domain dedicated pins + */ +typedef enum XMC_SCU_HIB_IO +{ + XMC_SCU_HIB_IO_0 = 0, /**< HIB_IO_0 pin. + At the first power-up and with every reset of the hibernate domain this pin is configured as opendrain output and drives "0". As output the medium driver mode is active. */ +#if (defined(DOXYGEN) || (UC_PACKAGE == BGA196) || (UC_PACKAGE == BGA144) || (UC_PACKAGE == LQFP144) || (UC_PACKAGE == LQFP100)) + XMC_SCU_HIB_IO_1 = 1 /**< HIB_IO_1 pin. + At the first power-up and with every reset of the hibernate domain this pin is configured as input with no pull device active. As output the medium driver mode is active. + @note : Only available in certain packages*/ +#endif +} XMC_SCU_HIB_IO_t; + +/** + * HIB_IOx pin I/O control + */ +typedef enum XMC_SCU_HIB_PIN_MODE +{ + XMC_SCU_HIB_PIN_MODE_INPUT_PULL_NONE = 0 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Direct input, no input pull device connected */ + XMC_SCU_HIB_PIN_MODE_INPUT_PULL_DOWN = 1 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Direct input, input pull down device connected */ + XMC_SCU_HIB_PIN_MODE_INPUT_PULL_UP = 2 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Direct input, input pull up device connected */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_HIBCTRL = 8 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Push-pull HIB control output */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_WDTSRV = 9 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Push-pull WDT service output */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_GPIO = 10 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Push-pull GPIO output */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_HIBCTRL = 12 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain HIB control output */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_WDTSRV = 13 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain WDT service output */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_GPIO = 14 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain GPIO output */ +} XMC_SCU_HIB_PIN_MODE_t; + +/** + * Selects the output polarity of the HIB_IOx + */ +typedef enum XMC_SCU_HIB_IO_OUTPUT_LEVEL +{ + XMC_SCU_HIB_IO_OUTPUT_LEVEL_LOW = 0 << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos, /**< Direct value */ + XMC_SCU_HIB_IO_OUTPUT_LEVEL_HIGH = 1 << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos /**< Inverted value */ +} XMC_SCU_HIB_IO_OUTPUT_LEVEL_t; + +/** + * Selects hibernate mode + */ +typedef enum XMC_SCU_HIB_HIBERNATE_MODE +{ + XMC_SCU_HIB_HIBERNATE_MODE_EXTERNAL = 0, /**< Request external hibernate mode */ +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + XMC_SCU_HIB_HIBERNATE_MODE_INTERNAL = 1, /**< Request internal hibernate mode. @note Only available in XMC44, XMC42 and XMC41 series */ +#endif +} XMC_SCU_HIB_HIBERNATE_MODE_t; + +/** + * Selects input signal HIB_SR0 of ERU0 + */ +typedef enum XMC_SCU_HIB_SR0_INPUT +{ + XMC_SCU_HIB_SR0_INPUT_HIB_IO_0 = SCU_HIBERNATE_HDCR_GPI0SEL_Msk, /**< Set HIB_SR0 to HIB_IO_0 digital input */ +#if (defined(DOXYGEN) || (UC_PACKAGE == BGA196) || (UC_PACKAGE == BGA144) || (UC_PACKAGE == LQFP144) || (UC_PACKAGE == LQFP100)) + XMC_SCU_HIB_SR0_INPUT_HIB_IO_1 = 0, /**< Set HIB_SR0 to HIB_IO_1 digital input. @note Only available in certain packages. */ +#endif +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + XMC_SCU_HIB_SR0_INPUT_ACMP0 = SCU_HIBERNATE_HDCR_ADIG0SEL_Msk, /**< Set HIB_SR0 to LPAC CMP0. @note Only available in XMC44, XMC42 and XMC41 series. */ +#endif +} XMC_SCU_HIB_SR0_INPUT_t; + +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + +#if ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)) +/** + * Selects input signal HIB_SR1 of ERU0. @note Only available in XMC44 in certain packages. + */ +typedef enum XMC_SCU_HIB_SR1_INPUT +{ + XMC_SCU_HIB_SR1_INPUT_HIB_IO_0 = SCU_HIBERNATE_HDCR_GPI1SEL_Msk, /**< Set HIB_SR1 to HIB_IO_0 digital input */ + XMC_SCU_HIB_SR1_INPUT_HIB_IO_1 = 0, /**< Set HIB_SR1 to HIB_IO_1 digital input. */ + XMC_SCU_HIB_SR1_INPUT_ACMP1 = SCU_HIBERNATE_HDCR_ADIG1SEL_Msk, /**< Set HIB_SR0 to LPAC CMP1. */ + XMC_SCU_HIB_SR1_INPUT_XTAL_GPI = SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk, /**< Set HIB_SR0 to RTC_XTAL_1 digital input */ +} XMC_SCU_HIB_SR1_INPUT_t; +#endif + +/** + * HIB LPAC input selection + */ +typedef enum XMC_SCU_HIB_LPAC_INPUT +{ + XMC_SCU_HIB_LPAC_INPUT_DISABLED = 0 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator permanently in power down */ + XMC_SCU_HIB_LPAC_INPUT_VBAT = 0x1 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for VBAT input */ + XMC_SCU_HIB_LPAC_INPUT_HIB_IO_0 = 0x2 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for HIB_IO_0 input */ +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + XMC_SCU_HIB_LPAC_INPUT_HIB_IO_1 = 0x4 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for HIB_IO_1 input. @note Only available in XMC44 series and LQFP100 package. */ +#endif +} XMC_SCU_HIB_LPAC_INPUT_t; + +/** + * HIB LPAC start trigger selection for selected inputs + */ +typedef enum XMC_SCU_HIB_LPAC_TRIGGER +{ + XMC_SCU_HIB_LPAC_TRIGGER_SUBSECOND_INTERVAL_COUNTER = 0 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< Sub-second interval counter */ + XMC_SCU_HIB_LPAC_TRIGGER_RTC_ALARM_EVENT = 0x1 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< RTC alarm event */ + XMC_SCU_HIB_LPAC_TRIGGER_RTC_PERIODIC_EVENT = 0x2 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< RTC periodic event */ + XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_POSITIVE_EDGE_EVENT = 0x3 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< On digital wakeup input positive edge event */ + XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_NEGATIVE_EDGE_EVENT = 0x5 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< On digital wakeup input negative edge event */ + XMC_SCU_HIB_LPAC_TRIGGER_CONTINOUS = 0x6 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< Continuous measurement */ + XMC_SCU_HIB_LPAC_TRIGGER_SINGLE_SHOT = 0x7 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< Single shot on software request */ +} XMC_SCU_HIB_LPAC_TRIGGER_t; + +/** + * HIB LPAC status + */ +typedef enum XMC_SCU_HIB_LPAC_STATUS +{ + XMC_SCU_HIB_LPAC_STATUS_VBAT_COMPARE_DONE = SCU_HIBERNATE_LPACST_VBATSCMP_Msk, /**< VBAT compare operation completed */ + XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_COMPARE_DONE = SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Msk, /**< HBI_IO_0 compare operation completed */ +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_COMPARE_DONE = SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Msk, /**< HBI_IO_1 compare operation completed. @note Only available in XMC44 series and LQFP100 package. */ +#endif + XMC_SCU_HIB_LPAC_STATUS_VBAT_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_VBATVAL_Msk, /**< VBAT comparison result above programmed threshold */ + XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_AHIBIO0VAL_Msk, /**< HBI_IO_0 comparison result above programmed threshold */ +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_AHIBIO1VAL_Msk, /**< HBI_IO_1 comparison result above programmed threshold. @note Only available in XMC44 series and LQFP100 package. */ +#endif +} XMC_SCU_HIB_LPAC_STATUS_t; + +#endif /* (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) */ + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/** + * Defines a data structure for initializing the PLL functional block. + * Structure holds divider values for N-DIV, P-DIV, K1-DIV, K2-DIV in order to generate desired + * frequency using VCO. It holds the PLL mode of operation either normal or prescaler (VCO bypassed). + * Use type \a XMC_SCU_CLOCK_PLL_CONFIG_t for accessing these structure parameters. + */ +typedef struct XMC_SCU_CLOCK_SYSPLL_CONFIG +{ + uint8_t n_div; /**< PLL N-Divider value. */ + uint8_t p_div; /**< PLL P-Divider value. */ + uint8_t k_div; /**< K1-Divider(Prescalar mode) or K2-Divider (Normal mode). */ + XMC_SCU_CLOCK_SYSPLL_MODE_t mode; /**< PLL mode of operation. */ + XMC_SCU_CLOCK_SYSPLLCLKSRC_t clksrc; /**< PLL divider input frequency. */ +} XMC_SCU_CLOCK_SYSPLL_CONFIG_t; + +/** + * Defines a data structure used for initializing the clock functional block. + * Clock functional block configures clock source needed for various peripheral and its divider values. + * Use type \a XMC_SCU_CLOCK_CONFIG_t for accessing these structure parameters. + */ +typedef struct XMC_SCU_CLOCK_CONFIG +{ + XMC_SCU_CLOCK_SYSPLL_CONFIG_t syspll_config; /**< PLL configuration */ + bool enable_oschp; /**< Enable external high precision oscillator. + Should be enabled when fOHP has to be source of system clock. */ + bool enable_osculp; /**< Enable external ultra low power oscillator. + Should be enabled when fULP has to be source of standby clock(fSTDBY). */ + XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t calibration_mode; /**< Backup clock trimming mode. */ + XMC_SCU_HIB_STDBYCLKSRC_t fstdby_clksrc; /**< Standby clock source. */ + XMC_SCU_CLOCK_SYSCLKSRC_t fsys_clksrc; /**< Choice of system clock. */ + uint8_t fsys_clkdiv; /**< Ratio of fPLL to fSYS. */ + uint8_t fcpu_clkdiv; /**< Ratio of fSys to fCPU. */ + uint8_t fccu_clkdiv; /**< Ratio of fSys to fCCU. */ + uint8_t fperipheral_clkdiv; /**< Ratio of fSYS to fPERI. */ +} const XMC_SCU_CLOCK_CONFIG_t; + +/** + * Low power modes + */ +typedef enum XMC_SCU_POWER_MODE_t +{ + XMC_SCU_POWER_MODE_SLEEP = 0, /**< sleep mode stops the processor clock */ + XMC_SCU_POWER_MODE_DEEPSLEEP = SCB_SCR_SLEEPDEEP_Msk /**< deep sleep mode stops the system clock and switches off the PLL and flash memory. */ +} XMC_SCU_POWER_MODE_t; + +/********************************************************************************************************************* + * API PROTOTYPES + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + * @param group ADC Group to which the channel being monitored belongs to.\n + * \b Range: 0 or 1. + * @param channel The channel whose voltage range has to be monitored.\n + * \b Range: 6 or 7. Value identifies the channel in the selected ADC group. + * + * @return None + * + * \parDescription
+ * Enables out of range comparator for the selected ADC group and channel. \n\n + * The ADC channel input is compared by Out of Range Comparator (ORC) for overvoltage monitoring + * or for detection of out of range analog inputs. ORC must be turned on explicitly + * to leverage the auditing feature. ORC is enabled by setting the enable bit in the GORCEN register. + * \parRelated APIs:
+ * XMC_SCU_DisableOutOfRangeComparator()\n\n\n + */ +void XMC_SCU_EnableOutOfRangeComparator(const uint32_t group, const uint32_t channel); + +/** + * + * @param group ADC Group to which the channel being monitored belongs to.\n + * \b Range: 0 or 1. + * @param channel The channel whose voltage range has to be monitored.\n + * \b Range: 6 or 7. Value identifies the channel in the selected ADC group. + * + * @return None + * + * \parDescription
+ * Disables the out of range comparator for the selected ADC group and the channel. \n\n + * Out of range comparator is disabled by clearing the enable bit in the GORCEN register. + * \parRelated APIs:
+ * XMC_SCU_EnableOutOfRangeComparator()\n\n\n + */ +void XMC_SCU_DisableOutOfRangeComparator(const uint32_t group, const uint32_t channel); + +/** + * @return None + * + * \parDescription
+ * Enables die temperature measurement by powering the DTS module.\n\n + * Die temperature sensor is enabled by setting the PWD bit of DTSCON register. + * \parRelated APIs:
+ * XMC_SCU_DisableTemperatureSensor(), XMC_SCU_IsTemperatureSensorEnabled(), XMC_SCU_CalibrateTemperatureSensor(), + * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +void XMC_SCU_EnableTemperatureSensor(void); + +/** + * @return None + * + * \parDescription
+ * Disables die temperature measurement by powering the DTS module off.\n\n + * Die temperature sensor is disabled by clearing the PWD bit of DTSCON register. + * \parRelated APIs:
+ * XMC_SCU_EnableTemperatureSensor(), XMC_SCU_IsTemperatureSensorEnabled(), XMC_SCU_CalibrateTemperatureSensor(), + * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +void XMC_SCU_DisableTemperatureSensor(void); + +/** + * @return Status of die temperature sensor. \n + * \b Range: true - if temperature sensor is enabled.\n + * false - if temperature sensor is disabled. + * + * \parDescription
+ * Provides the die temperature sensor power status.\n\n + * The status is obtained by reading the PWD bit of DTSCON register. + * \parRelated APIs:
+ * XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor(), + * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +bool XMC_SCU_IsTemperatureSensorEnabled(void); + +/** + * + * @param offset Offset value for calibrating the DTS result.\n + * \b Range: 0 to 127. + * @param gain Gain value for calibrating the DTS conversion result.\n + * \b Range: 0 to 63. + * + * @return None + * + * \parDescription
+ * Calibrates the measurement of temperature by configuring the values of offset and gain of \a DTSCON register. \n\n + * Allows to improve the accuracy of the temperature measurement with the adjustment of \a OFFSET and \a GAIN bit fields + * in the \a DTSCON register. + * Offset adjustment is defined as a shift of the conversion result. The range of the offset adjustment is 7 bits with a + * resolution that corresponds to +/- 12.5�C. The offset value gets added to the measure result. + * Offset is considered as a signed value. + * Gain adjustment helps in minimizing gain error. When the \a gain value is 0, result is generated with maximum gain. + * When the \a gain value is 63, result is generated with least gain, i.e, \a RESULT - 63 at the highest measured temperature.\n + * It is recommended to use following steps:\n + * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\n + * - Call \a XMC_SCU_CalibrateTempMonitor with desired offset and gain calibration values to the DTS.\n + * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.\n + * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n + * - Check whether Die Temperature Sensor (DTS) is busy in conversion by calling \a XMC_SCU_IsTemperatureSensorBusy() and wait till + * conversion complete.\n + * - Read the die temperature value using \a XMC_SCU_GetTemperatureMeasurement API. + * \parRelated APIs:
+ * XMC_SCU_EnableTemperatureSensor(), + * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +void XMC_SCU_CalibrateTemperatureSensor(uint32_t offset, uint32_t gain); + +/** + * @return XMC_SCU_STATUS_t Result of starting the temperature measurement.\n + * \b Range: \n + * XMC_SCU_STATUS_OK if the measurement is started successfully.\n + * XMC_SCU_STATUS_ERROR if temperature sensor is not enabled.\n + * XMC_SCU_STATUS_BUSY if temperature sensor is busy measuring the temperature.\n + * + * + * \parDescription
+ * Starts die temperature measurement using internal temperature sensor.\n\n + * The API checks if the temperature sensor is enabled and is not busy in measurement.\n + * It is recommended to use following steps:\n + * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\n + * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.\n + * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n + * - Check whether Die Temperature Sensor (DTS) is busy in conversion by calling \a XMC_SCU_IsTemperatureSensorBusy() and wait till + * conversion complete.\n + * - Read the die temperature value using \a XMC_SCU_GetTemperatureMeasurement API. + * \parRelated APIs:
+ * XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor(), + * XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +XMC_SCU_STATUS_t XMC_SCU_StartTemperatureMeasurement(void); + + +/** + * + * @return uint32_t Measured temperature value.\n + * \b Range: Valid temperature range is 0 to 1023. \n + * If sensor is not enabled, 0x7FFFFFFFH is returned. + * + * \parDescription
+ * Reads the measured value of die temperature.\n\n + * Temperature measurement result is read from \a RESULT bit field of \a DTSSTAT register. + * The temperature measured in �C is given by (RESULT - 605) / 2.05 [�C] + * \parRelated APIs:
+ * XMC_SCU_IsTemperatureSensorBusy() \n\n\n + */ +uint32_t XMC_SCU_GetTemperatureMeasurement(void); + +/** + * @return bool Indicates if the die temperature sensor is busy.\n + * \b Range: \a true if sensor is busy in temperature measurement. + * \a false if sensor is free and can accept a new request for measurement. + * + * \parDescription
+ * Checks whether Die Temperature Sensor (DTS) is busy in temperature measurement.\n\n + * The status is read from the \a BUSY bit field of the \a DTSSTAT register. + * \parRelated APIs:
+ * XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +bool XMC_SCU_IsTemperatureSensorBusy(void); + +/** + * @return bool Status of die temperature sensor whether it is ready to start measurement. \n + * \b Range: \n \a true if temperature sensor is ready to start measurement. \n + * \a false if temperature sensor is not ready to start measurement. + * + * \parDescription
+ * Checks if the die temperature sensor is ready to start a measurement\n\n + * The status is obtained by reading \a RDY bit of \a DTSSTAT register. It is recommended + * to check the ready status of die temperature sensor before starting it. + * \parRelated APIs:
+ * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_IsTemperatureSensorBusy() \n\n\n + */ +bool XMC_SCU_IsTemperatureSensorReady(void); + +#if (UC_SERIES != XMC45) +/** + * @return bool Indicates if the measured die temperature value has exceeded the configured upper limit.\n + * \b Range: \a true if the temperature value has exceeded the configured upper limit. \a false + * if the temperature value is less than the configured upper limit. + * + * \parDescription
+ * Checks if the measured temperature has exceeded the configured upper limit of temperature.\n\n + * The API checks \a OVERFL bit (Upper Limit Overflow Status bit) of \a DTEMPALARM register. + * The \a OVERFL bit will be set if the measured temperature has exceeded the limit configured in + * the bitfield \a UPPER in the \a DTEMPLIM register. + * \parRelated APIs:
+ * XMC_SCU_SetRawTempLimits(),XMC_SCU_LowTemperature() \n\n\n + */ +bool XMC_SCU_HighTemperature(void); + +/** + * + * @param lower_temp Lower threshold of die temperature. If measured temperature falls below this value, + * alarm bit will be set in \a UNDERFL bit field of \a DTEMPALARM register. + * @param upper_temp Upper threshold of die temperature. If measured temperature exceeds this value, + * alarm bit will be set in \a OVERFL bit field of \a DTEMPALARM register. + * + * @return None + * + * \parDescription
+ * Configures the lower and upper threshold of die temperature.\n\n + * API configures \a DTEMPLIM register for upper and lower die temperature threshold limits. + * When the measured temperature is outside the range defined by the limits, alarm bits \a UNDERFL or \a OVERFL + * will be set in the register \a DTEMPALARM.\n + * It is recommended to use following steps:\n + * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\n + * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values.\n + * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n + * - Use \a XMC_SCU_HighTemperature() and XMC_SCU_LowTemperature() to monitor the temperature.\n + * \parRelated APIs:
+ * XMC_SCU_HighTemperature(), XMC_SCU_LowTemperature() \n\n\n + */ +void XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp); + +/** + * @return bool Indicates if the measured die temperature value has dropped below the configured lower limit.\n + * \b Range: \a true if the temperature value has dropped below the configured lower limit. \a false + * if the temperature value is higher than the configured lower limit. + * + * \parDescription
+ * Checks if the measured temperature has dropped below the configured lower limit of temperature.\n\n + * The API checks \a UNDERFL bit (Lower LimitUnderflow Status bit) of \a DTEMPALARM register. + * The \a UNDERFL bit will be set if the measured temperature has dropped below the limit configured in + * the bitfield \a LOWER in the \a DTEMPLIM register. + * \parRelated APIs:
+ * XMC_SCU_SetRawTempLimits(),XMC_SCU_HighTemperature() \n\n\n + */ +bool XMC_SCU_LowTemperature(void); +#endif + +/** + * @return uint32_t Configured boot mode for the device.\n + * \b Range: Use type @ref XMC_SCU_BOOTMODE_t for enumeration of different boot modes. + * + * \parDescription
+ * Provides the boot mode configured for the device.\n\n + * The boot mode is read from the \a STCON register bit field \a SWCON. + * + * \parRelated APIs:
+ * XMC_SCU_SetBootMode() \n\n\n + */ +uint32_t XMC_SCU_GetBootMode(void); + +/** + * + * @param mode Boot mode to be configured for the device.\n + * \b Range: Use type @ref XMC_SCU_BOOTMODE_t for selecting the boot mode. + * + * @return None + * + * \parDescription
+ * Configures the desired boot mode for the device.\n\n + * The XMC4 series devices support multiple boot modes. A running application can set a desired bootmode and + * launch it by means of software reset. Switching of boot modes should be handled carefully. User should ensure that + * the initial boot sequence is executed. A stable execution environment should be maintained when program control is + * eventually handed over to the application program.\n + * It is recommended to use following steps to launch requested bootmode:\n + * - Call \a XMC_SCU_SetBootMode() with desired boot mode value.\n + * - Trigger a software reset using system reset request by enabling a bit \a SYSRESETREQ of AIRCR register + * (PPB->AIRCR |= PPB_AIRCR_SYSRESETREQ_Msk).\n + * \parRelated APIs:
+ * XMC_SCU_GetBootMode() \n\n\n + */ +void XMC_SCU_SetBootMode(const XMC_SCU_BOOTMODE_t mode); + +/** + * + * @param index The SCU general purpose register to be read.\n + * \b Range: 0 and 1 corresponding to GPR0 and GPR1. + * + * @return uint32_t Data read from the selected general purpose register. + * + * \parDescription
+ * Provides stored data from general purpose SCU register.\n\n + * SCU consists of 2 general purpose registers. These registers can be used for storing + * data. The API reads from either GPR0 or GPR1 based on the \a index value. + * \parRelated APIs:
+ * XMC_SCU_WriteGPR()\n\n\n + */ +uint32_t XMC_SCU_ReadGPR(const uint32_t index); + +/** + * + * @param index The SCU general purpose register to be written.\n + * \b Range: 0 and 1 corresponding to GPR0 and GPR1. + * @param data Data to be written to the selected general purpose register. + * + * @return None + * + * \parDescription
+ * Stores data in the selected general purpose SCU register.\n\n + * SCU consists of 2 general purpose registers. These registers can be used for storing + * data. The API writes data to either GPR0 or GPR1 based on the \a index value. + * \parRelated APIs:
+ * XMC_SCU_ReadGPR()\n\n\n + */ +void XMC_SCU_WriteGPR(const uint32_t index, const uint32_t data); + +/** + * + * @param address Location in the retention memory to be written.\n + * \b Range: 4 bit address space is provided for selecting 16 words of 32 bits. + * equivalent to 64 bytes of data. \a address value should be from + * 0 to 15. + * @param data 32 bit data to be written into retention memory. The API writes + * one word(4 bytes) of data to the address specified.\n + * \b Range: 32 bit data. + * + * @return None + * + * \parDescription
+ * Writes input data to the selected address of Retention memory in hibernate domain.\n\n + * The retention memory is located in hibernate domain. + * It is used for the purpose of store/restore of context information. + * Access to the retention memory space is served over shared serial interface. + * Retention memory content is retained even in hibernate mode. + * \parRelated APIs:
+ * XMC_SCU_ReadFromRetentionMemory() \n\n\n + */ +void XMC_SCU_WriteToRetentionMemory(uint32_t address, uint32_t data); + +/** + * + * @param address Location in the retention memory to be read.\n + * \b Range: 4 bit address space is provided for selecting 16 words of 32 bits. + * equivalent to 64 bytes of data. \a address value should be from + * 0 to 15. + * + * @return uint32_t 32 bit data read from retention memory. The API reads + * one word(4 bytes) of data from the address specified.\n + * \b Range: 32 bit data. + * + * \parDescription
+ * Reads data from selected address of retention memory in hibernate domain.\n\n + * The retention memory is located in hibernate domain. + * It is used for the purpose of store/restore of context information. + * Access to the retention memory space is served over shared serial interface. + * Retention memory content is retained even in hibernate mode. + * \parRelated APIs:
+ * XMC_SCU_WriteToRetentionMemory() \n\n\n + */ +uint32_t XMC_SCU_ReadFromRetentionMemory(uint32_t address); + +/** + * + * @param request Non-maskable interrupt (NMI) request source to be enabled.\n + * \b Range: Use type @ref XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple + * sources can be combined using \a OR operation. + * + * @return None + * + * \parDescription
+ * Selectively enables interrupt sources to generate non maskable interrupt(NMI).\n\n + * NMI assertion can be individually enabled by setting corresponding bit of an interrupt in the + * \a NMIREQEN register. + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_DisableNmiRequest() \n\n\n + */ +void XMC_SCU_INTERRUPT_EnableNmiRequest(const uint32_t request); + +/** + * + * @param request Non-maskable interrupt (NMI) request source to be disabled.\n + * \b Range: Use type @ref XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple + * sources can be combined using \a OR operation. + * + * @return None + * + * \parDescription
+ * Selectively disables interrupt sources from generating non maskable interrupt(NMI).\n\n + * NMI assertion can be individually disabled by clearing corresponding bits in the \a NMIREQEN register. + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_EnableNmiRequest() \n\n\n + */ +void XMC_SCU_INTERRUPT_DisableNmiRequest(const uint32_t request); + +/** + * + * @param trap The event for which, trap generation has to be enabled.\n + * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. + * + * @return None + * + * \parDescription
+ * Enables assertion of trap for the selected trap event.\n\n + * Trap assertion can be individually enabled by clearing respective bit of the + * event in \a TRAPDIS register in order to get an exception. + * \parRelated APIs:
+ * XMC_SCU_TRAP_Disable(), XMC_SCU_TRAP_ClearStatus(), XMC_SCU_TRAP_GetStatus() \n\n\n + */ +void XMC_SCU_TRAP_Enable(const uint32_t trap); + +/** + * + * @param trap The event for which, trap generation has to be disabled.\n + * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. + * + * @return None + * + * \parDescription
+ * Disables assertion of trap for the selected trap event.\n\n + * Trap assertion can be individually disabled by setting the respective event bit + * in the \a TRAPDIS register in order to suppress trap generation. + * \parRelated APIs:
+ * XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_ClearStatus(), XMC_SCU_TRAP_GetStatus() \n\n\n + */ +void XMC_SCU_TRAP_Disable(const uint32_t trap); + +/** + * + * @param trap The event for which, trap status bit has to be cleared.\n + * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. + * + * @return None + * + * \parDescription
+ * Clears the trap status of input event.\n\n + * Once a trap event is detected, it will have to be acknowledged and later serviced. + * The trap status bit should be cleared to detect the occurence of trap next time. + * This is useful while polling for TRAPSTAT without enabling the NMI for trap. + * Trap status can be cleared by setting the event bit in the \a TRAPCLR register. + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_GetStatus() \n\n\n + */ +void XMC_SCU_TRAP_ClearStatus(const uint32_t trap); + +/** + * @return uint32_t Status of trap generating events.\n + * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. The returned + * value indicates the status of multiple events at their respective bit positions. + * User should mask the bits of the events of interest using the type specified. + * + * \parDescription
+ * Provides the status of trap generating events. \n\n + * The status is read from \a TRAPRAW register. Status of the specific events can be checked + * using their respective bits in the \a TRAPRAW register. The bit masks can be obtained from + * the enumeration type @ref XMC_SCU_TRAP_t. Multiple events can be combined using \a OR operation. + * A trap event is considered to be asserted if the respective bit of the event is set to 1. + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_ClearStatus() \n\n\n + */ +uint32_t XMC_SCU_TRAP_GetStatus(void); + +/** + * + * @param trap The event for which, trap has to be triggered.\n + * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. + * + * @return None + * + * \parDescription
+ * Triggers trap generation for the event specified. \n\n + * The trap source has to be enabled before invocation of this API. + * Trap event can be triggered by setting its respective bit in the \a TRAPSET register. + * Trap event can be configured to generate a non maskable interrupt by using the API XMC_SCU_INTERRUPT_EnableNmiRequest().\n + * It is recommended to use following steps to manually assert a trap event:\n + * - Call \a XMC_SCU_TRAP_EnableEvent with desired trap request source ID.\n + * - Call \a XMC_SCU_TRAP_SetEvent with same trap request source ID to manually assert a trap event.\n + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_GetStatus() \n\n\n + */ +void XMC_SCU_TRAP_Trigger(const uint32_t trap); + +/** + * + * @param peripheral The peripheral to be reset.\n + * \b Range: Type @ref XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals that can be reset. + * + * @return None + * + * \parDescription
+ * Puts the specified peripheral in to reset state. \n\n + * The API achieves reset of peripherals by setting the respective bit in the \a PRSET0, \a PRSET1 or \a PRSET2 + * register. Status of reset assertion automatically stored in the \a PRSTATn register and can be checked by + * user software to determine the state of the system and for debug purpose.\n + * It is recommended to use following steps to assert a peripheral reset:\n + * - Call \a XMC_SCU_RESET_AssertPeripheralReset() with desired peripheral identifier.\n + * - Call \a XMC_SCU_RESET_IsPeripheralResetAsserted with same peripheral identifier to verify whether peripheral + * is in reset state.\n + * \parRelated APIs:
+ * XMC_SCU_RESET_IsPeripheralResetAsserted() \n\n\n + */ +void XMC_SCU_RESET_AssertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peripheral); + +/** + * + * @param peripheral The peripheral to be moved out of reset state.\n + * \b Range: Type @ref XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals that can be reset. + * + * @return None + * + * \parDescription
+ * Enables the specified peripheral by moving it out of reset state. \n\n + * Any peripheral should be moved out of reset state for executing its functionality. + * The API enables the peripheral by setting its respective bit in the \a PRCLR0, \a PRCLR1 or \a PRCLR2 + * register. Status of reset deassertion is automatically stored in the \a PRSTATn register and can be checked by + * the user software to determine the state of the system and for debug purpose.\n + * It is recommended to use following steps to deassert a peripheral reset:\n + * - Call \a XMC_SCU_RESET_DeassertPeripheralReset() with desired peripheral identifier.\n + * - Call \a XMC_SCU_RESET_IsPeripheralResetAsserted() with desired peripheral identifier to verify whether peripheral + * has been enabled.\n + * \parRelated APIs:
+ * XMC_SCU_RESET_AssertPeripheralReset() \n\n\n + */ +void XMC_SCU_RESET_DeassertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peripheral); + +/** + * + * @param peripheral The peripheral, whose reset status has to be checked.\n + * \b Range: Type @ref XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals. + * + * @return bool Status of peripheral reset. \n + * \b Range: \a true if peripheral is in reset state. \a false if peripheral is enabled and out of reset state. + * + * \parDescription
+ * Checks the reset status of the selected peripheral.\n\n + * The API reads the reset status from \a PRSTATn register. Returns true if the peripheral is in + * reset state. On power up of the device, all the peripherals will be in reset state. + * If the peripheral is enabled, \a false will be returned as the status. + * \parRelated APIs:
+ * XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset() \n\n\n + */ +bool XMC_SCU_RESET_IsPeripheralResetAsserted(const XMC_SCU_PERIPHERAL_RESET_t peripheral); + +/** + * + * @param memory The on-chip RAM type, for which the parity error status has to be cleared.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * memory status bits can be cleared by using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Clears the parity error status bit. \n\n + * When a memory parity error is detected using the status bits in \a PEFLAG register. It has to + * be cleared by software to detect the parity error from the same memory next time. + * The API clears the parity error status bit of the selected peripheral by setting the + * respective bit in the \a PEFLAG register. Status of multiple memory parity errors + * can be cleared by combining the enum values using \a OR operation. + * \parRelated APIs:
+ * XMC_SCU_PARITY_GetStatus(), XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_EnableTrapGeneration() \n\n\n + */ +void XMC_SCU_PARITY_ClearStatus(const uint32_t memory); + +/** + * + * @param memory The on-chip RAM type, for which the parity error checking has to be enabled.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * memory types can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Enables parity error checking for the selected on-chip RAM type.\n\n + * Parity error checking can be enabled by setting respective bits in the \a PEEN register. + * Additionally parity error can be configured to generate trap when the error is detected, + * using the API XMC_SCU_PARITY_EnableTrapGeneration(). Such a trap can be further configured + * to generate non maskable interrupt(NMI) using the API XMC_SCU_INTERRUPT_EnableNmiRequest(). + * \parRelated APIs:
+ * XMC_SCU_PARITY_EnableTrapGeneration(), XMC_SCU_INTERRUPT_EnableNmiRequest() \n\n\n + */ +void XMC_SCU_PARITY_Enable(const uint32_t memory); + +/** + * + * @param memory The on-chip RAM type, for which the parity error checking has to be disabled.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * memory types can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Disables parity error checking for the selected on-chip RAM type.\n\n + * Parity error detection can be disabled by clearing the respective bit in the \a PEEN register. + * \parRelated APIs:
+ * XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_DisableTrapGeneration() \n\n\n + */ +void XMC_SCU_PARITY_Disable(const uint32_t memory); + +/** + * + * @param memory The on-chip RAM type, for which the parity error trap generation has to be enabled.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * memory types can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Enables trap assertion for the parity error source.\n\n + * Parity error detection for different types of on-chip RAM can generate trap. + * Trap assertion for parity error can be individually enabled by setting the respective bits + * in the \a PETE register. The generated trap can be additionally configured to generate + * non maskable interrupt(NMI) using the API XMC_SCU_INTERRUPT_EnableNmiRequest(). + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_PARITY_DisableTrapGeneration() \n\n\n + */ +void XMC_SCU_PARITY_EnableTrapGeneration(const uint32_t memory); + +/** + * + * @param memory The on-chip RAM type, for which the parity error trap generation has to be disabled.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * memory types can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Disables the assertion of trap for the parity error source.\n\n + * Trap assertion can be disabled by clearing the respective bit of the RAM type in the \a PETE register. + * + * \parRelated APIs:
+ * XMC_SCU_PARITY_EnableTrapGeneration() \n\n\n + */ +void XMC_SCU_PARITY_DisableTrapGeneration(const uint32_t memory); + +/** + * + * @return uint32_t Status of parity error detection for the on-chip RAM modules.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to get the bit mask of each RAM module type. + * + * \parDescription
+ * Provides the status of parity error detection for the on-chip RAM modules.\n\n + * Parity error status information is obtained from the \a PEFLAG register. + * If a particular RAM module has parity error, its respective bit field will be set to 1 in the + * returned value. A check for the status of a particular RAM module can be done by + * masking the returned value with the RAM module identifier from the type @ref XMC_SCU_PARITY_t. + * \parRelated APIs:
+ * XMC_SCU_PARITY_ClearStatus() \n\n\n + */ +uint32_t XMC_SCU_PARITY_GetStatus(void); + +/** + * + * @param clock Peripheral for which the clock has to be enabled. \n + * \b Range: Use type @ref XMC_SCU_CLOCK_t to select the peripheral. + * + * @return None + * + * \parDescription
+ * Enables the source clock for selected peripheral.\n\n + * The various outputs of Clock Generation Unit (CGU) can be individually enabled by setting the peripheral + * specific bit in the \a CLKSET register.\n + * It is recommended to use following steps to verify whether a source clock of peripheral is enabled/disabled:\n + * - Call \a XMC_SCU_CLOCK_EnableClock() with desired peripheral identifier.\n + * - Call \a XMC_SCU_CLOCK_IsClockEnabled() with same peripheral identifier to verify whether the clock is enabled.\n + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableClock(), XMC_SCU_RESET_DeassertPeripheralReset() \n\n\n + */ +void XMC_SCU_CLOCK_EnableClock(const XMC_SCU_CLOCK_t clock); + +/** + * + * @param clock Peripheral for which the clock has to be disabled. \n + * \b Range: Use type @ref XMC_SCU_CLOCK_t to select the peripheral. + * + * @return None + * + * \parDescription
+ * Disables source clock for the peripheral selected.\n\n + * The various outputs of Clock Generation Unit (CGU) can be individually disabled by setting the peripheral + * specific bits in the \a CLKCLR register.\n + * It is recommended to use following steps to verify whether clock source of the peripheral is enabled/disabled:\n + * - Call \a XMC_SCU_CLOCK_DisableClock with desired peripheral identifier.\n + * - Call \a XMC_SCU_CLOCK_IsClockEnabled with same peripheral identifier to verify whether peripheral is enabled/disabled.\n + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableClock(), XMC_SCU_RESET_AssertPeripheralReset() \n\n\n + */ +void XMC_SCU_CLOCK_DisableClock(const XMC_SCU_CLOCK_t clock); + +/** + * + * @param clock Peripheral for which the clock status has to be checked. \n + * \b Range: Use type @ref XMC_SCU_CLOCK_t to select the peripheral. + * + * @return bool Status of peripheral clock.\n + * \b Range: \a true if peripheral clock is enabled. \a false if peripheral clock is disabled. + * + * \parDescription
+ * Checks the status of peripheral source clock.\n\n + * The status of peripheral source clock is read from the \a CLKSTATn register. + * Returns \a true if clock is enabled and returns \a false otherwise. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableClock(), XMC_SCU_CLOCK_DisableClock() \n\n\n + */ +bool XMC_SCU_CLOCK_IsClockEnabled(const XMC_SCU_CLOCK_t clock); + +/** + * + * @param source Source of clock for fSYS.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSCLKSRC_t to select the source of clock.\n + * XMC_SCU_CLOCK_SYSCLKSRC_OFI for selecting internal fast clock as fSYS.\n + * XMC_SCU_CLOCK_SYSCLKSRC_PLL for selecting the output of PLL fPLL as fSYS. + * + * @return None + * + * \parDescription
+ * Selects the source for system clock (fSYS).\n\n + * System clock is selected by setting \a SYSSEL bits in the \a SYSCLKCR register. + * If \a XMC_SCU_CLOCK_SYSCLKSRC_PLL is selected, then the dividers of the PLL have to be + * additionally configured to achieve the required system clock frequency. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StartSystemPll(), XMC_SCU_CLOCK_EnableHighPerformanceOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_SetSystemClockSource(const XMC_SCU_CLOCK_SYSCLKSRC_t source); + +/** + * @return XMC_SCU_CLOCK_SYSCLKSRC_t Source of clock for fSYS.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSCLKSRC_t to select the source of clock.\n + * XMC_SCU_CLOCK_SYSCLKSRC_OFI - internal fast clock selected as fSYS.\n + * XMC_SCU_CLOCK_SYSCLKSRC_PLL - output of PLL fPLL selected as fSYS. + * + * \parDescription
+ * Provides the selected source of system clock (fSYS). \n\n + * Selected source of fSYS is obtained by reading \a SYSSEL bits of \a SYSCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSystemClockSource(), XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency() \n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_SYSCLKSRC_t XMC_SCU_CLOCK_GetSystemClockSource(void) +{ + return (XMC_SCU_CLOCK_SYSCLKSRC_t)(SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk); +} + +/** + * + * @param source Source of clock for USB and SDMMC(fUSB/SDMMC).\n + * \b Range: Use type @ref XMC_SCU_CLOCK_USBCLKSRC_t to select the source of clock.\n + * XMC_SCU_CLOCK_USBCLKSRC_USBPLL - output of USB PLL as source of USB clock(fUSB/SDMMC).\n + * XMC_SCU_CLOCK_USBCLKSRC_SYSPLL - output of PLL fPLL as source of USB clock(fUSB/SDMMC). + * + * @return None + * + * \parDescription
+ * Selects the source of USB/SDMMC clock (fUSB/SDMMC).\n\n + * USB and SDMMC use a common clock source. They can either use fUSB PLL or fPLL as the source of clock. + * The selection is done by configuring the \a USBSEL bits of \a USBCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbPllClockFrequency() \n\n\n + */ +void XMC_SCU_CLOCK_SetUsbClockSource(const XMC_SCU_CLOCK_USBCLKSRC_t source); + +/** + * @return XMC_SCU_CLOCK_USBCLKSRC_t Source of clock for USB and SDMMC(fUSB/SDMMC).\n + * \b Range: Use type @ref XMC_SCU_CLOCK_USBCLKSRC_t to identify the source of clock.\n + * XMC_SCU_CLOCK_USBCLKSRC_USBPLL - output of USB PLL is selected as source of USB clock(fUSB/SDMMC).\n + * XMC_SCU_CLOCK_USBCLKSRC_SYSPLL - output of PLL fPLL is selected as source of USB clock(fUSB/SDMMC). + * + * \parDescription
+ * Provides the selected source of USB and SDMMC clock frequency.\n\n + * The clock source is read from from the \a USBSEL bits of \a USBCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbPllClockFrequency() \n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_USBCLKSRC_t XMC_SCU_CLOCK_GetUsbClockSource(void) +{ + return (XMC_SCU_CLOCK_USBCLKSRC_t)(SCU_CLK->USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk); +} + +/** + * + * @param source Clock source for watchdog timer.\n + * \b Range: Use type XMC_SCU_CLOCK_WDTCLKSRC_t to identify the clock source.\n + * XMC_SCU_CLOCK_WDTCLKSRC_OFI - internal fast oscillator (fOFI)\n + * XMC_SCU_CLOCK_WDTCLKSRC_STDBY - backup standby clock (fSTDBY)\n + * XMC_SCU_CLOCK_WDTCLKSRC_PLL - PLL output clock (fPLL) + * + * @return None + * + * \parDescription
+ * Selects the source of WDT clock (fWDT).\n\n + * The selected value is configured to the \a WDTSEL bits of \a WDTCLKCR register. + * The watchdog timer counts at the frequency selected using this API. So the time for + * timeout or pre-warning of watchdog has to be calculated based on this selection. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_GetWdtClockFrequency() \n\n\n + */ +void XMC_SCU_CLOCK_SetWdtClockSource(const XMC_SCU_CLOCK_WDTCLKSRC_t source); + +/** + * @return XMC_SCU_CLOCK_WDTCLKSRC_t Clock source configured for watchdog timer.\n + * \b Range: Use type XMC_SCU_CLOCK_WDTCLKSRC_t to identify the clock source.\n + * XMC_SCU_CLOCK_WDTCLKSRC_OFI - internal fast oscillator (fOFI)\n + * XMC_SCU_CLOCK_WDTCLKSRC_STDBY - backup standby clock (fSTDBY)\n + * XMC_SCU_CLOCK_WDTCLKSRC_PLL - PLL output clock (fPLL) + * + * \parDescription
+ * Provides the source of clock used for watchdog timer.\n\n + * The value is obtained by reading \a WDTSEL bits of \a WDTCLKCR register. + * The time for timeout or pre-warning of watchdog has to be calculated based on + * the clock source selected. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetWdtClockSource() \n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_WDTCLKSRC_t XMC_SCU_CLOCK_GetWdtClockSource(void) +{ + return (XMC_SCU_CLOCK_WDTCLKSRC_t)(SCU_CLK->WDTCLKCR & SCU_CLK_WDTCLKCR_WDTSEL_Msk); +} + +/** + * + * @param source Source for standby clock.\n + * \b Range: Use type @ref XMC_SCU_HIB_STDBYCLKSRC_t to identify the clock source.\n + * XMC_SCU_HIB_STDBYCLKSRC_OSI - internal slow oscillator (fOSI) \n + * XMC_SCU_HIB_STDBYCLKSRC_OSCULP - ultra low power osciallator (fULP) \n + * + * @return None + * + * \parDescription
+ * Selects the source of Standby clock (fSTDBY).\n\n + * Clock source is configured by setting the \a STDBYSEL bits of \a HDCR register. + * Hibernate domain should be enabled explicitly before using the API. + * \parRelated APIs:
+ * XMC_SCU_HIB_GetStdbyClockSource(), XMC_SCU_HIB_EnableHibernateDomain() \n\n\n + */ +void XMC_SCU_HIB_SetStandbyClockSource(const XMC_SCU_HIB_STDBYCLKSRC_t source); + +/** + * @return XMC_SCU_HIB_RTCCLKSRC_t Source clock of standby clock(fSTDBY).\n + * \b Range: Use type @ref XMC_SCU_HIB_STDBYCLKSRC_t to identify the clock source.\n + * XMC_SCU_HIB_STDBYCLKSRC_OSI - internal slow oscillator (fOSI) \n + * XMC_SCU_HIB_STDBYCLKSRC_OSCULP - ultra low power osciallator (fULP) \n + * + * \parDescription
+ * Provides the source of standby clock (fSTDBY).\n\n + * The value is obtained by reading \a STDBYSEL bits of \a HDCR register.\n + * \parRelated APIs:
+ * XMC_SCU_HIB_SetStandbyClockSource(), XMC_SCU_HIB_EnableHibernateDomain() \n\n\n + */ +__STATIC_INLINE XMC_SCU_HIB_RTCCLKSRC_t XMC_SCU_HIB_GetStdbyClockSource(void) +{ + return (XMC_SCU_HIB_RTCCLKSRC_t)(SCU_HIBERNATE->HDCR & SCU_HIBERNATE_HDCR_STDBYSEL_Msk); +} + +/** + * + * @param source Source of RTC clock.\n + * \b Range: Use type @ref XMC_SCU_HIB_RTCCLKSRC_t to identify the clock source.\n + * XMC_SCU_HIB_RTCCLKSRC_OSI - internal slow oscillator(fOSI). \n + * XMC_SCU_HIB_RTCCLKSRC_ULP - ultra low power oscillator(fULP). \n + * + * @return None + * + * \parDescription
+ * Selects the source of RTC clock (fRTC).\n\n + * The value is configured to \a RCS bit of \a HDCR register. + * fULP needs external input powered by VBAT or VDDP. fOSI is internal clock. + * The frequency of the clock will be 32.768 kHz. + * \parRelated APIs:
+ * XMC_SCU_HIB_GetRtcClockSource() \n\n\n + */ +void XMC_SCU_HIB_SetRtcClockSource(const XMC_SCU_HIB_RTCCLKSRC_t source); + +/** + * @return XMC_SCU_HIB_RTCCLKSRC_t Source of RTC clock.\n + * \b Range: Use type @ref XMC_SCU_HIB_RTCCLKSRC_t to identify the clock source.\n + * XMC_SCU_HIB_RTCCLKSRC_OSI - internal slow oscillator(fOSI). \n + * XMC_SCU_HIB_RTCCLKSRC_ULP - ultra low power oscillator(fULP). \n + * + * \parDescription
+ * Provides the source of RTC clock (fRTC). + * The value is obtained by reading \a RCS bit of \a HDCR register. + * The frequency of the clock will be 32.768 kHz. + * \parRelated APIs:
+ * XMC_SCU_HIB_SetRtcClockSource() \n\n\n + */ +__STATIC_INLINE XMC_SCU_HIB_RTCCLKSRC_t XMC_SCU_HIB_GetRtcClockSource(void) +{ + return (XMC_SCU_HIB_RTCCLKSRC_t)(SCU_HIBERNATE->HDCR & SCU_HIBERNATE_HDCR_RCS_Msk); +} + +/** + * + * @param clock Source of external clock output(fEXT).\n + * \b Range: Use type @ref XMC_SCU_CLOCK_EXTOUTCLKSRC_t to identify the clock.\n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS - system clock fSYS. \n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_USB - USB clock fUSB. \n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL - PLL output fPLL. \n + * \if XMC42 + * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n + * + * \endif + * \if XMC41 + * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n + * \endif + * + * @return None + * + * \parDescription
+ * Selects the source of external clock out (fEXT).\n\n + * The value will be configured to \a ECKSEL bits of \a EXTCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetExternalOutputClockSource(const XMC_SCU_CLOCK_EXTOUTCLKSRC_t clock); + +/** + * @return XMC_SCU_CLOCK_EXTOUTCLKSRC_t Source of external clock output(fEXT).\n + * \b Range: Use type @ref XMC_SCU_CLOCK_EXTOUTCLKSRC_t to identify the clock.\n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS - system clock fSYS. \n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_USB - USB clock fUSB. \n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL - PLL output fPLL. \n + * \if XMC42 + * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n + * \endif + * \if XMC41 + * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n + * \endif + * + * \parDescription
+ * Provides the source of external clock output(fEXT).\n\n + * The value is obtained by reading \a ECKSEL bits of \a EXTCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider() \n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_EXTOUTCLKSRC_t XMC_SCU_CLOCK_GetExternalOutputClockSource(void) +{ + return (XMC_SCU_CLOCK_EXTOUTCLKSRC_t)(SCU_CLK->EXTCLKCR & SCU_CLK_EXTCLKCR_ECKSEL_Msk); +} + +/** + * + * @param source Source of clock for system PLL.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLLCLKSRC_t for identifying the clock source.\n + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP - External High performance oscillator(fOHP).\n + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI - Internal fast clock (fOFI). + * + * @return None + * + * \parDescription
+ * Selects the source of system PLL.\n\n + * The value is configured to \a VCOBYP bit of \a PLLCON0 register. + * If \a XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP is selected, ensure that the high performance oscillator is + * enabled by using the API XMC_SCU_CLOCK_EnableHighPerformanceOscillator(). + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillator()\n\n\n + */ +void XMC_SCU_CLOCK_SetSystemPllClockSource(const XMC_SCU_CLOCK_SYSPLLCLKSRC_t source); + +/** + * @return XMC_SCU_CLOCK_OSCCLKSRC_t Source of clock for system PLL.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLLCLKSRC_t for identifying the clock source.\n + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP - External High performance oscillator(fOHP).\n + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI - Internal fast clock (fOFI). + * + * \parDescription
+ * Provides the source of system PLL clock (fPLL). \n\n + * The value is obtained by reading \a VCOBYP bit of \a PLLCON0 register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_SetSystemPllClockSource()\n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_SYSPLLCLKSRC_t XMC_SCU_CLOCK_GetSystemPllClockSource(void) +{ + return (XMC_SCU_CLOCK_SYSPLLCLKSRC_t)(SCU_PLL->PLLCON0 & SCU_PLL_PLLCON0_VCOBYP_Msk); +} + +#if defined(ECAT0) +/** + * + * @param source Source of ECAT clock.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_ECATCLKSRC_t to identify the clock source.\n + * XMC_SCU_CLOCK_ECATCLKSRC_USBPLL - USB PLL (fUSBPLL) as a source for ECAT clock. \n + * XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL - Main PLL output (fPLL) as a source for ECAT clock. \n + * + * @return None + * + * \parDescription
+ * Selects the source of ECAT clock (fECAT).\n\n + * The value is configured to \a ECATSEL bit of \a ECATCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetECATClockSource() \n\n\n + */ +__STATIC_INLINE void XMC_SCU_CLOCK_SetECATClockSource(const XMC_SCU_CLOCK_ECATCLKSRC_t source) +{ + SCU_CLK->ECATCLKCR = (SCU_CLK->ECATCLKCR & ((uint32_t)~SCU_CLK_ECATCLKCR_ECATSEL_Msk)) | + ((uint32_t)source); +} + +/** + * @return XMC_SCU_CLOCK_ECATCLKSRC_t Source of ECAT clock.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_ECATCLKSRC_t to identify the clock source.\n + * XMC_SCU_CLOCK_ECATCLKSRC_USBPLL - USB PLL (fUSBPLL) as a source for ECAT clock. \n + * XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL - Main PLL output (fPLL) as a source for ECAT clock. \n + * + * \parDescription
+ * Provides the source of ECAT clock (fECAT). + * The value is obtained by reading \a ECATSEL bit of \a ECATCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_HIB_SetRtcClockSource() \n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_ECATCLKSRC_t XMC_SCU_CLOCK_GetECATClockSource(void) +{ + return (XMC_SCU_CLOCK_ECATCLKSRC_t)((SCU_CLK->ECATCLKCR & SCU_CLK_ECATCLKCR_ECATSEL_Msk) >> SCU_CLK_ECATCLKCR_ECATSEL_Pos); +} +#endif + +/** + * + * @param divider Ratio of fSYS clock source to the value of fSYS. + * \b Range: 1 to 256. + * + * @return None + * + * \parDescription
+ * Configures the ratio of system clock source to the value of system clock frequency.\n\n + * The value is configured as \a SYSDIV bits of \a SYSCLKCR register. The divider value is + * decremented by 1 before configuring. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemClockDivider(), XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n + */ +void XMC_SCU_CLOCK_SetSystemClockDivider(const uint32_t divider); + +/** + * @return uint32_t Ratio of fSYS clock source to the value of fSYS. + * \b Range: 0 to 255. + * + * \parDescription
+ * Provides the value of ratio between the source of system clock to the the value of system clock frequency. \n\n + * The value is obtained by reading \a SYSDIV bits of \a SYSCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSystemClockDivider(), XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetSystemClockDivider(void) +{ + return (uint32_t)((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) >> SCU_CLK_SYSCLKCR_SYSDIV_Pos); +} + +/** + * + * @param ratio Ratio of fCCU clock source to the value of fCCU. + * \b Range: 1 or 2.\n + * 1-> fCCU= fSYS \n + * 2-> fCCU= fSYS/2. + * + * @return None + * + * \parDescription
+ * Configures the divider for CCU clock source. \n\n + * Capture compare unit(CCU) can take either fSYS or fSYS/2 as the source of clock. + * The configuration is set to \a CCUDIV bit of \a CCUCLKCR register. The CCUDIV bit is 1 bit wide. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetCcuClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetCcuClockDivider(const uint32_t ratio); + +/** + * @return uint32_t Ratio of fCCU clock source to the value of fCCU. + * \b Range: 0 or 1.\n + * 0-> fCCU= fSYS \n + * 1-> fCCU= fSYS/2. + * + * \parDescription
+ * Provides the ratio of CCU clock(fCCU) to system clock(fSYS).\n\n + * The value is obtained by reading \a CCUDIV bit of \a CCUCLKCR register. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetCcuClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCcuClockDivider(void) +{ + return (uint32_t)((SCU_CLK->CCUCLKCR & SCU_CLK_CCUCLKCR_CCUDIV_Msk) >> SCU_CLK_CCUCLKCR_CCUDIV_Pos); +} + +/** + * + * @param ratio Ratio between system clock(fSYS) and CPU clock(fCPU). + * \b Range: 1 or 2.\n + * 1-> fCPU= fSYS. \n + * 2-> fCPU= fSYS/2. + * + * @return None + * + * \parDescription
+ * Configures the CPU clock by setting the divider value for the system clock. \n\n + * The value is set to the \a CPUDIV bit of \a CPUCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetCpuClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetCpuClockDivider(const uint32_t ratio); + +/** + * @return uint32_t Ratio between system clock(fSYS) and CPU clock(fCPU). + * \b Range: 0 or 1.\n + * 0-> fCPU= fSYS. \n + * 1-> fCPU= fSYS/2. + * + * \parDescription
+ * Provides the ratio between system clock(fSYS) and CPU clock(fCPU). \n\n + * The value is obtained by reading \a CPUDIV bit of \a CPUCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetCpuClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockDivider(void) +{ + return (uint32_t)((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) >> SCU_CLK_CPUCLKCR_CPUDIV_Pos); +} + +/** + * + * @param ratio Ratio of peripheral clock source to the value of peripheral clock.\n + * \b Range: 1 or 2.\n + * 1-> fPERIPH= fCPU.\n + * 2-> fPERIPH= fCPU/2. + * + * @return None + * + * \parDescription
+ * Configures the peripheral clock by setting the divider for CPU clock(fCPU).\n\n + * The peripheral clock can be equal to either fCPU or fCPU/2. The value is configured to \a PBDIV bit of \a PBCLKCR register. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetPeripheralClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetPeripheralClockDivider(const uint32_t ratio); + +/** + * @return uint32_t Ratio of peripheral clock source to the value of peripheral clock.\n + * \b Range: 0 or 1.\n + * 0-> fPERIPH= fCPU.\n + * 1-> fPERIPH= fCPU/2. + * + * \parDescription
+ * Provides the ratio of CPU clock(fCPU) to peripheral clock(fPERIPH).\n\n + * The value is obtained by reading \a PBDIV bit of \a PBCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetPeripheralClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetPeripheralClockDivider(void) +{ + return (uint32_t)((SCU_CLK->PBCLKCR & SCU_CLK_PBCLKCR_PBDIV_Msk) >> SCU_CLK_PBCLKCR_PBDIV_Pos); +} + +/** + * + * @param ratio Ratio of PLL output clock(fPLL) to USB clock(fUSB). + * \b Range: 1 to 8. + * + * @return None + * + * \parDescription
+ * Configures the USB clock(fUSB) by setting the USB clock divider. \n\n + * The value is decremented by 1 before setting it to \a USBDIV bits of \a USBCLKCR register. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetUsbClockDivider(), XMC_SCU_CLOCK_SetUsbClockSource() \n\n\n + */ +void XMC_SCU_CLOCK_SetUsbClockDivider(const uint32_t ratio); + +/** + * + * @return uint32_t Ratio of PLL output clock(fPLL) to USB clock(fUSB). + * \b Range: 0 to 7. + * + * \parDescription
+ * Provides the ratio between PLL output frequency(fPLL) and USB clock(fUSB).\n\n + * The value is obtained by reading \a USBDIV bit of \a USBCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbClockSource() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetUsbClockDivider(void) +{ + return (uint32_t)((SCU_CLK->USBCLKCR & SCU_CLK_USBCLKCR_USBDIV_Msk) >> SCU_CLK_USBCLKCR_USBDIV_Pos); +} + + + +#if defined(EBU) +/** + * + * @param ratio Ratio of PLL clock(fPLL) to EBU clock(fEBU).\n + * \b Range: 1 to 64. + * + * @return None + * + * \parDescription
+ * Configures the EBU clock(fEBU) by setting the divider value.\n\n + * The clock divider is configured to the \a EBUDIV bits of \a EBUCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetEbuClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetEbuClockDivider(const uint32_t ratio); + +/** + * + * @return uint32_t Ratio of PLL clock(fPLL) to EBU clock(fEBU).\n + * \b Range: 0 to 63. + * + * \parDescription
+ * Provides the ratio between PLL clock(fPLL) and EBU clock(fEBU).\n\n + * The value is obtained by reading \a EBUDIV bits of \a EBUCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetEbuClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetEbuClockDivider(void) +{ + return (uint32_t)((SCU_CLK->EBUCLKCR & SCU_CLK_EBUCLKCR_EBUDIV_Msk) >> SCU_CLK_EBUCLKCR_EBUDIV_Pos); +} +#endif + +/** + * + * @param ratio Ratio between the source of WDT clock and the WDT clock.\n + * \b Range: 1 to 256. + * + * @return None + * + * \parDescription
+ * Configures the WDT clock by setting the clock divider for the WDT clock source.\n\n + * The value is configured to \a WDTDIV bits of \a WDTCLKCR register. The value of divider + * is decremented by 1 before configuring. Check the selected clock source for the WDT clock + * before configuring the divider using the API XMC_SCU_CLOCK_SetWdtClockSource(). + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetWdtClockSource(), XMC_SCU_CLOCK_GetWdtClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetWdtClockDivider(const uint32_t ratio); + +/** + * + * @return uint32_t Ratio between the source of WDT clock and the WDT clock.\n + * \b Range: 0 to 255. + * + * \parDescription
+ * Provides the ratio between the WDT parent clock and the WDT clock. \n\n + * The value is obtained by reading \a WDTDIV bits of \a WDTCLKCR register. + * Ensure that the WDT parent clock is considered before using the value of + * the divider value. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetWdtClockSource(), XMC_SCU_CLOCK_SetWdtClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetWdtClockDivider(void) +{ + return (uint32_t)((SCU_CLK->WDTCLKCR & SCU_CLK_WDTCLKCR_WDTDIV_Msk) >> SCU_CLK_WDTCLKCR_WDTDIV_Pos); +} + +/** + * + * @param ratio Ratio between the external output parent clock selected and the output clock.\n + * \b Range: 1 to 512. + * + * @return None + * + * \parDescription
+ * Configures the external output clock by setting the divider value for the parent clock. \n\n + * The value will be configured to \a ECKDIV bits of \a EXTCLKCR register. + * The divider value is decremented by 1 before storing it to the bit fields. + * Ensure that the source of external output clock is configured appropriately using the API + * XMC_SCU_CLOCK_SetExternalOutputClockSource(). + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetExternalOutputClockSource(), XMC_SCU_CLOCK_GetExternalOutputClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetExternalOutputClockDivider(const uint32_t ratio); + +/** + * + * @return uint32_t Ratio between the external output parent clock selected and the output clock.\n + * \b Range: 0 to 511. + * + * \parDescription
+ * Provides the divider value applied on parent clock before the generation of external output clock. \n\n + * The value is obtained by reading \a EXTDIV bit of \a EXTCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetExternalOutputClockDivider(void) +{ + return (uint32_t)((SCU_CLK->EXTCLKCR & SCU_CLK_EXTCLKCR_ECKDIV_Msk) >> SCU_CLK_EXTCLKCR_ECKDIV_Pos); +} + +#if defined(ECAT0) +/** + * + * @param ratio Ratio between the source of ECAT clock and the ECAT clock.\n + * \b Range: 1 to 4. + * + * @return None + * + * \parDescription
+ * Configures the ECAT clock by setting the clock divider for the ECAT clock source.\n\n + * The value is configured to \a ECADIV bits of \a ECATCLKCR register. The value of divider + * is decremented by 1 before configuring. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetECATClockSource(), XMC_SCU_CLOCK_GetECATClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetECATClockDivider(const uint32_t divider); + +/** + * + * @return uint32_t Ratio between the source of ECAT clock and the ECAT clock.\n + * \b Range: 0 to 3. + * + * \parDescription
+ * Provides the ratio between the ECAT parent clock and the ECAT clock. \n\n + * The value is obtained by reading \a ECADIV bits of \a ECATCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetECATClockSource(), XMC_SCU_CLOCK_SetECATClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetECATClockDivider(void) +{ + return (uint32_t)((SCU_CLK->ECATCLKCR & SCU_CLK_ECATCLKCR_ECADIV_Msk) >> SCU_CLK_ECATCLKCR_ECADIV_Pos); +} +#endif + +/** + * + * @return None + * + * \parDescription
+ * Enables the high precision oscillator by configuring external crystal mode.\n\n + * The API configures \a MODE bits of \a OSCHPCTRL register to 0, there by configuring the + * external clock input. + * The System Oscillator Watchdog is enabled. The user should check the status + * of the oscillator using XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableHighPerformanceOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_EnableHighPerformanceOscillator(void); + +/** + * @return None + * + * \parDescription
+ * Disables the high precision oscillator by disabling the external oscillator.\n\n + * The API configures \a MODE bits of \a OSCHPCTRL register to 1, there by disabling the + * external oscillator. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_DisableHighPerformanceOscillator(void); + +/** + * + * @return Status of high performance oscillator + * + * \parDescription
+ * Checks if the OSC_HP oscillator is stable and usable + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillator() \n\n\n + */ +bool XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable(void); + +/** + * + * @return None + * + * \parDescription
+ * Enables XTAL1 input of OSC_ULP as general purpose input. + * Use XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus to monitor the status of OSC_HP XTAL1 pin. + * @Note OSC_ULP should be disabled previously using XMC_SCU_CLOCK_DisableHighPerformanceOscillator(). + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableHighPerformanceOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(void); + +/** + * + * @return None + * + * \parDescription
+ * Disables XTAL1 input of OSC_ULP as general purpose input. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput() \n\n\n + */ +void XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(void); + +/** + * + * @return Status OSC_HP XTAL1 pin + * + * \parDescription
+ * Monitor the status of OSC_HP XTAL1 pin. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus(void); + +/** + * + * @return None + * + * \parDescription
+ * Enables ultra low power oscillator(ULP). \n\n + * It enables the hibernate domain, configures the ultra low power oscillator + * uisng the \a MODE bits of the \a OSCULCTRL register. The \a Mode bits will be + * reset to 0 to enable the low power oscillator. Mirror register update delays + * are handled internally. + * The OSC_ULP Oscillator Watchdog is enabled. The user should check the status + * of the oscillator using XMC_SCU_CLOCK_IsLowPowerOscillatorStable() + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableLowPowerOscillator() + * XMC_SCU_CLOCK_IsLowPowerOscillatorStable() \n\n\n + */ +void XMC_SCU_CLOCK_EnableLowPowerOscillator(void); + +/** + * + * @return None + * + * \parDescription
+ * Disables ultra low power oscillator.\n\n + * It is disabled by setting the \a MODE bits of \a OSCULCTRL register to value 2. + * By default on power up, the ultra low power osciallator is disabled. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableLowPowerOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_DisableLowPowerOscillator(void); + +/** + * + * @return Status of low power oscillator + * + * \parDescription
+ * Checks if the OSC_ULP oscillator is stable and usable + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableLowPowerOscillator() \n\n\n + */ +bool XMC_SCU_CLOCK_IsLowPowerOscillatorStable(void); + +/** + * + * @return None + * + * \parDescription
+ * Enables XTAL1 input of OSC_ULP as general purpose input. + * Use XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus to monitor the status of OSC_ULP XTAL1 pin. + * @Note OSC_ULP should be disabled previously using XMC_SCU_CLOCK_DisableLowPowerOscillator(). + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableLowPowerOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(void); + +/** + * + * @return None + * + * \parDescription
+ * Disables XTAL1 input of OSC_ULP as general purpose input. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput() \n\n\n + */ +void XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(void); + +/** + * + * @return Status OSC_ULP XTAL1 pin + * + * \parDescription
+ * Monitor the status of OSC_ULP XTAL1 pin. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus(void); + +/** + * + * @return uint32_t System frequency in Hertz.\n + * \b Range: clock frequency in Hertz. Range of the value depends on the source clock frequency + * and the configured values of dividers. + * + * \parDescription
+ * Provides the value of system PLL output clock frequency(fPLL).\n\n + * The API uses \a N-DIV, \a P-DIV, \a K1-DIV, \a K2-DIV bits information from \a PLLCON1 register and + * VCOBYP bit information from \a PLLCON0 register. It calculates frequency of system pll clock using following formula: + * If normal Mode : fPLL = (fOSC * N)/(P * K2). + * If prescaler mode: fPLL = fOSC/ K1. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetSystemPllClockFrequency(void); + +/** + * + * @return uint32_t Source clock used for deriving system clock.\n + * \b Range: fOHP frequency if external high precision frequency is used. \n + * fOFI fast internal clock frequency. + * + * \parDescription
+ * Provides the value of the input clock frequency for deriving the system clock. + * The API retrieves frequency of system PLL input clock (fPLLin). + * Based on \a PINSEL bits information from \a PLLCON2 register, the parent clock source is obtained. + * This bit field specifies if fOHP or fOFI is used for deriving system clock. + * System clock frequency is obtained by dividing the source clock frequency with different divider values. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemPllClockFrequency() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency(void); + +/** + * + * @return uint32_t USB PLL output clock frequency. + * + * \parDescription
+ * Provides the frequency of USB PLL output clock (fUSBPLL).\n\n + * It obtains the \a VCOBYP bits information from \a USBPLLCON register and decides if USB PLL mode is used. + * If USB PLL mode is used, the USB clock frequency is obtained by dividing the source clock by USB PLL dividers.\n + * The frequency is obtained using following formula:\n + * If Normal Mode : fUSBPLL = (fOSC * N)/(P * 2).\n + * If Prescaler mode: fPLL = fOSC. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetUsbPllClockFrequency(void); + +/** + * + * @return uint32_t System clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of system clock (fSYS).\n\n + * The value obtained by dividing \a CPUDIV bits information of \a CPUCLKCR register with SystemCoreClock (fCPU) value.\n + * Based on these values, fSYS clock frequency is derived using the following formula:\n + * fSYS = fCPU << CPUDIV. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetUsbPllClockFrequency() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetSystemClockFrequency(void) +{ + return SystemCoreClock << ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) >> SCU_CLK_CPUCLKCR_CPUDIV_Pos); +} + + +/** + * + * @return uint32_t CCU clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of clock(fCPU) used for CCU4, CCU8, POSIF and HRPWM.\n\n + * The value is obtained from \a CCUDIV bits of \a CCUCLKCR register and system clock (fSYS) frequency. + * Based on these values, fCCU clock frequency is calculated using following formula:\n + * fCCU = fSYS >> CCUDIV.\n + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetCcuClockDivider(), XMC_SCU_CLOCK_GetSystemClockFrequency() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetCcuClockFrequency(void); + +/** + * @return uint32_t USB clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of USB and SDMMC clock(fUSB/fSDMMC).\n\n + * The value is obtained from \a USBDIV bits of \a USBCLKCR register and USB clock source. + * Based on these values fUSB/fSDMMC clock frequency is calculated using following formula:\n + * if USB clock source = USBPLL: fUSB/fSDMMC = fUSBPLL/(USBDIV + 1).\n + * if USB clock source = PLL: fUSB/fSDMMC = fPLL/(USBDIV + 1).\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetUsbClockSource(), XMC_SCU_CLOCK_GetUsbClockDivider() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetUsbClockFrequency(void); + +/** + * @return uint32_t Ethernet clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of Ethernet clock(fETH).\n\n + * The value is derived from system clock frequency(fSYS). It is calculated using + * the following formula:\n + * fETH = fSYS >> 1; + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemClockFrequency() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetEthernetClockFrequency(void) +{ + return XMC_SCU_CLOCK_GetSystemClockFrequency() >> 1U; +} + +#if defined(EBU) +/** + * @return uint32_t EBU clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of EBU clock(fEBU).\n\n + * The value is derived from system PLL clock frequency(fPLL) by applying the EBU divider. + * It is calculated using the following formula:\n + * fETH = fPLL /(EBUDIV+1) + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetEbuClockDivider(), XMC_SCU_CLOCK_GetSystemPllClockFrequency() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetEbuClockFrequency(void); +#endif + +/** + * @return uint32_t WDT clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of WDT clock(fWDT).\n\n + * The value is derived using \a WDTDIV bits of \a WDTCLKCR register and WDT clock source. + * Based on these values it is calculated using the following formula:\n + * if WDT clock source = PLL: fWDT = fUSBPLL/(WDTDIV + 1).\n + * if WDT clock source = OFI: fWDT = fOFI/(WDTDIV + 1).\n + * if WDT clock source = Standby: fWDT = fSTDBY/(WDTDIV + 1).\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetWdtClockSource(), XMC_SCU_CLOCK_GetWdtClockDivider() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetWdtClockFrequency(void); + +/** + * + * @return uint32_t External clock out frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of external output clock(fEXT).\n\n + * The value is derived using \a ECKDIV bits of \a EXCLKCR register and external clock out source. + * Based on these values, it is calculated using the following formula:\n + * if external clock out source = System clock: fEXT = fSYS.\n + * if external clock out source = PLL: fEXT = fPLL/(ECKDIV + 1).\n + * if external clock out source = USBPLL: fEXT = fUSBPLL/(ECKDIV + 1).\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetExternalOutputClockDivider(), XMC_SCU_CLOCK_GetExternalOutputClockSource() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetExternalOutputClockFrequency(void); + +#if defined(ECAT) +/** + * @return uint32_t ECAT clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of ECAT clock(fECAT).\n\n + * The value is derived using \a ECADIV bits of \a ECATCLKCR register and ECAT clock source. + * Based on these values it is calculated using the following formula:\n + * if ECAT clock source = PLL: fECAT = fPLL/(ECADIV + 1).\n + * if ECAT clock source = USBPLL: fECAT = fUSBPLL/(ECADIV + 1).\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetECATClockSource(), XMC_SCU_CLOCK_GetECATClockDivider() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetECATClockFrequency(void); +#endif + +/** + * @return None + * + * \parDescription
+ * Enables main PLL for system clock. \n\n + * System PLL is enabled by clearing the \a PLLPWD and \a VCOPWD bits of \a PLLCON0 register. + * By default the system PLL is in power saving mode. The API enables the PLL and the voltage + * controlled oscillator associated with it. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableSystemPll(), XMC_SCU_CLOCK_StartSystemPll() \n\n\n + */ +void XMC_SCU_CLOCK_EnableSystemPll(void); + + /** + * @return None + * + * \parDescription
+ * Disables main PLL for system clock. \n\n + * System PLL is disabled by setting the \a PLLPWD and \a VCOPWD bits of \a PLLCON0 register. + * By default the system PLL is in power saving mode. If the system PLL is explicitly enabled, + * the API disables the PLL and the voltage controlled oscillator(VCO) associated with it. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableSystemPll(), XMC_SCU_CLOCK_StopSystemPll() \n\n\n + */ + void XMC_SCU_CLOCK_DisableSystemPll(void); + +/** + * @param source PLL clock source. \n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLLCLKSRC_t to identify the clock source.\n + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP- External high precision oscillator input. + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI- Internal fast clock input. + * @param mode Mode of PLL operation.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLL_MODE_t to identify the PLL mode. \n + * XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL- PLL frequency obtained from output of VCO(fVCO).\n + * XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR- VCO is bypassed. Frequency obtained from fOSC.\n + * @param pdiv Input divider. Represents (PDIV+1) applied to external reference frequency. \n + * \b Range: 1 to 16.\n + * @param ndiv Feedback divider. Represents(NDIV+1) \n + * \b Range: 1 to 128. \n + * @param kdiv Output divider. Represents (K2DIV+1) in normal PLL mode or (K1DIV+1) in prescaler mode.\n + * \b Range: 1 to 128. \n + * @return None + * + * \parDescription
+ * Enables system PLL.\n\n + * Based on the selected source of clock, either external frequency fOHP or internal clock fOFI will be used. + * Based on the selected PLL mode, either voltage controlled oscillator(VCO) output(fVCO) or direct input frequency + * is used for the output dividers.\n + * The API implements the following sequence:\n + * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n + * - Clear all PLL related traps.\n + * - If external fOHP is selected as source, wait for the external oscillator to stabilize.\n + * - If PLL normal mode is selected, calculate the value of K2DIV and configure the PDIV, NDIV and K2DIV values.\n + * - Ramp up the PLL frequency in steps. \n + * - If prescaler mode is selected, configure the value of K1DIV.\n + * - Wait for LOCK.\n + * - Restore the trap configuration from stored temporary variable.\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemPllClockFrequency(), XMC_SCU_CLOCK_StopSystemPll() \n\n\n + */ +void XMC_SCU_CLOCK_StartSystemPll(XMC_SCU_CLOCK_SYSPLLCLKSRC_t source, + XMC_SCU_CLOCK_SYSPLL_MODE_t mode, + uint32_t pdiv, + uint32_t ndiv, + uint32_t kdiv); + +/** + * + * @return None + * + * \parDescription
+ * Disables the system PLL. + * PLL is placed in power saving mode. It disables the PLL by setting the \a PLLPWD bit of \a PLLCON0 register. + * If the PLL is put to power saving mode, it can no longer be used. + * It is recommended to ensure following steps before using \a XMC_SCU_CLOCK_StopSystemPll API:\n + * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n + * - Clear all PLL related traps.\n + * - Ramp down frequency until fPLL reaches backup clock frequency (fOFI).\n + * - Disable PLL.\n + * - Restore the trap configuration from stored temporary variable.\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemPllClockFrequency(), XMC_SCU_CLOCK_StartSystemPll() \n\n\n + */ +void XMC_SCU_CLOCK_StopSystemPll(void); + +/** + * @param kdiv PLL output divider K2DIV. \n + * \b Range: 1 to 128. Represents (K2DIV+1). + * @return None + * + * \parDescription
+ * Ramps up or ramps down the PLL output frequency in provided step. \n\n + * The PLL output frequency is divided by the \a kdiv value. This generates a step of ramp + * for the PLL output frequency. The API waits for the clock to stabilize before the completing its + * execution. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StartSystemPll() \n\n\n + */ +void XMC_SCU_CLOCK_StepSystemPllFrequency(uint32_t kdiv); + +/** + * @param None + * @return Boolean value indicating if System PLL is locked + * + * \parDescription
+ * Return status of System PLL VCO. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StartSystemPll() \n\n\n + */ +bool XMC_SCU_CLOCK_IsSystemPllLocked(void); + +/** + * @return None + * + * \parDescription
+ * Enables USB PLL for USB clock. \n\n + * USB PLL is enabled by clearing the \a PLLPWD and \a VCOPWD bits of \a USBPLLCON register. + * By default the USB PLL is in power saving mode. The API enables the PLL and the voltage + * controlled oscillator associated with it. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableUsbPll(), XMC_SCU_CLOCK_StartUsbPll() \n\n\n + */ + void XMC_SCU_CLOCK_EnableUsbPll(void); + + /** + * @return None + * + * \parDescription
+ * Disables USB PLL for USB clock. \n\n + * USB PLL is disabled by setting the \a PLLPWD and \a VCOPWD bits of \a USBPLLCON register. + * By default the USB PLL is in power saving mode. If the USB PLL is explicitly enabled, + * the API disables the PLL and the voltage controlled oscillator(VCO) associated with it. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableUsbPll(), XMC_SCU_CLOCK_StopUsbPll() \n\n\n + */ +void XMC_SCU_CLOCK_DisableUsbPll(void); + +/** + * + * @param pdiv Input divider value. Represents (PDIV+1) divider for the USB PLL.\n + * \b Range: 1 to 16. + * @param ndiv VCO feedback divider for USB PLL. Represents (NDIV+1) feedback divider.\n + * \b Range: 1 to 128. + * + * @return None + * + * \parDescription
+ * Configures USB PLL dividers and enables the PLL.\n\n + * The API follows the required sequence for safely configuring the divider values of USB PLL. + * Checks for PLL stabilization before enabling the same. After the configuring the dividers, + * it waits till the VCO lock is achieved. + * The sequence followed is as follows:\n + * - Enable the USB PLL and configure VCO to be bypassed.\n + * - Set up the HP oscillator clock input.\n + * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n + * - Clear all USBPLL related traps.\n + * - Disconnect the oscillator from USB PLL and configure the dividers PDIV and NDIV. \n + * - Connect the oscillator to USB PLL and enable VCO.\n + * - Wait for LOCK.\n + * - Restore the trap configuration from stored temporary variable.\n + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StopUsbPll() \n\n\n + */ +void XMC_SCU_CLOCK_StartUsbPll(uint32_t pdiv, uint32_t ndiv); + +/** + * + * @return None + * + * \parDescription
+ * Disables USB PLL operation.\n\n + * USB PLL is disabled by placing the USB PLL in power saving mode. The VCO and USB PLL are put in power saving mode + * by setting the \a PLLPWD bit and \a VCOPWD bit of \a USBLLCON register to 1. VCO bypass mode is enabled by setting the + * \a VCOBYP bit of \a USBLLCON register to 1. + * It is recommended to ensure following steps before using \a XMC_SCU_CLOCK_StopUsbPll API:\n + * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n + * - Clear all USBPLL related traps.\n + * - Ramp down frequency.\n + * - Disable PLL.\n + * - Restore the trap configuration from stored temporary variable.\n + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StartUsbPll() \n\n\n + */ +void XMC_SCU_CLOCK_StopUsbPll(void); + +/** + * @param None + * @return Boolean value indicating if USB PLL is locked + * + * \parDescription
+ * Return status of USB PLL VCO. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StartUsbPll() \n\n\n + */ +bool XMC_SCU_CLOCK_IsUsbPllLocked(void); + +/** + * @param mode Backup clock calibration mode.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t to identify the calibration mode.\n + * XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY- Force trimming of internal oscillator with firmware configured values.\n + * XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC- Calibrate internal oscillator automatically using standby clock(fSTDBY).\n + * + * @return None + * + * \parDescription
+ * Configures the calibration mode of internal oscillator.\n\n + * Based on the calibration mode selected, the internal oscillator calibration will be configured. + * The calibration is useful while using fast internal clock(fOFI). When factory mode calibration is used, + * the internal oscillator is trimmed using the firmware configured values. If automatic calibration is + * selected, the internal oscillator will be monitored using the backup clock. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n + */ +void XMC_SCU_CLOCK_SetBackupClockCalibrationMode(XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t mode); + +/** + * @param mode Low power mode\n + * @param sleep_on_exit Enter sleep, or deep sleep, on return from an ISR + * + * @return None + * + * \parDescription
+ * Enter selected low power mode and wait for interrupt + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSleepConfig(), XMC_SCU_CLOCK_SetDeepSleepConfig() \n\n\n + */ +__STATIC_INLINE void XMC_SCU_POWER_WaitForInterrupt(XMC_SCU_POWER_MODE_t mode, bool sleep_on_exit) +{ + SCB->SCR = mode | (sleep_on_exit ? SCB_SCR_SLEEPONEXIT_Msk : 0); + + __WFI(); +} + +/** + * @param mode Low power mode\n + * + * @return None + * + * \parDescription
+ * Enter selected low power mode and wait for event + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSleepConfig(), XMC_SCU_CLOCK_SetDeepSleepConfig() \n\n\n + */ +__STATIC_INLINE void XMC_SCU_POWER_WaitForEvent(XMC_SCU_POWER_MODE_t mode) +{ + SCB->SCR = mode | SCB_SCR_SEVONPEND_Msk; + + __WFE(); +} + +/** + * @param threshold Threshold value for comparison to VDDP for brownout detection. LSB33V is 22.5mV + * @param interval Interval value for comparison to VDDP expressed in cycles of system clock + * @return None + * + * Enable power monitoring control register for brown-out detection. + * Brown Out Trap need to be enabled using XMC_SCU_TRAP_Enable() and event handling done in NMI_Handler. + * + * \parRelated APIs:
+ * XMC_SCU_TRAP_Enable() \n\n\n + * + */ +__STATIC_INLINE void XMC_SCU_POWER_EnableMonitor(uint8_t threshold, uint8_t interval) +{ + SCU_POWER->PWRMON = SCU_POWER_PWRMON_ENB_Msk | + ((uint32_t)threshold << SCU_POWER_PWRMON_THRS_Pos) | + ((uint32_t)interval << SCU_POWER_PWRMON_INTV_Pos); +} + +/** + * @return None + * + * Disable power monitoring control register for brown-out detection. + * + */ +__STATIC_INLINE void XMC_SCU_POWER_DisableMonitor(void) +{ + SCU_POWER->PWRMON &= ~SCU_POWER_PWRMON_ENB_Msk; +} + +/** + * @return ::XMC_SCU_POWER_EVR_STATUS_t + * + * \parDescription
+ * Returns status of the EVR13. + * + */ +__STATIC_INLINE int32_t XMC_SCU_POWER_GetEVRStatus(void) +{ + return SCU_POWER->EVRSTAT; +} + +/** + * @return EVR13 voltage in volts + * + * \parDescription
+ * Returns EVR13 voltage in volts. + * + */ +float XMC_SCU_POWER_GetEVR13Voltage(void); + +/** + * @return EVR33 voltage in volts + * + * \parDescription
+ * Returns EVR33 voltage in volts + * + */ +float XMC_SCU_POWER_GetEVR33Voltage(void); + +/** + * @return None + * + * \parDescription
+ * Enables the USB PHY and also OTG comparator if available.\n\n + * Configures the \a USBPHYPDQ bit of \a PWRSET register to move the USB PHY from power down state. + * If USB OTG is available in the device, the \a USBOTGEN bit of \a PWRSET register is set to 1. This + * enables the USB on the go comparators. + * + * \parRelated APIs:
+ * XMC_SCU_POWER_DisableUsb(), XMC_SCU_CLOCK_SetUsbClockSource() \n\n\n + */ +void XMC_SCU_POWER_EnableUsb(void); + +/** + * @return None + * + * \parDescription
+ * Disables the USB PHY and also OTG comparator if available.\n\n + * Configures the \a USBPHYPDQ bit of \a PWRSET register to move the USB PHY to power down state. + * If USB OTG is available in the device, the \a USBOTGEN bit of \a PWRSET register is set to 0. This + * disables the USB on the go comparators. + * + * \parRelated APIs:
+ * XMC_SCU_POWER_EnableUsb(), XMC_SCU_CLOCK_SetUsbClockSource() \n\n\n + */ +void XMC_SCU_POWER_DisableUsb(void); + +/** + * @return None + * + * \parDescription
+ * Powers up the hibernation domain.\n\n + * Hibernate domain should be enabled before using any peripheral from the hibernate domain. + * It enables the power to the hibernate domain and moves it out of reset state. + * Power to hibernate domain is enabled by setting the \a HIB bit of \a PWRSET register only if it is currently powered down. + * The API will wait until HIB domain is enabled. If hibernate domain is in a state of reset, + * \a HIBRS bit of \a RSTCLR register is set to move it out of reset state.\n + * It is recommended to use following steps to verify whether a hibernation domain is enabled/disabled:\n + * - Call \a XMC_SCU_HIB_EnableHibernateDomain . + * - Call \a XMC_SCU_HIB_IsHibernateDomainEnabled and check the return value. If return value is true, it indicates + * that the hibernation domain is enabled otherwise disabled.\n + * \parRelated APIs:
+ * XMC_SCU_HIB_DisableHibernateDomain(), XMC_SCU_HIB_IsHibernateDomainEnabled() \n\n\n + */ +void XMC_SCU_HIB_EnableHibernateDomain(void); + +/** + * + * @return None + * + * \parDescription
+ * Powers down the hibernation domain.\n\n + * After disabling the hibernate domain, none of the peripherals from the hibernte domain can be used. + * Hibernate domain is disabled by setting the \a HIB bit of \a PWRCLR register and \ HIBRS bit of \a RSTSET register.\n + * It is recommended to use following steps to verify whether a hibernation domain is enabled/disabled:\n + * - Call \a XMC_SCU_HIB_DisableHibernateDomain . + * - Call \a XMC_SCU_HIB_IsHibernateDomainEnabled and check return value. If return value is true, it indicates + * that the hibernation domain is enabled otherwise disabled.\n + * \parRelated APIs:
+ * XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_IsHibernateDomainEnabled() \n\n\n + */ +void XMC_SCU_HIB_DisableHibernateDomain(void); + +/** + * + * @return bool Power status of hibernate domain.\n + * \b Range: Boolean state value.\n + * \a true if hibernate domain is enabled.\n + * \a false if hibernate domain is disabled.\n + * + * + * \parDescription
+ * Checks whether hibernation domain is enabled/disabled.\n\n + * The API can be used before using the peripherals from hibernation domain to ensure that the + * power is supplied to the peripherals and also that the hibernation domain is not in reset state. + * The status is obtained using the \a HIBEN bit of \a PWRSTAT register and \a HIBRS bit of \a RSTSET register. + * \parRelated APIs:
+ * XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain() \n\n\n + */ +bool XMC_SCU_HIB_IsHibernateDomainEnabled(void); + +/** + * @return ::XMC_SCU_HIB_CTRL_STATUS_t + * + * \parDescription
+ * Returns status of the external hibernate control. + * + */ +__STATIC_INLINE int32_t XMC_SCU_HIB_GetHibernateControlStatus(void) +{ + return (SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk); +} + +/** + * @return ::XMC_SCU_HIB_EVENT_t + * + * \parDescription
+ * Returns status of hibernate wakeup events. + * + */ +__STATIC_INLINE int32_t XMC_SCU_HIB_GetEventStatus(void) +{ + return SCU_HIBERNATE->HDSTAT; +} + +/** + * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t + * @return None + * + * \parDescription
+ * Clear hibernate wakeup event status + * + */ +void XMC_SCU_HIB_ClearEventStatus(int32_t event); + +/** + * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t + * @return None + * + * \parDescription
+ * Trigger hibernate wakeup event + * + */ +void XMC_SCU_HIB_TriggerEvent(int32_t event); + +/** + * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t + * @return None + * + * \parDescription
+ * Enable hibernate wakeup event source + * + */ +void XMC_SCU_HIB_EnableEvent(int32_t event); + +/** + * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t + * @return None + * + * \parDescription
+ * Disable hibernate wakeup event source + * + */ +void XMC_SCU_HIB_DisableEvent(int32_t event); + +/** + * @return None + * + * \parDescription
+ * Request enter external hibernate state + * + */ +void XMC_SCU_HIB_EnterHibernateState(void); + +/** + * @param mode hibernate mode ::XMC_SCU_HIB_HIBERNATE_MODE_t + * @return None + * + * \parDescription
+ * Request enter external hibernate state + * + */ +void XMC_SCU_HIB_EnterHibernateStateEx(XMC_SCU_HIB_HIBERNATE_MODE_t mode); + +/** + * @return Detection of a wakeup from hibernate mode + * + * \parDescription
+ * Detection of a wakeup from hibernate mode + */ +__STATIC_INLINE bool XMC_SCU_HIB_IsWakeupEventDetected(void) +{ + return ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBWK_Msk) != 0U); +} + +/** + * @return None + * + * \parDescription
+ * Clear detection status of wakeup from hibernate mode + */ +__STATIC_INLINE void XMC_SCU_HIB_ClearWakeupEventDetectionStatus(void) +{ + SCU_RESET->RSTCLR = SCU_RESET_RSTCLR_HIBWK_Msk; +} + +/** + * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t + * @return None + * + * \parDescription
+ * Selects input for Wake-Up from Hibernate + * + */ +void XMC_SCU_HIB_SetWakeupTriggerInput(XMC_SCU_HIB_IO_t pin); + +/** + * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t + * @param mode Hibernate domain dedicated pin mode ::XMC_SCU_HIB_PIN_MODE_t + * @return None + * + * \parDescription
+ * Selects mode of hibernate domain dedicated pins HIB_IOx + * + */ +void XMC_SCU_HIB_SetPinMode(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_PIN_MODE_t mode); + +/** + * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t + * @param level Output polarity of the hibernate domain dedicated pins HIB_IOx ::XMC_SCU_HIB_IO_OUTPUT_LEVEL_t + * @return None + * + * \parDescription
+ * Selects the output polarity of the hibernate domain dedicated pins HIB_IOx + * + */ +void XMC_SCU_HIB_SetPinOutputLevel(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_IO_OUTPUT_LEVEL_t level); + +/** + * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t + * @return None + * + * \parDescription
+ * Selects input to ERU0 module (HIB_SR0) that optionally can be used with software as a general purpose input. + * + * \parRelated APIs:
+ * XMC_SCU_HIB_SetSR0Input() + * + */ +void XMC_SCU_HIB_SetInput0(XMC_SCU_HIB_IO_t pin); + +/** + * @param input input signal HIB_SR0 of ERU0 + * @return None + * + * \parDescription
+ * Selects input to ERU0 module (HIB_SR0). + * + * \parRelated APIs:
+ * XMC_SCU_HIB_SetInput0() + * + */ +void XMC_SCU_HIB_SetSR0Input(XMC_SCU_HIB_SR0_INPUT_t input); + +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + +#if ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)) +/** + * @param input input signal HIB_SR1 of ERU0 + * @return None + * + * \parDescription
+ * Configures HIB_SR1 input to ERU0 module. + * @note Only available in XMC44 series and LQFP100 package + * + */ +void XMC_SCU_HIB_SetSR1Input(XMC_SCU_HIB_SR1_INPUT_t input); +#endif + +/** + * @param input LPAC compare input. Values from ::XMC_SCU_HIB_LPAC_INPUT_t can be ORed. + * @return None + * + * \parDescription
+ * Selects inputs to the LPAC comparator. Several inputs can be selected (time multiplexing). + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_SetInput(XMC_SCU_HIB_LPAC_INPUT_t input); + +/** + * @param trigger LPAC compare trigger + * @return None + * + * \parDescription
+ * Selects trigger mechanism to start a comparison. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_SetTrigger(XMC_SCU_HIB_LPAC_TRIGGER_t trigger); + +/** + * @param enable_delay Enable conversion delay + * @param interval_count compare interval (interval_count + 16) * 1/32768 (s) + * @param settle_count settleing time of LPAC after powered up (triggered) before measurement start (settle_count + 1) * 1/32768 (s) + * @return None + * + * \parDescription
+ * Configures timing behavior of comparator. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_SetTiming(bool enable_delay, uint16_t interval_count, uint8_t settle_count); + +/** + * @param low VBAT low threshold + * @param high VBAT high threshold + * @return None + * + * \parDescription
+ * Select compare thresholds for VBAT. + * After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards. + * Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements + * until it has been crossed downwards and the threshold values gets swapped again. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_SetVBATThresholds(uint8_t lower, uint8_t upper); + +/** + * @param low HIB_IO_0 low threshold + * @param high HIB_IO_0 high threshold + * @return None + * + * \parDescription
+ * Select compare thresholds for HIB_IO_0. + * After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards. + * Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements + * until it has been crossed downwards and the threshold values gets swapped again. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_SetHIBIO0Thresholds(uint8_t lower, uint8_t upper); + +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)) +/** + * @param low HIB_IO_1 low threshold + * @param high HIB_IO_1 high threshold + * @return None + * + * \parDescription
+ * Select compare thresholds for HIB_IO_1. + * After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards. + * Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements + * until it has been crossed downwards and the threshold values gets swapped again. + * @note Only available in XMC44 series and LQFP100 package + * + */ +void XMC_SCU_HIB_LPAC_SetHIBIO1Thresholds(uint8_t lower, uint8_t upper); +#endif + +/** + * @return HIB LPAC status ::XMC_SCU_HIB_LPAC_STATUS_t + * + * \parDescription
+ * Return status of HIB LPAC. + * @note Only available in XMC44, XMC42 and XMC41 series and in certain packages + * + */ +int32_t XMC_SCU_HIB_LPAC_GetStatus(void); + +/** + * @param status HIB LPAC status. Values from ::XMC_SCU_HIB_LPAC_STATUS_t can be ORed. + * @return None + * + * \parDescription
+ * Clear status of HIB LPAC. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_ClearStatus(int32_t status); + +/** + * @param input LPAC compare input. Values from ::XMC_SCU_HIB_LPAC_INPUT_t can be ORed. + * @return None + * + * \parDescription
+ * Trigger comparasion on the selected inputs. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_TriggerCompare(XMC_SCU_HIB_LPAC_INPUT_t input); + +#endif + +/** + * + * @return None + * + * \parDescription
+ * Enables slow internal oscillator(fOSI).\n\n + * By default on device power up, the slow internall oscillator is enabled. + * It can be disabled only if the external oscillator(fULP) is enabled and toggling. + * It is recommended to enable fOSI to prevent deadlock if fULP fails. + * fOSI is enabled by clearing the \a PWD bit of \a OSCSICTRL register. + * The API waits for the mirror register update of the configured register. + * The slow internal oscillator registers are in hibernate domain. + * Ensure that the hibernate domain is enabled before changing the configuration. + * \parRelated APIs:
+ * XMC_SCU_HIB_DisableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(), + * XMC_SCU_HIB_EnableHibernateDomain() \n\n\n + */ +void XMC_SCU_HIB_EnableInternalSlowClock(void); + +/** + * + * @return None + * + * \parDescription
+ * Disables slow internal oscillator(fOSI).\n\n + * By default on device power up, the slow internall oscillator is enabled. + * It can be disabled only if the external oscillator(fULP) is enabled and toggling. + * It is recommended to enable fOSI to prevent deadlock if fULP fails. + * fOSI is disabled by setting the \a PWD bit of \a OSCSICTRL register. + * The API waits for the mirror register update of the configured register. + * The slow internal oscillator registers are in hibernate domain. + * Ensure that the hibernate domain is enabled before changing the configuration. + * \parRelated APIs:
+ * XMC_SCU_HIB_EnableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(), + * XMC_SCU_HIB_EnableHibernateDomain() \n\n\n + */ +void XMC_SCU_HIB_DisableInternalSlowClock(void); + +/** + * @param config Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state. ::XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_t + * @return None + * + * \parDescription
+ * Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state. + * In addition the state of FLASH, PLL and PLLVCO during DEEPSLEEP state. + * Use this enum as parameter of XMC_SCU_CLOCK_SetDeepSleepConfig before going to DEEPSLEEP state. + * + * The DEEPSLEEP state of the system corresponds to the DEEPSLEEP state of the CPU. The state is + * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is + * stopped. + * + * In Deep Sleep state the OSC_HP and the PLL may be switched off. The wake-up logic in the NVIC is still clocked + * by a free-running clock. Peripherals are only clocked when configured to stay enabled. + * Configuration of peripherals and any SRAM content is preserved. + * The Flash module can be put into low-power mode to achieve a further power reduction. + * On wake-up Flash module will be restarted again before instructions or data access is possible. + * Any interrupt will bring the system back to operation via the NVIC.The clock setup before + * entering Deep Sleep state is restored upon wake-up. + * + * @usage + * @code + * // Configure system during SLEEP state + * XMC_SCU_CLOCK_SetDeepSleepConfig(XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI | + * XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_FLASH_POWERDOWN | + * XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN); + * + * // Make sure that SLEEPDEEP bit is set + * SCB->SCR |= SCB_SCR_DEEPSLEEP_Msk; + * + * // Return to SLEEP mode after handling the wakeup event + * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; + * + * // Put system in DEEPSLEEP state + * __WFI(); + * + * @endcode + * + *\parRelated APIs:
+ * XMC_SCU_CLOCK_Init() \n\n\n + * + */ +__STATIC_INLINE void XMC_SCU_CLOCK_SetDeepSleepConfig(int32_t config) +{ + SCU_CLK->DSLEEPCR = config; +} + +/** + * @param config Defines the source of the system clock and peripherals clock gating in SLEEP state. ::XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_t + * @return None + * + * \parDescription
+ * Defines the source of the system clock and peripherals clock gating in SLEEP state. + * + * The SLEEP state of the system corresponds to the SLEEP state of the CPU. The state is + * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is + * stopped. Peripherals are only clocked when configured to stay enabled. + * + * Peripherals can continue to operate unaffected and eventually generate an event to + * wake-up the CPU. Any interrupt to the NVIC will bring the CPU back to operation. The + * clock tree upon exit from SLEEP state is restored to what it was before entry into SLEEP + * state. + * + * @usage + * @code + * // Configure system during SLEEP state + * XMC_SCU_CLOCK_SetSleepConfig(XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI); + * + * // Make sure that SLEEPDEEP bit is cleared + * SCB->SCR &= ~ SCB_SCR_DEEPSLEEP_Msk; + * + * // Return to SLEEP mode after handling the wakeup event + * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; + * + * // Put system in SLEEP state + * __WFI(); + * + * @endcode + * + *\parRelated APIs:
+ * XMC_SCU_CLOCK_Init() \n\n\n + * + */ +__STATIC_INLINE void XMC_SCU_CLOCK_SetSleepConfig(int32_t config) +{ + SCU_CLK->SLEEPCR = config; +} + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* UC_FAMILY == XMC4 */ + +#endif /* XMC4_SCU_H */ + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_usic_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_usic_map.h new file mode 100644 index 00000000..93dc69be --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc4_usic_map.h @@ -0,0 +1,2021 @@ +/** + * @file xmc4_usic_map.h + * @date 2016-07-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial version + * + * 2015-08-25: + * - Added XMC4800 + * + * 2015-12-07: + * - Add XMC4300 support + * + * 2016-07-20: + * - Add missing USIC2_C1_DX0_P4_6,USIC1_C0_DX0_P1_14, USIC2_C0_DX0_P6_5, USIC2_C0_DX0_P9_4, USIC2_C1_DX1_P9_9, USIC2_C1_DX2_P9_8 for XMC47/48 BGA196 + * - Add missing USIC2_C1_DX0_P4_6, USIC1_C0_DX0_P1_14 for XMC47/48 LQFP100 + * - Add missing USIC2_C1_DX0_P4_6, USIC1_C0_DX0_P1_14, USIC2_C0_DX0_P6_5 for XMC47/48 LQFP144 + * + * @endcond + * + */ + +#ifndef XMC4_USIC_MAP_H +#define XMC4_USIC_MAP_H + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define USIC_INPUT_ALWAYS_1 7 + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX0_P8_8 4 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_P8_3 2 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_P8_1 2 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX0_P6_5 3 +#define USIC2_C0_DX0_P9_4 4 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_P9_1 2 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_P9_0 2 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX0_P4_6 4 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_P9_9 2 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_P9_8 2 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX0_P6_5 3 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX0_P4_6 4 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX0_P8_8 4 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_P8_3 2 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_P8_1 2 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX0_P6_5 3 +#define USIC2_C0_DX0_P9_4 4 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_P9_1 2 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_P9_0 2 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX0_P4_6 4 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_P9_9 2 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_P9_8 2 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX0_P6_5 3 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX0_P4_6 4 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + +#endif /* XMC4_USIC_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_can.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_can.h new file mode 100644 index 00000000..7e6048fd --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_can.h @@ -0,0 +1,2198 @@ +/** + * @file xmc_can.h + * @date 2016-06-07 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Documentation improved
+ * + * 2015-05-20: + * - New elements have added in XMC_CAN_MO_t data structure
+ * - XMC_CAN_MO_Config() signature has changed
+ * - XMC_CAN_STATUS_t enum structure has updated.
+ * + * 2015-06-20: + * - New APIs added: XMC_CAN_NODE_ClearStatus(),XMC_CAN_MO_ReceiveData(), XMC_CAN_GATEWAY_InitDesObject().
+ * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-07-09: + * - New API added: XMC_CAN_NODE_Enable.
+ * + * 2015-09-01: + * - Removed fCANB clock support
+ * + * 2015-09-15: + * - Added "xmc_can_map.h" include
+ * + * 2016-06-07: + * - Added XMC_CAN_IsPanelControlReady() + * + * Details of use for node configuration related APIs
+ * Please use the XMC_CAN_NODE_SetInitBit() and XMC_CAN_NODE_EnableConfigurationChange() before calling node configuration + * related APIs. + * XMC_CAN_NODE_DisableConfigurationChange() and XMC_CAN_NODE_ResetInitBit() can be called for disable the configuration + * change and enable the node for communication afterwards. + * Do not use this when configuring the nominal bit time with XMC_CAN_NODE_NominalBitTimeConfigure(). In this case the + * Enable/Disable node configuration change is taken in account. + * + * Example Usage: + * @code + * //disabling the Node + * XMC_CAN_NODE_SetInitBit(CAN_NODE0) + * //allowing the configuration change + * XMC_CAN_NODE_EnableConfigurationChange(CAN_NODE0) + * //Node configuration + * XMC_CAN_NODE_FrameCounterConfigure(CAN_NODE0,&can_node_frame_counter); + * XMC_CAN_NODE_EnableLoopBack(CAN_NODE0) + * //disable configuration + * XMC_CAN_NODE_DisableConfigurationChange(CAN_NODE0) + * //Enabling node for communication + * XMC_CAN_NODE_ResetInitBit(CAN_NODE0) + * @endcode + * + * 2016-06-20: + * - Fixed bug in XMC_CAN_MO_Config()
+ * @endcond + * + */ + +#ifndef XMC_CAN_H +#define XMC_CAN_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_common.h" + +#if defined(CAN) + +#include "xmc_scu.h" +#include "xmc_can_map.h" +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup CAN + * @brief Controller Area Network Controller (CAN) driver for the XMC microcontroller family. + * + * CAN driver provides transfer of CAN frames in accordance with CAN specificetion V2.0 B (active). Each CAN node + * can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. + * All CAN nodes share a common set of message objects. Each message object can be individually allocated to one of the + * CAN nodes. + * Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build + * gateways between + * the CAN nodes or to setup a FIFO buffer. The CAN module provides Analyzer mode,Loop-back mode and bit timming for + * node analysis. + * + * The driver is divided into five sections: + * \par CAN Global features: + * -# Allows to configure module frequency using function XMC_CAN_Init(). + * -# Allows to configure Module interrupt using configuration structure XMC_CAN_NODE_INTERRUPT_TRIGGER_t and function + * XMC_CAN_EventTrigger(). + * + * \par CAN_NODE features: + * -# Allows to set baud rate by configuration structure XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t and Baudrate Configuration + * function XMC_CAN_NODE_NominalBitTimeConfigure(). + * -# Allows to configure loop-back mode using fuction XMC_CAN_NODE_EnableLoopBack(). + * -# Allows to configure CAN Node analyzer using function XMC_CAN_NODE_SetAnalyzerMode(). + * -# Allows CAN node events enable/ disable by enum structure XMC_CAN_NODE_EVENT_t and functions XMC_CAN_NODE_EnableEvent() + * and XMC_CAN_NODE_DisableEvent(). + * -# Provides bit timming analysis, configuration structure XMC_CAN_NODE_FRAME_COUNTER_t and function + * XMC_CAN_NODE_FrameCounterConfigure(). + * + * \par CAN_MO features: + * -# Allows message object initialization by configuration structure XMC_CAN_MO_t and function XMC_CAN_MO_Config(). + * -# Allows transfer of message objects using functions XMC_CAN_MO_Transmit() and XMC_CAN_MO_Receive(). + * -# Allows to configure Single Data Transfer and Single Transmit Trial using functions + * XMC_CAN_MO_EnableSingleTransmitTrial() and XMC_CAN_MO_EnableSingleTransmitTrial(). + * -# Allows to configure MO events using function XMC_CAN_MO_EnableEvent(). + * + * \par CAN_FIFO features: + * -# Allows message object FIFO structure by configuration structure XMC_CAN_FIFO_CONFIG_t and functions + * XMC_CAN_TXFIFO_ConfigMOBaseObject() , XMC_CAN_RXFIFO_ConfigMOBaseObject() and XMC_CAN_TXFIFO_Transmit(). + * + * \par CAN_GATEWAY features: + * -# Provides Gateway mode, configuration structure XMC_CAN_GATEWAY_CONFIG_t and function XMC_CAN_GATEWAY_InitSourceObject(). + * + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_CAN_MO_MOAR_STDID_Pos (18U) /**< Standard Identifier bitposition */ + +#define XMC_CAN_MO_MOAR_STDID_Msk ((0x000007FFUL) << XMC_CAN_MO_MOAR_STDID_Pos) /**< Standard Identifier bitMask */ + +#define CAN_NODE_NIPR_Msk (0x7UL) /**< Node event mask */ + +#define CAN_MO_MOIPR_Msk (0x7U) /**< Message Object event mask */ + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +/** + * Defines the status of CAN, to verify the CAN related API calls. Use type \a XMC_CAN_STATUS_t for this enum. +*/ +typedef enum XMC_CAN_STATUS +{ + XMC_CAN_STATUS_SUCCESS, /**< Driver accepted application request*/ + XMC_CAN_STATUS_ERROR, /**< Returned when unknown error occurred */ + XMC_CAN_STATUS_BUSY, /**< Driver is busy and can not handle request*/ + XMC_CAN_STATUS_MO_NOT_ACCEPTABLE, /**< Message object type not allowed*/ + XMC_CAN_STATUS_MO_DISABLED /**< Returned if Message object is disabled */ +} XMC_CAN_STATUS_t; + +/** +* Defines CAN module Panel Commands . Use type \a XMC_CAN_PANCMD_t for this enum. +*/ +typedef enum XMC_CAN_PANCMD +{ + XMC_CAN_PANCMD_INIT_LIST = 1U, /**< Command to initialize a list */ + XMC_CAN_PANCMD_STATIC_ALLOCATE = 2U, /**< Command to activate static allocation */ + XMC_CAN_PANCMD_DYNAMIC_ALLOCATE = 3U, /**< Command to activate dynamic allocation */ + + XMC_CAN_PANCMD_STATIC_INSERT_BEFORE = 4U, /**< Remove a message object from the list and insert it before a given object.*/ + XMC_CAN_PANCMD_DYNAMIC_INSERT_BEFORE = 5U, /**< Command to activate dynamic allocation */ + XMC_CAN_PANCMD_STATIC_INSERT_BEHIND = 6U, /**< Command to activate dynamic allocation */ + XMC_CAN_PANCMD_DYNAMIC_INSERT_BEHIND = 7U /**< Command to activate dynamic allocation */ +} XMC_CAN_PANCMD_t; + +/** +* Defines loop Back Mode, to enable/disable an in-system test of the MultiCAN module . +* Use type \a XMC_CAN_LOOKBACKMODE_t for this enum. +*/ +typedef enum XMC_CAN_LOOKBACKMODE +{ + XMC_CAN_LOOKBACKMODE_ENABLED, /**< Each CAN node can be connected to the internal CAN bus */ + XMC_CAN_LOOKBACKMODE_DISABLED /**< Each CAN node can be connected to the external CAN bus */ +} XMC_CAN_LOOKBACKMODE_t; + +/** + * Defines Message Object direction. Use type \a XMC_CAN_MO_TYPE_t for this enum. + */ +typedef enum XMC_CAN_MO_TYPE +{ + XMC_CAN_MO_TYPE_RECMSGOBJ, /**< Receive Message Object selected */ + XMC_CAN_MO_TYPE_TRANSMSGOBJ /**< Transmit Message Object selected */ +} XMC_CAN_MO_TYPE_t; + +/** + * Defines Data frame types. Use type \a XMC_CAN_FRAME_TYPE_t for this enum. + */ +typedef enum XMC_CAN_FRAME_TYPE +{ + XMC_CAN_FRAME_TYPE_STANDARD_11BITS, /**< Standard type identifier*/ + XMC_CAN_FRAME_TYPE_EXTENDED_29BITS /**< Extended type identifier*/ +} XMC_CAN_FRAME_TYPE_t; + + +/** + * Defines arbitration mode for transmit acceptance filtering. Use type \a XMC_CAN_ARBITRATION_MODE_t for this enum. + */ +typedef enum XMC_CAN_ARBITRATION_MODE +{ + XMC_CAN_ARBITRATION_MODE_ORDER_BASED_PRIO_1 = 1U, /**< Transmit acceptance based in the order(prio) */ + XMC_CAN_ARBITRATION_MODE_IDE_DIR_BASED_PRIO_2 = 2U, /**< Transmit acceptance filtering is based on the CAN identifier */ + XMC_CAN_ARBITRATION_MODE_ORDER_BASED_PRIO_3 = 3U /**< Transmit acceptance based in the order */ +} XMC_CAN_ARBITRATION_MODE_t; + +/** + * Defines the operation mode of the frame counter. Use type \a XMC_CAN_FRAME_COUNT_MODE_t for this enum. + */ +typedef enum XMC_CAN_FRAME_COUNT_MODE +{ + XMC_CAN_FRAME_COUNT_MODE = 0U, /**< Frame Count Mode */ + XMC_CAN_FRAME_COUNT_MODE_TIME_STAMP = 1U, /**< The frame counter is incremented with the beginning of a new bit time*/ + XMC_CAN_FRAME_COUNT_MODE_BIT_TIMING = 2U /**< Used for baud rate detection and analysis of the bit timing */ +} XMC_CAN_FRAME_COUNT_MODE_t; + +/** + * Defines the Divider Modes. Use type \a XMC_CAN_DM_t for this enum. + */ +typedef enum XMC_CAN_DM +{ + XMC_CAN_DM_NORMAL = 1U, /**< Normal divider mode */ + XMC_CAN_DM_FRACTIONAL = 2U, /**< Fractional divider mode */ + XMC_CAN_DM_OFF = 3U /**< Divider Mode in off-state*/ +} XMC_CAN_DM_t; + +/** + * Defines mask value for CAN Message Object set status. Use type \a XMC_CAN_MO_SET_STATUS_t for this enum. + */ +typedef enum XMC_CAN_MO_SET_STATUS +{ + XMC_CAN_MO_SET_STATUS_RX_PENDING = CAN_MO_MOCTR_SETRXPND_Msk, /**< Set receive pending */ + XMC_CAN_MO_SET_STATUS_TX_PENDING = CAN_MO_MOCTR_SETTXPND_Msk, /**< Set transmit pending */ + XMC_CAN_MO_SET_STATUS_RX_UPDATING = CAN_MO_MOCTR_SETRXUPD_Msk, /**< Set receive updating */ + XMC_CAN_MO_SET_STATUS_NEW_DATA = CAN_MO_MOCTR_SETNEWDAT_Msk, /**< Set new data */ + XMC_CAN_MO_SET_STATUS_MESSAGE_LOST = CAN_MO_MOCTR_SETMSGLST_Msk, /**< Set message lost */ + XMC_CAN_MO_SET_STATUS_MESSAGE_VALID = CAN_MO_MOCTR_SETMSGVAL_Msk, /**< Set message valid */ + XMC_CAN_MO_SET_STATUS_RX_TX_SELECTED = CAN_MO_MOCTR_SETRTSEL_Msk, /**< Set transmit/receive selected */ + XMC_CAN_MO_SET_STATUS_RX_ENABLE = CAN_MO_MOCTR_SETRXEN_Msk, /**< Set receive enable */ + XMC_CAN_MO_SET_STATUS_TX_REQUEST = CAN_MO_MOCTR_SETTXRQ_Msk, /**< Set transmit request */ + XMC_CAN_MO_SET_STATUS_TX_ENABLE0 = CAN_MO_MOCTR_SETTXEN0_Msk, /**< Set transmit enable 0 */ + XMC_CAN_MO_SET_STATUS_TX_ENABLE1 = CAN_MO_MOCTR_SETTXEN1_Msk, /**< Set transmit enable 1 */ + XMC_CAN_MO_SET_STATUS_MESSAGE_DIRECTION = CAN_MO_MOCTR_SETDIR_Msk /**< Set message direction */ +} XMC_CAN_MO_SET_STATUS_t; + +/** + * Defines mask value for CAN Message Object reset status. Use type \a XMC_CAN_MO_RESET_STATUS_t for this enum. + */ +typedef enum XMC_CAN_MO_RESET_STATUS +{ + XMC_CAN_MO_RESET_STATUS_RX_PENDING = CAN_MO_MOCTR_RESRXPND_Msk, /**< Reset receive pending */ + XMC_CAN_MO_RESET_STATUS_TX_PENDING = CAN_MO_MOCTR_RESTXPND_Msk, /**< Reset transmit pending */ + XMC_CAN_MO_RESET_STATUS_RX_UPDATING = CAN_MO_MOCTR_RESRXUPD_Msk, /**< Reset receive updating */ + XMC_CAN_MO_RESET_STATUS_NEW_DATA = CAN_MO_MOCTR_RESNEWDAT_Msk, /**< Reset new data */ + XMC_CAN_MO_RESET_STATUS_MESSAGE_LOST = CAN_MO_MOCTR_RESMSGLST_Msk, /**< Reset message lost */ + XMC_CAN_MO_RESET_STATUS_MESSAGE_VALID = CAN_MO_MOCTR_RESMSGVAL_Msk, /**< Reset message valid */ + XMC_CAN_MO_RESET_STATUS_RX_TX_SELECTED = CAN_MO_MOCTR_RESRTSEL_Msk, /**< Reset transmit/receive selected */ + XMC_CAN_MO_RESET_STATUS_RX_ENABLE = CAN_MO_MOCTR_RESRXEN_Msk, /**< Reset receive enable */ + XMC_CAN_MO_RESET_STATUS_TX_REQUEST = CAN_MO_MOCTR_RESTXRQ_Msk, /**< Reset transmit request */ + XMC_CAN_MO_RESET_STATUS_TX_ENABLE0 = CAN_MO_MOCTR_RESTXEN0_Msk, /**< Reset transmit enable 0 */ + XMC_CAN_MO_RESET_STATUS_TX_ENABLE1 = CAN_MO_MOCTR_RESTXEN1_Msk, /**< Reset transmit enable 1 */ + XMC_CAN_MO_RESET_STATUS_MESSAGE_DIRECTION = CAN_MO_MOCTR_RESDIR_Msk /**< Reset message direction */ +} XMC_CAN_MO_RESET_STATUS_t; + +/** + * Defines mask value for CAN Message Object status. Use type \a XMC_CAN_MO_STATUS_t for this enum. + */ +typedef enum XMC_CAN_MO_STATUS +{ + XMC_CAN_MO_STATUS_RX_PENDING = CAN_MO_MOSTAT_RXPND_Msk, /**< Defines message has been successfully received or not received */ + XMC_CAN_MO_STATUS_TX_PENDING = CAN_MO_MOSTAT_TXPND_Msk, /**< Defines message has been successfully transmitted or not transmitted */ + XMC_CAN_MO_STATUS_RX_UPDATING = CAN_MO_MOSTAT_RXUPD_Msk, /**< Defines Message identifier, DLC, and data of the message object are currently updated or not updated */ + XMC_CAN_MO_STATUS_NEW_DATA = CAN_MO_MOSTAT_NEWDAT_Msk, /**< Defines no update of the message object since last flag reset or Message object has been updated */ + XMC_CAN_MO_STATUS_MESSAGE_LOST = CAN_MO_MOSTAT_MSGLST_Msk, /**< CAN message is lost because NEWDAT has become set again when it has already been set or No CAN message is lost */ + XMC_CAN_MO_STATUS_MESSAGE_VALID = CAN_MO_MOSTAT_MSGVAL_Msk, /**< Message valid */ + XMC_CAN_MO_STATUS_RX_TX_SELECTED = CAN_MO_MOSTAT_RTSEL_Msk, /**< Transmit/Receive selected */ + XMC_CAN_MO_STATUS_RX_ENABLE = CAN_MO_MOSTAT_RXEN_Msk, /**< Receive enable */ + XMC_CAN_MO_STATUS_TX_REQUEST = CAN_MO_MOSTAT_TXRQ_Msk, /**< Transmit request */ + XMC_CAN_MO_STATUS_TX_ENABLE0 = CAN_MO_MOSTAT_TXEN0_Msk, /**< Transmit enable 0 */ + XMC_CAN_MO_STATUS_TX_ENABLE1 = CAN_MO_MOSTAT_TXEN1_Msk, /**< Transmit enable 1 */ + XMC_CAN_MO_STATUS_MESSAGE_DIRECTION = CAN_MO_MOSTAT_DIR_Msk, /**< Message direction */ + XMC_CAN_MO_STATUS_LIST = CAN_MO_MOSTAT_LIST_Msk, /**< List allocation */ + XMC_CAN_MO_STATUS_POINTER_TO_PREVIOUS_MO = CAN_MO_MOSTAT_PPREV_Msk, /**< Pointer to previous Message Object */ + XMC_CAN_MO_STATUS_POINTER_TO_NEXT_MO = (int32_t)CAN_MO_MOSTAT_PNEXT_Msk /**< Pointer to next Message Object */ +} XMC_CAN_MO_STATUS_t; + +/** + * Defines mask value for CAN Node status. Use type \a XMC_CAN_NODE_STATUS_t for this enum. + */ +typedef enum XMC_CAN_NODE_STATUS +{ + XMC_CAN_NODE_STATUS_LAST_ERROR_CODE = CAN_NODE_NSR_LEC_Msk, /**< Last Error Code */ + XMC_CAN_NODE_STATUS_TX_OK = CAN_NODE_NSR_TXOK_Msk, /**< Message transmitted successfully */ + XMC_CAN_NODE_STATUS_RX_OK = CAN_NODE_NSR_RXOK_Msk, /**< Message received successfully */ + XMC_CAN_NODE_STATUS_ALERT_WARNING = CAN_NODE_NSR_ALERT_Msk, /**< Alert warning */ + XMC_CAN_NODE_STATUS_ERROR_WARNING_STATUS = CAN_NODE_NSR_EWRN_Msk, /**< Error warning status */ + XMC_CAN_NODE_STATUS_BUS_OFF= CAN_NODE_NSR_BOFF_Msk, /**< Bus-off status */ + XMC_CAN_NODE_STATUS_LIST_LENGTH_ERROR = CAN_NODE_NSR_LLE_Msk, /**< List length error */ + XMC_CAN_NODE_STATUS_LIST_OBJECT_ERROR = CAN_NODE_NSR_LOE_Msk, /**< List object error */ +#if !defined(MULTICAN_PLUS) + XMC_CAN_NODE_STATUS_SUSPENDED_ACK = CAN_NODE_NSR_SUSACK_Msk /**< Suspend Acknowledge */ +#endif +} XMC_CAN_NODE_STATUS_t; + +/** + * Defines mask value for CAN Node control like initialization, node disable and analyzer mode . + * Use type \a XMC_CAN_NODE_CONTROL_t for this enum. + */ +typedef enum XMC_CAN_NODE_CONTROL +{ + XMC_CAN_NODE_CONTROL_NODE_INIT = CAN_NODE_NCR_INIT_Msk, /**< Node initialization */ + XMC_CAN_NODE_CONTROL_TX_INT_ENABLE = CAN_NODE_NCR_TRIE_Msk, /**< Transfer event enable */ + XMC_CAN_NODE_CONTROL_LEC_INT_ENABLE = CAN_NODE_NCR_LECIE_Msk, /**< LEC Indicated Error Event Enable */ + XMC_CAN_NODE_CONTROL_ALERT_INT_ENABLE = CAN_NODE_NCR_ALIE_Msk, /**< Alert Event Enable */ + XMC_CAN_NODE_CONTROL_CAN_DISABLE = CAN_NODE_NCR_CANDIS_Msk, /**< CAN disable */ + XMC_CAN_NODE_CONTROL_CONF_CHANGE_ENABLE= CAN_NODE_NCR_CCE_Msk, /**< Configuration change enable */ + XMC_CAN_NODE_CONTROL_CAN_ANALYZER_NODEDE = CAN_NODE_NCR_CALM_Msk, /**< CAN Analyzer mode */ +#if !defined(MULTICAN_PLUS) + XMC_CAN_NODE_CONTROL_SUSPENDED_ENABLE = CAN_NODE_NCR_SUSEN_Msk /**< Suspend Enable */ +#endif +} XMC_CAN_NODE_CONTROL_t; + +/** + * Defines mask value for CAN Node events. Use type \a XMC_CAN_NODE_EVENT_t for this enum. + */ +typedef enum XMC_CAN_NODE_EVENT +{ + XMC_CAN_NODE_EVENT_TX_INT = CAN_NODE_NCR_TRIE_Msk, /**< Node Transfer OK Event */ + XMC_CAN_NODE_EVENT_ALERT = CAN_NODE_NCR_ALIE_Msk, /**< Node Alert Event */ + XMC_CAN_NODE_EVENT_LEC = CAN_NODE_NCR_LECIE_Msk, /**< Last Error code Event */ + XMC_CAN_NODE_EVENT_CFCIE = CAN_NODE_NFCR_CFCIE_Msk /**< CAN Frame Count Event */ +} XMC_CAN_NODE_EVENT_t; + +/** + * Defines mask value for CAN node pointer events position. Use type \a XMC_CAN_NODE_POINTER_EVENT_t for this enum. + */ +typedef enum XMC_CAN_NODE_POINTER_EVENT +{ + XMC_CAN_NODE_POINTER_EVENT_ALERT = CAN_NODE_NIPR_ALINP_Pos, /**< Node Alert Event node pointer */ + XMC_CAN_NODE_POINTER_EVENT_LEC = CAN_NODE_NIPR_LECINP_Pos, /**< Last Error code Event node pointer */ + XMC_CAN_NODE_POINTER_EVENT_TRANSFER_OK = CAN_NODE_NIPR_TRINP_Pos, /**< Transmit Event node pointer */ + XMC_CAN_NODE_POINTER_EVENT_FRAME_COUNTER = CAN_NODE_NIPR_CFCINP_Pos /**< CAN Frame Count Event node pointer */ +} XMC_CAN_NODE_POINTER_EVENT_t; + +/** + * Defines CAN Message Object event node pointer position. Use type \a XMC_CAN_MO_POINTER_EVENT_t for this enum. + */ +typedef enum XMC_CAN_MO_POINTER_EVENT +{ + XMC_CAN_MO_POINTER_EVENT_TRANSMIT = CAN_MO_MOIPR_TXINP_Pos, /**< Transmit Event node pointer */ + XMC_CAN_MO_POINTER_EVENT_RECEIVE = CAN_MO_MOIPR_RXINP_Pos /**< Receive Event node pointer */ +} XMC_CAN_MO_POINTER_EVENT_t; + +/** + * Defines mask value for CAN Message Object event type. Use type \a XMC_CAN_MO_EVENT_t for this enum. + */ +typedef enum XMC_CAN_MO_EVENT +{ + XMC_CAN_MO_EVENT_TRANSMIT = CAN_MO_MOFCR_TXIE_Msk, /**< Message Object transmit event */ + XMC_CAN_MO_EVENT_RECEIVE = CAN_MO_MOFCR_RXIE_Msk, /**< Message Object receive event */ + XMC_CAN_MO_EVENT_OVERFLOW = CAN_MO_MOFCR_OVIE_Msk, /**< Message Object overflow event */ +} XMC_CAN_MO_EVENT_t; + +/** + * Defines the possible receive inputs. Use type \a XMC_CAN_NODE_RECEIVE_INPUT_t for this enum. + */ +typedef enum XMC_CAN_NODE_RECEIVE_INPUT +{ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCA, /**< CAN Receive Input A */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCB, /**< CAN Receive Input B */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCC, /**< CAN Receive Input C */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCD, /**< CAN Receive Input D */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCE, /**< CAN Receive Input E */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCF, /**< CAN Receive Input F */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCG, /**< CAN Receive Input G */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCH /**< CAN Receive Input H */ +} XMC_CAN_NODE_RECEIVE_INPUT_t; + +/** + * Defines last error transfer direction. Use type \a XMC_CAN_NODE_LAST_ERROR_DIR_t for this enum. + */ +typedef enum XMC_CAN_NODE_LAST_ERROR_DIR +{ + XMC_CAN_NODE_LAST_ERROR_DIR_WHILE_NODE_RECEPCION, /**< The last error occurred while the CAN node x was receiver */ + XMC_CAN_NODE_LAST_ERROR_DIR_WHILE_NODE_TRANSMISSION /**< The last error occurred while the CAN node x was transmitter */ +} XMC_CAN_NODE_LAST_ERROR_DIR_t; + + +/** + * Defines last error increment. Use type \a XMC_CAN_NODE_LAST_ERROR_INC_t for this enum. + */ +typedef enum XMC_CAN_NODE_LAST_ERROR_INC +{ + XMC_CAN_NODE_LAST_ERROR_INC_1, /**< The last error led to an error counter increment of 1. */ + XMC_CAN_NODE_LAST_ERROR_INC_8 /**< The last error led to an error counter increment of 8. */ +} XMC_CAN_NODE_LAST_ERROR_INC_t; + +/** + * Defines interrupt request on interrupt output line INT_O[n]. Use type \a XMC_CAN_NODE_INTERRUPT_TRIGGER_t for this enum. + */ +typedef enum XMC_CAN_NODE_INTERRUPT_TRIGGER +{ + XMC_CAN_NODE_INTR_TRIGGER_0 = 0x1U, + XMC_CAN_NODE_INTR_TRIGGER_1 = 0x2U, + XMC_CAN_NODE_INTR_TRIGGER_2 = 0x4U, + XMC_CAN_NODE_INTR_TRIGGER_3 = 0x8U, + XMC_CAN_NODE_INTR_TRIGGER_4 = 0x16U, + XMC_CAN_NODE_INTR_TRIGGER_5 = 0x32U, + XMC_CAN_NODE_INTR_TRIGGER_6 = 0x64U, + XMC_CAN_NODE_INTR_TRIGGER_7 = 0x128U, +} XMC_CAN_NODE_INTERRUPT_TRIGGER_t; + +#if defined(MULTICAN_PLUS) || defined(DOXYGEN) +/** + * Defines the Clock source used for the MCAN peripheral. @note Only available for XMC1400, XMC4800 and XMC4700 series + */ +typedef enum XMC_CAN_CANCLKSRC +{ +#if UC_FAMILY == XMC4 + XMC_CAN_CANCLKSRC_FPERI = 0x1U, + XMC_CAN_CANCLKSRC_FOHP = 0x2U, +#else + XMC_CAN_CANCLKSRC_MCLK = 0x1U, + XMC_CAN_CANCLKSRC_FOHP = 0x2U +#endif +} XMC_CAN_CANCLKSRC_t; +#endif + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ +/** + * Defines CAN node Nominal Bit Time. Use type \a XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t for this structure. +*/ +typedef struct XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG +{ + uint32_t can_frequency; /**< Frequency of the CAN module(fCAN). \a can_frequency shall be range of 5MHz to 120MHz */ + uint32_t baudrate; /**< Specifies the node baud rate. Unit: baud \a baudrate shall be range of 100Kbps to 1000Kbps*/ + uint16_t sample_point; /**< Sample point is used to compensate mismatch between transmitter and receiver clock phases detected in + the synchronization segment. Sample point. Range = [0, 10000] with respect [0%, 100%] of the total bit time.*/ + uint16_t sjw; /**< (Re) Synchronization Jump Width. Range:0-3 */ +} XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t; + +/** + * Defines base, top and bottom of CAN Message Object FIFO Structure. Use type \a XMC_CAN_FIFO_CONFIG_t for this structure. + * A FIFO consists of one base object and n slave objects. + */ +typedef struct XMC_CAN_FIFO_CONFIG +{ + uint8_t fifo_bottom; /**< points to the first element(slave object) in a FIFO structure.Range :0-63*/ + uint8_t fifo_top; /**< points to the last element(slave object) in a FIFO structure. Range :0-63*/ + uint8_t fifo_base; /**< points to the actual target object(Base object) within a FIFO/Gateway structure. Range :0-63*/ +} XMC_CAN_FIFO_CONFIG_t; + +/** + * Defines CAN Gateway FIFO structure and provides additional options for gateway destination object. + * Use type \a XMC_CAN_GATEWAY_CONFIG_t for this structure. + */ +typedef struct XMC_CAN_GATEWAY_CONFIG +{ + uint8_t gateway_bottom; /**< points to the first element(gateway destination object) in a FIFO structure. Range :0-63*/ + uint8_t gateway_top; /**< points to the last element(gateway destination object) in a FIFO structure. Range :0-63*/ + uint8_t gateway_base; /**< points to the actual target object within a FIFO/Gateway structure. Range :0-63*/ + bool gateway_data_frame_send; /**< TXRQ updated in the gateway destination object after the internal transfer from the gateway source + to the gateway destination object */ + bool gateway_identifier_copy; /**< The identifier of the gateway source object (after storing the received frame in the source) is copied + to the gateway destination object. */ + + bool gateway_data_length_code_copy; /**< Data length code of the gateway source object (after storing the received frame in the source) is copied to the + gateway destination object */ + bool gateway_data_copy; /**< Data fields in registers MODATALn and MODATAHn of the gateway source object (after storing the received frame in the source) + are copied to the gateway destination.*/ + +} XMC_CAN_GATEWAY_CONFIG_t; + +/** +* Defines CAN Global Initialization structure +*/ +typedef CAN_GLOBAL_TypeDef XMC_CAN_t; + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Defines frame counter configuration. Use type \a XMC_CAN_NODE_FRAME_COUNTER_t for this structure. + * It provides configuration of frame counter that counts transmitted/received CAN frames or obtains information about the time + * when a frame has been started to transmit or be received by the CAN node. +*/ +typedef struct XMC_CAN_NODE_FRAME_COUNTER +{ + + union{ + struct{ + uint32_t : 16; + uint32_t can_frame_count_selection:3; /**< Defines function of the frame counter */ + uint32_t can_frame_count_mode:2; /**< Determines the operation mode of the frame counter */ + uint32_t : 11; + }; + uint32_t nfcr; + + }; +} XMC_CAN_NODE_FRAME_COUNTER_t; + +/** + *Defines Node Runtime structure. +*/ +typedef CAN_NODE_TypeDef XMC_CAN_NODE_t; /**< pointer to the Node CAN register */ + +/** + * Defines CAN Message Object runtime elements. Use type \a XMC_CAN_MO_t for this structure. + */ +typedef struct XMC_CAN_MO +{ + CAN_MO_TypeDef *can_mo_ptr; /**< Pointer to the Message Object CAN register */ + union{ + struct{ + uint32_t can_identifier:29; /**< standard (11 bit)/Extended (29 bit) message identifier */ + uint32_t can_id_mode:1; /**< Standard/Extended identifier support */ + uint32_t can_priority:2; /**< Arbitration Mode/Priority */ + }; + uint32_t mo_ar; + }; + union{ + struct{ + uint32_t can_id_mask:29; /**< CAN Identifier of Message Object */ + uint32_t can_ide_mask:1; /**< Identifier Extension Bit of Message Object */ + }; + uint32_t mo_amr; + }; + uint8_t can_data_length; /**< Message data length, Range:0-8 */ + + union{ + + uint8_t can_data_byte[8]; /**< Each position of the array represents a data byte*/ + uint16_t can_data_word[4]; /**< Each position of the array represents a 16 bits data word*/ + uint32_t can_data[2]; /**< can_data[0] lower 4 bytes of the data. can_data[1], higher 4 bytes + of the data */ + uint64_t can_data_long; /** Data of the Message Object*/ + }; + + XMC_CAN_MO_TYPE_t can_mo_type; /**< Message Type */ + +} XMC_CAN_MO_t; +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @return None + * + * \parDescription:
+ * Disables CAN module. In disabled state, no registers of CAN module can be read or written except the CAN_CLC register. + * + * \parRelated APIs:
+ * XMC_CAN_Enable()\n\n\n + * + */ + +void XMC_CAN_Disable(XMC_CAN_t *const obj); + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @return None + * + * \parDescription:
+ * Enables CAN module and initializes all CAN registers to reset values. It is required to re-configure desired CAN nodes, + * before any data transfer. It configures CAN_CLC.DISR bit. + * + * \parRelated APIs:
+ * XMC_CAN_Disable()\n\n\n + * + */ + +void XMC_CAN_Enable(XMC_CAN_t *const obj); + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @param node_num CAN node number,Range : 0-2 + * @param mo_num CAN Message Object number,Range : 0-63 + * + * @return None + * + * \parDescription:
+ * Allocates Message Object from free list to node list. Each \a node_num is linked to one unique list of message objects. + * A CAN node performs message transfer only with the \a mo_num message objects that are allocated to the list of the CAN node. + * It configures PANCTR register. + * + * \parRelated APIs:
+ * None + * + */ + +void XMC_CAN_AllocateMOtoNodeList(XMC_CAN_t *const obj, const uint8_t node_num, const uint8_t mo_num); + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @return Ready status of list controller + * + * \parDescription:
+ * Returns ready status of the list controller + * + * \parRelated APIs:
+ * XMC_CAN_PanelControl() + * + */ +__STATIC_INLINE bool XMC_CAN_IsPanelControlReady(XMC_CAN_t *const obj) +{ + return (bool)((obj->PANCTR & (CAN_PANCTR_BUSY_Msk | CAN_PANCTR_RBUSY_Msk)) == 0); +} + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @param pancmd panal command selection. Refer @ref XMC_CAN_PANCMD_t for valid values. + * @param arg1 Panel Argument 1,Range : 0-2 + * @param arg2 Panel Argument 2, Range : 0-63 + * + * @return None + * + * \parDescription:
+ * Configures the panel command and panel arguments. A panel operation consists of a command code (PANCMD) and up to two + * panel arguments (PANAR1, PANAR2). Commands that have a return value deliver it to the PANAR1 bit field. Commands that + * return an error flag deliver it to bit 31 of the Panel Control Register, this means bit 7 of PANAR2. \a arg1 represents + * panel argument PANAR1,\a arg2 represents panel argument PANAR2 and \a pancmd represents command code. It configures PANCTR + * register. + * + * \parRelated APIs:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_PanelControl(XMC_CAN_t *const obj, + const XMC_CAN_PANCMD_t pancmd, + const uint8_t arg1, + const uint8_t arg2) +{ + obj->PANCTR = (((uint32_t)pancmd << CAN_PANCTR_PANCMD_Pos) & (uint32_t)CAN_PANCTR_PANCMD_Msk) | + (((uint32_t)arg1 << CAN_PANCTR_PANAR1_Pos) & (uint32_t)CAN_PANCTR_PANAR1_Msk) | + (((uint32_t)arg2 << CAN_PANCTR_PANAR2_Pos) & (uint32_t)CAN_PANCTR_PANAR2_Msk); +} + + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @param service_requestr Interrupt trigger number selection. Refer @ref XMC_CAN_NODE_INTERRUPT_TRIGGER_t for valid values. + * Multiple interrupt trigger events can be ORed. + * + * @return None + * + * \parDescription:
+ * Configures multiple interrupt requests with a single write operation. \a service_requestr represents single interrupt + * request or multiple.It configures MITR register. + * + * \parRelated APIs:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_EventTrigger(XMC_CAN_t *const obj,const XMC_CAN_NODE_INTERRUPT_TRIGGER_t service_requestr) +{ + obj->MITR = ((uint32_t)service_requestr << CAN_MITR_IT_Pos) & (uint32_t)CAN_MITR_IT_Msk; +} + + + + /*INIT APIs*/ + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @param can_frequency CAN module frequency(fCAN). Range : 5MHz to 120MHz + * + * @return None + * + * \parDescription:
+ * Configures clock rate of the module timer clock fCAN. Altering CAN module \a can_frequency shall affects baud rate, + * call XMC_CAN_NODE_NominalBitTimeConfigure() to configure baud rate for current CAN frequency.It configures FDR register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_NominalBitTimeConfigure()\n\n\n + * + */ + + +#if defined(MULTICAN_PLUS) +void XMC_CAN_Init(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can_frequency); +/** + * + */ +XMC_CAN_CANCLKSRC_t XMC_CAN_GetBaudrateClockSource(XMC_CAN_t *const obj); +/** + * + */ +void XMC_CAN_SetBaudrateClockSource(XMC_CAN_t *const obj,const XMC_CAN_CANCLKSRC_t source); +/** + * + */ +uint32_t XMC_CAN_GetBaudrateClockFrequency(XMC_CAN_t *const obj); +#else +void XMC_CAN_Init(XMC_CAN_t *const obj, uint32_t can_frequency); +#endif + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Initializes CAN message object. Initialization includes configuring Message Object identifier type, Message Object + * identifier value, Message Object type, and transfer requests. It configures FDR register. + * + * \parRelated APIs:
+ * None + * + */ + +void XMC_CAN_MO_Config(const XMC_CAN_MO_t *const can_mo); + + + /*NODE APIs*/ + + +/** + * + * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers. + * @param ptr_event CAN_NODE interrupt pointer position. Refer @ref XMC_CAN_NODE_POINTER_EVENT_t structure for valid values. + * @param service_request Interrupt service request number. Range : 0-7 + * + * @return None + * + * \parDescription:
+ * Configures node interrupt pointer \a service_request for CAN Node events \a ptr_event. It configures NIPR register. + * + * \parRelated APIs:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_SetEventNodePointer(XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_POINTER_EVENT_t ptr_event, + const uint32_t service_request) +{ + can_node->NIPR = (uint32_t)((can_node->NIPR) & ~(uint32_t)(CAN_NODE_NIPR_Msk << (uint32_t)ptr_event)) | (service_request << (uint32_t)ptr_event); +} + + +/** + * + * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers. Range :CAN_NODE0-CAN_NODE2 + * @param can_bit_time Nominal bit time configuration data structure. Refer @ref XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t for details. + * + * @return None + * + * \parDescription:
+ * Configures CAN node Baudrate. \a can_bit_time specifies required baudrate for a specified \a can_node. + * It configures NBTR register. + * + * \parRelated APIs:
+ * None + * + */ +void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const can_bit_time); + +/** + * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param input CAN receive input selection. Refer @ref XMC_CAN_NODE_RECEIVE_INPUT_t for details. + * + * @return None + * + * \parDescription:
+ * \a input specifies CAN input receive pin. This API Configures NPCRx register,it is required to call + * XMC_CAN_NODE_EnableConfigurationChange(), before configuring NPCRx register, call XMC_CAN_NODE_DisableConfigurationChange() + * API after configuring NPCRx register. CAN input receive pins which falls under analog port pins should call + * XMC_GPIO_EnableDigitalInput(),to enable digital pad. + * + *\parRelated APIs:
+ * None + * + * \parNote:
+ * NPCRx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_SetReceiveInput(XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_RECEIVE_INPUT_t input) +{ + can_node->NPCR = ((can_node->NPCR) & ~(uint32_t)(CAN_NODE_NPCR_RXSEL_Msk)) | + (((uint32_t)input << CAN_NODE_NPCR_RXSEL_Pos) & (uint32_t)CAN_NODE_NPCR_RXSEL_Msk); +} + + +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Enable Node \a can_node in Loop-Back Mode. A Node is connected to an internal (virtual) loop-back CAN bus. All CAN + * nodes which are in Loop- Back Mode are connected to this virtual CAN bus so that they can communicate with each + * other internally. The external transmit line is forced recessive in Loop-Back Mode. This API Configures NPCRx register. + * call XMC_CAN_NODE_EnableConfigurationChange() API before NPCRx configuration, same way XMC_CAN_NODE_DisableConfigurationChange() + * API after NPCRx configuration configuration. + * + * \parRelated APIs:
] + * XMC_CAN_NODE_DisableLoopBack(). + * + * \parNote:
+ * NPCRx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_EnableLoopBack(XMC_CAN_NODE_t *const can_node) +{ + can_node->NPCR |= (uint32_t)CAN_NODE_NPCR_LBM_Msk; +} + + +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Disable Node Loop-Back Mode, disables internal (virtual) loop-back CAN bus. This API Configures NPCRx register. + * Call XMC_CAN_NODE_EnableConfigurationChange() API before NPCRx configuration, same way XMC_CAN_NODE_DisableConfigurationChange() + * API after NPCRx configuration. + * + * \parRelated APIs:
] + * XMC_CAN_NODE_EnableLoopBack() + * + * + * \parNote:
+ * NPCRx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_DisableLoopBack(XMC_CAN_NODE_t *const can_node) +{ + can_node->NPCR &= ~(uint32_t)CAN_NODE_NPCR_LBM_Msk; +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param event CAN node event mask value. Refer @ref XMC_CAN_NODE_EVENT_t structure for valid values. + * multiple events can be ORed. + * + * @return None + * + * \parDescription:
+ * Enable CAN Node events. It configures NFCR register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_DisableEvent() + * + */ + +void XMC_CAN_NODE_EnableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event); + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param event CAN node event mask value. Refer @ref XMC_CAN_NODE_EVENT_t structure for valid values. + * multiple events can be ORed. + * + * @return None + * + * \parDescription:
+ * Disable CAN Node events. It configures NFCR register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_EnableEvent() + * + */ + +void XMC_CAN_NODE_DisableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event); + + +/** + * + * @param node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return XMC_CAN_NODE_LAST_ERROR_DIR_t Last error transfer direction. Refer @ref XMC_CAN_NODE_LAST_ERROR_DIR_t. + * + * \parDescription:
+ * Returns NODE Last Error occurred during Transmit/receive direction. It returns value of NFCR register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetLastErrTransferInc()\n\n\n + * + */ + +__STATIC_INLINE XMC_CAN_NODE_LAST_ERROR_DIR_t XMC_CAN_NODE_GetLastErrTransferDir(XMC_CAN_NODE_t *const node) +{ + return (XMC_CAN_NODE_LAST_ERROR_DIR_t)(((node->NECNT) & CAN_NODE_NECNT_LETD_Msk) >> CAN_NODE_NECNT_LETD_Pos); +} + + +/** + * + * @param node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return XMC_CAN_NODE_LAST_ERROR_INC_t Last error transfer increment. Refer @ref XMC_CAN_NODE_LAST_ERROR_INC_t. + * + * \parDescription:
+ * Returns NODE Last Error Transfer Increment. It returns value of NFCR register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetLastErrTransferDir()\n\n\n + * + */ + +__STATIC_INLINE XMC_CAN_NODE_LAST_ERROR_INC_t XMC_CAN_NODE_GetLastErrTransferInc(XMC_CAN_NODE_t *const node) +{ + return (XMC_CAN_NODE_LAST_ERROR_INC_t)(((node->NECNT) & CAN_NODE_NECNT_LEINC_Msk)>> CAN_NODE_NECNT_LEINC_Pos); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param error_warning_level Error Warning level value. Range :0-255. + * + * @return None + * + * \parDescription:
+ * Configures error warning level in order to set the corresponding error warning bit EWRN. It configures \a error_warning_level + * into NECNT register. Before this configuration call XMC_CAN_NODE_EnableConfigurationChange() API. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetErrorWarningLevel()\n\n\n + * + * \parNote:
+ * NECNTx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_SetErrorWarningLevel(XMC_CAN_NODE_t *const can_node, uint8_t error_warning_level) +{ + can_node->NECNT = ((can_node->NECNT) & ~(uint32_t)(CAN_NODE_NECNT_EWRNLVL_Msk)) | + (((uint32_t)error_warning_level << CAN_NODE_NECNT_EWRNLVL_Pos) & (uint32_t)CAN_NODE_NECNT_EWRNLVL_Msk); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param can_tec transmit error counter value. Range :0-255 + * + * @return None + * + * \parDescription:
+ * Configures Transmit error counter. It configures \a can_tec into NECNT register. Before this configuration call + * XMC_CAN_NODE_EnableConfigurationChange() API. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetTransmitErrorCounter()\n\n\n + * + * \parNote:
+ * NECNTx can be written only if bit NCRx.CCE is set. + * + */ + + +__STATIC_INLINE void XMC_CAN_NODE_SetTransmitErrorCounter(XMC_CAN_NODE_t *const can_node, uint8_t can_tec) +{ + can_node->NECNT = ((can_node->NECNT) & ~(uint32_t)(CAN_NODE_NECNT_TEC_Msk)) | + (((uint32_t)can_tec << CAN_NODE_NECNT_TEC_Pos) & (uint32_t)CAN_NODE_NECNT_TEC_Msk); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param can_rec receive error counter value. Range :0-255 + * + * @return None + * + * \parDescription:
+ * Configures Receive Error Counter. It configures \a can_rec into NECNT register. Before this configuration call + * XMC_CAN_NODE_EnableConfigurationChange() API. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetReceiveErrorCounter()\n\n\n + * + * \parNote:
+ * NECNTx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_SetReceiveErrorCounter(XMC_CAN_NODE_t *const can_node, uint8_t can_rec) +{ + can_node->NECNT = ((can_node->NECNT) & ~(uint32_t)(CAN_NODE_NECNT_REC_Msk)) | + (((uint32_t)can_rec << CAN_NODE_NECNT_REC_Pos) & (uint32_t)CAN_NODE_NECNT_REC_Msk); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return uint8_t Error Warning Level. Range :0 - 255 + * + * \parDescription:
+ * Returns error warning level. This determines the threshold value (warning level, default 96) to be reached in order + * to set the corresponding error warning bit EWRN. It reads NECNT register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_SetErrorWarningLevel()\n\n\n + * + */ + + +__STATIC_INLINE uint8_t XMC_CAN_NODE_GetErrorWarningLevel(XMC_CAN_NODE_t *const can_node) +{ + return (uint8_t)((uint32_t)((can_node->NECNT) & CAN_NODE_NECNT_EWRNLVL_Msk) >> CAN_NODE_NECNT_EWRNLVL_Pos); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return uint8_t transmit error counter value. Range :0 - 255 + * + * \parDescription:
+ * Returns Transmit Error Counter value. If the Bitstream Processor detects an error while a transmit operation is + * running, the Transmit Error Counter is incremented by 8. An increment of 1 is used when the error condition was + * reported by an external CAN node via an Error Frame generation. It reads NECNT register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_SetTransmitErrorCounter() + * + * \parNote:
+ * NECNTx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE uint8_t XMC_CAN_NODE_GetTransmitErrorCounter(XMC_CAN_NODE_t *const can_node) +{ + return (uint8_t)((uint32_t)((can_node->NECNT) & CAN_NODE_NECNT_TEC_Msk) >> CAN_NODE_NECNT_TEC_Pos); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return uint8_t receive error counter value. + * + * \parDescription:
+ * Returns Receive Error Counter value. It reads NECNT register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_SetReceiveErrorCounter() + * + */ + +__STATIC_INLINE uint8_t XMC_CAN_NODE_GetReceiveErrorCounter(XMC_CAN_NODE_t *const can_node) +{ + return (uint8_t)((uint32_t)((can_node->NECNT) & CAN_NODE_NECNT_REC_Msk) >> CAN_NODE_NECNT_REC_Pos); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return uint32_t Current status of the node. + * + * \parDescription:
+ * Returns errors status as well as successfully transferred CAN frames status. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_ClearStatus() + * + */ + +__STATIC_INLINE uint32_t XMC_CAN_NODE_GetStatus(XMC_CAN_NODE_t *const can_node) +{ + return ((can_node->NSR)); +} + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param can_node_status Status to clear.Refer @ref XMC_CAN_NODE_STATUS_t for valid values. + * + * @return None + * + * \parDescription:
+ * Clear errors status as well as successfully transferred CAN frames status. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetStatus() + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_ClearStatus(XMC_CAN_NODE_t *const can_node,XMC_CAN_NODE_STATUS_t can_node_status) +{ + can_node->NSR &= ~(uint32_t)can_node_status; +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Allow to change the configuration of the CAN node, like bit timing, CAN bus transmit/receive ports and error + * counters read. It configures NCRx.CCE bit. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_DisableConfigurationChange() + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_EnableConfigurationChange(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_CCE_Msk; +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Forbid to change the configuration of the CAN node. It configures NCRx.CCE bit. + * + * \parRelated API's:
+ * XMC_CAN_NODE_EnableConfigurationChange() + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_DisableConfigurationChange(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR &= ~(uint32_t)CAN_NODE_NCR_CCE_Msk; +} + + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Disable CAN node participation in CAN traffic. Bit INIT is automatically set when the CAN node enters the bus-off + * state. It configures NCR.INIT bit. + * + * \parRelated API's:
+ * XMC_CAN_NODE_ResetInitBit() + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_SetInitBit(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_INIT_Msk; +} + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Enable CAN node participation in CAN traffic. Bit INIT is automatically set when the CAN node enters the bus-off + * state. It configures NCR.INIT bit. + * + * \parRelated API's:
+ * XMC_CAN_NODE_SetInitBit() + * + */ +__STATIC_INLINE void XMC_CAN_NODE_ResetInitBit(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR &= ~(uint32_t)CAN_NODE_NCR_INIT_Msk; +} + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Enable the CAN node, starts the participation in CAN traffic. It configures NCR.CANDIS and the NCR.INIT bits. + * + * \parRelated API's:
+ * None + * + */ +__STATIC_INLINE void XMC_CAN_NODE_Enable(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR &= ~(uint32_t)CAN_NODE_NCR_CANDIS_Msk; + XMC_CAN_NODE_ResetInitBit(can_node); +} + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Disable the CAN node, terminates participation in CAN traffic. It configures NCR.CANDIS bit. + * + * \parRelated API's:
+ * None + * + */ +__STATIC_INLINE void XMC_CAN_NODE_Disable(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_CANDIS_Msk; +} + +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Configure CAN node in Analyzer Mode. This means that messages may be received, but not transmitted. No acknowledge + * is sent on the CAN bus upon frame reception. Active-error flags are sent recessive instead of dominant. + * The transmit line is continuously held at recessive (1) level. XMC_CAN_NODE_SetInitBit() should be called before + * set / reset AnalyzerMode. It configures NCR.CALM bit. + * + * \parRelated API's:
+ * XMC_CAN_NODE_ReSetAnalyzerMode() + * + */ + + +__STATIC_INLINE void XMC_CAN_NODE_SetAnalyzerMode(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_CALM_Msk; +} + + +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Reset the Analyzer mode. CAN node is no more in Analyzer Mode. Please refer XMC_CAN_NODE_SetAnalyzerMode(). + * It configures NCR.CALM bit. XMC_CAN_NODE_SetInitBit() should be called before set / reset AnalyzerMode. + * + * \parRelated API's:
+ * XMC_CAN_NODE_SetAnalyzerMode() + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_ReSetAnalyzerMode(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR &= ~(uint32_t)CAN_NODE_NCR_CALM_Msk; +} + +#if !defined(MULTICAN_PLUS) +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Trigger the suspension of the CAN node. An OCDS(on chip debug support) suspend trigger disables the CAN node: As + * soon as the CAN node becomes bus-idle or bus-off, bit INIT is internally forced to 1 to disable the CAN node. + * The actual value of bit INIT remains unchanged. It configures NCR.SUSEN bit + * + * \parRelated API's:
+ * None + * + *\parNote:
+ * Bit SUSEN is reset via OCDS(on chip debug support) Reset. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_EnableSuspend(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_SUSEN_Msk; +} +#else +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Disables the transmission on CAN node x as soon as bus-idle is reached. + * + * \parRelated API's:
+ * None + * + * @note Only available for XMC1400,XMC4800 and XMC4700 series + */ + +__STATIC_INLINE void XMC_CAN_NODE_DisableTransmit(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_TXDIS_Msk; +} +#endif + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param can_node_init frame counter mode selection. Refer @ref XMC_CAN_NODE_FRAME_COUNTER_t for valid values. + * + * @return None + * + * \parDescription:
+ * Configures frame counter functions. Each CAN \a can_node is equipped with a frame counter that counts transmitted/received + * CAN frames or obtains information about the time when a frame has been started to transmit or be received by the CAN + * node. It configures NFCR register. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_FrameCounterConfigure(XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_FRAME_COUNTER_t *const can_node_init) +{ + can_node->NFCR = (can_node->NFCR & ~(uint32_t)(CAN_NODE_NFCR_CFMOD_Msk | + CAN_NODE_NFCR_CFSEL_Msk)) | + can_node_init->nfcr; +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return uint16_t current value of the CAN frame counter. Range :0-65535 + * + * \parDescription:
+ * Returns the frame counter value \a can_node of the CAN node. In Frame Count Mode (CFMOD = 00B), this API returns the frame + * count value. In Time Stamp Mode (CFMOD = 01B), this API returns the captured bit time count value, captured with + * the start of a new frame. In all Bit Timing Analysis Modes (CFMOD = 10B), this API always returns the number of + * fCLC clock cycles (measurement result) minus 1. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE uint16_t XMC_CAN_NODE_GetCANFrameCounter(XMC_CAN_NODE_t *const can_node) +{ + return (uint16_t)(((uint32_t)(can_node->NFCR & CAN_NODE_NFCR_CFC_Msk) >> CAN_NODE_NFCR_CFC_Pos)); +} + + /*MO APIs*/ + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * + * @return None + * + * \parDescription:
+ * Configures Data to be transmitted and data length code. + * + * \parRelated API's:
+ * XMC_CAN_MO_Config()\n\n\n + * + */ + + +XMC_CAN_STATUS_t XMC_CAN_MO_UpdateData(const XMC_CAN_MO_t *const can_mo); + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * + * \parDescription:
+ * Configures transmit request for sending data frame. It configures MOCTR register. Data shall be updated + * using XMC_CAN_MO_UpdateData() before calling this API. + * + * \parRelated API's:
+ * XMC_CAN_MO_UpdateData()\n\n\n + * + */ + +XMC_CAN_STATUS_t XMC_CAN_MO_Transmit(const XMC_CAN_MO_t *const can_mo); + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * + * \parDescription:
+ * Reads the Message Object data bytes, into message pointer passed as input parameter \a can_mo. + * can_data[0] of can_mo holds lower 4 bytes, can_data[1] of can_mo holds higher 4 bytes. + * + * \parRelated API's:
+ * None + * + */ + +XMC_CAN_STATUS_t XMC_CAN_MO_Receive(XMC_CAN_MO_t *can_mo); + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * + * \parDescription:
+ * Reads the Message Object data bytes, into message pointer passed as input parameter \a can_mo. + * can_data[0] of can_mo holds lower 4 bytes, can_data[1] of can_mo holds higher 4 bytes. + * + * \parRelated API's:
+ * None + * + */ +XMC_CAN_STATUS_t XMC_CAN_MO_ReceiveData (XMC_CAN_MO_t *can_mo); +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_mo_ptr_int Message Object event node pointer selection. Refer @ref XMC_CAN_MO_POINTER_EVENT_t structure + * for valid values. + * @param service_request interrupt output line of multiCAN module. + * + * @return None + * + * \parDescription:
+ * Configures Message Object event node pointer with \a service_request number. It configures MOIPR register. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_MO_SetEventNodePointer(const XMC_CAN_MO_t *const can_mo, + const XMC_CAN_MO_POINTER_EVENT_t can_mo_ptr_int, + const uint32_t service_request) +{ + can_mo->can_mo_ptr->MOIPR = ((can_mo->can_mo_ptr->MOIPR ) & ~(uint32_t)((uint32_t)CAN_MO_MOIPR_Msk << (uint32_t)can_mo_ptr_int)) | + (service_request << (uint32_t)can_mo_ptr_int); +} + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return uint32_t Current Message Object status. + * + * \parDescription:
+ * Returns Message Object status, that indicates message object transfer status and message object list status + * information such as the number of the current message object predecessor and successor message object, as well as + * the list number to which the message object is assigned. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE uint32_t XMC_CAN_MO_GetStatus(const XMC_CAN_MO_t *const can_mo) +{ + return ((can_mo->can_mo_ptr->MOSTAT)); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param mask Message Object set status selection. Refer @ref XMC_CAN_MO_SET_STATUS_t for details. + * Multiple enums can be ORed. + * @return None + * + * \parDescription:
+ * Configures Message Object set Status. It configures MOCTR register. + * + * \parRelated API's:
+ * XMC_CAN_MO_ResetStatus()\n\n\n + * + */ + +__STATIC_INLINE void XMC_CAN_MO_SetStatus(const XMC_CAN_MO_t *const can_mo, const uint32_t mask) +{ + can_mo->can_mo_ptr->MOCTR = mask; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param mask Message Object set status selection. Refer @ref XMC_CAN_MO_RESET_STATUS_t for details. + * Multiple enums can be ORed. + * @return None + * + * \parDescription:
+ * Clears Message Object interrupt events. It configures MOCTR register. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_MO_ResetStatus(const XMC_CAN_MO_t *const can_mo,const uint32_t mask) +{ + can_mo->can_mo_ptr->MOCTR = mask; +} + + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param event CAN node Message Object event selection. Refer @ref XMC_CAN_MO_EVENT_t for details. + * + * @return None + * + * \parDescription:
+ * Enable CAN Message Object events. \a event can be ORed multiple Message Object events. It configures MOFCR register. + * + * \parRelated API's:
+ * XMC_CAN_MO_DisableEvent() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_EnableEvent(const XMC_CAN_MO_t *const can_mo, + const uint32_t event) +{ + can_mo->can_mo_ptr->MOFCR |= event; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param event CAN node Message Object event selection. Refer @ref XMC_CAN_MO_EVENT_t for details. + * + * @return None + * + * \parDescription:
+ * Disable CAN Message Object events. \a event can be ORed multiple Message Object events. It configures MOFCR register. + * + * \parRelated API's:
+ * XMC_CAN_MO_EnableEvent() + * + * + */ + +__STATIC_INLINE void XMC_CAN_MO_DisableEvent(const XMC_CAN_MO_t *const can_mo, + const uint32_t event) +{ + can_mo->can_mo_ptr->MOFCR &= ~event; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Enable the single transmit trial(STT). In STT,TXRQ is cleared on transmission start of message object n. Thus, + * no transmission retry is performed in case of transmission failure. It configures MOFCR.STT bit. + * + * \parRelated API's:
+ * XMC_CAN_MO_DisableSingleTransmitTrial() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_EnableSingleTransmitTrial(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR |= (uint32_t) CAN_MO_MOFCR_STT_Msk; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Disable the single transmit trial(STT). In STT,TXRQ is cleared on transmission start of message object n. Thus, + * no transmission retry is performed in case of transmission failure. It configures MOFCR.STT bit. + * + * \parRelated API's:
+ * XMC_CAN_MO_EnableSingleTransmitTrial() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_DisableSingleTransmitTrial(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR &= ~(uint32_t)CAN_MO_MOFCR_STT_Msk; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param data_length_code transfer data length. Range:0-8 + * + * @return None + * + * \parDescription:
+ * Configures CAN Message Object Data Length Code. It configures MOFCR register. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_MO_DataLengthCode(const XMC_CAN_MO_t *const can_mo,const uint8_t data_length_code) +{ + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_DLC_Msk)) | + (((uint32_t)data_length_code << CAN_MO_MOFCR_DLC_Pos) & (uint32_t)CAN_MO_MOFCR_DLC_Msk); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param data_length_code transfer data length. Range:0-8 + * + * @return None + * + * \parDescription:
+ * Configures CAN Message Object Data Length Code. It configures MOFCR register. + * + * \parRelated API's:
+ * XMC_CAN_MO_GetDataLengthCode() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_SetDataLengthCode(XMC_CAN_MO_t *const can_mo,const uint8_t data_length_code) +{ + can_mo->can_data_length = data_length_code; + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_DLC_Msk)) | + (((uint32_t)data_length_code << CAN_MO_MOFCR_DLC_Pos) & (uint32_t)CAN_MO_MOFCR_DLC_Msk); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return Data length code + * + * \parDescription:
+ * Gets the Data Length Code. + * + * \parRelated API's:
+ * XMC_CAN_MO_SetDataLengthCode() + * + */ + +__STATIC_INLINE uint8_t XMC_CAN_MO_GetDataLengthCode(const XMC_CAN_MO_t *const can_mo) +{ + return (((can_mo->can_mo_ptr->MOFCR) & (uint32_t)(CAN_MO_MOFCR_DLC_Msk)) >> CAN_MO_MOFCR_DLC_Pos); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_identifier Identifier. + * + * @return None + * + * \parDescription:
+ * Configures CAN Message Object Identifier. It configures MOAR register. + * + * \parRelated API's:
+ * XMC_CAN_MO_GetIdentifier() + * + */ + +void XMC_CAN_MO_SetIdentifier(XMC_CAN_MO_t *const can_mo, const uint32_t can_identifier); + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return CAN MO identifier + * + * \parDescription:
+ * Gets the Identifier of the MO + * + * \parRelated API's:
+ * XMC_CAN_MO_SetIdentifier() + * + */ + +uint32_t XMC_CAN_MO_GetIdentifier(const XMC_CAN_MO_t *const can_mo); + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return Acceptance mask + * + * \parDescription:
+ * Gets the acceptance mask for the CAN MO. + * + * \parRelated API's:
+ * XMC_CAN_MO_SetAcceptanceMask() + * + */ + +uint32_t XMC_CAN_MO_GetAcceptanceMask(const XMC_CAN_MO_t *const can_mo); + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_id_mask CAN MO acceptance mask. + * + * @return None + * + * \parDescription:
+ * Sets the acceptance mask of the MO + * + * \parRelated API's:
+ * XMC_CAN_MO_GetAcceptanceMask() + * + */ + +void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo,const uint32_t can_id_mask); + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Message object receives frames only with matching IDE bit. + * + * \parRelated API's:
+ * XMC_CAN_MO_AcceptStandardAndExtendedID() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_AcceptOnlyMatchingIDE(XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_ide_mask = 1U; + can_mo->can_mo_ptr->MOAMR |=(uint32_t)(CAN_MO_MOAMR_MIDE_Msk); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Message object accepts the reception of both, standard and extended frames. + * + * \parRelated API's:
+ * XMC_CAN_MO_AcceptOnlyMatchingIDE() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_AcceptStandardAndExtendedID(XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_ide_mask = 0U; + can_mo->can_mo_ptr->MOAMR &= ~(uint32_t)(CAN_MO_MOAMR_MIDE_Msk); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Message object handles standard frames with 11-bit identifier. + * + * \parRelated API's:
+ * XMC_CAN_MO_SetExtendedID() + * + * \parNote:
+ * After setting the identifier type user has to set the identifier value by using @ref XMC_CAN_MO_SetIdentifier() API. + */ + +__STATIC_INLINE void XMC_CAN_MO_SetStandardID(XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_STANDARD_11BITS; + can_mo->can_mo_ptr->MOAR &= ~(uint32_t)(CAN_MO_MOAR_IDE_Msk); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Message object handles extended frames with 29-bit identifier. + * + * \parRelated API's:
+ * XMC_CAN_MO_SetStandardID() + * + * \parNote:
+ * After setting the identifier type user has to set the identifier value by using @ref XMC_CAN_MO_SetIdentifier() API. + * + */ + +__STATIC_INLINE void XMC_CAN_MO_SetExtendedID(XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_EXTENDED_29BITS; + can_mo->can_mo_ptr->MOAR |= (uint32_t)CAN_MO_MOAR_IDE_Msk; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to enable the FIFO Foreign Remote Request. This Specifies TXRQ of the message object referenced + * by the pointer CUR is set on reception of a matching Remote Frame. It configures MOFCR.FRREN register. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_DisableForeingRemoteRequest()\n\n\n + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_EnableForeignRemoteRequest(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR |= (uint32_t)CAN_MO_MOFCR_FRREN_Msk; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to disable the FIFO Foreign Remote Request. TXRQ of message object n is set on reception + * of a matching Remote Frame. It configures MOFCR.FRREN register. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_EnableForeignRemoteRequest()\n\n\n + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_DisableForeingRemoteRequest(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR &= ~(uint32_t)CAN_MO_MOFCR_FRREN_Msk; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to enable the FIFO Remote Monitoring. This Specifies identifier, IDE(Identifier Extension) bit, + * and DLC of a matching Remote Frame are copied to transmit object n in order to monitor incoming Remote Frames. + * It configures MOFCR.RMM bit. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_DisableRemoteMonitoring()\n\n\n + * + * \parNote:
+ * Remote monitoring(RMM) applies only to transmit objects and has no effect on receive objects. + * + */ +__STATIC_INLINE void XMC_CAN_FIFO_EnableRemoteMonitoring(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR |= (uint32_t)CAN_MO_MOFCR_RMM_Msk; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to disable the FIFO Remote Monitoring. This Specifies Identifier, Identifier Extension bit, + * and DLC of message object n remain unchanged upon the reception of a matching Remote Frame. + * It configures MOFCR.RMM bit. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_EnableRemoteMonitoring()\n\n\n + * + * \parNote:
+ * Remote monitoring(RMM) applies only to transmit objects and has no effect on receive objects. + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_DisableRemoteMonitoring(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR &= ~(uint32_t)CAN_MO_MOFCR_RMM_Msk; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param select_pointer Selected Message Object number. Range:0-63 + * + * @return None + * + * \parDescription:
+ * Set Object Select Pointer. If the current pointer CUR of FIFO base object becomes equal \a select_pointer, + * a FIFO overflow interrupt request is generated. Used for FIFO monitoring purpose. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_SetSELMO(const XMC_CAN_MO_t *const can_mo,const uint8_t select_pointer) +{ + can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_SEL_Msk)) | + (((uint32_t)select_pointer << CAN_MO_MOFGPR_SEL_Pos) & (uint32_t)CAN_MO_MOFGPR_SEL_Msk); +} + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return uint8_t Current Message Object Number. Range:0-63 + * + * \parDescription:
+ * Returns the current FIFO Message Object,points to the actual target object within a FIFO/Gateway structure. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE uint8_t XMC_CAN_FIFO_GetCurrentMO(const XMC_CAN_MO_t *const can_mo) +{ + return (uint8_t)((uint32_t)(can_mo->can_mo_ptr->MOFGPR & CAN_MO_MOFGPR_CUR_Msk) >> CAN_MO_MOFGPR_CUR_Pos); +} + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to enable the Single Data Transfer of the FIFO Message Object. If SDT = 1 and message object n + * is not a FIFO base object, then MSGVAL is reset when this object has taken part in a successful data transfer + * (receive or transmit). If SDT = 1 and message object n is a FIFO base object, then MSGVAL is reset when the pointer + * to the current object CUR reaches the value of SEL in the FIFO/Gateway Pointer Register. It configures MOFCR.SDT bit. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_DisableSingleDataTransfer() + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_EnableSingleDataTransfer(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR |= (uint32_t)CAN_MO_MOFCR_SDT_Msk; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to disable the Single Data Transfer of the FIFO Message Object, with this configuration bit + * MSGVAL is not affected. It configures MOFCR.SDT bit. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_EnableSingleDataTransfer() + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_DisableSingleDataTransfer(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR &= ~(uint32_t)CAN_MO_MOFCR_SDT_Msk; +} + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_fifo CAN FIFO configuration data structure. Refer @ref XMC_CAN_FIFO_CONFIG_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the transmit FIFO. A FIFO consists of one base object and n slave objects. Please refer + * reference manual \b Transmit FIFO for more info. + * + * \parRelated API's:
+ * None. + * + */ + +void XMC_CAN_TXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo); + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_fifo CAN FIFO configuration data structure. Refer @ref XMC_CAN_FIFO_CONFIG_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the base object of receive FIFO. + * + * \parRelated API's:
+ * None + */ + +void XMC_CAN_RXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo); + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_fifo CAN FIFO configuration data structure. Refer @ref XMC_CAN_FIFO_CONFIG_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the slave object of transmit FIFO. + * + * \parRelated API's:
+ * None + * + */ +void XMC_CAN_TXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo); + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the slave Object of receive FIFO. It configures MOCTR.RESRXEN bit. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_RXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOCTR = (uint32_t)CAN_MO_MOCTR_RESRXEN_Msk; +} + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_gateway CAN gateway configuration data structure. Refer XMC_CAN_GATEWAY_CONFIG_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the Gateway source object. The Gateway Mode \a can_gateway makes it possible to establish an automatic + * information transfer between two independent CAN buses without CPU interaction. Please refer reference manual + * \b GatewayMode for more info. + * + * \parRelated API's:
+ * None + * + */ + +void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_GATEWAY_CONFIG_t can_gateway); + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the Gateway destination object. The Gateway Mode \a can_gateway makes it possible to establish an automatic + * information transfer between two independent CAN buses without CPU interaction. Please refer reference manual + * \b GatewayMode for more info. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_GATEWAY_InitDesObject(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESRXEN_Msk | + CAN_MO_MOCTR_RESNEWDAT_Msk; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * + * \parDescription:
+ * To transmit Message Object from the FIFO. Prior to this CAN node Message Object FIFO structure shall be made using + * XMC_CAN_TXFIFO_ConfigMOBaseObject(), XMC_CAN_TXFIFO_ConfigMOSlaveObject(),XMC_CAN_RXFIFO_ConfigMOBaseObject() API's. + * Please refer reference manual \b MessageObject \b FIFOStructure for more info. + * + * + */ +XMC_CAN_STATUS_t XMC_CAN_TXFIFO_Transmit(const XMC_CAN_MO_t *const can_mo); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CAN) */ + +#endif /* XMC_CAN_H */ + + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_can_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_can_map.h new file mode 100644 index 00000000..a8bff4d6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_can_map.h @@ -0,0 +1,629 @@ +/** + * @file xmc_can_map.h + * @date 2015-10-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-10-20: + * - Removed "const" in the MOs for avoiding compiler warnings + * + * 2015-09-15: + * - Initial version + * + * @endcond + * + */ + +#ifndef XMC_CAN_MAP_H +#define XMC_CAN_MAP_H + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN48) +#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#endif + +#if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN64) +#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#endif + +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48) +#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#endif + +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN64) +#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#endif + +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#endif + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE5_RXD_P5_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#endif + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#endif + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LFBGA196) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE3_RXD_P7_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE4_RXD_P7_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE5_RXD_P5_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE5_RXD_P8_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#endif + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + +#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || (UC_SERIES == XMC43)|| (UC_SERIES == XMC14) +#define CAN_MO0 ((CAN_MO_TypeDef *)&(CAN_MO->MO[0])) +#define CAN_MO1 ((CAN_MO_TypeDef *)&(CAN_MO->MO[1])) +#define CAN_MO2 ((CAN_MO_TypeDef *)&(CAN_MO->MO[2])) +#define CAN_MO3 ((CAN_MO_TypeDef *)&(CAN_MO->MO[3])) +#define CAN_MO4 ((CAN_MO_TypeDef *)&(CAN_MO->MO[4])) +#define CAN_MO5 ((CAN_MO_TypeDef *)&(CAN_MO->MO[5])) +#define CAN_MO6 ((CAN_MO_TypeDef *)&(CAN_MO->MO[6])) +#define CAN_MO7 ((CAN_MO_TypeDef *)&(CAN_MO->MO[7])) +#define CAN_MO8 ((CAN_MO_TypeDef *)&(CAN_MO->MO[8])) +#define CAN_MO9 ((CAN_MO_TypeDef *)&(CAN_MO->MO[9])) +#define CAN_MO10 ((CAN_MO_TypeDef *)&(CAN_MO->MO[10])) +#define CAN_MO11 ((CAN_MO_TypeDef *)&(CAN_MO->MO[11])) +#define CAN_MO12 ((CAN_MO_TypeDef *)&(CAN_MO->MO[12])) +#define CAN_MO13 ((CAN_MO_TypeDef *)&(CAN_MO->MO[13])) +#define CAN_MO14 ((CAN_MO_TypeDef *)&(CAN_MO->MO[14])) +#define CAN_MO15 ((CAN_MO_TypeDef *)&(CAN_MO->MO[15])) +#define CAN_MO16 ((CAN_MO_TypeDef *)&(CAN_MO->MO[16])) +#define CAN_MO17 ((CAN_MO_TypeDef *)&(CAN_MO->MO[17])) +#define CAN_MO18 ((CAN_MO_TypeDef *)&(CAN_MO->MO[18])) +#define CAN_MO19 ((CAN_MO_TypeDef *)&(CAN_MO->MO[19])) +#define CAN_MO20 ((CAN_MO_TypeDef *)&(CAN_MO->MO[20])) +#define CAN_MO21 ((CAN_MO_TypeDef *)&(CAN_MO->MO[21])) +#define CAN_MO22 ((CAN_MO_TypeDef *)&(CAN_MO->MO[22])) +#define CAN_MO23 ((CAN_MO_TypeDef *)&(CAN_MO->MO[23])) +#define CAN_MO24 ((CAN_MO_TypeDef *)&(CAN_MO->MO[24])) +#define CAN_MO25 ((CAN_MO_TypeDef *)&(CAN_MO->MO[25])) +#define CAN_MO26 ((CAN_MO_TypeDef *)&(CAN_MO->MO[26])) +#define CAN_MO27 ((CAN_MO_TypeDef *)&(CAN_MO->MO[27])) +#define CAN_MO28 ((CAN_MO_TypeDef *)&(CAN_MO->MO[28])) +#define CAN_MO29 ((CAN_MO_TypeDef *)&(CAN_MO->MO[29])) +#define CAN_MO30 ((CAN_MO_TypeDef *)&(CAN_MO->MO[30])) +#define CAN_MO31 ((CAN_MO_TypeDef *)&(CAN_MO->MO[31])) +#endif + + +#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48)|| (UC_SERIES == XMC43) +#define CAN_MO32 ((CAN_MO_TypeDef *)&(CAN_MO->MO[32])) +#define CAN_MO33 ((CAN_MO_TypeDef *)&(CAN_MO->MO[33])) +#define CAN_MO34 ((CAN_MO_TypeDef *)&(CAN_MO->MO[34])) +#define CAN_MO35 ((CAN_MO_TypeDef *)&(CAN_MO->MO[35])) +#define CAN_MO36 ((CAN_MO_TypeDef *)&(CAN_MO->MO[36])) +#define CAN_MO37 ((CAN_MO_TypeDef *)&(CAN_MO->MO[37])) +#define CAN_MO38 ((CAN_MO_TypeDef *)&(CAN_MO->MO[38])) +#define CAN_MO39 ((CAN_MO_TypeDef *)&(CAN_MO->MO[39])) +#define CAN_MO40 ((CAN_MO_TypeDef *)&(CAN_MO->MO[40])) +#define CAN_MO41 ((CAN_MO_TypeDef *)&(CAN_MO->MO[41])) +#define CAN_MO42 ((CAN_MO_TypeDef *)&(CAN_MO->MO[42])) +#define CAN_MO43 ((CAN_MO_TypeDef *)&(CAN_MO->MO[43])) +#define CAN_MO44 ((CAN_MO_TypeDef *)&(CAN_MO->MO[44])) +#define CAN_MO45 ((CAN_MO_TypeDef *)&(CAN_MO->MO[45])) +#define CAN_MO46 ((CAN_MO_TypeDef *)&(CAN_MO->MO[46])) +#define CAN_MO47 ((CAN_MO_TypeDef *)&(CAN_MO->MO[47])) +#define CAN_MO48 ((CAN_MO_TypeDef *)&(CAN_MO->MO[48])) +#define CAN_MO49 ((CAN_MO_TypeDef *)&(CAN_MO->MO[49])) +#define CAN_MO50 ((CAN_MO_TypeDef *)&(CAN_MO->MO[50])) +#define CAN_MO51 ((CAN_MO_TypeDef *)&(CAN_MO->MO[51])) +#define CAN_MO52 ((CAN_MO_TypeDef *)&(CAN_MO->MO[52])) +#define CAN_MO53 ((CAN_MO_TypeDef *)&(CAN_MO->MO[53])) +#define CAN_MO54 ((CAN_MO_TypeDef *)&(CAN_MO->MO[54])) +#define CAN_MO55 ((CAN_MO_TypeDef *)&(CAN_MO->MO[55])) +#define CAN_MO56 ((CAN_MO_TypeDef *)&(CAN_MO->MO[56])) +#define CAN_MO57 ((CAN_MO_TypeDef *)&(CAN_MO->MO[57])) +#define CAN_MO58 ((CAN_MO_TypeDef *)&(CAN_MO->MO[58])) +#define CAN_MO59 ((CAN_MO_TypeDef *)&(CAN_MO->MO[59])) +#define CAN_MO60 ((CAN_MO_TypeDef *)&(CAN_MO->MO[60])) +#define CAN_MO61 ((CAN_MO_TypeDef *)&(CAN_MO->MO[61])) +#define CAN_MO62 ((CAN_MO_TypeDef *)&(CAN_MO->MO[62])) +#define CAN_MO63 ((CAN_MO_TypeDef *)&(CAN_MO->MO[63])) +#if (UC_SERIES != XMC43) +#define CAN_MO64 ((CAN_MO_TypeDef *)&(CAN_MO->MO[64])) +#define CAN_MO65 ((CAN_MO_TypeDef *)&(CAN_MO->MO[65])) +#define CAN_MO66 ((CAN_MO_TypeDef *)&(CAN_MO->MO[66])) +#define CAN_MO67 ((CAN_MO_TypeDef *)&(CAN_MO->MO[67])) +#define CAN_MO68 ((CAN_MO_TypeDef *)&(CAN_MO->MO[68])) +#define CAN_MO69 ((CAN_MO_TypeDef *)&(CAN_MO->MO[69])) +#define CAN_MO70 ((CAN_MO_TypeDef *)&(CAN_MO->MO[70])) +#define CAN_MO71 ((CAN_MO_TypeDef *)&(CAN_MO->MO[71])) +#define CAN_MO72 ((CAN_MO_TypeDef *)&(CAN_MO->MO[72])) +#define CAN_MO73 ((CAN_MO_TypeDef *)&(CAN_MO->MO[73])) +#define CAN_MO74 ((CAN_MO_TypeDef *)&(CAN_MO->MO[74])) +#define CAN_MO75 ((CAN_MO_TypeDef *)&(CAN_MO->MO[75])) +#define CAN_MO76 ((CAN_MO_TypeDef *)&(CAN_MO->MO[76])) +#define CAN_MO77 ((CAN_MO_TypeDef *)&(CAN_MO->MO[77])) +#define CAN_MO78 ((CAN_MO_TypeDef *)&(CAN_MO->MO[78])) +#define CAN_MO79 ((CAN_MO_TypeDef *)&(CAN_MO->MO[79])) +#define CAN_MO80 ((CAN_MO_TypeDef *)&(CAN_MO->MO[80])) +#define CAN_MO81 ((CAN_MO_TypeDef *)&(CAN_MO->MO[81])) +#define CAN_MO82 ((CAN_MO_TypeDef *)&(CAN_MO->MO[82])) +#define CAN_MO83 ((CAN_MO_TypeDef *)&(CAN_MO->MO[83])) +#define CAN_MO84 ((CAN_MO_TypeDef *)&(CAN_MO->MO[84])) +#define CAN_MO85 ((CAN_MO_TypeDef *)&(CAN_MO->MO[85])) +#define CAN_MO86 ((CAN_MO_TypeDef *)&(CAN_MO->MO[86])) +#define CAN_MO87 ((CAN_MO_TypeDef *)&(CAN_MO->MO[87])) +#define CAN_MO88 ((CAN_MO_TypeDef *)&(CAN_MO->MO[88])) +#define CAN_MO89 ((CAN_MO_TypeDef *)&(CAN_MO->MO[89])) +#define CAN_MO90 ((CAN_MO_TypeDef *)&(CAN_MO->MO[90])) +#define CAN_MO91 ((CAN_MO_TypeDef *)&(CAN_MO->MO[91])) +#define CAN_MO92 ((CAN_MO_TypeDef *)&(CAN_MO->MO[92])) +#define CAN_MO93 ((CAN_MO_TypeDef *)&(CAN_MO->MO[93])) +#define CAN_MO94 ((CAN_MO_TypeDef *)&(CAN_MO->MO[94])) +#define CAN_MO95 ((CAN_MO_TypeDef *)&(CAN_MO->MO[95])) +#define CAN_MO96 ((CAN_MO_TypeDef *)&(CAN_MO->MO[96])) +#define CAN_MO97 ((CAN_MO_TypeDef *)&(CAN_MO->MO[97])) +#define CAN_MO98 ((CAN_MO_TypeDef *)&(CAN_MO->MO[98])) +#define CAN_MO99 ((CAN_MO_TypeDef *)&(CAN_MO->MO[99])) +#define CAN_MO100 ((CAN_MO_TypeDef *)&(CAN_MO->MO[100])) +#define CAN_MO101 ((CAN_MO_TypeDef *)&(CAN_MO->MO[101])) +#define CAN_MO102 ((CAN_MO_TypeDef *)&(CAN_MO->MO[102])) +#define CAN_MO103 ((CAN_MO_TypeDef *)&(CAN_MO->MO[103])) +#define CAN_MO104 ((CAN_MO_TypeDef *)&(CAN_MO->MO[104])) +#define CAN_MO105 ((CAN_MO_TypeDef *)&(CAN_MO->MO[105])) +#define CAN_MO106 ((CAN_MO_TypeDef *)&(CAN_MO->MO[106])) +#define CAN_MO107 ((CAN_MO_TypeDef *)&(CAN_MO->MO[107])) +#define CAN_MO108 ((CAN_MO_TypeDef *)&(CAN_MO->MO[108])) +#define CAN_MO109 ((CAN_MO_TypeDef *)&(CAN_MO->MO[109])) +#define CAN_MO110 ((CAN_MO_TypeDef *)&(CAN_MO->MO[110])) +#define CAN_MO111 ((CAN_MO_TypeDef *)&(CAN_MO->MO[111])) +#define CAN_MO112 ((CAN_MO_TypeDef *)&(CAN_MO->MO[112])) +#define CAN_MO113 ((CAN_MO_TypeDef *)&(CAN_MO->MO[113])) +#define CAN_MO114 ((CAN_MO_TypeDef *)&(CAN_MO->MO[114])) +#define CAN_MO115 ((CAN_MO_TypeDef *)&(CAN_MO->MO[115])) +#define CAN_MO116 ((CAN_MO_TypeDef *)&(CAN_MO->MO[116])) +#define CAN_MO117 ((CAN_MO_TypeDef *)&(CAN_MO->MO[117])) +#define CAN_MO118 ((CAN_MO_TypeDef *)&(CAN_MO->MO[118])) +#define CAN_MO119 ((CAN_MO_TypeDef *)&(CAN_MO->MO[119])) +#define CAN_MO120 ((CAN_MO_TypeDef *)&(CAN_MO->MO[120])) +#define CAN_MO121 ((CAN_MO_TypeDef *)&(CAN_MO->MO[121])) +#define CAN_MO122 ((CAN_MO_TypeDef *)&(CAN_MO->MO[122])) +#define CAN_MO123 ((CAN_MO_TypeDef *)&(CAN_MO->MO[123])) +#define CAN_MO124 ((CAN_MO_TypeDef *)&(CAN_MO->MO[124])) +#define CAN_MO125 ((CAN_MO_TypeDef *)&(CAN_MO->MO[125])) +#define CAN_MO126 ((CAN_MO_TypeDef *)&(CAN_MO->MO[126])) +#define CAN_MO127 ((CAN_MO_TypeDef *)&(CAN_MO->MO[127])) +#define CAN_MO128 ((CAN_MO_TypeDef *)&(CAN_MO->MO[128])) +#define CAN_MO129 ((CAN_MO_TypeDef *)&(CAN_MO->MO[129])) +#define CAN_MO130 ((CAN_MO_TypeDef *)&(CAN_MO->MO[130])) +#define CAN_MO131 ((CAN_MO_TypeDef *)&(CAN_MO->MO[131])) +#define CAN_MO132 ((CAN_MO_TypeDef *)&(CAN_MO->MO[132])) +#define CAN_MO133 ((CAN_MO_TypeDef *)&(CAN_MO->MO[133])) +#define CAN_MO134 ((CAN_MO_TypeDef *)&(CAN_MO->MO[134])) +#define CAN_MO135 ((CAN_MO_TypeDef *)&(CAN_MO->MO[135])) +#define CAN_MO136 ((CAN_MO_TypeDef *)&(CAN_MO->MO[136])) +#define CAN_MO137 ((CAN_MO_TypeDef *)&(CAN_MO->MO[137])) +#define CAN_MO138 ((CAN_MO_TypeDef *)&(CAN_MO->MO[138])) +#define CAN_MO139 ((CAN_MO_TypeDef *)&(CAN_MO->MO[139])) +#define CAN_MO140 ((CAN_MO_TypeDef *)&(CAN_MO->MO[140])) +#define CAN_MO141 ((CAN_MO_TypeDef *)&(CAN_MO->MO[141])) +#define CAN_MO142 ((CAN_MO_TypeDef *)&(CAN_MO->MO[142])) +#define CAN_MO143 ((CAN_MO_TypeDef *)&(CAN_MO->MO[143])) +#define CAN_MO144 ((CAN_MO_TypeDef *)&(CAN_MO->MO[144])) +#define CAN_MO145 ((CAN_MO_TypeDef *)&(CAN_MO->MO[145])) +#define CAN_MO146 ((CAN_MO_TypeDef *)&(CAN_MO->MO[146])) +#define CAN_MO147 ((CAN_MO_TypeDef *)&(CAN_MO->MO[147])) +#define CAN_MO148 ((CAN_MO_TypeDef *)&(CAN_MO->MO[148])) +#define CAN_MO149 ((CAN_MO_TypeDef *)&(CAN_MO->MO[149])) +#define CAN_MO150 ((CAN_MO_TypeDef *)&(CAN_MO->MO[150])) +#define CAN_MO151 ((CAN_MO_TypeDef *)&(CAN_MO->MO[151])) +#define CAN_MO152 ((CAN_MO_TypeDef *)&(CAN_MO->MO[152])) +#define CAN_MO153 ((CAN_MO_TypeDef *)&(CAN_MO->MO[153])) +#define CAN_MO154 ((CAN_MO_TypeDef *)&(CAN_MO->MO[154])) +#define CAN_MO155 ((CAN_MO_TypeDef *)&(CAN_MO->MO[155])) +#define CAN_MO156 ((CAN_MO_TypeDef *)&(CAN_MO->MO[156])) +#define CAN_MO157 ((CAN_MO_TypeDef *)&(CAN_MO->MO[157])) +#define CAN_MO158 ((CAN_MO_TypeDef *)&(CAN_MO->MO[158])) +#define CAN_MO159 ((CAN_MO_TypeDef *)&(CAN_MO->MO[159])) +#define CAN_MO160 ((CAN_MO_TypeDef *)&(CAN_MO->MO[160])) +#define CAN_MO161 ((CAN_MO_TypeDef *)&(CAN_MO->MO[161])) +#define CAN_MO162 ((CAN_MO_TypeDef *)&(CAN_MO->MO[162])) +#define CAN_MO163 ((CAN_MO_TypeDef *)&(CAN_MO->MO[163])) +#define CAN_MO164 ((CAN_MO_TypeDef *)&(CAN_MO->MO[164])) +#define CAN_MO165 ((CAN_MO_TypeDef *)&(CAN_MO->MO[165])) +#define CAN_MO166 ((CAN_MO_TypeDef *)&(CAN_MO->MO[166])) +#define CAN_MO167 ((CAN_MO_TypeDef *)&(CAN_MO->MO[167])) +#define CAN_MO168 ((CAN_MO_TypeDef *)&(CAN_MO->MO[168])) +#define CAN_MO169 ((CAN_MO_TypeDef *)&(CAN_MO->MO[169])) +#define CAN_MO170 ((CAN_MO_TypeDef *)&(CAN_MO->MO[170])) +#define CAN_MO171 ((CAN_MO_TypeDef *)&(CAN_MO->MO[171])) +#define CAN_MO172 ((CAN_MO_TypeDef *)&(CAN_MO->MO[172])) +#define CAN_MO173 ((CAN_MO_TypeDef *)&(CAN_MO->MO[173])) +#define CAN_MO174 ((CAN_MO_TypeDef *)&(CAN_MO->MO[174])) +#define CAN_MO175 ((CAN_MO_TypeDef *)&(CAN_MO->MO[175])) +#define CAN_MO176 ((CAN_MO_TypeDef *)&(CAN_MO->MO[176])) +#define CAN_MO177 ((CAN_MO_TypeDef *)&(CAN_MO->MO[177])) +#define CAN_MO178 ((CAN_MO_TypeDef *)&(CAN_MO->MO[178])) +#define CAN_MO179 ((CAN_MO_TypeDef *)&(CAN_MO->MO[179])) +#define CAN_MO180 ((CAN_MO_TypeDef *)&(CAN_MO->MO[180])) +#define CAN_MO181 ((CAN_MO_TypeDef *)&(CAN_MO->MO[181])) +#define CAN_MO182 ((CAN_MO_TypeDef *)&(CAN_MO->MO[182])) +#define CAN_MO183 ((CAN_MO_TypeDef *)&(CAN_MO->MO[183])) +#define CAN_MO184 ((CAN_MO_TypeDef *)&(CAN_MO->MO[184])) +#define CAN_MO185 ((CAN_MO_TypeDef *)&(CAN_MO->MO[185])) +#define CAN_MO186 ((CAN_MO_TypeDef *)&(CAN_MO->MO[186])) +#define CAN_MO187 ((CAN_MO_TypeDef *)&(CAN_MO->MO[187])) +#define CAN_MO188 ((CAN_MO_TypeDef *)&(CAN_MO->MO[188])) +#define CAN_MO189 ((CAN_MO_TypeDef *)&(CAN_MO->MO[189])) +#define CAN_MO190 ((CAN_MO_TypeDef *)&(CAN_MO->MO[190])) +#define CAN_MO191 ((CAN_MO_TypeDef *)&(CAN_MO->MO[191])) +#define CAN_MO192 ((CAN_MO_TypeDef *)&(CAN_MO->MO[192])) +#define CAN_MO193 ((CAN_MO_TypeDef *)&(CAN_MO->MO[193])) +#define CAN_MO194 ((CAN_MO_TypeDef *)&(CAN_MO->MO[194])) +#define CAN_MO195 ((CAN_MO_TypeDef *)&(CAN_MO->MO[195])) +#define CAN_MO196 ((CAN_MO_TypeDef *)&(CAN_MO->MO[196])) +#define CAN_MO197 ((CAN_MO_TypeDef *)&(CAN_MO->MO[197])) +#define CAN_MO198 ((CAN_MO_TypeDef *)&(CAN_MO->MO[198])) +#define CAN_MO199 ((CAN_MO_TypeDef *)&(CAN_MO->MO[199])) +#define CAN_MO200 ((CAN_MO_TypeDef *)&(CAN_MO->MO[200])) +#define CAN_MO201 ((CAN_MO_TypeDef *)&(CAN_MO->MO[201])) +#define CAN_MO202 ((CAN_MO_TypeDef *)&(CAN_MO->MO[202])) +#define CAN_MO203 ((CAN_MO_TypeDef *)&(CAN_MO->MO[203])) +#define CAN_MO204 ((CAN_MO_TypeDef *)&(CAN_MO->MO[204])) +#define CAN_MO205 ((CAN_MO_TypeDef *)&(CAN_MO->MO[205])) +#define CAN_MO206 ((CAN_MO_TypeDef *)&(CAN_MO->MO[206])) +#define CAN_MO207 ((CAN_MO_TypeDef *)&(CAN_MO->MO[207])) +#define CAN_MO208 ((CAN_MO_TypeDef *)&(CAN_MO->MO[208])) +#define CAN_MO209 ((CAN_MO_TypeDef *)&(CAN_MO->MO[209])) +#define CAN_MO210 ((CAN_MO_TypeDef *)&(CAN_MO->MO[210])) +#define CAN_MO211 ((CAN_MO_TypeDef *)&(CAN_MO->MO[211])) +#define CAN_MO212 ((CAN_MO_TypeDef *)&(CAN_MO->MO[212])) +#define CAN_MO213 ((CAN_MO_TypeDef *)&(CAN_MO->MO[213])) +#define CAN_MO214 ((CAN_MO_TypeDef *)&(CAN_MO->MO[214])) +#define CAN_MO215 ((CAN_MO_TypeDef *)&(CAN_MO->MO[215])) +#define CAN_MO216 ((CAN_MO_TypeDef *)&(CAN_MO->MO[216])) +#define CAN_MO217 ((CAN_MO_TypeDef *)&(CAN_MO->MO[217])) +#define CAN_MO218 ((CAN_MO_TypeDef *)&(CAN_MO->MO[218])) +#define CAN_MO219 ((CAN_MO_TypeDef *)&(CAN_MO->MO[219])) +#define CAN_MO220 ((CAN_MO_TypeDef *)&(CAN_MO->MO[220])) +#define CAN_MO221 ((CAN_MO_TypeDef *)&(CAN_MO->MO[221])) +#define CAN_MO222 ((CAN_MO_TypeDef *)&(CAN_MO->MO[222])) +#define CAN_MO223 ((CAN_MO_TypeDef *)&(CAN_MO->MO[223])) +#define CAN_MO224 ((CAN_MO_TypeDef *)&(CAN_MO->MO[224])) +#define CAN_MO225 ((CAN_MO_TypeDef *)&(CAN_MO->MO[225])) +#define CAN_MO226 ((CAN_MO_TypeDef *)&(CAN_MO->MO[226])) +#define CAN_MO227 ((CAN_MO_TypeDef *)&(CAN_MO->MO[227])) +#define CAN_MO228 ((CAN_MO_TypeDef *)&(CAN_MO->MO[228])) +#define CAN_MO229 ((CAN_MO_TypeDef *)&(CAN_MO->MO[229])) +#define CAN_MO230 ((CAN_MO_TypeDef *)&(CAN_MO->MO[230])) +#define CAN_MO231 ((CAN_MO_TypeDef *)&(CAN_MO->MO[231])) +#define CAN_MO232 ((CAN_MO_TypeDef *)&(CAN_MO->MO[232])) +#define CAN_MO233 ((CAN_MO_TypeDef *)&(CAN_MO->MO[233])) +#define CAN_MO234 ((CAN_MO_TypeDef *)&(CAN_MO->MO[234])) +#define CAN_MO235 ((CAN_MO_TypeDef *)&(CAN_MO->MO[235])) +#define CAN_MO236 ((CAN_MO_TypeDef *)&(CAN_MO->MO[236])) +#define CAN_MO237 ((CAN_MO_TypeDef *)&(CAN_MO->MO[237])) +#define CAN_MO238 ((CAN_MO_TypeDef *)&(CAN_MO->MO[238])) +#define CAN_MO239 ((CAN_MO_TypeDef *)&(CAN_MO->MO[239])) +#define CAN_MO240 ((CAN_MO_TypeDef *)&(CAN_MO->MO[240])) +#define CAN_MO241 ((CAN_MO_TypeDef *)&(CAN_MO->MO[241])) +#define CAN_MO242 ((CAN_MO_TypeDef *)&(CAN_MO->MO[242])) +#define CAN_MO243 ((CAN_MO_TypeDef *)&(CAN_MO->MO[243])) +#define CAN_MO244 ((CAN_MO_TypeDef *)&(CAN_MO->MO[244])) +#define CAN_MO245 ((CAN_MO_TypeDef *)&(CAN_MO->MO[245])) +#define CAN_MO246 ((CAN_MO_TypeDef *)&(CAN_MO->MO[246])) +#define CAN_MO247 ((CAN_MO_TypeDef *)&(CAN_MO->MO[247])) +#define CAN_MO248 ((CAN_MO_TypeDef *)&(CAN_MO->MO[248])) +#define CAN_MO249 ((CAN_MO_TypeDef *)&(CAN_MO->MO[249])) +#define CAN_MO250 ((CAN_MO_TypeDef *)&(CAN_MO->MO[250])) +#define CAN_MO251 ((CAN_MO_TypeDef *)&(CAN_MO->MO[251])) +#define CAN_MO252 ((CAN_MO_TypeDef *)&(CAN_MO->MO[252])) +#define CAN_MO253 ((CAN_MO_TypeDef *)&(CAN_MO->MO[253])) +#define CAN_MO254 ((CAN_MO_TypeDef *)&(CAN_MO->MO[254])) +#define CAN_MO255 ((CAN_MO_TypeDef *)&(CAN_MO->MO[255])) +#endif +#endif + +#endif /* XMC_CAN_MAP_H*/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ccu4.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ccu4.h new file mode 100644 index 00000000..5d5c02c8 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ccu4.h @@ -0,0 +1,2386 @@ +/** + * @file xmc_ccu4.h + * @date 2016-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Documentation updates
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-07-22: + * - XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
+ * + * 2015-08-17: + * - XMC_CCU4_SLICE_PRESCALER_t enum is added to set the prescaler divider.
+ * - XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t enum item names are updated according to the guidelines.
+ * - XMC_CCU4_EnableShadowTransfer() API is made as inline, to improve the speed.
+ * + * 2015-09-29: + * - In XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t, two more enum items are added to support external count direction + * settings. + * + * 2015-10-07: + * - XMC_CCU4_SLICE_GetEvent() is made as inline. + * - XMC_CCU4_SLICE_MULTI_IRQ_ID_t is added to support the XMC_CCU4_SLICE_EnableMultipleEvents() and + * XMC_CCU4_SLICE_DisableMultipleEvents() APIs. + * - DOC updates for the newly added APIs. + * + * 2016-03-09: + * - Optimization of write only registers + * + * 2016-05-20: + * - Added XMC_CCU4_SLICE_StopClearTimer() + * - Changed implementation of XMC_CCU4_SLICE_StopTimer() and XMC_CCU4_SLICE_ClearTimer() to avoid RMW access + * + * @endcond + */ + +#ifndef XMC_CCU4_H +#define XMC_CCU4_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_common.h" +#if defined(CCU40) + +#if UC_FAMILY == XMC1 + #include "xmc1_ccu4_map.h" +#endif + +#if UC_FAMILY == XMC4 + #include "xmc4_ccu4_map.h" +#endif + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup CCU4 + * @brief Capture Compare Unit 4 (CCU4) low level driver for XMC family of microcontrollers
+ * + * The CCU4 peripheral is a major component for systems that need general purpose timers for signal + * monitoring/conditioning and Pulse Width Modulation (PWM) signal generation. Power electronic control systems like + * switched mode power supplies or interruptible power supplies, can easily be implemented with the functions inside the + * CCU4 peripheral.\n + * Each CCU4 module is comprised of four identical 16 bit Capture/Compare Timer slices, CC4y (where y = [0..4]). Each + * timer slice can work in compare mode or in capture mode. + * + * APIs provided in this file cover the following functional blocks of CCU4:\n + * -- Timer configuration, Capture configuration, Function/Event configuration, Interrupt configuration\n + * \par Note: + * 1. SLICE (APIs prefixed with e.g. XMC_CCU4_SLICE_) + * 2. Module (APIs are not having any prefix e.g. XMC_CCU4_) + * + * \par Timer(Compare mode) configuration: + * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_COMPARE_CONFIG_t and the initialization + * function XMC_CCU4_SLICE_CompareInit(). + * + * It can be used to: + * -# Start and Stop the timer. (XMC_CCU4_SLICE_StartTimer(), XMC_CCU4_SLICE_StopTimer()) + * -# Update the period, compare, Dither, Prescaler and Passive values. (XMC_CCU4_SLICE_SetTimerPeriodMatch(), + * XMC_CCU4_SLICE_SetTimerCompareMatch(), XMC_CCU4_SLICE_SetPrescaler(), XMC_CCU4_SLICE_SetDitherCompareValue(), + * XMC_CCU4_SLICE_SetPassiveLevel()) + * -# Enable the slices to support multichannel mode. (XMC_CCU4_SLICE_EnableMultiChannelMode()) + * + * \par Capture configuration: + * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_CAPTURE_CONFIG_t and the initialization + * function XMC_CCU4_SLICE_CaptureInit(). + * + * It can be used to: + * -# Configure the capture functionality. (XMC_CCU4_SLICE_Capture0Config(), XMC_CCU4_SLICE_Capture1Config()) + * -# Read the captured values along with the status, which indicate the value is latest or not. + * (XMC_CCU4_SLICE_GetCaptureRegisterValue()) + * + * \par Function/Event configuration: + * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_EVENT_CONFIG_t.\n + * + * It can be used to: + * -# Enable and Disable the events. (XMC_CCU4_SLICE_EnableEvent(), XMC_CCU4_SLICE_DisableEvent()) + * -# Configure to start and stop the timer on external events.(XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_StopConfig()) + * -# Modulation, external load and Gating of the timer output.(XMC_CCU4_SLICE_ModulationConfig(), + * XMC_CCU4_SLICE_LoadConfig(), XMC_CCU4_SLICE_GateConfig()) + * -# Control the count direction of the timer based on the external event. (XMC_CCU4_SLICE_DirectionConfig()) + * -# Count the external events.(XMC_CCU4_SLICE_CountConfig()) + * -# External Trap. Which can be used as protective feature.(XMC_CCU4_SLICE_EnableTrap(), XMC_CCU4_SLICE_DisableTrap(), + * XMC_CCU4_SLICE_TrapConfig()) + * + * \par Interrupt configuration: + * This section of the LLD provides the function to configure the interrupt node to each event (XMC_CCU4_SLICE_SetInterruptNode()) + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +/* Macro to check if the interrupt enum passed is valid */ +#define XMC_CCU4_SLICE_CHECK_INTERRUPT(interrupt) \ + ((interrupt == XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN)|| \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT0) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT1) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT2) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_TRAP)) + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/** + * Typedef for CCU4 Global data structure + */ +typedef CCU4_GLOBAL_TypeDef XMC_CCU4_MODULE_t; + +/** + * Typedef for CCU4 Slice data structure + */ +typedef CCU4_CC4_TypeDef XMC_CCU4_SLICE_t; + +/** + * Return Value of an API + */ +typedef enum XMC_CCU4_STATUS +{ + XMC_CCU4_STATUS_OK = 0U, /**< API fulfils request */ + XMC_CCU4_STATUS_ERROR , /**< API cannot fulfil the request */ + XMC_CCU4_STATUS_RUNNING , /**< The timer slice is currently running */ + XMC_CCU4_STATUS_IDLE /**< The timer slice is currently idle */ +} XMC_CCU4_STATUS_t; + +/** + * CCU4 module clock + */ +typedef enum XMC_CCU4_CLOCK +{ + XMC_CCU4_CLOCK_SCU = 0U, /**< Select the fCCU as the clock */ + XMC_CCU4_CLOCK_EXTERNAL_A , /**< External clock-A */ + XMC_CCU4_CLOCK_EXTERNAL_B , /**< External clock-B */ + XMC_CCU4_CLOCK_EXTERNAL_C /**< External clock-C */ +} XMC_CCU4_CLOCK_t; + +/** + * CCU4 set the shadow transfer type for multichannel mode + */ +typedef enum XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER +{ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0 = (uint32_t)0x4000000, /**< Shadow transfer through software + only for slice 0*/ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0 = (uint32_t)0x4000400, /**< Shadow transfer through software + and hardware for slice 0 */ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1 = (uint32_t)0x8000000, /**< Shadow transfer through software + only for slice 1*/ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1 = (uint32_t)0x8000800, /**< Shadow transfer through software + and hardware for slice 1 */ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2 = (uint32_t)0x10000000, /**< Shadow transfer through software + only for slice 2 */ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE2 = (uint32_t)0x10001000, /**< Shadow transfer through software + and hardware for slice 2 */ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE3 = (uint32_t)0x20000000, /**< Shadow transfer through software + only for slice 3*/ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE3 = (uint32_t)0x20002000 /**< Shadow transfer through software + and hardware for slice 3 */ +} XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_t; + +/** + * Operational modes of CCU4 slice + */ +typedef enum XMC_CCU4_SLICE_MODE +{ + XMC_CCU4_SLICE_MODE_COMPARE = 0U, /**< slice(CC4y) operates in Compare Mode */ + XMC_CCU4_SLICE_MODE_CAPTURE /**< slice(CC4y) operates in Capture Mode */ +} XMC_CCU4_SLICE_MODE_t; + +/** + * Timer counting modes for the slice + */ +typedef enum XMC_CCU4_SLICE_TIMER_COUNT_MODE +{ + XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA = 0U, /**< Edge Aligned Mode */ + XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA /**< Center Aligned Mode */ +} XMC_CCU4_SLICE_TIMER_COUNT_MODE_t; + +/** + * Timer repetition mode for the slice + */ +typedef enum XMC_CCU4_SLICE_TIMER_REPEAT_MODE +{ + XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT = 0U, /**< Repetitive mode: continuous mode of operation */ + XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE /**< Single shot mode: Once a Period match/One match + occurs timer goes to idle state */ +} XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t; + +/** + * Timer counting direction for the CCU4 slice + */ +typedef enum XMC_CCU4_SLICE_TIMER_COUNT_DIR +{ + XMC_CCU4_SLICE_TIMER_COUNT_DIR_UP = 0U, /**< Counting up */ + XMC_CCU4_SLICE_TIMER_COUNT_DIR_DOWN /**< Counting down */ +} XMC_CCU4_SLICE_TIMER_COUNT_DIR_t; + +/** + * Capture mode register sets + */ +typedef enum XMC_CCU4_SLICE_CAP_REG_SET +{ + XMC_CCU4_SLICE_CAP_REG_SET_LOW = 0U, /**< Capture register-0, Capture register-1 used */ + XMC_CCU4_SLICE_CAP_REG_SET_HIGH /**< Capture register-2, Capture register-3 used */ +} XMC_CCU4_SLICE_CAP_REG_SET_t; + +/** + * Prescaler mode + */ +typedef enum XMC_CCU4_SLICE_PRESCALER_MODE +{ + XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL = 0U, /**< Fixed division of module clock */ + XMC_CCU4_SLICE_PRESCALER_MODE_FLOAT /**< Floating divider. */ +} XMC_CCU4_SLICE_PRESCALER_MODE_t; + +/** + * Timer output passive level + */ +typedef enum XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL +{ + XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW = 0U, /**< Passive level = Low */ + XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH /**< Passive level = High */ +} XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t; + +/** + * Timer clock Divider + */ +typedef enum XMC_CCU4_SLICE_PRESCALER +{ + XMC_CCU4_SLICE_PRESCALER_1 = 0U, /**< Slice Clock = fccu4 */ + XMC_CCU4_SLICE_PRESCALER_2 , /**< Slice Clock = fccu4/2 */ + XMC_CCU4_SLICE_PRESCALER_4 , /**< Slice Clock = fccu4/4 */ + XMC_CCU4_SLICE_PRESCALER_8 , /**< Slice Clock = fccu4/8 */ + XMC_CCU4_SLICE_PRESCALER_16 , /**< Slice Clock = fccu4/16 */ + XMC_CCU4_SLICE_PRESCALER_32 , /**< Slice Clock = fccu4/32 */ + XMC_CCU4_SLICE_PRESCALER_64 , /**< Slice Clock = fccu4/64 */ + XMC_CCU4_SLICE_PRESCALER_128 , /**< Slice Clock = fccu4/128 */ + XMC_CCU4_SLICE_PRESCALER_256 , /**< Slice Clock = fccu4/256 */ + XMC_CCU4_SLICE_PRESCALER_512 , /**< Slice Clock = fccu4/512 */ + XMC_CCU4_SLICE_PRESCALER_1024 , /**< Slice Clock = fccu4/1024 */ + XMC_CCU4_SLICE_PRESCALER_2048 , /**< Slice Clock = fccu4/2048 */ + XMC_CCU4_SLICE_PRESCALER_4096 , /**< Slice Clock = fccu4/4096 */ + XMC_CCU4_SLICE_PRESCALER_8192 , /**< Slice Clock = fccu4/8192 */ + XMC_CCU4_SLICE_PRESCALER_16384 , /**< Slice Clock = fccu4/16384 */ + XMC_CCU4_SLICE_PRESCALER_32768 /**< Slice Clock = fccu4/32768 */ +} XMC_CCU4_SLICE_PRESCALER_t; + +/** + * External Function list + */ +typedef enum XMC_CCU4_SLICE_FUNCTION +{ + XMC_CCU4_SLICE_FUNCTION_START = 0U, /**< Start function */ + XMC_CCU4_SLICE_FUNCTION_STOP , /**< Stop function */ + XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT0 , /**< Capture Event-0 function, CCycapt0 signal is used for event + generation */ + XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT1 , /**< Capture Event-1 function, CCycapt1 signal is used for event + generation */ + XMC_CCU4_SLICE_FUNCTION_GATING , /**< Gating function */ + XMC_CCU4_SLICE_FUNCTION_DIRECTION , /**< Direction function */ + XMC_CCU4_SLICE_FUNCTION_LOAD , /**< Load function */ + XMC_CCU4_SLICE_FUNCTION_COUNT , /**< Counting function */ + XMC_CCU4_SLICE_FUNCTION_OVERRIDE , /**< Override function */ + XMC_CCU4_SLICE_FUNCTION_MODULATION , /**< Modulation function */ + XMC_CCU4_SLICE_FUNCTION_TRAP /**< Trap function */ +} XMC_CCU4_SLICE_FUNCTION_t; + +/** + * External Event list + */ +typedef enum XMC_CCU4_SLICE_EVENT +{ + XMC_CCU4_SLICE_EVENT_NONE = 0U, /**< None */ + XMC_CCU4_SLICE_EVENT_0 , /**< Event-0 */ + XMC_CCU4_SLICE_EVENT_1 , /**< Event-1 */ + XMC_CCU4_SLICE_EVENT_2 /**< Event-2 */ +} XMC_CCU4_SLICE_EVENT_t; + +/** + * External Event trigger criteria - Edge sensitivity + */ +typedef enum XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY +{ + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE = 0U, /**< None */ + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE , /**< Rising Edge of the input signal generates event trigger*/ + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE , /**< Falling Edge of the input signal generates event + trigger */ + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE /**< Both Rising and Falling edges cause an event trigger*/ +} XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t; + +/** + * External Event trigger criteria - Level sensitivity + */ +typedef enum XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY +{ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH = 0U, /**< Level sensitive functions react to a high signal level*/ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW = 1U, /**< Level sensitive functions react to a low signal level*/ + /* Below enum items can be utilised specific to the functionality */ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW = 0U, /**< Timer counts up, during Low state of the control signal */ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH = 1U /**< Timer counts up, during High state of the control signal */ +} XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t; + +/** + * Low pass filter Configuration. The External Event input should be stable for a selected number of clock cycles. + */ +typedef enum XMC_CCU4_SLICE_EVENT_FILTER +{ + XMC_CCU4_SLICE_EVENT_FILTER_DISABLED = 0U, /**< No Low Pass Filter */ + XMC_CCU4_SLICE_EVENT_FILTER_3_CYCLES , /**< 3 clock cycles */ + XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES , /**< 5 clock cycles */ + XMC_CCU4_SLICE_EVENT_FILTER_7_CYCLES /**< 7 clock cycles */ +} XMC_CCU4_SLICE_EVENT_FILTER_t; + +/** + * External Event Input list. This list depicts the possible input connections to the CCU4 slice. + * Interconnects are specific to each device. + */ +typedef uint8_t XMC_CCU4_SLICE_INPUT_t; + +/** + * Actions that can be performed upon detection of an external Timer STOP event + */ +typedef enum XMC_CCU4_SLICE_END_MODE +{ + XMC_CCU4_SLICE_END_MODE_TIMER_STOP = 0U, /**< Stops the timer, without clearing TIMER register */ + XMC_CCU4_SLICE_END_MODE_TIMER_CLEAR , /**< Without stopping timer, clears the TIMER register */ + XMC_CCU4_SLICE_END_MODE_TIMER_STOP_CLEAR /**< Stops the timer and clears the TIMER register */ +} XMC_CCU4_SLICE_END_MODE_t; + +/** + * Actions that can be performed upon detection of an external Timer START event + */ +typedef enum XMC_CCU4_SLICE_START_MODE +{ + XMC_CCU4_SLICE_START_MODE_TIMER_START = 0U, /**< Start the timer from the current count of TIMER register */ + XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR /**< Clears the TIMER register and start the timer */ +} XMC_CCU4_SLICE_START_MODE_t; + +/** + * Modulation of timer output signals + */ +typedef enum XMC_CCU4_SLICE_MODULATION_MODE +{ + XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_ST_OUT = 0U, /**< Clear ST and OUT signals */ + XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT /**< Clear only the OUT signal */ +} XMC_CCU4_SLICE_MODULATION_MODE_t; + +/** + * Trap exit mode + */ +typedef enum XMC_CCU4_SLICE_TRAP_EXIT_MODE +{ + XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC = 0U, /**< Clear trap state as soon as the trap signal is de-asserted */ + XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW /**< Clear only when acknowledged by software */ +} XMC_CCU4_SLICE_TRAP_EXIT_MODE_t; + +/** + * Timer clear on capture + */ +typedef enum XMC_CCU4_SLICE_TIMER_CLEAR_MODE +{ + XMC_CCU4_SLICE_TIMER_CLEAR_MODE_NEVER = 0U, /**< Never clear the timer on any capture event */ + XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_HIGH , /**< Clear only when timer value has been captured in C3V and C2V */ + XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_LOW , /**< Clear only when timer value has been captured in C1V and C0V */ + XMC_CCU4_SLICE_TIMER_CLEAR_MODE_ALWAYS /**< Always clear the timer upon detection of any capture event */ +} XMC_CCU4_SLICE_TIMER_CLEAR_MODE_t; + +/** + * Multi Channel Shadow transfer request configuration options + */ +typedef enum XMC_CCU4_SLICE_MCMS_ACTION +{ + XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR = 0U, /**< Transfer Compare and Period Shadow register values to + the actual registers upon MCS xfer request */ + XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP = 1U, /**< Transfer Compare, Period and Prescaler Compare Shadow + register values to the actual registers upon MCS xfer + request */ + XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT = 3U /**< Transfer Compare, Period ,Prescaler Compare and Dither + Compare register values to the actual registers upon + MCS xfer request */ +} XMC_CCU4_SLICE_MCMS_ACTION_t; + +/** + * Available Interrupt Event Ids + */ +typedef enum XMC_CCU4_SLICE_IRQ_ID +{ + XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH = 0U , /**< Period match counting up */ + XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH = 1U , /**< Period match -> One match counting down */ + XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP = 2U , /**< Compare match counting up */ + XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN = 3U , /**< Compare match counting down */ + XMC_CCU4_SLICE_IRQ_ID_EVENT0 = 8U , /**< Event-0 occurrence */ + XMC_CCU4_SLICE_IRQ_ID_EVENT1 = 9U , /**< Event-1 occurrence */ + XMC_CCU4_SLICE_IRQ_ID_EVENT2 = 10U, /**< Event-2 occurrence */ + XMC_CCU4_SLICE_IRQ_ID_TRAP = 11U /**< Trap occurrence */ +} XMC_CCU4_SLICE_IRQ_ID_t; + +/** + * Available Interrupt Event Ids, which is added to support multi event APIs + */ +typedef enum XMC_CCU4_SLICE_MULTI_IRQ_ID +{ + XMC_CCU4_SLICE_MULTI_IRQ_ID_PERIOD_MATCH = 0x1U, /**< Period match counting up */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_ONE_MATCH = 0x2U, /**< Period match -> One match counting down */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP = 0x4U, /**< Compare match counting up */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN = 0x8U, /**< Compare match counting down */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT0 = 0x100U, /**< Event-0 occurrence */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT1 = 0x200U, /**< Event-1 occurrence */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT2 = 0x400U, /**< Event-2 occurrence */ +} XMC_CCU4_SLICE_MULTI_IRQ_ID_t; + +/** + * Service Request Lines for CCU4. Event are mapped to these SR lines and these are used to generate the interrupt. + */ +typedef enum XMC_CCU4_SLICE_SR_ID +{ + XMC_CCU4_SLICE_SR_ID_0 = 0U, /**< Service Request Line-0 selected */ + XMC_CCU4_SLICE_SR_ID_1 , /**< Service Request Line-1 selected */ + XMC_CCU4_SLICE_SR_ID_2 , /**< Service Request Line-2 selected */ + XMC_CCU4_SLICE_SR_ID_3 /**< Service Request Line-3 selected */ +} XMC_CCU4_SLICE_SR_ID_t; + +/** + * Slice shadow transfer options. + */ +typedef enum XMC_CCU4_SHADOW_TRANSFER +{ + XMC_CCU4_SHADOW_TRANSFER_SLICE_0 = CCU4_GCSS_S0SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-0 */ + XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_0 = CCU4_GCSS_S0DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-0 */ + XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_0 = CCU4_GCSS_S0PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-0 */ + XMC_CCU4_SHADOW_TRANSFER_SLICE_1 = CCU4_GCSS_S1SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-1 */ + XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_1 = CCU4_GCSS_S1DSE_Msk, /**< Transfer Dither compare shadow register value + to actual registers for SLICE-1 */ + XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_1 = CCU4_GCSS_S1PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-1 */ + XMC_CCU4_SHADOW_TRANSFER_SLICE_2 = CCU4_GCSS_S2SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-2 */ + XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_2 = CCU4_GCSS_S2DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-2 */ + XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_2 = CCU4_GCSS_S2PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-2 */ + XMC_CCU4_SHADOW_TRANSFER_SLICE_3 = CCU4_GCSS_S3SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-3 */ + XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_3 = CCU4_GCSS_S3DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-3 */ + XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_3 = CCU4_GCSS_S3PSE_Msk /**< Transfer Prescaler shadow register value to + actual register for SLICE-3 */ +} XMC_CCU4_SHADOW_TRANSFER_t; + +#if defined(CCU4V3) || defined(DOXYGEN)/* Defined for XMC1400 devices only */ +/** + * Slice shadow transfer mode options. + * @note Only available for XMC1400 series + */ +typedef enum XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE +{ + XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_IN_PERIOD_MATCH_AND_ONE_MATCH = 0U, /**< Shadow transfer is done in Period Match and + One match. */ + XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH = 1U, /**< Shadow transfer is done only in Period Match. */ + XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_ONE_MATCH = 2U /**< Shadow transfer is done only in One Match. */ +} XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t; + + +/** + * Immediate write into configuration register + * @note Only available for XMC1400 series + */ +typedef enum XMC_CCU4_SLICE_WRITE_INTO +{ + XMC_CCU4_SLICE_WRITE_INTO_PERIOD_CONFIGURATION = CCU4_CC4_STC_IRPC_Msk, /**< Immediate or Coherent + Write into Period + Configuration */ + XMC_CCU4_SLICE_WRITE_INTO_COMPARE_CONFIGURATION = CCU4_CC4_STC_IRCC_Msk, /**< Immediate or Coherent + Write into Compare + Configuration */ + XMC_CCU4_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION = CCU4_CC4_STC_IRLC_Msk, /**< Immediate or Coherent + Write into Passive Level + Configuration */ + XMC_CCU4_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRDC_Msk, /**< Immediate or Coherent + Write into Dither Value + Configuration */ + XMC_CCU4_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRFC_Msk /**< Immediate or Coherent + Write into Floating Prescaler + Value Configuration */ +} XMC_CCU4_SLICE_WRITE_INTO_t; + + +/** + * Automatic Shadow Transfer request when writing into shadow register + * @note Only available for XMC1400 series + */ +typedef enum XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO +{ + XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PERIOD_SHADOW = CCU4_CC4_STC_ASPC_Msk, /**< Automatic Shadow + Transfer request when + writing into Period + Shadow Register */ + XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_COMPARE_SHADOW = CCU4_CC4_STC_ASCC_Msk, /**< Automatic Shadow + transfer request + when writing into + Compare Shadow Register */ + XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PASSIVE_LEVEL = CCU4_CC4_STC_ASLC_Msk, /**< Automatic Shadow transfer + request when writing + into Passive Level Register*/ + XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_DITHER_SHADOW = CCU4_CC4_STC_ASDC_Msk, /**< Automatic Shadow transfer + request when writing + into Dither Shadow Register */ + XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_FLOATING_PRESCALER_SHADOW = CCU4_CC4_STC_ASFC_Msk /**< Automatic Shadow transfer + request when writing + into Floating Prescaler Shadow + register */ + +} XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t; +#endif +/** + * Used to create Mask needed for Multi-channel Shadow transfer enable/disable + */ +typedef enum XMC_CCU4_SLICE_MASK +{ + XMC_CCU4_SLICE_MASK_SLICE_0 = 1U , /**< SLICE-0 */ + XMC_CCU4_SLICE_MASK_SLICE_1 = 2U , /**< SLICE-1 */ + XMC_CCU4_SLICE_MASK_SLICE_2 = 4U , /**< SLICE-2 */ + XMC_CCU4_SLICE_MASK_SLICE_3 = 8U /**< SLICE-3 */ +} XMC_CCU4_SLICE_MASK_t; + + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/** + * Configuration data structure of an External Event(Event-0/1/2). + * Needed to configure the various aspects of an External Event. + * This structure will not connect the external event with an external function. + */ +typedef struct XMC_CCU4_SLICE_EVENT_CONFIG +{ + XMC_CCU4_SLICE_INPUT_t mapped_input; /**< Required input signal for the Event */ + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t edge; /**< Select the event edge of the input signal. + This is needed for an edge sensitive External function.*/ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t level; /**< Select the event level of the input signal. + This is needed for an level sensitive External function.*/ + XMC_CCU4_SLICE_EVENT_FILTER_t duration; /**< Low Pass filter duration in terms of fCCU clock cycles */ +} XMC_CCU4_SLICE_EVENT_CONFIG_t; + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Configuration data structure for CCU4 slice. Specifically configures the CCU4 slice to compare mode operation. + * This excludes event and function configuration. + */ +typedef struct XMC_CCU4_SLICE_COMPARE_CONFIG +{ + union + { + struct + { + uint32_t timer_mode : 1; /**< Edge aligned or Centre Aligned. + Accepts enum ::XMC_CCU4_SLICE_TIMER_COUNT_MODE_t */ + uint32_t monoshot : 1; /**< Single shot or Continuous mode . + Accepts enum :: XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t*/ + uint32_t shadow_xfer_clear : 1; /**< Should PR and CR shadow xfer happen when timer is cleared? */ + uint32_t : 10; + uint32_t dither_timer_period: 1; /**< Can the period of the timer dither? */ + uint32_t dither_duty_cycle : 1; /**< Can the compare match of the timer dither? */ + uint32_t : 1; + uint32_t prescaler_mode: 1; /**< Normal or floating prescaler mode. + Accepts enum :: XMC_CCU4_SLICE_PRESCALER_MODE_t*/ + uint32_t : 8; + uint32_t mcm_enable : 1; /**< Multi-Channel mode enable? */ + uint32_t : 6; + }; + uint32_t tc; + }; + uint32_t prescaler_initval : 4; /**< Initial prescaler divider value + Accepts enum :: XMC_CCU4_SLICE_PRESCALER_t */ + uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to */ + uint32_t dither_limit : 4; /**< The value that determines the spreading of dithering */ + uint32_t passive_level : 1; /**< Configuration of ST and OUT passive levels. + Accepts enum :: XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t*/ + uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer if true.*/ +} XMC_CCU4_SLICE_COMPARE_CONFIG_t; + +/** + * Configuration data structure for CCU4 slice. Specifically configures the CCU4 slice to capture mode operation. + * This excludes event and function configuration. + */ +typedef struct XMC_CCU4_SLICE_CAPTURE_CONFIG +{ + union + { + struct + { + uint32_t : 4; + uint32_t fifo_enable : 1; /**< Should the capture registers be setup as a FIFO?(Extended capture mode)*/ + uint32_t timer_clear_mode : 2; /**< How should the timer register be cleared upon detection of capture event? + Accepts enum ::XMC_CCU4_SLICE_TIMER_CLEAR_MODE_t*/ + uint32_t : 4; + uint32_t same_event : 1; /**< Should the capture event for C1V/C0V and C3V/C2V be same capture edge? */ + uint32_t ignore_full_flag : 1; /**< Should updates to capture registers follow full flag rules? */ + uint32_t : 3; + uint32_t prescaler_mode: 1; /**< Normal or floating prescaler Accepts enum :: XMC_CCU4_SLICE_PRESCALER_MODE_t*/ + uint32_t : 15; + }; + uint32_t tc; + }; + uint32_t prescaler_initval : 4; /**< Prescaler divider value */ + uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to */ + uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer */ +} XMC_CCU4_SLICE_CAPTURE_CONFIG_t; +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +__STATIC_INLINE bool XMC_CCU4_IsValidModule(const XMC_CCU4_MODULE_t *const module) +{ + bool tmp = false; + + tmp = (module == CCU40); + +#if defined(CCU41) + tmp = tmp || (module == CCU41); +#endif + +#if defined(CCU42) + tmp = tmp || (module == CCU42); +#endif + +#if defined(CCU43) + tmp = tmp || (module == CCU43); +#endif + + return tmp; +} + +__STATIC_INLINE bool XMC_CCU4_IsValidSlice(const XMC_CCU4_SLICE_t *const slice) +{ + bool tmp = false; + + tmp = (slice == CCU40_CC40); +#if defined(CCU40_CC41) + tmp = tmp || (slice == CCU40_CC41); +#endif +#if defined(CCU40_CC42) + tmp = tmp || (slice == CCU40_CC42); +#endif +#if defined(CCU40_CC43) + tmp = tmp || (slice == CCU40_CC43); +#endif +#if defined(CCU41) + tmp = tmp || (slice == CCU41_CC40); +#if defined(CCU41_CC41) + tmp = tmp || (slice == CCU41_CC41); +#endif +#if defined(CCU41_CC42) + tmp = tmp || (slice == CCU41_CC42); +#endif +#if defined(CCU41_CC43) + tmp = tmp || (slice == CCU41_CC43); +#endif +#endif +#if defined(CCU42) + tmp = tmp || (slice == CCU42_CC40); +#if defined(CCU42_CC41) + tmp = tmp || (slice == CCU42_CC41); +#endif +#if defined(CCU42_CC42) + tmp = tmp || (slice == CCU42_CC42); +#endif +#if defined(CCU42_CC43) + tmp = tmp || (slice == CCU42_CC43); +#endif +#endif +#if defined(CCU43) + tmp = tmp || (slice == CCU43_CC40); +#if defined(CCU43_CC41) + tmp = tmp || (slice == CCU43_CC41); +#endif +#if defined(CCU43_CC42) + tmp = tmp || (slice == CCU43_CC42); +#endif +#if defined(CCU43_CC43) + tmp = tmp || (slice == CCU43_CC43); +#endif +#endif + + return tmp; +} + +/** + * @param module Constant pointer to CCU4 module + * @param mcs_action multi-channel shadow transfer request configuration + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of global register GCTRL.
\n + * As part of module initialization, behaviour of the module upon detection + * Multi-Channel Mode trigger is configured. Will also invoke the XMC_CCU4_EnableModule(). + * The API call would bring up the required CCU4 module and also initialize the module for + * the required multi-channel shadow transfer. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_CompareInit()
XMC_CCU4_SLICE_CaptureInit(). + */ +void XMC_CCU4_Init(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_SLICE_MCMS_ACTION_t mcs_action); + +/** + * @param module Constant pointer to CCU4 module + * @param clock Choice of input clock to the module + * @return
+ * None
+ * + * \parDescription:
+ * Selects the Module Clock by configuring GCTRL.PCIS bits.
\n + * There are 3 potential clock sources. This API helps to select the required clock source. + * Call to this API is valid after the XMC_CCU4_Init(). + * + * \parRelated APIs:
+ * None.
+ */ +void XMC_CCU4_SetModuleClock(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_CLOCK_t clock); + +/** + * @param module Constant pointer to CCU4 module + * @return
+ * None
+ * + * \parDescription:
+ * Enables the CCU4 module and brings it to active state.
\n + * Also disables the gating of the clock signal (if applicable depending on the device being selected). + * Invoke this API before any operations are done on the CCU4 module. Invoked from XMC_CCU4_Init(). + * + * \parRelated APIs:
+ * XMC_CCU4_SetModuleClock()
XMC_CCU4_DisableModule()
XMC_CCU4_StartPrescaler(). + */ +void XMC_CCU4_EnableModule(XMC_CCU4_MODULE_t *const module); + +/** + * @param module Constant pointer to CCU4 module + * @return
+ * None
+ * + * \parDescription:
+ * Brings the CCU4 module to reset state and enables gating of the clock signal(if applicable depending + * on the device being selected).
\n + * Invoke this API when a CCU4 module needs to be disabled completely. + * Any operation on the CCU4 module will have no effect after this API is called. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableModule()
XMC_CCU4_DisableModule(). + */ +void XMC_CCU4_DisableModule(XMC_CCU4_MODULE_t *const module); + +/** + * @param module Constant pointer to CCU4 module + * @return
+ * None
+ * + * \parDescription:
+ * Starts the prescaler and restores clocks to the timer slices, by setting GIDLC.SPRB bit.
\n + * Once the input to the prescaler has been chosen and the prescaler divider of all slices programmed, + * the prescaler itself may be started. Invoke this API after XMC_CCU4_Init() + * (Mandatory to fully initialize the module).Directly accessed register is GIDLC. + * + * \parRelated APIs:
+ * XMC_CCU4_Init()
XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock()
XMC_CCU4_StartPrescaler()
+ * XMC_CCU4_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_StartPrescaler(XMC_CCU4_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU4_StartPrescaler:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + module->GIDLC |= (uint32_t) CCU4_GIDLC_SPRB_Msk; +} + +/** + * @param module Constant pointer to CCU4 module + * @return
+ * None
+ * + * \parDescription:
+ * Stops the prescaler and blocks clocks to the timer slices, by setting GIDLS.CPRB bit.
\n + * Opposite of the StartPrescaler routine. + * Clears the run bit of the prescaler. Ensures that the module clock is not supplied to + * the slices of the module.Registers directly accessed is GIDLS. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock()
XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_StopPrescaler(XMC_CCU4_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU4_StopPrescaler:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + module->GIDLS |= (uint32_t) CCU4_GIDLS_CPRB_Msk; +} + +/** + * @param module Constant pointer to CCU4 module + * @return
+ * None
+ * + * \parDescription:
+ * Returns the state of the prescaler, by reading GSTAT.PRB bit.
\n + * This will return true if the prescaler is running. If clock is being supplied to the slices of the + * module then returns as true. + * + * \parRelated APIs:
+ * XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler()
XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock(). + */ +__STATIC_INLINE bool XMC_CCU4_IsPrescalerRunning(XMC_CCU4_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU4_IsPrescalerRunning:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + return((bool)((module->GSTAT & (uint32_t) CCU4_GSTAT_PRB_Msk) == (uint32_t)CCU4_GSTAT_PRB_Msk)); +} + +/** + * @param module Constant pointer to CCU4 module + * @param clock_mask Slices whose clocks are to be enabled simultaneously. + * Bit location 0/1/2/3 represents slice-0/1/2/3 respectively. + * Range: [0x1 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Enables clocks of multiple slices at a time, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * GIDLC.CS3I bits.\n\n + * Takes an input clock_mask, which determines the slices that would receive the clock. Bring them out + * of the idle state simultaneously. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock(). + */ +__STATIC_INLINE void XMC_CCU4_EnableMultipleClocks(XMC_CCU4_MODULE_t *const module, const uint8_t clock_mask) +{ + XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Wrong clock mask", (clock_mask < 16U)); + + module->GIDLC |= (uint32_t) clock_mask; +} + +/** + * @param module Constant pointer to CCU4 module + * @param slice_number Slice for which the clock should be Enabled. + * Range: [0x0 to 0x3] + * @return
+ * None
+ * + * \parDescription:
+ * Enables the slice timer clock, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * GIDLC.CS3I bits according to the selected \a slice_number.\n\n + * It is possible to enable/disable clock at slice level. This uses the \b slice_number to indicate the + * slice whose clock needs to be enabled. + * + * \parRelated APIs:
+ * XMC_CCU4_DisableClock()
XMC_CCU4_EnableMultipleClocks()
XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_EnableClock(XMC_CCU4_MODULE_t *const module, const uint8_t slice_number) +{ + XMC_ASSERT("XMC_CCU4_EnableClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + XMC_ASSERT("XMC_CCU4_EnableClock:Invalid Slice Number", (slice_number < 4U)); + + module->GIDLC |= ((uint32_t) 1) << slice_number; +} + +/** + * @param module Constant pointer to CCU4 module + * @param slice_number Slice for which the clock should be disabled. + * Range: [0x0 to 0x3] + * @return
+ * None
+ * + * \parDescription:
+ * Disables the slice timer clock, by configuring GIDLS.SS0I, GIDLS.SSS1I, GIDLS.SSS2I, + * GIDLS.SSS3I bits according to the selected \a slice_number .\n\n + * It is possible to disable clock at slice level using the module pointer. + * \b slice_number is used to disable the clock to a given slice of the module. + * Directly accessed Register is GIDLS. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableClock()
XMC_CCU4_EnableMultipleClocks()
XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_DisableClock(XMC_CCU4_MODULE_t *const module, const uint8_t slice_number) +{ + XMC_ASSERT("XMC_CCU4_DisableClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + XMC_ASSERT("XMC_CCU4_DisableClock:Invalid Slice Number", (slice_number < 4U)); + + module->GIDLS |= ((uint32_t) 1) << slice_number; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param compare_init Pointer to slice configuration structure + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of a CC4 slice to compare mode, by configuring CC4yTC, CC4yCMC, CC4yPSC, CC4yDITH, CC4yPSL, + * CC4yFPCS, CC4yCHC registers.\n\n + * CC4 slice is configured with Timer configurations in this routine. + * After initialization user has to explicitly enable the shadow transfer for the required values by calling + * XMC_CCU4_EnableShadowTransfer() with appropriate mask. + * + * \parRelated APIs:
+ * None. + */ +void XMC_CCU4_SLICE_CompareInit(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_COMPARE_CONFIG_t *const compare_init); + +/** + * @param slice Constant pointer to CC4 Slice + * @param capture_init Pointer to slice configuration structure + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of a CC4 slice to capture mode, by configuring CC4yTC, CC4yCMC, CC4yPSC,CC4yFPCS registers.\n\n + * CC4 slice is configured with Capture configurations in this routine.After initialization user has to explicitly + * enable the shadow transfer for the required values by calling XMC_CCU4_EnableShadowTransfer() + * with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_Capture0Config()
XMC_CCU4_SLICE_Capture1Config(). + */ +void XMC_CCU4_SLICE_CaptureInit(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAPTURE_CONFIG_t *const capture_init); + + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Start Function + * @param start_mode Behavior of slice when the start function is activated + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Start Function of the slice, by configuring CC4yCMC.ENDS and CC4yTC.ENDM bits.\n\n + * Start function is mapped with one of the 3 events. An external signal can control when a CC4 timer should start. + * Additionally, the behaviour of the slice upon activation of the start function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StopConfig()
XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_StartConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_START_MODE_t start_mode); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Stop Function + * @param end_mode Behavior of slice when the stop function is activated + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Stop function for the slice, by configuring CC4yCMC.STRTS and CC4yTC.STRM bits.\n\n + * Stop function is mapped with one of the 3 events. An external signal can control when a CCU4 timer should stop. + * Additionally, the behaviour of the slice upon activation of the stop function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartConfig()
XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_StopConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_END_MODE_t end_mode); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External load Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Load Function for the slice, by configuring CC4yCMC.LDS bit.\n\n + * Load function is mapped with one of the 3 events. Up on occurrence of the event,\n + * if CC4yTCST.CDIR set to 0,CC4yTIMER register is reloaded with the value from compare register\n + * if CC4yTCST.CDIR set to 1,CC4yTIMER register is reloaded with the value from period register\n + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_LoadConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Modulation Function + * @param mod_mode Desired Modulation mode + * @param synch_with_pwm Option to synchronize modulation with PWM start + * Pass \b true if the modulation needs to be synchronized with PWM signal. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Output Modulation Function of the slice, by configuring CCeyCMC.MOS, CC4yTC.EMT and + * CC4yTC.EMS bits.\n\n + * Modulation function is mapped with one of the 3 events. The output signal of the CCU can + * be modulated according to a external input. Additionally, the behaviour of the slice upon activation + * of the modulation function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_ModulationConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_MODULATION_MODE_t mod_mode, + const bool synch_with_pwm); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Count Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Count Function of the slice, by configuring CC4yCMC.CNTS bit.\n\n + * Count function is mapped with one of the 3 events. CCU4 slice can take an external + * signal to act as the counting event. The CCU4 slice would count the + * edges present on the \b event selected. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_CountConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Gating Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Gating Function of the slice, by configuring CC4yCMC.GATES bit.\n\n + * Gating function is mapped with one of the 3 events. A CCU4 slice can use an input signal that would + * operate as counter gating. If the configured Active level is detected the counter will gate all the pulses. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_GateConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the Capture-0 Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Capture-0 Function of the slice, by configuring CC4yCMC.CAP0S bit.\n\n + * Capture function is mapped with one of the 3 events. A CCU4 slice can be configured into capture-0 mode + * with the selected \b event. In this mode the CCU4 will capture the timer value into CC4yC0V and CC4yC1V. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_Capture0Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the Capture-1 Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Capture-1 Function of the slice, by configuring CC4yCMC.CAP1S bit.\n\n + * Capture function is mapped with one of the 3 events. A CCU4 slice can be configured into capture-1 + * mode with the selected \b event. In this mode the CCU4 will capture the timer value into CC4yC2V and CC4yC3V. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_Capture1Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * bool would return true if the extended capture read back mode is enabled
+ * + * \parDescription:
+ * Checks if Extended capture mode read is enabled for particular slice or not, by reading CC4yTC.ECM bit.\n\n + * In this mode the there is only one associated read address for all the capture registers. + * Individual capture registers can still be accessed in this mode. + * + * \parRelated APIs:
+ * XMC_CCU4_GetCapturedValueFromFifo(). + */ +__STATIC_INLINE bool XMC_CCU4_SLICE_IsExtendedCapReadEnabled(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_IsExtendedCapReadEnabled:Invalid Module Pointer", XMC_CCU4_IsValidSlice(slice)); + return((bool)((slice->TC & (uint32_t) CCU4_CC4_TC_ECM_Msk) == (uint32_t)CCU4_CC4_TC_ECM_Msk)); +} + +#if defined(CCU4V1) /* Defined for XMC4500, XMC4400, XMC4200, XMC4100 devices only */ +/** + * @param module Constant pointer to CCU4 module + * @param slice_number to check whether read value belongs to required slice or not + * @return
+ * int32_t Returns -1 if the FIFO value being retrieved is not from the \b slice_number. + * Returns the value captured in the \b slice_number, if captured value is from the correct slice. + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Read captured value from FIFO(ECRD register).\n\n + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * derived/inferred from the captured values. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_IsExtendedCapReadEnabled(). + * @note Only available for XMC4500, XMC4400, XMC4200 and XMC4100 series + */ +int32_t XMC_CCU4_GetCapturedValueFromFifo(const XMC_CCU4_MODULE_t *const module, const uint8_t slice_number); +#else +/** + * @param slice Constant pointer to CC4 Slice + * @param set The capture register set from which the captured value is to be retrieved + * @return
+ * uint32_t Returns the value captured in the \b slice_number + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Read captured value from FIFO(CC4yECRD0 and CC4yECRD1).\n\n + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * derived/inferred from the captured values. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_IsExtendedCapReadEnabled(). + * @note Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only. For other devices use XMC_CCU4_GetCapturedValueFromFifo() API + */ +uint32_t XMC_CCU4_SLICE_GetCapturedValueFromFifo(const XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAP_REG_SET_t set); +#endif + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Count Direction Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Count Direction of the slice, by configuring CC4yCMC.UDS bit.\n\n + * Count direction function is mapped with one of the 3 events. A slice can be configured to change the + * CC4yTIMER count direction depending on an external signal. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_DirectionConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Configures the status bit override Function of the slice, by configuring CC4yCMC.OFS bit.\n\n + * Status bit override function is mapped with one of the 3 events. A slice can be configured to change the + * output of the timer's CC4yST signal depending on an external signal. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(). + */ +void XMC_CCU4_SLICE_StatusBitOverrideConfig(XMC_CCU4_SLICE_t *const slice); + +/** + * @param slice Constant pointer to CC4 Slice + * @param exit_mode How should a previously logged trap state be exited? + * @param synch_with_pwm Should exit of trap state be synchronized with PWM cycle start? + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Trap Function of the slice, by configuring CC4yCMC.TS, CC4yTC.TRPSE, and CC4yTC.TRPSW bits.\n\n + * Trap function is mapped with Event-2. Criteria for exiting the trap state is configured. + * This trap function allows PWM outputs to react on the state of an input pin. + * Thus PWM output can be forced to inactive state upon detection of a trap. + * It is also possible to synchronize the trap function with the PWM signal using the \b synch_with_pwm. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_TrapConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_TRAP_EXIT_MODE_t exit_mode, + bool synch_with_pwm); + + +/** + * @param slice Constant pointer to CC4 Slice + * @param ev1_config Pointer to event 1 configuration data + * @param ev2_config Pointer to event 2 configuration data + * @return
+ * None
+ * + * + * \parDescription:
+ * Map Status bit override function with an Event1 & Event 2 of the slice and configure CC4yINS register.\n\n + * Details such as the input mapped to the event, event detection criteria and Low Pass filter options are programmed + * by this routine for the events 1 & 2. Event-1 input would be the trigger to override the value. + * Event-2 input would be the override value. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StatusBitOverrideConfig(). + */ +void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev2_config); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event The External Event which needs to be configured. + * @param config Pointer to event configuration data. + * @return
+ * None
+ * + * \parDescription:
+ * Configures an External Event of the slice, by updating CC4yINS register .\n\n + * Details such as the input mapped to the event, event detection criteria and low pass filter + * options are programmed by this routine. The Event \b config will configure the input selection, + * the edge selection, the level selection and the Low pass filter for the event. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartConfig()
XMC_CCU4_SLICE_StopConfig()
XMC_CCU4_SLICE_LoadConfig()
+ * XMC_CCU4_SLICE_ModulationConfig()
XMC_CCU4_SLICE_CountConfig()
XMC_CCU4_SLICE_GateConfig()
+ * XMC_CCU4_SLICE_Capture0Config()
XMC_CCU4_SLICE_Capture1Config()
XMC_CCU4_SLICE_DirectionConfig()
+ * XMC_CCU4_SLICE_StatusBitOverrideConfig()
XMC_CCU4_SLICE_TrapConfig(). + */ +void XMC_CCU4_SLICE_ConfigureEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const config); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event The External Event which needs to be configured. + * @param input One of the 16 inputs meant to be mapped to the desired event + * @return
+ * None
+ * + * + * \parDescription:
+ * Selects an input for an external event, by configuring CC4yINS register.\n\n + * It is possible to select one of the possible 16 input signals for a given Event. + * This configures the CC4yINS.EVxIS for the selected event. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartConfig()
XMC_CCU4_SLICE_StopConfig()
XMC_CCU4_SLICE_LoadConfig()
+ * XMC_CCU4_SLICE_ModulationConfig()
XMC_CCU4_SLICE_CountConfig()
XMC_CCU4_SLICE_GateConfig()
+ * XMC_CCU4_SLICE_Capture0Config()
XMC_CCU4_SLICE_Capture1Config()
XMC_CCU4_SLICE_DirectionConfig()
+ * XMC_CCU4_SLICE_StatusBitOverrideConfig()
XMC_CCU4_SLICE_TrapConfig(). + */ +void XMC_CCU4_SLICE_SetInput(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_INPUT_t input); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Enables the trap feature, by setting CC4yTC.TRAPE0, CC4yTC.TRAPE1, CC4yTC.TRAPE2 and CC4yTC.TRAPE3 bit based on the + * \a out_mask.\n\n + * A particularly useful feature where the PWM output can be forced inactive upon detection of a trap. The trap signal + * can be the output of a sensing element which has just detected an abnormal electrical condition. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_TrapConfig()
XMC_CCU4_SLICE_DisableTrap()
XMC_CCU4_SLICE_ConfigureEvent()
+ * XMC_CCU4_SLICE_SetInput(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableTrap(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableTrap:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC |= (uint32_t) CCU4_CC4_TC_TRAPE_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables the trap feature, by clearing CC4yTC.TRAPE0, CC4yTC.TRAPE1, CC4yTC.TRAPE2 and CC4yTC.TRAPE3 bit based on the + * \a out_mask.\n\n.\n\n + * This API will revert the changes done by XMC_CCU4_SLICE_EnableTrap(). + * This Ensures that the TRAP function has no effect on the output of the CCU4 slice. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableTrap(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableTrap(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableTrap:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU4_CC4_TC_TRAPE_Msk); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * bool returns \b true if the Timer is running else it returns \b false. + * + * \parDescription:
+ * Returns the state of the timer (Either Running or stopped(idle)), by reading CC4yTCST.TRB bit. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartTimer()
XMC_CCU4_SLICE_StopTimer(). + */ +__STATIC_INLINE bool XMC_CCU4_SLICE_IsTimerRunning(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetTimerStatus:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return (bool)(((slice->TCST) & CCU4_CC4_TCST_TRB_Msk) == CCU4_CC4_TCST_TRB_Msk); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * ::XMC_CCU4_SLICE_TIMER_COUNT_DIR_t returns the direction in which the timer is counting. + * + * \parDescription:
+ * Returns the timer counting direction, by reading CC4yTCST.CDIR bit.\n\n + * This API will return the direction in which the timer is currently + * incrementing(XMC_CCU4_SLICE_TIMER_COUNT_DIR_UP) or decrementing (XMC_CCU4_SLICE_TIMER_COUNT_DIR_DOWN). + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_CCU4_SLICE_TIMER_COUNT_DIR_t XMC_CCU4_SLICE_GetCountingDir(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetCountingDir:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((XMC_CCU4_SLICE_TIMER_COUNT_DIR_t)(((slice->TCST) & CCU4_CC4_TCST_CDIR_Msk) >> CCU4_CC4_TCST_CDIR_Pos)); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Starts the timer counting operation, by setting CC4yTCSET.TRBS bit.\n\n + * It is necessary to have configured the CC4 slice before starting its timer. + * Before the Timer is started ensure that the clock is provided to the slice. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StopTimer(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_StartTimer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_StartTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TCSET = CCU4_CC4_TCSET_TRBS_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Stops the Timer.
\n + * Timer counting operation can be stopped by invoking this API, by setting CC4yTCCLR.TRBC bit. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_StopTimer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_StopTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TCCLR = (uint32_t) CCU4_CC4_TCCLR_TRBC_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Resets the timer count to zero, by setting CC4yTCCLR.TCC bit.\n\n + * A timer which has been stopped can still retain the last counted value. + * After invoking this API the timer value will be cleared. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_ClearTimer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_ClearTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TCCLR = (uint32_t) CCU4_CC4_TCCLR_TCC_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Stops and resets the timer count to zero, by setting CC4yTCCLR.TCC and CC4yTCCLR.TRBC bit.\n\n + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_StopClearTimer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_StopClearTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TCCLR = CCU4_CC4_TCCLR_TRBC_Msk | CCU4_CC4_TCCLR_TCC_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * ::XMC_CCU4_SLICE_MODE_t returns XMC_CCU4_SLICE_MODE_COMPARE if the slice is operating in compare mode + * returns XMC_CCU4_SLICE_MODE_CAPTURE if the slice is operating in capture mode + * + * \parDescription:
+ * Retrieves the current mode of operation in the slice (either Capture mode or Compare mode), by reading + * CC4yTC.CMOD bit.\n\n + * Ensure that before invoking this API the CCU4 slice should be configured otherwise the output of this API is + * invalid. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_CCU4_SLICE_MODE_t XMC_CCU4_SLICE_GetSliceMode(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetSliceMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((XMC_CCU4_SLICE_MODE_t)(((slice->TC) & CCU4_CC4_TC_CMOD_Msk) >> CCU4_CC4_TC_CMOD_Pos)); +} +/** + * @param slice Constant pointer to CC4 Slice + * @param mode Desired repetition mode (Either single shot or Continuous) + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Timer to either Single shot mode or continuous mode, by configuring CC4yTC.TSSM bit.\n\n + * The timer will count up to the terminal count as specified in the period register and stops immediately if the repeat + * mode has been set to single shot. In the continuous mode of operation, the timer starts counting all over again after + * reaching the terminal count. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetTimerRepeatMode(). + */ +void XMC_CCU4_SLICE_SetTimerRepeatMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t mode); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * ::XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t returns XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT if continuous mode is selected + * returns XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE if single shot mode is selected + * + * \parDescription:
+ * Retrieves the Timer repeat mode, either Single shot mode or continuous mode, by reading CC4yTC.TSSM bit.\n\n + * The timer will count up to the terminal count as specified in the period register and stops immediately if the repeat + * mode has been set to single shot mode. In the continuous mode of operation, the timer starts counting + * all over again after reaching the terminal count. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetTimerRepeatMode(). + */ +__STATIC_INLINE XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t XMC_CCU4_SLICE_GetTimerRepeatMode( + const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TSSM_Msk) >> CCU4_CC4_TC_TSSM_Pos)); +} +/** + * @param slice Constant pointer to CC4 Slice + * @param mode Desired counting mode (Either Edge Aligned or Center Aligned) + * @return
+ * None
+ * + * \parDescription:
+ * Configures the timer counting mode either Edge Aligned or Center Aligned, by configuring CC4yTC.TCM bit.\n\n + * In the edge aligned mode, the timer counts from 0 to the terminal count. Once the timer count has reached a preset + * compare value, the timer status output asserts itself. It will now deassert only after the timer count reaches the + * terminal count.\n In the center aligned mode, the timer first counts from 0 to the terminal count and then back to 0. + * During this upward and downward counting, the timer status output stays asserted as long as the timer value is + * greater than the compare value. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetTimerCountingMode(). + */ +void XMC_CCU4_SLICE_SetTimerCountingMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_COUNT_MODE_t mode); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * ::XMC_CCU4_SLICE_TIMER_COUNT_MODE_t returns XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA if edge aligned mode is selected + * returns XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA if center aligned mode is selected + * + * \parDescription:
+ * Retrieves timer counting mode either Edge aligned or Center Aligned, by reading CC4yTC.TCM bit.\n\n + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetTimerCountingMode(). + */ +__STATIC_INLINE XMC_CCU4_SLICE_TIMER_COUNT_MODE_t XMC_CCU4_SLICE_GetTimerCountingMode( + const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetTimerCountingMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((XMC_CCU4_SLICE_TIMER_COUNT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TCM_Msk) >> CCU4_CC4_TC_TCM_Pos)); +} +/** + * @param slice Constant pointer to CC4 Slice + * @param period_val Timer period value + * Range: [0x0 to 0xFFFF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer period, by writing CC4yPRS register.\n\n + * The frequency of counting/ PWM frequency is determined by this value. The period value is written to a shadow + * register. Explicitly enable the shadow transfer for the the period value by calling + * XMC_CCU4_EnableShadowTransfer() with appropriate mask. If shadow transfer is enabled and the timer is running, + * a period match transfers the value from the shadow register to the actual period register. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetTimerPeriodMatch(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetTimerPeriodMatch(XMC_CCU4_SLICE_t *const slice, const uint16_t period_val) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->PRS = (uint32_t) period_val; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * uint16_t returns the current timer period value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the timer period value currently effective, by reading CC4yPR register.\n\n + * If the timer is active then the value being returned is currently being used for the PWM period. + * + * \parNote:
+ * The XMC_CCU4_SLICE_SetTimerPeriodMatch() would set the new period value to a shadow register. + * This would only transfer the new values into the actual period register if the shadow transfer request + * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU4_SLICE_GetTimerPeriodMatch() + * would not reflect the new values until the shadow transfer completes. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetTimerPeriodMatch(). + */ +__STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerPeriodMatch(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((uint16_t)slice->PR); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param compare_val Timer compare value + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer compare value, by writing CC4yCRS register.
\n + * The PWM duty cycle is determined by this value. + * The compare value is written to a shadow register. Explicitly enable the shadow transfer for + * the the period/compare value by calling XMC_CCU4_EnableShadowTransfer() with + * appropriate mask.If shadow transfer is enabled and the timer is running, + * a period match transfers the value from the shadow register to the actual compare register. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetTimerPeriodMatch(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetTimerCompareMatch(XMC_CCU4_SLICE_t *const slice, const uint16_t compare_val) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->CRS = (uint32_t) compare_val; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * uint16_t returns the current timer compare value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the timer compare value currently effective, by reading CC4yCRS register.\n\n + * If the timer is active then the value being returned is currently being for the PWM duty cycle( timer compare value). + * + * \parNote:
+ * The XMC_CCU4_SLICE_SetTimerCompareMatch() would set the new compare value to a shadow register. + * This would only transfer the new values into the actual compare register if the shadow transfer request + * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU4_SLICE_GetTimerCompareMatch() + * would not reflect the new values until the shadow transfer completes. + * Directly accessed Register is CC4yCR. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetTimerCompareMatch(). + */ +__STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerCompareMatch(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((uint16_t)slice->CR); +} + +/** + * @param module Constant pointer to CCU4 module + * @param shadow_transfer_msk Shadow transfer request mask for various transfers. + * Use ::XMC_CCU4_SHADOW_TRANSFER_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Requests of shadow transfer for Period, Compare, Passive level, dither and prescaler, by configuring + * the GCSS register.\n\n + * The transfer from the shadow registers to the actual registers is done in the immediate next occurrence of the + * shadow transfer trigger after the API is called. + * + * Any call to XMC_CCU4_SLICE_SetTimerPeriodMatch()
XMC_CCU4_SLICE_SetTimerCompareMatch()
+ * XMC_CCU4_SLICE_SetPrescaler()
XMC_CCU4_SLICE_CompareInit()
XMC_CCU4_SLICE_CaptureInit(). + * must be succeeded by this API. + * Directly accessed Register is GCSS. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_CCU4_EnableShadowTransfer(XMC_CCU4_MODULE_t *const module, const uint32_t shadow_transfer_msk) +{ + XMC_ASSERT("XMC_CCU4_EnableShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidModule(module)); + module->GCSS = (uint32_t)shadow_transfer_msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * uint16_t returns the current timer value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the latest timer value, from CC4yTIMER register.\n\n + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetTimerValue(). + */ +__STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerValue(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((uint16_t)slice->TIMER); +} +/** + * @param slice Constant pointer to CC4 Slice + * @param timer_val The new timer value that has to be loaded into the TIMER register. + * Range: [0x0 to 0xFFFF] + * @return
+ * None
+ * + * \parDescription:
+ * Loads a new timer value, by setting CC4yTIMER register.\n\n + * + * \parNote:
+ * Request to load is ignored if the timer is running. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetTimerValue(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetTimerValue(XMC_CCU4_SLICE_t *const slice, const uint16_t timer_val) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TIMER = (uint32_t) timer_val; +} +/** + * @param slice Constant pointer to CC4 Slice + * @param period_dither Boolean instruction on dithering of period match + * @param duty_dither Boolean instruction on dithering of compare match + * @param spread Dither compare value + * @return
+ * None
+ * + * \parDescription:
+ * Enables dithering of PWM frequency and duty cycle, by configuring CC4yTC.DITHE and CC4yDITS bits.\n\n + * Some control loops are slow in updating PWM frequency and duty cycle. In such a case, a Bresenham style dithering + * can help reduce long term errors. Dithering can be applied to period and duty individually, + * this can be selected using the parameter \b period_dither and \b duty_dither. + * The \b spread would provide the dither compare value. If the dither counter value is less than this \b spread then + * the period/compare values would be dithered according to the dither mode selected. This API would invoke + * XMC_CCU4_SLICE_SetDitherCompareValue(). + * + * \parNote:
+ * After this API call, XMC_CCU4_EnableShadowTransfer() has to be called with appropriate mask + * to transfer the dither value. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_DisableDithering(). + */ +void XMC_CCU4_SLICE_EnableDithering(XMC_CCU4_SLICE_t *const slice, + const bool period_dither, + const bool duty_dither, + const uint8_t spread); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables dithering of PWM frequency and duty cycle, by clearing CC4yTC.DITHE bits.\n\n + * This disables the Dither mode that was set in XMC_CCU4_SLICE_EnableDithering(). + * This API will not clear the dither compare value. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableDithering(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableDithering(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableDithering:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU4_CC4_TC_DITHE_Msk); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Enables the floating prescaler, by setting CC4yTC.FPE bit.\n\n + * The prescaler divider starts with an initial value and increments upon every period match. It keeps incrementing + * until a ceiling (prescaler compare value) is hit and thereafter rolls back to the original prescaler divider value.\n + * It is necessary to have programmed an initial divider value and a compare value before the feature is enabled. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue()
XMC_CCU4_SLICE_DisableFloatingPrescaler()
+ * XMC_CCU4_SLICE_SetPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableFloatingPrescaler(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC |= (uint32_t) CCU4_CC4_TC_FPE_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables the floating prescaler, by clearing CC4yTC.FPE bit.\n\n + * This would return the prescaler to the normal mode. + * The prescaler that would be applied is the value present in CC4yPSC. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableFloatingPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableFloatingPrescaler(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU4_CC4_TC_FPE_Msk); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param comp_val Dither compare value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Sets the dither spread/compare value, by setting CC4yDITS.DCVS bits.\n\n + * This value is the cornerstone of PWM dithering feature. Dithering is applied/done when the value in the + * dithering counter is less than this compare/spread value. For all dithering counter values greater than + * the spread value, there is no dithering. After setting the value XMC_CCU4_EnableShadowTransfer() has to be + * called with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableDithering(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetDitherCompareValue(XMC_CCU4_SLICE_t *const slice, const uint8_t comp_val) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetDitherCompareValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->DITS = comp_val; +} +/** + * @param slice Constant pointer to CC4 Slice + * @param div_val Prescaler divider value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the slice specific prescaler divider, by configuring the CC4yPSC and CC4yFPC registers.\n\n + * The prescaler divider may only be programmed after the prescaler run bit has been cleared + * by calling XMC_CCU4_StopPrescaler(). + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue(). + */ +void XMC_CCU4_SLICE_SetPrescaler(XMC_CCU4_SLICE_t *const slice, const uint8_t div_val); + +/** + * @param slice Constant pointer to CC4 Slice + * @param cmp_val Prescaler divider compare value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the slice specific prescaler divider compare value, by configuring CC4yFPCS register.\n\n + * The compare value is applicable only in floating mode of operation. The prescaler divider starts with an initial + * value and increments to the compare value steadily upon every period match. Once prescaler divider + * equals the prescaler divider compare value, the value in the former resets back to the PVAL (from FPC). After setting + * the value, XMC_CCU4_EnableShadowTransfer() has to be called with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue(XMC_CCU4_SLICE_t *const slice, + const uint8_t cmp_val) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + /* write to the shadow register */ + slice->FPCS = (uint32_t) cmp_val; +} +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Enables the multichannel mode, by setting CC4yTC.MCME bit.
\n + * The output state of the Timer slices can be controlled in parallel by a single input signal. + * A particularly useful feature in motor control applications where the PWM output of multiple slices of a module can + * be gated and ungated by multi-channel gating inputs connected to the slices. A peripheral like POSIF connected to the + * motor knows exactly which of the power drive switches are to be turned on and off at any instant. It can thus through + * a gating bus (known as multi-channel inputs) control which of the slices output stays gated/ungated. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_DisableMultiChannelMode()
XMC_CCU4_SetMultiChannelShadowTransferMode(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableMultiChannelMode(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableMultiChannelMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC |= (uint32_t) CCU4_CC4_TC_MCME_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables the multichannel mode, by clearing CC4yTC.MCME bit.
\n + * This would return the slices to the normal operation mode. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableMultiChannelMode(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableMultiChannelMode(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableMultiChannelMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU4_CC4_TC_MCME_Msk); +} + +/** + * @param module Constant pointer to CCU4 module + * @param slice_mode_msk Slices for which the configuration has to be applied. + * Use ::XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Enables the Multi-channel shadow transfer request trigger signal either by software or hardware by configuring + * GCTRL.MSE0, GCTRL.MSE1, GCTRL.MSE2, and GCTRL.MSE3 based on the mask.\n\n + * The shadow transfer would take place either if it was requested by software or by the CCU4x.MCSS input. + * + * \parRelated APIs:
+ * None. +*/ +void XMC_CCU4_SetMultiChannelShadowTransferMode(XMC_CCU4_MODULE_t *const module, const uint32_t slice_mode_msk); + +/** + * @param slice Constant pointer to CC4 Slice + * @param reg_num The capture register from which the captured value is to be retrieved + * Range: [0,3] + * @return
+ * uint32_t Returns the Capture register value. + * Range: [0 to 0x1FFFFF] + * + * \parDescription:
+ * Retrieves timer value which has been captured in the Capture registers, by reading CC4yCV[\b reg_num] register.\n\n + * The signal whose timing characteristics are to be measured must be mapped to an event which in turn must be mapped + * to the capture function. Based on the capture criteria, the timer values are captured into capture registers. Timing + * characteristics of the input signal may then be derived/inferred from the captured values. The full flag will help + * to find out if there is a new captured value present. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetLastCapturedTimerValue(). + */ +uint32_t XMC_CCU4_SLICE_GetCaptureRegisterValue(const XMC_CCU4_SLICE_t *const slice, const uint8_t reg_num); + +/** + * @param slice Constant pointer to CC4 Slice + * @param set The capture register set, which must be evaluated + * @param val_ptr Out Parameter of the API.Stores the captured timer value into this out parameter. + * @return
+ * ::XMC_CCU4_STATUS_t Returns XMC_CCU4_STATUS_OK if there was new value present in the capture registers. + * returns XMC_CCU4_STATUS_ERROR if there was no new value present in the capture registers. + * + * \parDescription:
+ * Retrieves the latest captured timer value, by reading CC4yCV registers.\n\n + * Retrieve the timer value last stored by the slice. When separate capture events are used, + * users must specify the capture set to evaluate. If single capture event mode is used, all 4 capture registers are + * evaluated.\n + * The lowest register is evaluated first followed by the next higher ordered register and this continues until all + * capture registers have been evaluated. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetCaptureRegisterValue(). + */ +XMC_CCU4_STATUS_t XMC_CCU4_SLICE_GetLastCapturedTimerValue(const XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Enables the generation of an interrupt pulse for the event, by configuring CC4yINTE register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API merely enables the event. Binding with SR is performed by another API. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableMultipleEvents()
XMC_CCU4_SLICE_DisableEvent()
+ * XMC_CCU4_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_EnableEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + slice->INTE |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param intr_mask Event mask such that multiple events can be enabled. + * Use ::XMC_CCU4_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Enables the generation of an interrupt pulse for the required events, by configuring CC4yINTE register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API merely enables the events. Binding with SR is performed by another API. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_DisableEvent()
+ * XMC_CCU4_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableMultipleEvents(XMC_CCU4_SLICE_t *const slice, const uint16_t intr_mask) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableMultipleEvents:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->INTE |= (uint32_t)intr_mask; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Disables the generation of an interrupt pulse for the event, by clearing CC4yINTE register.\n\n + * Prevents the event from being asserted + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_EnableMultipleEvents()
+ * XMC_CCU4_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_DisableEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + slice->INTE &= ~(((uint32_t) 1) << ((uint32_t) event)); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param mask Event mask such that multiple events can be enabled. + * Use ::XMC_CCU4_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Disables the generation of an interrupt pulse for the required events, by clearing CC4yINTE register.\n\n + * Prevents selected events of the slice from being asserted. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_EnableMultipleEvents()
+ * XMC_CCU4_SLICE_DisableEvent(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableMultipleEvents(XMC_CCU4_SLICE_t *const slice, const uint16_t mask) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableMultipleEvents:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->INTE &= ~((uint32_t) mask); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Manually asserts the requested event, by setting CC4ySWS register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API manually asserts the requested event. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_EnableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetEvent(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + slice->SWS |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Asserted event which must be acknowledged. + * @return
+ * None
+ * + * \parDescription:
+ * Acknowledges an asserted event, by setting CC4ySWR with respective event flag.\n\n + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent()
XMC_CCU4_SLICE_GetEvent(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_ClearEvent(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU4_SLICE_ClearEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_ClearEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + slice->SWR |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Event to be evaluated for assertion + * @return
+ * bool Returns true if event is set else false is returned. + * + * \parDescription:
+ * Evaluates if a given event is asserted or not, by reading CC4yINTS register.\n\n + * Return true if the event is asserted. For a event to be asserted it has to be + * first enabled. Only if that event is enabled the call to this API is valid. + * If the Event is enabled and has not yet occurred then a false is returned. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent(). + */ +__STATIC_INLINE bool XMC_CCU4_SLICE_GetEvent(const XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_GetEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + + return(((uint32_t)(slice->INTS & ((uint32_t)1 << (uint32_t)event))) != 0U); +} +/** + * @param slice Constant pointer to CC4 Slice + * @param event Event which must be bound to a service request line + * @param sr The Service request line which is bound to the \b event + * @return
+ * None
+ * + * \parDescription:
+ * Binds requested event to a service request line, by configuring CC4ySRS register with respective event.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API binds the requested event with the requested service request line(\b sr). + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent(). + */ +void XMC_CCU4_SLICE_SetInterruptNode(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_IRQ_ID_t event, + const XMC_CCU4_SLICE_SR_ID_t sr); + +/** + * @param slice Constant pointer to CC4 Slice + * @param level Slice output passive level + * @return
+ * None
+ * + * \parDescription:
+ * Configures the passive level for the slice output, by setting CC4yPSL register.\n\n + * Defines the passive level for the timer slice output pin. Selects either level high is passive + * or level low is passive. This is the level of the output before the compare match is value changes it. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent(). + */ +void XMC_CCU4_SLICE_SetPassiveLevel(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t level); + +#if defined(CCU4V3) || defined(DOXYGEN) /* Defined for XMC1400 devices only */ +/** + * @param slice Constant pointer to CC4 Slice + * + * @return
+ * None
+ * + * \parDescription:
+ * Cascades the shadow transfer operation throughout the CCU4 timer slices, by setting CSE bit in STC register.\n\n + * + * The shadow transfer enable bits needs to be set in all timer slices, that are being used in the cascaded architecture, + * at the same time. The shadow transfer enable bits, also need to be set for all slices even if the shadow values of + * some slices were not updated. It is possible to to cascade with the adjacent slices only. CC40 slice is a + * master to start the operation. + * + * \parNote:
+ * XMC_CCU4_EnableShadowTransfer() must be called to enable the shadow transfer of the all the slices, which needs to be + * cascaded. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableShadowTransfer(), XMC_CCU4_SLICE_DisableCascadedShadowTransfer()
. + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableCascadedShadowTransfer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC |= (uint32_t) CCU4_CC4_STC_CSE_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * + * @return
+ * None
+ * + * \parDescription:
+ * Disables the cascaded the shadow transfer operation, by clearing CSE bit in STC register.\n\n + * + * If in any slice the cascaded mode disabled, other slices from there onwards does not update the values in cascaded mode. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableCascadedShadowTransfer()
. + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableCascadedShadowTransfer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC &= ~(uint32_t) CCU4_CC4_STC_CSE_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param shadow_transfer_mode mode to be configured + * Use :: XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t enum items for mode + * @return
+ * None
+ * + * \parDescription:
+ * Configures when the shadow transfer has to occur, by setting STM bit in STC register.\n\n + * + * After requesting for shadow transfer mode using XMC_CCU4_EnableShadowTransfer(), actual transfer occurs based on the + * selection done using this API (i.e. on period and One match, on Period match only, on One match only). + * + * \parNote:
+ * This is effective when the timer is configured in centre aligned mode. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableShadowTransfer()
+ * @note Only available for XMC1400 series +*/ +__STATIC_INLINE void XMC_CCU4_SLICE_SetShadowTransferMode(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t shadow_transfer_mode) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetShadowTransferMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC = ((slice->STC) & ~(uint32_t)((uint32_t)CCU4_CC4_STC_STM_Msk << (uint32_t)CCU4_CC4_STC_STM_Pos)) | + ((shadow_transfer_mode << CCU4_CC4_STC_STM_Pos) & (uint32_t)CCU4_CC4_STC_STM_Msk); +} + + /** + * @param slice Constant pointer to CC4 Slice + * @param coherent_write specifies for what fields this mode has to be applied + * Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the specified fields shadow value to be updated in synchronous with PWM after shadow transfer request, by + * clearing IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n + * + * When coherent shadow is enabled, after calling XMC_CCU4_EnableShadowTransfer(), the value which are written in the + * respective shadow registers get updated according the configuration done using XMC_CCU4_SLICE_SetShadowTransferMode() + * API. \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU4_EnableShadowTransfer(), XMC_CCU4_SLICE_SetShadowTransferMode()
+ * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle(XMC_CCU4_SLICE_t *const slice, + const uint32_t coherent_write) +{ + XMC_ASSERT("XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC &= ~(uint32_t)coherent_write; +} + + /** + * @param slice Constant pointer to CC4 Slice + * @param immediate_write specifies for what fields this mode has to be applied + * Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the specified fields shadow value to be updated immediately after shadow transfer request, by setting + * IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n + * + * When immediate shadow is enabled, by calling XMC_CCU4_EnableShadowTransfer() the value which are written in the + * shadow registers get updated to the actual registers immediately. \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU4_EnableShadowTransfer()
+ * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer(XMC_CCU4_SLICE_t *const slice, + const uint32_t immediate_write) +{ + XMC_ASSERT("XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC |= immediate_write; +} + + /** + * @param slice Constant pointer to CC4 Slice + * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request is generated + * Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a + * bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configure on which shadow register update, automatic shadow transfer request generation has to be enabled. By setting + * ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n + * + * By updating the configured shadow register, the shadow transfer request is generated to update all the shadow registers. + * \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest(). + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t *const slice, + const uint32_t automatic_shadow_transfer) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC |= automatic_shadow_transfer; +} + + /** + * @param slice Constant pointer to CC4 Slice + * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request should not be + * generated + * Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a + * bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configure on which shadow register update, automatic shadow transfer request generation has to be disabled. By + * clearing ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n + * + * This disables the generation of automatic shadow transfer request for the specified register update. + * \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest(). + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t *const slice, + const uint32_t automatic_shadow_transfer) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC &= ~(uint32_t)automatic_shadow_transfer; +} +#endif +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CCU40) */ + +#endif /* CCU4_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ccu8.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ccu8.h new file mode 100644 index 00000000..8b732444 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ccu8.h @@ -0,0 +1,2929 @@ +/** + * @file xmc_ccu8.h + * @date 2016-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Documentation updates
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * - Added XMC_CCU8_SLICE_LoadSelector() API, to select which compare register value has to be loaded + * during external load event. + * + * 2015-07-01: + * - In XMC_CCU8_SLICE_CHECK_INTERRUPT macro, fixed the missing item for compare match down for channel 2.
+ * + * 2015-07-24: + * - XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
+ * + * 2015-08-17: + * - XMC_CCU8_SLICE_PRESCALER_t enum is added to set the prescaler divider.
+ * - XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t is added for all the devices except XMC45 devices, to set when the + * shadow transfer has to happen.
+ * - XMC_CCU8_SOURCE_OUT0_t, XMC_CCU8_SOURCE_OUT1_t, XMC_CCU8_SOURCE_OUT2_t, XMC_CCU8_SOURCE_OUT3_t enums are added + * to maps one of the ST to OUT0, OUT1, OUT3, OUT4 signals. + * - In XMC_CCU8_SLICE_COMPARE_CONFIG_t structure, selector_out0, selector_out1, selector_out2, selector_out3 are + * added to support XMC14 devices. + * - XMC_CCU8_EnableShadowTransfer() API is made as inline, to improve the speed.
+ * - XMC_CCU8_SLICE_EnableCascadedShadowTransfer(), XMC_CCU8_SLICE_DisableCascadedShadowTransfer(), + * XMC_CCU8_SLICE_SetShadowTransferMode() API are supported for all the devices except XMC45. + * + * 2015-09-29: + * - In XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_t, two more enum items are added to support external count direction + * settings. + * + * 2015-10-07: + * - XMC_CCU8_SLICE_SetTimerCompareMatchChannel1(), XMC_CCU8_SLICE_SetTimerCompareMatchChannel2() inline APIs are + * added to update the respective compare registers directly. + * - XMC_CCU8_SLICE_GetEvent() is made as inline. + * - XMC_CCU8_SLICE_MULTI_IRQ_ID_t is added to support the XMC_CCU8_SLICE_EnableMultipleEvents() and + * XMC_CCU8_SLICE_DisableMultipleEvents() APIs. + * - DOC updates for the newly added APIs. + * + * 2016-03-09: + * - Optimization of write only registers + * + * 2016-05-20: + * - Added XMC_CCU8_SLICE_StopClearTimer() + * - Changed XMC_CCU8_SLICE_StopTimer() and XMC_CCU8_SLICE_ClearTimer() + * + * @endcond + */ + +#ifndef XMC_CCU8_H +#define XMC_CCU8_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_common.h" + +#if defined(CCU80) + +#if UC_FAMILY == XMC1 + #include "xmc1_ccu8_map.h" +#endif + +#if UC_FAMILY == XMC4 + #include "xmc4_ccu8_map.h" +#endif + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup CCU8 + * + * @brief Capture Compare Unit 8 (CCU8) low level driver for XMC family of microcontrollers
+ * + * The CCU8 peripheral functions play a major role in applications that need complex Pulse Width Modulation (PWM) signal + * generation, with complementary high side and low side switches, multi phase control. These functions in conjunction + * with a very flexible and programmable signal conditioning scheme, make the CCU8 the must have peripheral for state + * of the art motor control, multi phase and multi level power electronics systems.\n + * Each CCU8 module is comprised of four identical 16 bit Capture/Compare Timer slices, CC8y (where y = [0..4]). Each + * timer slice can work in compare mode or in capture mode. + * + * APIs provided in this file cover the following functional blocks of CCU8: + * -- Timer configuration, Capture configuration, Function/Event configuration, Interrupt configuration + * \par Note: + * 1. SLICE (APIs prefixed with e.g. XMC_CCU8_SLICE_) + * 2. Module (APIs are not having any prefix e.g. XMC_CCU8_) + * + * \par Timer(Compare mode) configuration: + * This section of the LLD provides the configuration structure XMC_CCU8_SLICE_COMPARE_CONFIG_t, + * XMC_CCU8_SLICE_DEAD_TIME_CONFIG_t and the initialization functions XMC_CCU8_SLICE_CompareInit(), XMC_CCU8_SLICE_DeadTimeInit(). + * + * It can be used to: + * -# Start and Stop the timer. (XMC_CCU8_SLICE_StartTimer(), XMC_CCU8_SLICE_StopTimer()) + * -# Update the period, compare, Dither, Prescaler and Passive values. (XMC_CCU8_SLICE_SetTimerPeriodMatch(), + * XMC_CCU8_SLICE_SetTimerCompareMatch(), XMC_CCU8_SLICE_SetPrescaler(), XMC_CCU8_SLICE_SetDitherCompareValue(), + * XMC_CCU8_SLICE_SetPassiveLevel()) + * -# Configure the dead time.(XMC_CCU8_SLICE_SetDeadTimeValue(), XMC_CCU8_SLICE_SetDeadTimePrescaler()) + * -# Enable the slices to support multichannel mode. (XMC_CCU8_SLICE_EnableMultiChannelMode()) + * + * \par Capture configuration: + * This section of the LLD provides the configuration structure XMC_CCU8_SLICE_CAPTURE_CONFIG_t and the initialization + * function XMC_CCU8_SLICE_CaptureInit(). + * + * It can be used to: + * -# Configure the capture functionality. (XMC_CCU8_SLICE_Capture0Config(), XMC_CCU8_SLICE_Capture1Config()) + * -# Read the captured values along with the status, which indicate the value is latest or not. + * (XMC_CCU8_SLICE_GetCaptureRegisterValue()) + * + * \par Function/Event configuration: + * This section of the LLD provides the configuration structure XMC_CCU8_SLICE_EVENT_CONFIG_t. + * + * It can be used to: + * -# Enable and Disable the events. (XMC_CCU8_SLICE_EnableEvent(), XMC_CCU8_SLICE_DisableEvent()) + * -# Configure to start and stop the timer on external events.(XMC_CCU8_SLICE_StartConfig(), XMC_CCU8_SLICE_StopConfig()) + * -# Modulation, external load and Gating of the timer output.(XMC_CCU8_SLICE_ModulationConfig(), + * XMC_CCU8_SLICE_LoadConfig(), XMC_CCU8_SLICE_GateConfig()) + * -# Control the count direction of the timer based on the external event. (XMC_CCU8_SLICE_DirectionConfig()) + * -# Count the external events.(XMC_CCU8_SLICE_CountConfig()) + * -# External Trap. Which can be used as protective feature.(XMC_CCU8_SLICE_EnableTrap(), XMC_CCU8_SLICE_DisableTrap(), + * XMC_CCU8_SLICE_TrapConfig()) + * + * \par Interrupt configuration: + * This section of the LLD provides the function to configure the interrupt node to each event (XMC_CCU8_SLICE_SetInterruptNode()) + * + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_CCU8_SLICE_CHECK_INTERRUPT(interrupt) \ + ((interrupt == XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_1) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_1)|| \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_2) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_2)|| \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_EVENT0) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_EVENT1) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_EVENT2) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_TRAP)) + +/* Macro to check if the slice ptr passed is valid */ +#define XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(cmp_channel) \ + ((cmp_channel == XMC_CCU8_SLICE_COMPARE_CHANNEL_1) || \ + (cmp_channel == XMC_CCU8_SLICE_COMPARE_CHANNEL_2)) + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/** + * Typedef for CCU8 Global data structure + */ +typedef CCU8_GLOBAL_TypeDef XMC_CCU8_MODULE_t; + +/** + * Typedef for CCU8 Slice data structure + */ +typedef CCU8_CC8_TypeDef XMC_CCU8_SLICE_t; + +/** + * Return Value of an API + */ +typedef enum XMC_CCU8_STATUS +{ + XMC_CCU8_STATUS_OK = 0U, /**< API fulfils request */ + XMC_CCU8_STATUS_ERROR , /**< API cannot fulfil request */ + XMC_CCU8_STATUS_RUNNING , /**< The timer slice is currently running */ + XMC_CCU8_STATUS_IDLE /**< The timer slice is currently idle */ +} XMC_CCU8_STATUS_t; + +/** + * CCU8 module clock + */ +typedef enum XMC_CCU8_CLOCK +{ + XMC_CCU8_CLOCK_SCU = 0U, /**< Select the fCCU as the clock */ + XMC_CCU8_CLOCK_EXTERNAL_A , /**< External clock-A */ + XMC_CCU8_CLOCK_EXTERNAL_B , /**< External clock-B */ + XMC_CCU8_CLOCK_EXTERNAL_C /**< External clock-C */ +} XMC_CCU8_CLOCK_t; + +/** + * CCU8 set the shadow transfer type for multichannel mode + */ +typedef enum XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER +{ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0 = (uint32_t)0x4000000, /**< Shadow transfer through software + only for slice 0*/ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0 = (uint32_t)0x4000400, /**< Shadow transfer through software + and hardware for slice 0 */ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1 = (uint32_t)0x8000000, /**< Shadow transfer through software + only for slice 1*/ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1 = (uint32_t)0x8000800, /**< Shadow transfer through software + and hardware for slice 1 */ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2 = (uint32_t)0x10000000, /**< Shadow transfer through software + only for slice 2 */ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE2 = (uint32_t)0x10001000, /**< Shadow transfer through software + and hardware for slice 2 */ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE3 = (uint32_t)0x20000000, /**< Shadow transfer through software + only for slice 3*/ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE3 = (uint32_t)0x20002000 /**< Shadow transfer through software + and hardware for slice 3 */ +} XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_t; + +/** + * Operational modes of CCU8 slice + */ +typedef enum XMC_CCU8_SLICE_MODE +{ + XMC_CCU8_SLICE_MODE_COMPARE = 0U, /**< slice(CC8y) operates in Compare Mode */ + XMC_CCU8_SLICE_MODE_CAPTURE /**< slice(CC8y) operates in Capture Mode */ +} XMC_CCU8_SLICE_MODE_t; + +/** + * Slice Output selection + */ +typedef enum XMC_CCU8_SLICE_OUTPUT +{ + XMC_CCU8_SLICE_OUTPUT_0 = 1U, /**< Slice Output-0 */ + XMC_CCU8_SLICE_OUTPUT_1 = 2U, /**< Slice Output-1 */ + XMC_CCU8_SLICE_OUTPUT_2 = 4U, /**< Slice Output-2 */ + XMC_CCU8_SLICE_OUTPUT_3 = 8U /**< Slice Output-3 */ +} XMC_CCU8_SLICE_OUTPUT_t; + +/** + * Timer counting modes for the slice + */ +typedef enum XMC_CCU8_SLICE_TIMER_COUNT_MODE +{ + XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA = 0U, /**< Edge Aligned Mode */ + XMC_CCU8_SLICE_TIMER_COUNT_MODE_CA /**< Centre Aligned Mode */ +} XMC_CCU8_SLICE_TIMER_COUNT_MODE_t; + +/** + * Timer repetition mode for the slice + */ +typedef enum XMC_CCU8_SLICE_TIMER_REPEAT_MODE +{ + XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT = 0U, /**< Repetitive mode: continuous mode of operation */ + XMC_CCU8_SLICE_TIMER_REPEAT_MODE_SINGLE /**< Single shot mode: Once a Period match/One match + occurs timer goes to idle state */ +} XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t; + +/** + * Timer counting direction for the CCU8 slice + */ +typedef enum XMC_CCU8_SLICE_TIMER_COUNT_DIR +{ + XMC_CCU8_SLICE_TIMER_COUNT_DIR_UP = 0U, /**< Counting up */ + XMC_CCU8_SLICE_TIMER_COUNT_DIR_DOWN /**< Counting down */ +} XMC_CCU8_SLICE_TIMER_COUNT_DIR_t; + +/** + * Capture mode register sets + */ +typedef enum XMC_CCU8_SLICE_CAP_REG_SET +{ + XMC_CCU8_SLICE_CAP_REG_SET_LOW = 0U, /**< Capture register-0, Capture register-1 used */ + XMC_CCU8_SLICE_CAP_REG_SET_HIGH /**< Capture register-0, Capture register-1 used */ +} XMC_CCU8_SLICE_CAP_REG_SET_t; + +/** + * Prescaler mode + */ +typedef enum XMC_CCU8_SLICE_PRESCALER_MODE +{ + XMC_CCU8_SLICE_PRESCALER_MODE_NORMAL = 0U, /**< Fixed division of module clock */ + XMC_CCU8_SLICE_PRESCALER_MODE_FLOAT /**< Floating divider */ +} XMC_CCU8_SLICE_PRESCALER_MODE_t; + +/** + * Timer output passive level + */ +typedef enum XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL +{ + XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_LOW = 0U, /**< Passive level = Low */ + XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH /**< Passive level = High */ +} XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t; + +/** + * Compare Channel selection + */ +typedef enum XMC_CCU8_SLICE_COMPARE_CHANNEL +{ + XMC_CCU8_SLICE_COMPARE_CHANNEL_1 = 0U, /**< Compare Channel-1 */ + XMC_CCU8_SLICE_COMPARE_CHANNEL_2 /**< Compare Channel-2 */ +} XMC_CCU8_SLICE_COMPARE_CHANNEL_t; + +/** + * Timer clock Divider + */ +typedef enum XMC_CCU8_SLICE_PRESCALER +{ + XMC_CCU8_SLICE_PRESCALER_1 = 0U, /**< Slice Clock = fccu8 */ + XMC_CCU8_SLICE_PRESCALER_2 , /**< Slice Clock = fccu8/2 */ + XMC_CCU8_SLICE_PRESCALER_4 , /**< Slice Clock = fccu8/4 */ + XMC_CCU8_SLICE_PRESCALER_8 , /**< Slice Clock = fccu8/8 */ + XMC_CCU8_SLICE_PRESCALER_16 , /**< Slice Clock = fccu8/16 */ + XMC_CCU8_SLICE_PRESCALER_32 , /**< Slice Clock = fccu8/32 */ + XMC_CCU8_SLICE_PRESCALER_64 , /**< Slice Clock = fccu8/64 */ + XMC_CCU8_SLICE_PRESCALER_128 , /**< Slice Clock = fccu8/128 */ + XMC_CCU8_SLICE_PRESCALER_256 , /**< Slice Clock = fccu8/256 */ + XMC_CCU8_SLICE_PRESCALER_512 , /**< Slice Clock = fccu8/512 */ + XMC_CCU8_SLICE_PRESCALER_1024 , /**< Slice Clock = fccu8/1024 */ + XMC_CCU8_SLICE_PRESCALER_2048 , /**< Slice Clock = fccu8/2048 */ + XMC_CCU8_SLICE_PRESCALER_4096 , /**< Slice Clock = fccu8/4096 */ + XMC_CCU8_SLICE_PRESCALER_8192 , /**< Slice Clock = fccu8/8192 */ + XMC_CCU8_SLICE_PRESCALER_16384 , /**< Slice Clock = fccu8/16384 */ + XMC_CCU8_SLICE_PRESCALER_32768 /**< Slice Clock = fccu8/32768 */ +} XMC_CCU8_SLICE_PRESCALER_t; + +/** + * Dead Time Generator Clock Divider + */ +typedef enum XMC_CCU8_SLICE_DTC_DIV +{ + XMC_CCU8_SLICE_DTC_DIV_1 = 0U, /**< DTC clock = Slice Clock */ + XMC_CCU8_SLICE_DTC_DIV_2 , /**< DTC clock = Slice Clock/2 */ + XMC_CCU8_SLICE_DTC_DIV_4 , /**< DTC clock = Slice Clock/4 */ + XMC_CCU8_SLICE_DTC_DIV_8 /**< DTC clock = Slice Clock/8 */ +} XMC_CCU8_SLICE_DTC_DIV_t; + + +/** + * The compare channel output which is routed to the slice output signal(STy). + */ +typedef enum XMC_CCU8_SLICE_STATUS +{ + XMC_CCU8_SLICE_STATUS_CHANNEL_1 = 0U, /**< Channel-1 status connected to Slice Status */ + XMC_CCU8_SLICE_STATUS_CHANNEL_2 , /**< Channel-2 status connected to Slice Status */ + XMC_CCU8_SLICE_STATUS_CHANNEL_1_AND_2 , /**< \b Wired \b AND of Channel-1 and Channel-2 status connected to + Slice status */ +#if ((UC_SERIES == XMC13) || (UC_SERIES == XMC14)) || defined(DOXYGEN) + XMC_CCU8_SLICE_STATUS_CHANNEL_1_OR_2 /**< \b Wired \b OR of Channel-1 and Channel-2 status connected to Slice + status. @note Only available for XMC1300 and XMC1400 series */ +#endif +} XMC_CCU8_SLICE_STATUS_t; + +/** + * Compare channel for which modulation has to be applied + */ +typedef enum XMC_CCU8_SLICE_MODULATION_CHANNEL +{ + XMC_CCU8_SLICE_MODULATION_CHANNEL_NONE = 0U, /**< No modulation */ + XMC_CCU8_SLICE_MODULATION_CHANNEL_1 , /**< Modulation for Compare Channel-1 */ + XMC_CCU8_SLICE_MODULATION_CHANNEL_2 , /**< Modulation for Compare Channel-2 */ + XMC_CCU8_SLICE_MODULATION_CHANNEL_1_AND_2 /**< Modulation for Compare Channel-1 and Compare Channel-2 */ +} XMC_CCU8_SLICE_MODULATION_CHANNEL_t; + +/** + * External Function list + */ +typedef enum XMC_CCU8_SLICE_FUNCTION +{ + XMC_CCU8_SLICE_FUNCTION_START = 0U, /**< Start function */ + XMC_CCU8_SLICE_FUNCTION_STOP , /**< Stop function */ + XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT0 , /**< Capture Event-0 function, CCycapt0 signal is used for event + generation */ + XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT1 , /**< Capture Event-1 function, CCycapt1 signal is used for event + generation */ + XMC_CCU8_SLICE_FUNCTION_GATING , /**< Gating function */ + XMC_CCU8_SLICE_FUNCTION_DIRECTION , /**< Direction function */ + XMC_CCU8_SLICE_FUNCTION_LOAD , /**< Load function */ + XMC_CCU8_SLICE_FUNCTION_COUNT , /**< Counting function */ + XMC_CCU8_SLICE_FUNCTION_OVERRIDE , /**< Override function */ + XMC_CCU8_SLICE_FUNCTION_MODULATION , /**< Modulation function */ + XMC_CCU8_SLICE_FUNCTION_TRAP /**< Trap function */ +} XMC_CCU8_SLICE_FUNCTION_t; + +/** + * External Event list + */ +typedef enum XMC_CCU8_SLICE_EVENT +{ + XMC_CCU8_SLICE_EVENT_NONE = 0U, /**< None */ + XMC_CCU8_SLICE_EVENT_0 , /**< Event-0 */ + XMC_CCU8_SLICE_EVENT_1 , /**< Event-1 */ + XMC_CCU8_SLICE_EVENT_2 /**< Event-2 */ +} XMC_CCU8_SLICE_EVENT_t; + +/** + * External Event trigger criteria - Edge sensitivity + */ +typedef enum XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY +{ + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_NONE = 0U, /**< None */ + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE , /**< Rising Edge of the input signal generates + event trigger */ + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE , /**< Falling Edge of the input signal generates event + trigger */ + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE /**< Both Rising and Falling edges cause an event trigger */ +} XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_t; + +/** + * External Event trigger criteria - Level sensitivity + */ +typedef enum XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY +{ + XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH = 0U, /**< Level sensitive functions react to a high signal level*/ + XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW = 1U, /**< Level sensitive functions react to a low signal level */ + /* Below enum items can be utilised specific to the functionality */ + XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW = 0U, /**< Timer counts up, during Low state of the control signal */ + XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH = 1U /**< Timer counts up, during High state of the control signal */ +} XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_t; + +/** + * Low pass filter Configuration. The External Event input should be stable for a selected number of clock cycles. + */ +typedef enum XMC_CCU8_SLICE_EVENT_FILTER +{ + XMC_CCU8_SLICE_EVENT_FILTER_DISABLED = 0U, /**< No Low Pass Filtering is applied */ + XMC_CCU8_SLICE_EVENT_FILTER_3_CYCLES , /**< Input should be stable for 3 clock cycles */ + XMC_CCU8_SLICE_EVENT_FILTER_5_CYCLES , /**< Input should be stable for 5 clock cycles */ + XMC_CCU8_SLICE_EVENT_FILTER_7_CYCLES /**< Input should be stable for 7 clock cycles */ +} XMC_CCU8_SLICE_EVENT_FILTER_t; + +/** + * External Event Input list. This list depicts the possible input connections to the CCU8 slice. + * Interconnects are specific to each device. + */ +typedef uint8_t XMC_CCU8_SLICE_INPUT_t; + + +/** + * Actions that can be performed upon detection of an external Timer STOP event + */ +typedef enum XMC_CCU8_SLICE_END_MODE +{ + XMC_CCU8_SLICE_END_MODE_TIMER_STOP = 0U, /**< Stops the timer, without clearing TIMER register */ + XMC_CCU8_SLICE_END_MODE_TIMER_CLEAR , /**< Without stopping timer, clears the TIMER register */ + XMC_CCU8_SLICE_END_MODE_TIMER_STOP_CLEAR /**< Stops the timer and clears the TIMER register */ +} XMC_CCU8_SLICE_END_MODE_t; + +/** + * Actions that can be performed upon detection of an external Timer START event + */ +typedef enum XMC_CCU8_SLICE_START_MODE +{ + XMC_CCU8_SLICE_START_MODE_TIMER_START = 0U, /**< Start the timer from the current count of TIMER register */ + XMC_CCU8_SLICE_START_MODE_TIMER_START_CLEAR /**< Clears the TIMER register and start the timer */ +} XMC_CCU8_SLICE_START_MODE_t; + +/** + * Modulation of timer output signals + */ +typedef enum XMC_CCU8_SLICE_MODULATION_MODE +{ + XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_ST_OUT = 0U, /**< Clear ST and OUT signals */ + XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_OUT /**< Clear only the OUT signal */ +} XMC_CCU8_SLICE_MODULATION_MODE_t; + +/** + * Trap exit mode + */ +typedef enum XMC_CCU8_SLICE_TRAP_EXIT_MODE +{ + XMC_CCU8_SLICE_TRAP_EXIT_MODE_AUTOMATIC = 0U, /**< Clear trap state as soon as the trap signal is de-asserted */ + XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW /**< Clear only when acknowledged by software */ +} XMC_CCU8_SLICE_TRAP_EXIT_MODE_t; + +/** + * Timer clear on capture + */ +typedef enum XMC_CCU8_SLICE_TIMER_CLEAR_MODE +{ + XMC_CCU8_SLICE_TIMER_CLEAR_MODE_NEVER = 0U, /**< Never clear the timer on any capture event */ + XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_HIGH , /**< Clear only when timer value has been captured in C3V and C2V */ + XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_LOW , /**< Clear only when timer value has been captured in C1V and C0V */ + XMC_CCU8_SLICE_TIMER_CLEAR_MODE_ALWAYS /**< Always clear the timer upon detection of any capture event */ +} XMC_CCU8_SLICE_TIMER_CLEAR_MODE_t; + +/** + * Multi Channel Shadow transfer request configuration options + */ +typedef enum XMC_CCU8_SLICE_MCMS_ACTION +{ + XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR = 0U, /**< Transfer Compare and Period Shadow register values to + the actual registers upon MCS xfer request */ + XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP = 1U, /**< Transfer Compare, Period and Prescaler Compare Shadow + register values to the actual registers upon MCS xfer + request */ + XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT = 3U /**< Transfer Compare, Period ,Prescaler Compare and Dither + Compare register values to the actual registers upon + MCS xfer request */ +} XMC_CCU8_SLICE_MCMS_ACTION_t; + +/** + * Available Interrupt Event Ids + */ +typedef enum XMC_CCU8_SLICE_IRQ_ID +{ + XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH = 0U , /**< Period match counting up */ + XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH = 1U , /**< One match counting down */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_1 = 2U , /**< Compare match counting up for channel 1 */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_1 = 3U , /**< Compare match counting down for channel 1 */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_2 = 4U , /**< Compare match counting up for channel 2 */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_2 = 5U , /**< Compare match counting down for channel 2 */ + XMC_CCU8_SLICE_IRQ_ID_EVENT0 = 8U , /**< Event-0 occurrence */ + XMC_CCU8_SLICE_IRQ_ID_EVENT1 = 9U , /**< Event-1 occurrence */ + XMC_CCU8_SLICE_IRQ_ID_EVENT2 = 10U, /**< Event-2 occurrence */ + XMC_CCU8_SLICE_IRQ_ID_TRAP = 11U /**< Trap occurrence */ +} XMC_CCU8_SLICE_IRQ_ID_t; + +/** + * Available Interrupt Event Ids, which is added to support multi event APIs + */ +typedef enum XMC_CCU8_SLICE_MULTI_IRQ_ID +{ + XMC_CCU8_SLICE_MULTI_IRQ_ID_PERIOD_MATCH = 0x1U, /**< Period match counting up */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_ONE_MATCH = 0x2U, /**< One match counting down */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP_CH_1 = 0x4U, /**< Compare match counting up for channel 1 */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN_CH_1 = 0x8U, /**< Compare match counting down for channel 1 */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP_CH_2 = 0x10U, /**< Compare match counting up for channel 2 */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN_CH_2 = 0x20U, /**< Compare match counting down for channel 2 */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT0 = 0x100U, /**< Event-0 occurrence */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT1 = 0x200U, /**< Event-1 occurrence */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT2 = 0x400U, /**< Event-2 occurrence */ +} XMC_CCU8_SLICE_MULTI_IRQ_ID_t; + +/** + * Service Request Lines for CCU8. Event are mapped to these SR lines and these are used to generate the interrupt. + */ +typedef enum XMC_CCU8_SLICE_SR_ID +{ + XMC_CCU8_SLICE_SR_ID_0 = 0U, /**< Service Request Line-0 selected */ + XMC_CCU8_SLICE_SR_ID_1 , /**< Service Request Line-1 selected */ + XMC_CCU8_SLICE_SR_ID_2 , /**< Service Request Line-2 selected */ + XMC_CCU8_SLICE_SR_ID_3 /**< Service Request Line-3 selected */ +} XMC_CCU8_SLICE_SR_ID_t; + + +/** + * Slice shadow transfer options. + */ +typedef enum XMC_CCU8_SHADOW_TRANSFER +{ + XMC_CCU8_SHADOW_TRANSFER_SLICE_0 = CCU8_GCSS_S0SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-0 */ + XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_0 = CCU8_GCSS_S0DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-0 */ + XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_0 = CCU8_GCSS_S0PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-0 */ + XMC_CCU8_SHADOW_TRANSFER_SLICE_1 = CCU8_GCSS_S1SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-1 */ + XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_1 = CCU8_GCSS_S1DSE_Msk, /**< Transfer Dither compare shadow register value + to actual registers for SLICE-1 */ + XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_1 = CCU8_GCSS_S1PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-1 */ + XMC_CCU8_SHADOW_TRANSFER_SLICE_2 = CCU8_GCSS_S2SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-2 */ + XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_2 = CCU8_GCSS_S2DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-2 */ + XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_2 = CCU8_GCSS_S2PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-2 */ + XMC_CCU8_SHADOW_TRANSFER_SLICE_3 = CCU8_GCSS_S3SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-3 */ + XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_3 = CCU8_GCSS_S3DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-3 */ + XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_3 = CCU8_GCSS_S3PSE_Msk /**< Transfer Prescaler shadow register value to + actual register for SLICE-3 */ +} XMC_CCU8_SHADOW_TRANSFER_t; + +#if (UC_SERIES != XMC45) || defined(DOXYGEN) +/** + * Slice shadow transfer mode options. + * @note Not available for XMC4500 series + */ +typedef enum XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE +{ + XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_IN_PERIOD_MATCH_AND_ONE_MATCH = 0U, /**< Shadow transfer is done in Period Match and + One match. */ + XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH = 1U, /**< Shadow transfer is done only in Period Match. */ + XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_ONE_MATCH = 2U /**< Shadow transfer is done only in One Match. */ +} XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t; +#endif + +#if defined(CCU8V3) || defined(DOXYGEN) /* Defined for XMC1400 devices only */ +/** + * Output sources for OUTy0 signal + * @note Only available for XMC1400 series + */ + typedef enum XMC_CCU8_SOURCE_OUT0 +{ + XMC_CCU8_SOURCE_OUT0_ST1 = (uint32_t)0x0, /**< CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_SOURCE_OUT0_INV_ST1 = (uint32_t)0x1, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_SOURCE_OUT0_ST2 = (uint32_t)0x2, /**< CCU8yST2 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_SOURCE_OUT0_INV_ST2 = (uint32_t)0x3 /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT0 */ +} XMC_CCU8_SOURCE_OUT0_t; + +/** + * Output sources for OUTy1 signal + * @note Only available for XMC1400 series + */ + typedef enum XMC_CCU8_SOURCE_OUT1 +{ + XMC_CCU8_SOURCE_OUT1_ST1 = (uint32_t)0x1, /**< CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_SOURCE_OUT1_INV_ST1 = (uint32_t)0x0, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_SOURCE_OUT1_ST2 = (uint32_t)0x3, /**< CCU8yST2 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_SOURCE_OUT1_INV_ST2 = (uint32_t)0x2 /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT1 */ +} XMC_CCU8_SOURCE_OUT1_t; + +/** + * Output sources for OUTy2 signal + * @note Only available for XMC1400 series + */ + typedef enum XMC_CCU8_SOURCE_OUT2 +{ + XMC_CCU8_SOURCE_OUT2_ST2 = (uint32_t)0x0, /**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT2_INV_ST2 = (uint32_t)0x1, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT2_ST1 = (uint32_t)0x2, /**< CCU8yST1 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT2_INV_ST1 = (uint32_t)0x3 /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT2 */ +} XMC_CCU8_SOURCE_OUT2_t; + +/** + * Output sources for OUTy3 signal + * @note Only available for XMC1400 series + */ + typedef enum XMC_CCU8_SOURCE_OUT3 +{ + XMC_CCU8_SOURCE_OUT3_ST2 = (uint32_t)0x1, /**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT3_INV_ST2 = (uint32_t)0x0, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT3_ST1 = (uint32_t)0x3, /**< CCU8yST1 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT3_INV_ST1 = (uint32_t)0x2 /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT2 */ +} XMC_CCU8_SOURCE_OUT3_t; +#endif + + +/** + * Output selector for CCU8x.OUT0-3 + */ +#if !defined(CCU8V3) /* Defined for all devices except XMC1400 */ +typedef enum XMC_CCU8_OUT_PATH +{ + XMC_CCU8_OUT_PATH_OUT0_ST1 = (uint32_t)0x20000, /**< CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_OUT_PATH_OUT0_INV_ST1 = (uint32_t)0x20002, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_OUT_PATH_OUT1_ST1 = (uint32_t)0x40000, /**< CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_OUT_PATH_OUT1_INV_ST1 = (uint32_t)0x40004, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_OUT_PATH_OUT2_ST2 = (uint32_t)0x80000, /**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_OUT_PATH_OUT2_INV_ST2 = (uint32_t)0x80008, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_OUT_PATH_OUT3_ST2 = (uint32_t)0x100000,/**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_OUT_PATH_OUT3_INV_ST1 = (uint32_t)0x100010 /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT3 */ +} XMC_CCU8_OUT_PATH_t; +#else +typedef enum XMC_CCU8_OUT_PATH +{ + XMC_CCU8_OUT_PATH_OUT0_ST1 = (uint32_t)0x000C0, /**< CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_OUT_PATH_OUT0_INV_ST1 = (uint32_t)0x000D0, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_OUT_PATH_OUT0_ST2 = (uint32_t)0x000E0, /**< CCU8yST2 signal path is connected the CCU8x.OUT0. @note Only available for XMC1400 series*/ + XMC_CCU8_OUT_PATH_OUT0_INV_ST2 = (uint32_t)0x000F0, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT0. @note Only available for XMC1400 series*/ + XMC_CCU8_OUT_PATH_OUT1_ST1 = (uint32_t)0x00D00, /**< CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_OUT_PATH_OUT1_INV_ST1 = (uint32_t)0x00C00, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_OUT_PATH_OUT1_ST2 = (uint32_t)0x00F00, /**< CCU8yST2 signal path is connected the CCU8x.OUT1. @note Only available for XMC1400 series*/ + XMC_CCU8_OUT_PATH_OUT1_INV_ST2 = (uint32_t)0x00E00, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT1. @note Only available for XMC1400 series */ + XMC_CCU8_OUT_PATH_OUT2_ST2 = (uint32_t)0x0C000, /**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_OUT_PATH_OUT2_INV_ST2 = (uint32_t)0x0D000, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_OUT_PATH_OUT2_ST1 = (uint32_t)0x0E000, /**< CCU8yST1 signal path is connected the CCU8x.OUT2. @note Only available for XMC1400 series*/ + XMC_CCU8_OUT_PATH_OUT2_INV_ST1 = (uint32_t)0x0F000, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT2.@note Only available for XMC1400 series */ + XMC_CCU8_OUT_PATH_OUT3_ST2 = (uint32_t)0xD0000, /**< CCU8yST2 signal path is connected the CCU8x.OUT3 */ + XMC_CCU8_OUT_PATH_OUT3_INV_ST2 = (uint32_t)0xC0000, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT3.@note Only available for XMC1400 series */ + XMC_CCU8_OUT_PATH_OUT3_ST1 = (uint32_t)0xF0000, /**< CCU8yST1 signal path is connected the CCU8x.OUT3.@note Only available for XMC1400 series */ + XMC_CCU8_OUT_PATH_OUT3_INV_ST1 = (uint32_t)0xE0000 /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT3 */ +} XMC_CCU8_OUT_PATH_t; + +/** + * Immediate write into configuration register + * @note Only available for XMC1400 series + */ +typedef enum XMC_CCU8_SLICE_WRITE_INTO +{ + XMC_CCU8_SLICE_WRITE_INTO_PERIOD_CONFIGURATION = CCU8_CC8_STC_IRPC_Msk, /**< Immediate or Coherent + Write into Period + Configuration */ + XMC_CCU8_SLICE_WRITE_INTO_COMPARE1_CONFIGURATION = CCU8_CC8_STC_IRCC1_Msk, /**< Immediate or Coherent + Write into Compare 1 + Configuration */ + XMC_CCU8_SLICE_WRITE_INTO_COMPARE2_CONFIGURATION = CCU8_CC8_STC_IRCC2_Msk, /**< Immediate or Coherent + Write into Compare 2 + Configuration */ + XMC_CCU8_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION = CCU8_CC8_STC_IRLC_Msk, /**< Immediate or Coherent + Write into Passive Level + Configuration */ + XMC_CCU8_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION = CCU8_CC8_STC_IRDC_Msk, /**< Immediate or Coherent + Write into Dither Value + Configuration */ + XMC_CCU8_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION = CCU8_CC8_STC_IRFC_Msk /**< Immediate or Coherent + Write into Floating Prescaler + Value Configuration */ +} XMC_CCU8_SLICE_WRITE_INTO_t; + + +/** + * Automatic Shadow Transfer request when writing into shadow register + * @note Only available for XMC1400 series + */ +typedef enum XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO +{ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PERIOD_SHADOW = CCU8_CC8_STC_ASPC_Msk, /**< Automatic Shadow + Transfer request when + writing into Period + Shadow Register */ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_COMPARE1_SHADOW = CCU8_CC8_STC_ASCC1_Msk, /**< Automatic Shadow + transfer request + when writing into + Compare 1 Shadow Register */ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_COMPARE2_SHADOW = CCU8_CC8_STC_ASCC2_Msk, /**< Automatic Shadow + transfer request + when writing into + Compare 2 Shadow Register */ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PASSIVE_LEVEL = CCU8_CC8_STC_ASLC_Msk, /**< Automatic Shadow transfer + request when writing + into Passive Level Register*/ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_DITHER_SHADOW = CCU8_CC8_STC_ASDC_Msk, /**< Automatic Shadow transfer + request when writing + into Dither Shadow Register */ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_FLOATING_PRESCALER_SHADOW = CCU8_CC8_STC_ASFC_Msk /**< Automatic Shadow transfer + request when writing + into Floating Prescaler Shadow + register */ + +} XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t; +#endif +/** + * CCU8 slice mask which can be used for the APIs as input where multi slice support is available + */ +typedef enum XMC_CCU8_SLICE_MASK +{ + XMC_CCU8_SLICE_MASK_SLICE_0 = 1U , /**< SLICE-0 */ + XMC_CCU8_SLICE_MASK_SLICE_1 = 2U , /**< SLICE-1 */ + XMC_CCU8_SLICE_MASK_SLICE_2 = 4U , /**< SLICE-2 */ + XMC_CCU8_SLICE_MASK_SLICE_3 = 8U /**< SLICE-3 */ +} XMC_CCU8_SLICE_MASK_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/** + * Configuration data structure of an External Event(Event-0/1/2). + * Needed to configure the various aspects of an External Event. + * This structure will not connect the external event with an external function. + */ +typedef struct XMC_CCU8_SLICE_EVENT_CONFIG +{ + XMC_CCU8_SLICE_INPUT_t mapped_input; /**< Required input signal for the Event. */ + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_t edge; /**< Select the event edge of the input signal. + This is needed for an edge sensitive External function.*/ + XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_t level; /**< Select the event level of the input signal. + This is needed for an level sensitive External function.*/ + XMC_CCU8_SLICE_EVENT_FILTER_t duration; /**< Low Pass filter duration in terms of fCCU clock cycles. */ +} XMC_CCU8_SLICE_EVENT_CONFIG_t; + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Dead Time configuration + */ +typedef struct XMC_CCU8_SLICE_DEAD_TIME_CONFIG +{ + union + { + struct + { + uint32_t enable_dead_time_channel1 : 1; /**< Enable dead time for Compare Channel-1 */ + uint32_t enable_dead_time_channel2 : 1; /**< Enable dead time for Compare Channel-2 */ + uint32_t channel1_st_path : 1; /**< Should dead time be applied to ST output of Compare Channel-1? */ + uint32_t channel1_inv_st_path : 1; /**< Should dead time be applied to inverse ST output of + Compare Channel-1? */ + uint32_t channel2_st_path : 1; /**< Should dead time be applied to ST output of Compare Channel-2? */ + uint32_t channel2_inv_st_path : 1; /**< Should dead time be applied to inverse ST output of + Compare Channel-2? */ + uint32_t div : 2; /**< Dead time prescaler divider value. + Accepts enum ::XMC_CCU8_SLICE_DTC_DIV_t*/ + uint32_t : 24; + }; + uint32_t dtc; + }; + union + { + struct + { + uint32_t channel1_st_rising_edge_counter : 8; /**< Contains the delay value that is applied to the rising edge + for compare channel-1. Range: [0x0 to 0xFF] */ + uint32_t channel1_st_falling_edge_counter : 8; /**< Contains the delay value that is applied to the falling edge + for compare channel-1. Range: [0x0 to 0xFF] */ + uint32_t : 16; + }; + uint32_t dc1r; + }; + union + { + struct + { + uint32_t channel2_st_rising_edge_counter : 8; /**< Contains the delay value that is applied to the rising edge + for compare channel-2. Range: [0x0 to 0xFF]*/ + uint32_t channel2_st_falling_edge_counter : 8; /**< Contains the delay value that is applied to the falling edge + for compare channel-2. Range: [0x0 to 0xFF]*/ + uint32_t : 16; + }; + uint32_t dc2r; + }; +} XMC_CCU8_SLICE_DEAD_TIME_CONFIG_t; + +/** + * Configuration data structure for CCU8 slice. Specifically configures the CCU8 slice to compare mode operation. + * This excludes event and function configuration. + */ +typedef struct XMC_CCU8_SLICE_COMPARE_CONFIG +{ + union + { + struct + { + uint32_t timer_mode : 1; /**< Edge aligned or Centre Aligned. + Accepts enum :: XMC_CCU8_SLICE_TIMER_COUNT_MODE_t */ + uint32_t monoshot : 1; /**< Single shot or Continuous mode . + Accepts enum :: XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t */ + uint32_t shadow_xfer_clear : 1; /**< Should PR and CR shadow xfer happen when timer is cleared? */ + uint32_t : 10; + uint32_t dither_timer_period: 1; /**< Can the period of the timer dither? */ + uint32_t dither_duty_cycle : 1; /**< Can the compare match of the timer dither? */ + uint32_t : 1; + uint32_t prescaler_mode: 1; /**< Normal or floating prescaler mode. + Accepts enum :: XMC_CCU8_SLICE_PRESCALER_MODE_t */ + uint32_t : 8; + uint32_t mcm_ch1_enable : 1; /**< Multi-Channel mode for compare channel 1 enable? */ + uint32_t mcm_ch2_enable : 1; /**< Multi-Channel mode for compare channel 2 enable? */ + uint32_t : 2; + uint32_t slice_status : 2; /**< Which of the two channels drives the slice status output. + Accepts enum :: XMC_CCU8_SLICE_STATUS_t*/ + uint32_t : 1; + }; + uint32_t tc; + }; + union + { + struct + { + uint32_t passive_level_out0 : 1; /**< ST and OUT passive levels Configuration for OUT0. + Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ + uint32_t passive_level_out1 : 1; /**< ST and OUT passive levels Configuration for OUT1. + Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ + uint32_t passive_level_out2 : 1; /**< ST and OUT passive levels Configuration for OUT2. + Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ + uint32_t passive_level_out3 : 1; /**< ST and OUT passive levels Configuration for OUT3. + Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ + uint32_t : 28; + }; + uint32_t psl; + }; + union + { + struct + { + uint32_t asymmetric_pwm : 1; /**< Should the PWM be a function of the 2 compare channels + rather than period value? */ + #if !defined(CCU8V3) /* Defined for all devices except XMC1400 */ + uint32_t invert_out0 : 1; /**< Should inverted ST of Channel-1 be connected to OUT0? */ + uint32_t invert_out1 : 1; /**< Should inverted ST of Channel-1 be connected to OUT1? */ + uint32_t invert_out2 : 1; /**< Should inverted ST of Channel-2 be connected to OUT2? */ + uint32_t invert_out3 : 1; /**< Should inverted ST of Channel-2 be connected to OUT3? */ + uint32_t : 27; + #else + uint32_t : 3; + uint32_t selector_out0 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT0 + Accepts enum :: XMC_CCU8_SOURCE_OUT0_t + refer OCS1 bit-field of CHC register. + @note Only available for XMC1400 series */ + uint32_t : 2; + uint32_t selector_out1 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT1 + Accepts enum :: XMC_CCU8_SOURCE_OUT1_t + refer OCS2 bit-field of CHC register. + @note Only available for XMC1400 series */ + uint32_t : 2; + uint32_t selector_out2 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT2 + Accepts enum :: XMC_CCU8_SOURCE_OUT2_t + refer OCS3 bit-field of CHC register. + @note Only available for XMC1400 series */ + uint32_t : 2; + uint32_t selector_out3 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT3 + Accepts enum :: XMC_CCU8_SOURCE_OUT3_t + refer OCS4 bit-field of CHC register. + @note Only available for XMC1400 series */ + uint32_t : 14; + #endif + }; + uint32_t chc; + }; + uint32_t prescaler_initval : 4; /**< Initial prescaler divider value + Accepts enum :: XMC_CCU8_SLICE_PRESCALER_t */ + uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to. + Range : [0 to 15] */ + uint32_t dither_limit : 4; /**< The value that determines the spreading of dithering + Range : [0 to 15] */ + uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer if true*/ +} XMC_CCU8_SLICE_COMPARE_CONFIG_t; + +/** + * Configuration data structure for CCU8 slice. Specifically configures the CCU8 slice to capture mode operation. + * This excludes event and function configuration. + */ +typedef struct XMC_CCU8_SLICE_CAPTURE_CONFIG +{ + union + { + struct + { + uint32_t : 4; + uint32_t fifo_enable : 1; /**< Should the capture registers be setup as a FIFO?(Extended capture mode) */ + uint32_t timer_clear_mode : 2; /**< How should the timer register be cleared upon detection of capture event? + Accepts enum ::XMC_CCU8_SLICE_TIMER_CLEAR_MODE_t */ + uint32_t : 4; + uint32_t same_event : 1; /**< Should the capture event for C1V/C0V and C3V/C2V be same capture edge? */ + uint32_t ignore_full_flag : 1; /**< Should updates to capture registers follow full flag rules? */ + uint32_t : 3; + uint32_t prescaler_mode: 1; /**< Normal or floating prescaler Accepts enum :: XMC_CCU8_SLICE_PRESCALER_MODE_t*/ + uint32_t : 15; + }; + uint32_t tc; + }; + uint32_t prescaler_initval : 4; /**< Prescaler divider value */ + uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to */ + uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer */ +} XMC_CCU8_SLICE_CAPTURE_CONFIG_t; +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +__STATIC_INLINE bool XMC_CCU8_IsValidModule(const XMC_CCU8_MODULE_t *const module) +{ + bool tmp = false; + + tmp = (module == CCU80); + +#if defined(CCU81) + tmp = tmp || (module == CCU81); +#endif + + return tmp; +} + +__STATIC_INLINE bool XMC_CCU8_IsValidSlice(const XMC_CCU8_SLICE_t *const slice) +{ + bool tmp = false; + + tmp = (slice == CCU80_CC80); +#if defined(CCU80_CC81) + tmp = tmp || (slice == CCU80_CC81); +#endif +#if defined(CCU80_CC82) + tmp = tmp || (slice == CCU80_CC82); +#endif +#if defined(CCU80_CC83) + tmp = tmp || (slice == CCU80_CC83); +#endif +#if defined(CCU81) + tmp = tmp || (slice == CCU81_CC80); +#if defined(CCU81_CC81) + tmp = tmp || (slice == CCU81_CC81); +#endif +#if defined(CCU81_CC82) + tmp = tmp || (slice == CCU81_CC82); +#endif +#if defined(CCU81_CC83) + tmp = tmp || (slice == CCU81_CC83); +#endif +#endif + + return tmp; +} + +/** + * @param module Constant pointer to CCU8 module + * @param mcs_action multi-channel shadow transfer request configuration + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of global register GCTRL.\n\n + * As part of module initialization, behaviour of the module upon detection + * Multi-Channel Mode trigger is configured. Will also invoke the XMC_CCU8_EnableModule(). + * The API call would bring up the required CCU8 module and also initialize the module for + * the required multi-channel shadow transfer. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_CompareInit()
XMC_CCU8_SLICE_CaptureInit(). + */ +void XMC_CCU8_Init(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_SLICE_MCMS_ACTION_t mcs_action); + +/** + * @param module Constant pointer to CCU8 module + * @return
+ * None
+ * + * \parDescription:
+ * Enables the CCU8 module and brings it to active state.\n\n + * Also disables the gating of the clock signal (if applicable depending on the device being selected). + * Invoke this API before any operations are done on the CCU8 module. Invoked from XMC_CCU8_Init(). + * + * \parRelated APIs:
+ * XMC_CCU8_SetModuleClock()
XMC_CCU8_DisableModule()
XMC_CCU8_StartPrescaler(). + */ +void XMC_CCU8_EnableModule(XMC_CCU8_MODULE_t *const module); + +/** + * @param module Constant pointer to CCU8 module + * @return
+ * None
+ * + * \parDescription:
+ * Brings the CCU8 module to reset state and enables gating of the clock signal(if applicable depending + * on the device being selected).\n\n + * Invoke this API when a CCU8 module needs to be disabled completely. + * Any operation on the CCU8 module will have no effect after this API is called. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableModule()
XMC_CCU8_DisableModule(). + */ +void XMC_CCU8_DisableModule(XMC_CCU8_MODULE_t *const module); + +/** + * @param module Constant pointer to CCU8 module + * @param clock Choice of input clock to the module + * @return
+ * None
+ * + * \parDescription:
+ * Selects the Module Clock by configuring GCTRL.PCIS bits.\n\n + * There are 3 potential clock sources. This API helps to select the required clock source. + * Call to this API is valid after the XMC_CCU8_Init(). + * + * \parRelated APIs:
+ * None.
+ */ +void XMC_CCU8_SetModuleClock(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_CLOCK_t clock); + + +/** + * @param module Constant pointer to CCU8 module + * @return
+ * None
+ * + * \parDescription:
+ * Starts the prescaler and restores clocks to the timer slices, by setting GIDLC.SPRB bit.
\n + * Once the input to the prescaler has been chosen and the prescaler divider of all slices programmed, + * the prescaler itself may be started. Invoke this API after XMC_CCU8_Init() + * (Mandatory to fully initialize the module). + * + * \parRelated APIs:
+ * XMC_CCU8_Init()
XMC_CCU8_EnableClock()
XMC_CCU8_DisableClock()
XMC_CCU8_StartPrescaler()
+ * XMC_CCU8_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_StartPrescaler(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_StartPrescaler:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + module->GIDLC |= (uint32_t) CCU8_GIDLC_SPRB_Msk; +} + +/** + * @param module Constant pointer to CCU8 module + * @return
+ * None
+ * + * \parDescription:
+ * Stops the prescaler and blocks clocks to the timer slices, by setting GIDLS.CPRB bit.\n\n + * Clears the run bit of the prescaler. Ensures that the module clock is not supplied to + * the slices of the module. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableClock()
XMC_CCU8_DisableClock()
XMC_CCU8_StartPrescaler()
XMC_CCU8_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_StopPrescaler(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_StopPrescaler:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + module->GIDLS |= (uint32_t) CCU8_GIDLS_CPRB_Msk; +} + +/** + * @param module Constant pointer to CCU8 module + * @return
+ * None
+ * + * \parDescription:
+ * Returns the state of the prescaler, by reading GSTAT.PRB bit.\n\n + * If clock is being supplied to the slices of the module then returns as true. + * + * \parRelated APIs:
+ * XMC_CCU8_StartPrescaler()
XMC_CCU8_StopPrescaler()
XMC_CCU8_EnableClock()
XMC_CCU8_DisableClock(). + */ +__STATIC_INLINE bool XMC_CCU8_IsPrescalerRunning(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_IsPrescalerRunning:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + return((bool)((module->GSTAT & (uint32_t) CCU8_GSTAT_PRB_Msk) == CCU8_GSTAT_PRB_Msk)); +} + +/** + * @param module Constant pointer to CCU8 module + * @param clock_mask Slices whose clocks are to be enabled simultaneously. + * Bit location 0/1/2/3 represents slice-0/1/2/3 respectively. + * Range: [0x1 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Enables clocks of multiple slices at a time, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * GIDLC.CS3I bits.\n\n + * Takes an input clock_mask, which determines the slices that would receive the clock. Bring them out + * of the idle state simultaneously. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableClock()
XMC_CCU8_DisableClock(). + */ +__STATIC_INLINE void XMC_CCU8_EnableMultipleClocks(XMC_CCU8_MODULE_t *const module, const uint8_t clock_mask) +{ + XMC_ASSERT("XMC_CCU8_EnableMultipleClocks:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_EnableMultipleClocks:Invalid clock mask", (clock_mask < 16U)); + + module->GIDLC |= (uint32_t) clock_mask; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param compare_init Pointer to slice configuration structure + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of a CC8 slice to compare mode, by configuring CC8yTC, CC8yCMC, CC8yPSC, CC8yDITH, CC8yPSL, + * CC8yFPCS, CC8yCHC registers.\n\n + * CC8 slice is configured with Timer configurations in this routine. Timer is stopped before initialization + * by calling XMC_CCU8_SLICE_StopTimer(). After initialization user has to explicitly enable + * the shadow transfer for the required values by calling XMC_CCU8_EnableShadowTransfer() with appropriate mask. + * + * \parRelated APIs:
+ * None. + */ +void XMC_CCU8_SLICE_CompareInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CONFIG_t *const compare_init); + +/** + * @param slice Constant pointer to CC8 Slice + * @param capture_init Pointer to slice configuration structure + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of a CC8 slice to capture mode, by configuring CC8yTC, CC8yCMC, CC8yPSC,CC8yFPCS registers.\n\n + * CC8 slice is configured with Capture configurations in this routine. Timer is stopped before initialization + * by calling XMC_CCU8_SLICE_StopTimer(). After initialization user has to explicitly enable the shadow transfer + * for the required values by calling XMC_CCU8_EnableShadowTransfer() with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_Capture0Config()
XMC_CCU8_SLICE_Capture1Config(). + */ +void XMC_CCU8_SLICE_CaptureInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_CAPTURE_CONFIG_t *const capture_init); + +/** + * @param module Constant pointer to CCU8 module + * @param slice_number Slice for which the clock should be Enabled. + * Range: [0x0 to 0x3] + * @return
+ * None
+ * + * \parDescription:
+ * Enables the slice timer clock, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * GIDLC.CS3I bits according to the selected \a slice_number.\n\n + * It is possible to enable/disable clock at slice level. This uses the \b slice_number to indicate the + * slice whose clock needs to be enabled. Directly accessed register is GIDLC. + * + * \parRelated APIs:
+ * XMC_CCU8_DisableClock()
XMC_CCU8_EnableMultipleClocks()
XMC_CCU8_StartPrescaler()
XMC_CCU8_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_EnableClock(XMC_CCU8_MODULE_t *const module, const uint8_t slice_number) +{ + XMC_ASSERT("XMC_CCU8_EnableClock:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_EnableClock:Invalid Slice Number", (slice_number < 4U)); + + module->GIDLC |= ((uint32_t) 1 << slice_number); +} + +/** + * @param module Constant pointer to CCU8 module + * @param slice_number Slice for which the clock should be disabled. + * Range: [0x0 to 0x3] + * @return
+ * None
+ * + * \parDescription:
+ * Disables the slice timer clock, by configuring GIDLS.SS0I, GIDLS.SSS1I, GIDLS.SSS2I, + * GIDLS.SSS3I bits according to the selected \a slice_number .\n\n + * It is possible to disable clock at slice level using the module pointer. + * \b slice_number is used to disable the clock to a given slice of the module. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableClock()
XMC_CCU8_EnableMultipleClocks()
XMC_CCU8_StartPrescaler()
XMC_CCU8_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_DisableClock(XMC_CCU8_MODULE_t *const module, const uint8_t slice_number) +{ + XMC_ASSERT("XMC_CCU8_DisableClock:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_DisableClock:Invalid Slice Number", (slice_number < 4U)); + + module->GIDLS |= ((uint32_t) 1 << slice_number); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param out_path_msk configuration for output path selection. + * combination of XMC_CCU8_OUT_PATH_t enum items can be used to create a mask. + * + * @return
+ * None
+ * + * \parDescription:
+ * Configure the out the path of the two compare channels with specified ST signal, by configuring the + ^ CC8yCHC register.\n\n + * + * For the two compare channels it is possible to select either direct ST signal or inverted ST signal. + * \b out_path_msk is used to set the required out put path. + * + * \parRelated APIs:
+ * None +*/ +void XMC_CCU8_SLICE_SetOutPath(XMC_CCU8_SLICE_t *const slice, const uint32_t out_path_msk); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Start Function + * @param start_mode Behaviour of slice when the start function is activated + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Start Function of the slice, by configuring CC8yCMC.ENDS and CC8yTC.ENDM bits.\n\n + * Start function is mapped with one of the 3 events. An external signal can control when a CC8 timer should start. + * Additionally, the behaviour of the slice upon activation of the start function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StopConfig()
XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_StartConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_START_MODE_t start_mode); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Stop Function + * @param end_mode Behaviour of slice when the stop function is activated + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Stop function for the slice, by configuring CC8yCMC.STRTS and CC8yTC.STRM bits.\n\n + * Stop function is mapped with one of the 3 events. An external signal can control when a CCU8 timer should stop. + * Additionally, the behaviour of the slice upon activation of the stop function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartConfig()
XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_StopConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_END_MODE_t end_mode); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External load Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Load Function for the slice, by configuring CC8yCMC.LDS bit.\n\n + * Load function is mapped with one of the 3 events. Up on occurrence of the event,\n + * if CC8yTCST.CDIR set to 0,CC8yTIMER register is reloaded with the value from compare channel 1 or + * compare channel 2\n + * if CC8yTCST.CDIR set to 1,CC8yTIMER register is reloaded with the value from period register\n + * + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_LoadConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @param ch_num Select which compare channel value has to be loaded to the Timer register during external load event. + * @return
+ * None
+ * + * \parDescription:
+ * Up on occurrence of the external load event, if CC8yTCST.CDIR set to 0, CC8yTIMER register can be reloaded\n + * with the value from compare channel 1 or compare channel 2\n + * If CC8yTC.TLS is 0, compare channel 1 value is loaded to the CC8yTIMER register\n + * If CC8yTC.TLS is 1, compare channel 2 value is loaded to the CC8yTIMER register\n + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_LoadSelector(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Modulation Function + * @param mod_mode Desired Modulation mode + * @param channel Specify the channel(s) on which the modulation should be applied. + * @param synch_with_pwm Option to synchronize modulation with PWM start + * Pass \b true if the modulation needs to be synchronized with PWM signal. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Output Modulation Function of the slice, by configuring CC8yCMC.MOS, CC8yTC.EMT and + * CC8yTC.EMS bits.\n\n + * Modulation function is mapped with one of the 3 events. The output signal of the CCU can + * be modulated according to a external input. Additionally, the behaviour of the slice upon activation + * of the modulation function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_ModulationConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_MODULATION_MODE_t mod_mode, + const XMC_CCU8_SLICE_MODULATION_CHANNEL_t channel, + const bool synch_with_pwm + ); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Count Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Count Function of the slice, by configuring CC8yCMC.CNTS bit.\n\n + * Count function is mapped with one of the 3 events. CCU8 slice can take an external + * signal to act as the counting event. The CCU8 slice would count the + * edges present on the \b event selected. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_CountConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Gating Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Gating Function of the slice, by configuring CC8yCMC.GATES bit.\n\n + * Gating function is mapped with one of the 3 events. A CCU8 slice can use an input signal that would + * operate as counter gating. If the configured Active level is detected the counter will gate all the pulses. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_GateConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the Capture-0 Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Capture-0 Function of the slice, by configuring CC8yCMC.CAP0S bit.\n\n + * Capture function is mapped with one of the 3 events. A CCU8 slice can be configured into capture-0 mode + * with the selected \b event. In this mode the CCU8 will capture the timer value into CC8yC0V and CC8yC1V. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_Capture0Config(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the Capture-1 Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Capture-1 Function of the slice, by configuring CC8yCMC.CAP1S bit.\n\n + * Capture function is mapped with one of the 3 events. A CCU8 slice can be configured into capture-1 + * mode with the selected \b event. In this mode the CCU8 will capture the timer value into CC8yC2V and CC8yC3V. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_Capture1Config(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * bool would return true if the extended capture read back mode is enabled
+ * + * \parDescription:
+ * Checks if Extended capture mode read is enabled for particular slice or not, by reading CC8yTC.ECM bit.\n\n + * In this mode the there is only one associated read address for all the capture registers. + * Individual capture registers can still be accessed in this mode. + * + * \parRelated APIs:
+ * XMC_CCU8_GetCapturedValueFromFifo(). + */ +__STATIC_INLINE bool XMC_CCU8_SLICE_IsExtendedCapReadEnabled(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_IsPrescalerRunning:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((bool)((slice->TC & (uint32_t) CCU8_CC8_TC_ECM_Msk) == (uint32_t)CCU8_CC8_TC_ECM_Msk)); +} + +#if defined(CCU8V1) /* Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only */ +/** + * @param module Constant pointer to CCU8 module + * @param slice_number to check whether read value belongs to required slice or not + * @return
+ * int32_t Returns -1 if the FIFO value being retrieved is not from the \b slice_number. + * Returns the value captured in the \b slice_number, if captured value is from the correct slice. + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Read captured value from FIFO(ECRD register).\n\n + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * derived/inferred from the captured values. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_IsExtendedCapReadEnabled(). + */ +int32_t XMC_CCU8_GetCapturedValueFromFifo(const XMC_CCU8_MODULE_t *const module, const uint8_t slice_number); +#else +/** + * @param slice Constant pointer to CC8 Slice + * @param set The capture register set from which the captured value is to be retrieved + * @return
+ * uint32_t Returns the value captured in the \b slice_number + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Read captured value from FIFO(CC8yECRD0 and CC8yECRD1).\n\n + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * derived/inferred from the captured values. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_IsExtendedCapReadEnabled(). + * @note Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only. For other devices use XMC_CCU8_GetCapturedValueFromFifo() API + */ +uint32_t XMC_CCU8_SLICE_GetCapturedValueFromFifo(const XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_CAP_REG_SET_t set); +#endif + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Count Direction Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Count Direction of the slice, by configuring CC8yCMC.UDS bit.\n\n + * Count direction function is mapped with one of the 3 events. A slice can be configured to change the + * CC8yTIMER count direction depending on an external signal. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_DirectionConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Configures the status bit override Function of the slice, by configuring CC8yCMC.OFS bit.\n\n + * Status bit override function is mapped with one of the 3 events. A slice can be configured to change the + * output of the timer's CC8yST1 signal depending on an external signal. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent(). + */ +void XMC_CCU8_SLICE_StatusBitOverrideConfig(XMC_CCU8_SLICE_t *const slice); + +/** + * @param slice Constant pointer to CC8 Slice + * @param exit_mode How should a previously logged trap state be exited? + * @param synch_with_pwm Should exit of trap state be synchronized with PWM cycle start? + * @return
+ * None
+ * + * + * \parDescription:
+ * Configures the Trap Function of the slice, by configuring CC8yCMC.TS, CC8yTC.TRPSE, and CC8yTC.TRPSW bits.\n\n + * Trap function is mapped with Event-2. Criteria for exiting the trap state is configured. + * This trap function allows PWM outputs to react on the state of an input pin. + * Thus PWM output can be forced to inactive state upon detection of a trap. + * It is also possible to synchronize the trap function with the PWM signal using the \b synch_with_pwm. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_TrapConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_TRAP_EXIT_MODE_t exit_mode, + bool synch_with_pwm); + +/** + * @param slice Constant pointer to CC8 Slice + * @param ev1_config Pointer to event 1 configuration data + * @param ev2_config Pointer to event 2 configuration data + * @return
+ * None
+ * + * + * \parDescription:
+ * Map Status bit override function with an Event1 & Event 2 of the slice and configure CC8yINS register.\n\n + * Details such as the input mapped to the event, event detection criteria and Low Pass filter options are programmed + * by this routine for the events 1 & 2. Event-1 input would be the trigger to override the value. + * Event-2 input would be the override value. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StatusBitOverrideConfig(). + */ +void XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev2_config); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event The External Event which needs to be configured. + * @param config Pointer to event configuration data. + * @return
+ * None
+ * + * \parDescription:
+ * Configures an External Event of the slice, by updating CC8yINS register .\n\n + * Details such as the input mapped to the event, event detection criteria and low pass filter + * options are programmed by this routine. The Event \b config will configure the input selection, + * the edge selection, the level selection and the Low pass filter for the event. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartConfig()
XMC_CCU8_SLICE_StopConfig()
XMC_CCU8_SLICE_LoadConfig()
+ * XMC_CCU8_SLICE_ModulationConfig()
XMC_CCU8_SLICE_CountConfig()
XMC_CCU8_SLICE_GateConfig()
+ * XMC_CCU8_SLICE_Capture0Config()
XMC_CCU8_SLICE_Capture1Config()
XMC_CCU8_SLICE_DirectionConfig()
+ * XMC_CCU8_SLICE_StatusBitOverrideConfig()
XMC_CCU8_SLICE_TrapConfig(). + */ +void XMC_CCU8_SLICE_ConfigureEvent(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *config); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event The External Event which needs to be configured. + * @param input One of the 16 inputs meant to be mapped to the desired event + * @return
+ * None
+ * + * + * \parDescription:
+ * Selects an input for an external event, by configuring CC8yINS register.\n\n + * It is possible to select one of the possible 16 input signals for a given Event. + * This configures the CC8yINS.EVxIS for the selected event. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartConfig()
XMC_CCU8_SLICE_StopConfig()
XMC_CCU8_SLICE_LoadConfig()
+ * XMC_CCU8_SLICE_ModulationConfig()
XMC_CCU8_SLICE_CountConfig()
XMC_CCU8_SLICE_GateConfig()
+ * XMC_CCU8_SLICE_Capture0Config()
XMC_CCU8_SLICE_Capture1Config()
XMC_CCU8_SLICE_DirectionConfig()
+ * XMC_CCU8_SLICE_StatusBitOverrideConfig()
XMC_CCU8_SLICE_TrapConfig(). + */ +void XMC_CCU8_SLICE_SetInput(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_INPUT_t input); + +/** + * @param slice Constant pointer to CC8 Slice + * @param out_mask Output signals for which the Trap function needs to be activated. + * Use ::XMC_CCU8_SLICE_OUTPUT_t enum items to create a mask of choice, + * using a bit wise OR operation + * Range: [0x1 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Enables the trap feature, by setting CC8yTC.TRAPE0, CC8yTC.TRAPE1, CC8yTC.TRAPE2 and CC8yTC.TRAPE3 bit based on the + * \a out_mask.\n\n + * A particularly useful feature where the PWM output can be forced inactive upon detection of a trap. The trap signal + * can be the output of a sensing element which has just detected an abnormal electrical condition. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_TrapConfig()
XMC_CCU8_SLICE_DisableTrap()
XMC_CCU8_SLICE_ConfigureEvent()
+ * XMC_CCU8_SLICE_SetInput(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableTrap(XMC_CCU8_SLICE_t *const slice, const uint32_t out_mask) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableTrap:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TC |= (uint32_t)out_mask << CCU8_CC8_TC_TRAPE0_Pos; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param out_mask Output signals for which the Trap function needs to be deactivated. + * Use ::XMC_CCU8_SLICE_OUTPUT_t enum items to create a mask of choice, + * using a bit wise OR operation. + * Range: [0x1 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Disables the trap feature, by clearing CC8yTC.TRAPE0, CC8yTC.TRAPE1, CC8yTC.TRAPE2 and CC8yTC.TRAPE3 bit based on the + * \a out_mask.\n\n.\n\n + * This API will revert the changes done by XMC_CCU8_SLICE_EnableTrap(). + * This Ensures that the TRAP function has no effect on the output of the CCU8 slice. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableTrap(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableTrap(XMC_CCU8_SLICE_t *const slice, const uint32_t out_mask) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableTrap:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + + slice->TC &= ~((uint32_t)out_mask << CCU8_CC8_TC_TRAPE0_Pos); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * bool returns \b true if the Timer is running else it returns \b false. + * + * \parDescription:
+ * Returns the state of the timer (Either Running or stopped(idle)), by reading CC8yTCST.TRB bit. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartTimer()
XMC_CCU8_SLICE_StopTimer(). + */ +__STATIC_INLINE bool XMC_CCU8_SLICE_IsTimerRunning(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetTimerStatus:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return(bool)(((slice->TCST) & CCU8_CC8_TCST_TRB_Msk) == (uint32_t)CCU8_CC8_TCST_TRB_Msk); +} + +/** + * @param slice Pointer to an instance of CC8 slice + * @return
+ * bool returns \b true if the dead time counter of Compare channel-1 is running else it returns \b false. + * + * \parDescription:
+ * Returns the state of the Dead time counter 1 (Either Running or stopped(idle)), by reading CC8yTCST.DTR1 bit. + * This returns the state of the dead time counter which is linked to Compare channel-1. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). + */ +__STATIC_INLINE bool XMC_CCU8_SLICE_IsDeadTimeCntr1Running(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_IsDeadTimeCntr1Running:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return(bool)(((slice->TCST) & CCU8_CC8_TCST_DTR1_Msk) == (uint32_t)CCU8_CC8_TCST_DTR1_Msk); +} + +/** + * @param slice Pointer to an instance of CC8 slice + * @return
+ * bool returns \b true if the dead time counter of Compare channel-2 is running else it returns \b false. + * + * \parDescription:
+ * Returns the state of the Dead time counter 2 (Either Running or stopped(idle)), by reading CC8yTCST.DTR2 bit. + * This returns the state of the dead time counter which is linked to Compare channel-2. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_IsDeadTimeCntr1Running(). + */ +__STATIC_INLINE bool XMC_CCU8_SLICE_IsDeadTimeCntr2Running(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_IsDeadTimeCntr2Running:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return(bool)(((slice->TCST) & CCU8_CC8_TCST_DTR2_Msk) == (uint32_t)CCU8_CC8_TCST_DTR2_Msk); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * ::XMC_CCU8_SLICE_TIMER_COUNT_DIR_t returns the direction in which the timer is counting. + * + * \parDescription:
+ * Returns the timer counting direction, by reading CC8yTCST.CDIR bit.\n\n + * This API will return the direction in which the timer is currently + * incrementing(XMC_CCU8_SLICE_TIMER_COUNT_DIR_UP) or decrementing (XMC_CCU8_SLICE_TIMER_COUNT_DIR_DOWN). + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_CCU8_SLICE_TIMER_COUNT_DIR_t XMC_CCU8_SLICE_GetCountingDir(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetCountingDir:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((XMC_CCU8_SLICE_TIMER_COUNT_DIR_t)(((slice->TCST) & CCU8_CC8_TCST_CDIR_Msk) >> CCU8_CC8_TCST_CDIR_Pos)); +} +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Starts the timer counting operation, by setting CC8yTCSET.TRBS bit.\n\n + * It is necessary to have configured the CC8 slice before starting its timer. + * Before the Timer is started ensure that the clock is provided to the slice. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StopTimer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_StartTimer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_StartTimer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TCSET = CCU8_CC8_TCSET_TRBS_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Stops the Timer.\n\n + * Timer counting operation can be stopped by invoking this API, by setting CC8yTCCLR.TRBC bit. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_StopTimer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_StopTimer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TCCLR = (uint32_t) CCU8_CC8_TCCLR_TRBC_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Resets the timer count to zero, by setting CC8yTCCLR.TCC bit.\n\n + * A timer which has been stopped can still retain the last counted value. + * After invoking this API the timer value will be cleared. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_ClearTimer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ClearTimer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TCCLR = (uint32_t) CCU8_CC8_TCCLR_TCC_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Stops and resets the timer count to zero, by setting CC8yTCCLR.TCC and CC8yTCCLR.TRBC bit.\n\n + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_StopClearTimer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_StopClearTimer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TCCLR = CCU8_CC8_TCCLR_TRBC_Msk | CCU8_CC8_TCCLR_TCC_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * ::XMC_CCU8_SLICE_MODE_t returns XMC_CCU8_SLICE_MODE_COMPARE if the slice is operating in compare mode + * returns XMC_CCU8_SLICE_MODE_CAPTURE if the slice is operating in capture mode + * + * \parDescription:
+ * Retrieves the current mode of operation in the slice (either Capture mode or Compare mode), by reading + * CC8yTC.CMOD bit.\n\n + * Ensure that before invoking this API the CCU8 slice should be configured otherwise the output of this API is + * invalid. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_CCU8_SLICE_MODE_t XMC_CCU8_SLICE_GetSliceMode(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetSliceMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((XMC_CCU8_SLICE_MODE_t)(((slice->TC) & CCU8_CC8_TC_CMOD_Msk) >> CCU8_CC8_TC_CMOD_Pos)); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param mode Desired repetition mode (Either single shot or Continuous) + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Timer to either Single shot mode or continuous mode, by configuring CC8yTC.TSSM bit.\n\n + * The timer will count up to the terminal count as specified in the period register and stops immediately if the repeat + * mode has been set to single shot. In the continuous mode of operation, the timer starts counting all over again after + * reaching the terminal count. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetTimerRepeatMode(). + */ +void XMC_CCU8_SLICE_SetTimerRepeatMode(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t mode); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * ::XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t returns XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT if continuous mode is selected + * returns XMC_CCU8_SLICE_TIMER_REPEAT_MODE_SINGLE if single shot mode is selected + * + * \parDescription:
+ * Retrieves the Timer repeat mode, either Single shot mode or continuous mode, by reading CC8yTC.TSSM bit.\n\n + * The timer will count upto the terminal count as specified in the period register and stops immediately if the repeat + * mode has been set to single shot mode. In the continuous mode of operation, the timer starts counting + * all over again after reaching the terminal count. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetTimerRepeatMode(). + */ +__STATIC_INLINE XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t XMC_CCU8_SLICE_GetTimerRepeatMode( + const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t)(((slice->TC) & CCU8_CC8_TC_TSSM_Msk) >> CCU8_CC8_TC_TSSM_Pos)); +} +/** + * @param slice Constant pointer to CC8 Slice + * @param mode Desired counting mode (Either Edge Aligned or Center Aligned) + * @return
+ * None
+ * + * \parDescription:
+ * Configures the timer counting mode either Edge Aligned or Center Aligned, by configuring CC8yTC.TCM bit.\n\n + * In the edge aligned mode, the timer counts from 0 to the terminal count. Once the timer count has reached a preset + * compare value, the timer status output asserts itself. It will now deassert only after the timer count reaches the + * terminal count.\n In the center aligned mode, the timer first counts from 0 to the terminal count and then back to 0. + * During this upward and downward counting, the timer status output stays asserted as long as the timer value is + * greater than the compare value. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetTimerCountingMode(). + */ +void XMC_CCU8_SLICE_SetTimerCountingMode(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_TIMER_COUNT_MODE_t mode); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * ::XMC_CCU8_SLICE_TIMER_COUNT_MODE_t returns XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA if edge aligned mode is selected + * returns XMC_CCU8_SLICE_TIMER_COUNT_MODE_CA if center aligned mode is selected + * + * \parDescription:
+ * Retrieves timer counting mode either Edge aligned or Center Aligned, by reading CC8yTC.TCM bit.\n\n + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetTimerCountingMode(). + */ +__STATIC_INLINE XMC_CCU8_SLICE_TIMER_COUNT_MODE_t XMC_CCU8_SLICE_GetTimerCountingMode( + const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetTimerCountingMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((XMC_CCU8_SLICE_TIMER_COUNT_MODE_t)(((slice->TC) & CCU8_CC8_TC_TCM_Msk) >> CCU8_CC8_TC_TCM_Pos)); +} +/** + * @param slice Constant pointer to CC8 Slice + * @param period_val Timer period value + * Range: [0x0 to 0xFFFF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer period, by writing CC8yPRS register.\n\n + * The frequency of counting/ PWM frequency is determined by this value. The period value is written to a shadow + * register. Explicitly enable the shadow transfer for the the period value by calling + * XMC_CCU8_EnableShadowTransfer() with appropriate mask. If shadow transfer is enabled and the timer is running, + * a period match transfers the value from the shadow register to the actual period register. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetTimerPeriodMatch(). + */ +void XMC_CCU8_SLICE_SetTimerPeriodMatch(XMC_CCU8_SLICE_t *const slice, const uint16_t period_val); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * uint16_t returns the current timer period value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the timer period value currently effective, by reading CC8yPR register.\n\n + * If the timer is active then the value being returned is currently being used for the PWM period. + * + * \parNote:
+ * The XMC_CCU8_SLICE_SetTimerPeriodMatch() would set the new period value to a shadow register. + * This would only transfer the new values into the actual period register if the shadow transfer request + * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU8_SLICE_GetTimerPeriodMatch() + * would not reflect the new values until the shadow transfer completes. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetTimerPeriodMatch(). + */ +__STATIC_INLINE uint16_t XMC_CCU8_SLICE_GetTimerPeriodMatch(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((uint16_t) slice->PR); +} +/** + * @param slice Constant pointer to CC8 Slice + * @param channel Select the compare channel to which the \b compare_val has to programmed. + * @param compare_val Timer compare value + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer compare value, by writing CC8yCR1S and CC8yCR2S registers.\n\n + * The PWM duty cycle is determined by this value.\n\n + * The compare value is written to a shadow register. Explicitly enable the shadow transfer for + * the the period/compare value by calling XMC_CCU8_EnableShadowTransfer() with + * appropriate mask.If shadow transfer is enabled and the timer is running, + * a period match transfers the value from the shadow register to the actual compare register. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer(). + */ +void XMC_CCU8_SLICE_SetTimerCompareMatch(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, + const uint16_t compare_val); + +/** + * @param slice Constant pointer to CC8 Slice + * @param compare_val Timer compare value + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer compare1 value, by writing CC8yCR1S register.\n\n + * The PWM duty cycle is determined by this value.\n\n + * The compare value is written to a shadow register. Explicitly enable the shadow transfer for + * the the period/compare value by calling XMC_CCU8_EnableShadowTransfer() with appropriate mask. + * If shadow transfer is enabled and the timer is running, a period match transfers the value from + * the shadow register to the actual compare register. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetTimerCompareMatchChannel1(XMC_CCU8_SLICE_t *const slice, const uint16_t compare_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCompareMatchChannel1:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->CR1S = (uint32_t) compare_val; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param compare_val Timer compare value + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer compare2 value, by writing CC8yCR2S register.\n\n + * The PWM duty cycle is determined by this value.\n\n + * The compare value is written to a shadow register. Explicitly enable the shadow transfer for + * the the period/compare value by calling XMC_CCU8_EnableShadowTransfer() with appropriate mask. + * If shadow transfer is enabled and the timer is running, a period match transfers the value from + * the shadow register to the actual compare register. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetTimerCompareMatchChannel2(XMC_CCU8_SLICE_t *const slice, const uint16_t compare_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCompareMatchChannel2:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->CR2S = (uint32_t) compare_val; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param channel Select the compare channel to retrieve from. + * @return
+ * uint16_t returns the current timer compare value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the timer compare value currently effective, by reading CC8yCR1S and CC8yCR2S registers.\n\n + * If the timer is active then the value being returned is currently being for the PWM duty cycle( timer compare value). + * + * \parNote:
+ * The XMC_CCU8_SLICE_SetTimerCompareMatch() would set the new compare value to a shadow register. + * This would only transfer the new values into the actual compare register if the shadow transfer request + * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU8_SLICE_GetTimerCompareMatch() + * would not reflect the new values until the shadow transfer completes. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetTimerCompareMatch(). + */ +uint16_t XMC_CCU8_SLICE_GetTimerCompareMatch(const XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel); + +/** + * @param module Constant pointer to CCU8 module + * @param shadow_transfer_msk Shadow transfer request mask for various transfers. + * Use ::XMC_CCU8_SHADOW_TRANSFER_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Requests of shadow transfer for Period, Compare, Passive level, dither and prescaler, by configuring + * the GCSS register.\n\n + * The transfer from the shadow registers to the actual registers is done in the immediate next occurrence of the + * shadow transfer trigger after the API is called. + * + * Any call to XMC_CCU8_SLICE_SetTimerPeriodMatch()
XMC_CCU8_SLICE_SetTimerCompareMatch()
+ * XMC_XMC_CCU8_SLICE_SetPrescaler()
XMC_CCU8_SLICE_CompareInit()
XMC_CCU8_SLICE_CaptureInit(). + * must be succeeded by this API. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_CCU8_EnableShadowTransfer(XMC_CCU8_MODULE_t *const module, const uint32_t shadow_transfer_msk) +{ + XMC_ASSERT("XMC_CCU8_EnableShadowTransfer:Invalid module Pointer", XMC_CCU8_IsValidModule(module)); + module->GCSS = (uint32_t)shadow_transfer_msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * uint16_t returns the current timer value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the latest timer value, from CC8yTIMER register.\n\n + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetTimerValue(). + */ +__STATIC_INLINE uint16_t XMC_CCU8_SLICE_GetTimerValue(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetTimerValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((uint16_t) slice->TIMER); +} +/** + * @param slice Constant pointer to CC8 Slice + * @param timer_val The new timer value that has to be loaded into the TIMER register. + * Range: [0x0 to 0xFFFF] + * @return
+ * None
+ * + * \parDescription:
+ * Loads a new timer value, by setting CC8yTIMER register.\n\n + * + * \parNote:
+ * Request to load is ignored if the timer is running. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetTimerValue(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetTimerValue(XMC_CCU8_SLICE_t *const slice, const uint16_t timer_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TIMER = (uint32_t) timer_val; +} +/** + * @param slice Constant pointer to CC8 Slice + * @param period_dither Boolean instruction on dithering of period match + * @param duty_dither Boolean instruction on dithering of compare match + * @param spread Dither compare value + * @return
+ * None
+ * + * \parDescription:
+ * Enables dithering of PWM frequency and duty cycle, by configuring CC8yTC.DITHE and CC8yDITS bits.\n\n + * Some control loops are slow in updating PWM frequency and duty cycle. In such a case, a Bresenham style dithering + * can help reduce long term errors. Dithering can be applied to period and duty individually, + * this can be selected using the parameter \b period_dither and \b duty_dither. + * The \b spread would provide the dither compare value. If the dither counter value is less than this \b spread then + * the period/compare values would be dithered according to the dither mode selected. This API would invoke + * XMC_CCU8_SLICE_SetDitherCompareValue(). + * + * \parNote:
+ * After this API call, XMC_CCU8_EnableShadowTransfer() has to be called with appropriate mask + * to transfer the dither value. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DisableDithering(). + */ +void XMC_CCU8_SLICE_EnableDithering(XMC_CCU8_SLICE_t *const slice, + const bool period_dither, + const bool duty_dither, + const uint8_t spread); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables dithering of PWM frequency and duty cycle, by clearing CC8yTC.DITHE bits.\n\n + * This disables the Dither mode that was set in XMC_CCU8_SLICE_EnableDithering(). + * This API will not clear the dither compare value. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableDithering(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableDithering(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableDithering:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU8_CC8_TC_DITHE_Msk); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Enables the floating prescaler, by setting CC8yTC.FPE bit.\n\n + * The prescaler divider starts with an initial value and increments upon every period match. It keeps incrementing + * until a ceiling (prescaler compare value) is hit and thereafter rolls back to the original prescaler divider value.\n + * It is necessary to have programmed an initial divider value and a compare value before the feature is enabled. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue()
XMC_CCU8_SLICE_DisableFloatingPrescaler()
+ * XMC_XMC_CCU8_SLICE_SetPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableFloatingPrescaler(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TC |= (uint32_t) CCU8_CC8_TC_FPE_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables the floating prescaler, by clearing CC8yTC.FPE bit.\n\n + * This would return the prescaler to the normal mode. + * The prescaler that would be applied is the value present in CC8yPSC. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableFloatingPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableFloatingPrescaler(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU8_CC8_TC_FPE_Msk); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param comp_val Dither compare value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Sets the dither spread/compare value, by setting CC8yDITS.DCVS bits.\n\n + * This value is the cornerstone of PWM dithering feature. Dithering is applied/done when the value in the + * dithering counter is less than this compare/spread value. For all dithering counter values greater than + * the spread value, there is no dithering. After setting the value XMC_CCU8_EnableShadowTransfer() has to be + * called with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableDithering(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetDitherCompareValue(XMC_CCU8_SLICE_t *const slice, const uint8_t comp_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetDitherCompareValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetDitherCompareValue:Invalid Dither compare value", (comp_val <= 15U)); + + slice->DITS = comp_val; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param div_val Prescaler divider value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the slice specific prescaler divider, by configuring the CC8yPSC and CC8yFPC registers.\n\n + * The prescaler divider may only be programmed after the prescaler run bit has been cleared + * by calling XMC_CCU8_StopPrescaler(). + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue(). + */ +void XMC_CCU8_SLICE_SetPrescaler(XMC_CCU8_SLICE_t *const slice, const uint8_t div_val); + +/** + * @param slice Constant pointer to CC8 Slice + * @param cmp_val Prescaler divider compare value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the slice specific prescaler divider compare value, by configuring CC8yFPCS register.\n\n + * The compare value is applicable only in floating mode of operation. The prescaler divider starts with an initial + * value and increments to the compare value steadily upon every period match. Once prescaler divider + * equals the prescaler divider compare value, the value in the former resets back to the PVAL (from FPC). After setting + * the value, XMC_CCU8_EnableShadowTransfer() has to be called with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue(XMC_CCU8_SLICE_t *const slice, + const uint8_t cmp_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + /* First, write to the shadow register */ + slice->FPCS = (uint32_t) cmp_val; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param ch_num Compare channel for which the multi-channel mode is needed. + * @return
+ * None
+ * + * \parDescription:
+ * Enables the multichannel mode, by setting CC8yTC.MCME1 or CC8yTC.MCME1 bits based on the \a ch_num.\n\n + * The output state of the Timer slices can be controlled in parallel by a single input signal. + * A particularly useful feature in motor control applications where the PWM output of multiple slices of a module can + * be gated and ungated by multi-channel gating inputs connected to the slices. A peripheral like POSIF connected to the + * motor knows exactly which of the power drive switches are to be turned on and off at any instant. It can thus through + * a gating bus (known as multi-channel inputs) control which of the slices output stays gated/ungated. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DisableMultiChannelMode()
XMC_CCU8_SetMultiChannelShadowTransferMode(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableMultiChannelMode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableMultiChannelMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_EnableMultiChannelMode:Invalid Channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(ch_num)); + + slice->TC |= (uint32_t)CCU8_CC8_TC_MCME1_Msk << ch_num; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param ch_num Compare channel for which the multi-channel mode needs to be disabled. + * @return
+ * None
+ * + * \parDescription:
+ * Disables the multichannel mode, by clearing CC8yTC.MCME1 or CC8yTC.MCME1 bits based on the \a ch_num.\n\n + * Returns the slices to the normal operation mode. This takes the slice number as input and + * configures the multi channel mode for it. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableMultiChannelMode(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableMultiChannelMode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableMultiChannelMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_DisableMultiChannelMode:Invalid Channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(ch_num)); + + slice->TC &= ~((uint32_t)CCU8_CC8_TC_MCME1_Msk << ch_num); +} + +/** + * @param module Constant pointer to CCU8 module + * @param slice_mode_msk Slices for which the configuration has to be applied. + * Use ::XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Enables the Multi-channel shadow transfer request trigger signal either by software or hardware by configuring + * GCTRL.MSE0, GCTRL.MSE1, GCTRL.MSE2, and GCTRL.MSE3 based on the mask.\n\n + * The shadow transfer would take place either if it was requested by software or by the CCU8x.MCSS input. + * + * \parRelated APIs:
+ * None. +*/ +void XMC_CCU8_SetMultiChannelShadowTransferMode(XMC_CCU8_MODULE_t *const module, const uint32_t slice_mode_msk); + +/** + * @param slice Constant pointer to CC8 Slice + * @param reg_num The capture register from which the captured value is to be retrieved + * Range: [0,3] + * @return
+ * uint32_t Returns the Capture register value. + * Range: [0 to 0x1FFFFF] + * + * \parDescription:
+ * Retrieves timer value which has been captured in the Capture registers, by reading CC8yCV[\b reg_num] register.\n\n + * The signal whose timing characteristics are to be measured must be mapped to an event which in turn must be mapped + * to the capture function. Based on the capture criteria, the timer values are captured into capture registers. Timing + * characteristics of the input signal may then be derived/inferred from the captured values. The full flag will help + * to find out if there is a new captured value present. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetLastCapturedTimerValue(). + */ +uint32_t XMC_CCU8_SLICE_GetCaptureRegisterValue(const XMC_CCU8_SLICE_t *const slice, const uint8_t reg_num); + +/** + * @param slice Constant pointer to CC8 Slice + * @param set The capture register set, which must be evaluated + * @param val_ptr Out Parameter of the API.Stores the captured timer value into this out parameter. + * @return
+ * ::XMC_CCU8_STATUS_t Returns XMC_CCU8_STATUS_OK if there was new value present in the capture registers. + * returns XMC_CCU8_STATUS_ERROR if there was no new value present in the capture registers. + * + * \parDescription:
+ * Retrieves the latest captured timer value, by reading CC8yCV registers.\n\n + * Retrieve the timer value last stored by the slice. When separate capture events are used, + * users must specify the capture set to evaluate. If single capture event mode is used, all 8 capture registers are + * evaluated.\n + * The lowest register is evaluated first followed by the next higher ordered register and this continues until all + * capture registers have been evaluated. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetCaptureregisterValue(). + */ +XMC_CCU8_STATUS_t XMC_CCU8_SLICE_GetLastCapturedTimerValue(const XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Enables the generation of an interrupt pulse for the event, by configuring CC8yINTE register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API merely enables the event. Binding with SR is performed by another API. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetInterruptNode()
XMC_CCU8_SLICE_EnableMultipleEvents()
XMC_CCU8_SLICE_DisableEvent()
+ * XMC_CCU8_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableEvent(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_EnableEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + + slice->INTE |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param mask Event mask such that multiple events can be enabled. + * Use ::XMC_CCU8_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Enables the generation of an interrupt pulse for the required events, by configuring CC8yINTE register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API merely enables the events. Binding with SR is performed by another API. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetInterruptNode()
XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_DisableEvent()
+ * XMC_CCU8_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableMultipleEvents(XMC_CCU8_SLICE_t *const slice, const uint16_t mask) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableMultipleEvents:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->INTE = (uint32_t) mask; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Disables the generation of an interrupt pulse for the event, by clearing CC8yINTE register.\n\n + * Prevents the event from being asserted. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetInterruptNode()
XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_EnableMultipleEvents()
+ * XMC_CCU8_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableEvent(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_DisableEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + + slice->INTE &= ~(((uint32_t) 1) << ((uint32_t) event)); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param mask Event mask such that multiple events can be enabled. + * Use ::XMC_CCU8_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Disables the generation of an interrupt pulse for the required events, by clearing CC8yINTE register.\n\n + * Prevents selected events of the slice from being asserted. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetInterruptNode()
XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_EnableMultipleEvents()
+ * XMC_CCU8_SLICE_DisableEvent(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableMultipleEvents(XMC_CCU8_SLICE_t *const slice, const uint16_t mask) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableMultipleEvents:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->INTE &= ~((uint32_t) mask); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Manually asserts the requested event, by setting CC8ySWS register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API manually asserts the requested event. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetInterruptNode()
XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_EnableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetEvent(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + + slice->SWS |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Asserted event which must be acknowledged. + * @return
+ * None
+ * + * \parDescription:
+ * Acknowledges an asserted event, by setting CC8ySWR with respective event flag.\n\n + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_SetEvent()
XMC_CCU8_SLICE_GetEvent(). + * + */ +__STATIC_INLINE void XMC_CCU8_SLICE_ClearEvent(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ClearEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ClearEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + slice->SWR |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Event to be evaluated for assertion + * @return
+ * bool Returns true if event is set else false is returned. + * + * \parDescription:
+ * Evaluates if a given event is asserted or not, by reading CC8yINTS register.\n\n + * Return true if the event is asserted. For a event to be asserted it has to be + * first enabled. Only if that event is enabled the call to this API is valid. + * If the Event is enabled and has not yet occurred then a false is returned. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_SetEvent(). + */ +__STATIC_INLINE bool XMC_CCU8_SLICE_GetEvent(const XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GetEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + return(((uint32_t)(slice->INTS & ((uint32_t)1 << event))) != 0U); + } + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Event which must be bound to a service request line + * @param sr The Service request line which is bound to the \b event + * @return
+ * None
+ * + * \parDescription:
+ * Binds requested event to a service request line, by configuring CC8ySRS register with respective event.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API binds the requested event with the requested service request line(\b sr). + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_SetEvent(). + * + */ +void XMC_CCU8_SLICE_SetInterruptNode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_IRQ_ID_t event, + const XMC_CCU8_SLICE_SR_ID_t sr); + +/** + * @param slice Constant pointer to CC8 Slice + * @param out Output signal for which the passive level needs to be set. + * @param level Output passive level for the \b out signal + * @return
+ * None
+ * + * \parDescription:
+ * Configures the passive level for the slice output, by setting CC8yPSL register.\n\n + * Defines the passive level for the timer slice output pin. Selects either level high is passive + * or level low is passive. This is the level of the output before the compare match is value changes it. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_SetEvent(). + */ +void XMC_CCU8_SLICE_SetPassiveLevel(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_OUTPUT_t out, + const XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t level); + +/** + * @param slice Constant pointer to CC8 Slice + * @param config Pointer to dead time configuration data + * @return
+ * None
+ * + * \parDescription:
+ * Initializes Dead time configuration for the slice outputs, by configuring CC8yDC1R, CC8yDC2R, CC8yDTC registers.\n\n + * This routine programs dead time delays (rising & falling) and dead time clock prescaler. + * Details such as the choice of dead time for channel1, channel2, ST1, Inverted ST1, ST2, Inverted ST2, are also + * programmed by this routine. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureDeadTime()
XMC_CCU8_SLICE_SetDeadTimeValue()
XMC_CCU8_SLICE_SetDeadTimePrescaler()
+ * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). + */ +void XMC_CCU8_SLICE_DeadTimeInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_DEAD_TIME_CONFIG_t *const config); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Configures the slice to generate PWM in asymmetric compare mode, by setting CC8yCHC.ASE bit.\n\n + * In asymmetric compare mode, the compare channels 1 & 2 are grouped to generate the PWM.This would + * generate an inverted PWM at OUT0 & OUT1. + * In Edge Aligned mode (counting up), the Status bit is set when a compare match of + * Compare channel-1 occurs and cleared when a compare match event of Compare channel-2 occurs.\n + * In Center Aligned mode, the status bit is set when a compare match event of Compare channel-1 occurs while + * counting up and cleared when a compare match event of Compare channel-2 occurs while counting down. + * + * \parNote:
+ * External count direction function is enabled then the asymmetric mode of operation is not possible. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableSymmetricCompareMode()
+ */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableAsymmetricCompareMode(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableAsymmetricCompareMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->CHC |= (uint32_t) CCU8_CC8_CHC_ASE_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Configures the slice to generate PWM in symmetric(standard) compare mode, by clearing CC8yCHC.ASE bit.\n\n + * In symmetric compare mode, the compare channels 1 & 2 are independent of each other & each channel generates the + * PWM & inverted PWM at OUT0, OUT1, OUT2 & OUT3. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableAsymmetricCompareMode(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableSymmetricCompareMode(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableSymmetricCompareMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->CHC &= ~((uint32_t) CCU8_CC8_CHC_ASE_Msk); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param mask The Dead Time configuration mask. + * Do a bitwise OR operation on the following values depending on the need. + * Value 0x1: Dead Time Enable for Compare Channel 1 + * Value 0x2: Dead Time Enable for Compare Channel 2 + * Value 0x4: Dead Time Enable for CC8yST1 path is enabled. + * Value 0x8: Dead Time Enable for Inverted CC8yST1 path is enabled. + * Value 0x10: Dead Time Enable for CC8yST2 path is enabled. + * Value 0x20: Dead Time Enable for Inverted CC8yST2 path is enabled. + * Range: [0x0 to 0x3F] + * + * \parDescription:
+ * Activates or deactivates dead time for compare channel and ST path, by configuring CC8y.DC1R, CC8y.DC1R and + * CC8y.DTC registers.\n\n + * Use the provided masks to enable/disable the dead time for the compare channels and the ST signals. It is possible + * to deactivate the dead time for all the options by passing a 0x0 as the mask. + * Details such as the choice of dead time for channel1, channel2, ST1, Inverted ST1, ST2, Inverted ST2, are + * programmed by this routine. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DeadTimeInit()
XMC_CCU8_SLICE_SetDeadTimeValue()
XMC_CCU8_SLICE_SetDeadTimePrescaler()
+ * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). + */ +void XMC_CCU8_SLICE_ConfigureDeadTime(XMC_CCU8_SLICE_t *const slice, const uint8_t mask); + +/** + * @param slice Constant pointer to CC8 Slice + * @param channel Compare channel number + * @param rise_value Programs rising edge delay + * Range: [0x0 to 0xFF] + * @param fall_value Programs falling edge delay + * Range: [0x0 to 0xFF] + * @return
+ * None
+ * + * \parDescription:
+ * Configures the dead time for rising and falling edges, by updating CC8y.DC1R, CC8y.DC1R registers.\n\n + * This API will Configure the delay that is need either when the value changes from 0 to 1 (rising edge) or + * value changes from 1 to 0(falling edge). Directly accessed registers are CC8yDC1R, CC8yDC2R. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DeadTimeInit()
XMC_CCU8_SLICE_SetDeadTimeValue()
XMC_CCU8_SLICE_ConfigureDeadTime()
+ * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). + */ +void XMC_CCU8_SLICE_SetDeadTimeValue(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, + const uint8_t rise_value, + const uint8_t fall_value); + +/** + * @param slice Pointer to an instance of CC8 slice + * @param div_val Prescaler divider value + * @return
+ * None
+ * + * \parDescription:
+ * Configures clock division factor for dead time generator, by configuring CC8yDTC.DTCC bit. + * The Clock divider works on the timer clock. It is possible to scale the timer clock for the dead time + * generator by a factor of 1/2/4/8. This selection is passed as an argument to the API. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DeadTimeInit()
XMC_CCU8_SLICE_SetDeadTimeValue()
XMC_CCU8_SLICE_ConfigureDeadTime()
+ * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). + */ +void XMC_CCU8_SLICE_SetDeadTimePrescaler(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_DTC_DIV_t div_val); + +/** + * @param slice Constant pointer to CC8 Slice + * @param channel which channel status has to be give as out + * @return
+ * None
+ * + * \parDescription:
+ * Configures status ST1, ST2 mapping to STy, by configuring CC8yTC.STOS bits.\n\n + * This routine defines the output STy as a function of ST1 or ST2 or both ST1 & ST2. + * It is possible to make the CCU8x.STy signal to reflect the CC8y.ST1/CC8y.ST2 or a function of the 2 signals. + * + * \parRelated APIs:
+ * None. + */ +void XMC_CCU8_SLICE_ConfigureStatusBitOutput(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_STATUS_t channel); + +#if (UC_SERIES != XMC45) || defined(DOXYGEN) +/** + * @param slice Constant pointer to CC8 Slice + * + * @return
+ * None
+ * + * \parDescription:
+ * Cascades the shadow transfer operation throughout the CCU8 timer slices, by setting CSE bit in STC register.\n\n + * + * The shadow transfer enable bits needs to be set in all timer slices, that are being used in the cascaded architecture, + * at the same time. The shadow transfer enable bits, also need to be set for all slices even if the shadow values of + * some slices were not updated. It is possible to to cascade with the adjacent slices only. CC80 slice is a + * master to start the operation. + * + * \parNote:
+ * XMC_CCU8_EnableShadowTransfer() must be called to enable the shadow transfer of the all the slices, which needs to be + * cascaded. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer(), XMC_CCU8_SLICE_DisableCascadedShadowTransfer()
. + * @note Not available for XMC4500 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableCascadedShadowTransfer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC |= (uint32_t) CCU8_CC8_STC_CSE_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * + * @return
+ * None
+ * + * \parDescription:
+ * Disables the cascaded the shadow transfer operation, by clearing CSE bit in STC register.\n\n + * + * If in any slice the cascaded mode disabled, other slices from there onwards does not update the values in cascaded mode. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableCascadedShadowTransfer()
. + * @note Not available for XMC4500 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableCascadedShadowTransfer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC &= ~(uint32_t) CCU8_CC8_STC_CSE_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param shadow_transfer_mode mode to be configured + * Use :: XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t enum items for mode + * @return
+ * None
+ * + * \parDescription:
+ * Configures when the shadow transfer has to occur, by setting STM bit in STC register.\n\n + * + * After requesting for shadow transfer mode using XMC_CCU8_EnableShadowTransfer(), actual transfer occurs based on the + * selection done using this API (i.e. on period and One match, on Period match only, on One match only). + * + * \parNote:
+ * This is effective when the timer is configured in centre aligned mode. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer()
+ * @note Not available for XMC4500 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetShadowTransferMode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t shadow_transfer_mode) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetShadowTransferMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC = ((slice->STC) & ~(uint32_t)((uint32_t)CCU8_CC8_STC_STM_Msk << (uint32_t)CCU8_CC8_STC_STM_Pos)) | + ((shadow_transfer_mode << CCU8_CC8_STC_STM_Pos) & (uint32_t)CCU8_CC8_STC_STM_Msk); +} +#endif + +#if defined(CCU8V3) || defined(DOXYGEN)/* Defined for XMC1400 devices only */ + /** + * @param slice Constant pointer to CC8 Slice + * @param immediate_write specifies for what fields this mode has to be applied + * Use :: XMC_CCU8_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the specified fields shadow value to be updated immediately after shadow transfer request, by setting + * IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n + * + * When immediate shadow is enabled, by calling XMC_CCU8_EnableShadowTransfer() the value which are written in the + * shadow registers get updated to the actual registers immediately. \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer()
+ * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_WriteImmediateAfterShadowTransfer(XMC_CCU8_SLICE_t *const slice, + const uint32_t immediate_write) +{ + XMC_ASSERT("XMC_CCU8_SLICE_WriteImmediateAfterShadowTransfer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC |= immediate_write; +} + + /** + * @param slice Constant pointer to CC8 Slice + * @param coherent_write specifies for what fields this mode has to be applied + * Use :: XMC_CCU8_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the specified fields shadow value to be updated in synchronous with PWM after shadow transfer request, by + * clearing IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n + * + * When coherent shadow is enabled, after calling XMC_CCU8_EnableShadowTransfer(), the value which are written in the + * respective shadow registers get updated according the configuration done using XMC_CCU8_SLICE_SetShadowTransferMode() + * API. \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer(), XMC_CCU8_SLICE_SetShadowTransferMode()
+ * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_WriteCoherentlyWithPWMCycle(XMC_CCU8_SLICE_t *const slice, + const uint32_t coherent_write) +{ + XMC_ASSERT("XMC_CCU8_SLICE_WriteCoherentlyWithPWMCycle:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC &= ~(uint32_t)coherent_write; +} + + /** + * @param slice Constant pointer to CC8 Slice + * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request is generated + * Use :: XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a + * bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configure on which shadow register update, automatic shadow transfer request generation has to be enabled. By setting + * ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n + * + * By updating the configured shadow register, the shadow transfer request is generated to update all the shadow registers. + * \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest(). + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest(XMC_CCU8_SLICE_t *const slice, + const uint32_t automatic_shadow_transfer) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC |= automatic_shadow_transfer; +} + + /** + * @param slice Constant pointer to CC8 Slice + * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request should not be + * generated + * Use :: XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a + * bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configure on which shadow register update, automatic shadow transfer request generation has to be disabled. By + * clearing ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n + * + * This disables the generation of automatic shadow transfer request for the specified register update. + * \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest(). + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest(XMC_CCU8_SLICE_t *const slice, + const uint32_t automatic_shadow_transfer) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC &= ~(uint32_t)automatic_shadow_transfer; +} +#endif +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CCU80) */ + +#endif /* XMC_CCU8_H */ + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_common.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_common.h new file mode 100644 index 00000000..77ff7e07 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_common.h @@ -0,0 +1,285 @@ +/** + * @file xmc_common.h + * @date 2017-04-04 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * - Brief section updated + * - Added XMC_LIB_VERSION macro + * + * 2016-02-26: + * - Updated XMC_LIB_VERSION macro to v2.1.6 + * + * 2016-05-30: + * - Updated XMC_LIB_VERSION macro to v2.1.8 + * + * 2016-11-18: + * - Updated XMC_LIB_VERSION macro to v2.1.10 + * - Changed type of size in XMC_PRIOARRAY_t to fix compilation warnings + * + * 2017-04-04: + * - Updated XMC_LIB_VERSION macro to v2.1.12 + * + * @endcond + * + */ + +#ifndef XMC_COMMON_H +#define XMC_COMMON_H + +#include +#include +#include +#include + +#include "xmc_device.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup COMMON + * @brief Common APIs to all peripherals for XMC microcontroller family + * @{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ +#define XMC_LIB_MAJOR_VERSION (2U) +#define XMC_LIB_MINOR_VERSION (1U) +#define XMC_LIB_PATCH_VERSION (12U) + +#define XMC_LIB_VERSION ((XMC_LIB_MAJOR_VERSION << 16U) + (XMC_LIB_MINOR_VERSION << 8U) + XMC_LIB_PATCH_VERSION) + +/* Define WEAK attribute */ +#if !defined(__WEAK) +#if defined ( __CC_ARM ) +#define __WEAK __attribute__ ((weak)) +#elif defined ( __ICCARM__ ) +#define __WEAK __weak +#elif defined ( __GNUC__ ) +#define __WEAK __attribute__ ((weak)) +#elif defined ( __TASKING__ ) +#define __WEAK __attribute__ ((weak)) +#endif +#endif + +#ifdef XMC_ASSERT_ENABLE + #define XMC_ASSERT(msg, exp) { if(!(exp)) {XMC_AssertHandler(msg, __FILE__, __LINE__);} } +#else + #define XMC_ASSERT(msg, exp) { ; } +#endif + +#ifdef XMC_DEBUG_ENABLE + #include + #define XMC_DEBUG(...) { printf(__VA_ARGS__); } +#else + #define XMC_DEBUG(...) { ; } +#endif + +#define XMC_UNUSED_ARG(x) (void)x + +#define XMC_STRUCT_INIT(m) memset(&m, 0, sizeof(m)) + +#define XMC_PRIOARRAY_DEF(name, size) \ +XMC_PRIOARRAY_ITEM_t prioarray_m_##name[size + 2]; \ +XMC_PRIOARRAY_t prioarray_def_##name = {(size), (prioarray_m_##name)}; + +#define XMC_PRIOARRAY(name) \ +&prioarray_def_##name + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ +/* + * + */ +typedef struct XMC_DRIVER_VERSION +{ + uint8_t major; + uint8_t minor; + uint8_t patch; +} XMC_DRIVER_VERSION_t; + +/* + * + */ +typedef void *XMC_LIST_t; + +/* + * + */ +typedef struct XMC_PRIOARRAY_ITEM +{ + int32_t priority; + int32_t previous; + int32_t next; +} XMC_PRIOARRAY_ITEM_t; + +/* + * + */ +typedef struct XMC_PRIOARRAY +{ + int32_t size; + XMC_PRIOARRAY_ITEM_t *items; +} XMC_PRIOARRAY_t; + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * + */ +void XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line); + +/* + * + */ +void XMC_LIST_Init(XMC_LIST_t *list); + +/* + * + */ +void XMC_LIST_Add(XMC_LIST_t *list, void *const item); + +/* + * + */ +void XMC_LIST_Remove(XMC_LIST_t *list, void *const item); + +/* + * + */ +uint32_t XMC_LIST_GetLength(XMC_LIST_t *list); + +/* + * + */ +void *XMC_LIST_GetHead(XMC_LIST_t *list); + +/* + * + */ +void *XMC_LIST_GetTail(XMC_LIST_t *list); + +/* + * + */ +void XMC_LIST_Insert(XMC_LIST_t *list, void *prev_item, void *new_item); + +/* + * + */ +void XMC_PRIOARRAY_Init(XMC_PRIOARRAY_t *prioarray); + +/* + * + */ +void XMC_PRIOARRAY_Add(XMC_PRIOARRAY_t *prioarray, int32_t item, int32_t priority); + +/* + * + */ +void XMC_PRIOARRAY_Remove(XMC_PRIOARRAY_t *prioarray, int32_t item); + +/* + * + */ +__STATIC_INLINE int32_t XMC_PRIOARRAY_GetHead(XMC_PRIOARRAY_t *prioarray) +{ + XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL); + return prioarray->items[prioarray->size].next; +} + +/* + * + */ +__STATIC_INLINE int32_t XMC_PRIOARRAY_GetTail(XMC_PRIOARRAY_t *prioarray) +{ + XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL); + return prioarray->items[prioarray->size + 1].previous; +} + +/* + * + */ +__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPriority(XMC_PRIOARRAY_t *prioarray, int32_t item) +{ + XMC_ASSERT("XMC_PRIOARRAY_GetItemPriority: item out of range", (item >= 0) && (item < prioarray->size)); + return prioarray->items[item].priority; +} + +/* + * + */ +__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemNext(XMC_PRIOARRAY_t *prioarray, int32_t item) +{ + XMC_ASSERT("XMC_PRIOARRAY_GetItemNext: item out of range", (item >= 0) && (item < prioarray->size)); + return prioarray->items[item].next; +} + +/* + * + */ +__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPrevious(XMC_PRIOARRAY_t *prioarray, int32_t item) +{ + XMC_ASSERT("XMC_PRIOARRAY_GetItemPrevious: item out of range", (item >= 0) && (item < prioarray->size)); + return prioarray->items[item].previous; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XMC_COMMON_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dac.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dac.h new file mode 100644 index 00000000..2c9d8b4e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dac.h @@ -0,0 +1,1357 @@ +/** + * @file xmc_dac.h + * @date 2015-08-31 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Initial version + * + * 2015-02-20: + * - Driver description added + * + * 2015-06-19: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-08-31: + * - Help document updated + * @endcond + * + */ + +#ifndef XMC_DAC_H +#define XMC_DAC_H + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include + +/* DAC peripheral is not available on XMC1X devices. */ +#if defined(DAC) + +/** + * @addtogroup XMClib + * @{ + */ + +/** + * @addtogroup DAC + * @{ + * + * @brief Digital to Analog Converter (DAC) driver for XMC 4000 microcontroller family.
+ * + * DAC driver uses DAC peripheral to convert digital value to analog value. XMC4000 microcontroller family has two DAC channels of 12-bit resolution + * and maximum conversion rate of 2MHz with full accuracy and 5MHz with reduced accuracy. + * It consists of inbuilt pattern generator, ramp generator and noise generator modes. Additionally, waveforms can be generated by configuring data registers + * in single value mode and in data mode. + * It has DMA handling capability to generate custom waveforms in data mode without CPU intervention. + * + * DAC driver features: + * -# Configuration structure XMC_DAC_CH_CONFIG_t and initialization function XMC_DAC_CH_Init() to initialize DAC and configure channel settings + * -# Pattern Generator Mode: + * - DAC is configured in pattern generator mode using XMC_DAC_CH_StartPatternMode() + * - XMC_DAC_CH_SetPattern() is used to set the waveform pattern values in pattern register for one quarter + * - Allows to change the trigger frequency using XMC_DAC_CH_SetPatternFrequency() + * -# Single Value Mode: + * - DAC is configured in single value mode using XMC_DAC_CH_StartSingleValueMode() + * - Allows to change the trigger frequency using XMC_DAC_CH_SetFrequency() + * -# Data Mode: + * - DAC is configured in data mode using XMC_DAC_CH_StartDataMode() + * - Allows to change the trigger frequency using XMC_DAC_CH_SetFrequency() + * -# Ramp Mode: + * - DAC is configured in ramp generator mode using XMC_DAC_CH_StartRampMode() + * - Allows to change the trigger frequency using XMC_DAC_CH_SetRampFrequency() + * - Allows to set the start and stop values of the ramp using XMC_DAC_CH_SetRampStart() and XMC_DAC_CH_SetRampStop() + * -# Noise Mode: + * - DAC is configured in noise mode using XMC_DAC_CH_StartNoiseMode() + * - Allows to change the trigger frequency using XMC_DAC_CH_SetFrequency() + * -# Allows to change the scale, offset dynamically using XMC_DAC_CH_SetOutputScale() and XMC_DAC_CH_SetOutputOffset() respectively + * -# Allows to select one of the eight possible trigger sources using XMC_DAC_CH_SetTrigger() + * -# 2 DAC channels can be used in synchronization in single value mode and data mode to generate two analog outputs in sync. XMC_DAC_EnableSimultaneousDataMode() + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define XMC_DAC0 ((XMC_DAC_t *)DAC_BASE) /**< DAC module register base */ + +#define XMC_DAC_DACCFG_NEGATE_Msk (0x10000000UL) /*< DAC negation enable mask in XMC44 device */ +#define XMC_DAC_NO_CHANNELS (2U) /**< DAC maximum channels */ +#define XMC_DAC_SAMPLES_PER_PERIOD (32U) /**< DAC samples per period in pattern mode */ + +#define XMC_DAC_PATTERN_TRIANGLE {0U, 4U, 8U, 12U, 16U, 19U, 23U, 27U, 31U} /**< First quarter Triangle waveform samples */ +#define XMC_DAC_PATTERN_SINE {0U, 6U, 12U, 17U, 22U, 26U, 29U, 30U, 31U} /**< First quarter Sine waveform samples */ +#define XMC_DAC_PATTERN_RECTANGLE {31U, 31U, 31U, 31U, 31U, 31U, 31U, 31U, 31U} /**< First quarter Rectangle waveform samples */ + +#define XMC_DAC_IS_DAC_VALID(PTR) ((PTR) == XMC_DAC0) +#define XMC_DAC_IS_CHANNEL_VALID(CH) (CH < XMC_DAC_NO_CHANNELS) +#define XMC_DAC_IS_TRIGGER_VALID(TRIGGER) ((TRIGGER == XMC_DAC_CH_TRIGGER_INTERNAL) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_CCU80_SR1) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_CCU40_SR1) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_CCU41_SR1) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_P2_9) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_P2_8) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_U0C0_DX1INS) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_U1C0_DX1INS) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_SOFTWARE)) +#define XMC_DAC_IS_MODE_VALID(MODE) ((MODE == XMC_DAC_CH_MODE_IDLE) ||\ + (MODE == XMC_DAC_CH_MODE_SINGLE) ||\ + (MODE == XMC_DAC_CH_MODE_DATA) ||\ + (MODE == XMC_DAC_CH_MODE_PATTERN) ||\ + (MODE == XMC_DAC_CH_MODE_NOISE) ||\ + (MODE == XMC_DAC_CH_MODE_RAMP)) +#define XMC_DAC_IS_OUTPUT_SCALE_VALID(SCALE) ((SCALE == XMC_DAC_CH_OUTPUT_SCALE_NONE) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_2) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_4) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_8) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_16) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_32) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_64) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_128) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_2) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_4) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_8) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_16) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_32) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_64) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_128)) + + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * Return types of the API's + */ +typedef enum XMC_DAC_CH_STATUS +{ + XMC_DAC_CH_STATUS_OK = 0U, /**< Status is ok, no error detected */ + XMC_DAC_CH_STATUS_ERROR = 1U, /**< Error detected */ + XMC_DAC_CH_STATUS_BUSY = 2U, /**< DAC is busy */ + XMC_DAC_CH_STATUS_ERROR_FREQ2LOW = 3U, /**< Frequency can't be configured. Frequency is to low. */ + XMC_DAC_CH_STATUS_ERROR_FREQ2HIGH = 4U /**< Frequency can't be configured. Frequency is to high. */ +} XMC_DAC_CH_STATUS_t; + +/** + * Operating modes of DAC + */ +typedef enum XMC_DAC_CH_MODE +{ + XMC_DAC_CH_MODE_IDLE = 0x0U << DAC_DAC0CFG0_MODE_Pos, /**< DAC is disabled */ + XMC_DAC_CH_MODE_SINGLE = 0x1U << DAC_DAC0CFG0_MODE_Pos, /**< Single value mode - single data value is updated and maintained */ + XMC_DAC_CH_MODE_DATA = 0x2U << DAC_DAC0CFG0_MODE_Pos, /**< Data mode - continuous data processing */ + XMC_DAC_CH_MODE_PATTERN = 0x3U << DAC_DAC0CFG0_MODE_Pos, /**< Pattern mode - inbuilt pattern waveform generation - + Sine, Triangle, Rectangle */ + XMC_DAC_CH_MODE_NOISE = 0x4U << DAC_DAC0CFG0_MODE_Pos, /**< Noise mode - pseudo-random noise generation */ + XMC_DAC_CH_MODE_RAMP = 0x5U << DAC_DAC0CFG0_MODE_Pos /**< Ramp mode - ramp generation */ +} XMC_DAC_CH_MODE_t; + +/** + * Trigger sources for the data update + */ +typedef enum XMC_DAC_CH_TRIGGER +{ + XMC_DAC_CH_TRIGGER_INTERNAL = + (0x0U << DAC_DAC0CFG1_TRIGMOD_Pos), /**< Internal trigger as per frequency divider value */ + XMC_DAC_CH_TRIGGER_EXTERNAL_CCU80_SR1 = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | 0x0U, /**< External trigger from CCU80 Interrupt SR1 */ + XMC_DAC_CH_TRIGGER_EXTERNAL_CCU40_SR1 = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x2U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from CCU40 Interrupt SR1 */ + XMC_DAC_CH_TRIGGER_EXTERNAL_CCU41_SR1 = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x3U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from CCU41 Interrupt SR1 */ + XMC_DAC_CH_TRIGGER_EXTERNAL_P2_9 = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x4U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from pin 2.9 */ + XMC_DAC_CH_TRIGGER_EXTERNAL_P2_8 = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x5U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from pin 2.8 */ + XMC_DAC_CH_TRIGGER_EXTERNAL_U0C0_DX1INS = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x6U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from USIC-0 DX1 Input Signal */ + XMC_DAC_CH_TRIGGER_EXTERNAL_U1C0_DX1INS = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x7U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from USIC-1 DX1 Input Signal */ + XMC_DAC_CH_TRIGGER_SOFTWARE = + (0x2U << DAC_DAC0CFG1_TRIGMOD_Pos) /**< Software trigger */ +} XMC_DAC_CH_TRIGGER_t; + +/** + * Data type of the input data + */ +typedef enum XMC_DAC_CH_DATA_TYPE +{ + XMC_DAC_CH_DATA_TYPE_UNSIGNED = 0U , /**< input data is unsigned */ + XMC_DAC_CH_DATA_TYPE_SIGNED = 1U /**< input data is signed */ +} XMC_DAC_CH_DATA_TYPE_t; + +/** + * Scaling of the input data + */ +typedef enum XMC_DAC_CH_OUTPUT_SCALE +{ + XMC_DAC_CH_OUTPUT_SCALE_NONE = + 0x0U, /**< No scaling */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_2 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x1U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 2 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_4 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x2U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 4 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_8 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x3U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 8 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_16 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x4U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 16 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_32 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x5U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 32 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_64 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x6U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 64 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_128 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x7U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 128 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_2 = + 0x1U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 2 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_4 = + 0x2U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 4 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_8 = + 0x3U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 8 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_16 = + 0x4U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 16 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_32 = + 0x5U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 32 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_64 = + 0x6U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 64 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_128 = + 0x7U << DAC_DAC0CFG1_SCALE_Pos /**< divided by 128 */ +} XMC_DAC_CH_OUTPUT_SCALE_t; + +/** + * Negation of input data (applicable only for XMC44 device) + */ +typedef enum XMC_DAC_CH_OUTPUT_NEGATION +{ + XMC_DAC_CH_OUTPUT_NEGATION_DISABLED = 0U, /**< XMC_DAC_CH_OUTPUT_NEGATION_DISABLED */ + XMC_DAC_CH_OUTPUT_NEGATION_ENABLED = 1U /**< XMC_DAC_CH_OUTPUT_NEGATION_ENABLED */ +} XMC_DAC_CH_OUTPUT_NEGATION_t; + +/** + * Output sign signal for the Pattern Generation Mode + */ +typedef enum XMC_DAC_CH_PATTERN_SIGN_OUTPUT +{ + XMC_DAC_CH_PATTERN_SIGN_OUTPUT_DISABLED = 0U, /**< Sign output signal generation is disabled */ + XMC_DAC_CH_PATTERN_SIGN_OUTPUT_ENABLED = 1U /**< Sign output signal generation is enabled */ +} XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ +/** + * DAC peripheral registers configuration. + */ +typedef struct +{ + __I uint32_t ID; + + struct + { + __IO uint32_t low; + __IO uint32_t high; + } DACCFG[XMC_DAC_NO_CHANNELS]; + + __IO uint32_t DACDATA[XMC_DAC_NO_CHANNELS]; + __IO uint32_t DAC01DATA; + + struct + { + __IO uint32_t low; + __IO uint32_t high; + } DACPAT[XMC_DAC_NO_CHANNELS]; + +} XMC_DAC_t; + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Channel related configuration + */ +typedef struct XMC_DAC_CH_CONFIG +{ + union + { + struct + { + uint32_t :23; /**< Not used bits */ + uint32_t data_type:1; /**< input data type - unsigned / signed */ + uint32_t :4; /**< Not used bits */ + uint32_t output_negation:1; /**< Negation of the output waveform enabled/disabled */ + uint32_t :3; + }; + uint32_t cfg0; + }; + union + { + struct + { + uint32_t output_scale:4; /**< Scale value of type XMC_DAC_CH_OUTPUT_SCALE_t. It includes scaling + mul/div bit */ + uint32_t output_offset:8; /**< offset value */ + uint32_t :20; + }; + uint32_t cfg1; + }; +} XMC_DAC_CH_CONFIG_t; +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param dac Pointer to an instance of DAC module + * + * @return None + * + * \parDescription:
+ * Enables DAC clock and releases DAC reset.
+ * + * \par + * Enabling DAC is the first step of DAC initialisation. This API is called by XMC_DAC_CH_Init(). + * DAC clock is enabled by setting \a DAC bit of \a CGATCLR1 register. DAC reset is released by setting \a DACRS bit of \a PRCLR1 register. + * + * + * \parRelated APIs:
+ * XMC_DAC_IsEnabled(), XMC_DAC_Disable(), XMC_DAC_CH_Init()\n\n\n + * + */ +void XMC_DAC_Enable(XMC_DAC_t *const dac); + +/** + * @param dac Pointer to an instance of DAC module + * + * @return None + * + * \parDescription:
+ * Disables DAC clock and resets DAC. + * + * \par + * DAC clock is disabled by setting \a DAC bit of \a CGATSET1 register. DAC is reset by setting \a DACRS bit of \a PRSET1 register. + * + * \parRelated APIs:
+ * XMC_DAC_IsEnabled(), XMC_DAC_Enable()\n\n\n + * + */ +void XMC_DAC_Disable(XMC_DAC_t *const dac); + +/** + * @param dac Pointer to an instance of DAC module + * + * @return bool
+ * true - if DAC is enabled
+ * false - if DAC is disabled + * + * \parDescription:
+ * Returns the state of the DAC. + * + * \par + * DAC enabled status is determined by referring to \a DACRS bit of \a PRSTAT1 register. + * + * \parRelated APIs:
+ * XMC_DAC_Enable(), XMC_DAC_Disable()\n\n\n + * + */ +bool XMC_DAC_IsEnabled(const XMC_DAC_t *const dac); + +/** + * @param dac Pointer to an instance of DAC module + * + * @return None + * + * \parDescription:
+ * DAC switches to Simultaneous data mode from Independent data mode. + * + * \par + * Independent data mode is the default data mode. + * Simultaneous data mode is enabled by setting \a DATMOD bit of \a DAC0CFG1 register. + * + * \parNote:
+ * Set channel 0 and channel 1 to Data mode before calling this API. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartSingleValueMode(), XMC_DAC_CH_StartDataMode(), XMC_DAC_SimultaneousWrite(), XMC_DAC_DisableSimultaneousDataMode()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_EnableSimultaneousDataMode(XMC_DAC_t *const dac) +{ + XMC_ASSERT("XMC_DAC_EnableSimultaneousDataMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + + dac->DACCFG[0].high |= DAC_DAC0CFG1_DATMOD_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * + * @return None + * + * \parDescription:
+ * DAC switches to independent data mode from simultaneous Data mode. + * + * \par + * Independent data mode is the default data mode. + * Simultaneous data mode is disabled by clearing \a DATMOD bit of \a DAC0CFG1 register. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartDataMode(), XMC_DAC_EnableSimultaneousDataMode()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_DisableSimultaneousDataMode(XMC_DAC_t *const dac) +{ + XMC_ASSERT("XMC_DAC_DisableSimultaneousDataMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + + dac->DACCFG[0].high &= ~DAC_DAC0CFG1_DATMOD_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param data0 Data for DAC channel 0 [0-4095] + * @param data1 Data for DAC channel 1 [0-4095] + * + * @return None + * + * \parDescription:
+ * The data (\e data0 & \e data1) to be converted by channel 0 & channel 1 are updated to \a DATA1 bit-fields of \a DAC01DATA register. + * data0 and data1 have the range of [0-4095]. + * + * \parNote:
+ * Channel 0 and Channel 1 should be set to simultaneous data mode before calling this API. + * + * \parRelated APIs:
+ * XMC_DAC_EnableSimultaneousDataMode()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_SimultaneousWrite(XMC_DAC_t *const dac, const uint16_t data0, const uint16_t data1) +{ + XMC_ASSERT("XMC_DAC_SimultaneousWrite: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + + dac->DAC01DATA = (data0 << DAC_DAC01DATA_DATA0_Pos) | (data1 << DAC_DAC01DATA_DATA1_Pos); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param config Pointer to the DAC channel configuration structure + * + * @return None + * + * \parDescription:
+ * Initialises and configures the DAC \e channel with the configuration date pointed by \e config. + * + * \par + * DAC channel is initialised by configuring the registers \a DAC0CFG0 and \a DAC0CFG1 registers (for channel 0) / \a DAC1CFG0 and \a DAC1CFG1 registers (for channel 1). + * It enables the channel output by calling XMC_DAC_CH_EnableOutput(). + * + */ +void XMC_DAC_CH_Init(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_CONFIG_t *const config); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Channel \a channel output is enabled by setting the \a ANAEN bit of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \parNote:
+ * \a tSTARTUP time for DAC analog output starts after the \a ANAEN bit is set to one. + * After the expiry of the startup time the default value is driven to DAC output and a new value can be written. + * + * \parRelated APIs:
+ * XMC_DAC_CH_DisableOutput(), XMC_DAC_CH_IsOutputEnabled()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_EnableOutput(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_EnableOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_EnableOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].high |= DAC_DAC0CFG1_ANAEN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Channel \a channel output is disabled by clearing the \a ANAEN bit of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \par + * A call to this API stops driving the converted digital input to its output. + * + * \parRelated APIs:
+ * XMC_DAC_CH_EnableOutput(), XMC_DAC_CH_IsOutputEnabled()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_DisableOutput(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_DisableOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_DisableOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].high &= ~DAC_DAC0CFG1_ANAEN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return bool
+ * true - if analog output is enabled
+ * false - if analog output is disabled
+ * + * \parDescription:
+ * Returns the status of DAC analog output. + * + * \par + * Channel \a channel output enabled or disabled is determined by reading the \a ANAEN bit of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_EnableOutput(), XMC_DAC_CH_DisableOutput()\n\n\n + * + */ +__STATIC_INLINE bool XMC_DAC_CH_IsOutputEnabled(const XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_IsOutputEnabled: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_IsOutputEnabled: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return (bool)(dac->DACCFG[channel].high & DAC_DAC0CFG1_ANAEN_Msk); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param data Data to be written [0-4095] + * + * @return None + * + * \parDescription:
+ * Writes the \e data to the \e channel's DATA register. + * + * \par + * The \e data is then converted and driven to the output. + * If the trigger is set, On a trigger event the data in DATA register is converted and driven to \e channel output. + * Data \a data is written to the \a channel by loading \a data to \a DATA0 bit-field of \a DAC0DATA (for channel 0) / \a DATA1 bit-field of \a DAC1DATA register (for channel 1). + * data has the range of [0-4095]. + * + * \parNote:
+ * The API can be used for Single Value Mode, Data Mode (Individual) & Ramp Mode. + * Call XMC_DAC_CH_EnableOutput() API to enable analog output. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartSingleValueMode(), XMC_DAC_CH_StartDataMode(), XMC_DAC_CH_StartRampMode()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_Write(XMC_DAC_t *const dac, const uint8_t channel, const uint16_t data) +{ + XMC_ASSERT("XMC_DAC_CH_Write: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_Write: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACDATA[channel] = data; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Sets the \e channel to Single Value Mode by calling XMC_DAC_CH_SetMode(). + * + * \parNote:
+ * Call XMC_DAC_CH_Write() API to write the data. + * + * \parRelated APIs:
+ * XMC_DAC_CH_Write()\n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartSingleValueMode(XMC_DAC_t *const dac, const uint8_t channel); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param trigger Data points update trigger + * @param frequency Waveform frequency [Hz] + * + * @return XMC_DAC_CH_STATUS_t status + * + * \parDescription:
+ * Sets the \e channel to Data mode. Trigger and frequency are configured. + * + * \parNote:
+ * Call XMC_DAC_CH_Write() API to write the data. Call XMC_DAC_EnableSimultaneousDataMode() to switch to Simultaneous data mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_Init(), XMC_DAC_CH_Write(), XMC_DAC_EnableSimultaneousDataMode() \n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartDataMode(XMC_DAC_t *const dac, + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param start Start point of the ramp [0-4095] + * @param stop Stop point of the ramp [0-4095] + * @param trigger Data points update trigger + * @param frequency Ramp frequency in [Hz] + * + * @return XMC_DAC_CH_STATUS_t status + * + * \parDescription:
+ * Sets the \e channel to Ramp mode. Trigger, frequency, start and stop values are configured. + * On a \e trigger ramp values are converted and driven to \e channel output. + * Start and stop have the range of [0-4095]. Stop should be equal or greater than start. + * + * \parNote:
+ * If the ramp counter reaches its \e stop value, it restarts from the \e start value with the next trigger pulse. + * + * \parRelated APIs:
+ * XMC_DAC_CH_Init(), XMC_DAC_CH_GetRampStart(), XMC_DAC_CH_GetRampStop() \n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartRampMode(XMC_DAC_t *const dac, + const uint8_t channel, + const uint16_t start, + const uint16_t stop, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param pattern Data table of a pattern + * @param sign_output Sign information of the waveform + * @param trigger Data points update trigger + * @param frequency Waveform frequency in [Hz] + * + * @return XMC_DAC_CH_STATUS_t status + * + * \parDescription:
+ * Sets the \e channel to Pattern mode. Trigger, frequency, sign output and data are configured. + * On a \e trigger, the \e pattern values are converted and driven to \e channel output. + * + * \parRelated APIs:
+ * XMC_DAC_CH_Init(), XMC_DAC_CH_DisablePatternSignOutput() \n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartPatternMode(XMC_DAC_t *const dac, + const uint8_t channel, + const uint8_t *const pattern, + const XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t sign_output, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param trigger Data points update trigger + * @param frequency Waveform frequency in [Hz] + * + * @return XMC_DAC_CH_STATUS_t status + * + * \parDescription:
+ * Sets the \e channel to Noise mode. Trigger and frequency are configured. + * On a \e trigger the DAC starts converting and drives to \e channel output. + * + * \parRelated APIs:
+ * XMC_DAC_CH_Init()\n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartNoiseMode(XMC_DAC_t *const dac, + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param pattern Pointer to the data table + * + * @return None + * + * \parDescription:
+ * The data for the Pattern mode is written to the \a DAC0PATL and \a DAC0PATH registers. + * The API is called by XMC_DAC_CH_StartPatternMode(). + * + * \parNote:
+ * Call this API if the \a channel is set to Pattern mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_EnablePatternSignOutput(), XMC_DAC_CH_DisablePatternSignOutput()\n\n\n + * + */ +void XMC_DAC_CH_SetPattern(XMC_DAC_t *const dac, const uint8_t channel, const uint8_t *const pattern); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Enables the output sign information for Pattern Mode. + * + * \par + * Sign output is enabled by setting \a SIGNEN bit of \a DAC0CFG0 register (for channel 0) / DAC1CFG0 register (for channel 1). + * + * \parNote:
+ * Call this API if the \e channel is set to Pattern mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartPatternMode(), XMC_DAC_CH_DisablePatternSignOutput()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_EnablePatternSignOutput(XMC_DAC_t *const dac, + const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_EnablePatternSignOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_EnablePatternSignOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low |= DAC_DAC0CFG0_SIGNEN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Disables output sign information for Pattern Mode. + * + * \par + * Sign output is disabled by clearing \a SIGNEN bit of \a DAC0CFG0 register (for channel 0) / DAC1CFG0 register (for channel 1). + * + * \parNote:
+ * Call this API if the \e channel is set to Pattern mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartPatternMode(), XMC_DAC_CH_EnablePatternSignOutput()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_DisablePatternSignOutput(XMC_DAC_t *const dac, + const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_DisablePatternSignOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_DisablePatternSignOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low &= ~DAC_DAC0CFG0_SIGNEN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param start Ramp start point [0-4095] + * + * @return None + * + * \parDescription:
+ * Sets the ramp start value by writing to the register \a DAC0DATA (for \e channel 0) or \a DAC1DATA (for \e channel 1). + * If the ramp counter reaches its stop value, it restarts from the \a start value with the next trigger pulse. + * Ensure \e start value is lower than the stop value. + * + * \parNote:
+ * Call this API if the \a channel is set to Ramp mode. + * Start value is a 12 bit data. + * + * \parRelated APIs:
+ * XMC_DAC_CH_GetRampStart(), XMC_DAC_CH_GetRampStop(), XMC_DAC_CH_SetRampStop()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetRampStart(XMC_DAC_t *const dac, const uint8_t channel, const uint16_t start) +{ + XMC_ASSERT("XMC_DAC_CH_SetRampStart: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetRampStart: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACDATA[channel] = start; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return uint16_t + * + * \parDescription:
+ * Gets the ramp start value by reading \a DATA0 bit-field of \a DAC0DATA register (for channel 0) / \a DATA1 bit-field of \a DAC1DATA register (for channel 1). + * If the ramp counter reaches its stop value, it restarts from the start value with the next trigger pulse. + * + * \parNote:
+ * Call this API if the \e channel is set to Ramp mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetRampStart(), XMC_DAC_CH_StartRampMode(), XMC_DAC_CH_GetRampStop(), XMC_DAC_CH_SetRampStop()\n\n\n + * + */ +__STATIC_INLINE uint16_t XMC_DAC_CH_GetRampStart(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_GetRampStart: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_GetRampStart: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return (uint16_t)(dac->DACDATA[channel]); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param stop Ramp stop point [0-4095] + * + * @return None + * + * \parDescription:
+ * Sets the ramp stop value by writing to the bit-field \a DATA0 (for \e channel 0) or \a DATA1 (for \e channel 1) of \a DAC01DATA register. + * If the ramp counter reaches its \a stop value, it restarts from the start value with the next trigger pulse. + * Ensure \e stop value is higher than the start value. + * + * \parNote:
+ * Call this API if the \e channel is set to Ramp mode. + * Stop value is a 12 bit data. + * + * \parRelated APIs:
+ * XMC_DAC_CH_GetRampStop(), XMC_DAC_CH_SetRampStart()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetRampStop(XMC_DAC_t *const dac, const uint8_t channel, const uint16_t stop) +{ + XMC_ASSERT("XMC_DAC_CH_SetRampStop: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetRampStop: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DAC01DATA = (dac->DAC01DATA & ~(DAC_DAC01DATA_DATA0_Msk << (channel * DAC_DAC01DATA_DATA1_Pos))) | + (stop << (channel * DAC_DAC01DATA_DATA1_Pos)); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return uint16_t + * + * \parDescription:
+ * Gets the ramp stop value by reading \a DATA0 bit-field of \a DAC01DATA register (for channel 0) / \a DATA1 bit-field of \a DAC01DATA register (for channel 1). + * If the ramp counter reaches its stop value, it restarts from the start value with the next trigger pulse. + * + * \parNote:
+ * Call this API if the \e channel is set to Ramp mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetRampStop(), XMC_DAC_CH_StartRampMode(), XMC_DAC_CH_GetRampStart()\n\n\n + * + */ +__STATIC_INLINE uint16_t XMC_DAC_CH_GetRampStop(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_GetRampStop: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_GetRampStop: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return((dac->DAC01DATA >> (channel * DAC_DAC01DATA_DATA1_Pos)) & DAC_DAC01DATA_DATA0_Msk); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param trigger Trigger source + * + * @return None + * + * \parDescription:
+ * Selects the \e trigger source for the \e channel by configuring the bits TRIGSEL & TRIGMOD of CFG register. + * + * \par + * Channel \a channel trigger source is selected by \a TRIGSEL bit-field of \a DAC0CFG1 register (for channel 0) / DAC1CFG1 register(for channel 1). + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetTrigger(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_TRIGGER_t trigger) +{ + XMC_ASSERT("XMC_DAC_CH_SetTrigger: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetTrigger: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_SetTrigger: trigger parameter not valid\n", XMC_DAC_IS_TRIGGER_VALID(trigger)); + + dac->DACCFG[channel].high = (dac->DACCFG[channel].high & ~(DAC_DAC0CFG1_TRIGSEL_Msk | DAC_DAC0CFG1_TRIGMOD_Msk)) | + trigger; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param frequency Waveform frequency in [Hz] + * + * @return XMC_DAC_CH_STATUS_t + * + * \parDescription:
+ * Sets the \e frequency of DAC channel. + * + * \par + * The value \e frequency acts as clock divider. The smallest \e frequency divider value is 16. + * A valid \e frequency value should be within the range XMC_DAC_MIN_FREQ_DIVIDER to XMC_DAC_MAX_FREQ_DIVIDER. A value outside this range is considered as in valid and API returns error. + * Frequency \a frequency is configured by setting \a FREQ bit-field of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parNote:
+ * Call this API only for Single value mode, Data mode and Noise mode. + * Call XMC_DAC_CH_SetRampFrequency() in case of Ramp mode and XMC_DAC_CH_SetPatternFrequency() in case of Pattern mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetRampFrequency(), XMC_DAC_CH_SetPatternFrequency()\n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetFrequency(XMC_DAC_t *const dac, const uint8_t channel, const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param frequency [Hz] + * + * @return XMC_DAC_CH_STATUS_t + * + * \parDescription:
+ * Sets the \e frequency of DAC channel by calling XMC_DAC_CH_SetFrequency(). + * + * \par + * For the Ramp mode, the \a frequency of operation depends on the total number of sample points (\a stop - \a start). + * Frequency \e frequency is multiplied by the total number of sample points, so that each trigger instance converts all the sample points of ramp. + * + * \parNote:
+ * Call this API only if the \a channel is set to Ramp mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartRampMode()\n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetRampFrequency(XMC_DAC_t *const dac, const uint8_t channel, const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param frequency in [Hz] + * + * @return XMC_DAC_CH_STATUS_t + * + * \parDescription:
+ * Sets the \e frequency of DAC channel by calling XMC_DAC_CH_SetFrequency(). + * + * \par + * For the Pattern mode, the \a frequency of operation depends on the total number of sample points \a XMC_DAC_SAMPLES_PER_PERIOD. + * Frequency \e frequency is multiplied by the total number of sample points, so that each trigger instance converts all the sample points of the pattern. + * + * \parNote:
+ * Call this API only if the \a channel is set to Pattern mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartPatternMode()\n\n\n + * + */ +__STATIC_INLINE XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetPatternFrequency(XMC_DAC_t *const dac, + const uint8_t channel, + const uint32_t frequency) +{ + XMC_ASSERT("XMC_DAC_CH_SetPatternFrequency: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetPatternFrequency: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return XMC_DAC_CH_SetFrequency(dac, channel, frequency * XMC_DAC_SAMPLES_PER_PERIOD); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param mode DAC operation mode + * + * @return None + * + * \parDescription:
+ * Sets the operating \e mode for the \e channel by setting the \a MODE bit-field of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * Different modes of DAC operation are defined by enum XMC_DAC_CH_MODE_t. + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetMode(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_MODE_t mode) +{ + XMC_ASSERT("XMC_DAC_CH_SetMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_SetMode: trigger parameter not valid\n", XMC_DAC_IS_MODE_VALID(mode)); + + dac->DACCFG[channel].low = (dac->DACCFG[channel].low & ~DAC_DAC0CFG0_MODE_Msk) | + mode; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Sets the \e channel's data to signed type by setting \a SIGN bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * The data for the conversion would then be treated as signed data type. + * + * \parNote:
+ * Offset and scaling can be applied to the data by calling XMC_DAC_CH_SetOutputOffset(), XMC_DAC_CH_SetOutputScale(). + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetUnsignedDataType()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetSignedDataType(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_SetSignedDataType: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetSignedDataType: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low |= (DAC_DAC0CFG0_SIGN_Msk); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Sets the \e channel's data to unsigned type by clearing \a SIGN bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * The data for the conversion would then be treated as unsigned data type. + * + * \parNote:
+ * Offset and scaling can be applied to the data by calling XMC_DAC_CH_SetOutputOffset(), XMC_DAC_CH_SetOutputScale(). + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetSignedDataType()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetUnsignedDataType(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_SetUnsignedDataType: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetUnsignedDataType: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low &= ~(DAC_DAC0CFG0_SIGN_Msk); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * A call to this API generates a trigger pulse by setting \a SWTRIG bit of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1), + * provided the \a TRIGMOD bit of CFG register is set to \a XMC_DAC_CH_TRIGGER_SOFTWARE. + * + * \parNote:
+ * If the \e channel is set to simultaneous data mode, SWTRIG bit of \e channel 1 is not valid. + * Only \a SWTRIG bit of channel 0 is used for channel 1. + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetTrigger(), XMC_DAC_CH_EnableEvent()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SoftwareTrigger(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_SoftwareTrigger: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SoftwareTrigger: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].high |= DAC_DAC0CFG1_SWTRIG_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Enables service request by setting \a SREN bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * Trigger signal is generated upon conversion of each data. + * + * \parNote:
+ * The service request signal can be connected to NVIC, DMA.\n + * + * \parRelated APIs:
+ * XMC_DAC_CH_DisableEvent()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_EnableEvent(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_EnableEvent: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_EnableEvent: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low |= DAC_DAC0CFG0_SREN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Disables service request by clearing \a SREN bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_EnableEvent()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_DisableEvent(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_DisableEvent: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_DisableEvent: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low &= ~DAC_DAC0CFG0_SREN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param offset + * + * @return None + * + * \parDescription:
+ * Sets the offset value.\n + * Offset range:0 - 255\n + * interpreted as : -128 to 127 (twos complement) in signed mode and 0 to 255 in unsigned mode. + * + * \parNote:
+ * Scaling can be applied to the output data after adding the \e offset value. + * + * \par + * Channel \a channel \a offset value is loaded to the bit-field \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetOutputScale()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetOutputOffset(XMC_DAC_t *const dac, const uint8_t channel, const uint8_t offset) +{ + XMC_ASSERT("XMC_DAC_CH_SetOutputOffset: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetOutputOffset: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].high = (dac->DACCFG[channel].high & ~DAC_DAC0CFG1_OFFS_Msk) | + offset << DAC_DAC0CFG1_OFFS_Pos; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param scale Input data scaling + * + * @return None + * + * \parDescription:
+ * Data of the \e channel is scaled. + * + * \par + * The data can either be scaled up-scaled (multiplied), down-scaled (divided) or no scaling (as is) based on the value of \e scale. + * Scaling is configured by setting bit-fields \a MULDIV and \a SCALE of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_GetOutputScale()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetOutputScale(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_OUTPUT_SCALE_t scale) +{ + XMC_ASSERT("XMC_DAC_CH_SetOutputScale: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetOutputScale: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_SetOutputScale: scale parameter not valid\n", XMC_DAC_IS_OUTPUT_SCALE_VALID(scale)); + + dac->DACCFG[channel].high = (dac->DACCFG[channel].high & ~(DAC_DAC0CFG1_MULDIV_Msk | DAC_DAC0CFG1_SCALE_Msk)) | + scale; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return XMC_DAC_CH_OUTPUT_SCALE_t + * + * \parDescription:
+ * Returns scaling information for the data. + * The input data could be either up-scaled (multiplied), down-scaled (divided) or without scaling (as is).\n + * Scaling factor is determined by reading bit-fields \a MULDIV and \a SCALE of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetOutputScale()\n\n\n + * + */ +__STATIC_INLINE XMC_DAC_CH_OUTPUT_SCALE_t XMC_DAC_CH_GetOutputScale(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_GetOutputScale: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_GetOutputScale: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return (XMC_DAC_CH_OUTPUT_SCALE_t)(dac->DACCFG[channel].high & (DAC_DAC0CFG1_MULDIV_Msk | DAC_DAC0CFG1_SCALE_Msk)); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * \parDescription:
+ * Enables output negation. + * + * \par + * By negating the DAC value is converted to its two's complement values. + * Can be used in Ramp mode to generate negative ramp. + * Negation in enabled by setting \a NEGATE bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parNote:
+ * Negation feature is not applicable for XMC45 devices. Calling this API in XMC45 devices doesn't have any effect. + * + * \parRelated APIs:
+ * XMC_DAC_CH_DisableOutputNegation(), XMC_DAC_CH_StartRampMode()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_EnableOutputNegation(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_EnableOutputNegation: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_EnableOutputNegation: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low |= XMC_DAC_DACCFG_NEGATE_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * \parDescription:
+ * Disables output negation. + * + * \par + * Negation is disabled by clearing \a NEGATE bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parNote:
+ * Negation feature is not applicable for XMC45 devices. Calling this API in XMC45 devices doesn't have any effect. + * + * \parRelated APIs:
+ * XMC_DAC_CH_EnableOutputNegation()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_DisableOutputNegation(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_DisableOutputNegation: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_DisableOutputNegation: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low &= ~XMC_DAC_DACCFG_NEGATE_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return bool\n + * true - if FIFO is full\n + * false - if FIFO is not full + * + * \parDescription:
+ * Returns FIFO status.\n + * + * \par + * FIFIO full status is determined by reading \a FIFOFUL bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_IsFifoEmpty()\n\n\n + * + */ +__STATIC_INLINE bool XMC_DAC_CH_IsFifoFull(const XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_IsFifoFull: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_IsFifoFull: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return (bool)(dac->DACCFG[channel].low & DAC_DAC0CFG0_FIFOFUL_Msk); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return bool\n + * true - if FIFO is empty\n + * false - if FIFO is not empty + * + * \parDescription:
+ * Returns FIFO status. + * + * \par + * FIFIO empty status is determined by reading \a FIFOEMP bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_IsFifoFull()\n\n\n + * + */ +__STATIC_INLINE bool XMC_DAC_CH_IsFifoEmpty(const XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_IsFifoEmpty: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_IsFifoEmpty: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return (bool)(dac->DACCFG[channel].low & DAC_DAC0CFG0_FIFOEMP_Msk); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(DAC) */ + +#endif /* XMC_DAC_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_device.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_device.h new file mode 100644 index 00000000..fe346210 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_device.h @@ -0,0 +1,1514 @@ +/** + * @file xmc_device.h + * @date 2016-07-21 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial version + * + * 2015-09-23: + * - Added XMC14 and XMC48/47 + * + * 2015-11-19: + * - Added XMC43 + * + * 2016-02-26: + * - Fixed CCU8 version for XMC43/47/48 + * + * 2016-06-14: + * - Added XMC1201_T028x0016, XMC1202_T016x0064, XMC1301_T016x0032, XMC1302_Q040x0200, + * XMC1302_T028x0016, XMC1402_T038x0032, XMC1402_T038x0064, XMC1402_T038x0128, + * XMC1403_Q040x0064, XMC1403_Q040x0128, XMC1403_Q040x0200, XMC1402_T038x0200 + * XMC1402_Q040x0200, XMC1402_Q048x0200, XMC1201_T028x0032 + * @endcond + * + */ + +#ifndef XMC_DEVICE_H +#define XMC_DEVICE_H + +/* Family definitions */ +#define XMC4 (4) +#define XMC1 (1) + +/* Series definitions */ +#define XMC48 (48) +#define XMC47 (47) +#define XMC45 (45) +#define XMC44 (44) +#define XMC43 (43) +#define XMC42 (42) +#define XMC41 (41) +#define XMC14 (14) +#define XMC13 (13) +#define XMC12 (12) +#define XMC11 (11) + +/* Device definitions */ +#define XMC4800 (4800) +#define XMC4700 (4700) +#define XMC4500 (4500) +#define XMC4502 (4502) +#define XMC4504 (4504) +#define XMC4400 (4400) +#define XMC4402 (4402) +#define XMC4300 (4300) +#define XMC4200 (4200) +#define XMC4100 (4100) +#define XMC4104 (4104) +#define XMC4108 (4108) +#define XMC1401 (1401) +#define XMC1402 (1402) +#define XMC1403 (1403) +#define XMC1404 (1404) +#define XMC1300 (1300) +#define XMC1301 (1301) +#define XMC1302 (1302) +#define XMC1200 (1200) +#define XMC1201 (1201) +#define XMC1202 (1202) +#define XMC1203 (1203) +#define XMC1100 (1100) + +/* Package definitions */ +#define BGA144 (1) +#define LQFP144 (2) +#define LQFP100 (3) +#define BGA64 (4) +#define LQFP64 (5) +#define VQFN48 (6) +#define TSSOP38 (7) +#define TSSOP28 (8) +#define TSSOP16 (9) +#define VQFN24 (10) +#define VQFN40 (11) +#define VQFN64 (12) +#define BGA196 (13) + +#if defined(XMC4800_E196x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE BGA196 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F144x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F100x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_E196x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE BGA196 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F144x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F100x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_E196x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE BGA196 +#define UC_FLASH (1024UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F144x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (1024UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F100x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (1024UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_E196x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE BGA196 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_F144x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_F100x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_E196x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE BGA196 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_F144x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_F100x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4500_E144x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4500 +#define UC_PACKAGE BGA144 +#define UC_FLASH (1024UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4500_F144x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4500 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (1024UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4500_F100x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4500 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (1024UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4500_F144x768) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4500 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (768UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4500_F100x768) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4500 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (768UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4502_F100x768) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4502 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (768UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4504_F100x512) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4504 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (512UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4504_F144x512) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4504 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (512UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4400_F100x512) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4400 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (512UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4400_F64x512) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4400 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (512UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4400_F100x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4400 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4400_F64x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4400 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4402_F100x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4402 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4402_F64x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4402 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4300_F100x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC43 +#define UC_DEVICE XMC4300 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (256UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4200_E64x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC42 +#define UC_DEVICE XMC4200 +#define UC_PACKAGE BGA64 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4200_F64x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC42 +#define UC_DEVICE XMC4200 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4200_Q48x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC42 +#define UC_DEVICE XMC4200 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4100_E64x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4100 +#define UC_PACKAGE BGA64 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4100_F64x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4100 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4100_Q48x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4100 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_E64x64) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE BGA64 +#define UC_FLASH (64UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_F64x64) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (64UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_Q48x64) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_E64x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE BGA64 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_F64x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_Q48x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4108_Q48x64) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4108 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4108_F64x64) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4108 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (64UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC1100_Q024x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (8UL) +#define CCU4V2 + +#elif defined(XMC1100_Q024x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1100_Q024x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1100_Q024x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1100_Q040x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1100_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1100_Q040x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1100_T016x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (8UL) +#define CCU4V2 + +#elif defined(XMC1100_T016x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1100_T016x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1100_T016x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1100_T038x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1100_T038x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1100_T038x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1201_Q040x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1201_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1201_Q040x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1201_Q040x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (128UL) +#define CCU4V2 + +#elif defined(XMC1201_Q040x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (200UL) +#define CCU4V2 + +#elif defined(XMC1201_T038x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1201_T038x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1201_T038x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1201_T038x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (128UL) +#define CCU4V2 + +#elif defined(XMC1201_T038x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (200UL) +#define CCU4V2 + +#elif defined(XMC1201_T028x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1201_T028x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1202_Q024x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1202_Q024x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1202_Q040x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1202_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1202_T016x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1202_T016x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1202_T016x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1202_T028x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1202_T028x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1202_T028x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1200_T038x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1200 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (200UL) +#define CCU4V2 + +#elif defined(XMC1301_Q024x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (8UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_Q024x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_Q040x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (8UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_Q040x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T016x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (8UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T016x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T016x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T038x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (8UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T038x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T038x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T038x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (64UL) + +#elif defined(XMC1302_Q024x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q024x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q024x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (64UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q040x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q040x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (64UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q040x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (128UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q040x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (200UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T038x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T038x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T038x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (64UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T038x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (128UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T038x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (200UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T028x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T016x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (8UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T016x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T016x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1401_Q048x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1401 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define CCU4V3 + +#elif defined(XMC1401_Q048x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1401 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define CCU4V3 + +#elif defined(XMC1401_F064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1401 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (64UL) +#define CCU4V3 + +#elif defined(XMC1401_F064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1401 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (128UL) +#define CCU4V3 + +#elif defined(XMC1402_T038x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (32UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_T038x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (64UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_T038x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (128UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_T038x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (200UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q040x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (64UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q040x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (128UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q040x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (200UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q048x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (32UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q048x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q048x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q048x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (200UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (64UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (128UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q064x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (200UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_F064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (64UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_F064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (128UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_F064x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (200UL) +#define CCU4V3 +#define CCU8V3 + + +#elif defined(XMC1403_Q048x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q048x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q048x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q040x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q040x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q040x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q064x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1404_Q048x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q048x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q048x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q064x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_F064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_F064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_F064x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#else +#error "xmc_device.h: device not supported" +#endif + +#if UC_SERIES == XMC45 +#include "XMC4500.h" +#define PERIPHERAL_RESET_SUPPORTED +#define USB_OTG_SUPPORTED + +#elif UC_SERIES == XMC44 +#include "XMC4400.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED +#define USB_OTG_SUPPORTED + +#elif UC_SERIES == XMC43 +#include "XMC4300.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED +#define USB_OTG_SUPPORTED + +#elif UC_SERIES == XMC42 +#include "XMC4200.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED + +#elif UC_SERIES == XMC41 +#include "XMC4100.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED + +#elif UC_SERIES == XMC47 +#include "XMC4700.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED +#define USB_OTG_SUPPORTED + +#elif UC_SERIES == XMC48 +#include "XMC4800.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED +#define USB_OTG_SUPPORTED + +#elif UC_SERIES == XMC11 +#include "XMC1100.h" +#define CLOCK_GATING_SUPPORTED + +#elif UC_SERIES == XMC12 +#include "XMC1200.h" +#define CLOCK_GATING_SUPPORTED + +#elif UC_SERIES == XMC13 +#include "XMC1300.h" +#define CLOCK_GATING_SUPPORTED + +#elif UC_SERIES == XMC14 +#include "XMC1400.h" +#define CLOCK_GATING_SUPPORTED +#endif + +#endif /* XMC_DEVICE_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dma.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dma.h new file mode 100644 index 00000000..786cd555 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dma.h @@ -0,0 +1,1269 @@ + +/** + * @file xmc_dma.h + * @date 2016-10-28 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Add the declarations for the following APIs:
+ * XMC_DMA_DisableRequestLine, XMC_DMA_ClearRequestLine,
+ * XMC_DMA_CH_ClearSourcePeripheralRequest,
+ * XMC_DMA_CH_ClearDestinationPeripheralRequest
+ * - Documentation updates
+ * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2016-10-28: + * - Fix documentation on maximum block size + * + * @endcond + */ + +#ifndef XMC_DMA_H +#define XMC_DMA_H + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_common.h" + +#if defined (GPDMA0) + +#include "xmc_dma_map.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup DMA + * @brief General purpose DMA (GPDMA) driver for the XMC4000 microcontroller family + * + * The GPDMA is a highly configurable DMA controller that allows high-speed data transfers + * between peripherals and memories. Complex data transfers can be done with minimal + * intervention of the processor, making CPU available for other operations. + * + * GPDMA provides extensive support for XMC microcontroller peripherals like A/D, D/A + * converters and timers. Data transfers through communication interfaces (USIC) using the + * GPDMA increase efficiency and parallelism for real-time applications. + * + * The DMA low level driver provides functions to configure and initialize the GPDMA + * hardware peripheral. + * @{ + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#if defined (GPDMA0) +#define XMC_DMA0 ((XMC_DMA_t *)GPDMA0_CH0_BASE) /**< DMA module 0 */ +#define XMC_DMA0_NUM_CHANNELS 8 +#endif + +#if defined (GPDMA1) +#define XMC_DMA1 ((XMC_DMA_t *)GPDMA1_CH0_BASE) /**< DMA module 1, only available in XMC45xx series */ +#define XMC_DMA1_NUM_CHANNELS 4 +#endif + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * DMA transfer types + */ +typedef enum XMC_DMA_CH_TRANSFER_TYPE +{ + XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK, /**< Single block */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_RELOAD, /**< Multi-block: src address contiguous, dst address reload */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_CONTIGUOUS, /**< Multi-block: src address reload, dst address contiguous */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD, /**< Multi-block: src address reload, dst address reload */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_LINKED, /**< Multi-block: src address contiguous, dst address linked */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED, /**< Multi-block: src address reload, dst address linked */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_CONTIGUOUS, /**< Multi-block: src address linked, dst address contiguous */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_RELOAD, /**< Multi-block: src address linked, dst address reload */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED /**< Multi-block: src address linked, dst address linked */ +} XMC_DMA_CH_TRANSFER_TYPE_t; + +/** + * DMA transfer flow modes + */ +typedef enum XMC_DMA_CH_TRANSFER_FLOW +{ + XMC_DMA_CH_TRANSFER_FLOW_M2M_DMA = 0x0UL, /**< Memory to memory (DMA flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA = 0x1UL, /**< Memory to peripheral (DMA flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA = 0x2UL, /**< Peripheral to memory (DMA flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA = 0x3UL, /**< Peripheral to peripheral (DMA flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_P2M_PER = 0x4UL, /**< Peripheral to memory (Peripheral flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_P2P_SRCPER = 0x5UL, /**< Peripheral to peripheral (Source peripheral flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_M2P_PER = 0x6UL, /**< Memory to peripheral (Peripheral flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_P2P_DSTPER = 0x7UL /**< Peripheral to peripheral (Destination peripheral flow controller) */ +} XMC_DMA_CH_TRANSFER_FLOW_t; + +/** + * Valid burst length values + */ +typedef enum XMC_DMA_CH_BURST_LENGTH +{ + XMC_DMA_CH_BURST_LENGTH_1 = 0x0UL, /**< Burst length: 1 word */ + XMC_DMA_CH_BURST_LENGTH_4 = 0x1UL, /**< Burst length: 4 words */ + XMC_DMA_CH_BURST_LENGTH_8 = 0x2UL /**< Burst length: 8 words */ +} XMC_DMA_CH_BURST_LENGTH_t; + +/** + * Valid transfer width values + */ +typedef enum XMC_DMA_CH_TRANSFER_WIDTH +{ + XMC_DMA_CH_TRANSFER_WIDTH_8 = 0x0UL, /**< 8-bit transfer width */ + XMC_DMA_CH_TRANSFER_WIDTH_16 = 0x1UL, /**< 16-bit transfer width */ + XMC_DMA_CH_TRANSFER_WIDTH_32 = 0x2UL /**< 32-bit transfer width */ +} XMC_DMA_CH_TRANSFER_WIDTH_t; + +/** + * DMA address count mode + */ +typedef enum XMC_DMA_CH_ADDRESS_COUNT_MODE +{ + XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT = 0x0UL, /**< Address count mode: increment */ + XMC_DMA_CH_ADDRESS_COUNT_MODE_DECREMENT = 0x1UL, /**< Address count mode: decrement */ + XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE = 0x2UL /**< Address count mode: no change */ +} XMC_DMA_CH_ADDRESS_COUNT_MODE_t; + +/** + * DMA channel priorities + */ +typedef enum XMC_DMA_CH_PRIORITY +{ + XMC_DMA_CH_PRIORITY_0 = 0x0UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 0 (low) */ + XMC_DMA_CH_PRIORITY_1 = 0x1UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 1 */ + XMC_DMA_CH_PRIORITY_2 = 0x2UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 2 */ + XMC_DMA_CH_PRIORITY_3 = 0x3UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 3 */ + XMC_DMA_CH_PRIORITY_4 = 0x4UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 4 */ + XMC_DMA_CH_PRIORITY_5 = 0x5UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 5 */ + XMC_DMA_CH_PRIORITY_6 = 0x6UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 6 */ + XMC_DMA_CH_PRIORITY_7 = 0x7UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos /**< DMA channel priority 7 (high) */ +} XMC_DMA_CH_PRIORITY_t; + +/** + * Source handshake interface + */ +typedef enum XMC_DMA_CH_SRC_HANDSHAKING +{ + XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE = 0x0UL << GPDMA0_CH_CFGL_HS_SEL_SRC_Pos, /**< Source: hardware handshake */ + XMC_DMA_CH_SRC_HANDSHAKING_SOFTWARE = 0x1UL << GPDMA0_CH_CFGL_HS_SEL_SRC_Pos /**< Source: software handshake */ +} XMC_DMA_CH_SRC_HANDSHAKING_t; + +/** + * Destination handshake interface + */ +typedef enum XMC_DMA_CH_DST_HANDSHAKING +{ + XMC_DMA_CH_DST_HANDSHAKING_HARDWARE = 0x0UL << GPDMA0_CH_CFGL_HS_SEL_DST_Pos, /**< Destination: hardware handshake */ + XMC_DMA_CH_DST_HANDSHAKING_SOFTWARE = 0x1UL << GPDMA0_CH_CFGL_HS_SEL_DST_Pos /**< Destination: software handshake */ +} XMC_DMA_CH_DST_HANDSHAKING_t; + +/** + * DMA hardware handshaking interface + * Hardware handshaking available only if DMA is flow controller + */ +typedef enum XMC_DMA_CH_HARDWARE_HANDSHAKING_IF +{ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_0 = 0x0UL, /**< Hardware handshaking interface 0 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_1 = 0x1UL, /**< Hardware handshaking interface 1 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_2 = 0x2UL, /**< Hardware handshaking interface 2 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_3 = 0x3UL, /**< Hardware handshaking interface 3 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_4 = 0x4UL, /**< Hardware handshaking interface 4 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_5 = 0x5UL, /**< Hardware handshaking interface 5 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_6 = 0x6UL, /**< Hardware handshaking interface 6 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_7 = 0x7UL /**< Hardware handshaking interface 7 */ +} XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_t; + +/** + * DMA events + */ +typedef enum XMC_DMA_CH_EVENT +{ + XMC_DMA_CH_EVENT_TRANSFER_COMPLETE = 0x1UL, /**< Transfer complete event */ + XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE = 0x2UL, /**< Block transfer complete event */ + XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE = 0x4UL, /**< Source transaction complete event */ + XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE = 0x8UL, /**< Destination transaction complete event */ + XMC_DMA_CH_EVENT_ERROR = 0x10UL /**< DMA error event */ +} XMC_DMA_CH_EVENT_t; + +/** + * Transaction types + */ +typedef enum XMC_DMA_CH_TRANSACTION_TYPE +{ + XMC_DMA_CH_TRANSACTION_TYPE_SINGLE, /**< Single DMA transaction */ + XMC_DMA_CH_TRANSACTION_TYPE_BURST /**< Burst transaction */ +} XMC_DMA_CH_TRANSACTION_TYPE_t; + +/** + * DMA channel status values + */ +typedef enum XMC_DMA_CH_STATUS +{ + XMC_DMA_CH_STATUS_OK, /**< DMA status OK */ + XMC_DMA_CH_STATUS_ERROR, /**< DMA status error */ + XMC_DMA_CH_STATUS_BUSY /**< DMA is busy */ +} XMC_DMA_CH_STATUS_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ + +/** + * DMA channel configuration structure
+ * + * The structure represents a collection of all hardware registers used + * to configure the DMA channel. It is contained within the ::XMC_DMA_t + * structure. It's registers can be used to configure DMA transfer details + * like source address, destination address, block size, incrementation + * modes and the like. + */ + +typedef struct { + __IO uint32_t SAR; + __I uint32_t RESERVED0; + __IO uint32_t DAR; + __I uint32_t RESERVED1; + __IO uint32_t LLP; + __I uint32_t RESERVED2; + __IO uint32_t CTLL; + __IO uint32_t CTLH; + __IO uint32_t SSTAT; + __I uint32_t RESERVED3; + __IO uint32_t DSTAT; + __I uint32_t RESERVED4; + __IO uint32_t SSTATAR; + __I uint32_t RESERVED5; + __IO uint32_t DSTATAR; + __I uint32_t RESERVED6; + __IO uint32_t CFGL; + __IO uint32_t CFGH; + __IO uint32_t SGR; + __I uint32_t RESERVED7; + __IO uint32_t DSR; + __I uint32_t RESERVED8; +} GPDMA_CH_t; + +/** + * DMA device structure
+ * + * The structure represents a collection of all hardware registers used + * to configure the GPDMA peripheral on the XMC4000 series of microcontrollers. + * The registers can be accessed with ::XMC_DMA0 and ::XMC_DMA1. + */ +typedef struct { + GPDMA_CH_t CH[8]; + + __IO uint32_t RAWCHEV[10]; + __I uint32_t STATUSCHEV[10]; + __IO uint32_t MASKCHEV[10]; + __O uint32_t CLEARCHEV[10]; + __I uint32_t STATUSGLEV; + __I uint32_t RESERVED20; + __IO uint32_t REQSRCREG; + __I uint32_t RESERVED21; + __IO uint32_t REQDSTREG; + __I uint32_t RESERVED22; + __IO uint32_t SGLREQSRCREG; + __I uint32_t RESERVED23; + __IO uint32_t SGLREQDSTREG; + __I uint32_t RESERVED24; + __IO uint32_t LSTSRCREG; + __I uint32_t RESERVED25; + __IO uint32_t LSTDSTREG; + __I uint32_t RESERVED26; + __IO uint32_t DMACFGREG; + __I uint32_t RESERVED27; + __IO uint32_t CHENREG; + __I uint32_t RESERVED28; + __I uint32_t ID; + __I uint32_t RESERVED29[19]; + __I uint32_t TYPE; + __I uint32_t VERSION; +} XMC_DMA_t; + +/* Anonymous structure/union guard start */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__TASKING__) + #pragma warning 586 +#endif + +/** + * DMA channel linked list item. + * Note: Needs to be word aligned + */ +typedef struct XMC_DMA_LLI +{ + uint32_t src_addr; /**< Source address */ + uint32_t dst_addr; /**< Destination address */ + struct XMC_DMA_LLI *llp; /**< Linked list pointer of type XMC_DMA_LLI_t */ + union + { + struct + { + uint32_t enable_interrupt: 1; /**< Enable interrupts? */ + uint32_t dst_transfer_width: 3; /**< Destination transfer width */ + uint32_t src_transfer_width: 3; /**< Source transfer width */ + uint32_t dst_address_count_mode: 2; /**< Destination address count mode */ + uint32_t src_address_count_mode: 2; /**< Source address count mode */ + uint32_t dst_burst_length: 3; /**< Destination burst length */ + uint32_t src_burst_length: 3; /**< Source burst length */ + uint32_t enable_src_gather: 1; /**< Enable source gather? */ + uint32_t enable_dst_scatter: 1; /**< Enable destination scatter? */ + uint32_t : 1; /**< Reserved bits */ + uint32_t transfer_flow: 3; /**< DMA transfer flow */ + uint32_t : 4; /**< Reserved bits */ + uint32_t enable_dst_linked_list: 1; /**< Enable destination linked list? */ + uint32_t enable_src_linked_list: 1; /**< Enable source linked list? */ + uint32_t : 3; /**< Reserved bits */ + }; + uint32_t control; + }; + uint32_t block_size; /**< Transfer block size */ + uint32_t src_status; /**< Source status */ + uint32_t dst_status; /**< Destination status */ +} XMC_DMA_LLI_t; + +typedef XMC_DMA_LLI_t **XMC_DMA_LIST_t; /**< Type definition for a linked list pointer */ + +/** + * DMA channel configuration structure + */ +typedef struct XMC_DMA_CH_CONFIG +{ + union + { + uint32_t control; + struct + { + uint32_t enable_interrupt: 1; /**< Enable interrupts? */ + uint32_t dst_transfer_width: 3; /**< Destination transfer width */ + uint32_t src_transfer_width: 3; /**< Source transfer width */ + uint32_t dst_address_count_mode: 2; /**< Destination address count mode */ + uint32_t src_address_count_mode: 2; /**< Source address count mode */ + uint32_t dst_burst_length: 3; /**< Destination burst length */ + uint32_t src_burst_length: 3; /**< Source burst length */ + uint32_t enable_src_gather: 1; /**< Enable source gather? */ + uint32_t enable_dst_scatter: 1; /**< Enable destination scatter? */ + uint32_t : 1; + uint32_t transfer_flow: 3; /**< DMA transfer flow */ + uint32_t : 9; + }; + }; + + uint32_t src_addr; /**< Source address */ + uint32_t dst_addr; /**< Destination address */ + XMC_DMA_LLI_t *linked_list_pointer; /**< Linked list pointer */ + + union + { + uint32_t src_gather_control; + struct + { + uint32_t src_gather_interval: 20; /**< Source gather interval */ + uint32_t src_gather_count: 12; /**< Source gather count */ + }; + }; + + union + { + uint32_t dst_scatter_control; + struct + { + uint32_t dst_scatter_interval: 20; /**< Destination scatter interval */ + uint32_t dst_scatter_count: 12; /**< Destination scatter count */ + }; + }; + + uint16_t block_size; /**< Block size for DMA controlled transfers [max. 4095]*/ + XMC_DMA_CH_TRANSFER_TYPE_t transfer_type; /**< DMA transfer type */ + XMC_DMA_CH_PRIORITY_t priority; /**< DMA channel priority */ + XMC_DMA_CH_SRC_HANDSHAKING_t src_handshaking; /**< DMA source handshaking interface */ + uint8_t src_peripheral_request; /**< Source peripheral request */ + XMC_DMA_CH_DST_HANDSHAKING_t dst_handshaking; /**< DMA destination handshaking interface */ + uint8_t dst_peripheral_request; /**< Destination peripheral request */ +} XMC_DMA_CH_CONFIG_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__TASKING__) + #pragma warning restore +#endif + +/** + * DMA channel event handler + */ +typedef void (*XMC_DMA_CH_EVENT_HANDLER_t)(XMC_DMA_CH_EVENT_t event); + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return None + * + * \parDescription:
+ * Initialize the GPDMA peripheral
+ * + * \par + * The function initializes a prioritized list of DMA channels and enables the GPDMA + * peripheral. + */ +void XMC_DMA_Init(XMC_DMA_t *const dma); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return None + * + * \parDescription:
+ * Enable the GPDMA peripheral
+ * + * \par + * The function de-asserts the GPDMA peripheral reset. In addition, it un-gates the + * GPDMA0 peripheral clock for all XMC4000 series of microcontrollers with an exception + * of the XMC4500 microcontroller. The XMC4500 doesn't support gating. + */ +void XMC_DMA_Enable(XMC_DMA_t *const dma); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return None + * + * \parDescription:
+ * Disable the GPDMA peripheral
+ * + * \par + * The function asserts the GPDMA peripheral reset. In addition, it gates the GPDMA0 + * peripheral clock for all XMC4000 series of microcontrollers with an exception of + * the XMC4500 microcontroller. The XMC4500 doesn't support gating. + */ +void XMC_DMA_Disable(XMC_DMA_t *const dma); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return bool + * + * \parDescription:
+ * Check if the GPDMA peripheral is enabled
+ * + * \par + * For the XMC4500 microcontroller, the function checks if the GPDMA module is asserted + * and returns "false" if it is. In addition, it also checks if the clock is gated + * for the other XMC4000 series of microcontrollers. It returns "true" if the peripheral + * is enabled. + */ +bool XMC_DMA_IsEnabled(const XMC_DMA_t *const dma); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA event status + * + * \parDescription:
+ * Get DMA event status
+ * + * \par + * The function returns the collective (global) status of GPDMA events. The following + * lists the various DMA events and their corresponding enumeration. The return value + * of this function may then be masked with any one of the following enumerations to + * obtain the status of individual DMA events.
+ * + * \par + * Transfer complete -> ::XMC_DMA_CH_EVENT_TRANSFER_COMPLETE
+ * Block transfer complete -> ::XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE
+ * Source transaction complete -> ::XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE
+ * Destination transaction complete -> ::XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE
+ * DMA error event -> ::XMC_DMA_CH_EVENT_ERROR
+ */ +__STATIC_INLINE uint32_t XMC_DMA_GetEventStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSGLEV); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA transfer complete status + * + * \parDescription:
+ * Get transfer complete status
+ * + * \par + * The function returns GPDMA transfer complete interrupt status.
+ */ +__STATIC_INLINE uint32_t XMC_DMA_GetChannelsTransferCompleteStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSCHEV[0]); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA block complete status + * + * \parDescription:
+ * Get block transfer complete status
+ * + * \par + * The function returns GPDMA block transfer complete interrupt status.
+ */ +__STATIC_INLINE uint32_t XMC_DMA_GetChannelsBlockCompleteStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSCHEV[2]); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA event status + * + * \parDescription:
+ * Get source transaction complete status
+ * + * \par + * The function returns the source transaction complete interrupt status.
+ * + * \parNote:
+ * If the source peripheral is memory, the source transaction complete interrupt is + * ignored. + */ +__STATIC_INLINE uint32_t XMC_DMA_GetChannelsSourceTransactionCompleteStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSCHEV[4]); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA event status + * + * \parDescription:
+ * Get destination transaction complete status
+ * + * \par + * The function returns the destination transaction complete interrupt status
+ * + * \parNote:
+ * If the destination peripheral is memory, the destination transaction complete + * interrupt is ignored. + */ +__STATIC_INLINE uint32_t XMC_DMA_GetChannelsDestinationTransactionCompleteStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSCHEV[6]); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA error event status + * + * \parDescription:
+ * Get DMA error event status
+ * + * \par + * The function returns error interrupt status.
+ */ +__STATIC_INLINE uint32_t XMC_DMA_GetChannelsErrorStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSCHEV[8]); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param line Which DLR (DMA line router) line should the function use? + * @param peripheral Which hardware peripheral is the GPDMA communicating with? + * @return None + * + * \parDescription:
+ * Enable request line
+ * + * \par + * The function enables a DLR (DMA line router) line and selects a service request + * source, resulting in the trigger of a DMA transfer.
+ * + * \parNote:
+ * The DLR is used for a DMA transfer typically involving a peripheral; For example, + * the ADC peripheral may use the DLR in hardware handshaking mode to transfer + * ADC conversion values to a destination memory block. + */ +void XMC_DMA_EnableRequestLine(XMC_DMA_t *const dma, uint8_t line, uint8_t peripheral); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param line Which DLR (DMA line router) line should the function use? + * @return None + * + * \parDescription:
+ * Disable request line
+ * + * \par + * The function disables a DLR (DMA line router) line by clearing appropriate bits + * in the LNEN register.
+ */ +void XMC_DMA_DisableRequestLine(XMC_DMA_t *const dma, uint8_t line); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param line Which DLR (DMA line router) line should the function use? + * @return None + * + * \parDescription:
+ * Clear request line
+ * + * \par + * The function clears a DLR (DMA line router) request line.
+ */ +void XMC_DMA_ClearRequestLine(XMC_DMA_t *const dma, uint8_t line); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param line The line for which the overrun status is requested + * @return bool "true" if overrun occured, "false" otherwise + * + * \parDescription:
+ * Get overrun status of a DLR line
+ * + * \par + * The DLR module's OVERSTAT register keeps track of DMA service request overruns. + * Should an overrun occur, the bit corresponding to the used DLR line is set. The + * function simply reads this status and returns "true" if an overrun is detected + * It returns "false" if an overrun isn't registered. + */ +bool XMC_DMA_GetOverrunStatus(XMC_DMA_t *const dma, const uint8_t line); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param line The line for which the overrun status must be cleared + * @return None + * + * \parDescription:
+ * Clear overrun status of a DLR line
+ * + * \par + * The function clears the overrun status of a line by setting the corresponding + * line bit in the DLR's OVERCLR register. + */ +void XMC_DMA_ClearOverrunStatus(XMC_DMA_t *const dma, const uint8_t line); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The GPDMA channel (number) which needs to be initialized + * @param config A constant pointer to ::XMC_DMA_CH_CONFIG_t, pointing to a const + * channel configuration + * @return XMC_DMA_CH_STATUS_t Initialization status + * + * \parDescription:
+ * Initialize a GPDMA channel with provided channel configuration
+ * + * \par + * The function sets up the following channel configuration parameters for a GPDMA + * channel (specified by the parameter channel):
+ * 1) Source and destination addresses (and linked list address if requested)
+ * 2) Source and destination handshaking interface (hardware or software?)
+ * 3) Scatter/gather configuration
+ * 4) Source and destination peripheral request (DMA is the flow controller)
+ * 5) Transfer flow and type
+ * + * \par + * The function returns one of the following values:
+ * 1) In case the DMA channel is not enabled: ::XMC_DMA_CH_STATUS_BUSY
+ * 2) If the GPDMA module itself is not enabled: ::XMC_DMA_CH_STATUS_ERROR
+ * 3) If the configuration was successful: ::XMC_DMA_CH_STATUS_OK
+ * + * \par + * Once the initialization is successful, calling ::XMC_DMA_CH_Enable() will trigger + * a GPDMA transfer. + */ +XMC_DMA_CH_STATUS_t XMC_DMA_CH_Init(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_CONFIG_t *const config); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should be enabled? + * @return None + * + * \parDescription:
+ * Enable a GPDMA channel
+ * + * \par + * The function sets the GPDMA's CHENREG register to enable a DMA channel. Please + * ensure that the GPDMA module itself is enabled before calling this function. + * See ::XMC_DMA_Enable() for details. + */ +__STATIC_INLINE void XMC_DMA_CH_Enable(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CHENREG = (uint32_t)(0x101UL << channel); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should be disabled? + * @return None + * + * \parDescription:
+ * Disable a GPDMA channel
+ * + * \par + * The function resets the GPDMA's CHENREG register to disable a DMA channel. + */ +void XMC_DMA_CH_Disable(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should be disabled? + * @return bool + * + * \parDescription:
+ * Check if a GPDMA channel is enabled
+ * + * \par + * The function reads the GPDMA's CHENREG register to check if a DMA channel is + * enabled or not. The function returns "true" is the requested channel is enabled, + * "false" otherwise. + */ +bool XMC_DMA_CH_IsEnabled(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should suspend transfer? + * @return None + * + * \parDescription:
+ * Suspend a GPDMA channel transfer
+ * + * \par + * The function sets the CH_SUSP bit of the GPDMA's GFGL register to initiate a + * DMA transfer suspend. The function may be called after enabling the DMA channel. + * Please see ::XMC_DMA_CH_Enable() for more information. + * + * \parRelated API:
+ * ::XMC_DMA_CH_Resume()
+ */ +void XMC_DMA_CH_Suspend(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should resume transfer? + * @return None + * + * \parDescription:
+ * Resume a GPDMA channel
+ * + * \par + * The function clears the CH_SUSP bit of the GPDMA's GFGL register to resume a + * DMA transfer. The function may be called after enabling the DMA channel. Please + * see ::XMC_DMA_CH_Enable() for more information. + * + * \parRelated API:
+ * ::XMC_DMA_CH_Suspend()
+ */ +void XMC_DMA_CH_Resume(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel A DMA channel + * @param addr source address + * @return None + * + * \parDescription:
+ * This function sets the source address of the specified channel
+ * + * \par + * The function may be called after enabling the DMA channel. Please + * see ::XMC_DMA_CH_Enable() for more information. + * + * \parRelated API:
+ * ::XMC_DMA_CH_SetDestinationAddress()
+ */ +__STATIC_INLINE void XMC_DMA_CH_SetSourceAddress(XMC_DMA_t *const dma, const uint8_t channel, uint32_t addr) +{ + dma->CH[channel].SAR = addr; +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel A DMA channel + * @param addr destination address + * @return None + * + * \parDescription:
+ * This function sets the destination address of the specified channel
+ * + * \par + * The function may be called after enabling the DMA channel. Please + * see ::XMC_DMA_CH_Enable() for more information. + * + * \parRelated API:
+ * ::XMC_DMA_CH_SetSourceAddress()
+ */ +__STATIC_INLINE void XMC_DMA_CH_SetDestinationAddress(XMC_DMA_t *const dma, const uint8_t channel, uint32_t addr) +{ + dma->CH[channel].DAR = addr; +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel A DMA channel + * @param block_size Transfer size [1-2048] + * @return None + * + * \parDescription:
+ * This function sets the block size of a transfer
+ * + * \par + * The function may be called after enabling the DMA channel. Please + * see ::XMC_DMA_CH_Enable() for more information. + * + */ +__STATIC_INLINE void XMC_DMA_CH_SetBlockSize(XMC_DMA_t *const dma, const uint8_t channel, uint32_t block_size) +{ + dma->CH[channel].CTLH = block_size; +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel A DMA channel + * @param ll_ptr linked list pointer + * @return None + * + * \parDescription:
+ * This function sets the linked list pointer
+ * + * \par + * The function may be called after enabling the DMA channel. Please + * see ::XMC_DMA_CH_Enable() for more information. + * + */ +__STATIC_INLINE void XMC_DMA_CH_SetLinkedListPointer(XMC_DMA_t *const dma, const uint8_t channel, XMC_DMA_LLI_t *ll_ptr) +{ + dma->CH[channel].LLP = (uint32_t)ll_ptr; +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should be checked for a suspended transfer? + * @return bool + * + * \parDescription:
+ * Check if a GPDMA
+ * + * \par + * The function reads the CH_SUSP bit of the GPDMA's GFGL register to check if a + * DMA transfer for the requested channel has been suspended. The function returns + * "true" if it detects a transfer suspension or "false" if it doesn't. + * + * \parRelated API:
+ * ::XMC_DMA_CH_Suspend(), ::XMC_DMA_CH_Resume()
+ */ +bool XMC_DMA_CH_IsSuspended(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the event(s) need(s) to be enabled + * @param event A valid GPDMA event (::XMC_DMA_CH_EVENT_t) or a valid combination + * of logically OR'd GPDMA events + * @return None + * + * \parDescription:
+ * Enable GPDMA event(s)
+ * + * \par + * The following events are supported by the GPDMA peripheral:
+ * 1) Transfer complete event
+ * 2) Block transfer complete event
+ * 3) Source transaction complete event
+ * 4) Destination transaction complete event
+ * 5) DMA error event
+ * + * \par + * The function can be used to enable one (or more) of the aforementioned events. + * Once the events have been enabled, ::XMC_DMA_CH_SetEventHandler() API can be + * used to set a callback function. + */ +void XMC_DMA_CH_EnableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the event(s) need(s) to be disabled + * @param event A valid GPDMA event (::XMC_DMA_CH_EVENT_t) or a valid combination + * of logically OR'd GPDMA events + * @return None + * + * \parDescription:
+ * Disable GPDMA event(s)
+ * + * \par + * The following events are supported by the GPDMA peripheral:
+ * 1) Transfer complete event
+ * 2) Block transfer complete event
+ * 3) Source transaction complete event
+ * 4) Destination transaction complete event
+ * 5) DMA error event
+ * + * \par + * The function can be used to disable one (or more) of the aforementioned events. + */ +void XMC_DMA_CH_DisableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the event(s) need(s) to be disabled + * @param event A valid GPDMA event (::XMC_DMA_CH_EVENT_t) or a valid combination + * of logically OR'd GPDMA events + * @return None + * + * \parDescription:
+ * Clear GPDMA event status
+ * + * \par + * The following events are supported by the GPDMA peripheral:
+ * 1) Transfer complete event
+ * 2) Block transfer complete event
+ * 3) Source transaction complete event
+ * 4) Destination transaction complete event
+ * 5) DMA error event
+ * + * \par + * The function is used to clear the status of one (or more) of the aforementioned + * events. Typically, its use is in the GPDMA interrupt handler function. Once an + * event is detected, an appropriate callback function must run and the event status + * should be cleared. + */ +void XMC_DMA_CH_ClearEventStatus(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the event(s) status must be obtained + * @return Event status + * + * \parDescription:
+ * Get GPDMA channel event status
+ * + * \par + * The function is used obtain the status of one (or more) of the aforementioned + * events. The return value may then be masked with any one of the following + * enumerations to obtain the status of individual DMA events.
+ * + * \par + * Transfer complete -> ::XMC_DMA_CH_EVENT_TRANSFER_COMPLETE
+ * Block transfer complete -> ::XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE
+ * Source transaction complete -> ::XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE
+ * Destination transaction complete -> ::XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE
+ * DMA error event -> ::XMC_DMA_CH_EVENT_ERROR
+ * + * \par + * Typically, its use is in the GPDMA interrupt handler function. Once an event is + * detected, an appropriate callback function must run and the event status should + * be cleared. + */ +uint32_t XMC_DMA_CH_GetEventStatus(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel is used for source gather? + * @param interval Gather interval + * @param count Gather count + * @return None + * + * \parDescription:
+ * Enable source gather
+ * + * \par + * The function is used to enable the source gather feature in the GPDMA peripheral. + * The user must also specify the gather count and interval. Once the configuration + * is successful, calling ::XMC_DMA_CH_EnableEvent() will initiate source gather. + * This function is normally used in conjunction with destination scatter. Please + * see ::XMC_DMA_CH_EnableDestinationScatter() for additional information. + */ +void XMC_DMA_CH_EnableSourceGather(XMC_DMA_t *const dma, const uint8_t channel, uint32_t interval, uint16_t count); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The source gather for which DMA channel is to be disabled? + * @return None + * + * \parDescription:
+ * Disable source gather
+ * + * \par + * The function is used to disable the source gather feature in the GPDMA peripheral. + */ +void XMC_DMA_CH_DisableSourceGather(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel is used for destination scatter? + * @param interval Scatter interval + * @param count Scatter count + * @return None + * + * \parDescription:
+ * Enable destination scatter
+ * + * \par + * The function is used to enable the destination scatter feature in the GPDMA + * peripheral. The user must also specify the scatter count and interval. Once + * the configuration is successful, calling ::XMC_DMA_CH_EnableEvent() will + * initiate destination gather. This function is normally used in conjunction + * with source gather. Please see ::XMC_DMA_CH_EnableSourceGather() for + * additional information. + */ +void XMC_DMA_CH_EnableDestinationScatter(XMC_DMA_t *const dma, const uint8_t channel, uint32_t interval, uint16_t count); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The source gather for which DMA channel is to be disabled? + * @return None + * + * \parDescription:
+ * Disable source gather
+ * + * \par + * The function is used to disable the destination scatter feature in the GPDMA + * peripheral. + */ +void XMC_DMA_CH_DisableDestinationScatter(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel is being used? + * @param type Transaction type: Single/burst mode + * @param last Specify "true" if it is the last source request trigger, "false" + * otherwise + * @return None + * + * \parDescription:
+ * Trigger source request
+ * + * \par + * The function can be used for GPDMA transfers involving a peripheral in software + * handshaking mode viz. Memory -> peripheral and peripheral -> peripheral. + * + * \par + * One would typically use this function in a (destination) peripheral's event + * callback function to trigger the source request. + */ +void XMC_DMA_CH_TriggerSourceRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel is being used? + * @param type Transaction type: Single/burst mode + * @param last Specify "true" if it is the last destination request trigger, "false" + * otherwise + * @return None + * + * \parDescription:
+ * Trigger destination request
+ * + * \par + * The function can be used for GPDMA transfers involving a peripheral in software + * handshaking mode viz. Peripheral -> memory and peripheral -> peripheral. + * + * \par + * One would typically use this function in a (source) peripheral's event + * callback function to trigger the destination request. + */ +void XMC_DMA_CH_TriggerDestinationRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the source address must be reloaded + * @return None + * + * \parDescription:
+ * Enable source address reload
+ * + * \par + * The function is used to automatically reload the source DMA address (from its + * initial value) at the end of every block in a multi-block transfer. The auto- + * reload will begin soon after the DMA channel initialization (configured for a + * multi-block transaction). + */ +void XMC_DMA_CH_EnableSourceAddressReload(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the source address reload must be disabled + * @return None + * + * \parDescription:
+ * Disable source address reload
+ * + * \par + * The source DMA address can be automatically reloaded from its initial value at + * the end of every block in a multi-block transfer. To disable this feature, use + * this function. + */ +void XMC_DMA_CH_DisableSourceAddressReload(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the destination address must be reloaded + * @return None + * + * \parDescription:
+ * Enable source address reload
+ * + * \par + * The function is used to automatically reload the destination DMA address (from + * its initial value) at the end of every block in a multi-block transfer. The auto- + * reload will begin soon after the DMA channel initialization (configured for a + * multi-block transaction). + */ +void XMC_DMA_CH_EnableDestinationAddressReload(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the destination address reload must be + * disabled + * @return None + * + * \parDescription:
+ * Disable destination address reload
+ * + * \par + * The destination DMA address can be automatically reloaded from its initial value + * at the end of every block in a multi-block transfer. To disable this feature, + * use this function. + */ +void XMC_DMA_CH_DisableDestinationAddressReload(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel is participating in a multi-block transfer? + * @return None + * + * \parDescription:
+ * Trigger the end of a multi-block transfer
+ * + * \par + * The function is used signal the end of multi-block DMA transfer. It clears the + * RELOAD_SRC and RELOAD_DST bits of the CFGL register to keep the source and + * destination addresses from getting updated. The function is typically used in + * an event handler to signal that the next block getting transferred is the last + * block in the transfer sequence. + */ +void XMC_DMA_CH_RequestLastMultiblockTransfer(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the event handler is being registered + * @param event_handler The event handler which will be invoked when the DMA event + * occurs + * @return None + * + * \parDescription:
+ * Set a GPDMA event handler to service GPDMA events
+ * + * \par + * The function is used to register user callback functions for servicing DMA events. + * Call this function after enabling the GPDMA events (See ::XMC_DMA_CH_EnableEvent()) + */ +void XMC_DMA_CH_SetEventHandler(XMC_DMA_t *const dma, const uint8_t channel, XMC_DMA_CH_EVENT_HANDLER_t event_handler); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The source peripheral request for which DMA channel is to be cleared? + * @return None + * + * \parDescription:
+ * Clear source peripheral request
+ * + * \par + * The function is used to clear the source peripheral request for a given DMA + * channel. + */ +void XMC_DMA_CH_ClearSourcePeripheralRequest(XMC_DMA_t *const dma, uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The destination peripheral request for which DMA channel is to be cleared? + * @return None + * + * \parDescription:
+ * Clear destination peripheral request
+ * + * \par + * The function is used to clear the destination peripheral request for a given DMA + * channel. + */ +void XMC_DMA_CH_ClearDestinationPeripheralRequest(XMC_DMA_t *const dma, uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return None + * + * \parDescription:
+ * Default GPDMA IRQ handler
+ * + * \par + * The function implements a default GPDMA IRQ handler. It can be used within the + * following (device specific) routines:
+ * 1) GPDMA0_0_IRQHandler
+ * 2) GPDMA1_0_IRQHandler
+ * + * The function handles the enabled GPDMA events and runs the user callback function + * registered by the user to service the event. To register a callback function, + * see ::XMC_DMA_CH_SetEventHandler() + */ +void XMC_DMA_IRQHandler(XMC_DMA_t *const dma); + +#ifdef __cplusplus +} +#endif + +/** + * @} (end addtogroup DMA) + */ + +/** + * @} (end addtogroup XMClib) + */ + +#endif /* defined (GPDMA0) */ +#endif /* XMC_DMA_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dma_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dma_map.h new file mode 100644 index 00000000..e31476b7 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dma_map.h @@ -0,0 +1,345 @@ + +/** + * @file xmc_dma_map.h + * @date 2015-05-07 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial version + * + * 2015-05-07: + * - Change line numbering for DMA1
+ * + * @endcond + */ + +#ifndef XMC_DMA_MAP_H +#define XMC_DMA_MAP_H + +#define DMA_PERIPHERAL_REQUEST(line, sel) (uint8_t)(line | (sel << 4U)) + +/* + * DMA LINE 0 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR0_0 DMA_PERIPHERAL_REQUEST(0, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR3_0 DMA_PERIPHERAL_REQUEST(0, 2) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR0_0 DMA_PERIPHERAL_REQUEST(0, 3) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR3_0 DMA_PERIPHERAL_REQUEST(0, 4) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM0_0 DMA_PERIPHERAL_REQUEST(0, 5) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CCU40_SR0_0 DMA_PERIPHERAL_REQUEST(0, 6) +#define DMA0_PERIPHERAL_REQUEST_CCU80_SR0_0 DMA_PERIPHERAL_REQUEST(0, 7) +#define DMA0_PERIPHERAL_REQUEST_CAN_SR0_0 DMA_PERIPHERAL_REQUEST(0, 9) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_0 DMA_PERIPHERAL_REQUEST(0, 11) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR3_0 DMA_PERIPHERAL_REQUEST(0, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU42_SR0_0 DMA_PERIPHERAL_REQUEST(0, 14) +#endif + +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) +#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 15) +#endif + +/* + * DMA LINE 1 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR3_1 DMA_PERIPHERAL_REQUEST(1, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR1_1 DMA_PERIPHERAL_REQUEST(1, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_1 DMA_PERIPHERAL_REQUEST(1, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR0_1 DMA_PERIPHERAL_REQUEST(1, 3) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR2_1 DMA_PERIPHERAL_REQUEST(1, 4) +#endif + +#define DMA0_PERIPHERAL_REQUEST_DAC_SR0_1 DMA_PERIPHERAL_REQUEST(1, 5) +#define DMA0_PERIPHERAL_REQUEST_CCU40_SR0_1 DMA_PERIPHERAL_REQUEST(1, 6) +#define DMA0_PERIPHERAL_REQUEST_CCU80_SR0_1 DMA_PERIPHERAL_REQUEST(1, 7) +#define DMA0_PERIPHERAL_REQUEST_CAN_SR0_1 DMA_PERIPHERAL_REQUEST(1, 9) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_1 DMA_PERIPHERAL_REQUEST(1, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_1 DMA_PERIPHERAL_REQUEST(1, 11) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR0_1 DMA_PERIPHERAL_REQUEST(1, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU42_SR0_1 DMA_PERIPHERAL_REQUEST(1, 14) +#endif + +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) +#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR1_1 DMA_PERIPHERAL_REQUEST(1, 15) +#endif + +/* + * DMA LINE 2 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR1_2 DMA_PERIPHERAL_REQUEST(2, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR2_2 DMA_PERIPHERAL_REQUEST(2, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR3_2 DMA_PERIPHERAL_REQUEST(2, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR3_2 DMA_PERIPHERAL_REQUEST(2, 3) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR1_2 DMA_PERIPHERAL_REQUEST(2, 4) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM1_2 DMA_PERIPHERAL_REQUEST(2, 5) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM3_2 DMA_PERIPHERAL_REQUEST(2, 6) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CCU40_SR1_2 DMA_PERIPHERAL_REQUEST(2, 7) +#define DMA0_PERIPHERAL_REQUEST_CCU80_SR1_2 DMA_PERIPHERAL_REQUEST(2, 8) +#define DMA0_PERIPHERAL_REQUEST_CAN_SR1_2 DMA_PERIPHERAL_REQUEST(2, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_2 DMA_PERIPHERAL_REQUEST(2, 11) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_2 DMA_PERIPHERAL_REQUEST(2, 12) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR2_2 DMA_PERIPHERAL_REQUEST(2, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU42_SR1_2 DMA_PERIPHERAL_REQUEST(2, 14) +#endif + +/* + * DMA LINE 3 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR2_3 DMA_PERIPHERAL_REQUEST(3, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR2_3 DMA_PERIPHERAL_REQUEST(3, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR3_3 DMA_PERIPHERAL_REQUEST(3, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR1_3 DMA_PERIPHERAL_REQUEST(3, 3) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR2_3 DMA_PERIPHERAL_REQUEST(3, 4) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM2_3 DMA_PERIPHERAL_REQUEST(3, 5) +#endif + +#define DMA0_PERIPHERAL_REQUEST_DAC_SR1_3 DMA_PERIPHERAL_REQUEST(3, 6) +#define DMA0_PERIPHERAL_REQUEST_CCU40_SR1_3 DMA_PERIPHERAL_REQUEST(3, 7) +#define DMA0_PERIPHERAL_REQUEST_CCU80_SR1_3 DMA_PERIPHERAL_REQUEST(3, 8) +#define DMA0_PERIPHERAL_REQUEST_CAN_SR1_3 DMA_PERIPHERAL_REQUEST(3, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_3 DMA_PERIPHERAL_REQUEST(3, 11) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_3 DMA_PERIPHERAL_REQUEST(3, 12) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR1_3 DMA_PERIPHERAL_REQUEST(3, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU42_SR1_3 DMA_PERIPHERAL_REQUEST(3, 14) +#endif + +/* + * DMA LINE 4 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR2_4 DMA_PERIPHERAL_REQUEST(4, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR0_4 DMA_PERIPHERAL_REQUEST(4, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR1_4 DMA_PERIPHERAL_REQUEST(4, 2) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR1_4 DMA_PERIPHERAL_REQUEST(4, 3) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR2_4 DMA_PERIPHERAL_REQUEST(4, 4) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM2_4 DMA_PERIPHERAL_REQUEST(4, 5) +#endif + +#define DMA0_PERIPHERAL_REQUEST_DAC_SR1_4 DMA_PERIPHERAL_REQUEST(4, 6) +#define DMA0_PERIPHERAL_REQUEST_CCU41_SR0_4 DMA_PERIPHERAL_REQUEST(4, 7) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_CCU81_SR0_4 DMA_PERIPHERAL_REQUEST(4, 8) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CAN_SR2_4 DMA_PERIPHERAL_REQUEST(4, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_4 DMA_PERIPHERAL_REQUEST(4, 11) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_4 DMA_PERIPHERAL_REQUEST(4, 12) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR1_4 DMA_PERIPHERAL_REQUEST(4, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU43_SR0_4 DMA_PERIPHERAL_REQUEST(4, 14) +#endif + +/* + * DMA LINE 5 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR1_5 DMA_PERIPHERAL_REQUEST(5, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR0_5 DMA_PERIPHERAL_REQUEST(5, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR1_5 DMA_PERIPHERAL_REQUEST(5, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR2_5 DMA_PERIPHERAL_REQUEST(5, 3) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR0_5 DMA_PERIPHERAL_REQUEST(5, 4) +#endif + +#define DMA0_PERIPHERAL_REQUEST_DAC_SR0_5 DMA_PERIPHERAL_REQUEST(5, 5) +#define DMA0_PERIPHERAL_REQUEST_CCU41_SR0_5 DMA_PERIPHERAL_REQUEST(5, 6) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_CCU81_SR0_5 DMA_PERIPHERAL_REQUEST(5, 7) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CAN_SR2_5 DMA_PERIPHERAL_REQUEST(5, 9) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_5 DMA_PERIPHERAL_REQUEST(5, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_5 DMA_PERIPHERAL_REQUEST(5, 11) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR2_5 DMA_PERIPHERAL_REQUEST(5, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU43_SR0_5 DMA_PERIPHERAL_REQUEST(5, 14) +#endif + +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) +#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR0_5 DMA_PERIPHERAL_REQUEST(5, 15) +#endif + +/* + * DMA LINE 6 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR3_6 DMA_PERIPHERAL_REQUEST(6, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR1_6 DMA_PERIPHERAL_REQUEST(6, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_6 DMA_PERIPHERAL_REQUEST(6, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR1_6 DMA_PERIPHERAL_REQUEST(6, 3) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR3_6 DMA_PERIPHERAL_REQUEST(6, 4) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM1_6 DMA_PERIPHERAL_REQUEST(6, 5) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM3_6 DMA_PERIPHERAL_REQUEST(6, 6) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CCU41_SR1_6 DMA_PERIPHERAL_REQUEST(6, 7) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_CCU81_SR1_6 DMA_PERIPHERAL_REQUEST(6, 8) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CAN_SR3_6 DMA_PERIPHERAL_REQUEST(6, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_6 DMA_PERIPHERAL_REQUEST(6, 11) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_6 DMA_PERIPHERAL_REQUEST(6, 12) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR0_6 DMA_PERIPHERAL_REQUEST(6, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU43_SR1_6 DMA_PERIPHERAL_REQUEST(6, 14) +#endif + +/* + * DMA LINE 7 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR0_7 DMA_PERIPHERAL_REQUEST(7, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR0_7 DMA_PERIPHERAL_REQUEST(7, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR3_7 DMA_PERIPHERAL_REQUEST(7, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR0_7 DMA_PERIPHERAL_REQUEST(7, 3) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR3_7 DMA_PERIPHERAL_REQUEST(7, 4) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM0_7 DMA_PERIPHERAL_REQUEST(7, 5) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CCU41_SR1_7 DMA_PERIPHERAL_REQUEST(7, 6) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_CCU81_SR1_7 DMA_PERIPHERAL_REQUEST(7, 7) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CAN_SR3_7 DMA_PERIPHERAL_REQUEST(7, 9) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_7 DMA_PERIPHERAL_REQUEST(7, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_7 DMA_PERIPHERAL_REQUEST(7, 11) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR3_7 DMA_PERIPHERAL_REQUEST(7, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU43_SR1_7 DMA_PERIPHERAL_REQUEST(7, 14) +#endif + +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) +#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR1_7 DMA_PERIPHERAL_REQUEST(7, 15) +#endif + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || UC_SERIES == XMC45) +/* + * DMA LINE 0 of DMA1 + */ + +#define DMA1_PERIPHERAL_REQUEST_ERU0_SR0_8 DMA_PERIPHERAL_REQUEST(0, 0) +#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR0_8 DMA_PERIPHERAL_REQUEST(0, 1) +#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR0_8 DMA_PERIPHERAL_REQUEST(0, 2) +#define DMA1_PERIPHERAL_REQUEST_DSD_SRM0_8 DMA_PERIPHERAL_REQUEST(0, 3) +#define DMA1_PERIPHERAL_REQUEST_DAC_SR0_8 DMA_PERIPHERAL_REQUEST(0, 4) +#define DMA1_PERIPHERAL_REQUEST_CCU42_SR0_8 DMA_PERIPHERAL_REQUEST(0, 5) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR0_8 DMA_PERIPHERAL_REQUEST(0, 6) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR2_8 DMA_PERIPHERAL_REQUEST(0, 7) + +/* + * DMA LINE 1 of DMA1 + */ + +#define DMA1_PERIPHERAL_REQUEST_ERU0_SR1_9 DMA_PERIPHERAL_REQUEST(1, 0) +#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR1_9 DMA_PERIPHERAL_REQUEST(1, 1) +#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR1_9 DMA_PERIPHERAL_REQUEST(1, 2) +#define DMA1_PERIPHERAL_REQUEST_DSD_SRM1_9 DMA_PERIPHERAL_REQUEST(1, 3) +#define DMA1_PERIPHERAL_REQUEST_DAC_SR1_9 DMA_PERIPHERAL_REQUEST(1, 4) +#define DMA1_PERIPHERAL_REQUEST_CCU42_SR1_9 DMA_PERIPHERAL_REQUEST(1, 5) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR1_9 DMA_PERIPHERAL_REQUEST(1, 6) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR3_9 DMA_PERIPHERAL_REQUEST(1, 7) + +/* + * DMA LINE 2 of DMA1 + */ + +#define DMA1_PERIPHERAL_REQUEST_ERU0_SR2_10 DMA_PERIPHERAL_REQUEST(2, 0) +#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR2_10 DMA_PERIPHERAL_REQUEST(2, 1) +#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR2_10 DMA_PERIPHERAL_REQUEST(2, 2) +#define DMA1_PERIPHERAL_REQUEST_DSD_SRM2_10 DMA_PERIPHERAL_REQUEST(2, 3) +#define DMA1_PERIPHERAL_REQUEST_DAC_SR0_10 DMA_PERIPHERAL_REQUEST(2, 4) +#define DMA1_PERIPHERAL_REQUEST_CCU43_SR0_10 DMA_PERIPHERAL_REQUEST(2, 5) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR0_10 DMA_PERIPHERAL_REQUEST(2, 6) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR2_10 DMA_PERIPHERAL_REQUEST(2, 7) + +/* + * DMA LINE 3 of DMA1 + */ + +#define DMA1_PERIPHERAL_REQUEST_ERU0_SR3_11 DMA_PERIPHERAL_REQUEST(3, 0) +#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR3_11 DMA_PERIPHERAL_REQUEST(3, 1) +#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR3_11 DMA_PERIPHERAL_REQUEST(3, 2) +#define DMA1_PERIPHERAL_REQUEST_DSD_SRM3_11 DMA_PERIPHERAL_REQUEST(3, 3) +#define DMA1_PERIPHERAL_REQUEST_DAC_SR1_11 DMA_PERIPHERAL_REQUEST(3, 4) +#define DMA1_PERIPHERAL_REQUEST_CCU43_SR1_11 DMA_PERIPHERAL_REQUEST(3, 5) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR1_11 DMA_PERIPHERAL_REQUEST(3, 6) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR3_11 DMA_PERIPHERAL_REQUEST(3, 7) + +#endif /* (UC_SERIES == XMC45) */ + +#endif /* XMC_DMA_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dsd.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dsd.h new file mode 100644 index 00000000..53a90794 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_dsd.h @@ -0,0 +1,1185 @@ +/** + * @file xmc_dsd.h + * @date 2015-09-18 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-03-30: + * - Initial version + * + * 2015-06-19: + * - Removed version macros and declaration of GetDriverVersion API
+ * - Added API XMC_DSD_CH_GetRectifyDelay
+ * + * 2015-07-16: + * - Renamed API “XMC_DSD_CH_AuxFilter_SetBoudary()†to “XMC_DSD_CH_AuxFilter_SetBoundary()â€
+ * + * 2015-09-18: + * - Added APIs "XMC_DSD_SetResultEventFlag()","XMC_DSD_ClearResultEventFlag()" + * "XMC_DSD_SetAlarmEventFlag()" and "XMC_DSD_ClearAlarmEventFlag()"
+ * - Support added for XMC4800 microcontroller family
+ * @endcond + * + */ + + +#ifndef XMC_DSD_H +#define XMC_DSD_H + + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ +#include + +#if defined(DSD) +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup DSD +* @{ +* @brief Delta Sigma Demodulator (DSD) driver for the XMC4500, XMC4400 and XMC4800 microcontroller family
+ * + * The DSD unit provides a series of digital input channels accepting data streams from external modulators + * using the Delta/Sigma (DS) conversion principle. The on-chip demodulator channels convert these inputs to + * discrete digital values. + * DSD unit can be used for isolated current/voltage measurement and for sensor interfaces.
+ * + * Driver is divided in six DSD functional blocks - + * - Main Filter (APIs prefixed with XMC_DSD_CH_MainFilter), + * - Aux Filter (APIs prefixed with XMC_DSD_CH_AuxFilter), + * - Integrator (APIs prefixed with XMC_DSD_CH_Integrator), + * - Timestamp (APIs prefixed with XMC_DSD_CH_Timestamp), + * - Rectification (APIs prefixed with XMC_DSD_CH_Rectify), + * - Carrier Generator (APIs prefixed with XMC_DSD_Generator) + * + * DSD driver features: + * -# DSD channel Configuration structure XMC_DSD_CH_CONFIG_t initialization function XMC_DSD_CH_Init() to configure all the functional blocks (except carrier generator) + * -# Configuration structure XMC_DSD_GENERATOR_CONFIG_t and initialization function XMC_DSD_Generator_Init() to configure carrier generator + * -# Configuration structure XMC_DSD_CH_FILTER_CONFIG_t and initialization function XMC_DSD_CH_MainFilter_Init() to configure main filter + * -# Configuration structure XMC_DSD_CH_AUX_FILTER_CONFIG_t and initialization function XMC_DSD_CH_AuxFilter_Init() to configure auxilary filter + * -# Configuration structure XMC_DSD_CH_INTEGRATOR_CONFIG_t and initialization function XMC_DSD_CH_Integrator_Init() to configure integrator + * -# Configuration structure XMC_DSD_CH_TIMESTAMP_CONFIG_t and initialization function XMC_DSD_CH_Timestamp_Init() to configure timestamp + * -# Configuration structure XMC_DSD_CH_RECTIFY_CONFIG_t and initialization function XMC_DSD_CH_Rectify_Init() to configure rectifier + */ + + /********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + #define XMC_DSD_CHECK_MODULE_PTR(PTR) ( ((PTR)== DSD)) + #define XMC_DSD_CHECK_CHANNEL_PTR(PTR) ( ((PTR) == DSD_CH0) || ((PTR) == DSD_CH1) || ((PTR) == DSD_CH2) || ((PTR) == DSD_CH3)) + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ +/** + * DSD Channel + */ +typedef DSD_CH_TypeDef XMC_DSD_CH_t; + +/** + * DSD Module + */ +typedef DSD_GLOBAL_TypeDef XMC_DSD_t; + + +/** + * Return types of the API's.Use type @ref XMC_DSD_STATUS_t for this enum. + */ +typedef enum XMC_DSD_STATUS +{ + + XMC_DSD_STATUS_OK, /**< API fulfills request */ + XMC_DSD_STATUS_ERROR /**< Error detected */ + +} XMC_DSD_STATUS_t; + +/** + * Enumerates the divider factor for the PWM pattern signal generator. + * Use divider factor to derive input frequency of the carrier signal generator(fCG), + * from the selected internal clock source(fCLK). + * Use type @ref XMC_DSD_GENERATOR_CLKDIV_t for this enum. + */ +typedef enum XMC_DSD_GENERATOR_CLKDIV +{ + XMC_DSD_GENERATOR_CLKDIV_2048 = 0x00U, /**< fCG = (fCLK/2)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_4096 = 0x01U, /**< fCG = (fCLK/4)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_6144 = 0x02U, /**< fCG = (fCLK/6)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_8192 = 0x03U, /**< fCG = (fCLK/8)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_10240 = 0x04U, /**< fCG = (fCLK/10)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_12288 = 0x05U, /**< fCG = (fCLK/12)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_14336 = 0x06U, /**< fCG = (fCLK/14)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_16384 = 0x07U, /**< fCG = (fCLK/16)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_18432 = 0x08U, /**< fCG = (fCLK/18)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_20480 = 0x09U, /**< fCG = (fCLK/20)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_22528 = 0x0AU, /**< fCG = (fCLK/22)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_24576 = 0x0BU, /**< fCG = (fCLK/24)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_26624 = 0x0CU, /**< fCG = (fCLK/26)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_28672 = 0x0DU, /**< fCG = (fCLK/28)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_30720 = 0x0EU, /**< fCG = (fCLK/30)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_32768 = 0x0FU /**< fCG = (fCLK/32)/1024 */ + +} XMC_DSD_GENERATOR_CLKDIV_t; + + +/** + * Enumerates the carrier generator operating mode. + * Use type @ref XMC_DSD_GENERATOR_MODE_t for this enum. + */ +typedef enum XMC_DSD_GENERATOR_MODE +{ + XMC_DSD_GENERATOR_MODE_STOPPED = 0x00U, /**< Stopped */ + XMC_DSD_GENERATOR_MODE_RECTANGLE = 0x01U, /**< Square wave */ + XMC_DSD_GENERATOR_MODE_TRIANGLE = 0x02U, /**< Triangle */ + XMC_DSD_GENERATOR_MODE_SINE = 0x03U /**< Sine wave*/ + +} XMC_DSD_GENERATOR_MODE_t; + + +/** + * Enumerates the CIC(cyclic integrating comb) filter type. + * Use type @ref XMC_DSD_CH_FILTER_TYPE_t for this enum. + */ +typedef enum XMC_DSD_CH_FILTER_TYPE +{ + + XMC_DSD_CH_FILTER_TYPE_CIC1, /**< CIC1 filter*/ + XMC_DSD_CH_FILTER_TYPE_CIC2, /**< CIC2 filter*/ + XMC_DSD_CH_FILTER_TYPE_CIC3, /**< CIC3 filter*/ + XMC_DSD_CH_FILTER_TYPE_CICF /**< CICF filter*/ + +} XMC_DSD_CH_FILTER_TYPE_t; + +/** + * Enumerates the input data source select. + * Use type @ref XMC_DSD_CH_DATA_SOURCE_t for this enum. + */ +typedef enum XMC_DSD_CH_DATA_SOURCE +{ + + XMC_DSD_CH_DATA_SOURCE_DISCONNECT = 0U, /**< Disconnected */ + XMC_DSD_CH_DATA_SOURCE_A_DIRECT = 2U, /**< External source, from input A, direct */ + XMC_DSD_CH_DATA_SOURCE_A_INVERTED = 3U, /**< External source, from input A, inverted */ + XMC_DSD_CH_DATA_SOURCE_B_DIRECT = 4U, /**< External source, from input B, direct */ + XMC_DSD_CH_DATA_SOURCE_B_INVERTED = 5U /**< External source, from input B, inverted */ + +} XMC_DSD_CH_DATA_SOURCE_t; + +/** + * Enumerates the sample clock source select. + * Use type @ref XMC_DSD_CH_CLOCK_SOURCE_t for this enum. + */ +typedef enum XMC_DSD_CH_CLOCK_SOURCE +{ + + XMC_DSD_CH_CLOCK_SOURCE_A = 1U, /**< External source, from input A */ + XMC_DSD_CH_CLOCK_SOURCE_B = 2U, /**< External source, from input B */ + XMC_DSD_CH_CLOCK_SOURCE_C = 3U, /**< External source, from input C */ + XMC_DSD_CH_CLOCK_SOURCE_D = 4U, /**< External source, from input D */ + XMC_DSD_CH_CLOCK_SOURCE_INTERN = 15U /**< Internal clock source */ + +} XMC_DSD_CH_CLOCK_SOURCE_t; + + +/** + * Enumerates the data strobe generation Mode. + * Use type @ref XMC_DSD_CH_STROBE_t for this enum. + */ +typedef enum XMC_DSD_CH_STROBE +{ + + XMC_DSD_CH_STROBE_DIRECT_CLOCK_RISE = 1U, /* Direct clock, a sample trigger is generated at each rising clock edge */ + XMC_DSD_CH_STROBE_DIRECT_CLOCK_FALL = 2U, /* Direct clock, a sample trigger is generated at each falling clock edge */ + XMC_DSD_CH_STROBE_DOUBLE_DATA = 3U, /* Double data, a sample trigger is generated at each rising and falling clock edge */ + XMC_DSD_CH_STROBE_DOUBLE_CLOCK_RISE = 5U, /* Double clock, a sample trigger is generated at every 2nd rising clock edge */ + XMC_DSD_CH_STROBE_DOUBLE_CLOCK_FALL = 6U /* Double clock, a sample trigger is generated at every 2nd falling clock edge */ + +} XMC_DSD_CH_STROBE_t; + + +/** + * Enumerates the divider factor for modulator clock (fMOD). + * Use divider factor to derive modulator clock frequency(fMOD), + * from the selected internal clock source(fCLK). + * Use type @ref XMC_DSD_CH_CLK_t for this enum. + */ +typedef enum XMC_DSD_CH_CLK_DIV +{ + + XMC_DSD_CH_CLK_DIV_2, /**< fMOD = fCLK/2 */ + XMC_DSD_CH_CLK_DIV_4, /**< fMOD = fCLK/4 */ + XMC_DSD_CH_CLK_DIV_6, /**< fMOD = fCLK/6 */ + XMC_DSD_CH_CLK_DIV_8, /**< fMOD = fCLK/8 */ + XMC_DSD_CH_CLK_DIV_10, /**< fMOD = fCLK/10 */ + XMC_DSD_CH_CLK_DIV_12, /**< fMOD = fCLK/12 */ + XMC_DSD_CH_CLK_DIV_14, /**< fMOD = fCLK/14 */ + XMC_DSD_CH_CLK_DIV_16, /**< fMOD = fCLK/16 */ + XMC_DSD_CH_CLK_DIV_18, /**< fMOD = fCLK/18 */ + XMC_DSD_CH_CLK_DIV_20, /**< fMOD = fCLK/20 */ + XMC_DSD_CH_CLK_DIV_22, /**< fMOD = fCLK/22 */ + XMC_DSD_CH_CLK_DIV_24, /**< fMOD = fCLK/24 */ + XMC_DSD_CH_CLK_DIV_26, /**< fMOD = fCLK/26 */ + XMC_DSD_CH_CLK_DIV_28, /**< fMOD = fCLK/28 */ + XMC_DSD_CH_CLK_DIV_30, /**< fMOD = fCLK/30 */ + XMC_DSD_CH_CLK_DIV_32 /**< fMOD = fCLK/32 */ + +} XMC_DSD_CH_CLK_t; + +/** + * Enumerates the integrator trigger mode. + * Use type @ref XMC_DSD_CH_INTEGRATOR_START_t for this enum. + */ +typedef enum XMC_DSD_CH_INTEGRATOR_START +{ + XMC_DSD_CH_INTEGRATOR_START_OFF, /**< No integration trigger */ + XMC_DSD_CH_INTEGRATOR_START_TRIGGER_FALL, /**< Trigger event upon a falling edge */ + XMC_DSD_CH_INTEGRATOR_START_TRIGGER_RISE, /**< Trigger event upon a rising edge */ + XMC_DSD_CH_INTEGRATOR_START_ALLWAYS_ON /**< No trigger, integrator active all the time */ + +} XMC_DSD_CH_INTEGRATOR_START_t; + +/** + * Enumerates the integration enable. + * Use type @ref XMC_DSD_CH_INTEGRATOR_STOP_t for this enum. + */ +typedef enum XMC_DSD_CH_INTEGRATOR_STOP +{ + XMC_DSD_CH_INTEGRATOR_STOP_END_OF_LOOPS, /**< Integration stopped upon the inverse trigger event */ + XMC_DSD_CH_INTEGRATOR_STOP_ENDLESS_OR_INVERSE_TRIGGER /**< Integration enabled upon the defined trigger event. */ + +} XMC_DSD_CH_INTEGRATOR_STOP_t; + + +/** + * Enumerates the trigger signal. + * Use type @ref XMC_DSD_CH_TRIGGER_SOURCE_t for this enum. + */ +typedef enum XMC_DSD_CH_TRIGGER_SOURCE +{ + + XMC_DSD_CH_TRIGGER_SOURCE_A = 0U, /**< Trigger signal,input A*/ + XMC_DSD_CH_TRIGGER_SOURCE_B = 1U, /**< Trigger signal,input B*/ + XMC_DSD_CH_TRIGGER_SOURCE_C = 2U, /**< Trigger signal,input C*/ + XMC_DSD_CH_TRIGGER_SOURCE_D = 3U, /**< Trigger signal,input D*/ + XMC_DSD_CH_TRIGGER_SOURCE_E = 4U, /**< Trigger signal,input E*/ + XMC_DSD_CH_TRIGGER_SOURCE_F = 5U, /**< Trigger signal,input F*/ + XMC_DSD_CH_TRIGGER_SOURCE_G = 6U, /**< Trigger signal,input G*/ + XMC_DSD_CH_TRIGGER_SOURCE_H = 7U /**< Trigger signal,input H*/ + +} XMC_DSD_CH_TRIGGER_SOURCE_t; + +/** + * Enumerates the timestamp trigger mode. + * Use type @ref XMC_DSD_CH_TIMESTAMP_TRIGGER_t for this enum. + */ +typedef enum XMC_DSD_CH_TIMESTAMP_TRIGGER +{ + XMC_DSD_CH_TIMESTAMP_TRIGGER_DISABLE, /**< No trigger event*/ + XMC_DSD_CH_TIMESTAMP_TRIGGER_FALL, /**< Trigger event upon a falling edge*/ + XMC_DSD_CH_TIMESTAMP_TRIGGER_RISE, /**< Trigger event upon a rising edge*/ + XMC_DSD_CH_TIMESTAMP_TRIGGER_BOTH_EDGES /**< Trigger event upon both the edge*/ + +} XMC_DSD_CH_TIMESTAMP_TRIGGER_t; + +/** + * Enumerates the carrier generation mode. + * Use type @ref XMC_DSD_CH_SIGN_SOURCE_t for this enum. + */ +typedef enum XMC_DSD_CH_SIGN_SOURCE +{ + XMC_DSD_CH_SIGN_SOURCE_ON_CHIP_GENERATOR, /**< Carrier is generated internally by DSD */ + XMC_DSD_CH_SIGN_SOURCE_NEXT_CHANNEL, /**< Carrier sign signal is generated internally by next channel*/ + XMC_DSD_CH_SIGN_SOURCE_EXTERNAL_A, /**< Carrier is generated externally, External sign signal A*/ + XMC_DSD_CH_SIGN_SOURCE_EXTERNAL_B /**< Carrier is generated externally, External sign signal B*/ + +} XMC_DSD_CH_SIGN_SOURCE_t; + +/** + * Enumerates the channel run control bit register value in global run control register. + * Use type @ref XMC_DSD_CH_ID_t for this enum. + */ +typedef enum XMC_DSD_CH_ID +{ + XMC_DSD_CH_ID_0 = 1U, /**< Register value for channel 0 */ + XMC_DSD_CH_ID_1 = 2U, /**< Register value for channel 1 */ + XMC_DSD_CH_ID_2 = 4U, /**< Register value for channel 2 */ + XMC_DSD_CH_ID_3 = 8U /**< Register value for channel 3 */ + +} XMC_DSD_CH_ID_t; + +/** + * Enumerates the service request generation mode for auxiliary filter. + * Use type @ref XMC_DSD_CH_AUX_EVENT_t for this enum. + * Note: This is combined ENUM for SRGA + ESEL bit fields + */ +typedef enum XMC_DSD_CH_AUX_EVENT +{ + XMC_DSD_CH_AUX_EVENT_DISABLED = 0U, /**< Service request is disabled */ + XMC_DSD_CH_AUX_EVENT_EVERY_NEW_RESULT = 1U, /**< Service request generated for aux filter for every new result */ + XMC_DSD_CH_AUX_EVENT_CAPTURE_SIGN_DELAY = 2U, /**< Service request generated for alternate source */ + XMC_DSD_CH_AUX_EVENT_INSIDE_BOUNDARY = 5U, /**< Service request generated for aux filter if result is inside boundary */ + XMC_DSD_CH_AUX_EVENT_OUTSIDE_BOUNDARY = 9U /**< Service request generated for aux filter if result is outside boundary */ + +} XMC_DSD_CH_AUX_EVENT_t; + +/** + * Enumerates the service request generation for main chain filter. + * Use type @ref XMC_DSD_CH_RESULT_EVENT_t for this enum. + */ +typedef enum XMC_DSD_CH_RESULT_EVENT +{ + XMC_DSD_CH_RESULT_EVENT_DISABLE = 0U, /**< Disable service request */ + XMC_DSD_CH_RESULT_EVENT_ENABLE = 3U /**< Enable service request for each new result value */ + +} XMC_DSD_CH_RESULT_EVENT_t; + + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * DSD generator generates several pattern and frequencies. + * Use type @ref XMC_DSD_GENERATOR_CONFIG_t for this data structure. + * Note: Output pins have to be enabled by user. + */ +typedef struct XMC_DSD_GENERATOR_CONFIG +{ + union + { + struct + { + uint32_t mode: 2; /**< carrier generator operating mode. This parameter can take a value of XMC_DSD_GENERATOR_MODE_t */ + uint32_t bit_reverse: 1; /**< should PWM signal be bit-reversed? 0: Normal mode, 1:Bit-reverse mode */ + uint32_t inverted_polarity: 1; /**< should PWM signal start from negative max. 0: Normal, 1: Inverted */ + uint32_t frequency: 4; /**< Frequency divider value of PWM signal. This parameter can take a value of XMC_DSD_GENERATOR_CLKDIV_t */ + uint32_t :24; + }; + uint32_t generator_conf; /**< Carrier generator configuration register(CGCFG)*/ + }; +} XMC_DSD_GENERATOR_CONFIG_t; + + +/** + * DSD filter is the basic module of the DSD. It can be used separately or can be combined with the other modules like + * integrator, rectify, auxiliary filter etc. + * The filter demodulates the incoming bit stream from the delta sigma modulator to a 16 bit result. + * Note: Configure or reconfigure filter parameters while the channel is inactive. + */ +typedef struct XMC_DSD_CH_FILTER_CONFIG +{ + uint32_t clock_divider: 4; /**< This parameter can take a value of XMC_DSD_CH_CLK_t */ + int16_t offset; /**< Offset subtracted from result.This parameter can take a value of int16_t */ + union + { + struct + { + uint32_t data_source: 4; /**< This parameter can take a value of XMC_DSD_CH_DATA_SOURCE_t */ + uint32_t : 12; + uint32_t clock_source: 4; /**< This parameter can take a value of XMC_DSD_CH_CLOCK_SOURCE_t */ + uint32_t strobe: 4; /**< This parameter can take a value of XMC_DSD_CH_STROBE_t */ + uint32_t :8; + }; + uint32_t demodulator_conf; /*Demodulator Input Configuration Register*/ + }; + union + { + struct + { + uint32_t : 8; + uint32_t filter_type: 2; /**< This parameter can take a value of XMC_DSD_CH_FILTER_TYPE_t */ + uint32_t : 4; + uint32_t result_event : 2; /**< This parameter can take a value of XMC_DSD_CH_RESULT_EVENT_t */ + uint32_t : 8; + uint32_t : 8; + }; + uint32_t main_filter_conf; + + }; + uint32_t decimation_factor; /**< This parameter can be in range of 4 - 256[dec] */ + uint32_t filter_start_value; /**< This parameter can be in range of 4 - decimation_factor[dec]*/ + +} XMC_DSD_CH_FILTER_CONFIG_t; + +/** + * The integrator is mainly used for high accurate measurement. + * Note:DSD Filter is mandatory to use this block. + */ +typedef struct XMC_DSD_CH_INTEGRATOR_CONFIG +{ + union + { + struct + { + uint32_t :8; + uint32_t start_condition: 2; /**< Can take a value of XMC_DSD_CH_INTEGRATOR_START_t.Bitfields \a ITRMODE of \a DICFG.*/ + uint32_t :2; + uint32_t trigger_source: 3; /**< Can take a value of XMC_DSD_CH_TRIGGER_SOURCE_t.Bitfields \a TRSEL of \a DICFG. */ + uint32_t :17; + }; + uint32_t integrator_trigger; /**< Demodulator Input Configuration Register(\a DICFG).*/ + + }; + uint32_t integration_loop; /**< Integration loops to see stop condition. Bitfields \a REPVAL of \a IWCTR.*/ + uint32_t discarded_values; /**< Number of mainfilter results,discarded before integration starts.Bitfields \a NVALDIS of \a IWCTR.*/ + uint32_t stop_condition; /**< Integrator stop condition. Can take a value of XMC_DSD_CH_INTEGRATOR_STOP_t.Bitfields \a IWS of \a IWCTR.*/ + uint32_t counted_values; /**< Number of mainfilter results, integrated to a integrator result.Bitfields \a NVALINT of \a IWCTR.*/ + +} XMC_DSD_CH_INTEGRATOR_CONFIG_t; + +/** + * DSD timestamp saves result, filter counter register and integrator count register. + * Note: Trigger source for timestamp and integrator trigger are shared. + * DSD Filter is mandatory to use this block. + */ +typedef struct XMC_DSD_CH_TIMESTAMP_CONFIG +{ + union + { + struct + { + uint32_t :10; + uint32_t trigger_mode:2; /**< This parameter can take a value of XMC_DSD_CH_TIMESTAMP_TRIGGER_t */ + uint32_t trigger_source: 3; /**< This parameter can take a value of XMC_DSD_CH_TRIGGER_SOURCE_t */ + uint32_t : 17; + }; + uint32_t timestamp_conf; + }; +} XMC_DSD_CH_TIMESTAMP_CONFIG_t; + +/** + * DSD auxiliary Filter is used as fast filter to detect overvoltage or current by defining the boundaries. + */ +typedef struct XMC_DSD_CH_AUX_FILTER_CONFIG +{ + union + { + struct + { + uint32_t : 8; /**< This parameter can be in range of 4 - 256[dec] */ + uint32_t filter_type : 2; /**< This parameter can take a value of XMC_DSD_CH_FILTER_TYPE_t */ + uint32_t result_event_type : 4; /**< Result event for aux filter and the event select configuration. + Use enum XMC_DSD_CH_AUX_EVENT_t */ + uint32_t enable_integrator_coupling : 1; /**< Only enable AUX filter when Integrator is enabled*/ + uint32_t : 17; + }; + uint32_t aux_filter_conf; + }; + union + { + struct + { + uint32_t lower_boundary : 16; /**< This parameter can take a value of int16_t */ + uint32_t upper_boundary : 16; /**< This parameter can take a value of int16_t */ + }; + uint32_t boundary_conf; + }; + + uint32_t decimation_factor; /**< This parameter can be in range of 4 - 256[dec]*/ + +} XMC_DSD_CH_AUX_FILTER_CONFIG_t; + + +/** + * DSD Rectify. + * Note: DSD Filter and integrator is mandatory to use this block. + */ +typedef struct XMC_DSD_CH_RECTIFY_CONFIG +{ + union + { + struct + { + uint32_t :4; + uint32_t sign_source: 2; /**< Can take a value of XMC_DSD_CH_SIGN_SOURCE_t.Bitfields \a SSRC of \a RECTCFG.*/ + uint32_t :26; + }; + uint32_t rectify_config; /**< Rectification configuration register(\a RECTCFG)*/ + }; + + uint8_t delay; + uint8_t half_cycle; + +} XMC_DSD_CH_RECTIFY_CONFIG_t; + + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +/** + * DSD Enable Channel + */ +typedef struct XMC_DSD_CONFIG +{ + XMC_DSD_CH_FILTER_CONFIG_t *const filter; /**< Pointer to the filter configuration */ + XMC_DSD_CH_INTEGRATOR_CONFIG_t *const integrator; /**< Pointer to the integrator configuration*/ + XMC_DSD_CH_TIMESTAMP_CONFIG_t *const timestamp; /**< Pointer to the time stamp configuration*/ + XMC_DSD_CH_AUX_FILTER_CONFIG_t *const aux; /**< Pointer to the aux_filter configuration*/ + XMC_DSD_CH_RECTIFY_CONFIG_t *const rectify; /**< Pointer to the rectify configuration*/ +} XMC_DSD_CH_CONFIG_t; + + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * De-asserts the DSD module from reset.\n + * Configures \a PRCLR0 register's \a DSDRS bit field. + * If running on XMC44/XMC48 device then it will ungate the peripheral clock. + * + * \parNote
+ * It is internally called by XMC_DSD_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_Disable(),XMC_DSD_Init() \n\n\n + */ +void XMC_DSD_Enable(XMC_DSD_t *const dsd); + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * Asserts the DSD module into reset.\n + * Configures \a PRSET0 register's \a DSDRS bit field. + * If running on XMC44/XMC48 device then it will gate the peripheral clock. + * + * \parRelated APIs:
+ * XMC_DSD_Enable()\n\n\n + */ +void XMC_DSD_Disable(XMC_DSD_t *const dsd); +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * Enable the module clock and internal module clock for DSD.\n + * Configures bit field \a MCSEL of register \a GLOBCFG and bit field \a DISR of register \a CLC. + * + * \parNote
+ * It is internally called by XMC_DSD_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_DisableClock(),XMC_DSD_Init() \n\n\n + */ +void XMC_DSD_EnableClock(XMC_DSD_t *const dsd); +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * Stop the module clock and disable internal module clock for DSD.\n + * Configures bit field \a MCSEL of register \a GLOBCFG and bit field \a DISR of register \a CLC. + * + * \parRelated APIs:
+ * XMC_DSD_DisableClock()\n\n\n + */ +void XMC_DSD_DisableClock(XMC_DSD_t *const dsd); +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return bool Return 1 if success else 0. + * + * \parDescription
+ * Find out if the DSD reset is asserted.\n + * Read \a PRSTAT0 register's \a DSDRS bit field.\n\n\n + */ +bool XMC_DSD_IsEnabled(XMC_DSD_t *const dsd); + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * Enable the DSD module and clock.\n + * + * \parNote
+ * This is the first API which application must invoke to configure DSD. + * + * \parRelated APIs:
+ * XMC_DSD_Enable(),XMC_DSD_EnableClock()\n\n\n + */ +void XMC_DSD_Init(XMC_DSD_t *const dsd); +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_TIMESTAMP_CONFIG_t + * @return None + * + * \parDescription
+ * Initialize timestamp mode of DSD module with \a init.\n + * Configures bits \a TRSEL and \a TSTRMODE of register \a DICFG . + * + * \parNote
+ * Trigger source for timestamp and integrator are shared. + * It is internally called by XMC_DSD_CH_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_CH_Init()\n\n\n +*/ +void XMC_DSD_CH_Timestamp_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_TIMESTAMP_CONFIG_t *const init); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_CONFIG_t + * @return XMC_DSD_STATUS_t if success Returns @ref XMC_DSD_STATUS_OK + * else return @ref XMC_DSD_STATUS_ERROR. + * + * \parDescription
+ * Initialize main filter,auxiliary filter,integrator, rectifier and timestamp of DSD module with \a init.\n + * Internally this API invoke main filter, auxiliary filter, integrator, rectifier and timestamp init API. + * + * \parRelated APIs:
+ * XMC_DSD_CH_MainFilter_Init(),XMC_DSD_CH_AuxFilter_Init(),XMC_DSD_CH_Integrator_Init(), + * XMC_DSD_CH_Rectify_Init(),XMC_DSD_CH_Timestamp_Init()\n\n\n +*/ +XMC_DSD_STATUS_t XMC_DSD_CH_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_CONFIG_t *const init); + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param channel Channel run control bit register value + * @return None + * + * \parDescription
+ * Start demodulator channel by enabling run control bit. + * Multiple channel can be start at a time. + * For an example: To start all four channel, call this function as + * XMC_DSD_Start(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1|XMC_DSD_CH_ID_2|XMC_DSD_CH_ID_3)); + * + * \parNote
+ * All filter blocks are cleared when CHxRUN is set. + * + * \parRelated APIs:
+ * XMC_DSD_Stop(),XMC_DSD_IsChannelStarted()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_Start(XMC_DSD_t *const dsd, const uint32_t channel) +{ + XMC_ASSERT("XMC_DSD_Start:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->GLOBRC |= channel; +} + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t\n + * @param channel Channel run control bit register value\n + * @return None\n + * + * \parDescription
+ * Stop demodulator channel by resetting run control bit. + * Multiple channel can be stop at a time. + * For an example: To stop all four channel, call this function as + * XMC_DSD_Stop(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1|XMC_DSD_CH_ID_2|XMC_DSD_CH_ID_3)); + * + * + * \parRelated APIs:
+ * XMC_DSD_Start(),XMC_DSD_IsChannelStarted()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_Stop(XMC_DSD_t *const dsd, const uint32_t channel) +{ + XMC_ASSERT("XMC_DSD_Stop:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->GLOBRC &= (uint32_t) ~channel; +} + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t\n + * @param channel Channel run control bit register value of type @ref XMC_DSD_CH_ID_t\n + * @return bool Return 1 if started else 0.\n + * + * \parDescription
+ * Find out if particular demodulator channel is started or not.\n + * + * \parRelated APIs:
+ * XMC_DSD_Start(),XMC_DSD_Stop()\n\n\n + */ +__STATIC_INLINE bool XMC_DSD_IsChannelStarted(XMC_DSD_t *const dsd, const XMC_DSD_CH_ID_t channel) +{ + bool status; + XMC_ASSERT("XMC_DSD_IsChannelStarted:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + if (dsd->GLOBRC & (uint32_t)channel) + { + status = true; + } + else + { + status = false; + } + return (status); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param dsd_Result pointer point to the address of 16 bit variable + * @return None + * + * \parDescription:
+ * Returns the result of most recent conversion associated with this channel.\n + * A call to this API would access the register bit field \a RESMx.RESULT (x = 0 - 3). + * + * \parRelated APIs:
+ * XMC_DSD_CH_GetResult_TS()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_CH_GetResult(XMC_DSD_CH_t *const channel, int16_t* dsd_Result) +{ + uint16_t result; + result = (uint16_t)((uint32_t)channel->RESM & DSD_CH_RESM_RESULT_Msk); + *dsd_Result = (int16_t)result; +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t\n + * @param dsd_Result pointer point to the address of 16 bit variable holds result value\n + * @param dsd_filter_loop pointer point to the address of 8 bit variable holds decimation counter value\n + * @param dsd_integration_loop pointer point to the address of 8 bit integration counter variable holds value\n + * @return None\n + * + * \parDescription:
+ * API to get the result of the last conversion associated with this channel with + * CIC filter decimation counter and number of values counted.\n + * A call to this API would access the register bit field \a TSTMPx.RESULT \a TSTMPx.CFMDCNT and \a TSTMPx.NVALCNT where (x = 0 - 3). + * + * \parRelated APIs:
+ * XMC_DSD_CH_GetResult(),XMC_DSD_CH_GetResult_TS_Time()\n\n\n + */ +void XMC_DSD_CH_GetResult_TS( + XMC_DSD_CH_t *const channel, + int16_t* dsd_Result, + uint8_t* dsd_filter_loop, + uint8_t* dsd_integration_loop); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t\n + * @param dsd_Result pointer point to the address of 16 bit variable holds result value\n + * @param time pointer point to the address of 32 bit variable holds the time\n + * @return None + * + * \parDescription:
+ * API to get the result of the last conversion with the time, associated with this channel.\n + * + * \parRelated APIs:
+ * XMC_DSD_CH_GetResult(),XMC_DSD_CH_GetResult_TS()\n\n\n + */ +void XMC_DSD_CH_GetResult_TS_Time(XMC_DSD_CH_t *const channel, int16_t* dsd_Result, uint32_t* time); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param dsd_Result pointer point to the address of 16 bit variable + * @return None + * + * \parDescription:
+ * Returns the most recent conversion result values of the auxiliary filter associated with this channel.\n + * A call to this API would access the register bit field \a RESAx.RESULT (x = 0 - 3). + * + * \parRelated APIs:
+ * XMC_DSD_CH_GetResult_TS()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_CH_GetResult_AUX(XMC_DSD_CH_t *const channel, int16_t* dsd_Result) +{ + uint16_t result; + result = (uint16_t) (channel->RESA & DSD_CH_RESA_RESULT_Msk); + *dsd_Result = (int16_t) (result); +} + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_GENERATOR_CONFIG_t + * @return None + * + * \parDescription
+ * This API initialize generator module with \a init, to generate a wave for a resolver. + * Three types of waveforms can be generated: Rectangle, Triangle and Sine. + * +*/ +void XMC_DSD_Generator_Init(XMC_DSD_t *const dsd, const XMC_DSD_GENERATOR_CONFIG_t *const init); + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param config Pointer to an instance of data structure of type @ref XMC_DSD_GENERATOR_CONFIG_t + * @return None + * + * \parDescription
+ * Start carrier generator by configuring operating mode. + * Configures bit field \a CGMOD of register \a CGCFG. + * + * + * \parRelated APIs:
+ * XMC_DSD_Generator_Stop()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_Generator_Start(XMC_DSD_t *const dsd, const XMC_DSD_GENERATOR_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_DSD_Generator_Start:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_ASSERT("XMC_DSD_Generator_Start:NULL Pointer", (config != (XMC_DSD_GENERATOR_CONFIG_t *)NULL) ); + dsd->CGCFG |= config->mode; +} + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * Stop carrier generator by configuring operating mode. + * Reset bit field \a CGMOD of register \a CGCFG. + * + * \parNote
+ * Stopping the carrier generator terminates the PWM output after completion of the current period. + * + * \parRelated APIs:
+ * XMC_DSD_Generator_Start()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_Generator_Stop(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_Generator_Stop:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->CGCFG &= ~((uint32_t)DSD_CGCFG_CGMOD_Msk); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_FILTER_CONFIG_t + * @return None + * + * \parDescription
+ * This API initialize main filter module with \a init. + * The filter demodulates the incoming bit stream from the delta sigma modulator to a 16 bit result. + * + * + * \parNote
+ * It is internally called by XMC_DSD_CH_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_CH_Init()\n\n\n +*/ +void XMC_DSD_CH_MainFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_FILTER_CONFIG_t *const init); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param offset Signed Offset value to be set + * @return None + * + * \parDescription
+ * API set the signed offset value for this channel. + * This offset value is subtracted from each result before being written to the corresponding result register \a RESMx. + * + * \parNote
+ * The offset value is measured for each channel separately. + * +*/ +__STATIC_INLINE void XMC_DSD_CH_MainFilter_SetOffset(XMC_DSD_CH_t *const channel, const int16_t offset) +{ + XMC_ASSERT("XMC_DSD_CH_MainFilter_SetOffset:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->OFFM = (uint32_t)offset; +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @return None + * + * \parDescription
+ * This API enable the service request generation for result of this channel. + * Result events are generated at the output rate of the configured main filter chain. + * Configure bit field \a SRGM of register \a FCFGC + * +*/ +__STATIC_INLINE void XMC_DSD_CH_MainFilter_EnableEvent(XMC_DSD_CH_t *const channel) +{ + XMC_ASSERT("XMC_DSD_CH_MainFilter_EnableEvent:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->FCFGC |= (uint32_t)DSD_CH_FCFGC_SRGM_Msk; +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @return None + * + * \parDescription
+ * This API disable the service request generation for result of this channel. + * Configure bit field \a SRGM of register \a FCFGC + * +*/ +__STATIC_INLINE void XMC_DSD_CH_MainFilter_DisableEvent(XMC_DSD_CH_t *const channel) +{ + XMC_ASSERT("XMC_DSD_CH_MainFilter_DisableEvent:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->FCFGC &= ~((uint32_t)DSD_CH_FCFGC_SRGM_Msk); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_AUX_FILTER_CONFIG_t + * @return None + * + * \parDescription
+ * This API initialize auxiliary filter module with \a init. The auxiliary Filter is mainly used as fast filter.\n + * Adding the auxiliary filter to the system structure helps by defining the boundaries and filter configurations.\n + * + * + * \parNote
+ * It is internally called by XMC_DSD_CH_Init().\n + * + * \parRelated APIs:
+ * XMC_DSD_CH_Init()\n\n\n +*/ +void XMC_DSD_CH_AuxFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_AUX_FILTER_CONFIG_t *const init); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param lower_boundary lower boundary value for limit checking + * @param upper_boundary upper boundary value for limit checking + * @return None + * + * \parDescription
+ * Invoke this API, to set the lower and upper boundary for limit checking for this channel. + * This (two’s complement) value is compared to the results of the parallel filter. + * Configure bit fields \a BOUNDARYU and \a BOUNDARYL of register \a BOUNDSEL. + * + * \parNote
+ * Lower and upper boundaries are internally configured by function XMC_DSD_CH_AuxFilter_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_CH_AuxFilter_Init()\n\n\n +*/ +__STATIC_INLINE void XMC_DSD_CH_AuxFilter_SetBoundary( + XMC_DSD_CH_t *const channel, + const int16_t lower_boundary, + const int16_t upper_boundary) +{ + XMC_ASSERT("XMC_DSD_CH_AuxFilter_SetBoundary:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->BOUNDSEL = (((uint32_t)upper_boundary << (uint32_t)DSD_CH_BOUNDSEL_BOUNDARYU_Pos) + | ((uint32_t)lower_boundary & (uint32_t)DSD_CH_BOUNDSEL_BOUNDARYL_Msk)); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param event to select the type of event which will be enabled of type @ref XMC_DSD_CH_AUX_EVENT_t + * @return None + * + * \parDescription
+ * This API enable the service request generation for this channel. + * Result events are generated at the output rate of the configured auxiliary filter chain. + * Configure bit field \a SRGA and ESEL of register \a FCFGA + * +*/ +__STATIC_INLINE void XMC_DSD_CH_AuxFilter_EnableEvent(XMC_DSD_CH_t *const channel, XMC_DSD_CH_AUX_EVENT_t event) +{ + XMC_ASSERT("XMC_DSD_CH_AuxFilter_EnableEvent:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->FCFGA &= ~((uint32_t)DSD_CH_FCFGA_ESEL_Msk|(uint32_t)DSD_CH_FCFGA_SRGA_Msk); + channel->FCFGA |= ((uint32_t)event << DSD_CH_FCFGA_SRGA_Pos); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @return None + * + * \parDescription
+ * This API disable the auxiliary filter service request generation for this channel. + * Clear the bit fields \a SRGA and ESEL of register \a FCFGA. + * +*/ +__STATIC_INLINE void XMC_DSD_CH_AuxFilter_DisableEvent(XMC_DSD_CH_t *const channel) +{ + XMC_ASSERT("XMC_DSD_CH_AuxFilter_DisableEvent:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->FCFGA &= ~((uint32_t)DSD_CH_FCFGA_ESEL_Msk|(uint32_t)DSD_CH_FCFGA_SRGA_Msk); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_INTEGRATOR_CONFIG_t + * @return None + * + * \parDescription
+ * Initialize integrator of DSD module.The integrator is mainly used for resolver feedback but can also be used for high accurate measurement. + * This API configures number of integration loops, number of results are discarded before integration starts, integrator stop condition, + * number of integrator loop to get integration result and trigger mode. + * + * \parNote
+ * Trigger source for timestamp and integrator are shared. + * It is internally called by XMC_DSD_CH_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_CH_Init()\n\n\n +*/ +void XMC_DSD_CH_Integrator_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_INTEGRATOR_CONFIG_t *const init); +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_RECTIFY_CONFIG_t + * @return None + * + * \parDescription
+ * Initialize rectification for this channel. + * In a resolver feedback system, rectifier is used to rectify the result from the integrator. + * Configure bit field \a RFEN and \a SSRC of register \a RECTCFG. Also configure sign delay + * value for positive halfwave(\a SDPOS) and negative halfwave(\a SDNEG). + * \parNote
+ * For the operational capability of rectifier the filter and the integrator is mandatory. + * It is internally called by XMC_DSD_CH_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_CH_Init()\n\n\n +*/ +void XMC_DSD_CH_Rectify_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_RECTIFY_CONFIG_t *const init); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param delay Captured value + * @return uint8_t + * + * \parDescription
+ * This API, capture sign delay value for DSD channel. + * Captured value indicates the values counted between the begin of the positive + * halfwave of the carrier signal and the first received positive value. + * Read bit field \a SDCAP of register \a CGSYNC + * +*/ +__STATIC_INLINE void XMC_DSD_CH_GetRectifyDelay(XMC_DSD_CH_t *const channel, uint8_t* delay) +{ + XMC_ASSERT("XMC_DSD_CH_GetRectifyDelay:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + *delay = (uint8_t)((channel->CGSYNC & DSD_CH_CGSYNC_SDCAP_Msk ) >> DSD_CH_CGSYNC_SDCAP_Pos); +} +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param channel_id Channel number register value of type @ref XMC_DSD_CH_ID_t + * @return None + * + * \parDescription
+ * Set the result event flag and trigger the corresponding event.\n + * Set bit fields \a RESEVx of register \a EVFLAG.Clearing these bits has no effect. + * + * \parNote
+ * API call for channel-0 : XMC_DSD_SetResultEventFlag(DSD,(uint32_t)XMC_DSD_CH_ID_0); + * API call for channel-0 and 1: XMC_DSD_SetResultEventFlag(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1)); + * + * \parRelated APIs:
+ * XMC_DSD_ClearResultEventFlag()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_SetResultEventFlag(XMC_DSD_t *const dsd, const uint32_t channel_id) +{ + XMC_ASSERT("XMC_DSD_SetResultEventFlag:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->EVFLAG = channel_id; +} +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param channel_id Channel number register value of type @ref XMC_DSD_CH_ID_t + * @return None + * + * \parDescription
+ * Clear the result event flag.\n + * Set bit fields \a RESECx of register \a EVFLAGCLR.Clearing these bits has no effect. + * + * \parNote
+ * API call for channel-0 : XMC_DSD_ClearResultEventFlag(DSD,(uint32_t)XMC_DSD_CH_ID_0); + * API call for channel-0 and 1: XMC_DSD_ClearResultEventFlag(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1)); + * + * \parRelated APIs:
+ * XMC_DSD_SetResultEventFlag()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_ClearResultEventFlag(XMC_DSD_t *const dsd, const uint32_t channel_id) +{ + XMC_ASSERT("XMC_DSD_ClearResultEventFlag:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->EVFLAGCLR = channel_id; +} +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param channel_id Channel number register value of type @ref XMC_DSD_CH_ID_t + * @return None + * + * \parDescription
+ * Set the alarm event flag.\n + * Set bit fields \a ALEVx of register \a EVFLAG.Clearing these bits has no effect. + * + * \parNote
+ * API call for channel-0 : XMC_DSD_SetAlarmEventFlag(DSD,(uint32_t)XMC_DSD_CH_ID_0); + * API call for channel-0 and 1: XMC_DSD_SetAlarmEventFlag(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1)); + * + * \parRelated APIs:
+ * XMC_DSD_ClearAlarmEventFlag()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_SetAlarmEventFlag(XMC_DSD_t *const dsd, const uint32_t channel_id) +{ + XMC_ASSERT("XMC_DSD_SetAlarmEventFlag:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->EVFLAG = (channel_id<< DSD_EVFLAGCLR_ALEC0_Pos); +} +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param channel_id Channel number register value of type @ref XMC_DSD_CH_ID_t + * @return None + * + * \parDescription
+ * Clear the result event flag.\n + * Set bit fields \a ALECx of register \a EVFLAGCLR.Clearing these bits has no effect. + * + * \parNote
+ * API call for channel-0 : XMC_DSD_ClearResultEventFlag(DSD,(uint32_t)XMC_DSD_CH_ID_0); + * API call for channel-0 and 1: XMC_DSD_ClearResultEventFlag(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1)); + * + * \parRelated APIs:
+ * XMC_DSD_SetAlarmEventFlag()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_ClearAlarmEventFlag(XMC_DSD_t *const dsd, const uint32_t channel_id) +{ + XMC_ASSERT("XMC_DSD_ClearAlarmEventFlag:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->EVFLAGCLR = (channel_id< +#if defined (EBU) +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup EBU + * @brief External Bus Unit (EBU) driver for the XMC4500 microcontroller + * + * The External Bus Unit (EBU) controls the transactions between external memories or + * peripheral units, and the internal memories and peripheral units. Several external + * device configurations are supported; e.g. Asynchronous static memories, SDRAM + * and various flash memory types. It supports multiple programmable address regions. + * + * The EBU low level driver provides functions to configure and initialize the EBU + * hardware peripheral. + * @{ + */ + +/********************************************************************************************************************** + * MACROS +**********************************************************************************************************************/ + +/** + * A convenient symbol for the EBU peripheral base address + */ +#if defined (EBU) +# define XMC_EBU ((XMC_EBU_t *)EBU_BASE) +#else +# error 'EBU' base peripheral pointer not defined +#endif + + +/* + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_EBU_CHECK_MODULE_PTR(p) ((p) == XMC_EBU) + +/********************************************************************************************************************** + * ENUMS +**********************************************************************************************************************/ + +/** + * Status return values for EBU low level driver + */ +typedef enum XMC_EBU_STATUS +{ + XMC_EBU_STATUS_OK = 0U, /**< Operation successful */ + XMC_EBU_STATUS_BUSY = 1U, /**< Busy with a previous request */ + XMC_EBU_STATUS_ERROR = 3U /**< Operation unsuccessful */ +} XMC_EBU_STATUS_t; + +/** + * EBU clock divide ratio + */ +typedef enum XMC_EBU_CLOCK_DIVIDE_RATIO +{ + XMC_EBU_CLOCK_DIVIDED_BY_1 = 0U, /**< Clock divided by 1 */ + XMC_EBU_CLOCK_DIVIDED_BY_2 = 1U, /**< Clock divided by 2 */ + XMC_EBU_CLOCK_DIVIDED_BY_3 = 2U, /**< Clock divided by 3 */ + XMC_EBU_CLOCK_DIVIDED_BY_4 = 3U /**< Clock divided by 4 */ +} XMC_EBU_CLOCK_DIVIDE_RATIO_t; + +/** + * EBU DIV2 clocking mode + */ +typedef enum XMC_EBU_DIV2_CLK_MODE +{ + XMC_EBU_DIV2_CLK_MODE_OFF = 0U, /**< Divider 2 clock mode OFF */ + XMC_EBU_DIV2_CLK_MODE_ON = 1U /**< Divider 2 clock mode ON */ +} XMC_EBU_DIV2_CLK_MODE_t; + +/** + * EBU clocking mode + */ +typedef enum XMC_EBU_CLK_MODE +{ + XMC_EBU_CLK_MODE_ASYNCHRONOUS_TO_AHB = 0U, /**< EBU is using standard clocking mode */ + XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU = 1U /**< EBU is running at AHB bus clock divided by 2 */ +} XMC_EBU_CLK_MODE_t; + +/** + * EBU arbitration mode + */ +typedef enum XMC_EBU_ARB_MODE +{ + XMC_EBU_ARB_MODE_NOT_SELECTED = 0U, /**< No Bus arbitration mode selected */ + XMC_EBU_ARB_MODE_ARBITER_MODE = 1U, /**< Arbiter Mode arbitration mode selected */ + XMC_EBU_ARB_MODE_PARTICIPANT_MODE = 2U, /**< Participant arbitration mode selected */ + XMC_EBU_ARB_MODE_SOLE_MASTER_MODE = 3U /**< Sole Master arbitration mode selected */ +} XMC_EBU_ARB_MODE_t; + +/** + * EBU ALE mode + */ +typedef enum XMC_EBU_ALE_MODE +{ + XMC_EBU_ALE_OUTPUT_IS_INV_ADV = 0U, /**< Output is ADV */ + XMC_EBU_ALE_OUTPUT_IS_ALE = 1U /**< Output is ALE */ +} XMC_EBU_ALE_MODE_t; + +/** + * EBU clock status + */ +typedef enum XMC_EBU_CLK_STATUS +{ + XMC_EBU_CLK_STATUS_DISABLE_BIT = EBU_CLC_DISS_Msk, /**< EBU Disable Status Bit */ + XMC_EBU_CLK_STATUS_MODE = EBU_CLC_SYNCACK_Msk, /**< EBU Clocking Mode Status */ + XMC_EBU_CLK_STATUS_DIV2_MODE = EBU_CLC_DIV2ACK_Msk, /**< DIV2 Clocking Mode Status */ + XMC_EBU_CLK_STATUS_DIV_RATIO = EBU_CLC_EBUDIVACK_Msk /**< EBU Clock Divide Ratio Status */ +} XMC_EBU_CLK_STATUS_t; + +/** + * EBU address selection + */ +typedef enum XMC_EBU_ADDRESS_SELECT +{ + XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE = EBU_ADDRSEL0_REGENAB_Msk, /**< Memory Region Enable */ + XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE = EBU_ADDRSEL0_ALTENAB_Msk, /**< Alternate Region Enable */ + XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_WRITE_PROTECT = EBU_ADDRSEL0_WPROT_Msk /**< Memory Region Write Protect */ +} XMC_EBU_ADDRESS_SELECT_t; + +/** + * EBU bus write configuration status + */ +typedef enum XMC_EBU_BUSWCON_SELECT +{ + XMC_EBU_BUSWCON_SELECT_NAN_WORKAROUND = EBU_BUSWCON0_NAA_Msk, /**< Enable flash non-array access workaround */ + XMC_EBU_BUSWCON_SELECT_DEVICE_ADDRESSING_MODE = EBU_BUSWCON0_PORTW_Msk, /**< Device Addressing Mode */ +} XMC_EBU_BUSWCON_SELECT_t; + +/** + * EBU burst length for synchronous burst + */ +typedef enum XMC_EBU_BURST_LENGTH_SYNC +{ + XMC_EBU_BURST_LENGTH_SYNC_1_DATA_ACCESS = 0U, /**< 1 data access (default after reset) */ + XMC_EBU_BURST_LENGTH_SYNC_2_DATA_ACCESSES = 1U, /**< 2 data access */ + XMC_EBU_BURST_LENGTH_SYNC_4_DATA_ACCESSES = 2U, /**< 3 data access */ + XMC_EBU_BURST_LENGTH_SYNC_8_DATA_ACCESSES = 3U, /**< 4 data access */ +} XMC_EBU_BURST_LENGTH_SYNC_t; + +/** + * EBU burst buffer mode + */ +typedef enum XMC_EBU_BURST_BUFFER_SYNC_MODE +{ + XMC_EBU_BURST_BUFFER_SYNC_LENGTH_SYNC_ENABLE = 0U, /**< Burst buffer length defined by value in FETBLEN */ + XMC_EBU_BURST_BUFFER_SYNC_SINGLE_MODE = 1U /**< All data required for transaction (single burst transfer) */ +} XMC_EBU_BURST_BUFFER_SYNC_MODE_t; + +/** + * Read single stage synchronization + */ +typedef enum XMC_EBU_READ_STAGES_SYNC +{ + XMC_EBU_READ_STAGES_SYNC_TWO = 0U, /**< Two stages of synchronization used (maximum margin) */ + XMC_EBU_READ_STAGES_SYNC_ONE = 1U /**< One stage of synchronization used (minimum latency) */ +} XMC_EBU_READ_STAGES_SYNC_t; + +/** + * EBU burst flash clock feedback enable/disable + */ +typedef enum XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK +{ + XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_DISABLE = 0U, /**< BFCLK feedback not used */ + XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE = 1U /**< BFCLK feedback used */ +} XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_t; + +/** + * EBU burst flash clock mode select + */ +typedef enum XMC_EBU_BURST_FLASH_CLOCK_MODE +{ + XMC_EBU_BURST_FLASH_CLOCK_MODE_RUN_CONTINUOSLY = 0U, /**< Burst flash clock runs continuously */ + XMC_EBU_BURST_FLASH_CLOCK_MODE_DISABLED_BETWEEN_ACCESSES = 1U /**< Burst flash clock disabled */ +} XMC_EBU_BURST_FLASH_CLOCK_MODE_t; + +/** + * EBU flash non-array access + */ +typedef enum XMC_EBU_FLASH_NON_ARRAY_ACCESS +{ + XMC_EBU_FLASH_NON_ARRAY_ACCESS_DISNABLE = 0U, /**< Disable non-array access */ + XMC_EBU_FLASH_NON_ARRAY_ACCESS_ENABLE = 1U /**< Enable non-array access */ +} XMC_EBU_FLASH_NON_ARRAY_ACCESS_t; + +/** + * EBU early chip select for synchronous burst + */ +typedef enum XMC_EBU_EARLY_CHIP_SELECT_SYNC_BURST +{ + XMC_EBU_EARLY_CHIP_SELECT_DELAYED = 0U, /**< Chip select delayed */ + XMC_EBU_EARLY_CHIP_SELECT_NOT_DELAYED = 1U /**< Chip select not delayed */ +} XMC_EBU_EARLY_CHIP_SELECT_SYNC_BURST_t; + +/** + * EBU early burst signal enable for synchronous burst + */ +typedef enum XMC_EBU_BURST_SIGNAL_SYNC_BURST +{ + XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_DELAYED = 0U, /**< Chip select delayed */ + XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_NOT_DELAYED = 1U /**< Chip select not delayed */ +} XMC_EBU_BURST_SIGNAL_SYNC_BURST_t; + +/** + * EBU burst address wrapping + */ +typedef enum XMC_EBU_BURST_ADDRESS_WRAPPING +{ + XMC_EBU_BURST_ADDRESS_WRAPPING_DISABLED = 0U, /**< Automatically re-aligns any non-aligned synchronous burst access */ + XMC_EBU_BURST_ADDRESS_WRAPPING_ENABLED = 1U /**< Starts any burst access at address specified by the AHB request */ +} XMC_EBU_BURST_ADDRESS_WRAPPING_t; + +/** + * EBU reversed polarity at WAIT + */ +typedef enum XMC_EBU_WAIT_SIGNAL_POLARITY +{ + XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_LOW = 0U, /**< OFF, input at WAIT pin is active low */ + XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_HIGH = 1U /**< Polarity reversed, input at WAIT pin is active high */ +} XMC_EBU_WAIT_SIGNAL_POLARITY_t; + +/** + * EBU byte control signal control + */ +typedef enum XMC_EBU_BYTE_CONTROL +{ + XMC_EBU_BYTE_CONTROL_FOLLOWS_CHIP_SELECT_TIMMING = 0U, /**< Control signals follow chip select timing */ + XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING = 1U, /**< Control signals follow control signal timing */ + XMC_EBU_BYTE_CONTROL_FOLLOWS_WRITE_ENABLE_SIGNAL_TIMMING = 2U /**< Control signals follow write enable timing */ +} XMC_EBU_BYTE_CONTROL_t; + +/** + * EBU device addressing mode + */ +typedef enum XMC_EBU_DEVICE_ADDRESSING_MODE +{ + XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS = 1U, /**< Address will only be driven onto AD[15:0] */ + XMC_EBU_DEVICE_ADDRESSING_MODE_TWIN_16_BITS_MULTIPLEXED = 2U, /**< Lower 16b will be driven onto A[15:0] & AD[15:0] */ + XMC_EBU_DEVICE_ADDRESSING_MODE_32_BITS_MULTIPLEXED = 3U /**< Full address driven onto A[15:0] & AD[15:0] */ +} XMC_EBU_DEVICE_ADDRESSING_MODE_t; + +/** + * EBU external wait control + */ +typedef enum XMC_EBU_WAIT_CONTROL +{ + XMC_EBU_WAIT_CONTROL_OFF = 0U, /**< Default after reset; Wait control off */ + XMC_EBU_WAIT_CONTROL_SYNC_EARLY_WAIT_ASYNC_ASYNC_INPUT_AT_WAIT = 1U, /**< SYNC: Wait for page load (Early WAIT); + ASYNC: Asynchronous input at WAIT */ + XMC_EBU_WAIT_CONTROL_SYNC_WAIT_WITH_DATA_ASYNC_SYNC_INPUT_AT_WAIT = 2U, /**< SYNC: Wait for page load (WAIT with data); + ASYNC: Synchronous input at WAIT; */ + XMC_EBU_WAIT_CONTROL_SYNC_ABORT_AND_RETRY_ACCESS = 3U /**< SYNC: Abort and retry access; */ +} XMC_EBU_WAIT_CONTROL_t; + +/** + * EBU asynchronous address phase + */ +typedef enum XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE +{ + XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_CLOCK_ENABLED_AT_BEGINNING_OF_ACCESS = 0U, /**< Enabled at beginning of access */ + XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_CLOCK_ENABLED_AFTER_ADDRESS_PHASE = 1U /**< Enabled after address phase */ +} XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_t; + +/** + * EBU device type for region + */ +typedef enum XMC_EBU_DEVICE_TYPE +{ + XMC_EBU_DEVICE_TYPE_MUXED_ASYNCHRONOUS_TYPE = 0U, /**< Device type muxed asynchronous */ + XMC_EBU_DEVICE_TYPE_MUXED_BURST_TYPE = 1U, /**< Device type muxed burst */ + XMC_EBU_DEVICE_TYPE_NAND_FLASH = 2U, /**< Device type NAND flash */ + XMC_EBU_DEVICE_TYPE_MUXED_CELLULAR_RAM = 3U, /**< Device type muxed cellular RAM */ + XMC_EBU_DEVICE_TYPE_DEMUXED_ASYNCHRONOUS_TYPE = 4U, /**< Device type de-muxed asynchronous */ + XMC_EBU_DEVICE_TYPE_DEMUXED_BURST_TYPE = 5U, /**< Device type de-muxed burst */ + XMC_EBU_DEVICE_TYPE_DEMUXED_PAGE_MODE = 6U, /**< Device type de-muxed page mode */ + XMC_EBU_DEVICE_TYPE_DEMUXED_CELLULAR_RAM = 7U, /**< Device type de-muxed cellular RAM */ + XMC_EBU_DEVICE_TYPE_SDRAM = 8U /**< Device type SDRAM */ +} XMC_EBU_DEVICE_TYPE_t; + +/** + * EBU lock chip select + */ +typedef enum XMC_EBU_LOCK_CHIP_SELECT +{ + XMC_EBU_LOCK_CHIP_SELECT_DISABLED = 0U, /**< Chip select cannot be locked */ + XMC_EBU_LOCK_CHIP_SELECT_ENABLED = 1U /**< Chip select automatically locked after a write operation */ +} XMC_EBU_LOCK_CHIP_SELECT_t; + +/** + * EBU Frequency of external clock at pin BFCLKO + */ +typedef enum XMC_EBU_FREQUENCY_EXT_CLK_PIN +{ + XMC_EBU_FREQ_EXT_CLK_PIN_EQUAL_TO_INT_CLK = 0U, /**< Equal to INT_CLK frequency */ + XMC_EBU_FREQ_EXT_CLK_PIN_HALF_OF_INT_CLK = 1U, /**< 1/2 of INT_CLK frequency */ + XMC_EBU_FREQ_EXT_CLK_PIN_THIRD_OF_INT_CLK = 2U, /**< 1/3 of INT_CLK frequency */ + XMC_EBU_FREQ_EXT_CLK_PIN_QUARTER_OF_INT_CLK = 3U /**< 1/4 of INT_CLK frequency */ +} XMC_EBU_FREQ_EXT_CLK_PIN_t; + +/** + * EBU extended data + */ +typedef enum XMC_EBU_EXT_DATA +{ + XMC_EBU_EXT_DATA_OUTPUT_EVERY_1_BFCLK_CYCLES = 0U, /**< External memory outputs data every BFCLK cycle */ + XMC_EBU_EXT_DATA_OUTPUT_EVERY_2_BFCLK_CYCLES = 1U, /**< External memory outputs data every two BFCLK cycles */ + XMC_EBU_EXT_DATA_OUTPUT_EVERY_4_BFCLK_CYCLES = 2U, /**< External memory outputs data every four BFCLK cycles */ + XMC_EBU_EXT_DATA_OUTPUT_EVERY_8_BFCLK_CYCLES = 3U /**< External memory outputs data every eight BFCLK cycles */ +} XMC_EBU_EXT_DATA_t; + +/** + * EBU SDRAM clock mode select + */ +typedef enum XMC_EBU_SDRAM_CLK_MODE +{ + XMC_EBU_SDRAM_CLK_MODE_CONTINUOUSLY_RUNS = 0U, /**< Clock continuously running */ + XMC_EBU_SDRAM_CLK_MODE_DISABLED_BETWEEN_ACCESSES = 1U /**< Clock disabled between accesses */ +} XMC_EBU_SDRAM_CLK_MODE_t; + +/** + * EBU power save mode used for gated clock mode + */ +typedef enum XMC_EBU_SDRAM_PWR_MODE +{ + XMC_EBU_SDRAM_PWR_MODE_PRECHARGE_BEFORE_CLK_STOP = 0U, /**< Precharge before clock stop */ + XMC_EBU_SDRAM_PWR_MODE_AUTO_PRECHARGE_BEFORE_CLK_STOP = 1U, /**< Auto-precharge before clock stop */ + XMC_EBU_SDRAM_PWR_MODE_ACTIVE_PWR_DOWN = 2U, /**< Active power down (stop clock without precharge) */ + XMC_EBU_SDRAM_PWR_MODE_CLK_STOP_PWR_DOWN = 3U /**< Clock stop power down */ +} XMC_EBU_SDRAM_PWR_MODE_t; + +/** + * EBU disable SDRAM clock output + */ +typedef enum XMC_EBU_SDRAM_CLK_OUTPUT +{ + XMC_EBU_SDRAM_CLK_OUTPUT_ENABLED = 0U, /**< Clock output enabled */ + XMC_EBU_SDRAM_CLK_OUTPUT_DISABLED = 1U /**< Clock output disabled */ +} XMC_EBU_SDRAM_CLK_OUTPUT_t; + +/** + * EBU mask for bank tag + */ +typedef enum XMC_EBU_SDRAM_MASK_FOR_BANKM_TAG +{ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_21_to_20 = 1U, /**< Mask for bank tag addresses 21 to 20 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_22_to_21 = 2U, /**< Mask for bank tag addresses 22 to 21 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_23_to_22 = 3U, /**< Mask for bank tag addresses 23 to 22 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_24_to_23 = 4U, /**< Mask for bank tag addresses 24 to 23 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_25_to_24 = 5U, /**< Mask for bank tag addresses 25 to 24 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_26_to_25 = 6U, /**< Mask for bank tag addresses 26 to 25 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_26 = 7U /**< Mask for bank tag addresses 26 */ +} XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_t; + +/** + * EBU Mask for row tag + */ +typedef enum XMC_EBU_SDRAM_MASK_FOR_ROW_TAG +{ + XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_9 = 1U, /**< Mask for row tag addresses 26 to 9 */ + XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_10 = 2U, /**< Mask for row tag addresses 26 to 10 */ + XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_11 = 3U, /**< Mask for row tag addresses 26 to 11 */ + XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_12 = 4U, /**< Mask for row tag addresses 26 to 12 */ + XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_13 = 5U /**< Mask for row tag addresses 26 to 13 */ +} XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_t; + +/** + * Number of address bits from bit 0 to be used for column address + */ +typedef enum XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS +{ + XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_8_to_0 = 1U, /**< Address [8:0] */ + XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_9_to_0 = 2U, /**< Address [9:0] */ + XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_10_to_0 = 3U /**< Address [10:0] */ +} XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_t; + +/** + * Number of clocks between a READ command and the availability of data + */ +typedef enum XMC_EBU_SDRAM_CAS_LATENCY +{ + XMC_EBU_SDRAM_CAS_LATENCY_2_CLKS = 2U, /**< 2 clocks between a READ command and the availability of data */ + XMC_EBU_SDRAM_CAS_LATENCY_3_CLKS = 3U /**< 3 clocks between a READ command and the availability of data */ +} XMC_EBU_SDRAM_CAS_LATENCY_t; + +/** + * Number of locations can be accessed with a single command + */ +typedef enum XMC_EBU_SDRAM_BURST_LENGTH +{ + XMC_EBU_SDRAM_BURST_LENGTH_1_LOCATION = 0U, /**< One location accessed with a single command */ + XMC_EBU_SDRAM_BURST_LENGTH_2_LOCATION = 1U, /**< Two location accessed with a single command */ + XMC_EBU_SDRAM_BURST_LENGTH_4_LOCATION = 2U, /**< Four location accessed with a single command */ + XMC_EBU_SDRAM_BURST_LENGTH_8_LOCATION = 3U, /**< Eight location accessed with a single command */ + XMC_EBU_SDRAM_BURST_LENGTH_16_LOCATION = 4U /**< Sixteen location accessed with a single command */ +} XMC_EBU_SDRAM_BURST_LENGTH_t; + +/** + * EBU SDRAM status + */ +typedef enum XMC_EBU_SDRAM_STATUS +{ + XMC_EBU_SDRAM_STATUS_RX_ERROR = EBU_SDRSTAT_SDERR_Msk, /**< Detected an error when returning read data */ + XMC_EBU_SDRAM_STATUS_BUSY = EBU_SDRSTAT_SDRMBUSY_Msk, /**< The status of power-up initialization sequence */ + XMC_EBU_SDRAM_STATUS_REFRESH_ERROR = EBU_SDRSTAT_REFERR_Msk /**< Failed previous refresh req collides with new req */ +} XMC_EBU_SDRAM_STATUS_t; + +/** + * SDRAM refresh status + */ +typedef enum XMC_EBU_SDRAM_RFRSH_STATUS +{ + XMC_EBU_SDRAM_RFRSH_STATUS_SELF_REFRESH_ENTRY_STATUS = EBU_SDRMREF_SELFRENST_Msk, /**< Self refresh entry command issue successful */ + XMC_EBU_SDRAM_RFRSH_STATUS_SELF_REFRESH_EXIT_STATUS = EBU_SDRMREF_SELFREXST_Msk /**< Self refresh exit command issue successful */ +} XMC_EBU_SDRAM_RFRSH_STATUS_t; + + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ + +/* Anonymous structure/union guard start */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__TASKING__) + #pragma warning 586 +#endif + +/** + * Clock configuration values of EBU
+ * + * The structure presents a convenient way to set/obtain the clock configuration + * values for clock mode, div2 clock mode and clock divide ratio of EBU. + * The XMC_EBU_Init() can be used to populate the structure with the clock + * configuration values of the EBU module. + */ +typedef struct XMC_EBU_CLK_CONFIG +{ + union + { + uint32_t raw0; + struct + { + uint32_t : 16; + uint32_t ebu_clk_mode : 1; /**< Clocking mode */ + uint32_t ebu_div2_clk_mode : 1; /**< DIV2 clocking mode */ + uint32_t ebu_clock_divide_ratio : 2; /**< Clock divide ratio */ + uint32_t : 12; + }; + }; +} XMC_EBU_CLK_CONFIG_t; + +/** + * Mode configuration values for EBU
+ * + * The structure presents a convenient way to set/obtain the mode configuration, + * SDRAM tristate, external clock, arbitration, timeout control and ALE mode for + * EBU. The XMC_EBU_Init() can be used to populate the structure with the + * clock configuration values of the EBU module. + */ +typedef struct XMC_EBU_MODE_CONFIG +{ + union + { + uint32_t raw0; + struct + { + uint32_t : 2; + uint32_t ebu_sdram_tristate : 1; /**< 0 - SDRAM cannot be shared; 1 - SDRAM can be shared */ + uint32_t : 1; + uint32_t ebu_extlock : 1; /**< 0 - ext bus is not locked after the EBU gains ownership; 1 - ext bus is not locked */ + uint32_t ebu_arbsync : 1; /**< 0 - arbitration inputs are sync; 1 - arbitration inputs are async */ + uint32_t ebu_arbitration_mode : 2; /**< Arbitration mode */ + /**< Determines num of inactive cycles leading to a bus timeout after the EBU gains ownership
+ 00H: Timeout is disabled
+ 01H: Timeout is generated after 1 x 8 clock cycles
+ FFH: Timeout is generated after 255 x 8 clock cycles */ + uint32_t bus_timeout_control : 8; /**< Determines num of inactive cycles leading to a bus timeout after the EBU gains ownership
+ 00H: Timeout is disabled
+ 01H: Timeout is generated after 1 x 8 clock cycles
+ FFH: Timeout is generated after 255 x 8 clock cycles
*/ + uint32_t : 15; + uint32_t ebu_ale_mode : 1; /**< ALE mode */ + }; + }; +} XMC_EBU_MODE_CONFIG_t; + +/** + * GPIO mode configuration for the allocated EBU ports
+ * Configuring this structure frees the allocated EBU ports for GPIO + * functionality. The XMC_EBU_Init() is used to populate the structure + * with the GPIO mode for the allocated EBU ports. + */ +typedef struct XMC_EBU_FREE_PINS_TO_GPIO +{ + union + { + uint32_t raw0; + struct + { + uint32_t : 16; + uint32_t address_pins_gpio : 9; /**< 0 - Address bit required for addressing memory; 1 - Address bit available as GPIO */ + uint32_t adv_pin_gpio : 1; /**< Adv pin to GPIO mode */ + uint32_t : 6; + }; + }; +} XMC_EBU_FREE_PINS_TO_GPIO_t; + +/** + * Read configuration for a region of EBU
+ * + * The structure presents a convenient way to set/obtain the read and read timing + * configuration for a region for EBU. The XMC_EBU_ConfigureRegion() can be + * used to populate the structure with the read configuration values for EBU. + */ +typedef struct XMC_EBU_BUS_READ_CONFIG +{ + /* EBU read configuration parameters */ + union + { + uint32_t raw0; + struct + { + uint32_t ebu_burst_length_sync : 3; /**< Burst length for synchronous burst */ + uint32_t ebu_burst_buffer_sync_mode : 1; /**< Burst buffer mode */ + uint32_t ebu_read_stages_synch : 1; /**< Read single stage synchronization */ + uint32_t ebu_burst_flash_clock_feedback : 1; /**< Burst flash clock feedback enable/disable */ + uint32_t ebu_burst_flash_clock_mode : 1; /**< Burst flash clock mode select */ + uint32_t ebu_flash_non_array_access : 1; /**< flash non-array access */ + uint32_t : 8; + uint32_t ebu_early_chip_select_sync_burst : 1; /**< Early chip select for sync burst */ + uint32_t ebu_burst_signal_sync : 1; /**< Early burst signal enable for synchronous burst */ + uint32_t ebu_burst_address_wrapping : 1; /**< Burst address wrapping */ + uint32_t ebu_wait_signal_polarity : 1; /**< Reversed polarity at WAIT */ + uint32_t ebu_byte_control : 2; /**< Byte control signal control */ + uint32_t ebu_device_addressing_mode : 2; /**< Device addressing mode */ + uint32_t ebu_wait_control : 2; /**< External wait control */ + uint32_t ebu_asynchronous_address_phase : 1; /**< Asynchronous address phase */ + uint32_t : 1; + uint32_t ebu_device_type : 4; /**< Device type for region */ + }; + }; + /* EBU read access parameters */ + union + { + uint32_t raw1; + struct + { + uint32_t ebu_recovery_cycles_between_different_regions : 4; + /** + * Recovery cycles after read accesses:
+ * 000B: No recovery phase clock cycles available
+ * 001B: 1 clock cycle selected
+ * ...
+ * 110B: 6 clock cycles selected
+ * 111B: 7 clock cycles selected
+ */ + uint32_t ebu_recovery_cycles_after_read_accesses : 3; + /** + * Programmed wait states for read accesses:
+ * 00000B: 1 wait state
+ * 00001B: 1 wait state
+ * 00010B: 2 wait state
+ * ...
+ * 11110B: 30 wait states
+ * 11111B: 31 wait states
+ */ + uint32_t ebu_programmed_wait_states_for_read_accesses : 5; + /** + * + */ + uint32_t ebu_data_hold_cycles_for_read_accesses: 4; + /** + * Frequency of external clock at pin BFCLKO + */ + uint32_t ebu_freq_ext_clk_pin : 2; + /** + * EBU Extended data + */ + uint32_t ebu_ext_data : 2; + /** + * Command delay cycles:
+ * 0000B: 0 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t command_delay_lines : 4; + /** + * Address hold cycles:
+ * 0000B: 0 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t address_hold_cycles : 4; + /** + * Address Cycles: + * 0000B: 1 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t address_cycles : 4; + }; + }; +} XMC_EBU_BUS_READ_CONFIG_t; + +/** + * Write configuration for a region of EBU
+ * + * The structure presents a convenient way to set/obtain the write and write timing + * configurations for a region of EBU. The XMC_EBU_ConfigureRegion() can be used + * to populate the structure with the write configuration values of EBU. + */ +typedef struct XMC_EBU_BUS_WRITE_CONFIG +{ + /* EBU write configuration parameters */ + union + { + uint32_t raw0; + struct + { + uint32_t ebu_burst_length_sync : 3; /**< Burst length for synchronous burst */ + uint32_t ebu_burst_buffer_sync_mode : 1; /**< Burst buffer mode */ + uint32_t : 12; + uint32_t ebu_early_chip_select_sync_burst : 1; /**< Early chip select for sync burst*/ + uint32_t ebu_burst_signal_sync : 1; /**< Early burst signal enable for synchronous burst */ + uint32_t : 1; + uint32_t ebu_wait_signal_polarity : 1; /**< Reversed polarity at WAIT */ + uint32_t ebu_byte_control : 2; /**< Byte control signal control */ + uint32_t ebu_device_addressing_mode : 2; /**< Device addressing mode */ + uint32_t ebu_wait_control : 2; /**< External wait control */ + uint32_t ebu_asynchronous_address_phase : 1; /**< Asynchronous address phase */ + uint32_t ebu_lock_chip_select : 1; /**< Lock chip select */ + uint32_t ebu_device_type : 4; /**< Device type for region */ + }; + }; + /* EBU write access parameters */ + union + { + uint32_t raw1; + struct + { + /** + * Recovery cycles between different regions:
+ * 0000B: No recovery phase clock cycles available
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t ebu_recovery_cycles_between_different_regions : 4; + + /** + * Recovery cycles after write accesses:
+ * 000B: No recovery phase clock cycles available
+ * 001B: 1 clock cycle selected
+ * ...
+ * 110B: 6 clock cycles selected
+ * 111B: 7 clock cycles selected
+ */ + uint32_t ebu_recovery_cycles_after_write_accesses : 3; + + /** + * Programmed wait states for write accesses:
+ * 00000B: 1 wait state
+ * 00001B: 1 wait state
+ * 00010B: 2 wait state
+ * ...
+ * 11110B: 30 wait states
+ * 11111B: 31 wait states
+ */ + uint32_t ebu_programmed_wait_states_for_write_accesses : 5; + + /** + * + */ + uint32_t ebu_data_hold_cycles_for_write_accesses : 4; + /**< + * Frequency of external clock at pin BFCLKO + */ + uint32_t ebu_freq_ext_clk_pin : 2; + /** + * EBU extended data + */ + uint32_t ebu_ext_data : 2; + /** + * Command delay cycles:
+ * 0000B: 0 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t command_delay_lines : 4; + /** Address hold cycles:
+ * 0000B: 0 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t address_hold_cycles : 4; + /** + * Address cycles:
+ * 0000B: 1 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t address_cycles : 4; + }; + }; +}XMC_EBU_BUS_WRITE_CONFIG_t; + +/** + * SDRAM configuration structure
+ * + * The structure is a placeholder for setting (and obtaining) the SDRAM configuration, + * operation mode configuration and the right refresh parameters. The XMC_EBU_ConfigureSdram() + * can be used to populate the structure with the SDRAM operation mode and + * refresh parameters configuration. + */ +typedef struct XMC_EBU_SDRAM_CONFIG +{ + /* EBU SDRAM control parameters */ + union + { + uint32_t raw0; + struct + { + /** + * Number of clock cycles between row activate command and a precharge + * command + */ + uint32_t ebu_row_precharge_delay_counter : 4; + /** + * (CRFSH) Number of refresh commands issued during powerup init sequence: + * Perform CRFSH + 1 refresh cycles + */ + uint32_t ebu_init_refresh_commands_counter : 4; + /** + * (CRSC) Number of NOP cycles after a mode register set command: + * Insert CRSC + 1 NOP cycles + */ + uint32_t ebu_mode_register_set_up_time : 2; + /** + * (CRP) Number of NOP cycles inserted after a precharge command: + * Insert CRP + 1 NOP cycles + */ + uint32_t ebu_row_precharge_time_counter : 2; + /** + * Number of address bits from bit 0 to be used for column address + */ + uint32_t ebu_sdram_width_of_column_address : 2; + /** + * (CRCD) Number of NOP cycles between a row address and a column + * address: Insert CRCD + 1 NOP cycles + */ + uint32_t ebu_sdram_row_to_column_delay_counter : 2; + /** + * Row cycle time counter: Insert (CRCE * 8) + CRC + 1 NOP cycles + */ + uint32_t ebu_sdram_row_cycle_time_counter : 3; + /** + * Mask for row tag + */ + uint32_t ebu_sdram_mask_for_row_tag : 3; + /** + * Mask for bank tag + */ + uint32_t ebu_sdram_mask_for_bank_tag : 3; + /** + * Extension to the Row cycle time counter (CRCE) + */ + uint32_t ebu_sdram_row_cycle_time_counter_extension : 3; + /** + * Disable SDRAM clock output + */ + uint32_t ebu_sdram_clk_output : 1; + /** + * Power Save Mode used for gated clock mode + */ + uint32_t ebu_sdram_pwr_mode : 2; + /** + * SDRAM clock mode select + */ + uint32_t ebu_sdram_clk_mode : 1; + }; + }; + /* EBU SDRAM mode parameters */ + union + { + uint32_t raw1; + struct + { + /** + * Number of locations can be accessed with a single command + */ + uint32_t ebu_sdram_burst_length : 3; + uint32_t : 1; + /** + * Number of clocks between a READ command and the availability + * of data + */ + uint32_t ebu_sdram_casclk_mode : 3; + uint32_t : 8; + /** + * Cold start + */ + uint32_t ebu_sdram_cold_start: 1; + /** + * Value to be written to the extended mode register of a mobile + * SDRAM device + */ + uint32_t ebu_sdram_extended_operation_mode : 12; + /** + * Value to be written to the bank select pins of a mobile SDRAM + * device during an extended mode register write operation + */ + uint32_t ebu_sdram_extended_operation_bank_select : 4; + }; + }; + /* EBU SDRAM refresh parameters */ + union + { + uint32_t raw2; + struct + { + /** + * Number of refresh counter period: + * Refresh period is 'num_refresh_counter_period' x 64 clock cycles + */ + uint32_t ebu_sdram_num_refresh_counter_period : 6; + /** + * Number of refresh commands + */ + uint32_t ebu_sdram_num_refresh_cmnds : 3; + uint32_t : 1; + /** + * If 1, the self refresh exit command is issued to all SDRAM devices + * regardless of their attachment to type 0 or type 1 + */ + uint32_t ebu_sdram_self_refresh_exit : 1; + uint32_t : 1; + /** + * If "1", the self refresh entry command is issued to all SDRAM devices, + * regardless regardless of their attachment to type 0 or type 1 + */ + uint32_t ebu_sdram_self_refresh_entry : 1; + /** + * If 1, memory controller will automatically issue the "self refresh + * entry" command to all SDRAM devices when it gives up control of the + * external bus. It will also automatically issue "self refresh exit" + * when it regains control of the bus + */ + uint32_t ebu_sdram_auto_self_refresh : 1; + /** + * Extended number of refresh counter period + */ + uint32_t ebu_sdram_extended_refresh_counter_period : 2; + /** + * Number of NOP cycles inserted after a self refresh exit before a + * command is permitted to the SDRAM/DDRAM + */ + uint32_t ebu_sdram_self_refresh_exit_delay : 8; + /** + * If 1, an auto refresh cycle will be performed; If 0, no refresh will + * be performed + */ + uint32_t ebu_sdram_auto_refresh : 1; + /** + * Number of NOPs after the SDRAM controller exits power down before an + * active command is permitted + */ + uint32_t ebu_sdram_delay_on_power_down_exit : 3; + uint32_t : 4; + }; + }; +} XMC_EBU_SDRAM_CONFIG_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__TASKING__) + #pragma warning restore +#endif + +/** + * EBU region initialization with read configurations
+ * + * The structure presents a convenient way to set/obtain the read and read timing + * configurations for a region of EBU. The XMC_EBU_ConfigureRegion() can be + * used to populate the structure with the read configuration values of EBU + */ +typedef struct XMC_EBU_REGION_READ_CONFIG +{ + const uint32_t ebu_region_no; /**< Number of region*/ + XMC_EBU_BUS_READ_CONFIG_t ebu_bus_read_config; /**< Read configuration and access parameters structure */ +} XMC_EBU_REGION_READ_CONFIG_t; + +/** + * EBU region initialization with write configurations
+ * + * The structure presents a convenient way to set/obtain the write and write + * timing configurations for a region of EBU. The XMC_EBU_ConfigureRegion() + * can be used to populate the structure with the write configuration + * values of EBU. + */ +typedef struct XMC_EBU_REGION_WRITE_CONFIG +{ + const uint32_t ebu_region_no; /**< Number of refresh counter period */ + XMC_EBU_BUS_WRITE_CONFIG_t ebu_bus_write_config; /**< Write configuration and access parameters structure */ +} XMC_EBU_REGION_WRITE_CONFIG_t; + +/** + * EBU region initialization with read and write configurations
+ * + * The structure presents a convenient way to set/obtain the read, read timing, + * write and write timing configurations for a region of EBU. The + * XMC_EBU_ConfigureRegion() can be used to populate the structure with the + * region read and write configuration values of EBU. + */ +typedef struct XMC_EBU_REGION +{ + XMC_EBU_REGION_READ_CONFIG_t read_config; + XMC_EBU_REGION_WRITE_CONFIG_t write_config; +} XMC_EBU_REGION_t; + +/** + * EBU global configurations
+ * + * The structure presents a convenient way to set/obtain the global configurations + * of the EBU like clock, mode and GPIO mode. The XMC_EBU_Init() can be + * used to populate the structure with the region read and write configuration + * values of EBU. + */ +typedef struct XMC_EBU_CONFIG +{ + XMC_EBU_CLK_CONFIG_t ebu_clk_config; /**< Clock configuration structure */ + XMC_EBU_MODE_CONFIG_t ebu_mode_config; /**< Mode configuration structure */ + XMC_EBU_FREE_PINS_TO_GPIO_t ebu_free_pins_to_gpio; /**< Free allocated EBU ports for GPIO */ +} XMC_EBU_CONFIG_t; + +/** + * External Bus Unit (EBU) device structure
+ * + * The structure represents a collection of all hardware registers + * used to configure the EBU peripheral on the XMC4500 microcontroller. + * The registers can be accessed with ::XMC_EBU. + */ +typedef struct +{ + __IO uint32_t CLC; + __IO uint32_t MODCON; + __I uint32_t ID; + __IO uint32_t USERCON; + __I uint32_t RESERVED0[2]; + __IO uint32_t ADDRSEL[4]; + struct + { + __IO uint32_t RDCON; + __IO uint32_t RDAPR; + __IO uint32_t WRCON; + __IO uint32_t WRAPR; + } BUS[4]; + __IO uint32_t SDRMCON; + __IO uint32_t SDRMOD; + __IO uint32_t SDRMREF; + __I uint32_t SDRSTAT; +} XMC_EBU_t; + +/********************************************************************************************************************** + * API PROTOTYPES +**********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param config Constant pointer to a constant ::XMC_EBU_CONFIG_t structure containing the + * clock mode and clock configuration. + * @return XMC_EBU_STATUS_t Always returns XMC_EBU_STATUS_OK (Only register assignment statements) + * + * \parDescription:
+ * Initialize the EBU peripheral
+ * + * \par + * The function enables the EBU peripheral, configures time values for clock mode, div2 + * clock mode, mode configuration, SDRAM tristate, external clock, arbitration, timeout + * control, ALE mode and configuration to free up the allocated EBU ports for GPIO + * functionality (if required). + */ +XMC_EBU_STATUS_t XMC_EBU_Init(XMC_EBU_t *const ebu, const XMC_EBU_CONFIG_t *const config); + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param config Constant pointer to a constant ::XMC_EBU_SDRAM_CONFIG_t structure containing + * the SDRAM configuration, operation mode configuration and right refresh + * parameters + * @return None + * + * \parDescription:
+ * Configures the SDRAM
+ * + * \par + * The function enables the SDRAM, sets SDRAM configuration parameters such as operation + * mode and refresh parameters. Please see ::XMC_EBU_SDRAM_CONFIG_t for more information. + */ +void XMC_EBU_ConfigureSdram(XMC_EBU_t *const ebu, const XMC_EBU_SDRAM_CONFIG_t *const config); + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param region Constant pointer to a constant ::XMC_EBU_REGION_t structure containing the + * read, read timing, write and write timing configurations for a region of + * EBU + * @return None + * + * \parDescription:
+ * Configures the SDRAM
+ * + * \par + * The function configures the EBU region read, read timing, write and write timing parameter + * configuration. It also configures the region registers for read and write accesses. Please + * see ::XMC_EBU_REGION_t for more information. + * + */ +void XMC_EBU_ConfigureRegion(XMC_EBU_t *const ebu, const XMC_EBU_REGION_t *const region); + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Enable EBU peripheral
+ * + * \par + * The function de-asserts the peripheral reset. The peripheral needs to be initialized. + * It also enables the control of the EBU. + * + * \parRelated APIs:
+ * XMC_EBU_Disable(), XMC_SCU_RESET_AssertPeripheralReset() + */ +__STATIC_INLINE void XMC_EBU_Enable(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_Enable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_EBU); + ebu->CLC &= ~EBU_CLC_DISR_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Disable EBU peripheral
+ * + * \par + * The function asserts the peripheral reset. It also disables the control of the EBU. + * + * \parRelated APIs:
+ * XMC_EBU_Enable(), XMC_SCU_RESET_DeassertPeripheralReset() + */ +__STATIC_INLINE void XMC_EBU_Disable(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_Disable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->CLC |= EBU_CLC_DISR_Msk; + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_EBU); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param clk_status Constant structure ::XMC_EBU_CLK_STATUS_t, containing the + * disable status, clock mode status, DIV2 clock mode status + * and clock divide ratio + * @return Status Returns clock status, disable status, clock mode status, DIV2 clock + * mode status and clock divide ratio + * + * \parDescription:
+ * Gets the clock status of EBU peripheral
+ * + * \par + * The function returns the clock staus of the EBU peripheral. The return value will + * indicate the following parameters:
+ * 1) Is EBU disabled?
+ * 2) Clocking mode
+ * 3) DIV2 clocking mode
+ * 4) Clock divide ratio
+ * + * \parRelated APIs:
+ * XMC_EBU_Enable(), XMC_EBU_Disable() and XMC_EBU_CLKDivideRatio() + */ +__STATIC_INLINE uint32_t XMC_EBU_GetCLKStatus(XMC_EBU_t *const ebu, const XMC_EBU_CLK_STATUS_t clk_status) +{ + XMC_ASSERT("XMC_EBU_GetCLKStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + return (uint32_t)(ebu->CLC & clk_status); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param clock_divide_ratio Structure ::XMC_EBU_CLOCK_DIVIDE_RATIO_t, containing the + * clock division factors of 1, 2, 3 and 4 respectively + * @return None + * + * \parDescription:
+ * Sets the clock divide ratio for EBU peripheral
+ * + * \par + * The function sets the CLC.EBUDIV bit-field to configure the clock divide ratio + * value (input clock divide by factor). + * + * \parRelated APIs:
+ * XMC_EBU_Enable(), XMC_EBU_Disable() and XMC_EBU_GetCLKStatus() + */ +__STATIC_INLINE void XMC_EBU_CLKDivideRatio(XMC_EBU_t *ebu, XMC_EBU_CLOCK_DIVIDE_RATIO_t clock_divide_ratio) +{ + XMC_ASSERT("XMC_EBU_CLKDivideRatio: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->CLC |= ((clock_divide_ratio << EBU_CLC_EBUDIV_Pos) & EBU_CLC_EBUDIV_Msk); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Sets the SDRAM self refresh exit (Power up)
+ * + * \par + * The function sets the SDRMREF.SELFREX bit to issue the self refresh command to + * all the SDRAM units. This ensures that the SDRAM units come out of the power down + * mode. The function also resets the bit SDRMREF.SELFRENST(Self refresh entry status). + */ +__STATIC_INLINE void XMC_EBU_SdramSetSelfRefreshExit(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramSetSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF |= EBU_SDRMREF_SELFREX_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Sets the SDRAM self refresh entry
+ * + * \par + * The function sets the SDRMREF.SELFREN bit-field to issue the self refresh command + * to all the SDRAM units. This ensures that the SDRAM units enter the power down mode + * after pre-charge. The function also resets the bit SDRMREF.SELFREXST(Self refresh + * exit status). + */ +__STATIC_INLINE void XMC_EBU_SdramSetSelfRefreshEntry(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramSetSelfRefreshEntry: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF |= EBU_SDRMREF_SELFREN_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Resets the SDRAM self refresh exit (Power up)
+ * + * \par + * The function resets the SDRMREF.SELFREX bit-field to stop issuing the self + * refresh command to all the SDRAM units connected to the bus. This ensures that + * the SDRAM units don't come out of the power down mode. + * + */ +__STATIC_INLINE void XMC_EBU_SdramResetSelfRefreshExit(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramResetSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF &= ~EBU_SDRMREF_SELFREX_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Resets the SDRAM self refresh entry
+ * + * \par + * The function resets the SDRMREF.SELFREN bit-field to stop issuing the self + * refresh command to all the SDRAM units. This ensures that the SDRAM units + * don't go into the power down mode after the pre-charge is all done. + * + */ +__STATIC_INLINE void XMC_EBU_SdramResetSelfRefreshEntry(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramResetSelfRefreshEntry: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF &= ~EBU_SDRMREF_SELFREN_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Sets the SDRAM auto refresh on self refresh exit
+ * + * \par + * The function sets the SDRMREF.ARFSH bit-field to enable an auto refresh cycle + * on existing self refresh before the self refresh exit delay. + * + * \parRelated APIs:
+ * XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit() + */ +__STATIC_INLINE void XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF |= EBU_SDRMREF_ARFSH_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Resets the SDRAM auto refresh on self refresh exit
+ * + * \par + * The function resets the SDRMREF.ARFSH bit to disable an auto refresh cycle + * on existing self refresh before the self refresh exit delay. No refresh will be + * performed. + * + * \parRelated APIs:
+ * XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit() + */ +__STATIC_INLINE void XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF &= ~EBU_SDRMREF_ARFSH_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Sets the SDRAM automatic self refresh
+ * + * \par + * The function sets the SDRMREF.AUTOSELFR bit-field. When set, the memory controller + * automatically issues the self refresh entry command to all SDRAM units + * devices when it gives up control of the external bus. It will also automatically + * issue the self refresh exit command when it regains control of the bus. + * + * \parRelated APIs:
+ * XMC_EBU_SdramDisableAutomaticSelfRefresh() + */ +__STATIC_INLINE void XMC_EBU_SdramEnableAutomaticSelfRefresh(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramEnableAutomaticSelfRefresh: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF |= EBU_SDRMREF_AUTOSELFR_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Resets the SDRAM automatic self refresh
+ * + * \par + * The function resets the SDRMREF.AUTOSELFR bit-field. When reset, the memory controller + * doesn't issue the self refresh entry command when it gives up control of the external + * bus. It will also not issue the self refresh exit command when it regains control of + * the bus. + * + * \parRelated APIs:
+ * XMC_EBU_SdramEnableAutomaticSelfRefresh() + */ +__STATIC_INLINE void XMC_EBU_SdramDisableAutomaticSelfRefresh(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramDisableAutomaticSelfRefresh: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF &= ~EBU_SDRMREF_AUTOSELFR_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu_addr_select_en Choose between a memory region enable or an alternate region enable + * @param ebu_region_n A valid region number for which enable and protection settings + * need to be configured + * @return None + * + * \parDescription:
+ * Controls the enable and protection settings of a region
+ * + * \par + * The function controls the enable and protection settings of a memory or alternate + * region. It configures the memory region enable, alternate region enable and the memory + * region's write protection. The bit-fields ADDRSEL.REGENAB, ADDRSEL.ALTENAB and + * ADDRSEL.WPROT are configured. + * + * \parRelated APIs:
+ * XMC_EBU_AddressSelectDisable() + */ +__STATIC_INLINE void XMC_EBU_AddressSelectEnable(XMC_EBU_t *const ebu, + uint32_t ebu_addr_select_en, + const uint32_t ebu_region_n) +{ + XMC_ASSERT("XMC_EBU_AddressSelectEnable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->ADDRSEL[ebu_region_n] |= ebu_addr_select_en; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu_addr_select_dis Choose between a memory region disable or an alternate + * region disable + * @param ebu_region_n A valid region number for which disable and protection + * settings configured + * @return None + * + * \parDescription:
+ * Controls the disable and protection settings of a region
+ * + * \par + * The function controls the disable and protection settings of a memory or alternate + * region. It configures the memory region disable, alternate region disable and the + * memory region write protect disable for write accesses. The bits ADDRSEL.REGENAB, + * ADDRSEL.ALTENAB and ADDRSEL.WPROT are configured. + * + * \parRelated APIs:
+ * XMC_EBU_AddressSelectEnable() + */ +__STATIC_INLINE void XMC_EBU_AddressSelectDisable(XMC_EBU_t *const ebu, + uint32_t ebu_addr_select_dis, + const uint32_t ebu_region_n) +{ + XMC_ASSERT("XMC_EBU_AddressSelectDisable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->ADDRSEL[ebu_region_n] &= ~ebu_addr_select_dis; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu_buswcon_status Enumeration of type ::XMC_EBU_BUSWCON_SELECT_t, representing + * values for non-array access and device addressing modes. + * @param ebu_region_n A valid region number for which status pertaining to WRITE is required + * @return Status Status of non-array access and device addressing mode + * + * \parDescription:
+ * Gets WRITE specific status for a region
+ * + * \par + * The function gets status of the various WRITE specific settings for a region. Status for + * non-array access enable and device addressing mode are obtained. The status bits of the + * BUSWCON register are returned. + * + * \parRelated APIs:
+ * XMC_EBU_ConfigureRegion() + */ +__STATIC_INLINE uint32_t XMC_EBU_GetBusWriteConfStatus(XMC_EBU_t *const ebu, + const XMC_EBU_BUSWCON_SELECT_t ebu_buswcon_status, + const uint32_t ebu_region_n) +{ + XMC_ASSERT("XMC_EBU_GetBusWriteConfStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + return (ebu->BUS[ebu_region_n].WRCON & ebu_buswcon_status); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return Status SDRAM error or busy states + * + * \parDescription:
+ * Gets SDRAM error or busy states
+ * + * \par + * The function gets SDRAM read error, refresh error and busy states. The bit-fields of SDRSTAT + * indicate the various states. REFERR reflects a failed previous refresh request collision + * with a new request. SDRMBUSY indicates the status of power-up initialization sequence. It + * indicates if it is running or not running. SDERR indicates if the SDRAM controller has + * detected an error when returning the read data. + * + * \parRelated APIs:
+ * XMC_EBU_ConfigureSdram() + */ +__STATIC_INLINE uint32_t XMC_EBU_SdramGetStatus(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramGetStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + return (uint32_t)(ebu->SDRSTAT); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param sdram_rfrsh_status Constant enum of type ::XMC_EBU_SDRAM_RFRSH_STATUS_t + * @return Status Status of self refresh entry and exit command issue + * + * \parDescription:
+ * Gets SDRAM refresh status
+ * + * \par + * The function gets SDRAM refresh status for self refresh entry/exit command successful issue. + * The bit-fields of SDRMREF indicate various states:
+ * SELFRENST reflects successful issue of self refresh entry command
+ * SELFREXST reflects successful issue of self refresh exit command
+ * + * \parRelated APIs:
+ * XMC_EBU_SdramResetSelfRefreshEntry(), XMC_EBU_SdramResetSelfRefreshExit() + */ +__STATIC_INLINE uint32_t XMC_EBU_SdramGetRefreshStatus(XMC_EBU_t *const ebu, + const XMC_EBU_SDRAM_RFRSH_STATUS_t sdram_rfrsh_status) +{ + XMC_ASSERT("XMC_EBU_SdramGetRefreshStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + return (uint32_t)(ebu->SDRMREF & sdram_rfrsh_status); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return bool Returns if the arbitration mode is selected or not + * + * \parDescription:
+ * Check if arbitration mode of EBU peripheral is selected + * + * \par + * The bit field ARBMODE of MODCON indicates the selected arbitration mode of the + * EBU. The follwing are the supported arbitration modes:
+ * 1) Arbiter Mode arbitration mode
+ * 2) Participant arbitration mode
+ * 3) Sole Master arbitration mode
+ * + * If any of the above modes are selected, the function returns "true". It returns + * false otherwise. + * + * \parRelated APIs:
+ * XMC_EBU_Init() \n\n\n + */ +__STATIC_INLINE bool XMC_EBU_IsBusAribitrationSelected(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_IsBusAribitrationSelected: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + return (bool)(ebu->MODCON & EBU_MODCON_ARBMODE_Msk); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EBU) */ + +#endif /* XMC_EBU_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ecat.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ecat.h new file mode 100644 index 00000000..45f1ff4e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ecat.h @@ -0,0 +1,462 @@ + +/** + * @file xmc_ecat.h + * @date 2015-12-27 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-12-27: + * - Initial Version
+ * + * @endcond + */ + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup ECAT + * @brief EtherCAT Low level driver for XMC4800/XMC4300 series. + * + * EtherCAT is an Ethernet-based fieldbus system. + * The EtherCAT Slave Controller (ECAT) read the data addressed to them while the telegram passes through the device. + * An EtherCAT Slave Controller (ESC) takes care of the EtherCAT communication as an interface between the EtherCAT + * fieldbus and the slave application. EtherCAT uses standard IEEE 802.3 Ethernet frames, thus a standard network + * controller can be used and no special hardware is required on master side. EtherCAT has a reserved EtherType of + * 0x88A4 that distinguishes it from other Ethernet frames. Thus, EtherCAT can run in parallel to other Ethernet + * protocols. EtherCAT does not require the IP protocol, however it can be encapsulated in IP/UDP. The EtherCAT + * Slave Controller processes the frame in hardware. Thus, communication performance is independent from processor + * power. + * + * The XMC_ECAT low level driver provides functions to configure and initialize the ECAT hardware peripheral. + * For EHTERCAT stack integration, the necessary hardware accees layer APIs shall be explicitly implemented depending + * upon the stack provider. The XMC_ECAT lld layer provides only the hardware initialization functions for start up and + * basic functionalities. + * @{ + */ + +#ifndef XMC_ECAT_H +#define XMC_ECAT_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_common.h" + +#if defined (ECAT0) + +#include "xmc_ecat_map.h" + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + +/** + * ECAT status return values + */ +typedef enum XMC_ECAT_STATUS +{ + XMC_ECAT_STATUS_OK = 0U, /**< Driver accepted application request */ + XMC_ECAT_STATUS_BUSY = 1U, /**< Driver is busy and cannot handle request */ + XMC_ECAT_STATUS_ERROR = 2U /**< Driver could not fulfil application request */ +} XMC_ECAT_STATUS_t; + +/** + * EtherCAT event enumeration types + */ +typedef enum XMC_ECAT_EVENT +{ + XMC_ECAT_EVENT_AL_CONTROL = ECAT_AL_EVENT_MASK_AL_CE_MASK_Msk, /**< Application control event mask */ + XMC_ECAT_EVENT_DC_LATCH = ECAT_AL_EVENT_MASK_DC_LE_MASK_Msk, /**< Distributed Clock latch event mask */ + XMC_ECAT_EVENT_DC_SYNC0 = ECAT_AL_EVENT_MASK_ST_S0_MASK_Msk, /**< State of distributed clock sync-0 event mask */ + XMC_ECAT_EVENT_DC_SYNC1 = ECAT_AL_EVENT_MASK_ST_S1_MASK_Msk, /**< State of distributed clock sync-1 event mask */ + XMC_ECAT_EVENT_SM_ACTIVATION_REGISTER = ECAT_AL_EVENT_MASK_SM_A_MASK_Msk, /**< SyncManager activation register mask*/ + XMC_ECAT_EVENT_EEPROM = ECAT_AL_EVENT_MASK_EEP_E_MASK_Msk, /**< EEPROM Emulation event mask*/ + XMC_ECAT_EVENT_WATCHDOG = ECAT_AL_EVENT_MASK_WP_D_MASK_Msk, /**< WATCHDOG process data event mask*/ + XMC_ECAT_EVENT_SM0 = ECAT_AL_EVENT_MASK_SMI_0_MASK_Msk, /**< Sync Manager 0 event mask*/ + XMC_ECAT_EVENT_SM1 = ECAT_AL_EVENT_MASK_SMI_1_MASK_Msk, /**< Sync Manager 1 event mask*/ + XMC_ECAT_EVENT_SM2 = ECAT_AL_EVENT_MASK_SMI_2_MASK_Msk, /**< Sync Manager 2 event mask*/ + XMC_ECAT_EVENT_SM3 = ECAT_AL_EVENT_MASK_SMI_3_MASK_Msk, /**< Sync Manager 3 event mask*/ + XMC_ECAT_EVENT_SM4 = ECAT_AL_EVENT_MASK_SMI_4_MASK_Msk, /**< Sync Manager 4 event mask*/ + XMC_ECAT_EVENT_SM5 = ECAT_AL_EVENT_MASK_SMI_5_MASK_Msk, /**< Sync Manager 5 event mask*/ + XMC_ECAT_EVENT_SM6 = ECAT_AL_EVENT_MASK_SMI_6_MASK_Msk, /**< Sync Manager 6 event mask*/ + XMC_ECAT_EVENT_SM7 = ECAT_AL_EVENT_MASK_SMI_7_MASK_Msk /**< Sync Manager 7 event mask*/ +} XMC_ECAT_EVENT_t; + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ + +/* Anonymous structure/union guard start */ +#if defined (__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined (__TASKING__) +#pragma warning 586 +#endif + +/** + * ECAT port control data structure + */ +typedef struct XMC_ECAT_PORT_CTRL +{ + union + { + struct + { + uint32_t enable_rstreq: 1; /**< Master can trigger a reset of the XMC4700 / XMC4800 (::bool) */ + uint32_t: 7; /**< Reserved bits */ + uint32_t latch_input0: 2; /**< Latch input 0 selection (::XMC_ECAT_PORT_LATCHIN0_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t latch_input1: 2; /**< Latch input 1 selection (::XMC_ECAT_PORT_LATCHIN1_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t phyaddr_offset: 5; /**< Ethernet PHY address offset, address of port 0 */ + uint32_t: 1; /**< Reserved bits */ + uint32_t mdio: 2; /**< Bidirectional, push-pull management data I/O line (::XMC_ETH_MAC_PORT_CTRL_MDIO_t) */ + uint32_t: 8; /**< Reserved bits */ + }; + + uint32_t raw; + } common; + + union + { + struct + { + uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ECAT_PORT0_CTRL_RXD0_t) */ + uint32_t rxd1: 2; /**< Receive data bit 1 (::XMC_ECAT_PORT0_CTRL_RXD1_t) */ + uint32_t rxd2: 2; /**< Receive data bit 2 (::XMC_ECAT_PORT0_CTRL_RXD2_t) */ + uint32_t rxd3: 2; /**< Receive data bit 3 (::XMC_ECAT_PORT0_CTRL_RXD3_t) */ + uint32_t rx_err: 2; /**< RX Error (::XMC_ECAT_PORT0_CTRL_RX_ERR_t) */ + uint32_t rx_dv: 2; /**< RX Data valid (::XMC_ECAT_PORT0_CTRL_RX_DV_t) */ + uint32_t rx_clk: 2; /**< RX Clock (::XMC_ECAT_PORT0_CTRL_RX_CLK_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t link: 2; /**< Link status (::XMC_ECAT_PORT0_CTRL_LINK_t) */ + uint32_t: 10; /**< Reserved bits */ + uint32_t tx_clk: 2; /**< TX Clock (::XMC_ECAT_PORT0_CTRL_TX_CLK_t) */ + uint32_t tx_shift: 2; /**< TX signal delay (::XMC_ECAT_PORT0_CTRL_TX_SHIFT_t) */ + }; + + uint32_t raw; + } port0; + + union + { + struct + { + uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ECAT_PORT_CTRL_RXD0_t) */ + uint32_t rxd1: 2; /**< Receive data bit 1 (::XMC_ECAT_PORT_CTRL_RXD1_t) */ + uint32_t rxd2: 2; /**< Receive data bit 2 (::XMC_ECAT_PORT_CTRL_RXD2_t) */ + uint32_t rxd3: 2; /**< Receive data bit 3 (::XMC_ECAT_PORT_CTRL_RXD3_t) */ + uint32_t rx_err: 2; /**< RX Error (::XMC_ECAT_PORT_CTRL_RX_ERR_t) */ + uint32_t rx_dv: 2; /**< RX Data valid (::XMC_ECAT_PORT_CTRL_RX_DV_t) */ + uint32_t rx_clk: 2; /**< RX Clock (::XMC_ECAT_PORT_CTRL_RX_CLK_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t link: 2; /**< Link status (::XMC_ECAT_PORT_CTRL_LINK_t) */ + uint32_t: 10; /**< Reserved bits */ + uint32_t tx_clk: 2; /**< TX Clock (::XMC_ECAT_PORT_CTRL_TX_CLK_t) */ + uint32_t tx_shift: 2; /**< TX signal delay (::XMC_ECAT_PORT1_CTRL_TX_SHIFT_t) */ + }; + + uint32_t raw; + } port1; + +} XMC_ECAT_PORT_CTRL_t; + +/** + * ECAT EEPROM configuration area data structure + */ +typedef union XMC_ECAT_CONFIG +{ + struct + { + uint32_t : 8; + + uint32_t : 2; + uint32_t enable_dc_sync_out : 1; + uint32_t enable_dc_latch_in : 1; + uint32_t enable_enhanced_link_p0 : 1; + uint32_t enable_enhanced_link_p1 : 1; + uint32_t : 2; + + uint32_t : 16; + + uint16_t sync_pulse_length; /**< Initialization value for Pulse Length of SYNC Signals register*/ + + uint32_t : 16; + + uint16_t station_alias; /**< Initialization value for Configured Station Alias Address register */ + + uint16_t : 16; + + uint16_t : 16; + + uint16_t checksum; + }; + + uint32_t dword[4]; /**< Four 32 bit double word equivalent to 8 16 bit configuration area word. */ +} XMC_ECAT_CONFIG_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) +#pragma pop +#elif defined (__TASKING__) +#pragma warning restore +#endif + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param config XMC_ECAT_CONFIG_t + * @return XMC_ECAT_STATUS_t ECAT Initialization status + * + * \parDescription:
+ * Initialize the Ethernet MAC peripheral
+ * + * \par + * The function sets the link speed, applies the duplex mode, sets auto-negotiation + * and loop-back settings. + */ +void XMC_ECAT_Init(XMC_ECAT_CONFIG_t *const config); + +/** + * @param None + * @return None + * + * \parDescription:
+ * Enable the EtherCAT peripheral
+ * + * \par + * The function de-asserts the peripheral reset. + */ +void XMC_ECAT_Enable(void); + +/** + * @param None + * @return None + * + * \parDescription:
+ * Disable the EtherCAT peripheral
+ * + * \par + * The function asserts the peripheral reset. + */ +void XMC_ECAT_Disable(void); + +/** + * @param phy_addr PHY address + * @param reg_addr Register address + * @param data The destination to which the read data needs to be copied to. + * + * @return XMC_ECAT_STATUS_t EtherCAT Read PHY API return status + * + * \parDescription:
+ * Read a PHY register
+ * + * \par + * The function reads a PHY register. It essentially polls busy bit during max + * PHY_TIMEOUT time and reads the information into 'data' when not busy. + */ +XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); + +/** + * @param phy_addr PHY address + * @param reg_addr Register address + * @param data The data to write + * @return XMC_ECAT_STATUS_t EtherCAT Write PHY API return status + * + * \parDescription:
+ * Write a PHY register
+ * + * \par + * The function reads a PHY register. It essentially writes the data and polls + * the busy bit until it is no longer busy. + */ +XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t data); + +/** + * @param port_ctrl Port control configuration + * @return None + * + * \parDescription:
+ * Set port control configuration
+ * + * \par + * The function sets the port control by writing the configuration into the ECAT CON register. + * + */ +__STATIC_INLINE void XMC_ECAT_SetPortControl(const XMC_ECAT_PORT_CTRL_t port_ctrl) +{ + ECAT0_CON->CON = (uint32_t)port_ctrl.common.raw; + ECAT0_CON->CONP0 = (uint32_t)port_ctrl.port0.raw; + ECAT0_CON->CONP1 = (uint32_t)port_ctrl.port1.raw; +} + +/** + * @param event Single or logically OR'd events specified in the enum type @refXMC_ECAT_EVENT_t + * @return None + * + * \parDescription:
+ * Enable ECAT event(s)
+ * + * \par + * The function can be used to enable ECAT event(s). + */ +void XMC_ECAT_EnableEvent(uint32_t event); + +/** + * @param event Single or logically OR'd events specified in the enum type @refXMC_ECAT_EVENT_t + * @return None + * + * \parDescription:
+ * Disable an ECAT event(s)
+ * + * \par + * The function can be used to disable ECAT event(s). + */ +void XMC_ECAT_DisableEvent(uint32_t event); + +/** + * @param None + * @return uint32_t Event status + * + * \parDescription:
+ * Get event status
+ * + * \par + * The function returns the ECAT status and interrupt status as a single word. The user + * can then check the status of the events by using an appropriate mask. + */ +uint32_t XMC_ECAT_GetEventStatus(void); + + +/** + * @param channel SyncManager channel number. + * @return None + * + * \parDescription:
+ * Disables selected SyncManager channel
+ * + * \par + * Sets bit 0 of the corresponding 0x807 register. + */ +void XMC_ECAT_DisableSyncManChannel(const uint8_t channel); + +/** + * @param channel SyncManager channel number. + * @return None + * + * \parDescription:
+ * Enables selected SyncManager channel
+ * + * \par + * Resets bit 0 of the corresponding 0x807 register. + */ +void XMC_ECAT_EnableSyncManChannel(const uint8_t channel); + +/** + * @param None + * @return uint16_t Content of register 0x220-0x221 + * + * \parDescription:
+ * Get content of AL event register
+ * + * \par + * Get the first two bytes of the AL Event register (0x220-0x221). + */ +__STATIC_INLINE uint16_t XMC_ECAT_GetALEventRegister(void) +{ + return ((uint16_t)ECAT0->AL_EVENT_REQ); +} + +/** + * @param None + * @return uint16_t Content of register 0x220-0x221 + * + * \parDescription:
+ * Get content of AL event register
+ * + * \par + * Get the first two bytes of the AL Event register (0x220-0x221). + */ +__STATIC_INLINE uint16_t XMC_ECAT_GetALEventMask(void) +{ + return ((uint16_t)ECAT0->AL_EVENT_MASK); +} + +/** + * @param intMask Interrupt mask (disabled interrupt shall be zero) + * @return None + * + * \parDescription:
+ * Sets application event mask register
+ * + * \par + * Performs a logical OR with the AL Event Mask register (0x0204 : 0x0205). + */ +__STATIC_INLINE void XMC_ECAT_SetALEventMask(uint16_t intMask) +{ + ECAT0->AL_EVENT_MASK |= (uint32_t)(intMask); +} + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (ECAT) */ + +#endif /* XMC_ECAT_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ecat_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ecat_map.h new file mode 100644 index 00000000..6053e7ba --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ecat_map.h @@ -0,0 +1,287 @@ +/** + * @file xmc_ecat_map.h + * @date 2016-07-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-09-09: + * - Initial + * + * 2015-07-20: + * - Added XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 and XMC_ECAT_PORT_CTRL_LATCHIN0_P9_1 + * + * @endcond + */ + +#ifndef XMC_ECAT_MAP_H +#define XMC_ECAT_MAP_H + +/** + * ECAT PORT 0 receive data 0 line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RXD0 +{ + XMC_ECAT_PORT0_CTRL_RXD0_P1_4 = 0U, /**< RXD0A receive data line */ + XMC_ECAT_PORT0_CTRL_RXD0_P5_0 = 1U, /**< RXD0B receive data line */ + XMC_ECAT_PORT0_CTRL_RXD0_P7_4 = 2U, /**< RXD0C receive data line */ +} XMC_ECAT_PORT0_CTRL_RXD0_t; + +/** + * ECAT PORT 0 receive data 1 line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RXD1 +{ + XMC_ECAT_PORT0_CTRL_RXD1_P1_5 = 0U, /**< RXD1A receive data line */ + XMC_ECAT_PORT0_CTRL_RXD1_P5_1 = 1U, /**< RXD1B receive data line */ + XMC_ECAT_PORT0_CTRL_RXD1_P7_5 = 2U, /**< RXD1C receive data line */ +} XMC_ECAT_PORT0_CTRL_RXD1_t; + +/** + * ECAT PORT 0 receive data 2 line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RXD2 +{ + XMC_ECAT_PORT0_CTRL_RXD2_P1_10 = 0U, /**< RXD2A receive data line */ + XMC_ECAT_PORT0_CTRL_RXD2_P5_2 = 1U, /**< RXD2B receive data line */ + XMC_ECAT_PORT0_CTRL_RXD2_P7_6 = 2U /**< RXD2C receive data line */ +} XMC_ECAT_PORT0_CTRL_RXD2_t; + +/** + * ECAT PORT 0 receive data 3 line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RXD3 +{ + XMC_ECAT_PORT0_CTRL_RXD3_P1_11 = 0U, /**< RXD3A Receive data line */ + XMC_ECAT_PORT0_CTRL_RXD3_P5_7 = 1U, /**< RXD3B Receive data line */ + XMC_ECAT_PORT0_CTRL_RXD3_P7_7 = 2U /**< RXD3C Receive data line */ +} XMC_ECAT_PORT0_CTRL_RXD3_t; + +/** + * ECAT PORT 0 receive error line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RX_ERR +{ + XMC_ECAT_PORT0_CTRL_RX_ERR_P4_0 = 0U, /**< RX_ERRA Receive error line */ + XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6 = 1U, /**< RX_ERRB Receive error line */ + XMC_ECAT_PORT0_CTRL_RX_ERR_P7_9 = 2U /**< RX_ERRC Receive error line */ +} XMC_ECAT_PORT0_CTRL_RX_ERR_t; + +/** + * ECAT PORT 0 receive clock line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RX_CLK +{ + XMC_ECAT_PORT0_CTRL_RX_CLK_P1_1 = 0U, /**< RX_CLKA Recevive clock */ + XMC_ECAT_PORT0_CTRL_RX_CLK_P5_4 = 1U, /**< RX_CLKB Recevive clock */ + XMC_ECAT_PORT0_CTRL_RX_CLK_P7_10 = 2U, /**< RX_CLKC Recevive clock */ +} XMC_ECAT_PORT0_CTRL_RX_CLK_t; + +/** + * ECAT PORT 0 data valid + */ +typedef enum XMC_ECAT_PORT0_CTRL_RX_DV +{ + XMC_ECAT_PORT0_CTRL_RX_DV_P1_9 = 0U, /**< RX_DVA Receive data valid */ + XMC_ECAT_PORT0_CTRL_RX_DV_P5_6 = 1U, /**< RX_DVB Receive data valid */ + XMC_ECAT_PORT0_CTRL_RX_DV_P7_11 = 2U, /**< RX_DVC Receive data valid */ +} XMC_ECAT_PORT0_CTRL_RX_DV_t; + +/** + * ECAT PORT 0 link status + */ +typedef enum XMC_ECAT_PORT0_CTRL_LINK +{ + XMC_ECAT_PORT0_CTRL_LINK_P4_1 = 0U, /**< LINKA Link status */ + XMC_ECAT_PORT0_CTRL_LINK_P1_15 = 1U, /**< LINKB Link status */ + XMC_ECAT_PORT0_CTRL_LINK_P9_10 = 2U, /**< LINKC Link status */ +} XMC_ECAT_PORT0_CTRL_LINK_t; + +/** + * ECAT PORT 0 transmit clock + */ +typedef enum XMC_ECAT_PORT0_CTRL_TX_CLK +{ + XMC_ECAT_PORT0_CTRL_TX_CLK_P1_0 = 0U, /**< TX_CLKA transmit clock */ + XMC_ECAT_PORT0_CTRL_TX_CLK_P5_5 = 1U, /**< TX_CLKB transmit clock */ + XMC_ECAT_PORT0_CTRL_TX_CLK_P9_1 = 2U, /**< TX_CLKC transmit clock */ +} XMC_ECAT_PORT0_CTRL_TX_CLK_t; + +/** + * ECAT PORT 1 receive data 0 line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RXD0 +{ + XMC_ECAT_PORT1_CTRL_RXD0_P0_11 = 0U, /**< RXD0A receive data line */ + XMC_ECAT_PORT1_CTRL_RXD0_P14_7 = 1U, /**< RXD0B receive data line */ + XMC_ECAT_PORT1_CTRL_RXD0_P8_4 = 2U, /**< RXD0C receive data line */ +} XMC_ECAT_PORT1_CTRL_RXD0_t; + +/** + * ECAT PORT 1 receive data 1 line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RXD1 +{ + XMC_ECAT_PORT1_CTRL_RXD1_P0_6 = 0U, /**< RXD1A receive data line */ + XMC_ECAT_PORT1_CTRL_RXD1_P14_12 = 1U, /**< RXD1B receive data line */ + XMC_ECAT_PORT1_CTRL_RXD1_P8_5 = 2U, /**< RXD1C receive data line */ +} XMC_ECAT_PORT1_CTRL_RXD1_t; + +/** + * ECAT PORT 1 receive data 2 line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RXD2 +{ + XMC_ECAT_PORT1_CTRL_RXD2_P0_5 = 0U, /**< RXD2A receive data line */ + XMC_ECAT_PORT1_CTRL_RXD2_P14_13 = 1U, /**< RXD2B receive data line */ + XMC_ECAT_PORT1_CTRL_RXD2_P8_6 = 2U /**< RXD2C receive data line */ +} XMC_ECAT_PORT1_CTRL_RXD2_t; + +/** + * ECAT PORT 1 receive data 3 line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RXD3 +{ + XMC_ECAT_PORT1_CTRL_RXD3_P0_4 = 0U, /**< RXD3A Receive data line */ + XMC_ECAT_PORT1_CTRL_RXD3_P14_14 = 1U, /**< RXD3B Receive data line */ + XMC_ECAT_PORT1_CTRL_RXD3_P8_7 = 2U /**< RXD3C Receive data line */ +} XMC_ECAT_PORT1_CTRL_RXD3_t; + +/** + * ECAT PORT 1 receive error line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RX_ERR +{ + XMC_ECAT_PORT1_CTRL_RX_ERR_P3_5 = 0U, /**< RX_ERRA Receive error line */ + XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2 = 1U, /**< RX_ERRB Receive error line */ + XMC_ECAT_PORT1_CTRL_RX_ERR_P8_9 = 2U /**< RX_ERRC Receive error line */ +} XMC_ECAT_PORT1_CTRL_RX_ERR_t; + +/** + * ECAT PORT 1 receive clock line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RX_CLK +{ + XMC_ECAT_PORT1_CTRL_RX_CLK_P0_1 = 0U, /**< RX_CLKA Recevive clock */ + XMC_ECAT_PORT1_CTRL_RX_CLK_P14_6 = 1U, /**< RX_CLKB Recevive clock */ + XMC_ECAT_PORT1_CTRL_RX_CLK_P8_10 = 2U, /**< RX_CLKC Recevive clock */ +} XMC_ECAT_PORT1_CTRL_RX_CLK_t; + +/** + * ECAT PORT 1 data valid + */ +typedef enum XMC_ECAT_PORT1_CTRL_RX_DV +{ + XMC_ECAT_PORT1_CTRL_RX_DV_P0_9 = 0U, /**< RX_DVA Receive data valid */ + XMC_ECAT_PORT1_CTRL_RX_DV_P14_15 = 1U, /**< RX_DVB Receive data valid */ + XMC_ECAT_PORT1_CTRL_RX_DV_P8_11 = 2U, /**< RX_DVC Receive data valid */ +} XMC_ECAT_PORT1_CTRL_RX_DV_t; + +/** + * ECAT PORT 0 link status + */ +typedef enum XMC_ECAT_PORT1_CTRL_LINK +{ + XMC_ECAT_PORT1_CTRL_LINK_P3_4 = 0U, /**< LINKA Link status */ + XMC_ECAT_PORT1_CTRL_LINK_P15_3 = 1U, /**< LINKB Link status */ + XMC_ECAT_PORT1_CTRL_LINK_P9_11 = 2U, /**< LINKC Link status */ +} XMC_ECAT_PORT1_CTRL_LINK_t; + +/** + * ECAT PORT 1 transmit clock + */ +typedef enum XMC_ECAT_PORT1_CTRL_TX_CLK +{ + XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10 = 0U, /**< TX_CLKA transmit clock */ + XMC_ECAT_PORT1_CTRL_TX_CLK_P5_9 = 1U, /**< TX_CLKB transmit clock */ + XMC_ECAT_PORT1_CTRL_TX_CLK_P9_0 = 2U, /**< TX_CLKC transmit clock */ +} XMC_ECAT_PORT1_CTRL_TX_CLK_t; + +/** + * ECAT management data I/O + */ +typedef enum XMC_ECAT_PORT_CTRL_MDIO +{ + XMC_ECAT_PORT_CTRL_MDIO_P0_12 = 0U, /**< MDIOA management data I/O */ + XMC_ECAT_PORT_CTRL_MDIO_P4_2 = 1U, /**< MDIOB management data I/O */ + XMC_ECAT_PORT_CTRL_MDIO_P9_7 = 2U /**< MDIOC management data I/O */ +} XMC_ECAT_PORT_CTRL_MDIO_t; + +/** + * ECAT latch 0 + */ +typedef enum XMC_ECAT_PORT_CTRL_LATCHIN0 +{ + XMC_ECAT_PORT_CTRL_LATCHIN0_P14_5 = 0U, /**< LATCH0A line */ + XMC_ECAT_PORT_CTRL_LATCHIN0_9_0 = 1U, /**< LATCH0B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 */ + XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 = 1U, /**< LATCH0B line */ + XMC_ECAT_PORT_CTRL_LATCHIN0_ERU0_PDOUT0 = 2U, /**< LATCH0C line */ + XMC_ECAT_PORT_CTRL_LATCHIN0_ERU1_PDOUT0 = 3U, /**< LATCH0D line */ +} XMC_ECAT_PORT_CTRL_LATCHIN0_t; + +/** + * ECAT latch 1 + */ +typedef enum XMC_ECAT_PORT_CTRL_LATCHIN1 +{ + XMC_ECAT_PORT_CTRL_LATCHIN1_P14_4 = 0U, /**< LATCH1 A line */ + XMC_ECAT_PORT_CTRL_LATCHIN1_9_1 = 1U, /**< LATCH1 B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1 */ + XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1 = 1U, /**< LATCH1 B line */ + XMC_ECAT_PORT_CTRL_LATCHIN1_ERU0_PDOUT1 = 2U, /**< LATCH1C line */ + XMC_ECAT_PORT_CTRL_LATCHIN1_ERU1_PDOUT1 = 3U, /**< LATCH1D line */ +} XMC_ECAT_PORT_CTRL_LATCHIN1_t; + +/** + * ECAT Port 0 Manual TX Shift configuration + */ +typedef enum XMC_ECAT_PORT0_CTRL_TX_SHIFT +{ + XMC_ECAT_PORT0_CTRL_TX_SHIFT_0NS = 0U, /**< ECAT Port 0 Manual TX Shift compensation 0 nanoseconds */ + XMC_ECAT_PORT0_CTRL_TX_SHIFT_10NS = 1U, /**< ECAT Port 0 Manual TX Shift compensation 10 nanoseconds */ + XMC_ECAT_PORT0_CTRL_TX_SHIFT_20NS = 2U, /**< ECAT Port 0 Manual TX Shift compensation 20 nanoseconds */ + XMC_ECAT_PORT0_CTRL_TX_SHIFT_30NS = 3U /**< ECAT Port 0 Manual TX Shift compensation 30 nanoseconds */ +} XMC_ECAT_PORT0_CTRL_TX_SHIFT_t; + +/** + * ECAT Port 1 Manual TX Shift configuration + */ +typedef enum XMC_ECAT_PORT1_CTRL_TX_SHIFT +{ + XMC_ECAT_PORT1_CTRL_TX_SHIFT_0NS = 0U, /**< ECAT Port 0 Manual TX Shift compensation 0 nanoseconds */ + XMC_ECAT_PORT1_CTRL_TX_SHIFT_10NS = 1U, /**< ECAT Port 0 Manual TX Shift compensation 10 nanoseconds */ + XMC_ECAT_PORT1_CTRL_TX_SHIFT_20NS = 2U, /**< ECAT Port 0 Manual TX Shift compensation 20 nanoseconds */ + XMC_ECAT_PORT1_CTRL_TX_SHIFT_30NS = 3U /**< ECAT Port 0 Manual TX Shift compensation 30 nanoseconds */ +} XMC_ECAT_PORT1_CTRL_TX_SHIFT_t; + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eru.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eru.h new file mode 100644 index 00000000..e5c04096 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eru.h @@ -0,0 +1,884 @@ +/** + * @file xmc_eru.h + * @date 2016-03-10 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Documentation updates
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-10-07: + * - Doc update for XMC_ERU_ETL_CONFIG_t field
+ * + * 2016-03-10: + * - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation.
+ * + * @endcond + */ + +#ifndef XMC_ERU_H +#define XMC_ERU_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_common.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup ERU + * @brief Event Request Unit (ERU) driver for the XMC microcontroller family. + * + * The Event Request Unit (ERU) is a versatile multiple input event detection and processing unit. + * The ERU module can be used to expand the P-to-P connections of the device: ports-to-peripherals, + * peripherals-to-peripherals and ports-to-ports. It also offers configurable logic, that allows the generation of + * triggers, pattern detection and real-time signal monitoring. + * + * @image html "eru_overview.png" + * + * The driver is divided into two sections: + * \par Event trigger logic (ERU_ETL): + * This section of the LLD provides the configuration structure XMC_ERU_ETL_CONFIG_t and the initialization function + * XMC_ERU_ETL_Init().\n + * It can be used to: + * -# Select one out of two inputs (A and B). For each of these two inputs, a vector of 4 possible signals is available. + * (XMC_ERU_ETL_SetSource()) + * -# Logically combine the two input signals to a common trigger. (XMC_ERU_ETL_SetSource()) + * -# Define the transition (edge selection, or by software) that leads to a trigger event and can also store this status. + * (XMC_ERU_ETL_SetEdgeDetection() and XMC_ERU_ETL_SetStatusFlag()) + * -# Distribute the events and status flags to the output channels. (XMC_ERU_ETL_EnableOutputTrigger()) + * + * \par Output gating unit (ERU_OGU): + * This section of the LLD provides the provides the configuration structure XMC_ERU_OGU_CONFIG_t and the initialization + * function XMC_ERU_ETL_OGU_Init(). + * It can be used to: + * -# Combine the trigger events and status information and gates the output depending on a gating signal. + * (XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_DisablePeripheralTrigger(), XMC_ERU_OGU_SetServiceRequestMode()) + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#if defined(ERU0) +#define XMC_ERU0 ((XMC_ERU_t *) ERU0_BASE) /**< ERU module 0 */ +#endif + +#if defined(ERU1) +#define XMC_ERU1 ((XMC_ERU_t *) ERU1_BASE) /**< ERU module 1, only available in XMC4 family */ +#endif + +#if UC_FAMILY == XMC1 + #include "xmc1_eru_map.h" +#endif + +#if UC_FAMILY == XMC4 + #include "xmc4_eru_map.h" +#endif + +#if defined(XMC_ERU0) && defined(XMC_ERU1) +#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0) | ((PTR)== XMC_ERU1)) +#elif defined(XMC_ERU0) +#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0)) +#elif defined(XMC_ERU1) +#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0)) +#endif + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/** + * Defines input signal for path A of ERSx(Event request source, x = [0 to 3]) unit. + * @image html "eru_input_a.png" "ETLx Input A selection" +*/ +typedef enum XMC_ERU_ETL_INPUT_A +{ + XMC_ERU_ETL_INPUT_A0 = 0x0U, /**< input A0 is selected */ + XMC_ERU_ETL_INPUT_A1 = 0x1U, /**< input A1 is selected */ + XMC_ERU_ETL_INPUT_A2 = 0x2U, /**< input A2 is selected */ + XMC_ERU_ETL_INPUT_A3 = 0x3U /**< input A3 is selected */ +} XMC_ERU_ETL_INPUT_A_t; + +/** + * Defines input signal for path B of ERSx(Event request source, x = [0 to 3]) unit. + * @image html "eru_input_b.png" "ETLx Input B selection" + */ +typedef enum XMC_ERU_ETL_INPUT_B +{ + XMC_ERU_ETL_INPUT_B0 = 0x0U, /**< input B0 is selected */ + XMC_ERU_ETL_INPUT_B1 = 0x1U, /**< input B1 is selected */ + XMC_ERU_ETL_INPUT_B2 = 0x2U, /**< input B2 is selected */ + XMC_ERU_ETL_INPUT_B3 = 0x3U /**< input B3 is selected */ +} XMC_ERU_ETL_INPUT_B_t; + +/** + * Defines input path combination along with polarity for event generation by ERSx(Event request source) unit to + * ETLx(Event trigger logic),x = [0 to 3] unit. + * @image html "eru_input_trigger.png" "ETLx input trigger signal generation" + */ +typedef enum XMC_ERU_ETL_SOURCE +{ + XMC_ERU_ETL_SOURCE_A = 0x0U, /**< select (A) path as a event source */ + XMC_ERU_ETL_SOURCE_B = 0x1U, /**< select (B) path as a event source */ + XMC_ERU_ETL_SOURCE_A_OR_B = 0x2U, /**< select (A OR B) path as a event source */ + XMC_ERU_ETL_SOURCE_A_AND_B = 0x3U, /**< select (A AND B) path as a event source */ + XMC_ERU_ETL_SOURCE_NOT_A = 0x4U, /**< select (inverted A) path as a event source */ + XMC_ERU_ETL_SOURCE_NOT_A_OR_B = 0x6U, /**< select (inverted A OR B) path as a event source */ + XMC_ERU_ETL_SOURCE_NOT_A_AND_B = 0x7U, /**< select (inverted A AND B) path as a event source */ + XMC_ERU_ETL_SOURCE_NOT_B = 0x9U, /**< select (inverted B) path as a event source */ + XMC_ERU_ETL_SOURCE_A_OR_NOT_B = 0xaU, /**< select (A OR inverted B) path as a event source */ + XMC_ERU_ETL_SOURCE_A_AND_NOT_B = 0xbU, /**< select (A AND inverted B) path as a event source */ + XMC_ERU_ETL_SOURCE_NOT_A_OR_NOT_B = 0xeU, /**< select (inverted A OR inverted B) path as a event + source */ + XMC_ERU_ETL_SOURCE_NOT_A_AND_NOT_B = 0xfU /**< select (inverted A AND inverted B) path as a event + source */ +} XMC_ERU_ETL_SOURCE_t; + +/** + * Defines trigger edge for the event generation by ETLx (Event Trigger Logic, x = [0 to 3]) unit, by getting the signal + * from ERSx(Event request source, x = [0 to 3]) unit. + */ +typedef enum XMC_ERU_ETL_EDGE_DETECTION +{ + XMC_ERU_ETL_EDGE_DETECTION_DISABLED = 0U, /**< no event enabled */ + XMC_ERU_ETL_EDGE_DETECTION_RISING = 1U, /**< detection of rising edge generates the event */ + XMC_ERU_ETL_EDGE_DETECTION_FALLING = 2U, /**< detection of falling edge generates the event */ + XMC_ERU_ETL_EDGE_DETECTION_BOTH = 3U /**< detection of either edges generates the event */ +} XMC_ERU_ETL_EDGE_DETECTION_t; + +/** + * Defines Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by + * ETLx(Event Trigger Logic, x = [0 to 3]) unit. + * @note Generation of output trigger pulse need to be enabled @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t + * @image html "eru_connection_matrix.png" "ERU_ETL ERU_OGU Connection matrix" + */ +typedef enum XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL +{ + XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0 = 0U, /**< Event from input ETLx triggers output OGU0 */ + XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL1 = 1U, /**< Event from input ETLx triggers output OGU1 */ + XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL2 = 2U, /**< Event from input ETLx triggers output OGU2 */ + XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL3 = 3U, /**< Event from input ETLx triggers output OGU3 */ +} XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t; + +/** + * Defines generation of the trigger pulse by ETLx(Event Trigger Logic, x = [0 to 3]) unit. + * Use type XMC_ERU_ETL_OUTPUT_TRIGGER_t for this enum. + */ +typedef enum XMC_ERU_ETL_OUTPUT_TRIGGER +{ + XMC_ERU_ETL_OUTPUT_TRIGGER_DISABLED = 0U, /**< trigger pulse generation disabled */ + XMC_ERU_ETL_OUTPUT_TRIGGER_ENABLED = 1U /**< trigger pulse generation enabled */ +} XMC_ERU_ETL_OUTPUT_TRIGGER_t; + +/** + * Defines status flag reset mode generated by ETLx(Event Trigger Logic, x = [0 to 3]) unit. + * Use type XMC_ERU_ETL_STATUS_FLAG_MODE_t for this enum. + */ +typedef enum XMC_ERU_ETL_STATUS_FLAG_MODE +{ + XMC_ERU_ETL_STATUS_FLAG_MODE_SWCTRL = 0U, /**< Status flag is in sticky mode. Retain the same state until + cleared by software. In case of pattern match this mode + is used. */ + XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL = 1U /**< Status flag is in non-sticky mode. Automatically cleared by + the opposite edge detection.\n + eg. if positive edge is selected as trigger event, for the + negative edge event the status flag is cleared. */ +} XMC_ERU_ETL_STATUS_FLAG_MODE_t; + +/** + * Defines pattern detection feature to be enabled or not in OGUy(Output gating unit, y = [0 to 3]). + * + */ +typedef enum XMC_ERU_OGU_PATTERN_DETECTION +{ + XMC_ERU_OGU_PATTERN_DETECTION_DISABLED = 0U, /**< Pattern match is disabled */ + XMC_ERU_OGU_PATTERN_DETECTION_ENABLED = 1U /**< Pattern match is enabled, the selected status flags of + ETLx(Event Trigger Logic, x = [0 to 3]) unit, are + used in pattern detection. */ +} XMC_ERU_OGU_PATTERN_DETECTION_t; + +/** + * Defines the inputs for Pattern detection. The configured status flag signal from the ETLx(Event Trigger Logic, + * x = [0 to 3]) unit indicates the pattern to be detected. + */ +typedef enum XMC_ERU_OGU_PATTERN_DETECTION_INPUT +{ + XMC_ERU_OGU_PATTERN_DETECTION_INPUT0 = 1U, /**< Status flag ETL0, participating in pattern match */ + XMC_ERU_OGU_PATTERN_DETECTION_INPUT1 = 2U, /**< Status flag ETL1, participating in pattern match */ + XMC_ERU_OGU_PATTERN_DETECTION_INPUT2 = 4U, /**< Status flag ETL0, participating in pattern match */ + XMC_ERU_OGU_PATTERN_DETECTION_INPUT3 = 8U /**< Status flag ETL0, participating in pattern match */ +} XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t; + +/** + * Defines peripheral trigger signal for event generation. Based on the selected peripheral for event generation, + * the trigger signal is mapped. + */ +typedef enum XMC_ERU_OGU_PERIPHERAL_TRIGGER +{ + XMC_ERU_OGU_PERIPHERAL_TRIGGER1 = 1U, /**< OGUy1 signal is mapped for event generation */ + XMC_ERU_OGU_PERIPHERAL_TRIGGER2 = 2U, /**< OGUy2 signal is mapped for event generation */ + XMC_ERU_OGU_PERIPHERAL_TRIGGER3 = 3U /**< OGUy3 signal is mapped for event generation */ +} XMC_ERU_OGU_PERIPHERAL_TRIGGER_t; + +/** + * Defines the gating scheme for service request generation. In later stage of the OGUy(Output gating unit, + * y = [0 to 3]) based on the gating scheme selected ERU_GOUTy(gated output signal) output is defined. + * @image html "interrupt_gating_signal.png" "Interrupt gating signal" + */ +typedef enum XMC_ERU_OGU_SERVICE_REQUEST +{ + XMC_ERU_OGU_SERVICE_REQUEST_DISABLED = 0U, /**< Service request blocked, ERUx_GOUTy = 0 */ + XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER = 1U, /**< Service request generated enabled, ERUx_GOUTy = 1 */ + XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH = 2U, /**< Service request generated on trigger + event and input pattern match, + ERUx_GOUTy = ~pattern matching result*/ + XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH = 3U/**< Service request generated on trigger + event and input pattern mismatch, + ERUx_GOUTy = pattern matching result*/ +} XMC_ERU_OGU_SERVICE_REQUEST_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * ERU module + */ +typedef struct { + union { + __IO uint32_t EXISEL; + + struct { + __IO uint32_t EXS0A : 2; + __IO uint32_t EXS0B : 2; + __IO uint32_t EXS1A : 2; + __IO uint32_t EXS1B : 2; + __IO uint32_t EXS2A : 2; + __IO uint32_t EXS2B : 2; + __IO uint32_t EXS3A : 2; + __IO uint32_t EXS3B : 2; + } EXISEL_b; + }; + __I uint32_t RESERVED0[3]; + + union { + __IO uint32_t EXICON[4]; + + struct { + __IO uint32_t PE : 1; + __IO uint32_t LD : 1; + __IO uint32_t ED : 2; + __IO uint32_t OCS : 3; + __IO uint32_t FL : 1; + __IO uint32_t SS : 4; + __I uint32_t RESERVED1 : 20; + } EXICON_b[4]; + }; + + union { + __IO uint32_t EXOCON[4]; + + struct { + __IO uint32_t ISS : 2; + __IO uint32_t GEEN : 1; + __I uint32_t PDR : 1; + __IO uint32_t GP : 2; + uint32_t : 6; + __IO uint32_t IPEN : 4; + __I uint32_t RESERVED2 : 16; + } EXOCON_b[4]; + }; +} XMC_ERU_t; + +/** + * \if XMC4 + * Structure for initializing ERUx_ETLy (x = [0..1], y = [0..4]) module. + * \endif + * \if XMC1 + * Structure for initializing ERUx_ETLy (x = [0], y = [0..4]) module. + * \endif + */ +typedef struct XMC_ERU_ETL_CONFIG +{ + union + { + uint32_t input; /**< While configuring the bit fields, the values have to be shifted according to the position */ + struct + { + uint32_t input_a: 2; /**< Configures input A. Refer @ref XMC_ERU_ETL_INPUT_A_t for valid values */ + uint32_t input_b: 2; /**< Configures input B. Refer @ref XMC_ERU_ETL_INPUT_B_t for valid values */ + uint32_t : 28; + }; + }; + + union + { + uint32_t raw; + struct + { + uint32_t enable_output_trigger: 1; /**< Enables the generation of trigger pulse(PE), for the configured edge + detection. This accepts boolean values as input. */ + uint32_t status_flag_mode: 1; /**< Enables the status flag auto clear(LD), for the opposite edge of the + configured event edge. This accepts boolean values as input. */ + uint32_t edge_detection: 2; /**< Configure the event trigger edge(FE, RE). + Refer @ref XMC_ERU_ETL_EDGE_DETECTION_t for valid values. */ + uint32_t output_trigger_channel: 3; /**< Output channel select(OCS) for ETLx output trigger pulse. + Refer @ref XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t for valid values. */ + uint32_t : 1; + uint32_t source: 4; /**< Input path combination along with polarity for event generation. + Refer @ref XMC_ERU_ETL_SOURCE_t for valid values. */ + uint32_t : 20; + }; + }; +} XMC_ERU_ETL_CONFIG_t; + +/** + * \if XMC4 + * Structure for initializing ERUx_OGUy (x = [0..1], y = [0..4]) module. + * \endif + * \if XMC1 + * Structure for initializing ERUx_OGUy (x = [0], y = [0..4]) module. + * \endif + */ +typedef union XMC_ERU_OGU_CONFIG +{ + uint32_t raw; + + struct + { + uint32_t peripheral_trigger: 2; /**< peripheral trigger(ISS) input selection. + Refer @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t for valid values. */ + uint32_t enable_pattern_detection: 1; /**< Enable generation of(GEEN) event for pattern detection result change. + This accepts boolean values as input. */ + uint32_t : 1; + uint32_t service_request: 2; /**< Gating(GP) on service request generation for pattern detection result. + Refer @ref XMC_ERU_OGU_SERVICE_REQUEST_t for valid values. */ + uint32_t : 6; + uint32_t pattern_detection_input: 4; /**< Enable input for the pattern detection(IPENx, x = [0 to 3]). + Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values. + OR combination of the enum items given as input */ + uint32_t : 16; + }; +} XMC_ERU_OGU_CONFIG_t; + +/*Anonymous structure/union guard end */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * API PROTOTYPES + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * + * @return None + * + * \parDescription:
+ * \if XMC4 + * If ERU1 module is selected, it enables clock and releases reset.
+ * \endif + * \if XMC1 + * Abstract API, not mandatory to call.
+ * \endif + * \par + * This API is called by XMC_ERU_ETL_Init() or XMC_ERU_OGU_Init() and therefore no need to call it explicitly during + * initialization sequence. Call this API to enable ERU1 module once again if the module is disabled by calling + * XMC_ERU_Disable(). For ERU0 module clock gating and reset features are not available. + * + * \parNote:
+ * \if XMC4 + * 1. Required to configure ERU1 module again after calling XMC_ERU_Disable(). Since the all the registers are + * reset with default values. + * \endif + * \parRelated APIs:
+ * XMC_ERU_ETL_Init(), XMC_ERU_OGU_Init(), XMC_ERU_Disable(). + */ +void XMC_ERU_Enable(XMC_ERU_t *const eru); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * + * @return None + * + * \parDescription:
+ * \if XMC4 + * Disables clock and releases reset for ERU1 module.
+ * \endif + * \if XMC1 + * Abstract API, not mandatory to call.
+ * \endif + * + * \parNote:
+ * \if XMC4 + * 1. Required to configure ERU1 module again after calling XMC_ERU_ETL_Init() or XMC_ERU_OGU_Init(). Since the all the + * registers are reset with default values. + * \endif + * \parRelated APIs:
+ * XMC_ERU_Enable() + */ +void XMC_ERU_Disable(XMC_ERU_t *const eru); + +/* ERU_ETL APIs */ + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_ETLx(Event trigger logic unit) channel + * Range : [0 to 3] + * @param config pointer to a constant ERU_ETLx configuration data structure. + * Refer data structure XMC_ERU_ETL_CONFIG_t for detail. + * + * @return None + * + * Description:
+ * Initializes the selected ERU_ETLx \a channel with the \a config structure.
+ * + * Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures + *
    + *
  • Input signal for path A and Path B,
    • + *
  • Trigger pulse generation,
    • + *
  • status flag clear mode,
    • + *
  • Event Trigger edge,
    • + *
  • Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse,
    • + *
  • input path combination along with polarity for event generation
    • + *
. + */ +void XMC_ERU_ETL_Init(XMC_ERU_t *const eru, const uint8_t channel, const XMC_ERU_ETL_CONFIG_t *const config); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * @param input_a input signal for path A of ERSx(Event request source, x = [0 to 3]) unit.\n + * Refer XMC_ERU_ETL_INPUT_A_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of + * the input is done based on selected signal.\n + * e.g: ERU0_ETL3_INPUTA_P2_7. + * @param input_b input signal for path B of ERSx(Event request source, x = [0 to 3]) unit.\n + * Refer XMC_ERU_ETL_INPUT_B_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of + * the input is done based on selected signal.\n + * e.g: ERU0_ETL0_INPUTB_P2_0. + * + * @return None + * + * \parDescription:
+ * Configures the event source for path A and path B in with selected \a input_a and \a input_b respectively.
+ * \par + * These values are set during initialization in XMC_ERU_ETL_Init(). Call this to change the input, as needed later in + * the program. According to the ports/peripheral selected, the event source has to be changed. + */ +void XMC_ERU_ETL_SetInput(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_INPUT_A_t input_a, + const XMC_ERU_ETL_INPUT_B_t input_b); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * @param source input path combination along with polarity for event generation by ERSx(Event request source) unit. + * Refer @ref XMC_ERU_ETL_SOURCE_t enum for valid input values. + * + * @return None + * + * \parDescription:
+ * Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits in + * ERSx(Event request source) unit
+ * \par + * The signal ERSxO is generated from the selection and this is connected to ETLx(Event trigger logic, + * x = [0 to 3]) for further action. These values are set during initialization in XMC_ERU_ETL_Init(). Call this to + * change the source, as needed later in the program. + */ +void XMC_ERU_ETL_SetSource(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_SOURCE_t source); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * @param edge_detection event trigger edge. + * Refer @ref XMC_ERU_ETL_EDGE_DETECTION_t enum for valid values. + * + * @return None + * + * \parDescription:
+ * Configure event trigger edge/s by setting (RE, FE) bits of EXICONx(x = [0 to 3]) register.
+ * \par + * Rising edge, falling edge or either edges can be selected to generate the event.These values are set during + * initialization in XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program. + */ +void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_EDGE_DETECTION_t edge_detection); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * + * @return XMC_ERU_ETL_EDGE_DETECTION_t indicate which egde/s is configured for event generation + * + * \parDescription:
+ * Return event trigger edge/s by reading (RE, FE) bits of EXICONx(x = [0 to 3]) register.
+ * \par + * Rising edge, falling edge or either edges can be selected to generate the event. + * Call this to get the configured trigger edge. */ +XMC_ERU_ETL_EDGE_DETECTION_t XMC_ERU_ETL_GetEdgeDetection(XMC_ERU_t *const eru, + const uint8_t channel); +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * + * @return None + * + * \parDescription:
+ * Set the status flag bit(FL) in EXICONx(x = [0 to 3]).
+ * \par + * The status flag indicates that the configured event has occurred. This status flag is used in Pattern match detection + * by OGUy(Output gating unit, y = [0 to 3]). + * \par + * \parRelated APIs:
+ * XMC_ERU_ETL_ClearStatusFlag(), XMC_ERU_ETL_GetStatusFlag() + */ +__STATIC_INLINE void XMC_ERU_ETL_SetStatusFlag(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_ETL_SetStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_SetStatusFlag:Invalid Channel Number", (channel < 4U)); + + eru->EXICON_b[channel].FL = true; +} + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * + * @return None + * + * \parDescription:
+ * Set the status flag bit(FL) in EXICONx(x = [0 to 3]).
+ * \par + * If auto clear of the status flag is not enabled by detection of the opposite edge of the event edge, this API clears + * the Flag. SO that next event is considered as new event. + * \parRelated APIs:
+ * XMC_ERU_ETL_SetStatusFlag(), XMC_ERU_ETL_GetStatusFlag() + */ +__STATIC_INLINE void XMC_ERU_ETL_ClearStatusFlag(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_ETL_ClearStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_ClearStatusFlag:Invalid Channel Number", (channel < 4U)); + + eru->EXICON_b[channel].FL = false; +} + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3]. + * + * @return uint32_t Current state of the status flag bit(FL). Result is in 32-bit format. + * + * \parDescription:
+ * Returns status flag state of \a channel. + * \par + * The function can typically be used to clear the status flag using software, when auto clear is not enabled. + * + * \parRelated APIs:
+ * XMC_ERU_ETL_SetStatusFlag(), XMC_ERU_ETL_ClearStatusFlag() + */ +__STATIC_INLINE uint32_t XMC_ERU_ETL_GetStatusFlag(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_ETL_GetStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_GetStatusFlag:Invalid Channel Number", (channel < 4U)); + + return (uint32_t)eru->EXICON_b[channel].FL; +} + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3]. + * @param mode Set whether status flag has to be cleared by software or hardware. + * Refer @ref XMC_ERU_ETL_STATUS_FLAG_MODE_t for valid value. + * + * @return None + * + * \parDescription:
+ * Set the mode for status flag mode by setting (LD) bit in EXICONx(x = \a channel) register.
+ * \par + * If SWCTRL is selected, status flag has to be cleared by software. This is typically used for pattern match detection. + * If HWCTRL is selected, status flag is cleared by hardware. If Positive edge is selected as event edge, for negative + * edge status flag is cleared and vice versa.This is typically used for continuous event detection.These values are set + * during initialization in XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_ERU_ETL_ClearStatusFlag(), XMC_ERU_ETL_GetStatusFlag() + */ +void XMC_ERU_ETL_SetStatusFlagMode(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_STATUS_FLAG_MODE_t mode); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3]. + * @param trigger Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse + * Refer @ref XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t for valid value. + * + * @return None + * + * \parDescription:
+ * Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by + * ETLx(Event Trigger Logic, x = \a channel) by setting (OCS and PE) bit fields. + * \par + * The trigger pulse is generated for one clock pulse along with the flag status update. This is typically used to + * trigger the ISR for the external events. The configured OGUy(Output gating unit y = [0 to 3]), generates the event + * based on the trigger pulse.If output trigger pulse generation is disabled by XMC_ERU_ETL_DisableOutputTrigger(), + * XMC_ERU_ETL_EnableOutputTrigger() can called to reconfigure. These values are set during initialization in + * XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_ERU_ETL_DisableOutputTrigger() + */ +void XMC_ERU_ETL_EnableOutputTrigger(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t trigger); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3]. + * + * @return None + * + * \parDescription:
+ * Disables the trigger pulse generation by clearing the (PE) of the EXICONx(x = \a channel). + * \par + * Typically this can used when only pattern match is being used for event generation. + * + * \parRelated APIs:
+ * XMC_ERU_ETL_EnableOutputTrigger() + */ +void XMC_ERU_ETL_DisableOutputTrigger(XMC_ERU_t *const eru, const uint8_t channel); + +/* ERU_OGU APIs */ + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * @param config pointer to constant ERU_OGUy configuration data structure. + * Refer data structure XMC_ERU_OGU_CONFIG_t for detail. + * + * @return None + * + * Description:
+ * Initializes the selected ERU_OGUy \a channel with the \a config structure.
+ * + * Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures + *
    + *
  • Pattern detection,
    • + *
  • Peripheral trigger input,
    • + *
  • Gating for service request generation
    • + *
. + */ +void XMC_ERU_OGU_Init(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_CONFIG_t *const config); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * @param input ERU_ETLx(x = [0 to 3]), for pattern match detection. + * Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values. Logical OR combination of the + * enum items can be passed as the input. + * + * @return None + * + * \parDescription:
+ * Configures ERU_ETLx(x = [0 to 3]) for pattern match detection by setting IPENx(x = [0 to 3]) and GEEN bits. + * \par + * These bits are dedicated to each channel of the ERU_ETLx(x = [0 to 3]). These values are set during initialization in + * XMC_ERU_OGU_Init(). Call this to change the pattern, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_ERU_OGU_DisablePatternDetection(), XMC_ERU_OGU_GetPatternDetectionStatus() + */ +void XMC_ERU_OGU_EnablePatternDetection(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t input); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * + * @return None + * + * \parDescription:
+ * Disable the pattern detection by clearing (GEEN) bit. + * \par + * Typically XMC_ERU_OGU_DisablePatternDetection is used when events has to be generated peripheral triggers. + * + * \parRelated APIs:
+ * XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_GetPatternDetectionStatus() + */ +void XMC_ERU_OGU_DisablePatternDetection(XMC_ERU_t *const eru, const uint8_t channel); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * + * @return uint32_t returns the pattern match result. Result is in 32-bit format. + * + * \parDescription:
+ * This API returns the pattern match result by reading (PDR) bit. + * \par + * \parRelated APIs:
+ * XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_DisablePatternDetection() + */ +__STATIC_INLINE uint32_t XMC_ERU_OGU_GetPatternDetectionStatus(XMC_ERU_t *const eru, + const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_OGU_GetPatternDetectionStatus:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_GetPatternDetectionStatus:Invalid Channel Number", (channel < 4U)); + + return (uint32_t)eru->EXOCON_b[channel].PDR; +} + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * @param peripheral_trigger which peripheral trigger signal is used for event generation. + * Refer @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t for the valid values, or + xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of the peripheral input is done based + on input. e.g: ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0. + * + * @return None + * + * \parDescription:
+ * Configures peripheral trigger input, by setting (ISS) bit. + * \par + * Based on the peripheral the input signal has to be selected. These values are set during initialization in + * XMC_ERU_OGU_Init(). Call this to change the input, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_ERU_OGU_DisablePeripheralTrigger() + */ +void XMC_ERU_OGU_EnablePeripheralTrigger(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * + * @return None + * + * \parDescription:
+ * Disables event generation based on peripheral trigger by clearing (ISS) bit. + * \par + * This is typically used when peripheral trigger is no longer need. After calling + * XMC_ERU_OGU_DisablePeripheralTrigger(), XMC_ERU_OGU_EnablePeripheralTrigger() has to be called to reconfigure the + * signals again. + * + * \parRelated APIs:
+ * XMC_ERU_OGU_EnablePeripheralTrigger() + */ +void XMC_ERU_OGU_DisablePeripheralTrigger(XMC_ERU_t *const eru, + const uint8_t channel); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * @param mode gating scheme for service request generation. + * Refer @ref XMC_ERU_OGU_SERVICE_REQUEST_t for valid values. + * + * @return None + * + * \parDescription:
+ * Configures the gating scheme for service request generation by setting (GP) bit.
+ * \par + * Typically this function is used to change the service request generation scheme. These values are set during + * initialization in XMC_ERU_OGU_Init(). Call this to change the gating mode, as needed later in the program. + * + */ +void XMC_ERU_OGU_SetServiceRequestMode(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_SERVICE_REQUEST_t mode); + +#ifdef __cplusplus +} +#endif + +/** + * @} (end addtogroup ERU) + */ + +/** + * @} (end addtogroup XMClib) + */ + +#endif /* XMC_ERU_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eth_mac.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eth_mac.h new file mode 100644 index 00000000..25488673 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eth_mac.h @@ -0,0 +1,1791 @@ + +/** + * @file xmc_eth_mac.h + * @date 2017-04-17 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * + * 2016-04-25: + * - Change XMC_ETH_MAC_BUF_SIZE to 1524 to allow for Tagged MAC frame format + * + * 2016-05-19: + * - Added XMC_ETH_MAC_GetTxBuffer() and XMC_ETH_MAC_GetRxBuffer() + * - Added XMC_ETH_MAC_SetTxBufferSize() + * + * 2016-06-08: + * - Added XMC_ETH_MAC_IsRxDescriptorOwnedByDma() + * + * 2017-02-25: + * - XMC_ETH_MAC_SetPortControl() fixed compilation warning + * + * 2017-04-02: + * - Added XMC_ETH_MAC_InitPTPEx() + * - Added XMC_ETH_MAC_SetPTPTime() + * - Added XMC_ETH_MAC_UpdateAddend() + * + * 2017-04-11: + * - Added XMC_ETH_MAC_EnablePTPAlarm() and XMC_ETH_MAC_DisablePTPAlarm + * + * 2017-04-17: + * - Fixed ordering of PTP nanoseconds and seconds in XMC_ETH_MAC_DMA_DESC_t + * + * @endcond + */ + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup ETH_MAC + * @brief Ethernet Low level driver for XMC4000 microcontroller family. + * + * The Ethernet MAC (ETH) is a major communication peripheral that supports 10/100 + * MBit/s data transfer rates in compliance with the IEEE 802.3-2002 standard. The ETH + * may be used to implement internet connected applications using IPv4 and IPv6. The + * ETH also includes support for IEEE1588 time synchronisation to allow implementation + * of Real Time Ethernet protocols. + * + * The XMC_ETH_MAC low level driver provides functions to configure and initialize + * the ETH_MAC hardware peripheral. + * @{ + */ + +#ifndef XMC_ETH_MAC_H +#define XMC_ETH_MAC_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_common.h" + +#if defined (ETH0) + +#include "xmc_eth_mac_map.h" + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +#define XMC_ETH_MAC_BUF_SIZE (1524) /**< ETH MAC buffer size */ +#define XMC_ETH_MAC_PHY_MAX_RETRIES (0xffffUL) /**< Maximum retries */ +#define XMC_ETH_WAKEUP_REGISTER_LENGTH (8U) /**< Remote wakeup frame reg length */ + +/** + * TDES0 Descriptor TX Packet Control/Status + */ +#define ETH_MAC_DMA_TDES0_OWN (0x80000000U) /**< Own bit 1=DMA, 0=CPU */ +#define ETH_MAC_DMA_TDES0_IC (0x40000000U) /**< Interrupt on competition */ +#define ETH_MAC_DMA_TDES0_LS (0x20000000U) /**< Last segment */ +#define ETH_MAC_DMA_TDES0_FS (0x10000000U) /**< First segment */ +#define ETH_MAC_DMA_TDES0_DC (0x08000000U) /**< Disable CRC */ +#define ETH_MAC_DMA_TDES0_DP (0x04000000U) /**< Disable pad */ +#define ETH_MAC_DMA_TDES0_TTSE (0x02000000U) /**< Transmit time stamp enable */ +#define ETH_MAC_DMA_TDES0_CIC (0x00C00000U) /**< Checksum insertion control */ +#define ETH_MAC_DMA_TDES0_TER (0x00200000U) /**< Transmit end of ring */ +#define ETH_MAC_DMA_TDES0_TCH (0x00100000U) /**< Second address chained */ +#define ETH_MAC_DMA_TDES0_TTSS (0x00020000U) /**< Transmit time stamp status */ +#define ETH_MAC_DMA_TDES0_IHE (0x00010000U) /**< IP header error */ +#define ETH_MAC_DMA_TDES0_ES (0x00008000U) /**< Error summary */ +#define ETH_MAC_DMA_TDES0_JT (0x00004000U) /**< Jabber timeout */ +#define ETH_MAC_DMA_TDES0_FF (0x00002000U) /**< Frame flushed */ +#define ETH_MAC_DMA_TDES0_IPE (0x00001000U) /**< IP payload error */ +#define ETH_MAC_DMA_TDES0_LOC (0x00000800U) /**< Loss of carrier */ +#define ETH_MAC_DMA_TDES0_NC (0x00000400U) /**< No carrier */ +#define ETH_MAC_DMA_TDES0_LC (0x00000200U) /**< Late collision */ +#define ETH_MAC_DMA_TDES0_EC (0x00000100U) /**< Excessive collision */ +#define ETH_MAC_DMA_TDES0_VF (0x00000080U) /**< VLAN frame */ +#define ETH_MAC_DMA_TDES0_CC (0x00000078U) /**< Collision count */ +#define ETH_MAC_DMA_TDES0_ED (0x00000004U) /**< Excessive deferral */ +#define ETH_MAC_DMA_TDES0_UF (0x00000002U) /**< Underflow error */ +#define ETH_MAC_DMA_TDES0_DB (0x00000001U) /**< Deferred bit */ + +/** + * RDES0 Descriptor RX Packet Status + */ +#define ETH_MAC_DMA_RDES0_OWN (0x80000000U) /**< Own bit 1=DMA, 0=CPU */ +#define ETH_MAC_DMA_RDES0_AFM (0x40000000U) /**< Destination address filter fail */ +#define ETH_MAC_DMA_RDES0_FL (0x3FFF0000U) /**< Frame length mask */ +#define ETH_MAC_DMA_RDES0_ES (0x00008000U) /**< Error summary */ +#define ETH_MAC_DMA_RDES0_DE (0x00004000U) /**< Descriptor error */ +#define ETH_MAC_DMA_RDES0_SAF (0x00002000U) /**< Source address filter fail */ +#define ETH_MAC_DMA_RDES0_LE (0x00001000U) /**< Length error */ +#define ETH_MAC_DMA_RDES0_OE (0x00000800U) /**< Overflow error */ +#define ETH_MAC_DMA_RDES0_VLAN (0x00000400U) /**< VLAN tag */ +#define ETH_MAC_DMA_RDES0_FS (0x00000200U) /**< First descriptor */ +#define ETH_MAC_DMA_RDES0_LS (0x00000100U) /**< Last descriptor */ +#define ETH_MAC_DMA_RDES0_TSA (0x00000080U) /**< Timestamp available */ +#define ETH_MAC_DMA_RDES0_LC (0x00000040U) /**< Late collision */ +#define ETH_MAC_DMA_RDES0_FT (0x00000020U) /**< Frame type */ +#define ETH_MAC_DMA_RDES0_RWT (0x00000010U) /**< Receive watchdog timeout */ +#define ETH_MAC_DMA_RDES0_RE (0x00000008U) /**< Receive error */ +#define ETH_MAC_DMA_RDES0_DBE (0x00000004U) /**< Dribble bit error */ +#define ETH_MAC_DMA_RDES0_CE (0x00000002U) /**< CRC error */ +#define ETH_MAC_DMA_RDES0_ESA (0x00000001U) /**< Extended Status/Rx MAC address */ + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + +/** + * Ethernet MAC status return values + */ +typedef enum XMC_ETH_MAC_STATUS +{ + XMC_ETH_MAC_STATUS_OK = 0U, /**< Driver accepted application request */ + XMC_ETH_MAC_STATUS_BUSY = 1U, /**< Driver is busy and cannot handle request */ + XMC_ETH_MAC_STATUS_ERROR = 2U /**< Driver could not fulfil application request */ +} XMC_ETH_MAC_STATUS_t; + +/** + * Transmission frame + */ +typedef enum XMC_ETH_MAC_TX_FRAME +{ + XMC_ETH_MAC_TX_FRAME_FRAGMENT = 0x1U, /**< Indicate frame fragment */ + XMC_ETH_MAC_TX_FRAME_EVENT = 0x2U, /**< Generate event when frame is transmitted */ + XMC_ETH_MAC_TX_FRAME_TIMESTAMP = 0x4U /**< Capture frame time stamp */ +} XMC_ETH_MAC_TX_FRAME_t; + +/** + * ETH MAC event + */ +typedef enum XMC_ETH_MAC_EVENT +{ + XMC_ETH_MAC_EVENT_PMT = ETH_INTERRUPT_MASK_PMTIM_Msk << 16, /**< Power management event */ + XMC_ETH_MAC_EVENT_TIMESTAMP = ETH_INTERRUPT_MASK_TSIM_Msk << 16, /**< Time stamp event */ + XMC_ETH_MAC_EVENT_EARLY_RECEIVE = ETH_STATUS_ERI_Msk, /**< Early receive */ + XMC_ETH_MAC_EVENT_BUS_ERROR = ETH_STATUS_FBI_Msk, /**< Bus error */ + XMC_ETH_MAC_EVENT_EARLY_TRANSMIT = ETH_STATUS_ETI_Msk, /**< Early transmit */ + XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT = ETH_STATUS_RWT_Msk, /**< Receive watchdog time-out */ + XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED = ETH_STATUS_RPS_Msk, /**< Receive process stopped */ + XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE = ETH_STATUS_RU_Msk, /**< Receive buffer unavailable */ + XMC_ETH_MAC_EVENT_RECEIVE = ETH_STATUS_RI_Msk, /**< Receive event */ + XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW = ETH_STATUS_UNF_Msk, /**< Transmit underflow */ + XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW = ETH_STATUS_OVF_Msk, /**< Receive overflow */ + XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT = ETH_STATUS_TJT_Msk, /**< Transmit jabber time-out */ + XMC_ETH_MAC_EVENT_TRANSMIT_BUFFER_UNAVAILABLE = ETH_STATUS_TU_Msk, /**< Transmit buffer unavailable */ + XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED = ETH_STATUS_TPS_Msk, /**< Transmit process stopped */ + XMC_ETH_MAC_EVENT_TRANSMIT = ETH_STATUS_TI_Msk /**< Transmit event */ +} XMC_ETH_MAC_EVENT_t; + +/** + * Link interface + */ +typedef enum XMC_ETH_LINK_INTERFACE +{ + XMC_ETH_LINK_INTERFACE_MII, /**< Link interface: Media independent interface */ + XMC_ETH_LINK_INTERFACE_RMII /**< Link interface: Reduced media independent interface */ +} XMC_ETH_LINK_INTERFACE_t; + +/** + * ETH link status + */ +typedef enum XMC_ETH_LINK_STATUS +{ + XMC_ETH_LINK_STATUS_DOWN, /**< Link status down */ + XMC_ETH_LINK_STATUS_UP /**< Link status up */ +} XMC_ETH_LINK_STATUS_t; + +/** + * ETH link speed + */ +typedef enum XMC_ETH_LINK_SPEED +{ + XMC_ETH_LINK_SPEED_10M = 0UL << ETH_MAC_CONFIGURATION_FES_Pos, /**< Link speed: 10M */ + XMC_ETH_LINK_SPEED_100M = 1UL << ETH_MAC_CONFIGURATION_FES_Pos /**< Link speed: 100M */ +} XMC_ETH_LINK_SPEED_t; + +/** + * ETH duplex settings (full/half?) + */ +typedef enum XMC_ETH_LINK_DUPLEX +{ + XMC_ETH_LINK_DUPLEX_HALF = 0UL << ETH_MAC_CONFIGURATION_DM_Pos, /**< Half duplex */ + XMC_ETH_LINK_DUPLEX_FULL = 1UL << ETH_MAC_CONFIGURATION_DM_Pos /**< Full duplex */ +} XMC_ETH_LINK_DUPLEX_t; + +/** + * MAC address filter + */ +typedef enum XMC_ETH_MAC_ADDR_FILTER +{ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE0 = 0x01000000UL, /**< Address filter mask: byte 0 */ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE1 = 0x02000000UL, /**< Address filter mask: byte 1 */ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE2 = 0x04000000UL, /**< Address filter mask: byte 2 */ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE3 = 0x08000000UL, /**< Address filter mask: byte 3 */ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE4 = 0x10000000UL, /**< Address filter mask: byte 4 */ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE5 = 0x20000000UL, /**< Address filter mask: byte 5 */ + XMC_ETH_MAC_ADDR_FILTER_SA = 0x40000000UL /**< Address filter SA */ +} XMC_ETH_MAC_ADDR_FILTER_t; + +/** + * Power management events that triggers a PMT interrupt + */ +typedef enum XMC_ETH_MAC_PMT_EVENT +{ + XMC_ETH_MAC_PMT_EVENT_ON_WAKEUP_FRAME = ETH_PMT_CONTROL_STATUS_RWKPKTEN_Msk, /**< Wakeup frame */ + XMC_ETH_MAC_PMT_EVENT_ON_MAGIC_PACKET = ETH_PMT_CONTROL_STATUS_MGKPKTEN_Msk, /**< Magic packet */ + XMC_ETH_MAC_PMT_EVENT_ON_UNICAST_FRAME_FILTER = ETH_PMT_CONTROL_STATUS_GLBLUCAST_Msk /**< Unicast frame filter */ +} XMC_ETH_MAC_PMT_EVENT_t; + + +/** + * ETH MAC time-stamp configuration enable + */ +typedef enum XMC_ETH_MAC_TIMESTAMP_CONFIG +{ + XMC_ETH_MAC_TIMESTAMP_CONFIG_FINE_UPDATE = ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk, /**< Fine update */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_TS_INTERRUPT = ETH_TIMESTAMP_CONTROL_TSTRIG_Msk, /**< Timestamp Interrupt Trigger Enable */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_ALL_FRAMES = ETH_TIMESTAMP_CONTROL_TSENALL_Msk, /**< Enable all frames */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTPV2 = ETH_TIMESTAMP_CONTROL_TSVER2ENA_Msk, /**< PTPV2 */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_ETHERNET = ETH_TIMESTAMP_CONTROL_TSIPENA_Msk, /**< PTP over ETH */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_IPV6 = ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Msk, /**< PTP over IPV6 */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_IPV4 = ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Msk, /**< PTP over IPV4 */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_MAC_ADDRESS_FILTER = ETH_TIMESTAMP_CONTROL_TSENMACADDR_Msk /**< MAC address filter */ +} XMC_ETH_MAC_TIMESTAMP_CONFIG_t; + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ + +/* Anonymous structure/union guard start */ +#if defined (__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined (__TASKING__) +#pragma warning 586 +#endif + +/** + * ETH MAC port control + */ +typedef union XMC_ETH_MAC_PORT_CTRL +{ + struct + { + uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ETH_MAC_PORT_CTRL_RXD0_t) */ + uint32_t rxd1: 2; /**< Receive data bit 1 (::XMC_ETH_MAC_PORT_CTRL_RXD1_t) */ + uint32_t rxd2: 2; /**< Receive data bit 2 (only MII) (::XMC_ETH_MAC_PORT_CTRL_RXD2_t) */ + uint32_t rxd3: 2; /**< Receive data bit 3 (only MII) (::XMC_ETH_MAC_PORT_CTRL_RXD3_t) */ + uint32_t clk_rmii: 2; /**< RMII: Continuous 50 MHz reference clock. + MII: Receive clock, 25 MHz for 100Mbit/s, 2.5 MHz for 10Mbit/s + (::XMC_ETH_MAC_PORT_CTRL_CLK_RMII_t) */ + uint32_t crs_dv: 2; /**< RMII: carrier sense/RX_Data valid. MII: RX_Data valid (::XMC_ETH_MAC_PORT_CTRL_CRS_DV_t) */ + uint32_t crs: 2; /**< Carrier sense for only MII (::XMC_ETH_MAC_PORT_CTRL_CRS_t) */ + uint32_t rxer: 2; /**< Receive error (::XMC_ETH_MAC_PORT_CTRL_RXER_t) */ + uint32_t col: 2; /**< Collision Detect for only MII (::XMC_ETH_MAC_PORT_CTRL_COL_t) */ + uint32_t clk_tx: 2; /**< Transmit clock (only MII), 25 MHz for 100Mbit/s, 2.5 MHz for 10Mbit/s (::XMC_ETH_MAC_PORT_CTRL_CLK_TX_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t mdio: 2; /**< Bidirectional, push-pull management data I/O line (::XMC_ETH_MAC_PORT_CTRL_MDIO_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t mode: 1; /**< RMII or MII (::XMC_ETH_MAC_PORT_CTRL_MODE_t) */ + }; + + uint32_t raw; +} XMC_ETH_MAC_PORT_CTRL_t; + +/** + * ETH MAC DMA descriptor + */ +typedef struct XMC_ETH_MAC_DMA_DESC +{ + uint32_t status; /**< DMA descriptor status */ + uint32_t length; /**< Descriptor length */ + uint32_t buffer1; /**< Buffer 1 */ + uint32_t buffer2; /**< Buffer 2 */ + uint32_t extended_status; /**< Extended status */ + uint32_t reserved; /**< Reserved */ + uint32_t time_stamp_nanoseconds; /**< Time stamp low */ + uint32_t time_stamp_seconds; /**< Time stamp high */ +} XMC_ETH_MAC_DMA_DESC_t; + +/** + * ETH MAC time + */ +typedef struct XMC_ETH_MAC_TIME +{ + uint32_t seconds; /**< Seconds */ + int32_t nanoseconds; /**< Nanoseconds */ +} XMC_ETH_MAC_TIME_t; + +/** + * ETH driver structure + */ +typedef struct XMC_ETH_MAC +{ + ETH_GLOBAL_TypeDef *regs; /**< ETH module 0 (now, we have a single ETH module) */ + uint64_t address; /**< MAC address */ + XMC_ETH_MAC_DMA_DESC_t *rx_desc; /**< DMA descriptor: RX */ + XMC_ETH_MAC_DMA_DESC_t *tx_desc; /**< DMA descriptor: TX */ + uint8_t *rx_buf; /**< RX buffer */ + uint8_t *tx_buf; /**< TX buffer */ + uint8_t *frame_end; /**< End of assembled frame fragments */ + uint8_t num_rx_buf; /**< How many RX descriptors? */ + uint8_t num_tx_buf; /**< How many TX descriptors? */ + uint8_t tx_index; /**< Transmit descriptor index */ + uint8_t rx_index; /**< Receive descriptor index */ + uint8_t tx_ts_index; /**< Transmit time-stamp descriptor index */ +} XMC_ETH_MAC_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) +#pragma pop +#elif defined (__TASKING__) +#pragma warning restore +#endif + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return XMC_ETH_MAC_STATUS_t Initialization status + * + * \parDescription:
+ * Initialize the Ethernet MAC peripheral
+ * + * \par + * The function sets the link speed, applies the duplex mode, sets auto-negotiation + * and loop-back settings. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_Init(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Initialize the RX DMA descriptors
+ * + * \par + * The function initializes the RX descriptors in a chained configuration. It sets + * up the status bit, control bit, buffer length and the buffer pointer. + */ +void XMC_ETH_MAC_InitRxDescriptors(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Initialize the TX DMA descriptors
+ * + * \par + * The function initializes the TX descriptors in a chained configuration. It sets + * up the status bit, control bit, buffer length and the buffer pointer. + */ +void XMC_ETH_MAC_InitTxDescriptors(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable the Ethernet MAC peripheral
+ * + * \par + * The function de-asserts the peripheral reset. + */ +void XMC_ETH_MAC_Enable(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable the Ethernet MAC peripheral
+ * + * \par + * The function asserts the peripheral reset. + */ +void XMC_ETH_MAC_Disable(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return bool + * + * \parDescription:
+ * Check if the ETH MAC is enabled
+ * + * \par + * The function checks if the ETH MAC is enabled or not. It returns "true" if the + * peripheral is enabled, "false" otherwise. + */ +bool XMC_ETH_MAC_IsEnabled(const XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Reset the ETH MAC peripheral
+ * + * \par + * The function resets the ETH MAC peripheral. It blocks until reset. + */ +__STATIC_INLINE void XMC_ETH_MAC_Reset(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->BUS_MODE |= (uint32_t)ETH_BUS_MODE_SWR_Msk; + while ((eth_mac->regs->BUS_MODE & (uint32_t)ETH_BUS_MODE_SWR_Msk) != 0U) + { + } +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr PHY address + * @param reg_addr Register address + * @param data The destination to which the read data needs to be copied to + * @return XMC_ETH_MAC_STATUS_t ETH MAC status + * + * \parDescription:
+ * Read a PHY register
+ * + * \par + * The function reads a PHY register. It essentially polls busy bit during max + * PHY_TIMEOUT time and reads the information into 'data' when not busy. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_ReadPhy(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr PHY address + * @param reg_addr Register address + * @param data The data to write + * @return XMC_ETH_MAC_STATUS_t ETH MAC status + * + * \parDescription:
+ * Write a PHY register
+ * + * \par + * The function reads a PHY register. It essentially writes the data and polls + * the busy bit until it is no longer busy. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_WritePhy(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, uint8_t reg_addr, uint16_t data); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param port_ctrl Port control configuration + * @return None + * + * \parDescription:
+ * Set port control configuration
+ * + * \par + * The function sets the port control by writing the configuration into the + * CON register. + * + * \note + * MII Mode is only available in: + * - XMC4500 LQFP144 and BGA144 packages + * - XMC4700 LQFP144 and BGA196 packages + * - XMC4800 LQFP144 and BGA196 packages + * + */ +__STATIC_INLINE void XMC_ETH_MAC_SetPortControl(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_PORT_CTRL_t port_ctrl) +{ + XMC_UNUSED_ARG(eth_mac); + ETH0_CON->CON = (uint32_t)port_ctrl.raw; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return XMC_ETH_MAC_STATUS_t ETH MAC status + * + * \parDescription:
+ * Set management clock divider
+ * + * \par + * The function sets the management clock divider by writing to the GMII_ADDRESS + * register. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SetManagmentClockDivider(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param addr The MAC address to set + * @return None + * + * \parDescription:
+ * Set MAC address
+ * + * \par + * The function sets the MAC address by writing to the MAC_ADDRESS0_HIGH and + * MAC_ADDRESS0_LOW registers. + */ +__STATIC_INLINE void XMC_ETH_MAC_SetAddress(XMC_ETH_MAC_t *const eth_mac, uint64_t addr) +{ + eth_mac->regs->MAC_ADDRESS0_HIGH = (uint32_t)(addr >> 32); + eth_mac->regs->MAC_ADDRESS0_LOW = (uint32_t)addr; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return uint64_t The MAC address which has been set + * + * \parDescription:
+ * Get MAC address
+ * + * \par + * The function returns the current ETH MAC address. + */ +__STATIC_INLINE uint64_t XMC_ETH_MAC_GetAddress(XMC_ETH_MAC_t *const eth_mac) +{ + return ((((uint64_t)eth_mac->regs->MAC_ADDRESS0_HIGH << 32)) | (uint64_t)eth_mac->regs->MAC_ADDRESS0_LOW); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param index Table entry index + * @param addr Address value + * @param flags Compare control. OR'ed combination of @ref XMC_ETH_MAC_ADDR_FILTER_t or zero. + * + * @return None + * + * \parDescription:
+ * Set perfect filter for address filtering
+ * + * \par + * The function can be used to set perfect filter for address filtering. + */ +void XMC_ETH_MAC_SetAddressPerfectFilter(XMC_ETH_MAC_t *const eth_mac, uint8_t index, const uint64_t addr, uint32_t flags); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param hash The hash to be used for filtering + * @return None + * + * \parDescription:
+ * Set hash filter for group address filtering
+ * + * \par + * The function sets up a hash filter for group address filtering. It writes the + * given hash value into the HASH_TABLE_LOW and HASH_TABLE_HIGH registers. + */ +void XMC_ETH_MAC_SetAddressHashFilter(XMC_ETH_MAC_t *const eth_mac, const uint64_t hash); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable frame filter
+ * + * \par + * The function resets the RA bitfield of the MAC_FRAME_FILTER register. This + * ensures that the receiver module passes only those frames (to the application) + * that pass the SA or DA address filter. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableFrameFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_RA_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable frame filter
+ * + * \par + * The function sets the RA bitfield of the MAC_FRAME_FILTER register. This + * ensures that the receiver module passes all received frames, irrespective + * of whether they pass the address filter or not. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableFrameFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_RA_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable hash perfect filter
+ * + * \par + * The function sets the HPF bitfield of the MAC_FRAME_FILTER register. The + * function configures the address filter to pass a frame if it matches + * either the perfect filtering or the hash filtering. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableHashPerfectFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_HPF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable perfect filter
+ * + * \par + * The function clears the HPF bitfield of the MAC_FRAME_FILTER register. When the + * function is invoked, the frame is passed only if it matches the hash filter. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnablePerfectFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_HPF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable source address filter
+ * + * \par + * The function sets the SAF bitfield of the MAC_FRAME_FILTER register. Verbatim + * from the reference manual - "When invoked, the MAC compares the SA field of the + * received frames with the values programmed in the enabled SA registers. If the + * comparison matches, then the SA Match bit of RxStatus Word is set high. When + * this bit is set high and the SA filter fails, the MAC drops the frame. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableSourceAddressFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_SAF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable source address filter
+ * + * \par + * The function resets the SAF bitfield of the MAC_FRAME_FILTER register. Verbatim + * from the reference manual - "When invoked, the MAC forwards the received frame to + * the application and updates the SA Match bit of the RxStatus depending on + * the SA address comparison". + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableSourceAddressFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_SAF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable source address inverse filtering
+ * + * \par + * The function resets the SAIF bitfield of the MAC_FRAME_FILTER register. Verbatim + * from the reference manual - "When invoked, the address check block operates in + * inverse filtering mode for the SA address comparison. The frames whose SA matches + * the SA registers are marked as failing the SA Address filter". + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableSourceAddressInverseFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_SAIF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable source address inverse filtering
+ * + * \par + * The function resets the SAIF bitfield of the MAC_FRAME_FILTER register. Verbatim + * from the reference manual - "When invoked, frames whose SA does not match the SA + * registers are marked as failing the SA Address filter". + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableSourceAddressInverseFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_SAIF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable destination address inverse filtering
+ * + * \par + * The function sets the DAIF bitfield of the MAC_FRAME_FILTER register. Verbatim + * from the reference manual - "When invoked, the address check block operates in + * inverse filtering mode for the DA address comparison for both unicast and + * multicast frames". + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableDestinationAddressInverseFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_DAIF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable destination address inverse filtering
+ * + * \par + * The function sets the DAIF bitfield of the MAC_FRAME_FILTER register. It can + * be used to perform normal filtering of frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableDestinationAddressInverseFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_DAIF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable multicast hash filter
+ * + * \par + * When invoked, the MAC performs destination address filtering of received + * multicast frames according to the hash table. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableMulticastHashFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_HMC_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable multicast hash filter
+ * + * \par + * The function disables multicast hash filtering. The MAC performs a perfect + * destination address filtering for multicast frames post invocation. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableMulticastHashFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_HMC_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable unicast hash filter
+ * + * \par + * The function enables the MAC to perform destination address filtering of + * unicast frames according to the hash table. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableUnicastHashFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_HUC_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable unicast hash filter
+ * + * \par + * The function disables unicast hash filtering. When invoked, the MAC performs a + * perfect destination address filtering for unicast frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableUnicastHashFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_HUC_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param frame A pointer to a uint8_t constant, holding the frame to be transmitted + * @param len Length of the frame to transmit + * @param flags Additional flags: ored combination of ::XMC_ETH_MAC_TX_FRAME_t or zero. + * @return XMC_ETH_MAC_STATUS_t ETH MAC status (XMC_ETH_MAC_STATUS_BUSY if busy, + * XMC_ETH_MAC_STATUS_OK otherwise). + * + * \parDescription:
+ * Send a frame
+ * + * \par + * The function is used to send a frame. The transmission is done using + * the ETH MAC's dedicated DMA unit. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SendFrame(XMC_ETH_MAC_t *const eth_mac, + const uint8_t *frame, + uint32_t len, + uint32_t flags); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param frame A constant pointer to a uint8_t constant, holding the received frame + * @param len Frame length? + * @return uint32_t Length of the frame + * + * \parDescription:
+ * Read a frame
+ * + * \par + * The function is used to read a frame. The function returns 'len', the length + * as specified as the actual parameter in the function call. + */ +uint32_t XMC_ETH_MAC_ReadFrame(XMC_ETH_MAC_t *const eth_mac, uint8_t *const frame, uint32_t len); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return uint32_t RX frame size + * + * \parDescription:
+ * Get RX frame size
+ * + * \par + * The function is used to get the effective length of the RX frame size. + */ +uint32_t XMC_ETH_MAC_GetRxFrameSize(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable reception of broadcast frames
+ * + * \par + * This function enables the AFM module to pass all received broadcast frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableReceptionBroadcastFrames(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_DBF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable reception of broadcast frames
+ * + * \par + * The function sets the DBF bitfield of the MAC_FRAME_FILTER register. When set, + * the AFM module filters all incoming broadcast frames. In addition, it overrides + * all other filter settings. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableReceptionBroadcastFrames(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_DBF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable reception of multicast frames
+ * + * \par + * The function sets the DBF bitfield of the MAC_FRAME_FILTER register. When set, + * the AFM module filters all incoming broadcast frames. In addition, it overrides + * all other filter settings. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableReceptionMulticastFrames(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_PM_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable reception of multicast frames
+ * + * \par + * The function disables the reception of multicast frames. When invoked, the AFM + * module passes all received broadcast frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableReceptionMulticastFrames(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_PM_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable promiscuous mode
+ * + * \par + * The function enables the promiscuous mode. In this mode, the address filter + * module passes all incoming frames regardless of its destination or source + * address. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnablePromiscuousMode(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_PR_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable promiscuous mode
+ * + * \par + * The function disables the promiscuous mode. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisablePromiscuousMode(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_PR_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable RX watchdog
+ * + * \par + * The function enables the RX watchdog by clearing the WD bitfield of the + * MAC_CONFIGURATION register. When invoked, the MAC does not allow more + * than 2048 bytes of the frame being received. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableRxWatchdog(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_WD_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable RX watchdog
+ * + * \par + * The function disables the RX watchdog by disabling the timer on the RX. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableRxWatchdog(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_WD_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable TX jabber
+ * + * \par + * When the function is invoked, the MAC cuts off the transmitter if the application + * sends out more than 2,048 bytes of data during transmission (10,240 bytes if + * jumbo frames are enabled) + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableTxJabber(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_JD_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable TX jabber
+ * + * \par + * When the function is invoked, the MAC disables the jabber timer on TX. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableTxJabber(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_JD_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Frame burst enable
+ * + * \par + * The function can be used to enable frame bursting during transmission in the + * MII half-duplex mode. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableFrameBurst(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_BE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Frame burst disable
+ * + * \par + * The function can be used to disable frame bursting. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableFrameBurst(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_BE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Jumbo frame enable
+ * + * \par + * The function can be used to enable jumbo frames. When enabled, the MAC allows + * jumbo frames of 9,018 bytes without reporting a giant frame error in the receive + * frame status. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableJumboFrame(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_JE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Jumbo frame disable
+ * + * \par + * The function can be used to disable jumbo frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableJumboFrame(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_JE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable receive own
+ * + * \par + * The function enables the MAC to receive all packets that are given by the PHY + * while transmitting. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableRxOwn(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_DO_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable receive own
+ * + * \par + * On invocation of the function, the MAC disables the reception of frames in the + * half-duplex mode. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableRxOwn(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_DO_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable loopback mode
+ * + * \par + * The function enables the MAC to operate in the loopback mode using the MII. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableLoopback(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_LM_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable loopback mode
+ * + * \par + * The function can be used to disable the loopback mode. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableLoopback(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_LM_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param speed The speed at which the link is set (10M or 100M?) + * @param duplex Duplex settings (half or full duplex?) + * @return None + * + * \parDescription:
+ * Set link
+ * + * \par + * The function sets the link speed and duplex settings. + */ +__STATIC_INLINE void XMC_ETH_MAC_SetLink(XMC_ETH_MAC_t *const eth_mac, + XMC_ETH_LINK_SPEED_t speed, + XMC_ETH_LINK_DUPLEX_t duplex) +{ + eth_mac->regs->MAC_CONFIGURATION = (eth_mac->regs->MAC_CONFIGURATION & + (uint32_t)~(ETH_MAC_CONFIGURATION_DM_Msk | ETH_MAC_CONFIGURATION_FES_Msk)) | + (uint32_t)speed | (uint32_t)duplex; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Return RX descriptor
+ * + * \par + * The function sets the specified DMA RX descriptor own bit. + */ +void XMC_ETH_MAC_ReturnRxDescriptor(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return bool true if RX descriptor is owned by DMA, false otherwise + * + * \parDescription:
+ * Is RX descriptor owned by DMA?
+ * + * \par + * The function checks if the RX descriptor is owned by the DMA. + */ +__STATIC_INLINE bool XMC_ETH_MAC_IsRxDescriptorOwnedByDma(XMC_ETH_MAC_t *const eth_mac) +{ + return ((eth_mac->rx_desc[eth_mac->rx_index].status & ETH_MAC_DMA_RDES0_OWN) != 0U); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Return TX descriptor
+ * + * \par + * The function sets the specified DMA TX descriptor own bit. + */ +void XMC_ETH_MAC_ReturnTxDescriptor(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return bool true if TX descriptor is owned by DMA, false otherwise + * + * \parDescription:
+ * Is TX descriptor owned by DMA?
+ * + * \par + * The function checks if the TX descriptor is owned by the DMA. + */ +__STATIC_INLINE bool XMC_ETH_MAC_IsTxDescriptorOwnedByDma(XMC_ETH_MAC_t *const eth_mac) +{ + return ((eth_mac->tx_desc[eth_mac->tx_index].status & ETH_MAC_DMA_TDES0_OWN) != 0U); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * ETH MAC Enable RX
+ * + * \par + * The function enables the receiver state machine of the MAC and puts the + * receive process in running state. The DMA then acquires the descriptor + * from the receive list and processes the received frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableRx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->OPERATION_MODE |= (uint32_t)ETH_OPERATION_MODE_SR_Msk; + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_RE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * ETH MAC Disable RX
+ * + * \par + * The function disables the receive process. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableRx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_RE_Msk; + eth_mac->regs->OPERATION_MODE &= (uint32_t)~ETH_OPERATION_MODE_SR_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * ETH MAC Enable TX
+ * + * \par + * The function enables the transmit state machine of the MAC and puts the + * transmit process in running state. The DMA then checks the TX list at the + * current position for transmitting a frame. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableTx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->OPERATION_MODE |= (uint32_t)ETH_OPERATION_MODE_ST_Msk; + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_TE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * ETH MAC Disable TX
+ * + * \par + * The function disables the transmit process. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableTx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_TE_Msk; + eth_mac->regs->OPERATION_MODE &= (uint32_t)~ETH_OPERATION_MODE_ST_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Flush TX
+ * + * \par + * The function initializes the TX DMA descriptors and enables the DMA transmission. + */ +void XMC_ETH_MAC_FlushTx(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Flush RX
+ * + * \par + * The function initializes the RX DMA descriptors and enables the DMA transmission. + */ +void XMC_ETH_MAC_FlushRx(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Resume TX
+ * + * \par + * Verbatim from the reference manual, the function enables the DMA to read the + * current descriptor pointed to by the "current host transmit descriptor" reg. + * If that descriptor is not available (owned by the CPU), the transmission + * returns to the suspend state else the transmission resumes. + */ +__STATIC_INLINE void XMC_ETH_MAC_ResumeTx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_TPS_Msk; + eth_mac->regs->TRANSMIT_POLL_DEMAND = 0U; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Resume RX
+ * + * \par + * Verbatim from the reference manual the function enables the DMA to read the + * current descriptor pointed to by the "current host transmit descriptor" reg. + * If that descriptor is not available (owned by the CPU), the transmission + * returns to the suspend state else the transmission resumes. + */ +__STATIC_INLINE void XMC_ETH_MAC_ResumeRx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_RU_Msk; + eth_mac->regs->RECEIVE_POLL_DEMAND = 0U; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return Pointer to current TX buffer + * + * \parDescription:
+ * Returns the current TX buffer. + */ +__STATIC_INLINE uint8_t *XMC_ETH_MAC_GetTxBuffer(XMC_ETH_MAC_t *const eth_mac) +{ + return (uint8_t *)(eth_mac->tx_desc[eth_mac->tx_index].buffer1); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return Pointer to current RX buffer + * + * \parDescription:
+ * Returns the current RX buffer. + */ +__STATIC_INLINE uint8_t *XMC_ETH_MAC_GetRxBuffer(XMC_ETH_MAC_t *const eth_mac) +{ + return (uint8_t *)(eth_mac->rx_desc[eth_mac->rx_index].buffer1); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param size Size of buffer + * @return None + * + * \parDescription:
+ * Sets the current TX buffer size. + */ +__STATIC_INLINE void XMC_ETH_MAC_SetTxBufferSize(XMC_ETH_MAC_t *const eth_mac, uint32_t size) +{ + eth_mac->tx_desc[eth_mac->tx_index].length = size; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param event A valid ETH PMT event (XMC_ETH_MAC_PMT_EVENT_t) or a valid combination + * of logically OR'd events + * @return None + * + * \parDescription:
+ * Enable power management event(s)
+ * + * \par + * The function enables the event(s) that trigger(s) a PMT interrupt. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnablePowerManagmentEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event) +{ + eth_mac->regs->PMT_CONTROL_STATUS |= (uint32_t)event; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param event A valid ETH PMT event (XMC_ETH_MAC_PMT_EVENT_t) or a valid combination + * of logically OR'd events + * @return None + * + * \parDescription:
+ * Disable power management event(s)
+ * + * \par + * The function disables the event(s) that trigger(s) a PMT interrupt. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisablePowerManagmentEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event) +{ + eth_mac->regs->PMT_CONTROL_STATUS &= ~(uint32_t)event; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param filter wake-up filter registers + * @return None + * + * \parDescription:
+ * Set wakeup frame filter
+ * + * \par + * The function populates the remote wakeup frame registers. + */ +void XMC_ETH_MAC_SetWakeUpFrameFilter(XMC_ETH_MAC_t *const eth_mac, + const uint32_t (*const filter)[XMC_ETH_WAKEUP_REGISTER_LENGTH]); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return bool true if the received packet is a magic packet, false otherwise + * + * \parDescription:
+ * Is magic packet received?
+ * + * \par + * The function checks if the packet received is a magic packet. + */ +__STATIC_INLINE bool XMC_ETH_MAC_IsMagicPacketReceived(XMC_ETH_MAC_t *const eth_mac) +{ + return (bool)(eth_mac->regs->PMT_CONTROL_STATUS & (uint32_t)ETH_PMT_CONTROL_STATUS_MGKPRCVD_Msk); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return bool true if the received packet is a wakeup frame, false otherwise + * + * \parDescription:
+ * Is wakeup frame received?
+ * + * \par + * The function checks if the packet received is a wakeup frame. + */ +__STATIC_INLINE bool XMC_ETH_MAC_IsWakeupFrameReceived(XMC_ETH_MAC_t *const eth_mac) +{ + return (bool)(eth_mac->regs->PMT_CONTROL_STATUS & (uint32_t)ETH_PMT_CONTROL_STATUS_RWKPRCVD_Msk); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable power down mode
+ * + * \par + * The function enables the power down mode of the ETH MAC. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnablePowerDownMode(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->PMT_CONTROL_STATUS |= (uint32_t)ETH_PMT_CONTROL_STATUS_PWRDWN_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable power down mode
+ * + * \par + * The function disables the power down mode of the ETH MAC. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisablePowerDownMode(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->PMT_CONTROL_STATUS &= ~(uint32_t)ETH_PMT_CONTROL_STATUS_PWRDWN_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param tag The (16 bit) VLAN tag to set + * @return None + * + * \parDescription:
+ * Set VLAN tag
+ * + * \par + * The function sets the VLAN tag to identify the VLAN frames. + */ +void XMC_ETH_MAC_SetVLANTag(XMC_ETH_MAC_t *const eth_mac, uint16_t tag); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param config The configuration the PTP should be configured with + * @return None + * + * \parDescription:
+ * Initialize PTP
+ * + * \par + * The function can be used to initialize PTP. + */ +void XMC_ETH_MAC_InitPTP(XMC_ETH_MAC_t *const eth_mac, uint32_t config); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param config Configuration of PTP module. See ::XMC_ETH_MAC_TIMESTAMP_CONFIG_t + * @param time Initialization time + * @return None + * + * \parDescription:
+ * Initialize PTP
+ * + * \par + * The function can be used to initialize PTP given a time parameter in addition + */ +void XMC_ETH_MAC_InitPTPEx(XMC_ETH_MAC_t *const eth_mac, uint32_t config, XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the PTP time + * @return None + * + * \parDescription:
+ * Get PTP time
+ * + * \par + * The function obtains the PTP time and writes the nanoseconds and seconds info + * to the 'time' argument. + */ +void XMC_ETH_MAC_GetPTPTime(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the PTP time + * @return None + * + * \parDescription:
+ * Get PTP time
+ * + * \par + * The function sets the PTP time give by the time parameter + */ +void XMC_ETH_MAC_SetPTPTime(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the PTP time + * @return None + * + * \parDescription:
+ * Update PTP time
+ * + * \par + * The function updates the PTP time with the nanoseconds and seconds info contained in + * the 'time' argument. + */ +void XMC_ETH_MAC_UpdatePTPTime(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the PTP time + * @return None + * + * \parDescription:
+ * Set PTP alarm
+ * + * \par + * The function programs the TARGET_TIME_NANOSECONDS and TARGET_TIME_SECONDS registers. It can + * be used to schedule an interrupt event triggered when the set alarm time limit is reached. + */ +void XMC_ETH_MAC_SetPTPAlarm(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enables timestamp interrupt
+ * + * \par + * The timestamp interrupt is generated when the System Time becomes greater than the value written + * in the Target Time register (Alarm). After the generation of the Timestamp Trigger Interrupt, the interrupt is disabled. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnablePTPAlarm(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSTRIG_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disables timestamp interrupt
+ * + * \par + * The timestamp interrupt is generated when the System Time becomes greater than the value written + * in the Target Time register (Alarm). After the generation of the Timestamp Trigger Interrupt, the interrupt is disabled. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisablePTPAlarm(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->TIMESTAMP_CONTROL &= (uint32_t)~ETH_TIMESTAMP_CONTROL_TSTRIG_Msk; +} + + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param addend Addend value + * @return None + * + * \parDescription:
+ * Adjust PTP clock
+ * + * \par + * The function is used to adjust the PTP clock (time synchronization) to compensate a reference clock drift. + */ +void XMC_ETH_MAC_UpdateAddend(XMC_ETH_MAC_t *const eth_mac, uint32_t addend); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param correction Correction factor + * @return None + * + * \parDescription:
+ * Adjust PTP clock
+ * + * \par + * The function can be used to adjust the PTP clock (time synchronization). Please see the + * function implementation for more information. + */ +void XMC_ETH_MAC_AdjustPTPClock(XMC_ETH_MAC_t *const eth_mac, uint32_t correction); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return uint32_t Timestamp status + * + * \parDescription:
+ * Get PTP status
+ * + * \par + * The function returns the timestamp status by reading the TIMESTAMP_STATUS register. + * As indicated in the reference manual, all bits of the TIMESTAMP_STATUS register (except + * bits [27:25]) are cleared after the invocation of this function. + */ +uint32_t XMC_ETH_MAC_GetPTPStatus(const XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the RX timestamp + * @return XMC_ETH_MAC_STATUS_t ETH MAC status + * + * \parDescription:
+ * Get RX timestamp
+ * + * \par + * The function can be used to get the RX timestamp. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_GetRxTimeStamp(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the TX timestamp + * @return XMC_ETH_MAC_STATUS_t ETH MAC status + * + * \parDescription:
+ * Get TX timestamp
+ * + * \par + * The function can be used to get the TX timestamp. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_GetTxTimeStamp(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param event Which event (or a combination of logically OR'd events) needs to be enabled? + * @return None + * + * \parDescription:
+ * Enable ETH MAC event(s)
+ * + * \par + * The function can be used to enable ETH MAC event(s). + */ +void XMC_ETH_MAC_EnableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param event Which event (or a combination of logically OR'd events) needs to be disabled? + * @return None + * + * \parDescription:
+ * Disable an ETH MAC event(s)
+ * + * \par + * The function can be used to disable ETH MAC event(s). + */ +void XMC_ETH_MAC_DisableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param event The status of which event (or a combination of logically OR'd events) needs to be cleared + * @return None + * + * \parDescription:
+ * Clear event status
+ * + * \par + * The function clears the status of an event passed as a parameter to the function. + */ +void XMC_ETH_MAC_ClearEventStatus(XMC_ETH_MAC_t *const eth_mac, uint32_t event); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return uint32_t Event status + * + * \parDescription:
+ * Get event status
+ * + * \par + * The function returns the ETH status and interrupt status as a single word. The user + * can then check the status of the events by using an appropriate mask. + */ +uint32_t XMC_ETH_MAC_GetEventStatus(const XMC_ETH_MAC_t *const eth_mac); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (ETH0) */ + +#endif /* XMC_ETH_MAC_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eth_mac_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eth_mac_map.h new file mode 100644 index 00000000..eb41fb92 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eth_mac_map.h @@ -0,0 +1,166 @@ +/** + * @file xmc_eth_mac_map.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial
+ * + * @endcond + */ + +#ifndef XMC_ETH_MAC_MAP_H +#define XMC_ETH_MAC_MAP_H + +/** + * ETH MAC interface mode + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_MODE +{ + XMC_ETH_MAC_PORT_CTRL_MODE_MII = 0x0U, /**< MII mode */ + XMC_ETH_MAC_PORT_CTRL_MODE_RMII = 0x1U /**< RMII mode */ +} XMC_ETH_MAC_PORT_CTRL_MODE_t; + +/** + * ETH MAC receive data 0 line + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_RXD0 +{ + XMC_ETH_MAC_PORT_CTRL_RXD0_P2_2 = 0U, /**< RXD0A receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD0_P0_2 = 1U, /**< RXD0B receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD0_P14_8 = 2U, /**< RXD0C receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD0_P5_0 = 3U /**< RXD0D receive data line */ +} XMC_ETH_MAC_PORT_CTRL_RXD0_t; + +/** + * ETH MAC receive data 1 line + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_RXD1 +{ + XMC_ETH_MAC_PORT_CTRL_RXD1_P2_3 = 0U, /**< RXD1A receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD1_P0_3 = 1U, /**< RXD1B receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD1_P14_9 = 2U, /**< RXD1C receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD1_P5_1 = 3U /**< RXD1D receive data line */ +} XMC_ETH_MAC_PORT_CTRL_RXD1_t; + +/** + * ETH MAC receive data 2 line + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_RXD2 +{ + XMC_ETH_MAC_PORT_CTRL_RXD2_P5_8 = 0U, /**< RXD2A receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD2_P6_4 = 1U /**< RXD2B receive data line */ +} XMC_ETH_MAC_PORT_CTRL_RXD2_t; + +/** + * ETH MAC receive data 3 line + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_RXD3 +{ + XMC_ETH_MAC_PORT_CTRL_RXD3_P5_9 = 0U, /**< RXD3A Receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD3_P6_3 = 1U /**< RXD3B Receive data line */ +} XMC_ETH_MAC_PORT_CTRL_RXD3_t; + +/** + * ETH MAC PHY clock + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_RMII +{ + XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P2_1 = 0U, /**< XMC_ETH_RMIIA PHY clock */ + XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P0_0 = 1U, /**< XMC_ETH_RMIIB PHY clock */ + XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P15_8 = 2U, /**< XMC_ETH_RMIIC PHY clock */ + XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P6_5 = 3U /**< XMC_ETH_RMIID PHY clock */ +} XMC_ETH_MAC_PORT_CTRL_CLK_RMII_t; + +/** + * ETH MAC carrier sense data valid + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_CRS_DV +{ + XMC_ETH_MAC_PORT_CTRL_CRS_DV_P2_5 = 0U, /**< XMC_ETH_CRS_DVA carrier sense data valid */ + XMC_ETH_MAC_PORT_CTRL_CRS_DV_P0_1 = 1U, /**< XMC_ETH_CRS_DVB carrier sense data valid */ + XMC_ETH_MAC_PORT_CTRL_CRS_DV_P15_9 = 2U, /**< XMC_ETH_CRS_DVC carrier sense data valid */ + XMC_ETH_MAC_PORT_CTRL_CRS_DV_P5_2 = 3U /**< XMC_ETH_CRS_DVD carrier sense data valid */ +} XMC_ETH_MAC_PORT_CTRL_CRS_DV_t; + +/** + * ETH MAC carrier sense + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_CRS +{ + XMC_ETH_MAC_PORT_CTRL_CRS_P5_11 = 0U, /**< XMC_ETH_CRSA carrier sense */ + XMC_ETH_MAC_PORT_CTRL_CRS_P5_4 = 3U /**< XMC_ETH_CRSD carrier sense */ +} XMC_ETH_MAC_PORT_CTRL_CRS_t; + +/** + * ETH MAC receive error + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_RXER +{ + XMC_ETH_MAC_PORT_CTRL_RXER_P2_4 = 0U, /**< XMC_ETH_RXERA carrier sense */ + XMC_ETH_MAC_PORT_CTRL_RXER_P0_11 = 1U, /**< XMC_ETH_RXERB carrier sense */ + XMC_ETH_MAC_PORT_CTRL_RXER_P5_3 = 3U /**< XMC_ETH_RXERD carrier sense */ +} XMC_ETH_MAC_PORT_CTRL_RXER_t; + +/** + * ETH MAC collision detection + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_COL +{ + XMC_ETH_MAC_PORT_CTRL_COL_P2_15 = 0U, /**< XMC_ETH_COLA collision detection */ + XMC_ETH_MAC_PORT_CTRL_COL_P5_5 = 3U /**< XMC_ETH_COLD collision detection */ +} XMC_ETH_MAC_PORT_CTRL_COL_t; + +/** + * ETH PHY transmit clock + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_TX +{ + XMC_ETH_MAC_PORT_CTRL_CLK_TX_P5_10 = 0U, /**< XMC_ETH_CLK_TXA PHY transmit clock */ + XMC_ETH_MAC_PORT_CTRL_CLK_TX_P6_6 = 1U /**< XMC_ETH_CLK_TXB PHY transmit clock */ +} XMC_ETH_MAC_PORT_CTRL_CLK_TX_t; + +/** + * ETH management data I/O + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_MDIO +{ + XMC_ETH_MAC_PORT_CTRL_MDIO_P0_9 = 0U, /**< XMC_ETH_MDIOA management data I/O */ + XMC_ETH_MAC_PORT_CTRL_MDIO_P2_0 = 1U, /**< XMC_ETH_MDIOB management data I/O */ + XMC_ETH_MAC_PORT_CTRL_MDIO_P1_11 = 2U /**< XMC_ETH_MDIOC management data I/O */ +} XMC_ETH_MAC_PORT_CTRL_MDIO_t; + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eth_phy.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eth_phy.h new file mode 100644 index 00000000..081370e4 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_eth_phy.h @@ -0,0 +1,222 @@ +/** + * @file xmc_eth_phy.h + * @date 2015-12-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * + * 2015-12-15: + * - Added XMC_ETH_PHY_ExitPowerDown and XMC_ETH_PHY_Reset + * + * @endcond + */ + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup ETH_PHY + * @brief Ethernet PHY driver for XMC4000 microcontroller family. + * + * The XMC_ETH_PHY low level driver provides functions used by XMC_ETH_MAC. + * @{ + */ + +#ifndef XMC_ETH_PHY_H +#define XMC_ETH_PHY_H + +/******************************************************************************* + * INCLUDES + *******************************************************************************/ + +#include + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * ETH PHY status returns + */ +typedef enum XMC_ETH_PHY_STATUS +{ + XMC_ETH_PHY_STATUS_OK = 0U, /**< OK. All is well! */ + XMC_ETH_PHY_STATUS_BUSY = 1U, /**< Busy */ + XMC_ETH_PHY_STATUS_ERROR = 2U, /**< Error */ + XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID = 3U, /**< Error in device identifier */ + XMC_ETH_PHY_STATUS_ERROR_TIMEOUT = 4U /**< Time-out error */ +} XMC_ETH_PHY_STATUS_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ + +/** + * ETH PHY configuration + */ +typedef struct XMC_ETH_PHY_CONFIG +{ + XMC_ETH_LINK_INTERFACE_t interface; /**< Link interface */ + XMC_ETH_LINK_SPEED_t speed; /**< ETH speed: 100M or 10M? */ + XMC_ETH_LINK_DUPLEX_t duplex; /**< Half or full duplex? */ + bool enable_auto_negotiate; /**< Enable auto-negotiate? */ + bool enable_loop_back; /**< Enable loop-back? */ +} XMC_ETH_PHY_CONFIG_t; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @param config A constant pointer to XMC_ETH_PHY_CONFIG_t, pointing to a physical layer config + * @return int32_t return status XMC_ETH_PHY_STATUS_t + * + * \parDescription:
+ * Initialize the ETH physical layer interface
+ * + * \par + * The function sets the link speed, applies the duplex mode, sets auto-negotiation + * and loop-back settings. + */ +int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return int32_t return status XMC_ETH_PHY_STATUS_t + * + * \parDescription:
+ * Enter power down mode
+ * + */ +int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return int32_t return status XMC_ETH_PHY_STATUS_t + * + * \parDescription:
+ * Exit power down mode
+ * + */ +int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return int32_t return status XMC_ETH_PHY_STATUS_t + * + * \parDescription:
+ * Reset transciver
+ * + */ +int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return XMC_ETH_LINK_STATUS_t ETH link status + * + * \parDescription:
+ * Get link status
+ * + * \par + * The function reads the physical layer interface and returns the link status. + * It returns either ::XMC_ETH_LINK_STATUS_UP or ::XMC_ETH_LINK_STATUS_DOWN. + */ +XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return XMC_ETH_LINK_SPEED_t ETH link speed + * + * \parDescription:
+ * Get link speed
+ * + * \par + * The function reads the physical layer interface and returns the link speed. + * It returns either ::XMC_ETH_LINK_SPEED_100M or ::XMC_ETH_LINK_SPEED_10M. + */ +XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return XMC_ETH_LINK_DUPLEX_t ETH link duplex settings + * + * \parDescription:
+ * Get link duplex settings
+ * + * \par + * The function reads the physical layer interface and returns the link duplex settings. + * It returns either ::XMC_ETH_LINK_DUPLEX_FULL or ::XMC_ETH_LINK_DUPLEX_HALF. + */ +XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return bool True if autonegotiation process is finished otherwise false + * + * \parDescription:
+ * Get status of autonegotiation
+ */ +bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XMC_ETH_PHY_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_fce.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_fce.h new file mode 100644 index 00000000..08d52888 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_fce.h @@ -0,0 +1,697 @@ +/** + * @file xmc_fce.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial + * + * 2015-05-20: + * - Description updated
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * @endcond + * + */ + +#ifndef XMC_FCE_H +#define XMC_FCE_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ + +#include + +#if defined (FCE) + +/** + * @addtogroup XMClib + * @{ + */ + +/** + * @addtogroup FCE + * @brief Flexible CRC Engine(FCE) driver for the XMC microcontroller family. + * + * The FCE provides a parallel implementation of Cyclic Redundancy Code (CRC) + * algorithms. The current FCE version for the XMC4000 microcontroller family implements the + * IEEE 802.3 ethernet CRC32, the CCITT CRC16 and the SAE J1850 CRC8 polynomials. + * The primary target of FCE is to be used as an hardware acceleration engine for software + * applications or operating systems services using CRC signatures. + * + * @image html fce_overview.png + * @image latex ../images/fce_overview.png + * FCE Features:
+ * @image html fce_polynomials.png + * @image latex ../images/fce_polynomials.png + * * CRC kernel 0 and 1: IEEE 802.3 CRC32 ethernet polynomial: 0x04C11DB71
+ * * CRC kernel 2: CCITT CRC16 polynomial: 0x1021
+ * * CRC kernel 3: SAE J1850 CRC8 polynomial: 0x1D
+ * * Configuration Registers enable to control the CRC operation and perform automatic checksum checks at + * the end of a message.
+ * * Extended register interface to control reliability of FCE execution in safety applications.
+ * * Error notification scheme via dedicated interrupt node for:
+ a)Transient error detection: Error interrupt generation (maskable) with local status register + (cleared by software)
+ b)Checksum failure: Error interrupt generation (maskable) with local status register (cleared by software)
+ + FCE provides one interrupt line to the interrupt system. Each CRC engine has its own set of flag registers.
+ + * @{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +#define XMC_FCE_CRC32_0 FCE_KE0 /**< Kernel 0
*/ +#define XMC_FCE_CRC32_1 FCE_KE1 /**< Kernel 1
*/ +#define XMC_FCE_CRC16 FCE_KE2 /**< Kernel 2
*/ +#define XMC_FCE_CRC8 FCE_KE3 /**< Kernel 3
*/ + +#define XMC_FCE_REFIN_SET (1U) /**< Enables input reflection */ +#define XMC_FCE_REFIN_RESET (0U) /**< Disables input reflection */ +#define XMC_FCE_REFOUT_SET (1U) /**< Enables output reflection */ +#define XMC_FCE_REFOUT_RESET (0U) /**< Disables output reflection */ +#define XMC_FCE_INVSEL_SET (1U) /**< Enables output inversion */ +#define XMC_FCE_INVSEL_RESET (0U) /**< Disables output inversion */ + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + +/** + * FCE interrupt configuration + */ +typedef enum XMC_FCE_CONFIG_INTERRUPT +{ + XMC_FCE_CFG_CONFIG_CMI = FCE_KE_CFG_CMI_Msk, /**< Enables CRC Mismatch interrupt \n*/ + XMC_FCE_CFG_CONFIG_CEI = FCE_KE_CFG_CEI_Msk, /**< Enables Configuration error interrupt \n*/ + XMC_FCE_CFG_CONFIG_LEI = FCE_KE_CFG_LEI_Msk, /**< Enables Length error interrupt \n*/ + XMC_FCE_CFG_CONFIG_BEI = FCE_KE_CFG_BEI_Msk /**< Enables Bus error interrupt \n*/ +} XMC_FCE_CONFIG_INTERRUPT_t; + +/** + * FCE operation configuration + */ +typedef enum XMC_FCE_CONFIG_OPERATION +{ + XMC_FCE_CFG_CONFIG_CCE = FCE_KE_CFG_CCE_Msk, /**< Enables CRC check */ + XMC_FCE_CFG_CONFIG_ALR = FCE_KE_CFG_ALR_Msk /**< Enables Automatic length reload */ +} XMC_FCE_CONFIG_OPERATION_t; + +/** + * FCE algorithm configuration + */ +typedef enum XMC_FCE_CONFIG_ALGO +{ + XMC_FCE_CFG_CONFIG_REFIN = FCE_KE_CFG_REFIN_Msk, /**< Enables input byte reflection */ + XMC_FCE_CFG_CONFIG_REFOUT = FCE_KE_CFG_REFOUT_Msk, /**< Enables Final CRC reflection */ + XMC_FCE_CFG_CONFIG_XSEL = FCE_KE_CFG_XSEL_Msk /**< Enables output inversion */ +} XMC_FCE_CONFIG_ALGO_t; + +/** + * FCE status flag configuration + */ +typedef enum XMC_FCE_STS_FLAG +{ + XMC_FCE_STS_MISMATCH_CRC = FCE_KE_STS_CMF_Msk, /**< CRC Mismatch flag */ + XMC_FCE_STS_CONFIG_ERROR = FCE_KE_STS_CEF_Msk, /**< Configuration Error flag */ + XMC_FCE_STS_LENGTH_ERROR = FCE_KE_STS_LEF_Msk, /**< Length Error flag */ + XMC_FCE_STS_BUS_ERROR = FCE_KE_STS_BEF_Msk /**< Bus Error flag */ +} XMC_FCE_STS_FLAG_t; + +/** + * FCE control configuration + */ +typedef enum XMC_FCE_CTR_TEST +{ + XMC_FCE_CTR_MISMATCH_CRC = FCE_KE_CTR_FCM_Msk, /**< Forces CRC mismatch */ + XMC_FCE_CTR_MISMATCH_CFG = FCE_KE_CTR_FRM_CFG_Msk, /**< Forces CFG Register mismatch */ + XMC_FCE_CTR_MISMATCH_CHECK = FCE_KE_CTR_FRM_CHECK_Msk /**< Forces CRC Check Register mismatch */ +} XMC_FCE_CTR_TEST_t; + +/** + * FCE status enumeration + */ +typedef enum XMC_FCE_STATUS +{ + XMC_FCE_STATUS_OK = 0, /**< Returns OK on success */ + XMC_FCE_STATUS_BUSY, /**< Returns BUSY when API is busy with a previous request */ + XMC_FCE_STATUS_ERROR /**< Returns ERROR when API cannot fulfil request */ +} XMC_FCE_STATUS_t; + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ + +/** + * FCE kernel + */ +typedef FCE_KE_TypeDef XMC_FCE_Kernel_t; + +/* Anonymous structure/union guard start */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__TASKING__) + #pragma warning 586 +#endif + +/** + * @brief XMC_FCE configuration structure + */ +typedef struct XMC_FCE_CONFIG +{ + union + { + uint32_t regval; + struct + { + uint32_t : 8; + uint32_t config_refin : 1; /**< Enables byte-wise reflection */ + uint32_t config_refout : 1; /**< Enables bit-wise reflection */ + uint32_t config_xsel : 1; /**< Enables output inversion */ + uint32_t : 21; /**< Reserved bits */ + }; + }; +} XMC_FCE_CONFIG_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__TASKING__) + #pragma warning restore +#endif + +/** + * FCE handler + */ +typedef struct XMC_FCE +{ + XMC_FCE_Kernel_t *kernel_ptr; /**< FCE Kernel Pointer */ + XMC_FCE_CONFIG_t fce_cfg_update; /**< FCE CFG register update */ + uint32_t seedvalue; /**< CRC seed value to be used */ +} XMC_FCE_t; + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param None + * @return uint32_t Module revision number + * + * \parDescription:
+ * Read FCE module revision number
+ * + * \par + * The value of a module revision starts with 0x01 (first revision). The current revision + * number is 0x01. + */ +__STATIC_INLINE uint32_t XMC_FCE_ReadModuleRev(void) +{ + return (uint32_t)(FCE->ID & FCE_ID_MOD_REV_Msk); +} + +/** + * @param None + * @return uint32_t Module type + * + * \parDescription:
+ * Read the FCE module type
+ * + * \par + * The return value is currently 0xC0. It defines the module as a 32-bit module. + */ +__STATIC_INLINE uint32_t XMC_FCE_ReadModuleType(void) +{ + return (uint32_t)((FCE->ID & FCE_ID_MOD_TYPE_Msk) >> FCE_ID_MOD_TYPE_Pos); +} + +/** + * @param None + * @return uint32_t Module number + * + * \parDescription:
+ * Read FCE module number
+ * + * \par + * The return value for FCE module is currently 0x00CA. + */ +__STATIC_INLINE uint32_t XMC_FCE_ReadModuleNumber(void) +{ + return ((uint32_t)((FCE->ID & FCE_ID_MOD_NUMBER_Msk) >> FCE_ID_MOD_NUMBER_Pos)); +} + +/** + * @param None + * @return bool Disable status + * + * + * \parDescription:
+ * Return the disable status
+ * + * \par + * The function reads the FCE module disable status (DISS) bit. It returns "true" if + * set, "false" otherwise. + */ +__STATIC_INLINE bool XMC_FCE_Get_DisableStatus(void) +{ + return (bool)(FCE->CLC &= (uint32_t)~FCE_CLC_DISS_Msk); +} + +/** + * @param None + * @return None + * + * \parDescription:
+ * Disable the FCE module
+ * + * \par + * The function asserts the FCE peripheral reset and sets the DISR bit in the CLC + * register. + * + * \parNote:
+ * All pending transactions running on the bus slave interface must be completed before + * entering the disabled state. + */ +void XMC_FCE_Disable(void); + +/** + * @param None + * @return None + * + * \parDescription:
+ * Enable the FCE module
+ * + * \par + * The function de-asserts the peripheral reset and clears the DISR bit CLC register. + */ +void XMC_FCE_Enable(void); + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @return ::XMC_FCE_STATUS_t + * + * \parDescription:
+ * Initialize the FCE engine
+ * + * \par + * The function sets to the CFG and CRC registers with the FCE configuration and + * seeds values. The function always returns XMC_FCE_STATUS_SUCCESS. + * + * \parNote:
+ * The software must first ensure that the CRC kernel is properly configured with the + * initial CRC value (seed value). + */ +XMC_FCE_STATUS_t XMC_FCE_Init(const XMC_FCE_t *const engine); + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param seedvalue Initial CRC value + * @return None + * + * \parDescription:
+ * Initialize FCE seed value + * + * \par + * The function sets the initial CRC (seed) value in the CRC register. + */ +__STATIC_INLINE void XMC_FCE_InitializeSeedValue(const XMC_FCE_t *const engine, uint32_t seedvalue) +{ + engine->kernel_ptr->CRC = seedvalue; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param event OR'd values of ::XMC_FCE_CONFIG_INTERRUPT_t enumeration values + * @return None + * + * \parDescription:
+ * Enable FCE event(s)
+ * + * \par + * The function sets the CFG register to enable FCE event(s). + */ +__STATIC_INLINE void XMC_FCE_EnableEvent(const XMC_FCE_t *const engine, uint32_t event) +{ + engine->kernel_ptr->CFG |= (uint32_t)event; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param event OR'd values of ::XMC_FCE_CONFIG_INTERRUPT_t enumeration values + * @return None + * + * \parDescription:
+ * Disable FCE event(s)
+ * + * \par + * The function clears the CFG register to disable FCE event(s). + */ +__STATIC_INLINE void XMC_FCE_DisableEvent(const XMC_FCE_t *const engine, uint32_t event) +{ + engine->kernel_ptr->CFG &= ~(uint32_t)event; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param event Event of type ::XMC_FCE_STS_FLAG_t + * @return bool + * + * \parDescription:
+ * Return the event status of FCE event
+ * + * \par + * The function returns the status of a single requested FCE event by reading the + * appropriate bit-fields of the STS register. + */ +__STATIC_INLINE bool XMC_FCE_GetEventStatus(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event) +{ + return (bool) (engine->kernel_ptr->STS & (uint32_t)event); +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param event Event of type ::XMC_FCE_STS_FLAG_t + * @return None + * + * \parDescription:
+ * Clear an FCE event
+ * + * \par + * The function clears requested FCE events by setting the bit-fields of the STS + * register. + */ +__STATIC_INLINE void XMC_FCE_ClearEvent(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event) +{ + engine->kernel_ptr->STS |= (uint32_t)event; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param operation FCE operation of type ::XMC_FCE_CONFIG_OPERATION_t + * @return None + * + * \parDescription:
+ * Enable CRC operations
+ * + * \par + * The function enables FRC operations by writing to the CFG register. + * + * \parNote:
+ * CRC comparison check (at the end of message) can be enabled using the CCE bit-field. + * Automatic reload of LENGTH field (at the end of message) can be enabled using the + * ALR bit field. + */ +__STATIC_INLINE void XMC_FCE_EnableOperation(const XMC_FCE_t *const engine, uint32_t operation) +{ + engine->kernel_ptr->CFG |= operation; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param operation FCE operation of type ::XMC_FCE_CONFIG_OPERATION_t + * @return None + * + * \parDescription:
+ * Disable CRC operations
+ * + * \par + * The function disables FRC operations by writing to the CFG register. + * + * \parNote:
+ * CRC comparison check (at the end of message) can be disabled using the CCE bit-field. + * Automatic reload of LENGTH field (at the end of message) can be disabled using the + * ALR bit field. + */ +__STATIC_INLINE void XMC_FCE_DisableOperation(const XMC_FCE_t *const engine, uint32_t operation) +{ + engine->kernel_ptr->CFG &= ~(uint32_t)operation; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param algo A valid algorithm of type ::XMC_FCE_CONFIG_ALGO_t or a valid combination + * of logically OR'd algorithms + * @return None + * + * \parDescription:
+ * Enables CRC algorithm(s)
+ * + * \parNote:
+ * Options for enabling CRC algorithm:
+ * REFIN: Input byte wise reflection
+ * REFOUT: Output bit wise reflection
+ * XSEL: Value to be XORed with final CRC
+ */ +__STATIC_INLINE void XMC_FCE_EnableCRCAlgorithm(const XMC_FCE_t *const engine, uint32_t algo) +{ + engine->kernel_ptr->CFG |= (uint32_t)algo; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param algo A valid algorithm of type ::XMC_FCE_CONFIG_ALGO_t or a valid combination + * of logically OR'd algorithms + * @return None + * + * \parDescription:
+ * Disable CRC algorithm(s)
+ * + * \parNote:
+ * Options for disabling CRC algorithm:
+ * REFIN: Input byte wise reflection
+ * REFOUT: Output bit wise reflection
+ * XSEL: Value to be XORed with final CRC
+ */ +__STATIC_INLINE void XMC_FCE_DisableCRCAlgorithm(const XMC_FCE_t *const engine, uint32_t algo) +{ + engine->kernel_ptr->CFG &= ~(uint32_t)algo; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param checkvalue Checksum value + * @return None + * + * \parDescription:
+ * Updates CRC check value
+ * + * \par + * When the CFG.CCE bit field is set, every time the IR register is written, the + * LENGTH register is decremented by one until it reaches zero. The hardware monitors + * the transition of the LENGTH register from 1 to 0 to detect the end of the + * message and proceed with the comparison of the result register (RES) value with + * the CHECK register value. + */ +__STATIC_INLINE void XMC_FCE_UpdateCRCCheck(const XMC_FCE_t *const engine, const uint32_t checkvalue) +{ + engine->kernel_ptr->CHECK = 0xFACECAFEU; + engine->kernel_ptr->CHECK = checkvalue; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param checklength Checksum length + * @return None
+ * + * \parDescription:
+ * Updates CRC length specified in the input parameter
+ * + * \par + * When the ALR bit field is set to 1, every write to the IR register decrements + * the value of the LENGTH bit field. The LENGTH field shall be reloaded with its + * configuration value at the end of the cycle where LENGTH reaches 0. + */ +__STATIC_INLINE void XMC_FCE_UpdateLength(const XMC_FCE_t *const engine, const uint32_t checklength) +{ + engine->kernel_ptr->LENGTH = 0xFACECAFEU; + engine->kernel_ptr->LENGTH = checklength; +} + +/** + * @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address + * @param data Pointer to the data buffer + * @param length Total number of bytes of data buffer + * @param result Pointer to computed CRC result + * @return XMC_FCE_STATUS_ERROR on error + * @return XMC_FCE_STATUS_SUCCESS otherwise. + * + * \parDescription:
+ * Calculate and updates the CRC8 checksum in the result pointer
+ * + * \parNote:
+ * A write to IRm (m = 3) triggers the CRC kernel to update the message checksum + * according to the IR and current CRC register contents. Any write transaction + * is allowed to this IRm register. Only the lower 8-bit of the write transactions + * will be used. ::XMC_FCE_GetCRCResult() should be called after invoking + * ::XMC_FCE_CalculateCRC8() to get final CRC value. + */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine, + const uint8_t *data, + uint32_t length, + uint8_t *result); + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param data Pointer to the data buffer + * @param length Length of data buffer + * @param result Pointer to computed CRC result + * @return XMC_FCE_STATUS_ERROR on error + * @return XMC_FCE_STATUS_SUCCESS otherwise. + * + * \parDescription:
+ * Calculate and update the RC16 checksum in the result pointer
+ * + * \parNote:
+ * A write to Internal Register (IRm m = 2) triggers the CRC kernel to update the + * message checksum according to the IR and current CRC register contents. Only 32-bit + * or 16-bit write transactions are permitted. Any other bus write transaction will + * lead to a bus error. Only the lower 16-bit of the write transactions will be used. + * ::XMC_FCE_GetCRCResult() should be called after ::XMC_FCE_CalculateCRC16() to get + * final CRC value. + */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine, + const uint16_t *data, + uint32_t length, + uint16_t *result); + +/** + * @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address + * @param data Pointer to the data buffer + * @param length Total number of bytes of data buffer + * @param result Pointer to computed CRC result + * @return XMC_FCE_STATUS_ERROR on error + * @return XMC_FCE_STATUS_SUCCESS otherwise. + * + * \parDescription
+ * Calculate and update the calculated CRC32 checksum in the result pointer
+ * + * \parNote:
+ * A write to Internal Register (IRm, m = 0-1) triggers the CRC kernel to update + * the message checksum according to the IR and current CRC register contents. Only + * 32-bit write transactions are permitted. Any other bus write transaction will + * lead to a bus error. ::XMC_FCE_GetCRCResult() should be called after + * ::XMC_FCE_CalculateCRC32() to get final CRC value. + */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine, + const uint32_t *data, + uint32_t length, + uint32_t *result); + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param result Pointer to CRC result + * @return None + * + * \parDescription:
+ * Read the final CRC value from RES register
+ */ +__STATIC_INLINE void XMC_FCE_GetCRCResult(const XMC_FCE_t *const engine, uint32_t *result) +{ + *result= engine->kernel_ptr->RES; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param test values of type ::XMC_FCE_CTR_TEST_t + * @return None + * + * \parDescription:
+ * Trigger the CTR register to generate a CRC mismatch/register mismatch/check register + * mismatch interrupt
+ */ +void XMC_FCE_TriggerMismatch(const XMC_FCE_t *const engine, XMC_FCE_CTR_TEST_t test); + +/** + * @param inbuffer Pointer to input data buffer + * @param outbuffer Pointer to the output data buffer + * @param length Length of the input buffer + * @return None + * + * \parDescription:
+ * Convert input data buffer's endianness from big endian to little endian
+ * + * \par + * The function stores the converted data in output data buffer. + * + * \parNote:
+ * This function should be invoked before using ::XMC_FCE_CalculateCRC16() to compute + * the CRC value. + */ +void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t length); + +/** + * @param inbuffer Pointer to input data buffer + * @param outbuffer Pointer to the output data buffer + * @param length Length of the input buffer + * @return None + * + * \parDescription:
+ * Convert input data buffer's endianness from big endian to little endian
+ * + * \par + * The function stores the converted data in output data buffer. + * + * \parNote:
+ * This function should be invoked before using ::XMC_FCE_CalculateCRC32() to compute + * the CRC value. + */ +void XMC_FCE_LittleEndian32bit(uint8_t* inbuffer, uint32_t* outbuffer, uint16_t length); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FCE) */ + +#endif /* XMC_FCE_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_flash.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_flash.h new file mode 100644 index 00000000..355dc3b5 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_flash.h @@ -0,0 +1,276 @@ +/** + * @file xmc_flash.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2014-12-10: + * - Initial
+ * 2015-02-20: + * - Updated for Documentation related changes
+ * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * @endcond + * + */ + + +#ifndef XMC_FLASH_H +#define XMC_FLASH_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_common.h" + +#if UC_FAMILY == XMC1 + #include "xmc1_flash.h" +#endif + +#if UC_FAMILY == XMC4 + #include "xmc4_flash.h" +#endif + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup FLASH + * @brief Flash driver for XMC microcontroller family. + * + * Flash is a non volatile memory module used to store instruction code or constant data. + * The flash low level driver provides support to the following functionalities of flash memory.
+ *
    + * \if XMC4 + *
  1. Provides function to program a page. ( XMC_FLASH_ProgramPage() )

    2. + *
  2. Provides functions to support read and write protection. ( XMC_FLASH_InstallProtection(), + * XMC_FLASH_ConfirmProtection(), XMC_FLASH_VerifyReadProtection(), XMC_FLASH_VerifyWriteProtection() )

    3. + *
  3. Provides function to erase sector. ( XMC_FLASH_EraseSector() )

    4. + * \endif + * \if XMC1 + *
  4. Provides functions to program and verify pages. ( XMC_FLASH_ProgramPage(), XMC_FLASH_ProgramPages() + * XMC_FLASH_ProgramVerifyPage() )

    5. + *
  5. Provides functions to write and verify blocks. ( XMC_FLASH_WriteBlocks(), XMC_FLASH_VerifyBlocks() )

    6. + *
  6. Provides functions to read data in terms of word and blocks. ( XMC_FLASH_ReadBlocks(), XMC_FLASH_ReadWord() ) + *

    7. + *
  7. Provides function to erase page. ( XMC_FLASH_ErasePage() )

    8. + * \endif + *
+ * @{ + */ + +/******************************************************************************* + * API PROTOTYPE + *******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * \if XMC1 + * Clears the previous error status by reseting the ECC and VERR error status bits of NVMSTATUS register.\n\n + * Call this API before starting any flash programming / erase related APIs to ensure all previous errors are cleared. + * \endif + * \if XMC4 + * Clears the previous error status by reseting the FSR status register.\n\n Call this API before starting any flash + * programming / erase related APIs to ensure all previous errors are cleared. + * \endif + * + * \parRelated APIs:
+ * None + * + */ +void XMC_FLASH_ClearStatus(void); + +/** + * + * @param None + * + * @return uint32_t Status of the previous flash operation. + * + * \parDescription:
+ * \if XMC1 + * Informs the status of flash by reading the NVMSTATUS register.\n\n It indicates the ECC, VERR(verification error), + * WRPERR (Write protocol error) errors as well as the current flash state. After calling the flash read/write/erase + * operation related APIs, call this API to get the verification status. The return value of this API shall be checked + * against the members of @ref XMC_FLASH_STATUS_t enumeration to get the relevant status. + * \endif + * \if XMC4 + * Informs the status of flash by reading the FSR register.\n\n It indicates the error status such as PFOPER, SQER, + * PROER, PFDBER, ORIER, VER errors as well as the current flash state. After calling the flash read/write/erase + * operation related APIs, call this API to verify flash status. The return value of this API shall be checked against + * the members of @ref XMC_FLASH_STATUS_t enumeration to get the relevant status. + * \endif + * + * \parRelated APIs:
+ * None + * + */ +uint32_t XMC_FLASH_GetStatus(void); + +/** + * + * @param event_msk ORed values of @ref XMC_FLASH_EVENT_t enumeration + * + * @return None + * + * \parDescription:
+ * Enables the particular flash events as specified in the input parameter.\n + * + * \parRelated APIs:
+ * XMC_FLASH_DisableEvent()\n\n\n + * + */ +void XMC_FLASH_EnableEvent(const uint32_t event_msk); + +/** + * + * @param event_msk ORed values of @ref XMC_FLASH_EVENT_t enumeration + * + * @return None + * + * \parDescription:
+ * Disables the particular flash events as specified in the input parameter.\n + * + * \parRelated APIs:
+ * XMC_FLASH_EnableEvent()\n\n\n + * + */ +void XMC_FLASH_DisableEvent(const uint32_t event_msk); + +/** + * + * @param address Pointer to the starting address of flash page from where the programming starts. + * @param data Pointer to the source address where targeted data is located. + * + * @return None + * + * \parDescription:
+ * \if XMC1 + * Programs a single flash page associated with the specified \a address.\n\n XMC1000 Flash can be programmed with one + * page (256 bytes) using this API. It calls the Flash Firmware routine \a XMC1000_NvmProgVerify(unsigned long pageAddr) + * to perform the programming. Refer XMC1000 reference manual of for more details on flash firmware routines + * (Section 25.3). Call XMC_FLASH_GetStatus() API after calling this API, to verify the programming operation. + * \endif + * \if XMC4 + * Programs a single flash page associated with the specified \a address.\n\n XMC4000 flash can be programmed with a + * granularity of 256 bytes page using this API. Before entering into page write process, it clears the error status + * bits inside status register. It starts the write process by issuing the page mode command followed by the load page + * command which loads the targeted \a data blocks into internal assembly buffer. Finally, it issues the write page + * command which programs the \a data into flash. Call XMC_FLASH_GetStatus() API after calling this API, to verify the + * programming operation.\n + * \endif + * + * \parNote:
+ * Flash will be busy state during write is ongoing, hence no operations allowed until it completes. + * + * \parRelated APIs:
+ * None + * + */ +void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data); + +/** + * + * @param address Pointer to the starting address of the page to be erased. + * + * @return None + * + * \parDescription:
+ * \if XMC1 + * Erases a complete sector starting from the \a address specified.\n\n XMC1000 Flash can be erased with granularity + * of one page = 16 blocks of 16 Bytes = 256 Bytes using this API. It internally calls XMC_FLASH_ErasePages API 16 + * times starting from the first page of the sector.. Call XMC_FLASH_GetStatus() API after calling this API, + * to verify the erase operation.\n + * \endif + * + * \if XMC4 + * Erases a sector associated with the specified \a address.\n\n Before erase, it clears the error status bits inside + * FSR status register. Issues the erase sector command sequence with the specified starting \a address to start flash + * erase process. Call XMC_FLASH_GetStatus() API after calling this API, to verify the erase operation.\n + * \endif + * \if XMC1 + * \parRelated APIs:
+ * XMC_FLASH_ErasePages() \n\n\n + * \endif + * \if XMC4 + * \parRelated APIs:
+ * None + * \endif + */ +void XMC_FLASH_EraseSector(uint32_t *address); + +/** + * + * @param None + * + * @return true if flash is in busy state else returns \a false. + * + * \parDescription:
+ * Checks whether flash is in busy state or not.\n\n It is checked by calling the XMC_FLASH_GetStatus() API internally. + * Refer XMC_FLASH_GetStatus() for more details.\n + * + * \parRelated APIs:
+ * XMC_FLASH_GetStatus()\n\n\n + * + */ +__STATIC_INLINE bool XMC_FLASH_IsBusy(void) +{ + return (bool)(XMC_FLASH_GetStatus() & XMC_FLASH_STATUS_BUSY); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_gpio.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_gpio.h new file mode 100644 index 00000000..671cdc0b --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_gpio.h @@ -0,0 +1,478 @@ +/** + * @file xmc_gpio.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * - Documentation improved
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * @endcond + * + */ + +#ifndef XMC_GPIO_H +#define XMC_GPIO_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_common.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup GPIO + * @brief General Purpose Input Output (GPIO) driver for the XMC microcontroller family. + * + * GPIO driver provide a generic and very flexible software interface for all standard digital I/O port pins. + * Each port slice has individual interfaces for the operation as General Purpose I/O and it further provides the + * connectivity to the on-chip periphery and the control for the pad characteristics. + * + * The driver is divided into Input and Output mode. + * + * Input mode features: + * -# Configuration structure XMC_GPIO_CONFIG_t and initialization function XMC_GPIO_Init() + * -# Allows the selection of weak pull-up or pull-down device. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() + * \if XMC1 + * -# Allows the selection of input hysteresis. XMC_GPIO_SetInputHysteresis() + * \endif + * + * + * Output mode features: + * -# Allows the selection of push pull/open drain and Alternate output. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() + * \if XMC4 + * -# Allows the selection of pad driver strength. Configuration structure XMC_GPIO_OUTPUT_STRENGTH_t and function XMC_GPIO_SetOutputStrength() + * \endif + * + * -# Allows the selection of initial output level. Configuration structure XMC_GPIO_OUTPUT_LEVEL_t and function XMC_GPIO_SetOutputLevel() + * + *@{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +#define PORT_IOCR_PC_Pos PORT0_IOCR0_PC0_Pos +#define PORT_IOCR_PC_Msk PORT0_IOCR0_PC0_Msk + +#define PORT_IOCR_PC_Size (8U) + + +#define XMC_GPIO_CHECK_OUTPUT_LEVEL(level) ((level == XMC_GPIO_OUTPUT_LEVEL_LOW) || \ + (level == XMC_GPIO_OUTPUT_LEVEL_HIGH)) + +#define XMC_GPIO_CHECK_HWCTRL(hwctrl) ((hwctrl == XMC_GPIO_HWCTRL_DISABLED) || \ + (hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL1) || \ + (hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL2)) + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + + +/** + * Defines output level of a pin. Use type \a XMC_GPIO_OUTPUT_LEVEL_t for this enum. + */ +typedef enum XMC_GPIO_OUTPUT_LEVEL +{ + XMC_GPIO_OUTPUT_LEVEL_LOW = 0x10000U, /**< Reset bit */ + XMC_GPIO_OUTPUT_LEVEL_HIGH = 0x1U, /**< Set bit */ +} XMC_GPIO_OUTPUT_LEVEL_t; + +/** + * Defines direct hardware control characteristics of the pin . Use type \a XMC_GPIO_HWCTRL_t for this enum. + */ +typedef enum XMC_GPIO_HWCTRL +{ + XMC_GPIO_HWCTRL_DISABLED = 0x0U, /**< Software control only */ + XMC_GPIO_HWCTRL_PERIPHERAL1 = 0x1U, /**< HWI0/HWO0 control path can override the software configuration */ + XMC_GPIO_HWCTRL_PERIPHERAL2 = 0x2U /**< HWI1/HWO1 control path can override the software configuration */ +} XMC_GPIO_HWCTRL_t; + +/********************************************************************************************************************** + * DEVICE FAMILY EXTENSIONS + *********************************************************************************************************************/ + + #if UC_FAMILY == XMC1 +#include "xmc1_gpio.h" +#elif UC_FAMILY == XMC4 +#include "xmc4_gpio.h" +#else +#error "xmc_gpio.h: family device not supported" +#endif + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @param port Constant pointer pointing to GPIO port, to access port registers like Pn_OUT,Pn_OMR,Pn_IOCR etc. + * @param pin Port pin number. + * @param config GPIO configuration data structure. Refer data structure @ref XMC_GPIO_CONFIG_t for details. + * + * @return None + * + * \parDescription:
+ * \if XMC1 + * Initializes input / output mode settings like, pull up / pull down devices,hysteresis, push pull /open drain. + * Also configures alternate function outputs and clears hardware port control for a selected \a port \a and \a pin. + * \a config provides selected I/O settings. It configures hardware registers Pn_IOCR,Pn_OUT, Pn_OMR,Pn_PDISC and Pn_PHCR. + * \endif + * \if XMC4 + * Initializes input / output mode settings like, pull up / pull down devices,push pull /open drain, and pad driver mode. + * Also configures alternate function outputs and clears hardware port control for selected \a port and \a pin . + * It configures hardware registers Pn_IOCR,Pn_OUT,Pn_OMR,Pn_PDISC and Pn_PDR.\n + * \endif + * + * \parRelated APIs:
+ * None + * + * \parNote:
+ * This API is called in definition of DAVE_init by code generation and therefore should not be explicitly called + * for the normal operation. Use other APIs only after DAVE_init is called successfully (returns DAVE_STATUS_SUCCESS). + * + * + */ + + +void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config); + +/** + * + * @param port Constant pointer pointing to GPIO port, to access hardware register Pn_IOCR. + * @param pin Port pin number. + * @param mode input / output functionality selection. Refer @ref XMC_GPIO_MODE_t for valid values. + * + * @return None + * + * \parDescription:
+ * Sets digital input and output driver functionality and characteristics of a GPIO port pin. It configures hardware + * registers Pn_IOCR. \a mode is initially configured during initialization in XMC_GPIO_Init(). Call this API to alter + * the port direction functionality as needed later in the program. + * + * \parRelated APIs:
+ * None + * + */ + +void XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode); + + +/** + * + * @param port Constant pointer pointing to GPIO port, to access hardware register Pn_OMR. + * @param pin Port pin number. + * @param level output level selection. Refer @ref XMC_GPIO_OUTPUT_LEVEL_t for valid values. + * + * @return None + * + * \parDescription:
+ * Set port pin output level to high or low.It configures hardware registers Pn_OMR.\a level is initially + * configured during initialization in XMC_GPIO_Init(). Call this API to alter output level as needed later in the program. + * + * \parRelated APIs:
+ * XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow(). + * + * \parNote:
+ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). + * + */ + + +__STATIC_INLINE void XMC_GPIO_SetOutputLevel(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_OUTPUT_LEVEL_t level) +{ + XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); + XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid output level", XMC_GPIO_CHECK_OUTPUT_LEVEL(level)); + + port->OMR = (uint32_t)level << pin; +} + + +/** + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. + * @param pin Port pin number. + * + * @return None + * + * \parDescription:
+ * Sets port pin output to high. It configures hardware registers Pn_OMR. + * + * \parRelated APIs:
+ * XMC_GPIO_SetOutputLow() + * + * \parNote:
+ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().\n + * Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0. + * + */ + +__STATIC_INLINE void XMC_GPIO_SetOutputHigh(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_SetOutputHigh: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); + + port->OMR = (uint32_t)0x1U << pin; +} + +/** + * + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. + * @param pin port pin number. + * + * @return None + * + *\parDescription:
+ * Sets port pin output to low. It configures hardware registers Pn_OMR.\n + * + * \parRelated APIs:
> + * XMC_GPIO_SetOutputHigh() + * + *\parNote:
+ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). + * Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0.\n + * + */ + +__STATIC_INLINE void XMC_GPIO_SetOutputLow(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_SetOutputLow: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); + + port->OMR = 0x10000U << pin; +} + +/** + * + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. + * @param pin port pin number. + * + * @return None + * + * \parDescription:
+ * Configures port pin output to Toggle. It configures hardware registers Pn_OMR. + * + * \parRelated APIs:
+ * XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow(). + * + * \parNote:
+ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). Register Pn_OMR is virtual + * and does not contain any flip-flop. A read action delivers the value of 0. + * + */ + +__STATIC_INLINE void XMC_GPIO_ToggleOutput(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_ToggleOutput: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); + + port->OMR = 0x10001U << pin; +} + +/** + * + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_IN. + * @param pin Port pin number. + * + * @return uint32_t pin logic level status. + * + *\parDescription:
+ * Reads the Pn_IN register and returns the current logical value at the GPIO pin. + * + * \parRelated APIs:
+ * None + * + * \parNote:
+ * Prior to this api, user has to configure port pin to input mode using XMC_GPIO_SetMode(). + * + */ + +__STATIC_INLINE uint32_t XMC_GPIO_GetInput(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_GetInput: Invalid port", XMC_GPIO_CHECK_PORT(port)); + + return (((port->IN) >> pin) & 0x1U); +} + +/** + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS. + * @param pin port pin number. + * + * @return None + * + * \parDescription:
+ * Enables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller enters + * Deep Sleep mode.Port pin enabled with power save mode option are set to a defined state and the input Schmitt-Trigger + * as well as the output driver stage are switched off. By default port pin does not react to power save mode request. + * + * \parRelated APIs:
+ * XMC_GPIO_DisablePowerSaveMode() + * + * Note:
+ * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so + * may result in an undefined behavior of the pin when the device enters the Deep Sleep state. + * + */ + + +__STATIC_INLINE void XMC_GPIO_EnablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_EnablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port)); + + port->PPS |= (uint32_t)0x1U << pin; +} + + +/** + * + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS. + * @param pin port pin number. + * + * @return None + * + * \parDescription:
+ * Disables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller enters + * Deep Sleep mode. This configuration enables input Schmitt-Trigger and output driver stage(if pin is enabled power + * save mode previously). By default port \a pin does not react to power save mode request. + * + * \parRelated APIs:
+ * XMC_GPIO_EnablePowerSaveMode() + * + *\parNote:
+ * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so + * may result in an undefined behavior of the pin when the device enters the Deep Sleep state. + * + */ + +__STATIC_INLINE void XMC_GPIO_DisablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_DisablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port)); + + port->PPS &= ~(uint32_t)((uint32_t)0x1U << pin); +} + + +/** + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_HWSEL. + * @param pin port pin number. + * @param hwctrl direct hardware control selection. Refer @ref XMC_GPIO_HWCTRL_t for valid values. + * + * @return None + * + * \parDescription:
+ * Selects direct hard ware control and configures Pn_HWSEL register.This configuration is useful for the port pins + * overlaid with peripheral functions for which the connected peripheral needs hardware control. + * + * \parRelated APIs:
+ * None + * + *\parNote:
+ * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). + * Doing so may result in an undefined behavior of the pin when the device enters the Deep Sleep state. + * + */ + +void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl); + + +/** + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC. + * @param pin port pin number. + * + * @return None + * + * \parRelated APIs:
+ * None + * + * \parDescription:
+ * Enable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only for + * analog port pins. + * + */ +__STATIC_INLINE void XMC_GPIO_EnableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port)); + + port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin); +} + + +/** + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC. + * @param pin port pin number. + * + * @return None + * + * \parRelated APIs:
+ * None + * + * \parDescription:
+ * Disable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only + * for analog port pins. + * + */ + +__STATIC_INLINE void XMC_GPIO_DisableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port)); + + port->PDISC |= (uint32_t)0x1U << pin; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} (end addtogroup GPIO) + */ + +/** + * @} (end addtogroup XMClib) + */ + +#endif /* XMC_GPIO_H */ + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_hrpwm.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_hrpwm.h new file mode 100644 index 00000000..655ef047 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_hrpwm.h @@ -0,0 +1,2317 @@ + +/** + * @file xmc_hrpwm.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Driver description updated
+ * - API's are renamed
+ * XMC_HRPWM_HRC_SetResolutionCR1() -> XMC_HRPWM_HRC_SetCompare1()
+ * XMC_HRPWM_HRC_SetResolutionCR2() -> XMC_HRPWM_HRC_SetCompare2()
+ * XMC_HRPWM_HRC_SetDeadTimeDCF() -> XMC_HRPWM_HRC_SetDeadTimeFalling()
+ * XMC_HRPWM_HRC_SetDeadTimeDCR() -> XMC_HRPWM_HRC_SetDeadTimeRising()
+ * + * 2015-05-12: + * - XMC_HRPWM_CSG_SelClampingInput() api is added to select the clamping input
+ * - Enum XMC_HRPWM_SHADOW_TX_t is renamed to XMC_HRPWM_SHADOW_TX_DAC_t to represent that shadow transfer is for DAC
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * - Updated copyright and change history section. + * + * @endcond + * + */ + +#ifndef HRPWM_H +#define HRPWM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** + * HEADER FILES + **********************************************************************************************************************/ +#include + +#if defined(HRPWM0) +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup HRPWM + * @brief High Resolution PWM Unit (HRPWM) driver for the XMC microcontroller family.
+ * + * The HRPWM extends the capabilities of the associated Capture/Compare Unit(CCU8), that simplifies the design various of SMPS. + * It allows easy and fast implementation of control loop, reduced total number of external components, avoid susceptibility + * to environmental and process variations there by reducing the size of the power supply.
+ * + *Comparator Slope Generator(CSG)
+ * HRPWM module consists 3 Comparator Slope Generator(CSG) units. Each CSG unit comprised of one High Speed Comparator, + * a dedicated 10 bit 30 MS/s DAC and one hardware controlled Slope Compensation module.
+ * + * CSG features include:
+ *
    + *
  1. 3 High Speed Comparators, that can be use to compare an external signal against the DAC value
    + *
  2. 3 (30MS/s) 10 bit DAC
    + *
  3. 3 Slope generation blocks, that are used to generate the DAC input value
    + *
  4. different slope generations schemes, for a flexible and automated DAC voltage generation
    + *
  5. 2 DAC reference values, to allow flexible hysteretic mode control
    + *
  6. Input multiplexer for the inverting comparator input, allowing several analog inputs to be connected to each comparator and also dynamic input switching.
    + *
  7. blanking compare mode, to avoid premature switch OFF due to noise
    + *
  8. a dedicated output per Comparator
    + *
  9. programmable clock prescaler
    + *
  10. programmable clock pulse swallower for slope linearization with uneven clock scale
    + *
  11. different slope generation schemes:
    + * – incrementing mode
    + * – decrementing mode
    + * – triangular mode
    + *
  12. shadow transfer for one DAC reference value
    + *
  13. external trigger for the DAC
    + *
  14. external control for the DAC reference values
    + *
  15. four dedicated service request lines
    + *
+ * + *High Resolution Channel unit(HRC)
+ * It also has 4 High Resolution Channel unit(HRC) that upgrades 4 compare channels of a Capture/Compare unit (CCU8), enabling + * generation of PWM with 150ps resolution. ie; the rise time and/or fall time of PWM can be changed in steps of 150ps.
+ * + * HRC features include:
+ *
    + *
  1. Upgrade up to 4 PWM signals of CCU8 outputs for high resolution positioning.
    + *
  2. Independent control of PWM set and reset.
    + *
  3. Delay the PWM rise time in steps of 150ps. This does not insert dead time.
    + *
  4. Extent the fall time of PWM in steps of 150ps. This does not insert dead time.
    + *
  5. Dead time insertion on complementary signals
    + *
  6. Passive level selection on outputs.
    + *
+ * @{ + */ +/*********************************************************************************************************************** + * MACROS + ********************************************************************************************************************/ +#define XMC_HRPWM_CSG0_MEMORY_ADDRESS 0x40020A40 /* CSG0 memory location */ +#define XMC_HRPWM_CSG1_MEMORY_ADDRESS 0x40020B40 /* CSG1 memory location */ +#define XMC_HRPWM_CSG2_MEMORY_ADDRESS 0x40020C40 /* CSG2 memory location */ + +#define XMC_HRPWM_COMPARATOR_STATUS (HRPWM0_CSGTRSG_D0STE_Msk + HRPWM0_CSGTRSG_D1STE_Msk + HRPWM0_CSGTRSG_D2STE_Msk) + +#define XMC_HRPWM_CHECK_MODULE_PTR(PTR) ((PTR)== HRPWM0) +#define XMC_HRPWM_CHECK_HRC_PTR(PTR) ( ((PTR)== HRPWM0_HRC0) || ((PTR)== HRPWM0_HRC1) || ((PTR)== HRPWM0_HRC2) || ((PTR)== HRPWM0_HRC3) ) +#define XMC_HRPWM_CHECK_CSG_PTR(PTR) ( ((PTR)== HRPWM0_CSG0) || ((PTR)== HRPWM0_CSG1) || ((PTR)== HRPWM0_CSG2) ) + +/*********************************************************************************************************************** + * ENUMS - General + **********************************************************************************************************************/ +/** + * Return HRPWM driver status + */ +typedef enum XMC_HRPWM_STATUS +{ + XMC_HRPWM_STATUS_OK = 0U, /**< Driver successfully completed the request */ + XMC_HRPWM_STATUS_BUSY, /**< Driver busy, cannot handle request */ + XMC_HRPWM_STATUS_ERROR /**< Driver cannot fulfill request, error occurred */ +} XMC_HRPWM_STATUS_t; + +/*********************************************************************************************************************** + * ENUMS - HRPWM + **********************************************************************************************************************/ +/** + * HRPWM module clock frequency + */ +typedef enum XMC_HRPWM_CLK_FREQ +{ + XMC_HRPWM_CLK_FREQ_NONE = 0U, /**< No clock frequency is selected */ + XMC_HRPWM_CLK_FREQ_180MHZ, /**< Module clock frequency is 180MHz */ + XMC_HRPWM_CLK_FREQ_120MHZ, /**< Module clock frequency is 120MHz */ + XMC_HRPWM_CLK_FREQ_80MHZ /**< Module clock frequency is 80MHz */ +} XMC_HRPWM_CLK_FREQ_t; + +/*********************************************************************************************************************** + * ENUMS - HRPWM HRC + **********************************************************************************************************************/ +/** + * HRPWM HRC High Resolution mode configuration + */ +typedef enum XMC_HRPWM_HRC_HR_EDGE +{ + XMC_HRPWM_HRC_HR_EDGE_SEL_RISING = 0U, /**< Rising edge high resolution signal positioning enabled */ + XMC_HRPWM_HRC_HR_EDGE_SEL_FALLING, /**< Falling edge high resolution signal positioning enabled */ + XMC_HRPWM_HRC_HR_EDGE_SEL_BOTH, /**< Both edges high resolution signal positioning enabled */ + XMC_HRPWM_HRC_HR_EDGE_SEL_NONE /**< No high resolution signal positioning */ +} XMC_HRPWM_HRC_HR_EDGE_t; + +/** + * HRPWM HRC source selector input + */ +typedef enum XMC_HRPWM_HRC_SRC_INPUT +{ + XMC_HRPWM_HRC_SRC_INPUT_CCU = 0U, /**< Source selector is controlled via CCU timer signal */ + XMC_HRPWM_HRC_SRC_INPUT_CSG /**< Source selector is controlled via CSG output signal */ +} XMC_HRPWM_HRC_SRC_INPUT_t; + +/** + * HRPWM HRC source selector - connection of source selector to which CSG unit + */ +typedef enum XMC_HRPWM_HRC_CMP_SEL +{ + XMC_HRPWM_HRC_CMP_SEL_CSG0 = 0U, /**< Comparator output of CSG0 selected */ + XMC_HRPWM_HRC_CMP_SEL_CSG1, /**< Comparator output of CSG1 selected */ + XMC_HRPWM_HRC_CMP_SEL_CSG2 /**< Comparator output of CSG2 selected */ +} XMC_HRPWM_HRC_CMP_SEL_t; + +/** + * HRPWM HRC source selector - connection of source selector to which CCU timer + */ +typedef enum XMC_HRPWM_HRC_TIMER_SEL +{ + XMC_HRPWM_HRC_TIMER_SEL_CCU_CC0 = 0U, /**< CCU timer 0 selected */ + XMC_HRPWM_HRC_TIMER_SEL_CCU_CC1, /**< CCU timer 1 selected */ + XMC_HRPWM_HRC_TIMER_SEL_CCU_CC2, /**< CCU timer 2 selected */ + XMC_HRPWM_HRC_TIMER_SEL_CCU_CC3 /**< CCU timer 3 selected */ +} XMC_HRPWM_HRC_TIMER_SEL_t; + +/** + * HR source selector edge configuration (GSEL) + */ +typedef enum XMC_HRPWM_HRC_SRC_EDGE_SEL +{ + XMC_HRPWM_HRC_SRC_EDGE_SEL_DISABLED = 0U, /**< source signal generation disabled */ + XMC_HRPWM_HRC_SRC_EDGE_SEL_RISING, /**< source signal generation on rising edge */ + XMC_HRPWM_HRC_SRC_EDGE_SEL_FALLING, /**< source signal generation on falling edge */ + XMC_HRPWM_HRC_SRC_EDGE_SEL_BOTH /**< source signal generation on both edges */ +} XMC_HRPWM_HRC_SRC_EDGE_SEL_t; + +/** + * HRPWM function Enable / Disable status + */ +typedef enum XMC_HRPWM_FUNC_STATUS +{ + XMC_HRPWM_FUNC_STATUS_DISABLE = 0U, /**< Function is disabled */ + XMC_HRPWM_FUNC_STATUS_ENABLE = 1U /**< Function is enabled */ +} XMC_HRPWM_FUNC_STATUS_t; + +/** + * HRPWM high resolution module status + */ +typedef enum XMC_HRPWM_HR_LOGIC +{ + XMC_HRPWM_HR_LOGIC_NOT_WORKING = 0U, /**< High resolution signal path is switched off for all HRC channels */ + XMC_HRPWM_HR_LOGIC_WORKING /**< High resolution signal path is switched on for all HRC channels */ +} XMC_HRPWM_HR_LOGIC_t; + +/** + * High resolution paths for HRC channels + */ +typedef enum XMC_HRPWM_HR_PATH +{ + XMC_HRPWM_HR_PATH_HRC0 = HRPWM0_HRCCFG_HRC0E_Msk, /**< HRC0 path selected for High resolution */ + XMC_HRPWM_HR_PATH_HRC1 = HRPWM0_HRCCFG_HRC1E_Msk, /**< HRC1 path selected for High resolution */ + XMC_HRPWM_HR_PATH_HRC2 = HRPWM0_HRCCFG_HRC2E_Msk, /**< HRC2 path selected for High resolution */ + XMC_HRPWM_HR_PATH_HRC3 = HRPWM0_HRCCFG_HRC3E_Msk, /**< HRC3 path selected for High resolution */ +} XMC_HRPWM_HR_PATH_t; + +/** + * @brief Low resolution paths for HRC channels + */ +typedef enum XMC_HRPWM_LR_PATH +{ + XMC_HRPWM_LR_PATH_HRC0 = HRPWM0_HRCCFG_LRC0E_Msk, /**< LRC0 path selected for Low resolution */ + XMC_HRPWM_LR_PATH_HRC1 = HRPWM0_HRCCFG_LRC1E_Msk, /**< LRC0 path selected for Low resolution */ + XMC_HRPWM_LR_PATH_HRC2 = HRPWM0_HRCCFG_LRC2E_Msk, /**< LRC0 path selected for Low resolution */ + XMC_HRPWM_LR_PATH_HRC3 = HRPWM0_HRCCFG_LRC3E_Msk /**< LRC0 path selected for Low resolution */ +} XMC_HRPWM_LR_PATH_t; + +/** + * Shadow transfer for HRC values + * The enum is used to access the bitfields of registers HRCSTRG, HRCCTRG, HRCSTSG + */ +typedef enum XMC_HRPWM_HRC_SHADOW_TX +{ + XMC_HRPWM_HRC_SHADOW_TX_HRC0_VALUE = 0x1U, /**< HRC0 shadow transfer mask for CR1 & CR2 */ + XMC_HRPWM_HRC_SHADOW_TX_HRC0_DT_VALUE = 0x2U, /**< HRC0 shadow transfer mask for DCR & DCRF */ + XMC_HRPWM_HRC_SHADOW_TX_HRC1_VALUE = 0x10U, /**< HRC1 shadow transfer mask for CR1 & CR2 */ + XMC_HRPWM_HRC_SHADOW_TX_HRC1_DT_VALUE = 0x20U, /**< HRC1 shadow transfer mask for DCR & DCRF */ + XMC_HRPWM_HRC_SHADOW_TX_HRC2_VALUE = 0x100U, /**< HRC2 shadow transfer mask for CR1 & CR2 */ + XMC_HRPWM_HRC_SHADOW_TX_HRC2_DT_VALUE = 0x200U, /**< HRC2 shadow transfer mask for DCR & DCRF */ + XMC_HRPWM_HRC_SHADOW_TX_HRC3_VALUE = 0x1000U, /**< HRC3 shadow transfer mask for CR1 & CR2 */ + XMC_HRPWM_HRC_SHADOW_TX_HRC3_DT_VALUE = 0x2000U /**< HRC3 shadow transfer mask for DCR & DCRF */ +} XMC_HRPWM_HRC_SHADOW_TX_t; + +/** + * HR source selector + */ +typedef enum XMC_HRPWM_HRC_SOURCE +{ + XMC_HRPWM_HRC_SOURCE_0 = 0U, /**< High resolution source 0 */ + XMC_HRPWM_HRC_SOURCE_1 /**< High resolution source 1 */ +} XMC_HRPWM_HRC_SOURCE_t; + +/** + * HRC dead time shadow transfer trigger selection + */ +typedef enum XMC_HRPWM_HRC_DT_TR_SEL +{ + XMC_HRPWM_HRC_DT_TR_SEL_TIMER = 0U, /**< Source for shadow transfer trigger is CCU8 timer. */ + XMC_HRPWM_HRC_DT_TR_SEL_OVERFLOW /**< Source for shadow transfer trigger is dead time timer overflow. */ +} XMC_HRPWM_HRC_DT_TR_SEL_t; + +/** + * HRPWM HRC output - Passive level + */ +typedef enum XMC_HRPWM_HRC_OUT_PASSIVE_LVL +{ + XMC_HRPWM_HRC_OUT_PASSIVE_LVL_LOW = 0U, /**< Passive low output */ + XMC_HRPWM_HRC_OUT_PASSIVE_LVL_HIGH /**< Passive high output */ +} XMC_HRPWM_HRC_OUT_PASSIVE_LVL_t; + +/*********************************************************************************************************************** + * ENUMS - HRPWM CSG + **********************************************************************************************************************/ +/** + * CSG power modes + */ + typedef enum XMC_HRPWM_CSG_POWER_MODE +{ + XMC_HRPWM_CSG_POWER_MODE_OFF = 0U << HRPWM0_CSGCFG_C0PM_Pos, /**< Comparator slope generator turned off */ + XMC_HRPWM_CSG_POWER_MODE_LOW_SPEED = 1U << HRPWM0_CSGCFG_C0PM_Pos, /**< Comparator slope generator in low speed mode */ + XMC_HRPWM_CSG_POWER_MODE_HI_SPEED = 3U << HRPWM0_CSGCFG_C0PM_Pos /**< Comparator slope generator in high speed mode */ +} XMC_HRPWM_CSG_POWER_MODE_t; + +/** + * DAC, Comparator start controls & Comparator clamped state control + * The enum is used to access the bitfields of registers CSGSETG, CSGCLRG, CSGSTATG + */ +typedef enum XMC_HRPWM_CSG_RUN_BIT +{ + XMC_HRPWM_CSG_RUN_BIT_DAC0 = 0x1U, /**< Start DAC0 */ + XMC_HRPWM_CSG_RUN_BIT_CMP0 = 0x2U, /**< Start comparator 0 */ + XMC_HRPWM_CSG_RUN_BIT_CMP0_PSL = 0x4U, /**< Set comparator 0 output to clamped state */ + XMC_HRPWM_CSG_RUN_BIT_DAC1 = 0x10U, /**< Start DAC1 */ + XMC_HRPWM_CSG_RUN_BIT_CMP1 = 0x20U, /**< Start comparator 1 */ + XMC_HRPWM_CSG_RUN_BIT_CMP1_PSL = 0x40U, /**< Set comparator 1 output to clamped state */ + XMC_HRPWM_CSG_RUN_BIT_DAC2 = 0x100U, /**< Start DAC2 */ + XMC_HRPWM_CSG_RUN_BIT_CMP2 = 0x200U, /**< Start comparator2 */ + XMC_HRPWM_CSG_RUN_BIT_CMP2_PSL = 0x400U /**< Set comparator 2 output to clamped state */ +} XMC_HRPWM_CSG_RUN_BIT_t; + +/** + * Slope start for DAC units + */ +typedef enum XMC_HRPWM_CSG_SLOPE_START +{ + XMC_HRPWM_CSG_SLOPE_START_DAC0 = HRPWM0_CSGFCG_S0STR_Msk, /**< Start slope generation for DAC0 */ + XMC_HRPWM_CSG_SLOPE_START_DAC1 = HRPWM0_CSGFCG_S1STR_Msk, /**< Start slope generation for DAC1 */ + XMC_HRPWM_CSG_SLOPE_START_DAC2 = HRPWM0_CSGFCG_S2STR_Msk /**< Start slope generation for DAC2 */ +} XMC_HRPWM_CSG_SLOPE_START_t; + +/** + * Slope stop for DAC units + */ +typedef enum XMC_HRPWM_CSG_SLOPE_STOP +{ + XMC_HRPWM_CSG_SLOPE_STOP_DAC0 = HRPWM0_CSGFCG_S0STP_Msk, /**< Stop slope generation for DAC0 */ + XMC_HRPWM_CSG_SLOPE_STOP_DAC1 = HRPWM0_CSGFCG_S1STP_Msk, /**< Stop slope generation for DAC1 */ + XMC_HRPWM_CSG_SLOPE_STOP_DAC2 = HRPWM0_CSGFCG_S2STP_Msk /**< Stop slope generation for DAC2 */ +} XMC_HRPWM_CSG_SLOPE_STOP_t; + +/** + * Prescaler start in CSG + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_START +{ + XMC_HRPWM_CSG_PRESCALER_START_CSG0 = HRPWM0_CSGFCG_PS0STR_Msk, /**< Start prescaler of CSG0 */ + XMC_HRPWM_CSG_PRESCALER_START_CSG1 = HRPWM0_CSGFCG_PS1STR_Msk, /**< Start prescaler of CSG1 */ + XMC_HRPWM_CSG_PRESCALER_START_CSG2 = HRPWM0_CSGFCG_PS2STR_Msk /**< Start prescaler of CSG2 */ +} XMC_HRPWM_CSG_PRESCALER_START_t; + +/** + * Prescaler stop in CSG + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_STOP +{ + XMC_HRPWM_CSG_PRESCALER_STOP_CSG0 = HRPWM0_CSGFCG_PS0STP_Msk, /**< Stop prescaler of CSG0 */ + XMC_HRPWM_CSG_PRESCALER_STOP_CSG1 = HRPWM0_CSGFCG_PS1STP_Msk, /**< Stop prescaler of CSG1 */ + XMC_HRPWM_CSG_PRESCALER_STOP_CSG2 = HRPWM0_CSGFCG_PS2STP_Msk /**< Stop prescaler of CSG2 */ +} XMC_HRPWM_CSG_PRESCALER_STOP_t; + +/** + * Clear prescaler in CSG + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_CLR +{ + XMC_HRPWM_CSG_PRESCALER_CLR_CSG0 = HRPWM0_CSGFCG_PS0CLR_Msk, /**< Clear prescaler of CSG0 */ + XMC_HRPWM_CSG_PRESCALER_CLR_CSG1 = HRPWM0_CSGFCG_PS1CLR_Msk, /**< Clear prescaler of CSG1 */ + XMC_HRPWM_CSG_PRESCALER_CLR_CSG2 = HRPWM0_CSGFCG_PS2CLR_Msk /**< Clear prescaler of CSG2 */ +} XMC_HRPWM_CSG_PRESCALER_CLR_t; + +/** + * DAC slope generation status + */ +typedef enum XMC_HRPWM_DAC_SLOPE_GEN_STATUS +{ + XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC0 = HRPWM0_CSGFSG_S0RB_Msk, /**< Slope generation status mask for DAC0 */ + XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC1 = HRPWM0_CSGFSG_S1RB_Msk, /**< Slope generation status mask for DAC1 */ + XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC2 = HRPWM0_CSGFSG_S2RB_Msk /**< Slope generation status mask for DAC2 */ +} XMC_HRPWM_DAC_SLOPE_GEN_STATUS_t; + +/** + * CSG prescaler status + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_STATUS +{ + XMC_HRPWM_CSG_PRESCALER_STATUS_CSG0 = HRPWM0_CSGFSG_P0RB_Msk, /**< Prescaler status in CSG0 */ + XMC_HRPWM_CSG_PRESCALER_STATUS_CSG1 = HRPWM0_CSGFSG_P1RB_Msk, /**< Prescaler status in CSG1 */ + XMC_HRPWM_CSG_PRESCALER_STATUS_CSG2 = HRPWM0_CSGFSG_P2RB_Msk /**< Prescaler status in CSG2 */ +} XMC_HRPWM_CSG_PRESCALER_STATUS_t; + +/** + * Comparator inputs + */ +typedef enum XMC_HRPWM_CSG_CMP_INPUT +{ + XMC_HRPWM_CSG_CMP_INPUT_CINA = 0U, /**< Input for comparator is CINA */ + XMC_HRPWM_CSG_CMP_INPUT_CINB /**< Input for comparator is CINB */ +} XMC_HRPWM_CSG_CMP_INPUT_t; + +/** + * CSG comparator input switch request + */ +typedef enum XMC_HRPWM_CSG_SWITCH_CMP_INPUT +{ + XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP0 = HRPWM0_CSGTRSG_SW0ST_Msk, /**< Request to switch the analog input connected to the comparator 0 between CINA and CINB */ + XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP1 = HRPWM0_CSGTRSG_SW1ST_Msk, /**< Request to switch the analog input connected to the comparator 1 between CINA and CINB */ + XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP2 = HRPWM0_CSGTRSG_SW2ST_Msk /**< Request to switch the analog input connected to the comparator 2 between CINA and CINB */ +} XMC_HRPWM_CSG_SWITCH_CMP_INPUT_t; + +/** + * CSG comparator input switch request + */ +typedef enum XMC_HRPWM_CSG_CMP_INVERTING_INPUT +{ + XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP0 = HRPWM0_CSGTRSG_D0STE_Msk, /**< Comparator 0 inverting input connection */ + XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP1 = HRPWM0_CSGTRSG_D1STE_Msk, /**< Comparator 1 inverting input connection */ + XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP2 = HRPWM0_CSGTRSG_D2STE_Msk /**< Comparator 2 inverting input connection */ +} XMC_HRPWM_CSG_CMP_INVERTING_INPUT_t; + +/** + * Input list to CSG + */ +typedef enum XMC_HRPWM_CSG_INPUT_SEL +{ + XMC_HRPWM_CSG_INPUT_SEL_IA = 0U, /**< Input selected for blanking or comparator switch: Input-A */ + XMC_HRPWM_CSG_INPUT_SEL_IB, /**< Input selected for blanking or comparator switch: Input-B */ + XMC_HRPWM_CSG_INPUT_SEL_IC, /**< Input selected for blanking or comparator switch: Input-C */ + XMC_HRPWM_CSG_INPUT_SEL_ID, /**< Input selected for blanking or comparator switch: Input-D */ + XMC_HRPWM_CSG_INPUT_SEL_IE, /**< Input selected for blanking or comparator switch: Input-E */ + XMC_HRPWM_CSG_INPUT_SEL_IF, /**< Input selected for blanking or comparator switch: Input-F */ + XMC_HRPWM_CSG_INPUT_SEL_IG, /**< Input selected for blanking or comparator switch: Input-G */ + XMC_HRPWM_CSG_INPUT_SEL_IH, /**< Input selected for blanking or comparator switch: Input-H */ + XMC_HRPWM_CSG_INPUT_SEL_II, /**< Input selected for blanking or comparator switch: Input-I */ + XMC_HRPWM_CSG_INPUT_SEL_IJ, /**< Input selected for blanking or comparator switch: Input-J */ + XMC_HRPWM_CSG_INPUT_SEL_IK, /**< Input selected for blanking or comparator switch: Input-K */ + XMC_HRPWM_CSG_INPUT_SEL_IL, /**< Input selected for blanking or comparator switch: Input-L */ + XMC_HRPWM_CSG_INPUT_SEL_IM, /**< Input selected for blanking or comparator switch: Input-M */ + XMC_HRPWM_CSG_INPUT_SEL_IN, /**< Input selected for blanking or comparator switch: Input-N */ + XMC_HRPWM_CSG_INPUT_SEL_IO, /**< Input selected for blanking or comparator switch: Input-O */ + XMC_HRPWM_CSG_INPUT_SEL_IP /**< Input selected for blanking or comparator switch: Input-P */ +} XMC_HRPWM_CSG_INPUT_SEL_t; + +/** + * HRPWM CSG - Selection of edge sensitivity + */ +typedef enum XMC_HRPWM_CSG_EDGE_SEL +{ + XMC_HRPWM_CSG_EDGE_SEL_DISABLED = 0U, /**< Trigger event not generated */ + XMC_HRPWM_CSG_EDGE_SEL_RISING_EDGE, /**< Trigger event not generated in rising edge */ + XMC_HRPWM_CSG_EDGE_SEL_FALLING_EDGE, /**< Trigger event not generated in falling edge */ + XMC_HRPWM_CSG_EDGE_SEL_BOTH_EDGE /**< Trigger event not generated in both edges */ +} XMC_HRPWM_CSG_EDGE_SEL_t; + +/** + * HRPWM CSG - Selection of level sensitivity + */ +typedef enum XMC_HRPWM_CSG_LVL_SEL +{ + XMC_HRPWM_CSG_LVL_SEL_DISABLED = 0U, /**< Level sensitivity is disabled */ + XMC_HRPWM_CSG_LVL_SEL_HIGH, /**< Level sensitivity is High */ + XMC_HRPWM_CSG_LVL_SEL_LOW /**< Level sensitivity is Low */ +} XMC_HRPWM_CSG_LVL_SEL_t; + +/** + * HRPWM CSG - Slope Generation clock selection + */ +typedef enum XMC_HRPWM_CSG_CLK_INPUT +{ + XMC_HRPWM_CSG_CLK_INPUT_MCLK = 0U, /**< Clock for CSG is module clock */ + XMC_HRPWM_CSG_CLK_INPUT_ECLKA, /**< Clock for CSG is external clock A */ + XMC_HRPWM_CSG_CLK_INPUT_ECLKB, /**< Clock for CSG is external clock B */ + XMC_HRPWM_CSG_CLK_INPUT_ECLKC /**< Clock for CSG is external clock C */ +} XMC_HRPWM_CSG_CLK_INPUT_t; + +/** + * HRPWM CSG - IRQ Event Id + * The enum is used to access the bitfields of registers CSGySRE, CSGySRS, CSGySWS, CSGySWC, CSGyISTAT + */ +typedef enum XMC_HRPWM_CSG_IRQ_ID +{ + XMC_HRPWM_CSG_IRQ_ID_VLS1 = 0x1U, /**< Interrupt on DAC value switch from CSGyDSV1 to CSGyDSV2 interrupt */ + XMC_HRPWM_CSG_IRQ_ID_VLS2 = 0x2U, /**< Interrupt on DAC value switch from CSGyDSV2 to CSGyDSV1 interrupt */ + XMC_HRPWM_CSG_IRQ_ID_TRGS = 0x4U, /**< Interrupt on DAC conversion trigger */ + XMC_HRPWM_CSG_IRQ_ID_STRS = 0x8U, /**< Interrupt on DAC start trigger */ + XMC_HRPWM_CSG_IRQ_ID_STPS = 0x10U, /**< Interrupt on DAC stop trigger */ + XMC_HRPWM_CSG_IRQ_ID_STD = 0x20U, /**< Interrupt on DAC shadow transfer */ + XMC_HRPWM_CSG_IRQ_ID_CRSE = 0x40U, /**< Interrupt on comparator output rise edge */ + XMC_HRPWM_CSG_IRQ_ID_CFSE = 0x80U, /**< Interrupt on comparator output fall edge */ + XMC_HRPWM_CSG_IRQ_ID_CSEE = 0x100U /**< Interrupt on comparator output clamped state */ +} XMC_HRPWM_CSG_IRQ_ID_t; + +/** + * HRPWM CSG - Initial DAC start mode + */ +typedef enum XMC_HRPWM_CSG_SWSM +{ + XMC_HRPWM_CSG_SWSM_DSV2_W_TRIGGER = 0U, /**< DSV2 is used as initial DAC value & conversion trigger is generated */ + XMC_HRPWM_CSG_SWSM_DSV1_W_TRIGGER, /**< DSV1 is used as initial DAC value & conversion trigger is generated */ + XMC_HRPWM_CSG_SWSM_DSV2_NO_TRIGGER, /**< DSV2 is used as initial DAC value & no conversion trigger generated */ + XMC_HRPWM_CSG_SWSM_DSV1_NO_TRIGGER /**< DSV1 is used as initial DAC value & no conversion trigger generated */ +} XMC_HRPWM_CSG_SWSM_t; + +/** + * HRPWM CSG - Configuration for Clock disable + */ +typedef enum XMC_HRPWM_CSG_CLK +{ + XMC_HRPWM_CSG_CLK_CSG0 = HRPWM0_CSGCFG_C0CD_Msk, /**< CSG0 clock mask */ + XMC_HRPWM_CSG_CLK_CSG1 = HRPWM0_CSGCFG_C1CD_Msk, /**< CSG1 clock mask */ + XMC_HRPWM_CSG_CLK_CSG2 = HRPWM0_CSGCFG_C2CD_Msk /**< CSG2 clock mask */ +} XMC_HRPWM_CSG_CLK_t; + +/** + * HRPWM CSG - DAC shadow transfer values + */ +typedef enum XMC_HRPWM_SHADOW_TX +{ + XMC_HRPWM_SHADOW_TX_DAC0 = HRPWM0_CSGTRC_D0SEC_Msk, /**< Shadow transfer mask for DAC0 - reference value 1 & Pulse swallow value */ + XMC_HRPWM_SHADOW_TX_DAC1 = HRPWM0_CSGTRC_D1SEC_Msk, /**< Shadow transfer mask for DAC1 - reference value 1 & Pulse swallow value */ + XMC_HRPWM_SHADOW_TX_DAC2 = HRPWM0_CSGTRC_D2SEC_Msk /**< Shadow transfer mask for DAC2 - reference value 1 & Pulse swallow value */ +} XMC_HRPWM_SHADOW_TX_DAC_t; + +/** + * HRPWM CSG - Service request line + */ +typedef enum XMC_HRPWM_CSG_IRQ_SR_LINE +{ + XMC_HRPWM_CSG_IRQ_SR_LINE_0 = 0U, /**< CSG - Service request SR-0 */ + XMC_HRPWM_CSG_IRQ_SR_LINE_1 = 1U, /**< CSG - Service request SR-1 */ + XMC_HRPWM_CSG_IRQ_SR_LINE_2 = 2U, /**< CSG - Service request SR-2 */ + XMC_HRPWM_CSG_IRQ_SR_LINE_3 = 3U /**< CSG - Service request SR-3 */ +} XMC_HRPWM_CSG_IRQ_SR_LINE_t; + +/** + * HRPWM CSG - Slope Generation control mode + */ +typedef enum XMC_HRPWM_CSG_SLOPE_CTRL_MODE +{ + XMC_HRPWM_CSG_SLOPE_CTRL_MODE_STATIC = 0U, /**< Slope generation mode - Static mode */ + XMC_HRPWM_CSG_SLOPE_CTRL_MODE_DEC_GEN, /**< Slope generation mode - Decrementing slope generation */ + XMC_HRPWM_CSG_SLOPE_CTRL_MODE_INC_GEN, /**< Slope generation mode - Incrementing slope generation */ + XMC_HRPWM_CSG_SLOPE_CTRL_MODE_TRIANGULAR /**< Slope generation mode - Triangular slope generation */ +} XMC_HRPWM_CSG_SLOPE_CTRL_MODE_t; + +/** + * HRPWM CSG - Prescaler external start configuration + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_EXT_START +{ + XMC_HRPWM_CSG_PRESCALER_EXT_START_IGNORE = 0U, /**< Prescaler operation on external start trigger is: Ignore */ + XMC_HRPWM_CSG_PRESCALER_EXT_START_STRT, /**< Prescaler operation on external start trigger is: Start prescaler */ + XMC_HRPWM_CSG_PRESCALER_EXT_START_CLR, /**< Prescaler operation on external start trigger is: Clear prescaler */ + XMC_HRPWM_CSG_PRESCALER_EXT_START_CLR_N_STRT /**< Prescaler operation on external start trigger is: Clear & Start prescaler */ +} XMC_HRPWM_CSG_PRESCALER_EXT_START_t; + +/** + * HRPWM CSG - Prescaler external stop configuration + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_EXT_STOP +{ + XMC_HRPWM_CSG_PRESCALER_EXT_STOP_IGNORE = 0U, /**< Prescaler operation on external stop trigger is: Ignore */ + XMC_HRPWM_CSG_PRESCALER_EXT_STOP_STP, /**< Prescaler operation on external stop trigger is: Stop prescaler */ + XMC_HRPWM_CSG_PRESCALER_EXT_STOP_CLR, /**< Prescaler operation on external stop trigger is: Clear prescaler */ + XMC_HRPWM_CSG_PRESCALER_EXT_STOP_CLR_N_STOP /**< Prescaler operation on external stop trigger is: Clear & Stop prescaler */ +} XMC_HRPWM_CSG_PRESCALER_EXT_STOP_t; + +/** + * HRPWM CSG - Slope Generation external start configuration + */ +typedef enum XMC_HRPWM_CSG_SLOPE_EXT_START +{ + XMC_HRPWM_CSG_SLOPE_EXT_START_IGNORE = 0U, /**< Slope generation on external start trigger is: Ignore */ + XMC_HRPWM_CSG_SLOPE_EXT_START_STRT, /**< Slope generation on external start trigger is: Start/restart slope generation */ + XMC_HRPWM_CSG_SLOPE_EXT_START_RESUME, /**< Slope generation on external start trigger is: Resumes slope generation */ +} XMC_HRPWM_CSG_SLOPE_EXT_START_t; + +/** + * HRPWM CGS - Slope Generation external stop configuration + */ +typedef enum XMC_HRPWM_CSG_SLOPE_EXT_STOP +{ + XMC_HRPWM_CSG_SLOPE_EXT_STOP_IGNORE = 0U, /**< Slope generation on external stop trigger is: Ignore */ + XMC_HRPWM_CSG_SLOPE_EXT_STOP_STP, /**< Slope generation on external stop trigger is: Stops/Halts the slope generation */ + XMC_HRPWM_CSG_SLOPE_EXT_STOP_FREEZE, /**< Slope generation on external stop trigger is: Freezes slope generation & feeds constantly + the value programmed in CSGyDSV2 to the DAC */ +} XMC_HRPWM_CSG_SLOPE_EXT_STOP_t; + +/** + * HRPWM CSG - Slice numbers + */ +typedef enum XMC_HRPWM_CSG_SLICE +{ + XMC_HRPWM_CSG_SLICE_0 = 0U, /**< CSG slice number is 0 */ + XMC_HRPWM_CSG_SLICE_1, /**< CSG slice number is 1 */ + XMC_HRPWM_CSG_SLICE_2 /**< CSG slice number is 2 */ +} XMC_HRPWM_CSG_SLICE_t; + +/** + * HRPWM CSG - Comparator output filter window + */ +typedef enum XMC_HRPWM_CSG_CMP_FILTER_WINDOW +{ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_2_CLK_CYCLES = 0U , /**< Needs to be stable for 2 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_3_CLK_CYCLES, /**< Needs to be stable for 3 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_4_CLK_CYCLES, /**< Needs to be stable for 4 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_5_CLK_CYCLES, /**< Needs to be stable for 5 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_6_CLK_CYCLES, /**< Needs to be stable for 6 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_7_CLK_CYCLES, /**< Needs to be stable for 7 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_8_CLK_CYCLES, /**< Needs to be stable for 8 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_9_CLK_CYCLES, /**< Needs to be stable for 9 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_10_CLK_CYCLES, /**< Needs to be stable for 10 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_11_CLK_CYCLES, /**< Needs to be stable for 11 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_12_CLK_CYCLES, /**< Needs to be stable for 12 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_13_CLK_CYCLES, /**< Needs to be stable for 13 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_14_CLK_CYCLES, /**< Needs to be stable for 14 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_15_CLK_CYCLES, /**< Needs to be stable for 15 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_16_CLK_CYCLES, /**< Needs to be stable for 16 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_32_CLK_CYCLES /**< Needs to be stable for 32 clk cycles */ +} XMC_HRPWM_CSG_CMP_FILTER_WINDOW_t; + +/** + * HRPWM CSG - Slope step gain + */ +typedef enum XMC_HRPWM_CSG_SLOPE_STEP_GAIN +{ + XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_1 = 0U, /**< slope step has an increment/decrement of 1 */ + XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_2, /**< slope step has an increment/decrement of 2 */ + XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_4, /**< slope step has an increment/decrement of 4 */ + XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_8 /**< slope step has an increment/decrement of 8 */ +} XMC_HRPWM_CSG_SLOPE_STEP_GAIN_t; + +/** + * HRPWM CSG - Slope step gain + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_DIVISION +{ + XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_1 = 0U, /**< Division by 1 */ + XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_2, /**< Division by 2 */ + XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_4, /**< Division by 4 */ + XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_8 /**< Division by 8 */ +} XMC_HRPWM_CSG_PRESCALER_DIVISION_t; + +/********************************************************************************************************************* + * DATA STRUCTURES - HRPWM + ********************************************************************************************************************/ +/** + * Typedef for HRPWM Global registers data structure + */ +typedef HRPWM0_Type XMC_HRPWM_t; + +/** + * Typedef for HRPWM high resolution channel registers data structure + */ +typedef HRPWM0_HRC_Type XMC_HRPWM_HRC_t; + +/** + * Typedef for CSG unit registers data structure + */ +typedef HRPWM0_CSG_Type XMC_HRPWM_CSG_t; + +/** + * HRPWM HRC source path configuration + */ +typedef struct XMC_HRPWM_HRC_SRC_CONFIG +{ + XMC_HRPWM_HRC_HR_EDGE_t high_res_mode; /**< high resolution mode configuration */ + XMC_HRPWM_HRC_SRC_INPUT_t set_config; /**< Selection of input for set configuration */ + XMC_HRPWM_HRC_SRC_INPUT_t clear_config; /**< Selection of input clear configuration */ + XMC_HRPWM_HRC_CMP_SEL_t cmp_set; /**< Selection of comparator for set configuration */ + XMC_HRPWM_HRC_CMP_SEL_t cmp_clear; /**< Selection of comparator for clear configuration */ + XMC_HRPWM_HRC_TIMER_SEL_t timer_sel; /**< Selection of timer */ + XMC_HRPWM_HRC_SRC_EDGE_SEL_t set_edge_config; /**< Selection of edge for generating set signal */ + XMC_HRPWM_HRC_SRC_EDGE_SEL_t clear_edge_config; /**< Selection of edge for generating clear signal */ + XMC_HRPWM_FUNC_STATUS_t src_trap_enable; /**< Selection of source for trap signal generation */ +} XMC_HRPWM_HRC_SRC_CONFIG_t; + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * HRPWM HRC configuration + */ +typedef struct XMC_HRPWM_HRC_CONFIG +{ + union + { + struct + { + uint32_t : 2; + uint32_t : 2; + uint32_t : 4; + uint32_t dt_enable: 1; /**< Enables dead time. Accepts enum @ref XMC_HRPWM_FUNC_STATUS_t */ + uint32_t hr_out0_trap_enable: 1; /**< Enables trap for HROUT0. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t hr_out1_trap_enable: 1; /**< Enables trap for HROUT1. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t hrc_shadow_xfer_linktoCCU8: 1; /**< Shadow transfer for CR1 and CR2 linked to shadow transfer trigger of CCU8 slice. + Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t dt_shadow_xfer_linktoCCU8: 1; /**< Shadow transfer for DCR and DCF linked to shadow transfer trigger of CCU8 slice. + Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t hr_out0_inv_enable: 1; /**< Enables inversion of HROUT0 output pin. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t hr_out1_inv_enable: 1; /**< Enables inversion of HROUT1 output pin. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t : 1; + uint32_t dt_trigger_sel: 1; /**< Selection of trigger for dead time shadow transfer. Accepts enum XMC_HRPWM_HRC_DT_TR_SEL_t */ + uint32_t : 15; + }; + uint32_t gc; /**< General high resolution channel configuration */ + }; + + union + { + struct + { + uint32_t hr_out0_passive_level_out: 1; /**< Selection of HROUT0 passive level. Accepts enum XMC_HRPWM_HRC_OUT_PASSIVE_LVL_t */ + uint32_t hr_out1_passive_level_out: 1; /**< Selection of HROUT0 passive level. Accepts enum XMC_HRPWM_HRC_OUT_PASSIVE_LVL_t */ + uint32_t : 30; + }; + uint32_t psl; /**< Output passive level configuration */ + }; +} XMC_HRPWM_HRC_CONFIG_t; + +/*********************************************************************************************************************** + * DATA STRUCTURES - CSG + **********************************************************************************************************************/ +/** + * Configuration data structure of a CSG input selection + */ +typedef struct XMC_HRPWM_CSG_INPUT_CONFIG +{ + XMC_HRPWM_CSG_INPUT_SEL_t mapped_input; /**< CSG input selection */ + XMC_HRPWM_CSG_EDGE_SEL_t edge; /**< Active edge of mapped_input */ + XMC_HRPWM_CSG_LVL_SEL_t level; /**< Active level of mapped_input */ +} XMC_HRPWM_CSG_INPUT_CONFIG_t; + +/** + *CSG Unit - Comparator configuration + */ +typedef struct XMC_HRPWM_CSG_CMP +{ + union + { + struct + { + uint32_t : 4; + uint32_t : 4; + uint32_t cmp_input_sel: 1; /**< Comparator input pin selection. Accepts enum XMC_HRPWM_CSG_CMP_INPUT_t */ + uint32_t cmp_input_sw: 2; /**< Comparator input switching configuration. Accepts enum XMC_HRPWM_CSG_LVL_SEL_t */ + uint32_t cmp_ext_sw_enable: 1; /**< Enable switching of input between CINA and CINB via external trigger. + Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t cmp_out_inv: 1; /**< Invert comparator output. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t : 1; /*Enable Comparator output synchronization */ + uint32_t blanking_mode: 2; /**< Select the edge for blanking. Accepts enum XMC_HRPWM_CSG_EDGE_SEL_t */ + uint32_t blank_ext_enable: 1; /**< Enable blanking via external trigger. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t filter_enable: 1; /**< Enable comparator output filter. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t filter_window: 4; /**< Select the comparator output filter window */ + uint32_t : 2; + uint32_t filter_control: 2; /**< Select the filter application condition + 00B Filtering is always done if enabled + 01B Filtering is only done when CSGyDSV1 value is currently fed to the DAC + 10B Filtering is only done when the CSGyDSV2 value is currently fed to the DAC */ + uint32_t : 6; + }; + uint32_t cc; /**< Comparator general configuration */ + }; + + uint32_t blanking_val; /**< blanking value, blanking time = blanking_val * module clk freq */ + + union + { + struct + { + uint32_t : 4; + uint32_t : 4; + uint32_t clamp_ctrl_lvl: 2; /**< Select the trigger signal level for clamping the comparator output. + Accepts enum XMC_HRPWM_CSG_LVL_SEL_t */ + uint32_t clamp_level: 1; /**< Select the comparator output passive level value. */ + uint32_t clamp_exit_sw_config: 1; /**< Clamped state exit software configuration */ + uint32_t clamp_enter_config: 2; /**< Clamping level enter configuration */ + uint32_t clamp_exit_config: 2; /**< Clamping level exit configuration */ + uint32_t : 16; + }; + uint32_t plc; /**< Comparator passive level configuration */ + }; +} XMC_HRPWM_CSG_CMP_t; + +/** + * CSG Unit - DAC configuration + */ +typedef struct XMC_HRPWM_CSG_DAC +{ + XMC_HRPWM_CSG_SWSM_t start_mode; /**< Initial DAC start mode */ + uint32_t dac_dsv1; /**< DAC reference value 1 */ + uint32_t dac_dsv2; /**< DAC reference value 2 */ +} XMC_HRPWM_CSG_DAC_t; + +/** + * CSG Unit - Slope Generation configuration + */ +typedef struct XMC_HRPWM_CSG_SGEN +{ + union + { + struct + { + uint32_t prescaler_ext_start_mode: 2; /**< Pre-scaler external start mode. Accepts enum XMC_HRPWM_CSG_PRESCALER_EXT_START_t */ + uint32_t prescaler_ext_stop_mode: 2; /**< Pre-scaler external stop mode. Accepts enum XMC_HRPWM_CSG_PRESCALER_EXT_STOP_t */ + uint32_t fixed_prescaler_enable: 1; /**< Fixed pre-scaler, 0:enabled, 1:disabled */ + uint32_t prescaler: 2; /**< Pre-scaler division factor */ + uint32_t : 1; + uint32_t ctrl_mode: 2; /**< Slope control mode. Accepts enum XMC_HRPWM_CSG_SLOPE_CTRL_MODE_t */ + uint32_t ext_start_mode: 2; /**< Slope external start mode. Accepts enum XMC_HRPWM_CSG_SLOPE_EXT_START_t */ + uint32_t ext_stop_mode: 2; /**< Slope external stop mode. Accepts enum XMC_HRPWM_CSG_SLOPE_EXT_STOP_t */ + uint32_t slope_ref_val_mode: 2; /**< Slope reference value mode */ + uint32_t : 2; /* start_mode */ + uint32_t step_gain: 2; /**< Slope step gain configuration */ + uint32_t static_mode_ist_enable: 1; /**< Immediate shadow transfer in static mode enabled. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t pulse_swallow_enable: 1; /**< Pulse swallow enable / disable. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t : 2; + uint32_t pulse_swallow_win_mode: 2; /**< Pulse swallow window mode */ + uint32_t : 6; + }; + uint32_t sc; /**< Slope Generation Configuration */ + }; + uint32_t pulse_swallow_val; /**< Pulse swallow value */ +} XMC_HRPWM_CSG_SGEN_t; + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +/** + * HRPWM CSG configuration + */ +typedef struct XMC_HRPWM_CSG_CONFIG +{ + XMC_HRPWM_CSG_CMP_t cmp_config; /**< Comparator set up */ + XMC_HRPWM_CSG_DAC_t dac_config; /**< DAC configuration of CSG */ + XMC_HRPWM_CSG_SGEN_t sgen_config; /**< Slope generation related configurations */ +} XMC_HRPWM_CSG_CONFIG_t; + +/*********************************************************************************************************************** + * API PROTOTYPES + **********************************************************************************************************************/ +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return XMC_HRPWM_STATUS_t + * + * \parDescription + *
HRPWM Init
\n + * + * This function initializes the HRPWM global registers. It configures the CSG trimming data. + * This is the first function that needs to be called in initializing HRC or CSG modules. + * + * \parRelated APIs:
+ * XMC_SDMMC_TriggerEvent()\n\n\n + + */ +XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm); + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Enable global high resolution generation
\n + * + * Enables global high resolution generation by setting GLBANA.GHREN bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_DisableGlobalHR()
+ */ +void XMC_HRPWM_EnableGlobalHR(XMC_HRPWM_t *const hrpwm); + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Disable global high resolution generation
\n + * + * Disables global high resolution generation by clearing GLBANA.GHREN bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableGlobalHR()
+ */ + +void XMC_HRPWM_DisableGlobalHR(XMC_HRPWM_t *const hrpwm); + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Enables the bias generation
\n + * + * Enables the bias generation of high resolution generation by setting HRBSC.HRBE bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_DisableBias()
+ */ + +__STATIC_INLINE void XMC_HRPWM_EnableBias(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_EnableBias:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRBSC |= HRPWM0_HRBSC_HRBE_Msk; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Disables the bias generation
\n + * + * Disables the bias generation of high resolution generation by clearing HRBSC.HRBE bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableBias()
+ */ +__STATIC_INLINE void XMC_HRPWM_DisableBias(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_DisableBias:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRBSC &= ~(HRPWM0_HRBSC_HRBE_Msk); +} + +/*********************************************************************************************************************** + * API PROTOTYPES - HRPWM HRC GLOBAL + **********************************************************************************************************************/ +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return XMC_HRPWM_HR_LOGIC_t + * + * \parDescription + *
Returns the status of the high resolution logic.
\n + * + * Returns status of the high resolution logic by checking HRGHRS.HRGR bit. + * The return value should be @ref XMC_HRPWM_HR_LOGIC_WORKING for proper generation of high resolution signal positioning. + */ + +XMC_HRPWM_HR_LOGIC_t XMC_HRPWM_GetHRGenReadyStatus(XMC_HRPWM_t *const hrpwm); + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HR_PATH_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the high resolution path.
\n + * + * Enables the high resolution path determined by passed mask value, by setting HRCCFG.HRC0E bit. + * By default signals from source selector 0 are linked to HR path and signals from source selector 1 are linked to LR path. + * This connections can be reversed at runtime, if bit HRCySC.ST is set to 1. + * + * \parRelated APIs:
+ * XMC_HRPWM_HRC_Set_HR_Source()
+ * XMC_HRPWM_DisableHighResolutionPath()
+ * XMC_HRPWM_EnableLowResolutionPath()
+ * XMC_HRPWM_DisableLowResolutionPath()
+ * XMC_HRPWM_EnableHRPowerMode()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_EnableHighResolutionPath(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_EnableHighResolutionPath:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCFG |= mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HR_PATH_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the high resolution path
\n + * + * Disables the high resolution path determined by passed mask value, by clearing HRCCFG.HRC0E bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionPath()
+ * XMC_HRPWM_EnableLowResolutionPath()
+ * XMC_HRPWM_DisableLowResolutionPath()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_DisableHighResolutionPath(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_DisableHighResolutionPath:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCFG &= ~mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_LR_PATH_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the low resolution path
\n + * + * Enables the low resolution path determined by passed mask value, by setting HRCCFG.LRC0E bit. + * By default signals from source selector 0 are linked to HR path and signals from source selector 1 are linked to LR path. + * This connections can be reversed at runtime, if bit HRCySC.ST is set to 1. + * + * \parRelated APIs:
+ * XMC_HRPWM_HRC_Set_HR_Source()
+ * XMC_HRPWM_EnableHighResolutionPath()
+ * XMC_HRPWM_DisableHighResolutionPath()
+ * XMC_HRPWM_DisableLowResolutionPath()
+ * XMC_HRPWM_EnableHRPowerMode()
+ */ + +__STATIC_INLINE void XMC_HRPWM_EnableLowResolutionPath(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_EnableLowResolutionPath:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCFG |= mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_LR_PATH_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the low resolution path
\n + * + * Disables the low resolution path determined by passed mask value, by clearing HRCCFG.LRC0E bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionPath()
+ * XMC_HRPWM_DisableHighResolutionPath()
+ * XMC_HRPWM_EnableLowResolutionPath()
+ * + */ + __STATIC_INLINE void XMC_HRPWM_DisableLowResolutionPath(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_DisableLowResolutionPath:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCFG &= ~mask; +} + + /** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HRC_SHADOW_TX_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the high resolution shadow transfer
\n + * + * Enables the high resolution shadow transfer determined by passed mask value, by setting HRCSTRG.H0ES, HRCSTRG.H0DES bits. + * The input for trigger for shadow transfer needs to be configured correctly. + * + * \parRelated APIs:
+ * XMC_HRPWM_DisableHighResolutionShadowTransfer()
+ * XMC_HRPWM_GetHighResolutionShadowTransferStatus()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_EnableHighResolutionShadowTransfer(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_EnableHighResolutionShadowTransfer:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCSTRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HRC_SHADOW_TX_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the high resolution shadow transfer
\n + * + * Disables the high resolution shadow transfer determined by passed mask value, by setting HRCCTRG.H0EC, HRCCTRG.H0DEC bits. + * It cancels shadow transfer request by @ref XMC_HRPWM_EnableHighResolutionShadowTransfer(), provided the shadow transfer has not occurred. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_DisableHighResolutionShadowTransfer(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_DisableHighResolutionShadowTransfer:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCTRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HRC_SHADOW_TX_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Returns the shadow transfer request status
\n + * + * Returns the shadow transfer request status, by checking HRCSTSG.H0STE, HRCSTSG.H0DSTE bits. + * Returns a non zero value if corresponding shadow transfer request has been performed. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * + */ +__STATIC_INLINE uint32_t XMC_HRPWM_GetHighResolutionShadowTransferStatus(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_GetHighResolutionShadowTransferStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return (hrpwm->HRCSTSG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Turns ON the power to all HR and LR path
\n + * + * Turns ON the power to all HR and LR path by setting HRCCFG.HRCPM bit. Enable the HR and LR paths as per requirement by + * calling following API @ref XMC_HRPWM_EnableHighResolutionPath() and @ref XMC_HRPWM_EnableLowResolutionPath(). + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionPath()
+ * XMC_HRPWM_EnableLowResolutionPath()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_EnableHRPowerMode(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_EnableHRPowerMode:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCFG |= HRPWM0_HRCCFG_HRCPM_Msk; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Turns OFF the power to all HR and LR path
\n + * + * Turns OFF the power to all HR and LR path by clearing HRCCFG.HRCPM bit. + * This disables all HR and LR paths. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHRPowerMode()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_DisableHRPowerMode(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_DisableHRPowerMode:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + /* Turn off high resolution generation logic */ + hrpwm->HRCCFG &= ~(HRPWM0_HRCCFG_HRCPM_Msk); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param clk_freq The operating clock frequency of HRPWM module. Use the enum type @ref XMC_HRPWM_CLK_FREQ_t to generate the mask. + * @return None + * + * \parDescription + *
Configures the clock frequency of operation of HRPWM module
\n + * + * Configures the clock frequency of operation of HRPWM module by configuring HRCCFG.CLKC bits. + * The clock is generally selected based on the device type selected. + * + */ + +__STATIC_INLINE void XMC_HRPWM_ModuleClkFreq(XMC_HRPWM_t *const hrpwm, const XMC_HRPWM_CLK_FREQ_t clk_freq) +{ + XMC_ASSERT("XMC_HRPWM_ModuleClkFreq:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + hrpwm->HRCCFG &= ~(HRPWM0_HRCCFG_CLKC_Msk); + hrpwm->HRCCFG |= (clk_freq << HRPWM0_HRCCFG_CLKC_Pos); +} + +/*********************************************************************************************************************** + * API PROTOTYPES - HRPWM CSG GLOBAL + **********************************************************************************************************************/ +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the operation of comparator
\n + * + * Enables the operation of comparator by setting CSGSETG.SC0R bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_StopComparator()
+ * XMC_HRPWM_IsComparatorRunning()
+ */ + +__STATIC_INLINE void XMC_HRPWM_StartComparator(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StartComparator:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGSETG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the operation of comparator
\n + * + * Disables the operation of comparator by setting CSGCLRG.CC0R bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_StartComparator()
+ * XMC_HRPWM_IsComparatorRunning()
+ */ +__STATIC_INLINE void XMC_HRPWM_StopComparator(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StopComparator:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGCLRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return bool + * + * \parDescription + *
Checks if comparator is enabled
\n + * + * Checks if comparator is enabled by checking CSGSTATG.C0RB bit. + * Returns true if comparator run bit is set, else returns false. + * + * \parRelated APIs:
+ * XMC_HRPWM_StartComparator()
+ * XMC_HRPWM_StopComparator()
+ */ +__STATIC_INLINE bool XMC_HRPWM_IsComparatorRunning(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + bool status; + + XMC_ASSERT("XMC_HRPWM_IsComparatorRunning:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + if(hrpwm->CSGSTATG & mask) + { + status = true; + } + else + { + status = false; + } + + return (status); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the operation of CSG DAC
\n + * + * Enables the operation of CSG DAC by setting CSGSETG.SD0R bit. + * The DAC operation is enabled. Either the value in DSV1 or DSV2 is sent to DAC, based on configuration. + * + * \parRelated APIs:
+ * XMC_HRPWM_StopDac()
+ * XMC_HRPWM_IsDacRunning()
+ */ + +__STATIC_INLINE void XMC_HRPWM_StartDac(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StartDac:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGSETG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the operation of CSG DAC
\n + * + * Disables the operation of CSG DAC by setting CSGCLRG.CD0R bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_StartDac()
+ * XMC_HRPWM_IsDacRunning()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_StopDac(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StopDac:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGCLRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Checks if CSG DAC is operational
\n + * + * Checks if CSG DAC is operational by checking CSGSTATG.D0RB bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_StartDac()
+ * XMC_HRPWM_StopDac()
+ */ +__STATIC_INLINE uint32_t XMC_HRPWM_IsDacRunning(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_IsDacRunning:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return (hrpwm->CSGSTATG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Set the comparator output to clamp state
\n + * + * Sets the comparator to clamped state via software by setting CSGSETG.SC0P bit. The output of comparator is now not dependent on its inputs pins. + * The clamped state is defined by comparator output passive level value. Output passive level can be set to high or low. + * + * \parRelated APIs:
+ * XMC_HRPWM_UnClampComparatorOutput()
+ * XMC_HRPWM_IsComparatorClamped()
+ */ + +__STATIC_INLINE void XMC_HRPWM_ClampComparatorOutput(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_ClampComparatorOutput:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + hrpwm->CSGSETG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Clear the comparator output from clamp state
\n + * + * Un-clamps the output of comparator from clamped state set via software by setting CSGCLRG.CC0P bit. The output of + * comparator is now dependent on the inputs of comparator. + * + * \parRelated APIs:
+ * XMC_HRPWM_ClampComparatorOutput()
+ * XMC_HRPWM_IsComparatorClamped()
+ */ +__STATIC_INLINE void XMC_HRPWM_UnClampComparatorOutput(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_UnClampComparatorOutput:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + hrpwm->CSGCLRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Checks if comparator is in clamped state
\n + * + * Checks if comparator is in clamped state by checking CSGSTATG.PSLS0 bit. + * Returns bit encoded status if comparator is set to clamped state via software. + * + * \parRelated APIs:
+ * XMC_HRPWM_ClampComparatorOutput()
+ * XMC_HRPWM_UnClampComparatorOutput()
+ */ + +__STATIC_INLINE uint32_t XMC_HRPWM_IsComparatorClamped(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_IsComparatorClamped:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + return (hrpwm->CSGSTATG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Returns bit encoded status of multiple DACs and Comparators, defined by the mask.
\n + * + * Returns bit encoded status of multiple DACs and Comparators from register CSGSTATG, defined by the mask. + * The mask is generated by bitwise ORing multiple Enums.
+ * mask = (uint32_t) (XMC_HRPWM_CSG_RUN_BIT_CMP0 | XMC_HRPWM_CSG_RUN_BIT_DAC0 | XMC_HRPWM_CSG_RUN_BIT_CMP0_PSL); + * + * \parRelated APIs:
+ * XMC_HRPWM_IsDacRunning()
+ * XMC_HRPWM_IsComparatorClamped()
+ */ + +__STATIC_INLINE uint32_t XMC_HRPWM_GetRunBitStatus(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_GetRunBitStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return (hrpwm->CSGSTATG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Start the prescaler & slope generation of DAC
\n + * + * Start the prescaler & slope generation of DAC by setting CSGFCG.S0STR and CSGFCG.PS0STR bits. + * The mask is generated by bitwise ORing multiple Enums.
+ * mask = (uint32_t) (XMC_HRPWM_CSG_SLOPE_START_DAC0 | XMC_HRPWM_CSG_PRESCALER_START_CSG0); + * + * \parRelated APIs:
+ * XMC_HRPWM_StopSlopeGeneration()
+ * XMC_HRPWM_IsSlopeGenerationRunning()
+ */ + +__STATIC_INLINE void XMC_HRPWM_StartSlopeGeneration(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StartSlopeGeneration:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGFCG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Stops the prescaler & slope generation of DAC
\n + * + * Stops the prescaler & slope generation of DAC by setting CSGFCG.S0STP and CSGFCG.PS0STP bits. + * The mask is generated by bitwise ORing multiple Enums.
+ * mask = (uint32_t) (XMC_HRPWM_CSG_SLOPE_START_DAC0 | XMC_HRPWM_CSG_PRESCALER_START_CSG0); + * + * \parRelated APIs:
+ * XMC_HRPWM_StartSlopeGeneration()
+ * XMC_HRPWM_IsSlopeGenerationRunning()
+ */ +__STATIC_INLINE void XMC_HRPWM_StopSlopeGeneration(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StopSlopeGeneration:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGFCG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return bool + * + * \parDescription + *
Checks if Prescaler & slope generation is running
\n + * + * Checks if Prescaler & slope generation is running by checking CSGFSG.S0RB CSGFSG.P0RB bits. + * The mask is generated by bitwise ORing multiple Enums.
+ * mask = (uint32_t) (XMC_HRPWM_CSG_SLOPE_START_DAC0 | XMC_HRPWM_CSG_PRESCALER_START_CSG0); + * + * \parRelated APIs:
+ * XMC_HRPWM_StartSlopeGeneration()
+ * XMC_HRPWM_StopSlopeGeneration()
+ */ +__STATIC_INLINE bool XMC_HRPWM_IsSlopeGenerationRunning(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + bool status; + + XMC_ASSERT("XMC_HRPWM_IsSlopeGenerationRunning:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + if (hrpwm->CSGFSG & mask) + { + status = true; + } + else + { + status = false; + } + + return (status); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_SHADOW_TX_DAC_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the shadow transfer of DSV1 and pulse swallow registers of DACs selected by mask
\n + * + * Enables the shadow transfer of DSV1 and pulse swallow registers of DACs selected by mask by setting CSGTRG.D0SES bit. + * The transfer is done at the next shadow transfer trigger. + * + * \parRelated APIs:
+ * XMC_HRPWM_DisableComparatorShadowTransfer()
+ * XMC_HRPWM_GetComparatorShadowTransferStatus()
+ */ +__STATIC_INLINE void XMC_HRPWM_EnableComparatorShadowTransfer(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_EnableComparatorShadowTransfer:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGTRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_SHADOW_TX_DAC_t to generate the mask. + * @return None + * + * \parDescription + *
Cancels the shadow transfer of DSV1 and pulse swallow registers
\n + * + * Cancels the shadow transfer of DSV1 and pulse swallow registers by setting CSGTRC.D0SEC bit. + * The transfer request is canceled. Needs to be called before the next shadow transfer trigger. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableComparatorShadowTransfer()
+ * XMC_HRPWM_GetComparatorShadowTransferStatus()
+ */ + +__STATIC_INLINE void XMC_HRPWM_DisableComparatorShadowTransfer(XMC_HRPWM_t *const hrpwm, uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_DisableComparatorShadowTransfer:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGTRC = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return uint32_t + * + * \parDescription + *
Gets the shadow transfer status of DSV1 and pulse swallow registers of all the DACs
\n + * + * Gets the shadow transfer status of DSV1 and pulse swallow registers of all the DACs by checking the register CSGTRSG + * The return value is not zero if shadow transfer has been requested, but is still pending completion. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableComparatorShadowTransfer()
+ * XMC_HRPWM_DisableComparatorShadowTransfer()
+ */ +__STATIC_INLINE uint32_t XMC_HRPWM_GetComparatorShadowTransferStatus(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_GetComparatorShadowTransferStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return(hrpwm->CSGTRSG & XMC_HRPWM_COMPARATOR_STATUS); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_PRESCALER_STATUS_t to generate the mask. + * @return None + * + * \parDescription + *
Clears the prescaler registers of DACs selected by mask
\n + * + * Clears the prescaler registers of DACs selected by mask, by setting CSGFCG.PS0CLR bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_IsPrescalerRunning()
+ */ +__STATIC_INLINE void XMC_HRPWM_ClearPreScaler(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_ClearPreScaler:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGFCG |= mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_PRESCALER_STATUS_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Checks the prescaler status of DACs selected by mask
\n + * + * Checks the prescaler status of DACs selected by mask, by checking CSGFCG.P0RB bit. + * Returns the bit encoded status information of prescaler. + * + * \parRelated APIs:
+ * XMC_HRPWM_ClearPreScaler()
+ * XMC_HRPWM_StartSlopeGeneration()
+ */ +__STATIC_INLINE uint32_t XMC_HRPWM_IsPrescalerRunning(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_IsPrescalerRunning:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return (hrpwm->CSGFSG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_SWITCH_CMP_INPUT_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Returns the bit encoded status of HW pin connected to comparator inverting pin
\n + * + * Returns the bit encoded status of HW pin connected to comparator inverting pin by checking CSGTRSG.SW0ST bit. + * The bit position is set to 1 if CINB is connected, else its CINA. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_SetCMPInput()
+ */ + +__STATIC_INLINE uint32_t XMC_HRPWM_GetCMPInput(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_GetCMPInput:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return (hrpwm->CSGTRSG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param slice Slice NO. + * @param power_mode The mode to be put in. + * @return None + * + * \parDescription + *
Sets the DAC in OFF, Low speed or High speed mode
\n + * + * Sets the DAC in OFF, Low speed or High speed mode, by setting CSGCFG.C0PM bits. + * + * \parRelated APIs:
+ * + */ +__STATIC_INLINE void XMC_HRPWM_SetCsgPowerMode(XMC_HRPWM_t *const hrpwm, + const XMC_HRPWM_CSG_SLICE_t slice, + const XMC_HRPWM_CSG_POWER_MODE_t power_mode) +{ + XMC_ASSERT("XMC_HRPWM_SetCsgPowerMode:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + hrpwm->CSGCFG &= ~(3U << (slice * 2U)); + hrpwm->CSGCFG |= power_mode << (slice * 2U); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_CLK_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the clock of selected CSG subunits
\n + * + * Disables the clock of selected CSG subunits by setting the CSGCFG.C0CD bit. + * + * \parRelated APIs:
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_DisableCsgClock(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_DisableCsgClock:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGCFG |= mask; +} + +/*********************************************************************************************************************** + * API PROTOTYPES - HRPWM HRC CHANNEL + **********************************************************************************************************************/ +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Initializes the HRC channel.
\n + * + * Initializes the HRC channel functionality.
+ * These include:
+ * 1) Dead time configuration.
+ * 3) Trap Configuration.
+ * 4) Shadow transfer configuration.
+ * 5) Output inversion configuration.
+ * 6) Passive levels of HRC outputs.
+ */ + +void XMC_HRPWM_HRC_Init(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_CONFIG_t *const config); + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Initializes the source 0 of HRC channel.
\n + * + * Initialize the source 0 functionality of HRC channel.
+ * This include:
+ * 1) general configuration for source 0 HRC channel.
+ * 2) Configuration of which inputs are being used to generate the set and clear for the latch and therefore controlling + * the generation of the output PWM signal.
+ * 3) Configuration for which timer from the Capture/Compare Unit is used for the Source Selector 0 and Source Selector 1.
+ * + * \parRelated APIs:
+ * XMC_HRPWM_HRC_ConfigSourceSelect1()
+ */ + + +void XMC_HRPWM_HRC_ConfigSourceSelect0(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config); + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Initializes the source 1 of HRC channel.
\n + * + * Initialize the source 1 functionality of HRC channel.
\n + * This include:
+ * 1) general configuration for source 1 HRC channel.
+ * 2) Configuration of which inputs are being used to generate the set and clear for the latch and therefore controlling + * the generation of the output PWM signal.
+ * 3) Configuration for which timer from the Capture/Compare Unit is used for the Source Selector 0 and Source Selector 1.
+ * + * \parRelated APIs:
+ * XMC_HRPWM_HRC_ConfigSourceSelect0()
+ */ + +void XMC_HRPWM_HRC_ConfigSourceSelect1(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config); + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param cr1_value high resolution positioning value. + * @return None + * + * \parDescription + *
Sets the shadow transfer register of high resolution positioning for rising edge
\n + * + * Call the shadow transfer update API for transfer to CR1 register. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * XMC_HRPWM_HRC_SetCompare2()
+ */ +__STATIC_INLINE void XMC_HRPWM_HRC_SetCompare1(XMC_HRPWM_HRC_t *const hrc, const uint8_t cr1_value) +{ + XMC_ASSERT("XMC_HRPWM_HRC_SetCompare1:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + hrc->SCR1 = (uint32_t) cr1_value; +} + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param cr2_value high resolution positioning value. + * @return None + * + * \parDescription + *
Sets the shadow transfer register of high resolution positioning for falling edge
\n + * + * Call the shadow transfer update API for transfer to CR2 register. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * XMC_HRPWM_HRC_SetCompare1()
+ */ +__STATIC_INLINE void XMC_HRPWM_HRC_SetCompare2(XMC_HRPWM_HRC_t *const hrc, const uint8_t cr2_value) +{ + XMC_ASSERT("XMC_HRPWM_HRC_SetCompare2:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + hrc->SCR2 = (uint32_t) cr2_value; +} + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param dcr_value Rising edge dead time value. + * @return None + * + * \parDescription + *
Sets the shadow transfer register of rising edge dead time.
\n + * + * Call the shadow transfer update API for transfer to DCR register. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * XMC_HRPWM_HRC_SetDeadTimeFalling()
+ */ + +__STATIC_INLINE void XMC_HRPWM_HRC_SetDeadTimeRising(XMC_HRPWM_HRC_t *const hrc, uint16_t dcr_value) +{ + XMC_ASSERT("XMC_HRPWM_HRC_SetDeadTimeRising:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + hrc->SDCR = (uint32_t) dcr_value; +} + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param dcf_value Falling edge dead time value. + * @return None + * + * \parDescription + *
Sets the shadow transfer register of falling edge dead time.
\n + * + * Call the shadow transfer update API for transfer to DCR register. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * XMC_HRPWM_HRC_SetDeadTimeRising()
+ */ +__STATIC_INLINE void XMC_HRPWM_HRC_SetDeadTimeFalling(XMC_HRPWM_HRC_t *const hrc, uint16_t dcf_value) +{ + XMC_ASSERT("XMC_HRPWM_HRC_SetDeadTimeFalling:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + hrc->SDCF = (uint32_t) dcf_value; +} + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param source Source connected to high resolution channel. + * @return None + * + * \parDescription + *
Sets the source to high resolution channel
\n + * + * Sets the shadow transfer register deciding the source connected to high resolution channel. + * This also affects the CCU8 timer used for linking shadow transfer trigger. + * Call the shadow transfer update API. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ */ + +__STATIC_INLINE void XMC_HRPWM_HRC_Set_HR_Source(XMC_HRPWM_HRC_t *const hrc, XMC_HRPWM_HRC_SOURCE_t source) +{ + XMC_ASSERT("XMC_HRPWM_HRC_Set_HR_Source:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + hrc->SSC = (uint32_t) source; +} + +/*********************************************************************************************************************** + * API PROTOTYPES - HRPWM CSG SLICE + **********************************************************************************************************************/ + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Initializes the CSG channel.
\n + * + * This function is used to initialize the CSG channel.
\n + * These include:
+ * 1) Comparator setup.
+ * 2) DAC Configuration.
+ * 3) Slope generation configuration.
+ */ +void XMC_HRPWM_CSG_Init(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param input Input to comparator. Use the enum type @ref XMC_HRPWM_CSG_CMP_INPUT_t to generate the input. + * @return None + * + * \parDescription + *
Configures the input connection to inverting pin of comparator
\n + * + * Selects the HW pin that gets connected to inverting pin of comparator.
+ * Either CINA or CINB can be set. + * The non-inverting pin is connected to DAC output. + * + * \parRelated APIs:
+ * XMC_HRPWM_GetCMPInput() + */ +void XMC_HRPWM_CSG_SetCMPInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CMP_INPUT_t input); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configures the input signal to blank the comparator output
\n + * + * Configures the input signal that is used as trigger signal to blank the comparator output.
+ * It configures the signal source, required edge or level. + * The comparator output is blanked and set to passive level. + * + */ +void XMC_HRPWM_CSG_SelBlankingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configures the input signal to clamp the comparator output
\n + * + * Configures the input signal that is used as level signal to clamp the comparator output.
+ * It configures the signal source and required level. + * + */ +void XMC_HRPWM_CSG_SelClampingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configures the input signal to start the DAC slope generation
\n + * + * Configures the input signal that is used as trigger signal to start the slope generation.
+ * It configures the signal source, required edge or level. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_StopSlopeGenConfig()
+ * + */ + +void XMC_HRPWM_CSG_StartSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configures the input signal to stop the DAC slope generation
\n + * + * Configures the input that is used as trigger signal to stop the slope generation.
+ * It configures the signal source, required edge or level. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_StartSlopeGenConfig()
+ */ + +void XMC_HRPWM_CSG_StopSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configures the input signal to trigger the DAC conversion
\n + * + * Configures the input signal that is used as trigger signal to perform the DAC conversion.
+ * It configures the signal source, required edge or level.
+ * This is used when DAC is configured in static mode. + * + */ + +void XMC_HRPWM_CSG_TriggerDACConvConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configure input selection for triggering shadow transfer
\n + * + * Configure the signal used to triggering shadow transfer.
+ * It configures the signal source, required edge or level. + * + */ + +void XMC_HRPWM_CSG_TriggerShadowXferConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configure input selection for switching DAC value between DSV1 and DSV2.
\n + * + * Configure the signal used to switch DAC value between DSV1 and DSV2.
+ * It configures the signal source, required edge or level. + * + */ + + +void XMC_HRPWM_CSG_DACRefValSwitchingConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param input_clk Clock selection. + * @return None + * + * \parDescription + *
Select the clock for slope generation
\n + * + * Selects the clock source used for slope generation.
+ * These are :
+ * module clock
+ * external clock A
+ * external clock B
+ * external clock C
+ * + */ + +void XMC_HRPWM_CSG_SelSlopeGenClkInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CLK_INPUT_t input_clk); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param event Event selected for interrupt. + * @param sr Service request node. + * @return None + * + * \parDescription + *
Connects the interrupt request to serve node
\n + * + * Enables the connection between interrupt request and serve node.
+ * Each event may be connected to any of four service node available. + * Each event/interrupt needs to be enabled individually. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_EnableEvent()
+ * XMC_HRPWM_CSG_GetEventStatus()
+ */ + +void XMC_HRPWM_CSG_SetSRNode(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_IRQ_ID_t event, + const XMC_HRPWM_CSG_IRQ_SR_LINE_t sr); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_IRQ_ID_t to generate the input. + * @return uint32_t + * + * \parDescription + *
Returns the bit encoded status of selected events
\n + * + * Checks the status of selected events. The return value is non-zero is the status is set. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_EnableEvent()
+ * XMC_HRPWM_CSG_SetSRNode()
+ * + */ +__STATIC_INLINE uint32_t XMC_HRPWM_CSG_GetEventStatus(XMC_HRPWM_CSG_t *const csg, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_CSG_GetEventStatus:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + return (csg->ISTAT & mask); +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param value Value to be written to DSV2 register. + * @return None + * + * \parDescription + *
Updates the DSV2 register
\n + * + * Updates the DSV2 register.
+ * Note DSV2 register does not have shadow register. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_UpdateDACRefDSV1()
+ */ +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateDACRefDSV2(XMC_HRPWM_CSG_t *const csg, uint32_t value) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateDACRefDSV2:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->DSV2 = value & HRPWM0_CSG_DSV2_DSV2_Msk; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param value Value to be written to blanking register. + * @return None + * + * \parDescription + *
Updates the BLV register
\n + * + * Updates the blanking register.
+ * Note BLV register does not have shadow register. + * + */ +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateBlankingValue(XMC_HRPWM_CSG_t *const csg, uint8_t value) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateBlankingValue:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->BLV = (uint32_t) value; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param window Size of filter window. + * @return None + * + * \parDescription + *
Updates the filter window size
\n + * + * Updates the filter window size used for pulse swallowing, in slope generation.
+ * This value is used in slope generation when filter window is enabled. + * A certain no of clock pulses in the filter window are swallowed and applied to slope generation. + * The pulse swallowed are determined by "Pulse swallow value" + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_UpdatePulseClk()
+ */ + +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateFilterWindow(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_CMP_FILTER_WINDOW_t window) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateFilterWindow:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->CC &= ~(HRPWM0_CSG_CC_COFM_Msk); + csg->CC |= (uint32_t) window << HRPWM0_CSG_CC_COFM_Pos; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param value No of clock pulses to be swallowed in the filter window. + * @return None + * + * \parDescription + *
Updates the no of clock pulses to be swallowed in the filter window
\n + * + * Update the pulse swallow value.
+ * This value is used in slope generation when filter window is enabled for slope generation. + * No of clock pulse swallow is determined by this value. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_UpdateFilterWindow()
+ */ + +__STATIC_INLINE void XMC_HRPWM_CSG_UpdatePulseClk(XMC_HRPWM_CSG_t *const csg, uint32_t value) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdatePulseClk:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SPC = value & HRPWM0_CSG_SPC_SPSWV_Msk; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param value Value to be written to DSV1 shadow register. + * @return None + * + * \parDescription + *
Updates the DSV1 shadow register
\n + * + * Update the DSV1 shadow register.
+ * Call the shadow transfer update API. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * XMC_HRPWM_CSG_UpdateDACRefDSV2()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateDACRefDSV1(XMC_HRPWM_CSG_t *const csg, uint32_t value) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateDACRefDSV1:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SDSV1 = value & HRPWM0_CSG_SDSV1_SDSV1_Msk; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param gain Gain value. + * @return None + * + * \parDescription + *
Updates the gain value of slope generation
\n + * + * Updates the gain value of slope generation by setting SC.GCFG bits. + * The value by which DAC increments/decrements is determined by the step gain. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_UpdateDACPrescaler()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateDACStepGain(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_SLOPE_STEP_GAIN_t gain) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateDACStepGain:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SC &= ~(HRPWM0_CSG_SC_GCFG_Msk); + csg->SC |= (uint32_t) gain << HRPWM0_CSG_SC_GCFG_Pos; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param div_value Prescaler value. + * @return None + * + * \parDescription + *
Updates the prescaler value of slope generation
\n + * + * Updates the prescaler value of slope generation by setting SC.PSV + * The rate of DAC value update is determined by prescaler. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_UpdateDACStepGain()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateDACPrescaler(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_PRESCALER_DIVISION_t div_value) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateDACPrescaler:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SC &= ~(HRPWM0_CSG_SC_PSV_Msk); + csg->SC |= (uint32_t) div_value << HRPWM0_CSG_SC_PSV_Pos; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param event Event selected for interrupt. + * @return None + * + * \parDescription + *
Enables the interrupt
\n + * + * Enables the selected interrupt request which may be forwarded to service node. + * The enabled event may be connected to any of the four service nodes. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_DisableEvent()
+ * XMC_HRPWM_CSG_GetEventStatus()
+ * XMC_HRPWM_CSG_SetSRNode()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_CSG_EnableEvent(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_HRPWM_CSG_EnableEvent:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SRE |= event; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param event Event selected for interrupt. + * @return None + * + * \parDescription + *
Disables the interrupt
\n + * + * Disables the selected interrupt request which may be forwarded to service node. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_EnableEvent()
+ * XMC_HRPWM_CSG_GetEventStatus()
+ * XMC_HRPWM_CSG_SetSRNode()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_CSG_DisableEvent(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_HRPWM_CSG_DisableEvent:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SRE &= ~event; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param event Event selected for software trigger. + * @return None + * + * \parDescription + *
Software request for selected event
\n + * + * Perform a software request for selected event.This overrides any hardware trigger. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_EnableEvent()
+ * XMC_HRPWM_CSG_GetEventStatus()
+ * XMC_HRPWM_CSG_SetSRNode()
+ * XMC_HRPWM_CSG_ClrEventSW()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_CSG_SetEventSW(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_HRPWM_CSG_SetEventSW:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SWS = event; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param event Event selected for software trigger. + * @return None + * + * \parDescription + *
Cancel software request for selected event
\n + * + * Cancel the Event trigger request performed via software.
+ * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_EnableEvent()
+ * XMC_HRPWM_CSG_GetEventStatus()
+ * XMC_HRPWM_CSG_SetSRNode()
+ * XMC_HRPWM_CSG_SetEventSW()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_CSG_ClrEventSW(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_HRPWM_CSG_ClrEventSW:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SWC = event; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* #if defined(HRPWM0) */ + +#ifdef __cplusplus +} +#endif + +#endif /* HRPWM_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_hrpwm_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_hrpwm_map.h new file mode 100644 index 00000000..21a3a3b6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_hrpwm_map.h @@ -0,0 +1,176 @@ + +/** + * @file xmc_hrpwm_map.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-06-20: + * - Updated copyright and change history section. + * + * @endcond + * + */ + +/** + * + * @brief HRPWM mapping for XMC4 microcontroller family.
+ * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_hrpwm.h" + +#ifndef XMC_HRPWM_MAP_H +#define XMC_HRPWM_MAP_H + +#if ((UC_DEVICE == XMC4400) || (UC_DEVICE == XMC4200) || (UC_DEVICE == XMC4100)) +/* CSG0 - General input to control Blanking and Switch of the Comparator */ +#define XMC_HRPWM_CSG0_BL_P1_4 XMC_HRPWM_CSG_INPUT_SEL_IA +#define XMC_HRPWM_CSG0_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG0_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG0_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG0_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG0_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG0_BL_CCU40_ST0 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG0_BL_CCU41_ST0 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG0_BL_HRPWM_QOUT0 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG0_BL_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG0_BL_CCU40_SR0 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG0_BL_CCU41_SR0 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG0_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG0_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG0_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG0_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +/* CSG0 - General input to control start/stop/trigger for Slope Control Logic */ +#define XMC_HRPWM_CSG0_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG0_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG0_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG0_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG0_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG0_SC_CCU40_ST0 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG0_SC_CCU41_ST0 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG0_SC_HRPWM_QOUT0 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG0_SC_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG0_SC_CCU40_SR0 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG0_SC_CCU41_SR0 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG0_SC_HRPWM_C0O XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG0_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG0_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG0_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +/* CSG1 - General input to control Blanking and Switch of the Comparator */ +#define XMC_HRPWM_CSG1_BL_P2_4 XMC_HRPWM_CSG_INPUT_SEL_IA +#define XMC_HRPWM_CSG1_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG1_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG1_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG1_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG1_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG1_BL_CCU40_ST1 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG1_BL_CCU41_ST1 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG1_BL_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG1_BL_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG1_BL_CCU40_SR1 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG1_BL_CCU41_SR1 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG1_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG1_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG1_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG1_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +/* CSG1 - General input to control start/stop/trigger for Slope Control Logic */ +#define XMC_HRPWM_CSG1_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG1_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG1_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG1_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG1_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG1_SC_CCU40_ST1 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG1_SC_CCU41_ST1 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG1_SC_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG1_SC_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG1_SC_CCU40_SR1 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG1_SC_CCU41_SR1 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG1_SC_HRPWM_C1O XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG1_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG1_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG1_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +/* CSG2 - General input to control Blanking and Switch of the Comparator */ +#define XMC_HRPWM_CSG2_BL_P2_5 XMC_HRPWM_CSG_INPUT_SEL_IA +#define XMC_HRPWM_CSG2_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG2_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG2_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG2_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG2_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG2_BL_CCU40_ST2 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG2_BL_CCU41_ST2 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG2_BL_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG2_BL_HRPWM_QOUT3 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG2_BL_CCU40_SR2 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG2_BL_CCU41_SR2 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG2_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG2_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG2_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG2_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +/* CSG2 - General input to control start/stop/trigger for Slope Control Logic */ +#define XMC_HRPWM_CSG2_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG2_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG2_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG2_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG2_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG2_SC_CCU40_ST2 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG2_SC_CCU41_ST2 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG2_SC_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG2_SC_HRPWM_QOUT3 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG2_SC_CCU40_SR2 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG2_SC_CCU41_SR2 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG2_SC_HRPWM_C2O XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG2_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG2_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG2_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +#endif + +#endif /* XMC_HRPWM_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_i2c.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_i2c.h new file mode 100644 index 00000000..78ffb946 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_i2c.h @@ -0,0 +1,782 @@ +/** + * @file xmc_i2c.h + * @date 2016-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - Description updated
+ * - Added XMC_I2C_CH_TriggerServiceRequest() and XMC_I2C_CH_SelectInterruptNodePointer()
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-08-27: + * - Added APIs for external input for BRG configuration:XMC_I2C_CH_ConfigExternalInputSignalToBRG()
+ * + * 2015-09-01: + * - Added APIs for enabling or disabling the ACK response to a 0x00 slave address: XMC_I2C_CH_EnableSlaveAcknowledgeTo00() and + * XMC_I2C_CH_DisableSlaveAcknowledgeTo00().
+ * - Modified XMC_I2C_CH_SetInputSource() API for avoiding complete DXCR register overwriting.
+ * - Modified XMC_I2C_CH_EVENT_t enum for supporting XMC_I2C_CH_EnableEvent() and XMC_I2C_CH_DisableEvent() + * for supporting multiple events configuration
+ * + * 2015-10-02: + * - Fix 10bit addressing + * + * 2015-10-07: + * - Fix register access in XMC_I2C_CH_EnableSlaveAcknowledgeTo00() and XMC_I2C_CH_DisableSlaveAcknowledgeTo00() APIs. + * - Naming of APIs modified: from XMC_I2C_CH_EnableSlaveAcknowledgeTo00() to XMC_I2C_CH_EnableAcknowledgeAddress0() + * and from XMC_I2C_CH_DisableSlaveAcknowledgeTo00() to XMC_I2C_CH_DisableAcknowledgeAddress0(). + * + * 2016-05-20: + * - Added XMC_I2C_CH_EnableDataTransmission() and XMC_I2C_CH_DisableDataTransmission() + * + * 2016-08-17: + * - Improved documentation of slave address passing + * + * @endcond + * + */ + +#ifndef XMC_I2C_H +#define XMC_I2C_H + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_usic.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup I2C + * @brief Inter Integrated Circuit(IIC) driver for the XMC microcontroller family. + * + * USIC IIC Features:
+ * * Two-wire interface, with one line for shift clock transfer and synchronization (shift clock SCL), the other one for the data transfer (shift data SDA)
+ * * Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
+ * * Support of 7-bit addressing, as well as 10-bit addressing
+ * * Master mode operation, where the IIC controls the bus transactions and provides the clock signal.
+ * * Slave mode operation, where an external master controls the bus transactions and provides the clock signal.
+ * * Multi-master mode operation, where several masters can be connected to the bus and bus arbitration can take place, i.e. the IIC module can be master or slave.
+ The master/slave operation of an IIC bus participant can change from frame to frame.
+ * * Efficient frame handling (low software effort), also allowing DMA transfers
+ * * Powerful interrupt handling due to multitude of indication flags
+ * @{ + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#if defined(USIC0) +#define XMC_I2C0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */ +#define XMC_I2C0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */ +#endif + +#if defined(USIC1) +#define XMC_I2C1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */ +#define XMC_I2C1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */ +#endif + +#if defined(USIC2) +#define XMC_I2C2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */ +#define XMC_I2C2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */ +#endif + +#define XMC_I2C_10BIT_ADDR_GROUP (0x7800U) /**< Value to verify the address is 10-bit or not */ + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * @brief I2C Status + */ +typedef enum XMC_I2C_CH_STATUS +{ + XMC_I2C_CH_STATUS_OK, /**< Status OK */ + XMC_I2C_CH_STATUS_ERROR, /**< Status ERROR */ + XMC_I2C_CH_STATUS_BUSY /**< Status BUSY */ +} XMC_I2C_CH_STATUS_t; + +/** + * @brief I2C status + */ +typedef enum XMC_I2C_CH_STATUS_FLAG +{ + XMC_I2C_CH_STATUS_FLAG_SLAVE_SELECT = USIC_CH_PSR_IICMode_SLSEL_Msk, /**< Slave select status */ + XMC_I2C_CH_STATUS_FLAG_WRONG_TDF_CODE_FOUND = USIC_CH_PSR_IICMode_WTDF_Msk, /**< Wrong TDF status */ + XMC_I2C_CH_STATUS_FLAG_START_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_SCR_Msk, /**< Start condition received status */ + XMC_I2C_CH_STATUS_FLAG_REPEATED_START_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_RSCR_Msk, /**< Repeated start condition received status */ + XMC_I2C_CH_STATUS_FLAG_STOP_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_PCR_Msk, /**< Stop condition received status */ + XMC_I2C_CH_STATUS_FLAG_NACK_RECEIVED = USIC_CH_PSR_IICMode_NACK_Msk, /**< NACK received status */ + XMC_I2C_CH_STATUS_FLAG_ARBITRATION_LOST = USIC_CH_PSR_IICMode_ARL_Msk, /**< Arbitration lost status */ + XMC_I2C_CH_STATUS_FLAG_SLAVE_READ_REQUESTED = USIC_CH_PSR_IICMode_SRR_Msk, /**< Slave read requested status */ + XMC_I2C_CH_STATUS_FLAG_ERROR = USIC_CH_PSR_IICMode_ERR_Msk, /**< Error status */ + XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED = USIC_CH_PSR_IICMode_ACK_Msk, /**< ACK received status */ + XMC_I2C_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_IICMode_RSIF_Msk, /**< Receive start indication status */ + XMC_I2C_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_IICMode_DLIF_Msk, /**< Data lost indication status */ + XMC_I2C_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_IICMode_TSIF_Msk, /**< Transmit shift indication status */ + XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_IICMode_TBIF_Msk, /**< Transmit buffer indication status */ + XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_IICMode_RIF_Msk, /**< Receive indication status */ + XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_IICMode_AIF_Msk, /**< Alternate receive indication status */ + XMC_I2C_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_IICMode_BRGIF_Msk /**< Baud rate generator indication status */ +} XMC_I2C_CH_STATUS_FLAG_t; + +/** + * @brief I2C receiver status. The received data byte is available at the bit + * positions RBUF[7:0], whereas the additional information is monitored at the bit positions +* RBUF[12:8]. + */ +typedef enum XMC_I2C_CH_RECEIVER_STATUS_FLAG +{ + XMC_I2C_CH_RECEIVER_STATUS_FLAG_ACK = 0x1U, /**< Bit 8: Value of Received Acknowledgement bit */ + XMC_I2C_CH_RECEIVER_STATUS_FLAG_FIN = 0x2U, /**< Bit 9: A 1 at this bit position indicates that after a (repeated) start condition + followed by the address reception the first data byte of a new frame has + been received. A 0 at this bit position indicates further data bytes */ + XMC_I2C_CH_RECEIVER_STATUS_FLAG_MODE = 0x4U, /**< Bit 10: A 0 at this bit position indicates that the data byte has been received + when the device has been in slave mode, whereas a 1 indicates a reception in master mode */ + XMC_I2C_CH_RECEIVER_STATUS_FLAG_ERR = 0x8U, /**< Bit 11: A 1 at this bit position indicates an incomplete/erroneous + data byte in the receive buffer */ + XMC_I2C_CH_RECEIVER_STATUS_FLAG_ADR = 0x10 /**< Bit 12: A 0 at this bit position indicates that the programmed address + has been received. A 1 indicates a general call address. */ +} XMC_I2C_CH_RECEIVER_STATUS_FLAG_t; + +/** + * @brief I2C commands + */ +typedef enum XMC_I2C_CH_CMD +{ + XMC_I2C_CH_CMD_WRITE, /**< I2C Command Write */ + XMC_I2C_CH_CMD_READ /**< I2C Command Read */ +} XMC_I2C_CH_CMD_t; + +/** + * @brief I2C events + */ +typedef enum XMC_I2C_CH_EVENT +{ + XMC_I2C_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */ + XMC_I2C_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */ + XMC_I2C_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */ + XMC_I2C_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */ + XMC_I2C_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */ + XMC_I2C_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */ + XMC_I2C_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */ + + XMC_I2C_CH_EVENT_START_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_SCRIEN_Msk, /**< Start condition received event */ + XMC_I2C_CH_EVENT_REPEATED_START_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_RSCRIEN_Msk, /**< Repeated start condition received event */ + XMC_I2C_CH_EVENT_STOP_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_PCRIEN_Msk, /**< Stop condition received event */ + XMC_I2C_CH_EVENT_NACK = USIC_CH_PCR_IICMode_NACKIEN_Msk, /**< NACK received event */ + XMC_I2C_CH_EVENT_ARBITRATION_LOST = USIC_CH_PCR_IICMode_ARLIEN_Msk, /**< Arbitration lost event */ + XMC_I2C_CH_EVENT_SLAVE_READ_REQUEST = USIC_CH_PCR_IICMode_SRRIEN_Msk, /**< Slave read request event */ + XMC_I2C_CH_EVENT_ERROR = USIC_CH_PCR_IICMode_ERRIEN_Msk, /**< Error condition event */ + XMC_I2C_CH_EVENT_ACK = USIC_CH_PCR_IICMode_ACKIEN_Msk /**< ACK received event */ +} XMC_I2C_CH_EVENT_t; + +/** + * @brief I2C input stage selection + */ +typedef enum XMC_I2C_CH_INPUT +{ + XMC_I2C_CH_INPUT_SDA = 0U, /**< selection of sda input stage */ +#if UC_FAMILY == XMC1 + XMC_I2C_CH_INPUT_SDA1 = 3U, + XMC_I2C_CH_INPUT_SDA2 = 5U, +#endif + XMC_I2C_CH_INPUT_SCL = 1U, /**< selection of scl input stage */ +#if UC_FAMILY == XMC1 + XMC_I2C_CH_INPUT_SCL1 = 4U +#endif +} XMC_I2C_CH_INPUT_t; + +/** + * I2C channel interrupt node pointers + */ +typedef enum XMC_I2C_CH_INTERRUPT_NODE_POINTER +{ + XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */ + XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */ + XMC_I2C_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */ + XMC_I2C_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */ + XMC_I2C_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */ +} XMC_I2C_CH_INTERRUPT_NODE_POINTER_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ +/** + * @brief I2C_CH configuration structure + */ +typedef struct XMC_I2C_CH_CONFIG +{ + uint32_t baudrate; /**< baud rate configuration upto max of 400KHz */ + uint16_t address; /**< slave address + A 7-bit address needs to be left shifted it by 1. + A 10-bit address needs to be ORed with XMC_I2C_10BIT_ADDR_GROUP. */ +} XMC_I2C_CH_CONFIG_t; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param config Constant pointer to I2C channel config structure of type @ref XMC_I2C_CH_CONFIG_t + * + * @return None
+ * + * \parDescription:
+ * Initializes the I2C \a channel.
+ * + * \par + * Configures the data format in SCTR register. Sets the slave address, baud rate. Enables transmit data valid, clears status flags + * and disables parity generation.
+ * + * \parRelated APIs:
+ * XMC_USIC_CH_Enable()\n\n + */ + +void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param rate baud rate of I2C channel + * + * @return None
+ * + * \parDescription:
+ * Sets the rate of I2C \a channel. + * + * \parNote:
+ * Standard over sampling is considered if rate <= 100KHz and fast over sampling is considered if rate > 100KHz.
+ * + * \parRelated APIs:
+ * XMC_USIC_CH_SetBaudrate()\n\n + */ +XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * + * @return None
+ * + * \parDescription:
+ * Starts the I2C \a channel. + * + * \par + * Sets the USIC input operation mode to I2C mode using CCR register. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetMode()\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_Start(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_I2C); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * + * @return @ref XMC_I2C_CH_STATUS_t
+ * + * \parDescription:
+ * Stops the I2C \a channel.
+ * + * \par + * Sets the USIC input operation to IDLE mode using CCR register. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetMode()\n\n + */ +XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param service_request Service request number in the range of 0-5 + * @return None
+ * + * \parDescription:
+ * Sets the interrupt node for protocol interrupt.
+ * + * \par + * To generate interrupt for an event, node pointer should be configured with service request number(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * + * \parNote:
+ * NVIC node should be separately enabled to generate the interrupt. After setting the node pointer, desired event must be enabled. + * + * \parRelated APIs:
+ * XMC_I2C_CH_EnableEvent(), NVIC_SetPriority(), NVIC_EnableIRQ(), XMC_I2C_CH_SetInputSource()
+ */ +__STATIC_INLINE void XMC_I2C_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const uint8_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, service_request); +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection + * @param interrupt_node Interrupt node pointer to be configured. \n + * \b Range: @ref XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, + * @ref XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc. + * @param service_request Service request number.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for USIC channel events. \n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_I2C_CH_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_I2C_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, + (uint32_t)service_request); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection + * @param service_request_line service request number of the event to be triggered. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Trigger a I2C interrupt service request.\n\n + * When the I2C service request is triggered, the NVIC interrupt associated with it will be + * generated if enabled. + * + * \parRelated APIs:
+ * XMC_I2C_CH_SelectInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line) +{ + XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param input I2C channel input stage of type @ref XMC_I2C_CH_INPUT_t + * @param source Input source select for the input stage(0->DX0A, 1->DX1A, .. 7->DX7G) + * @return None
+ * + * \parDescription:
+ * Sets the input source for I2C \a channel.
+ * Defines the input stage for the corresponding input line. + * + * @note After configuring the input source for corresponding channel, interrupt node pointer is set. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetInptSource(), XMC_USIC_CH_SetInterruptNodePointer() + * + */ +__STATIC_INLINE void XMC_I2C_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_INPUT_t input, const uint8_t source) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_INSW_Msk)) | USIC_CH_DX0CR_DSEN_Msk; + XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param address I2C slave address + * @return None
+ * + * \parDescription:
+ * Sets the I2C \a channel slave address.
+ * + * \par + * Address is set in PCR_IICMode register by checking if it is in 10-bit address group or 7-bit address group. + * (If first five bits of address are assigned with 0xF0, then address mode is 10-bit mode otherwise it is 7-bit mode)\n + * @note A 7-bit address should include an additional bit at the LSB for read/write indication. For example, address 0x05 should + * be provided as 0x0a. A 10-bit address should be provided with the identifier 0b11110xx at the most significant bits. For example, + * address 0x305 should be provided as 0x7b05(bitwise OR with 0x7800). + * + * \parRelated APIs:
+ * XMC_I2C_CH_GetSlaveAddress()\n\n + */ +void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t address); + +/** + * @param channel Constant pointer to USIC channel handler of type @ref XMC_USIC_CH_t + * @return uint16_t Slave address
+ * + * \parDescription:
+ * Gets the I2C \a channel slave address.
+ * + * \par + * Returns the address using PCR_IICMode register by checking if it is in 10-bit address group or 7-bit address group.
+ * (If first five bits of address are assigned with 0xF0, then address mode is considered as 10-bit mode otherwise it is 7-bit mode)\n + * @note A 7-bit address will include an additional bit at the LSB. For example, address 0x05 will be returned as 0x0a. + * 10-bit address will not include the 10-bit address identifier 0b11110xx at the most signifcant bits. + * + * \parRelated APIs:
+ * XMC_I2C_CH_SetSlaveAddress()\n\n + */ +uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param addr I2C master address + * @param command read/write command + * @return None
+ * + * \parDescription:
+ * Starts the I2C master \a channel.
+ * + * \par + * Sends the Start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.\n + * @note Address(addr) should reserve an additional bit at the LSB for read/write indication. For example, address 0x05 should + * be provided as 0x0a. If the address is 10-bit, only most significant bits with the 10-bit identifier should be sent using this function. + * For example, if the 10-bit address is 0x305, the address should be provided as 0xf6(prepend with 0b11110, upper two bits of address 0b11, + * followed by 1-bit field for read/write). + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n + */ +void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param addr I2C master address + * @param command read/write command + * @return None
+ * + * \parDescription:
+ * Sends the repeated start condition from I2C master \a channel.
+ * + * \par + * Sends the repeated start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.\n + * @note Address(addr) should reserve an additional bit at the LSB for read/write indication. For example, address 0x05 should + * be provided as 0x0a. If the address is 10-bit, only most significant bits with the 10-bit identifier should be sent using this function. + * For example, if the 10-bit address is 0x305, the address should be provided as 0xf6(prepend with 0b11110, upper two bits of address 0b11, + * followed by 1-bit field for read/write). + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n + */ +void XMC_I2C_CH_MasterRepeatedStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return None
+ * + * \parDescription:
+ * Stops the I2C master \a channel.
+ * + * \par + * Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Stop command. + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n + */ +void XMC_I2C_CH_MasterStop(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param data data to transmit from I2C \a channel + * @return None
+ * + * \parDescription:
+ * Transmit the data from the I2C master \a channel.
+ * + * \par + * Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Send command. + * + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus()\n\n + */ +void XMC_I2C_CH_MasterTransmit(XMC_USIC_CH_t *const channel, const uint8_t data); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param data data to transmit from I2C \a channel + * @return None
+ * + * \parDescription:
+ * Transmit the data from the I2C slave \a channel.
+ * + * \par + * Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Slave Send command. + * + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus(),XMC_I2C_CH_ClearStatusFlag()\n\n + */ +void XMC_I2C_CH_SlaveTransmit(XMC_USIC_CH_t *const channel, const uint8_t data); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return None
+ * + * \parDescription:
+ * Sends the Ack request from I2C master \a channel.
+ * + * \par +* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Receive Ack command. + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit()\n\n + */ +void XMC_I2C_CH_MasterReceiveAck(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return None
+ * + * \parDescription:
+ * Sends the Nack request from I2C master \a channel.
+ * + * \par + * Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Receive Nack command. + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit()\n\n + */ +void XMC_I2C_CH_MasterReceiveNack(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return uint8_t OUTR/RBUF register data
+ * + * \parDescription:
+ * Reads the data from I2C \a channel.
+ * + * \par + * Data is read by using OUTR/RBUF register based on FIFO/non-FIFO modes. + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit()\n\n + */ +uint8_t XMC_I2C_CH_GetReceivedData(const XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return uint8_t Receiver status flag
+ * + * \parDescription:
+ * Gets the receiver status of I2C \a channel using RBUF register of bits 8-12 which gives information about receiver status. + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit()\n\n + */ +__STATIC_INLINE uint8_t XMC_I2C_CH_GetReceiverStatusFlag(XMC_USIC_CH_t *const channel) +{ + return((uint8_t)((channel->RBUF) >> 8U)); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param event ORed values of @ref XMC_I2C_CH_EVENT_t enum + * @return None
+ * + * \parDescription:
+ * Enables the input parameter @ref XMC_I2C_CH_EVENT_t event using PCR_IICMode register. + * + * \parRelated APIs:
+ * XMC_I2C_CH_DisableEvent()\n\n + */ +void XMC_I2C_CH_EnableEvent(XMC_USIC_CH_t *const channel, uint32_t event); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param event ORed values of @ref XMC_I2C_CH_EVENT_t enum + * @return None
+ * + * \parDescription:
+ * Disables the input parameter @ref XMC_I2C_CH_EVENT_t event using PCR_IICMode register. + * + * \parRelated APIs:
+ * XMC_I2C_CH_EnableEvent()\n\n + */ +void XMC_I2C_CH_DisableEvent(XMC_USIC_CH_t *const channel, uint32_t event); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return uint32_t Status byte
+ * + * \parDescription:
+ * Retrieves the status byte of I2C \a channel using PSR_IICMode register.\n + * + * \parRelated APIs:
+ * XMC_I2C_CH_ClearStatusFlag()\n\n + */ +__STATIC_INLINE uint32_t XMC_I2C_CH_GetStatusFlag(XMC_USIC_CH_t *const channel) +{ + return (channel->PSR_IICMode); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param flag Status flag + * @return None
+ * + * \parDescription:
+ * Clears the status flag of I2C \a channel by setting the input parameter \a flag in PSCR register. + * + * \parRelated APIs:
+ * XMC_I2C_CH_GetStatusFlag()\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, uint32_t flag) +{ + channel->PSCR |= flag; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection + * @param pdiv Desired divider for the external frequency input. \b Range: minimum value = 1, maximum value = 1024 \n + * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n + * This can be related to the number of samples for each logic state of the data signal. \n + * \b Range: 1 to 32. Value should be chosen based on the protocol used. + * @param combination_mode USIC channel input combination mode \n + * + * @return None + * + * \parDescription
+ * Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and + * the combination mode of the USIC channel. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, + const uint16_t pdiv, + const uint32_t oversampling, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) +{ + XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel,pdiv,oversampling,combination_mode); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return None + * + * \parDescription:
+ * Retrieves the status byte of I2C \a channel using PSR_IICMode register.\n + * + * \parRelated APIs:
+ * XMC_I2C_CH_DisableAcknowledgeAddress0()\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_EnableAcknowledgeAddress0(XMC_USIC_CH_t *const channel) +{ + channel->PCR_IICMode |= USIC_CH_PCR_IICMode_ACK00_Msk; +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return None + * + * \parDescription:
+ * This bit defines that slave device should not be sensitive to the slave address 00H.\n + * + * \parRelated APIs:
+ * XMC_I2C_CH_EnableAcknowledgeAddress0()\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_DisableAcknowledgeAddress0(XMC_USIC_CH_t *const channel) +{ + channel->PCR_IICMode &= ~USIC_CH_PCR_IICMode_ACK00_Msk; +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection + * @return None + * + * \parDescription
+ * Enable data transmission.\n\n + * Use this function in combination with XMC_I2C_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode() + * + * \parRelated APIs:
+ * XMC_I2C_CH_DisableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection + * @return None + * + * \parDescription
+ * Disable data transmission.\n\n + * Use this function in combination with XMC_I2C_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * + * \parRelated APIs:
+ * XMC_I2C_CH_EnableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_i2s.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_i2s.h new file mode 100644 index 00000000..60808167 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_i2s.h @@ -0,0 +1,837 @@ +/** + * @file xmc_i2s.h + * @date 2016-06-30 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-08-21: + * - Initial
+ * + * 2015-08-24: + * - Added APIs for enabling/disabling delay compensation XMC_I2S_CH_DisableDelayCompensation() and + * XMC_I2S_CH_EnableDelayCompensation()
+ * + * 2015-09-01: + * - Modified XMC_I2S_CH_SetInputSource() for avoiding complete DXCR register overwriting.
+ * - Modified XMC_I2S_CH_EVENT_t enum for supporting XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent()
+ * for supporting multiple events configuration
+ * + * 2015-09-14: + * - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length
+ * + * 2016-05-20: + * - Added XMC_I2S_CH_EnableDataTransmission() and XMC_I2S_CH_DisableDataTransmission() + * + * 2016-06-30: + * - Documentation updates. + * + * @endcond + * + */ + +#ifndef XMC_I2S_H_ +#define XMC_I2S_H_ + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ +#include "xmc_usic.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup I2S + * @brief (IIS) driver for the XMC microcontroller family. + * + * USIC IIS Features:
+ * @{ + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#if defined(USIC0) +#define XMC_I2S0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */ +#define XMC_I2S0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */ +#endif + +#if defined(USIC1) +#define XMC_I2S1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */ +#define XMC_I2S1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */ +#endif + +#if defined(USIC2) +#define XMC_I2S2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */ +#define XMC_I2S2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */ +#endif +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * @brief I2S Status + */ +typedef enum XMC_I2S_CH_STATUS +{ + XMC_I2S_CH_STATUS_OK, /**< Status OK */ + XMC_I2S_CH_STATUS_ERROR, /**< Status ERROR */ + XMC_I2S_CH_STATUS_BUSY /**< Status BUSY */ +} XMC_I2S_CH_STATUS_t; + +/** + * @brief I2S status flag + */ +typedef enum XMC_I2S_CH_STATUS_FLAG +{ + XMC_I2S_CH_STATUS_FLAG_WORD_ADDRESS = USIC_CH_PSR_IISMode_WA_Msk, /**< Word Address status */ + XMC_I2S_CH_STATUS_FLAG_DX2S = USIC_CH_PSR_IISMode_DX2S_Msk, /**< Status of WA input(DX2) signal*/ + XMC_I2S_CH_STATUS_FLAG_DX2T_EVENT_DETECTED = USIC_CH_PSR_IISMode_DX2TEV_Msk, /**< Status for WA input signal transition */ + XMC_I2S_CH_STATUS_FLAG_WA_FALLING_EDGE_EVENT = USIC_CH_PSR_IISMode_WAFE_Msk, /**< Falling edge of the WA output + signal has been generated */ + XMC_I2S_CH_STATUS_FLAG_WA_RISING_EDGE_EVENT = USIC_CH_PSR_IISMode_WARE_Msk, /**< Rising edge of the WA output + signal has been generated */ + XMC_I2S_CH_STATUS_FLAG_WA_GENERATION_END = USIC_CH_PSR_IISMode_END_Msk, /**< The WA generation has ended */ + XMC_I2S_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_IISMode_RSIF_Msk, /**< Receive start indication status */ + XMC_I2S_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_IISMode_DLIF_Msk, /**< Data lost indication status */ + XMC_I2S_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_IISMode_TSIF_Msk, /**< Transmit shift indication status */ + XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_IISMode_TBIF_Msk, /**< Transmit buffer indication status */ + XMC_I2S_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_IISMode_RIF_Msk, /**< Receive indication status */ + XMC_I2S_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_IISMode_AIF_Msk, /**< Alternate receive indication status */ + XMC_I2S_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_IISMode_BRGIF_Msk /**< Baud rate generator indication status */ +} XMC_I2S_CH_STATUS_FLAG_t; + +/** + * @brief I2S Baudrate Generator shift clock output +*/ +typedef enum XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT +{ + XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK, /**< Baudrate Generator shift clock output: SCLK*/ + XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 /**< Clock obtained as input from master: DX1*/ +} XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t; + +/** + * @brief I2S channel interrupt node pointers + */ +typedef enum XMC_I2S_CH_INTERRUPT_NODE_POINTER +{ + XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */ + XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */ + XMC_I2S_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */ + XMC_I2S_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */ + XMC_I2S_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */ +} XMC_I2S_CH_INTERRUPT_NODE_POINTER_t; + +/** + * @brief I2S events + */ +typedef enum XMC_I2S_CH_EVENT +{ + XMC_I2S_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */ + XMC_I2S_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */ + XMC_I2S_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */ + XMC_I2S_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */ + XMC_I2S_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */ + XMC_I2S_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */ + XMC_I2S_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */ + + XMC_I2S_CH_EVENT_WA_FALLING_EDGE = USIC_CH_PCR_IISMode_WAFEIEN_Msk << 2U, /**< WA falling edge event */ + XMC_I2S_CH_EVENT_WA_RISING_EDGE = USIC_CH_PCR_IISMode_WAREIEN_Msk << 2U, /**< WA rising edge event */ + XMC_I2S_CH_EVENT_WA_GENERATION_END = USIC_CH_PCR_IISMode_ENDIEN_Msk << 2U, /**< END event */ + XMC_I2S_CH_EVENT_DX2TIEN_ACTIVATED = USIC_CH_PCR_IISMode_DX2TIEN_Msk << 2U /**< WA input signal transition event*/ +} XMC_I2S_CH_EVENT_t; + +/** + * @brief Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal. + */ +typedef enum XMC_I2S_CH_WA_POLARITY +{ + XMC_I2S_CH_WA_POLARITY_DIRECT = 0x0UL, /**< The SELO outputs have the same polarity + as the WA signal (active high) */ + XMC_I2S_CH_WA_POLARITY_INVERTED = 0x1UL << USIC_CH_PCR_IISMode_SELINV_Pos /**< The SELO outputs have the inverted + polarity to the WA signal (active low)*/ +} XMC_I2S_CH_WA_POLARITY_t; + +/** + * @brief Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal. + */ +typedef enum XMC_I2S_CH_CHANNEL +{ + XMC_I2S_CH_CHANNEL_1_LEFT = 0U, /**< Channel 1 (left) */ + XMC_I2S_CH_CHANNEL_2_RIGHT = 1U /**< Channel 2 (right) */ +} XMC_I2S_CH_CHANNEL_t; + +/** + * @brief I2S input stage selection + */ +typedef enum XMC_I2S_CH_INPUT +{ + XMC_I2S_CH_INPUT_DIN0 = 0UL, /**< Data input stage 0 */ + XMC_I2S_CH_INPUT_SLAVE_SCLKIN = 1UL, /**< Clock input stage */ + XMC_I2S_CH_INPUT_SLAVE_WA = 2UL, /**< WA input stage */ +#if UC_FAMILY == XMC1 + XMC_I2S_CH_INPUT_DIN1 = 3UL, /**< Data input stage 1 */ + XMC_I2S_CH_INPUT_DIN2 = 4UL, /**< Data input stage 2 */ + XMC_I2S_CH_INPUT_DIN3 = 5UL /**< Data input stage 3 */ +#endif +} XMC_I2S_CH_INPUT_t; + +/** + * @brief Defines the I2S bus mode + */ +typedef enum XMC_I2S_CH_BUS_MODE +{ + XMC_I2S_CH_BUS_MODE_MASTER, /**< I2S Master */ + XMC_I2S_CH_BUS_MODE_SLAVE /**< I2S Slave */ +} XMC_I2S_CH_BUS_MODE_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ +/** + * @brief I2S_CH configuration structure + */ +typedef struct XMC_I2S_CH_CONFIG +{ + uint32_t baudrate; /**< Module baud rate for communication */ + uint8_t data_bits; /**< Data word length. A data frame can consists of several data words. \n + Value configured as USIC channel word length. \n + \b Range: minimum= 1, maximum= 16*/ + uint8_t frame_length; /**< Number of data bits transferred after a change of signal WA (data frame). \n + Configured as USIC channel frame length. \n + \b Range: minimum= 1, maximum= 63*/ + uint8_t data_delayed_sclk_periods; /**< Data delay defined in sclk periods */ + XMC_I2S_CH_WA_POLARITY_t wa_inversion; /**< Enable inversion of Slave select signal relative to the internal WA */ + XMC_I2S_CH_BUS_MODE_t bus_mode; /**< Bus mode MASTER/SLAVE */ +} XMC_I2S_CH_CONFIG_t; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0, XMC_I2S1_CH1,XMC_I2S2_CH0, XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @param config Constant pointer to I2S configuration structure of type @ref XMC_I2S_CH_CONFIG_t. + * @return XMC_I2S_CH_STATUS_t Status of initializing the USIC channel for I2S protocol.\n + * \b Range: @ref XMC_I2S_CH_STATUS_OK if initialization is successful.\n + * @ref XMC_I2S_CH_STATUS_ERROR if configuration of baudrate failed. + * + * \parDescription
+ * Initializes the USIC channel for I2S protocol.\n\n + * During the initialization, USIC channel is enabled and baudrate is configured. + * After each change of the WA signal, a complete data frame is intended to be transferred (frame length <= system word length). + * The number of data bits transferred after a change of signal WA is defined by config->frame_length. + * A data frame can consist of several data words with a data word length defined by config->data_bits. + * The changes of signal WA define the system word length as the number of SCLK cycles between two changes of WA. + * The system word length is set by default to the frame length defined by config->frame_length. + * + * XMC_I2S_CH_Start() should be invoked after the initialization to enable the channel. + * + * \parRelated APIs:
+ * XMC_I2S_CH_Start(), XMC_I2S_CH_Stop(), XMC_I2S_CH_Transmit(), XMC_I2S_CH_SetSystemWordLength()\n\n\n + */ +void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the selected USIC channel to operate in I2S mode, by setting CCR.MODE bits.\n\n + * It should be executed after XMC_I2S_CH_Init() during initialization. By invoking XMC_I2S_CH_Stop(), the MODE is set + * to IDLE state. Call XMC_I2S_CH_Start() to set the I2S mode again, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_I2S_CH_Init(), XMC_I2S_CH_Stop() + */ +__STATIC_INLINE void XMC_I2S_CH_Start(XMC_USIC_CH_t *const channel) +{ + /* USIC channel in I2S mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_I2S); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for stopping is processed. \n + * XMC_I2S_CH_STATUS_OK- If the USIC channel is successfully put to IDLE mode. \n + * XMC_I2S_CH_STATUS_BUSY- If the USIC channel is busy transmitting data. + * + * \parDescription:
+ * Set the selected I2S channel to IDLE mode, by clearing CCR.MODE bits.\n\n + * After calling XMC_I2S_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_I2S_CH_Start() has to be + * invoked to start the communication again. + * + * \parRelated APIs:
+ * XMC_I2S_CH_Start() + */ +XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param rate Bus speed in bits per second + * + * @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for setting baudrate is processed. \n + * XMC_I2S_CH_STATUS_OK- If the baudrate is successfully changed. \n + * XMC_I2S_CH_STATUS_ERROR- If the new baudrate value is out of range. + * + * \parDescription:
+ * Sets the bus speed in bits per second + * + * \parRelated APIs:
+ * XMC_I2S_CH_Init(), XMC_I2S_CH_Stop() + */ +XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param sclk_cycles_system_word_length system word length in terms of sclk clock cycles. + * + * @return None + * + * \parDescription:
+ * Configures the system word length by setting BRG.DCTQ bit field.\n\n + * This value has to be always higher than 1U and lower than the data with (SCTR.FLE) + * + */ +void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param data Data to be transmitted + * @param channel_number Communication output channel of the I2S, based on this channel selection TCI(Transmit control information)is updated.\n + * Refer @ref XMC_I2S_CH_CHANNEL_t for valid values. + * + * @return None + * + * \parDescription:
+ * Puts the data into FIFO, if FIFO mode is enabled or else into standard buffer, by setting the proper mode.\n\n + * TCI(Transmit Control Information) allows dynamic control of output channel during data transfers. To support this auto + * update, TCSR.WAMD(Automatic WA mode) will be enabled during the initialization using XMC_I2S_CH_Init() for all modes. + * + * + * \parRelated APIs:
+ * XMC_I2S_CH_Receive() + */ +void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNEL_t channel_number); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param channel_number Communication output channel of the I2S, based on this mode TCI(Transmit control information)is updated.\n + * Refer @ref XMC_I2S_CH_CHANNEL_t for valid values. + * + * @return None + * + * \parDescription:
+ * Transmits a dummy data(FFFFH) to provide clock for slave and receives the data from the slave.\n\n + * XMC_I2S_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data + * XMC_I2S_CH_GetReceivedData() can be invoked to read the data from the buffers. + * + * \parRelated APIs:
+ * XMC_I2S_CH_GetReceivedData() + */ +__STATIC_INLINE void XMC_I2S_CH_Receive(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CHANNEL_t channel_number) +{ + /* Transmit dummy data */ + XMC_I2S_CH_Transmit(channel, (uint16_t)0xffffU , channel_number); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return uint16_t Data read from the receive buffer. + * + * \parDescription:
+ * Reads data from the receive buffer based on the FIFO selection.\n\n + * Invocation of XMC_I2S_CH_Receive() receives the data and place it into receive buffer. After receiving the data + * XMC_I2S_CH_GetReceivedData() can be used to read the data from the buffer. + * + * \parRelated APIs:
+ * XMC_I2S_CH_Receive() + */ +uint16_t XMC_I2S_CH_GetReceivedData(XMC_USIC_CH_t *const channel); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the order of data transfer from LSB to MSB, by clearing SCTR.SDIR bit.\n\n + * This is typically based on the slave settings. Invoke XMC_I2S_CH_SetBitOrderLsbFirst() to set direction as needed in + * the program. + * + * \parRelated APIs:
+ * XMC_I2S_CH_SetBitOrderMsbFirst() + */ +__STATIC_INLINE void XMC_I2S_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t *const channel) +{ + channel->SCTR &= (uint32_t)~USIC_CH_SCTR_SDIR_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.\n\n + * This is typically based on the slave settings. This is not set during XMC_I2S_CH_Init(). + * Invoke XMC_I2S_CH_SetBitOrderMsbFirst() to set direction as needed in the program. + * + * \parRelated APIs:
+ * XMC_I2S_CH_SetBitOrderLsbFirst() + */ +__STATIC_INLINE void XMC_I2S_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t *const channel) +{ + channel->SCTR |= (uint32_t)USIC_CH_SCTR_SDIR_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param event Protocol events which have to be enabled. + * Refer @ XMC_I2S_CH_EVENT_t for valid values. OR combinations of these enum items can be used + * as input. + * + * @return None + * + * \parDescription:
+ * Enables the I2S protocol specific events, by configuring PCR register.\n\n + * Events can be enabled as needed using XMC_I2S_CH_EnableEvent(). + * XMC_I2S_CH_DisableEvent() can be used to disable the events. + * + * \parRelated APIs:
+ * XMC_I2S_CH_DisableEvent() + */ +void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param event Protocol events which have to be disabled. + * Refer @ XMC_I2S_CH_EVENT_t for valid values. OR combinations of these enum item can be used + * as input. + * + * @return None + * + * \parDescription:
+ * Disables the I2S protocol specific events, by configuring PCR register.\n\n + * After disabling the events, XMC_I2S_CH_EnableEvent() has to be invoked to re-enable the events. + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableEvent() + */ +void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return uint32_t Status of I2S protocol events. + * + * \parDescription:
+ * Returns the status of the events, by reading PSR register.\n\n + * This indicates the status of the all the events, for I2S communication. + * + * \parRelated APIs:
+ * XMC_I2S_CH_ClearStatusFlag() + */ +__STATIC_INLINE uint32_t XMC_I2S_CH_GetStatusFlag(XMC_USIC_CH_t *const channel) +{ + return channel->PSR_IISMode; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param flag Protocol event status to be cleared for detection of next occurence. + * Refer @ XMC_I2S_CH_STATUS_FLAG_t for valid values. OR combinations of these enum item can be used + * as input. + * @return None + * + * \parDescription:
+ * Clears the events specified, by setting PSCR register.\n\n + * During communication the events occurred have to be cleared to detect their next occurence.\n + * e.g: During transmission Transmit buffer event occurs to indicating data word transfer has started. This + * event has to be cleared after transmission of each data word. Otherwise next event cannot be recognized. + * + * \parRelated APIs:
+ * XMC_I2S_CH_GetStatusFlag() + */ +__STATIC_INLINE void XMC_I2S_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag) +{ + channel->PSCR |= flag; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Enables the generation of Master clock by setting PCR.MCLK bit.\n\n + * This clock can be used as a clock reference for external devices. This is not enabled during initialization in + * XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by + * XMC_I2S_CH_DisableMasterClock(). + * + * \parRelated APIs:
+ * XMC_I2S_CH_DisableMasterClock() + */ +__STATIC_INLINE void XMC_I2S_CH_EnableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_IISMode |= (uint32_t)USIC_CH_PCR_IISMode_MCLK_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Disables the generation of Master clock by clearing PCR.MCLK bit.\n\n + * This clock can be enabled by invoking XMC_I2S_CH_EnableMasterClock() as needed in the program. + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableMasterClock() + */ +__STATIC_INLINE void XMC_I2S_CH_DisableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_IISMode &= (uint32_t)~USIC_CH_PCR_IISMode_MCLK_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param clock_output shift clock source.\n + * Refer @ref XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t for valid inputs. + * + * @return None + * + * \parDescription:
+ * Configures the shift clock source by setting BRG.SCLKOSEL.\n\n + * In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available + * for external slave devices by SCLKOUT signal.\n + * In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.\n + */ +__STATIC_INLINE void XMC_I2S_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) +{ + XMC_USIC_CH_ConfigureShiftClockOutput(channel, (XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t)0U, + (XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param word_length Number of bits to be configured for a data word. \n + * \b Range: 1 to 16. + * + * @return None + * + * \parDescription
+ * Defines the data word length.\n\n + * Sets the number of bits to represent a data word. Frame length should be a multiple of word length. + * + * \parRelated APIs:
+ * XMC_I2S_CH_SetFrameLength() + */ +__STATIC_INLINE void XMC_I2S_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length) +{ + XMC_USIC_CH_SetWordLength(channel, word_length); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param frame_length Number of bits in a frame. \n + * \b Range: 1 to 64. + * + * @return None + * + * \parDescription
+ * Define the data frame length.\n\n + * Set the number of bits to be serially transmitted in a frame. + * The frame length should be multiples of word length. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetWordLength() + */ +__STATIC_INLINE void XMC_I2S_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length) +{ + XMC_USIC_CH_SetFrameLength(channel, frame_length); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input I2S channel input stage.\n + * Refer @ref XMC_I2S_CH_INPUT_t for valid values + * @param source Input source select for the input stage. + * Range : [0 to 7] + * + * @return None + * + * \parDescription
+ * Selects the data source for I2S input stage, by configuring DXCR.DSEL bits.\n\n + * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the + * input stages like DX0CR, DX1CR etc. This is not done during initialization. This has to be configured before starting + * the I2S communication. + */ +__STATIC_INLINE void XMC_I2S_CH_SetInputSource(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_INPUT_t input, + const uint8_t source) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_DSEN_Msk)) | USIC_CH_DX0CR_INSW_Msk; + XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param wa_inversion Polarity of the word address signal.\n + * Refer @ref XMC_I2S_CH_WA_POLARITY_t for valid values + * + * @return None + * + * \parDescription
+ * Set the polarity of the word address signal, by configuring PCR.SELINV bit.\n\n + * Normally WA signal is active low level signal. This is configured + * in XMC_I2S_CH_Init() during initialization. Invoke XMC_I2S_CH_WordAddressSignalPolarity() with desired settings as + * needed later in the program. + */ +__STATIC_INLINE void XMC_I2S_CH_WordAddressSignalPolarity(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_WA_POLARITY_t wa_inversion) +{ + /* Configuration of Protocol Control Register */ + channel->PCR_IISMode = (uint32_t)((channel->PCR_IISMode & (~USIC_CH_PCR_IISMode_SELINV_Msk)) | (uint32_t)wa_inversion); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input I2S channel input stage.\n + * Refer @ref XMC_I2S_CH_INPUT_t for valid inputs. + * + * @return None + * + * \parDescription
+ * Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y = \a input).\n\n + * This is not set in XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableInputInversion() as needed later in the program. To + * disable the inversion XMC_I2S_CH_DisableInputInversion() can be invoked. + * + * \parRelated APIs:
+ * XMC_I2S_CH_DisableInputInversion() + */ +__STATIC_INLINE void XMC_I2S_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_INPUT_t input) +{ + XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input I2S channel input stage.\n + * Refer @ref XMC_I2S_CH_INPUT_t for valid inputs. + * + * @return None + * + * \parDescription
+ * Disables the polarity inversion of input data signal, by clearing DXyCR.DPOL(where y = \a input).\n\n + * Resets the input data polarity. Invoke XMC_I2S_CH_EnableInputInversion() to apply inversion. + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableInputInversion() + */ +__STATIC_INLINE void XMC_I2S_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_INPUT_t input) +{ + XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param service_request Service request number. + Range: [0 to 5] + * + * @return None + * + * \parDescription
+ * Sets the interrupt node for I2S channel events.\n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so. This is not configured in XMC_I2S_CH_Init() during + * initialization. + * + * \parNote::
+ * 1. NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableEvent() + */ +__STATIC_INLINE void XMC_I2S_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const uint8_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, (uint32_t)service_request); +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @param interrupt_node Interrupt node pointer to be configured. \n + * \b Range: @ref XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, + * @ref XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc. + * @param service_request Service request number.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for USIC channel events. \n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, + (uint32_t)service_request); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @param service_request_line service request number of the event to be triggered. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Trigger a I2S interrupt service request.\n\n + * When the I2S service request is triggered, the NVIC interrupt associated with it will be + * generated if enabled. + * + * \parRelated APIs:
+ * XMC_I2S_CH_SelectInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line) +{ + XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @return None + * + * \parDescription
+ * Enables delay compensation. \n\n + * + * Delay compensation can be applied to the receive path. + * \parRelated APIs:
+ * XMC_I2S_CH_DisableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_EnableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_EnableDelayCompensation(channel); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @return None + * + * \parDescription
+ * Disables delay compensation.. \n\n + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_DisableDelayCompensation(channel); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @return None + * + * \parDescription
+ * Enable data transmission.\n\n + * Use this function in combination with XMC_I2S_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode() + * + * \parRelated APIs:
+ * XMC_I2S_CH_DisableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @return None + * + * \parDescription
+ * Disable data transmission.\n\n + * Use this function in combination with XMC_I2S_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ +#endif /* XMC_I2S_H_ */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ledts.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ledts.h new file mode 100644 index 00000000..0934eda6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_ledts.h @@ -0,0 +1,1052 @@ +/** + * @file xmc_ledts.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * - Documentation improved
+ * - New API added: XMC_LEDTS_SetActivePADNo()
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * @endcond + * + */ + +#ifndef XMC_LEDTS_H +#define XMC_LEDTS_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +#if defined(LEDTS0) +#include "xmc_scu.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup LEDTS + * @brief LED and Touch-Sense control(LEDTS) driver for the XMC controller family. + * + * The LED and Touch-Sense (LEDTS) drives LEDs and controls touch pads used as human-machine interface (HMI) in an + * application. The LEDTS can measure the capacitance of up to 8 touch pads, can also drive up to 64 LEDs in an LED matrix. + * Touch pads and LEDs can share pins to minimize the number of pins needed for such applications, this is realized by + * the module controlling the touch pads and driving the LEDs in a time-division multiplexed manner. + * + * This device contains LEDTS kernel that has an LED driving function and a touch-sensing function. + * + * It is recommended to set up all configurations for the LEDTS in all Special Function Registers(SFR) before + * enabling and starting LED and/or touch-sense function(s). + * + * This Low Level Driver(LLD) provides APIs to configure and control LED functionality, Touch-Sense functionality and + * features common to both functionalities. + * + * LED features: + * -# Configuration structure to configure LED functionality (XMC_LEDTS_LED_CONFIG_t) and initialization funtion + * (XMC_LEDTS_InitLED()). + * -# Selection of number of LED columns, active column level and enabling LED funtionality (XMC_LEDTS_InitLED()). + * -# Setting line pattern to be displayed on LED column (XMC_LEDTS_SetLEDLinePattern()). + * -# Brightness control of LED column (XMC_LEDTS_SetColumnBrightness()). + * -# Setting number of columns to be activated (XMC_LEDTS_SetNumOfLEDColumns()). + * + * Touch-Sense features: + * -# Configuration structure to perform basic Touch-Sense functionality (XMC_LEDTS_TS_CONFIG_BASIC_t) settings and + * initialization funtion (XMC_LEDTS_InitTSBasic()). + * -# Configuration structure to perform advanced Touch-Sense functionality (XMC_LEDTS_TS_CONFIG_ADVANCED_t) settings + * and initialization function (XMC_LEDTS_InitTSAdvanced()). + * -# Setting number of touch inputs and acculumate count on touch input (XMC_LEDTS_InitTSBasic()). + * -# Enabling/disabling of common compare, Touch-Sense counter auto reset and Touch-Sense funtionality. + * (XMC_LEDTS_InitTSBasic()). + * -# Set number of mask bits for time frame validation and first touch input to be active. (XMC_LEDTS_InitTSAdvanced()). + * -# Enable/disable time frame interrupt, external pull-up on touch pin and hardware or software control of + * pad turn (XMC_LEDTS_InitTSAdvanced()). + * -# Setting size of common oscillation window for all touch-sense inputs (XMC_LEDTS_SetCommonOscillationWindow()). + * -# Setting size of oscillation window for a touch-sense input (XMC_LEDTS_SetOscillationWindow()). + * + * Common features: + * -# Global configuration structure XMC_LEDTS_GLOBAL_CONFIG_t and initialization function XMC_LEDTS_InitGlobal(). + * -# Selection of Clock source for LEDTS module (XMC_LEDTS_InitGlobal()). + * -# Kick-start and stop of LEDTS module (XMC_LEDTS_StartCounter() / XMC_LEDTS_StopCounter()). + * -# Read and clear of interrupt status flags (XMC_LEDTS_ReadInterruptFlag() / XMC_LEDTS_ClearInterruptFlag()). + * -# Reading of previous active column number (XMC_LEDTS_ReadFNCOL()). + * -# Enable/Disable Interrupts(XMC_LEDTS_EnableInterrupt() / XMC_LEDTS_DisableInterrupt()). + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#if defined(LEDTS0) +#define XMC_LEDTS0 ((XMC_LEDTS_GLOBAL_t *) LEDTS0) /**< Typedef for LEDTS kernel0*/ +#define XMC_LEDTS_CHECK_LEDTS0(PTR) (PTR == XMC_LEDTS0) +#else +#define XMC_LEDTS_CHECK_LEDTS0(PTR) 0 +#endif + +#if defined(LEDTS1) +#define XMC_LEDTS1 ((XMC_LEDTS_GLOBAL_t *) LEDTS1) /**< Typedef for LEDTS kernel1*/ +#define XMC_LEDTS_CHECK_LEDTS1(PTR) (PTR == XMC_LEDTS1) +#else +#define XMC_LEDTS_CHECK_LEDTS1(PTR) 0 +#endif + +#if defined(LEDTS2) +#define XMC_LEDTS2 ((XMC_LEDTS_GLOBAL_t *) LEDTS2) /**< Typedef for LEDTS kernel2*/ +#define XMC_LEDTS_CHECK_LEDTS2(PTR) (PTR == XMC_LEDTS2) +#else +#define XMC_LEDTS_CHECK_LEDTS2(PTR) 0 +#endif + +#define XMC_LEDTS_CHECK_KERNEL_PTR(PTR) (XMC_LEDTS_CHECK_LEDTS0(PTR) || \ + XMC_LEDTS_CHECK_LEDTS1(PTR) || \ + XMC_LEDTS_CHECK_LEDTS2(PTR)) + +/** + * Defines LEDTS module structure. This holds data and configuration registers of LEDTS modules. Use type + * XMC_LEDTS_GLOBAL_t for this data structure.\n + */ +typedef struct XMC_LEDTS_GLOBAL{ /*!< (@ 0x50020000) LEDTS Structure */ + __I uint32_t ID; /*!< (@ 0x50020000) Module Identification Register */ + __IO uint32_t GLOBCTL; /*!< (@ 0x50020004) Global Control Register */ + __IO uint32_t FNCTL; /*!< (@ 0x50020008) Function Control Register */ + __O uint32_t EVFR; /*!< (@ 0x5002000C) Event Flag Register */ + __IO uint32_t TSVAL; /*!< (@ 0x50020010) Touch-sense TS-Counter Value */ + __IO uint32_t LINE[2]; /*!< (@ 0x50020014) Line Pattern Register 0 */ + __IO uint32_t LDCMP[2]; /*!< (@ 0x5002001C) LED Compare Register 0 */ + __IO uint32_t TSCMP[2]; /*!< (@ 0x50020024) Touch-sense Compare Register 0 */ + } XMC_LEDTS_GLOBAL_t; + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +/** + * Defines typedef for LEDTS Global data structure. Use type XMC_LEDTS_t for this data structure.\n + */ +typedef XMC_LEDTS_GLOBAL_t XMC_LEDTS_t; + +#if defined(LEDTS0) +#define XMC_LEDTS0 ((XMC_LEDTS_GLOBAL_t *) LEDTS0) /**< Typedef for LEDTS kernel0*/ +#endif + +#if defined(LEDTS1) +#define XMC_LEDTS1 ((XMC_LEDTS_GLOBAL_t *) LEDTS1) /**< Typedef for LEDTS kernel1*/ +#endif + + +/** + * Defines return value of an API. Use type XMC_LEDTS_STATUS_t for this enum. + */ +typedef enum XMC_LEDTS_STATUS +{ + XMC_LEDTS_STATUS_SUCCESS = 0, /**< API fulfills request */ + XMC_LEDTS_STATUS_RUNNING = 1, /**< The kernel-counter is currently running */ + XMC_LEDTS_STATUS_ERROR = 2, /**< API cannot fulfill request */ + XMC_LEDTS_STATUS_IDLE = 3 /**< The kernel-counter is currently idle */ +} XMC_LEDTS_STATUS_t; + +/** + * Defines return value for checking interrupt flag. Use type XMC_LEDTS_FLAG_STATUS_t for this enum. + */ +typedef enum XMC_LEDTS_FLAG_STATUS +{ + XMC_LEDTS_FLAG_STATUS_NO = 0, /**< Flag not raised */ + XMC_LEDTS_FLAG_STATUS_YES = 1 /**< Flag is raised */ +} XMC_LEDTS_FLAG_STATUS_t; + +/** + * Defines Touch-Sense function enable/disable. Use type XMC_LEDTS_TS_FUNC_t for this enum. + */ +typedef enum XMC_LEDTS_TS_FUNC +{ + XMC_LEDTS_TS_FUNC_DISABLE = 0, /**< Disable touch-sense function */ + XMC_LEDTS_TS_FUNC_ENABLE = 1 /**< Enable touch-sense function */ +} XMC_LEDTS_TS_FUNC_t; + +/** + * Defines LED function enable/disable. Use type XMC_LEDTS_LED_FUNC_t for this enum. + */ +typedef enum XMC_LEDTS_LED_FUNC +{ + XMC_LEDTS_LED_FUNC_DISABLE = 0, /**< Disable LED function */ + XMC_LEDTS_LED_FUNC_ENABLE = 1 /**< Enable LED function */ +} XMC_LEDTS_LED_FUNC_t; + +/** + * Defines Clock master enable/disable. Use type for XMC_LEDTS_CLOCK_TYPE_t for this enum. + */ +typedef enum XMC_LEDTS_CLOCK_TYPE +{ + XMC_LEDTS_CLOCK_TYPE_MASTER = 0, /**< Kernel generates its own clock */ + XMC_LEDTS_CLOCK_TYPE_SLAVE = 1 /**< Clock is taken from another master kernel */ +} XMC_LEDTS_CLOCK_TYPE_t; + +/** + * Defines enable/disable of autoscan time period synchronization. Use type XMC_LEDTS_TP_SYNC_t for this enum. + */ +typedef enum XMC_LEDTS_TP_SYNC +{ + XMC_LEDTS_TP_SYNC_DISABLE = 0, /**< Synchronization is disabled */ + XMC_LEDTS_TP_SYNC_ENABLE = 1 /**< Synchronization enabled on Kernel0 autoscan time period */ +} XMC_LEDTS_TP_SYNC_t; + +/** + * Defines Suspend request configuration. Use type XMC_LEDTS_SUSPEND_t for this enum. + */ +typedef enum XMC_LEDTS_SUSPEND +{ + XMC_LEDTS_SUSPEND_DISABLE = 0, /**< Ignore suspend request */ + XMC_LEDTS_SUSPEND_ENABLE = 1 /**< Enable suspend according to request */ +} XMC_LEDTS_SUSPEND_t; + +/** + * Defines number of bits to mask for time frame event validation. Use type XMC_LEDTS_TS_COUNTER_MASK_t for this enum. + */ +typedef enum XMC_LEDTS_TS_COUNTER_MASK +{ + XMC_LEDTS_TS_COUNTER_MASK_1_LSB = 0, /**< Mask LSB bit only */ + XMC_LEDTS_TS_COUNTER_MASK_2_LSB = 1, /**< Mask 2 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_3_LSB = 2, /**< Mask 3 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_4_LSB = 3, /**< Mask 4 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_5_LSB = 4, /**< Mask 5 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_6_LSB = 5, /**< Mask 6 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_7_LSB = 6, /**< Mask 7 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_8_LSB = 7 /**< Mask 8 LSB bits */ +} XMC_LEDTS_TS_COUNTER_MASK_t; + +/** + * Defines Enable/disable of (extended) time frame validation. Use type XMC_LEDTS_TF_VALIDATION_t for this enum. + */ +typedef enum XMC_LEDTS_TF_VALIDATION +{ + XMC_LEDTS_TF_VALIDATION_DISABLE = 0, /**< Disable time frame validation */ + XMC_LEDTS_TF_VALIDATION_ENABLE = 1 /**< Enable time frame validation */ +} XMC_LEDTS_TF_VALIDATION_t; + +/** + * Defines Enable or disable interrupts. Use type XMC_LEDTS_INTERRUPT_t for this enum. + */ +typedef enum XMC_LEDTS_INTERRUPT +{ + XMC_LEDTS_INTERRUPT_TIMESLICE = LEDTS_GLOBCTL_ITS_EN_Msk, /**< Enable or Disable time slice interrupt */ + XMC_LEDTS_INTERRUPT_TIMEFRAME = LEDTS_GLOBCTL_ITF_EN_Msk, /**< Enable or Disable time frame interrupt */ + XMC_LEDTS_INTERRUPT_TIMEPERIOD = LEDTS_GLOBCTL_ITP_EN_Msk /**< Enable or Disable autoscan time period interrupt */ +} XMC_LEDTS_INTERRUPT_t; + +/** + * Defines Touch-Sense TSIN pad turn. Use type XMC_LEDTS_PAD_TURN_t for this enum. + */ +typedef enum XMC_LEDTS_PAD_TURN +{ + XMC_LEDTS_PAD_TURN_0 = 0, /**< TSIN0 is next or currently active */ + XMC_LEDTS_PAD_TURN_1 = 1, /**< TSIN1 is next or currently active */ + XMC_LEDTS_PAD_TURN_2 = 2, /**< TSIN2 is next or currently active */ + XMC_LEDTS_PAD_TURN_3 = 3, /**< TSIN3 is next or currently active */ + XMC_LEDTS_PAD_TURN_4 = 4, /**< TSIN4 is next or currently active */ + XMC_LEDTS_PAD_TURN_5 = 5, /**< TSIN5 is next or currently active */ + XMC_LEDTS_PAD_TURN_6 = 6, /**< TSIN6 is next or currently active */ + XMC_LEDTS_PAD_TURN_7 = 7 /**< TSIN7 is next or currently active */ +} XMC_LEDTS_PAD_TURN_t; + +/** + * Defines software control for Touch-Sense pad turn. Use type XMC_LEDTS_PAD_TURN_SW_CONTROL_t for this enum. + */ +typedef enum XMC_LEDTS_PAD_TURN_SW_CONTROL +{ + XMC_LEDTS_SW_CONTROL_DISABLE = 0, /**< Disable software control. Auto hardware control */ + XMC_LEDTS_SW_CONTROL_ENABLE = 1 /**< Enable software control for pad turn */ +} XMC_LEDTS_PAD_TURN_SW_CONTROL_t; + +/** + * Defines External pull-up on touch-sense pin. Use type XMC_LEDTS_EXT_PULLUP_COLA_t for this enum. + */ +typedef enum XMC_LEDTS_EXT_PULLUP_COLA +{ + XMC_LEDTS_EXT_PULLUP_COLA_DISABLE = 0, /**< Disable external pull-up. Internal pull-up is active */ + XMC_LEDTS_EXT_PULLUP_COLA_ENABLE = 1 /**< Enable external pull-up */ +} XMC_LEDTS_EXT_PULLUP_COLA_t; + +/** + * Defines number of accumulation counts on Touch-Sense input. Use type XMC_LEDTS_ACCUMULATION_COUNT_t for this enum. + */ +typedef enum XMC_LEDTS_ACCUMULATION_COUNT +{ + XMC_LEDTS_ACCUMULATION_COUNT_1_TIME = 0, /**< Accumulate once */ + XMC_LEDTS_ACCUMULATION_COUNT_2_TIMES = 1, /**< Accumulate twice */ + XMC_LEDTS_ACCUMULATION_COUNT_3_TIMES = 2, /**< Accumulate thrice */ + XMC_LEDTS_ACCUMULATION_COUNT_4_TIMES = 3, /**< Accumulate 4 times */ + XMC_LEDTS_ACCUMULATION_COUNT_5_TIMES = 4, /**< Accumulate 5 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_6_TIMES = 5, /**< Accumulate 6 times */ + XMC_LEDTS_ACCUMULATION_COUNT_7_TIMES = 6, /**< Accumulate 7 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_8_TIMES = 7, /**< Accumulate 8 times */ + XMC_LEDTS_ACCUMULATION_COUNT_9_TIMES = 8, /**< Accumulate 9 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_10_TIMES = 9, /**< Accumulate 10 times */ + XMC_LEDTS_ACCUMULATION_COUNT_11_TIMES = 10, /**< Accumulate 11 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_12_TIMES = 11, /**< Accumulate 12 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_13_TIMES = 12, /**< Accumulate 13 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_14_TIMES = 13, /**< Accumulate 14 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_15_TIMES = 14, /**< Accumulate 15 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_16_TIMES = 15 /**< Accumulate 16 times*/ +} XMC_LEDTS_ACCUMULATION_COUNT_t; + +/** + * Defines enable/disable of common compare configuration for Touch-Sense. Use type XMC_LEDTS_COMMON_COMPARE_t + * for this enum. + */ +typedef enum XMC_LEDTS_COMMON_COMPARE +{ + XMC_LEDTS_COMMON_COMPARE_DISABLE = 0, /**< Disable common compare for touch-sense */ + XMC_LEDTS_COMMON_COMPARE_ENABLE = 1 /**< Enable common compare for touch-sense */ +} XMC_LEDTS_COMMON_COMPARE_t; + +/** + * Defines extended Touch-Sense output for pin-low-level. Use type XMC_LEDTS_EXTEND_TS_OUTPUT_t for this enum. + */ +typedef enum XMC_LEDTS_EXTEND_TS_OUTPUT +{ + XMC_LEDTS_EXTEND_TS_OUTPUT_BY_1_CLK = 0, /**< Extend Touch-Sense output for pin-low-level by 1 ledts_clk */ + XMC_LEDTS_EXTEND_TS_OUTPUT_BY_4_CLK = 1, /**< Extend Touch-Sense output for pin-low-level by 4 ledts_clk */ + XMC_LEDTS_EXTEND_TS_OUTPUT_BY_8_CLK = 2, /**< Extend Touch-Sense output for pin-low-level by 8 ledts_clk */ + XMC_LEDTS_EXTEND_TS_OUTPUT_BY_16_CLK = 3 /**< Extend Touch-Sense output for pin-low-level by 16 ledts_clk */ +} XMC_LEDTS_EXTEND_TS_OUTPUT_t; + +/** + * Defines enable/disable of Touch-Sense counter auto reset configuration. Use type XMC_LEDTS_TS_COUNTER_AUTO_RESET_t + * for this enum. + */ +typedef enum XMC_LEDTS_TS_COUNTER_AUTO_RESET +{ + XMC_LEDTS_TS_COUNTER_AUTO_RESET_DISABLE = 0, /**< Disable Touch-Sense counter automatic reset */ + XMC_LEDTS_TS_COUNTER_AUTO_RESET_ENABLE = 1 /**< Enable Touch-Sense counter automatic reset to 0x00 */ +} XMC_LEDTS_TS_COUNTER_AUTO_RESET_t; + +/** + * Defines enable/disable of Touch-Sense counter saturation configuration. Use type XMC_LEDTS_TS_COUNTER_SATURATION_t + * for this enum. + */ +typedef enum XMC_LEDTS_TS_COUNTER_SATURATION +{ + XMC_LEDTS_TS_COUNTER_SATURATION_DISABLE = 0, /**< Disabled. Touch-Sense counter overflows when it reaches 0xFF */ + XMC_LEDTS_TS_COUNTER_SATURATION_ENABLE = 1 /**< Enabled. Touch-Sense counter stops counting when it reaches 0xFF */ +} XMC_LEDTS_TS_COUNTER_SATURATION_t; + +/** + * Defines number of Touch-Sense Input (for HW pad turn control). Use type XMC_LEDTS_NUMBER_TS_INPUT_t for this enum. + */ +typedef enum XMC_LEDTS_NUMBER_TS_INPUT +{ + XMC_LEDTS_NUMBER_TS_INPUT_1 = 0, /**< Only TSIN0 is used */ + XMC_LEDTS_NUMBER_TS_INPUT_2 = 1, /**< TSIN0 & TSIN1 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_3 = 2, /**< TSIN0-TSIN2 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_4 = 3, /**< TSIN0-TSIN3 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_5 = 4, /**< TSIN0-TSIN4 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_6 = 5, /**< TSIN0-TSIN5 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_7 = 6, /**< TSIN0-TSIN6 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_8 = 7 /**< TSIN0-TSIN7 are used */ +} XMC_LEDTS_NUMBER_TS_INPUT_t; + +/** + * Defines level of LED column when active. Use type XMC_LEDTS_ACTIVE_LEVEL_LED_COL_t for this enum. + */ +typedef enum XMC_LEDTS_ACTIVE_LEVEL_LED_COL +{ + XMC_LEDTS_ACTIVE_LEVEL_LED_COL_LOW = 0, /**< LED column pins output low when active */ + XMC_LEDTS_ACTIVE_LEVEL_LED_COL_HIGH = 1 /**< LED column pins output high when active */ +} XMC_LEDTS_ACTIVE_LEVEL_LED_COL_t; + +/** + * Defines Number of LED columns. Use type XMC_LEDTS_NUMBER_LED_COLUMNS_t for this enum. + */ +typedef enum XMC_LEDTS_NUMBER_LED_COLUMNS +{ + XMC_LEDTS_NUMBER_LED_COLUMNS_1 = 0, /**< COLA only if TS is enabled, else COL0 only */ + XMC_LEDTS_NUMBER_LED_COLUMNS_2 = 1, /**< COLA,COL0 if TS is enabled, else COL0-1 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_3 = 2, /**< COLA,COL0-1 if TS is enabled, else COL0-2 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_4 = 3, /**< COLA,COL0-2 if TS is enabled, else COL0-3 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_5 = 4, /**< COLA,COL0-3 if TS is enabled, else COL0-4 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_6 = 5, /**< COLA,COL0-4 if TS is enabled, else COL0-5 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_7 = 6, /**< COLA,COL0-5 if TS is enabled, else COL0-6 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_8 = 7 /**< Only possible if TS is disabled; COLA,COL0-6 used */ +} XMC_LEDTS_NUMBER_LED_COLUMNS_t; + +/** + * Defines Interrupt flag status. Use type XMC_LEDTS_TS_INTERRUPT_FLAG_t for this enum. + */ +typedef enum XMC_LEDTS_INTERRUPT_FLAG +{ + XMC_LEDTS_INTERRUPT_FLAG_TIMESLICE = LEDTS_EVFR_TSF_Msk, /**< Time slice interrupt flag status */ + XMC_LEDTS_INTERRUPT_FLAG_TIMEFRAME = LEDTS_EVFR_TFF_Msk, /**< Time frame interrupt flag status */ + XMC_LEDTS_INTERRUPT_FLAG_TIMEPERIOD = LEDTS_EVFR_TPF_Msk, /**< Time period interrupt flag status */ + XMC_LEDTS_INTERRUPT_FLAG_TSCOUNTER_OVERFLOW = LEDTS_EVFR_TSCTROVF_Msk, /**< TS counter overflow flag status */ +} XMC_LEDTS_TS_INTERRUPT_FLAG_t; + +/** + * Defines (Extended) Time frame interrupt flag status. Use type XMC_LEDTS_TF_INTERRUPT_FLAG_t for this enum. + */ +typedef enum XMC_LEDTS_TF_INTERRUPT_FLAG +{ + XMC_LEDTS_TF_INTERRUPT_FLAG_INACTIVE = 0, /**< (Extended) Time frame interrupt not active */ + XMC_LEDTS_TF_INTERRUPT_FLAG_ACTIVE = 1 /**< (Extended) Time frame interrupt active */ +} XMC_LEDTS_TF_INTERRUPT_FLAG_t; + +/** + * Defines Autoscan time period interrupt flag status. Use type XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_t for this enum. + */ +typedef enum XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG +{ + XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_INACTIVE = 0, /**< Autoscan time period interrupt not active */ + XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_ACTIVE = 1 /**< Autoscan time period interrupt active */ +} XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_t; + +/** + * Defines Touch-Sense counter overflow indication. Use type XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_t for this enum. + */ +typedef enum XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG +{ + XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_NO = 0, /**< Touch-sense counter has not overflowed */ + XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_YES = 1 /**< Touch-sense counter has overflowed at least once */ +} XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_t; + +/** + * Defines available LED columns. Use type XMC_LEDTS_LED_COLUMN_t for this enum. + */ +typedef enum XMC_LEDTS_LED_COLUMN +{ + XMC_LEDTS_LED_COLUMN_0 = 0, /**< Denotes LED Column 0 */ + XMC_LEDTS_LED_COLUMN_1 = 1, /**< Denotes LED Column 1 */ + XMC_LEDTS_LED_COLUMN_2 = 2, /**< Denotes LED Column 2 */ + XMC_LEDTS_LED_COLUMN_3 = 3, /**< Denotes LED Column 3 */ + XMC_LEDTS_LED_COLUMN_4 = 4, /**< Denotes LED Column 4 */ + XMC_LEDTS_LED_COLUMN_5 = 5, /**< Denotes LED Column 5 */ + XMC_LEDTS_LED_COLUMN_6 = 6, /**< Denotes LED Column 6 */ + XMC_LEDTS_LED_COLUMN_A = 7 /**< Denotes LED Column A */ +} XMC_LEDTS_LED_COLUMN_t; + +/** + * Defines available Touch-Sense inputs. Use type XMC_LEDTS_TS_INPUT_t for this enum. + */ +typedef enum XMC_LEDTS_TS_INPUT +{ + XMC_LEDTS_TS_INPUT_0 = 0, /**< TSIN0 - Denotes touch-sense line 1 */ + XMC_LEDTS_TS_INPUT_1 = 1, /**< TSIN1 - Denotes touch-sense line 2 */ + XMC_LEDTS_TS_INPUT_2 = 2, /**< TSIN2 - Denotes touch-sense line 3*/ + XMC_LEDTS_TS_INPUT_3 = 3, /**< TSIN3 - Denotes touch-sense line 4*/ + XMC_LEDTS_TS_INPUT_4 = 4, /**< TSIN4 - Denotes touch-sense line 5*/ + XMC_LEDTS_TS_INPUT_5 = 5, /**< TSIN5 - Denotes touch-sense line 6*/ + XMC_LEDTS_TS_INPUT_6 = 6, /**< TSIN6 - Denotes touch-sense line 7*/ + XMC_LEDTS_TS_INPUT_7 = 7 /**< TSIN7 - Denotes touch-sense line 8*/ +} XMC_LEDTS_TS_INPUT_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + /*Anonymous structure/union guard start*/ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Data structure for initialization of global features common to LED and touch-sense function. Use + * type XMC_LEDTS_GLOBAL_CONFIG_t for this structure. + */ +typedef struct XMC_LEDTS_GLOBAL_CONFIG +{ + union + { + struct + { + uint32_t : 2; + uint32_t clock_generation:1; /**< When this bit is set LEDTS counter takes its clock from another master + kernel. Kernel generates its own clock when this bit is not set (CMTR). + Refer @ref XMC_LEDTS_CLOCK_TYPE_t enum for possible values. */ + + uint32_t autoscan_synchronization:1; /**< Set this bit to synchronize start of autoscan time period with master + kernel(ENSYNC). Refer @ref XMC_LEDTS_TP_SYNC_t enum for possible values. */ + uint32_t : 4; + uint32_t suspend_response:1; /**< Suspend request configuration(SUSCFG). + Refer @ref XMC_LEDTS_SUSPEND_t enum for possible values.*/ + }; + uint32_t globctl; + }; +}XMC_LEDTS_GLOBAL_CONFIG_t; + +/** + * Data structure for LED function initialization. Use type XMC_LEDTS_LED_CONFIG_t for this structure. + */ +typedef struct XMC_LEDTS_LED_CONFIG +{ + union + { + struct + { + uint32_t : 28; + uint32_t column_active_level:1; /**< When this bit is set LED column level is active high, otherwise column + level is active low(COLLEV). Refer @ref XMC_LEDTS_ACTIVE_LEVEL_LED_COL_t + enum for possible values.*/ + + uint32_t no_of_led_columns:3; /**< Defines number of LED columns(NR_LEDCOL). Range 0 - 7. + Refer @ref XMC_LEDTS_NUMBER_LED_COLUMNS_t enum for possible values. */ + }; + uint32_t fnctl; + }; +}XMC_LEDTS_LED_CONFIG_t; + +/** + * Data structure for basic Touch-Sense function initialization. Use type XMC_LEDTS_TS_CONFIG_BASIC_t for + * this structure. + */ +typedef struct XMC_LEDTS_TS_CONFIG_BASIC +{ + union + { + struct + { + uint32_t : 16; + uint32_t no_of_accumulation:4; /**< Defines number of times touch-sense input pin is enabled in touch-sense + time slice of consecutive frames(ACCCNT). Range 0 - 15. + Refer @ref XMC_LEDTS_ACCUMULATION_COUNT_t enum type for possible values. */ + + uint32_t common_compare:1; /**< When this bit is set it enables common compare for all touch sense inputs. + Disables common compare when not set(TSCCMP). + Refer @ref XMC_LEDTS_COMMON_COMPARE_t enum for possible values.*/ + uint32_t : 2; + uint32_t counter_auto_reset:1; /**< When this bit is set TS-counter is automatically reset to 00H on first pad + turn of a new touch-sense pin(TSCTRR). + Refer @ref XMC_LEDTS_TS_COUNTER_AUTO_RESET_t enum for possible values.*/ + + uint32_t counter_saturation:1; /**< When this bit is set TS-counter stops counting in the touch-sense time slice + of the same frame when it reaches FFH (TSCTRSAT). + Refer @ref XMC_LEDTS_TS_COUNTER_SATURATION_t enum for possible values. */ + + uint32_t no_of_touch_inputs:3; /**< Defines number of touch-sense inputs (NR_TSIN). Range 0 - 7. + Refer @ref XMC_LEDTS_NUMBER_TS_INPUT_t enum for possible values. */ + }; + uint32_t fnctl; + }; +}XMC_LEDTS_TS_CONFIG_BASIC_t; + +/** + * Data structure for advanced Touch-Sense function initialization. Use type XMC_LEDTS_TS_CONFIG_ADVANCED_t + * for this structure. + */ +typedef struct XMC_LEDTS_TS_CONFIG_ADVANCED +{ + union + { + struct + { + uint32_t : 9; + uint32_t validation_mask:3; /**< This bit-field defines number of LSB bits to mask for TS counter and shadow + TS counter comparison when Time Frame validation is enabled(MASKVAL). + Refer @ref XMC_LEDTS_TS_COUNTER_MASK_t enum for possible values.*/ + + uint32_t time_frame_validation:1; /**< Disable or enable (extended) time frame validation(FENVAL). + when validation fails time frame interrupt is not triggered. + Refer @ref XMC_LEDTS_TF_VALIDATION_t enum for possible values.*/ + uint32_t : 1; + uint32_t : 1; + }; + uint32_t globctl; + }; + union + { + struct + { + uint32_t first_pad_turn:3; /**< This bit-field denotes TSIN[x] pin on which oscillations are measured + currently/next(PADT). Refer @ref XMC_LEDTS_PAD_TURN_t enum for possible + values.*/ + + uint32_t pad_turn_control:1; /**< Control pad turn via HW or SW(PADTSW). + Refer @ref XMC_LEDTS_PAD_TURN_SW_CONTROL_t enum for possible values. */ + + uint32_t external_pullup:1; /**< Disable or enable external pull-up on touch pin(EPULL). + Refer @ref XMC_LEDTS_EXT_PULLUP_COLA_t enum for possible values. */ + uint32_t : 16; + uint32_t pin_low_extend:2; /**< This bit extends touch-sense output for pin-low-level configuration for + adjustment of oscillation per user system. + Refer @ref XMC_LEDTS_EXTEND_TS_OUTPUT_t enum for possible values. */ + }; + uint32_t fnctl; + }; +}XMC_LEDTS_TS_CONFIG_ADVANCED_t; + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +#ifdef __cplusplus +extern "C" { +#endif +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param config Pointer to constant LEDTS Global configuration structure. Refer @ref XMC_LEDTS_GLOBAL_CONFIG_t + * data structure.
+ * + * @return + * XMC_LEDTS_STATUS_SUCCESS - on success.
+ * XMC_LEDTS_STATUS_RUNNING - LEDTS module currently active. Refer @ref XMC_LEDTS_STATUS_t enum type.
+ * + * \parDescription
+ * Initializes and configures GLOBCTL register of \a ledts with configuration data pointed by \a config. + * \par + * This API selects clock source (GLOBCTL.CMTR), enables/disables auto scan sync(GLOBCTL.ENSYNC) & + * suspend config(GLOBCTL.SUSCFG).
+ * Call this API to initialize global register fields common to both LED and touch-sense(TS).\n + * + * \parNote
+ * LEDTS should be stopped by using XMC_LEDTS_StopCounter()before calling this API.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter()\n + * + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitGlobal(XMC_LEDTS_t *const ledts, const XMC_LEDTS_GLOBAL_CONFIG_t *config); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param config Pointer to constant LEDTS LED configuration structure. Refer @ref XMC_LEDTS_LED_CONFIG_t + * data structure.
+ * + * @return + * XMC_LEDTS_STATUS_SUCCESS - on success.
+ * XMC_LEDTS_STATUS_RUNNING - LEDTS module currently active/running. Refer @ref XMC_LEDTS_STATUS_t enum type.
+ * + * \parDescription
+ * Configures FNCTL register of \a ledts with configuration data pointed by \a config and enables LED functionality. + * \par + * This API sets number of LED columns(FNCTL.NR_LEDCOL), column level(FNCTL.COLLEV) and enables LED + * functionality(GLOBCTL.LD_EN). + * \par + * Call this API to Configure \a FNCTL & \a GLOBCTL registers for LED-driving function. Global initialization of + * LEDTS module should be done by calling XMC_LEDTS_InitGlobal() prior to calling this API.\n + * + * \parNote
+ * LEDTS should be stopped by using XMC_LEDTS_StopCounter() before calling this API.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter() XMC_LEDTS_InitGlobal()\n + * + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitLED(XMC_LEDTS_t *const ledts, const XMC_LEDTS_LED_CONFIG_t *config); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param config Pointer to constant LEDTS TS basic configuration structure. Refer @ref XMC_LEDTS_TS_CONFIG_BASIC_t + * data structure.
+ * + * @return + * XMC_LEDTS_STATUS_SUCCESS - on success.
+ * XMC_LEDTS_STATUS_RUNNING - LEDTS module currently active/running. Refer @ref XMC_LEDTS_STATUS_t enum type.
+ * + * \parDescription
+ * Configures FNCTL register of \a ledts for basic touch sense functionality with configuration data pointed by \a config + * and enables TS functionality. + * \par + * This API sets number of touch inputs(FNCTL.NR_TSIN), accumulate count on touch input(FNCTL.ACCCNT). + * \par + * This API Enables/disables common compare(FNCTL.TSCCMP), TS counter auto reset(FNCTL.TSCTRR), counter + * saturation(FNCTL.TSCTRSAT) and enables TS functionality(GLOBCTL.TS_EN). + * \par + * Call this API to configure \a FNCTL & \a GLOBCTL registers for basic touch sense function. Global initialization + * of LEDTS module should be done by calling XMC_LEDTS_InitGlobal() prior to calling this API.\n + * + * \parNote
+ * LEDTS should be stopped by using XMC_LEDTS_StopCounter() before calling this API.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter() XMC_LEDTS_InitGlobal()\n + * + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSBasic(XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_BASIC_t *config); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param config Pointer to constant LEDTS TS advanced configuration structure. + * Refer @ref XMC_LEDTS_TS_CONFIG_ADVANCED_t data structure.
+ * + * @return + * XMC_LEDTS_STATUS_SUCCESS - on success.
+ * XMC_LEDTS_STATUS_RUNNING - LEDTS module currently active/running. Refer @ref XMC_LEDTS_STATUS_t enum type.
+ * + * \parDescription
+ * Configures FNCTL register of \a ledts for advanced touch sense functionality with configuration data pointed by + * \a config. + * \par + * This API sets number of mask-bits for time frame validation(GLOBCTL.MASKVAL) & first touch input to be active(if + * pad turn control is set to S/W)(FNCTL.PADT). + * \par + * Enables/disables time frame interrupt(GLOBCTL.ITF_EN), external pull up on touch pin(FNCTL.EPULL) & H/W or S/W + * control of pad turn(if set to H/W, touch input activation is done in round-robin sequence, starting from TSIN0) + * (FNCTL.PADTSW). + * \par + * Call this API to initialize registers for advanced touch sense function. Before calling this API Call + * XMC_LEDTS_InitGlobal() to do Global initialization and XMC_LEDTS_InitTSBasic() to do basic init of touch-sense.\n + * + * \parNote
+ * LEDTS should be stopped by using XMC_LEDTS_StopCounter() before calling this API.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter(), XMC_LEDTS_InitTSBasic().\n + * + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSAdvanced (XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_ADVANCED_t *config); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param prescaler Constant prescaler value. Range: 0H to FFFFH.
+ * + * @return + * None.
+ * + * \parDescription
+ * Kick-starts the LEDTS module by programming CLK_PS bit field of GLOBCTL register with \a prescaler value to start + * the LEDTS-counter. + * \par + * To set LEDTS counter at least one of the touch-sense or LED function should be enabled. + * Call this API to start LEDTS counter.\n + * + * \parNote
+ * This should be called after all used modules have been initialized.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter(), XMC_LEDTS_InitLED(), XMC_LEDTS_InitTSBasic(), XMC_LEDTS_InitTSAdvanced().\n + * + */ +void XMC_LEDTS_StartCounter(XMC_LEDTS_t *const ledts, const uint16_t prescaler); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * + * @return + * None.
+ * + * \parDescription
+ * Stops the LEDTS module by programming the CLK_PS bit field(with value = 0) of GLOBCTL register.
+ * This could be done when it is required to change some module configuration which requires the LEDTS-counter + * to be stopped before the register bit/bit field can be programmed.
Call this API to stop LEDTS counter.\n + * + * \parRelated API's
+ * XMC_LEDTS_StartCounter(), XMC_LEDTS_InitLED(), XMC_LEDTS_InitTSBasic(), XMC_LEDTS_InitTSAdvanced().\n + * + */ +void XMC_LEDTS_StopCounter(XMC_LEDTS_t *const ledts); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param interrupt_mask mask value of @ref XMC_LEDTS_INTERRUPT_t enum type.
+ * + * @return + * None.
+ * + * \parDescription
+ * Enables requested interrupt type by configuring GLOBCTL register with masked value \a interrupt_mask.
+ * \par + * This API can be used to enable time slice(GLOBCTL.ITS_EN) or time frame(GLOBCTL.ITF_EN )or time period + * (GLOBCTL.ITP_EN)interrupt or any combination of these interrupts by passing appropriate bitwise ORed mask value.\n + * + * \parRelated API's
+ * XMC_LEDTS_DisableInterrupt().\n + * + */ +__STATIC_INLINE void XMC_LEDTS_EnableInterrupt(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask) +{ + XMC_ASSERT("XMC_LEDTS_EnableInterrupt:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->GLOBCTL |= interrupt_mask; +} + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param interrupt_mask mask value of @ref XMC_LEDTS_INTERRUPT_t enum type.
+ * + * @return + * None.
+ * + * \parDescription
+ * Disables requested interrupt type by configuring GLOBCTL register with masked value \a interrupt_mask.
+ * \par + * This API can be used to disable time slice(GLOBCTL.ITS_EN) or time frame(GLOBCTL.ITF_EN )or time period + * (GLOBCTL.ITP_EN)interrupt or any combination of these interrupts by passing appropriate bitwise ORed mask value.\n + * + * \parRelated API's
+ * XMC_LEDTS_EnableInterrupt().\n + * + */ +__STATIC_INLINE void XMC_LEDTS_DisableInterrupt(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask) +{ + XMC_ASSERT("XMC_LEDTS_DisableInterrupt:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->GLOBCTL &= ~interrupt_mask; +} + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * + * @return + * Status flags for events. Possible event flags are 0x01(time slice), 0x02(time frame), + 0x04(time period), 0x08(TS counter overflow).
+ * + * \parDescription
+ * Returns interrupt status flag by reading TSF(time slice), TFF(time frame), TPF(time period), TSCTROVF + * (touch sense counter overflow) fields of EVFR register.
+ * Typically used in interrupt handler to find out which event has triggered the interrupt.\n + * + * \parNote
+ * These flags are set on event regardless of corresponding interrupt is enabled or not.\n + * + * \parRelated API's
+ * XMC_LEDTS_ClearInterruptFlag().\n + * + */ +uint32_t XMC_LEDTS_ReadInterruptFlag(XMC_LEDTS_t *const ledts); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param interrupt_mask mask value of @ref XMC_LEDTS_INTERRUPT_t enum type.
+ * + * @return + * None.
+ * + * \parDescription
+ * Clears interrupt status flags in EVFR register as indicated by mask value \a interrupt_mask.
+ * This API sets EVFR.CTSF, EVFR.CTFF, EVFR.CTPF bit fields to clear time slice, time frame or time period interrupts + * respectively. + * \par + * Typically used along with XMC_LEDTS_ReadInterruptFlag() to figure out which event triggered the interrupt.\n + * + * \parNote
+ * Calling this API moves interrupt from pending/active state to inactive state. If the interrupt is pulsed, + * failing to clear the event bit might cause CPU to immediately re-enter the interrupt service routine(ISR).\n + * + * \parRelated API's
+ * XMC_LEDTS_ReadInterruptFlag().\n + * + */ +void XMC_LEDTS_ClearInterruptFlag(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param pad_num Pad number. Range refer @ref XMC_LEDTS_NUMBER_TS_INPUT_t enum type.
+ * + * @return + * None.
+ * + * \parDescription
+ * Sets TSIN[x] (where x corresponds to \a active pad number to be set) field of TSIN[x](x = 0-7) .
+ * This is the TSIN[x] pin that is next or currently active in pad turn.
+ * Call this API to set the active pad turn. + * \par + * Touch sense functionality should be initialized and configured before calling this API.\n + * + */ +void XMC_LEDTS_SetActivePADNo(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t pad_num); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param column Column number. Range refer @ref XMC_LEDTS_LED_COLUMN_t enum type.
+ * @param pattern Pattern to be displayed. Range: 0H to FFH.
+ * + * @return + * None.
+ * + * \parDescription
+ * Sets LINE_x (where x corresponds to \a column number) field of LINEx(x = 0-1) register to \a pattern value.
+ * This value is output on LINE_x when LED \a column x is active.
Call this API to set desired LED pattern. + * \par + * LED functionality should be initialized and configured before calling this API.\n + * + */ +void XMC_LEDTS_SetLEDLinePattern(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t pattern); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param column Column number. Range refer @ref XMC_LEDTS_LED_COLUMN_t enum type.
+ * @param brightness LED brightness level. Range: 0H(min brightness) to FFH(max brightness).
+ * + * @return + * None.
+ * + * \parDescription
+ * Programs CMP_LDx (where x denotes \a column number) field of LDCMPx(x = 0-1)register to the requested \a brightness + * level. + * \par + * The LDCMPx registers hold the COMPARE values for their respective LED columns. These values are used for LED + * brightness control. Call this API to control brightness level of the LED. + * \par + * LED functionality should be initialized and configured before calling this API.\n + * + */ +void XMC_LEDTS_SetColumnBrightness(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t brightness); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param common_size Requested common oscillation window width. Range: FFH(min) to 00H.(max)
+ * + * @return + * None.
+ * + * \parDescription
+ * Programs the respective LDCMP1 register bit field CMP_LDA_TSCOM with \a common_size. + * \par + * Call this API to adjust the size of the common oscillation window to increase/decrease the number of recorded + * number of oscillation counts for all touch-sense inputs.\n + * + */ +void XMC_LEDTS_SetCommonOscillationWindow(XMC_LEDTS_t *const ledts, const uint8_t common_size); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * + * @return + * uint32_t Previous active LED column number. Range: 0 to 7.
+ * + * \parDescription
+ * Returns active LED column number in previous time-slice by reading FNCOL bit field of FNCTL register. + * Call this API to figure out active column during previous time slice.\n + * + */ +uint32_t XMC_LEDTS_ReadFNCOL(XMC_LEDTS_t *const ledts); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure
+ * @param count Number of LED columns to be enabled. Range: 0 to 7.
+ * + * @return + * None.
+ * + * \parDescription
+ * Sets \a count number of LED columns active by programming NR_LEDCOL bit field of FNCTL register.
+ * \par + * Call this API to set desired number of LED columns active.\n + * + * \parNote
+ * NR_LEDCOL bit field can only be modified when LEDTS counter is not running, use XMC_LEDTS_StopCounter() + * to stop LEDTS module before calling this API.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter().\n + */ +void XMC_LEDTS_SetNumOfLEDColumns(XMC_LEDTS_t *const ledts, uint8_t count); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * + * @return + * uint16_t Shadow touch sense counter value. Range: 0H to FFFFH.
+ * + * \parDescription
+ * Returns latched touch sense counter value by reading the TSCTRVALR field of TSVAL register.
+ * \par + * This API is typically called in time frame(TF) event handler to get oscillation count of the touch-sense input + * active in previous time frame.\n + * + * \parNote
+ * This is the latched value of the TS-counter(on every extended time frame event).\n + * + * \parRelated API's
+ * XMC_LEDTS_ReadInterruptFlag().\n + */ +uint16_t XMC_LEDTS_ReadTSVAL(XMC_LEDTS_t *const ledts); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param touchpad Touch-sense input pad number. Range refer @ref XMC_LEDTS_NUMBER_TS_INPUT_t enum type.
+ * @param size Requested oscillation window width. Range: 0H(max) to FFH(min).
+ * + * @return + * None.
+ * + * \parDescription
+ * Sets the size of \a touchpad touch sense oscillation window to \a size. + * \par + * This API programs the respective CMP_TSx(where x is \a touchpad number) bit fields of TSCMPx(x = 0-1) register. + * \a size value determines the size of the pad oscillation window for each pad input lines during their pad turn. + * \par + * Call this API to increase/decrease recorded number of oscillation counts for the requested touch-sense input.\n + * + */ +void XMC_LEDTS_SetOscillationWindow(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t touchpad, const uint8_t size); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LEDTS0 */ + +#endif /* XMC_LEDTS_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_posif.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_posif.h new file mode 100644 index 00000000..2cbab878 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_posif.h @@ -0,0 +1,1046 @@ +/** + * @file xmc_posif.h + * @date 2016-03-09 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Initial version + * + * 2015-02-20: + * - Driver description added
+ * + * 2015-06-19: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-07-02: + * - Updated XMC_POSIF_QD_GetDirection API + * + * 2016-03-09: + * - Optimization of write only registers + * + * @endcond + * + */ + + +#ifndef XMC_POSIF_H +#define XMC_POSIF_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +#if defined(POSIF0) +#include + +/** + * @addtogroup XMClib + * @{ + */ + +/** + * @addtogroup POSIF + * @{ + * @brief Position Interface Unit (POSIF) driver for the XMC microcontroller family
+ * + * The POSIF unit is a flexible and powerful component for motor control systems that use + * rotary encoders or hall sensors as feedback loop. It provides interface for motor position and velocity measurement. + * POSIF unit works with CCU4 and CCU8 to enable position and velocity measurement and to control PWM outputs using multi channel pattern.
+ * + * Driver is divided in three POSIF functional blocks - Hall Sensor Control (POSIF_HSC), Quadrature Decoder (POSIF_QD) and + * MultiChannel Mode (POSIF_MCM).
+ * + * POSIF driver features: + * -# Configuration structure XMC_POSIF_CONFIG_t and initialization function XMC_POSIF_Init() to configure global settings + * -# Allows to change the operating mode using XMC_POSIF_SetMode() + * -# Allows the selection of one of the four inputs (A, B, C or D) using XMC_POSIF_SelectInputSource(). In hall sensor control, inputs are + * hall0, hall1 and hall2 signals. For quadrature decoder mode, inputs are phase A, phase B and index signals. + * -# Hall Sensor Control (APIs prefixed with XMC_POSIF_HSC_)
+ * - Configuration structure XMC_POSIF_HSC_CONFIG_t and initialization function XMC_POSIF_HSC_Init() + * - Update current and expected hall pattern in shadow register using XMC_POSIF_HSC_SetHallPatterns() + * - Allows immediate shadow transfer using XMC_POSIF_HSC_UpdateHallPattern() + * -# Quadrature Decoder (APIs prefixed with XMC_POSIF_QD_)
+ * - Configuration structure XMC_POSIF_QD_CONFIG_t and initialization function XMC_POSIF_QD_Init() + * - Get direction of rotation using XMC_POSIF_QD_GetDirection() + * -# MultiChannel Mode (APIs prefixed with XMC_POSIF_MCM_)
+ * - Configuration structure XMC_POSIF_MCM_CONFIG_t and initialization function XMC_POSIF_MCM_Init() + * - Update multichannel pattern in shadow register using XMC_POSIF_MCM_SetMultiChannelPattern() + * - Allows immediate shadow transfer using XMC_POSIF_MCM_UpdateMultiChannelPattern() + * -# User need to call respective init functions to configure POSIF operating mode. e.g to configure POSIF in hall sensor control with multichannel mode + * call both XMC_POSIF_HSC_Init() and XMC_POSIF_MCM_Init(). + * -# Allows to enable and disable interrupt sources and assign to service request node using XMC_POSIF_EnableEvent(), XMC_POSIF_DisableEvent() and XMC_POSIF_SetInterruptNode() + + */ +/* POSIF is not available on XMC11 and XMC12 devices */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_POSIF_PCONF_INSEL_Msk (0x3fUL << POSIF_PCONF_INSEL0_Pos) /*< Mask for input pins selection */ +#define XMC_POSIF_INSEL_MAX (4U) /*< Maximum possible input selector */ +#define XMC_POSIF_HALPS_HALLPAT_Msk (0x3FUL) + +#if ((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || (UC_SERIES == XMC14)) +#define XMC_POSIF_CHECK_MODULE_PTR(PTR) ( ((PTR)== POSIF0) || ((PTR)== POSIF1) ) /*< Check for valid module pointer */ +#else +#define XMC_POSIF_CHECK_MODULE_PTR(PTR) ( ((PTR)== POSIF0)) /*< Check for valid module pointer */ +#endif + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +/** + * Defines the return status, to verify the POSIF related API calls. Use type @ref XMC_POSIF_STATUS_t for this enum. + */ +typedef enum XMC_POSIF_STATUS +{ + XMC_POSIF_STATUS_OK = 0U, /**< API fulfills request */ + XMC_POSIF_STATUS_ERROR /**< API cannot fulfill request */ +} XMC_POSIF_STATUS_t; + +/** + * Defines POSIF configurable modes.Use type @ref XMC_POSIF_MODE_t for this enum. + * The members defines the function selector(FSEL) bitfields of \a PCONF register. + */ +typedef enum XMC_POSIF_MODE +{ + XMC_POSIF_MODE_HALL_SENSOR = 0U, /**< Hall sensor mode */ + XMC_POSIF_MODE_QD , /**< Quadrature Decoder mode */ + XMC_POSIF_MODE_MCM , /**< Standalone Multichannel mode */ + XMC_POSIF_MODE_MCM_QD /**< Quadrature Decoder + Standalone Multichannel mode */ +} XMC_POSIF_MODE_t; + +/** + * Defines POSIF configurable input ports.Use type @ref XMC_POSIF_INPUT_PORT_t for this enum. + * The member defines the respective input selector(INSELX) bitfields of \a PCONF register. + * It selects, which input is used for the phase or Hall input function (depending on the module is set for + * Quadrature Decoder or Hall Sensor Mode). Same enum can be used to configure pattern update signal select by configuring + * \a PCONF register's \a MSETS bit field. + */ +typedef enum XMC_POSIF_INPUT_PORT +{ + XMC_POSIF_INPUT_PORT_A = 0U, /**< INPUT-A */ + XMC_POSIF_INPUT_PORT_B , /**< INPUT-B */ + XMC_POSIF_INPUT_PORT_C , /**< INPUT-C */ + XMC_POSIF_INPUT_PORT_D , /**< INPUT-D */ + XMC_POSIF_INPUT_PORT_E , /**< INPUT-E */ + XMC_POSIF_INPUT_PORT_F , /**< INPUT-F */ + XMC_POSIF_INPUT_PORT_G , /**< INPUT-G */ + XMC_POSIF_INPUT_PORT_H /**< INPUT-H */ +} XMC_POSIF_INPUT_PORT_t; + +/** + * Defines active level of an input signal.Use type @ref XMC_POSIF_INPUT_ACTIVE_LEVEL_t for this enum. + */ +typedef enum XMC_POSIF_INPUT_ACTIVE_LEVEL +{ + XMC_POSIF_INPUT_ACTIVE_LEVEL_HIGH = 0U, /**< Input - Active High */ + XMC_POSIF_INPUT_ACTIVE_LEVEL_LOW /**< Input - Active Low */ +} XMC_POSIF_INPUT_ACTIVE_LEVEL_t; + +/** + * Defines POSIF input debounce filter configuration.POSIF inputs are connected to low pass filter and + * this enum is used to configure low pass filters cut off frequency. + * Use type @ref XMC_POSIF_FILTER_t for this enum. + * The member defines the low pass filter configuration(LPC) bitfield of \a PCONF register. + */ +typedef enum XMC_POSIF_FILTER +{ + XMC_POSIF_FILTER_DISABLED = 0U, /**< No filtering */ + XMC_POSIF_FILTER_1_CLOCK_CYCLE , /**< Filter of 1 Clock Cycle */ + XMC_POSIF_FILTER_2_CLOCK_CYCLE , /**< Filter of 2 Clock Cycles */ + XMC_POSIF_FILTER_4_CLOCK_CYCLE , /**< Filter of 4 Clock Cycles */ + XMC_POSIF_FILTER_8_CLOCK_CYCLE , /**< Filter of 8 Clock Cycles */ + XMC_POSIF_FILTER_16_CLOCK_CYCLE , /**< Filter of 16 Clock Cycles */ + XMC_POSIF_FILTER_32_CLOCK_CYCLE , /**< Filter of 32 Clock Cycles */ + XMC_POSIF_FILTER_64_CLOCK_CYCLE /**< Filter of 64 Clock Cycles */ +} XMC_POSIF_FILTER_t; + +/** + * Defines POSIF events.Use type @ref XMC_POSIF_IRQ_EVENT_t for this enum. + * The member defines available event sources.It is used to configure which event to be used for + * interrupt generation using \a PFLGE register. [ PFLG,SPFLG,RPFLG] + */ +typedef enum XMC_POSIF_IRQ_EVENT +{ + XMC_POSIF_IRQ_EVENT_CHE = 0U, /**< Hall Mode : Correct Hall Event */ + XMC_POSIF_IRQ_EVENT_WHE = 1U, /**< Hall Mode : Wrong Hall Event */ + XMC_POSIF_IRQ_EVENT_HALL_INPUT = 2U, /**< Hall Mode : Hall Input update */ + XMC_POSIF_IRQ_EVENT_MCP_SHADOW_TRANSFER = 4U, /**< Hall Mode + MCM Mode : MC Pattern shadow transfer */ + XMC_POSIF_IRQ_EVENT_INDX = 8U, /**< Quadrature Mode : Index event detection */ + XMC_POSIF_IRQ_EVENT_ERR = 9U, /**< Quadrature Mode : Quadrature Phase Error */ + XMC_POSIF_IRQ_EVENT_CNT = 10U, /**< Quadrature Mode : Quadrature Clock event */ + XMC_POSIF_IRQ_EVENT_DIR = 11U, /**< Quadrature Mode : Quadrature Direction change event */ + XMC_POSIF_IRQ_EVENT_PCLK = 12U /**< Quadrature Mode : Quadrature period clock generation event */ +} XMC_POSIF_IRQ_EVENT_t; + +/** + * Defines POSIF service request lines.Use type @ref XMC_POSIF_SR_ID_t for this enum. + * It used to connect POSIF event to required service request line. + * in \a PFLGE register for interrupt generation. + */ +typedef enum XMC_POSIF_SR_ID +{ + XMC_POSIF_SR_ID_0 = 0U, /**< SR-0 */ + XMC_POSIF_SR_ID_1 /**< SR-1 */ +} XMC_POSIF_SR_ID_t; + +/** + * Defines position decoder mode selection.Use type @ref XMC_POSIF_QD_MODE_t for this enum. + * The member defines configuration for the operation of the quadrature decoder mode. + * It used to configure \a QDC register. + */ +typedef enum XMC_POSIF_QD_MODE +{ + XMC_POSIF_QD_MODE_QUADRATURE = 0U, /**< Standard Quadrature Mode */ + XMC_POSIF_QD_MODE_DIRECTION_COUNT /**< Direction Count Mode */ +} XMC_POSIF_QD_MODE_t; + +/** + * Defines motor rotation direction.Use type @ref XMC_POSIF_QD_DIR_t for this enum. + * The member defines the direction in quadrature mode. + */ +typedef enum XMC_POSIF_QD_DIR +{ + XMC_POSIF_QD_DIR_COUNTERCLOCKWISE = 0U, /**< Counter Clockwise */ + XMC_POSIF_QD_DIR_CLOCKWISE /**< Clockwise */ +} XMC_POSIF_QD_DIR_t; + +/** + * Defines frequency of index signal generation.Use type @ref XMC_POSIF_QD_INDEX_GENERATION_t for this enum. + * Member represents available configuration for index marker generation using \a ICM bit field in \a QDC register. + */ +typedef enum XMC_POSIF_QD_INDEX_GENERATION +{ + XMC_POSIF_QD_INDEX_GENERATION_NEVER = 0U, /**< Never generate the index marker signal */ + XMC_POSIF_QD_INDEX_GENERATION_ONCE , /**< Generate only once after the first revolution */ + XMC_POSIF_QD_INDEX_GENERATION_ALWAYS /**< Index marker generated upon every revolution */ +} XMC_POSIF_QD_INDEX_GENERATION_t; + +/** + * Defines trigger edge in hall sensor mode.Use type @ref XMC_POSIF_HSC_TRIGGER_EDGE_t for this enum. + * It can be used to configure \a PCONF register's \a SPES and \a MSES bit fields. + */ +typedef enum XMC_POSIF_HSC_TRIGGER_EDGE +{ + XMC_POSIF_HSC_TRIGGER_EDGE_RISING = 0U, /**< Rising edge */ + XMC_POSIF_HSC_TRIGGER_EDGE_FALLING /**< Falling edge */ +} XMC_POSIF_HSC_TRIGGER_EDGE_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * + * Defines POSIF peripheral register structure.Use type @ref XMC_POSIF_t for this data structure. + */ +typedef POSIF_GLOBAL_TypeDef XMC_POSIF_t; + +/** + * Defines POSIF quadrature decoder initialization data structure. + * Use type @ref XMC_POSIF_QD_CONFIG_t for this data structure. + * It used to configure Quadrature mode using \a QDC register. + */ +typedef struct XMC_POSIF_QD_CONFIG +{ + XMC_POSIF_QD_MODE_t mode; /**< Operational Mode of the quadrature encoder and decoder */ + union + { + struct + { + uint32_t phase_a: 1; /**< Phase-A active level configuration */ + uint32_t phase_b: 1; /**< Phase-B active level configuration */ + uint32_t phase_leader: 1; /**< Which of the two phase signals[Phase A or Phase B] leads the other? */ + uint32_t : 1; + uint32_t index: 2; /**< Index signal generation control. Use @ref XMC_POSIF_QD_INDEX_GENERATION_t to configure this field.*/ + uint32_t : 26; + }; + uint32_t qdc; + }; +} XMC_POSIF_QD_CONFIG_t; + +/** + * Defines POSIF hall sensor control initialization data structure. + * Use type @ref XMC_POSIF_HSC_CONFIG_t for this data structure. + * It used to initialize hall sensor mode configuration using \a PCONF register. + */ +typedef struct XMC_POSIF_HSC_CONFIG +{ + union + { + struct + { + uint32_t : 4; + uint32_t disable_idle_signal: 1; /**< Should idle signal be disabled upon wrong hall event? */ + uint32_t : 11; + uint32_t sampling_trigger: 1; /**< Of HSDA and HSDB, which one is to be used to trigger POSIF to sample hall pattern? */ + uint32_t sampling_trigger_edge: 1; /**< Which edge of the sampling trigger signal is to be considered? */ + uint32_t : 6; + uint32_t external_error_port: 2; /**< Of the 4 external error ports, which one is to be considered? */ + uint32_t external_error_enable: 1; /**< Should external errors lead to Wrong Hall event? */ + uint32_t external_error_level: 1; /**< What should be the active level of external error signal? */ + uint32_t: 4; + }; + uint32_t hall_config; + }; +} XMC_POSIF_HSC_CONFIG_t; + +/** + * Defines POSIF multi-channel mode initialization data structure. + * Use type @ref XMC_POSIF_MCM_CONFIG_t for this data structure. + * It used to initialize multi channel mode configuration using \a PCONF register. + */ +typedef struct XMC_POSIF_MCM_CONFIG +{ + union + { + struct + { + uint32_t : 5; + uint32_t pattern_sw_update: 1; /**< should multi channel pattern updated by SW ? */ + uint32_t : 12; + uint32_t pattern_update_trigger: 3; /**< Of the 8 update triggers, which one is to be considered? */ + uint32_t pattern_trigger_edge: 1; /**< Which edge of the pattern update trigger is to be considered? */ + uint32_t pwm_sync: 2; /**< Of the 4 pwm sync inputs, which one is to be considered? */ + uint32_t : 8; + }; + uint32_t mcm_config; + }; +}XMC_POSIF_MCM_CONFIG_t; + +/** + * Defines POSIF module initialization data structure. + * Use type @ref XMC_POSIF_CONFIG_t for this data structure. + * It is used to initialize POSIF module using \a PCONF register. + */ +typedef struct XMC_POSIF_CONFIG +{ + union + { + struct + { + uint32_t mode: 2; /**< POSIF Operational mode. Use @ref XMC_POSIF_MODE_t to configure */ + uint32_t :6; + uint32_t input0: 2; /**< Choice of input for Input-1 */ + uint32_t input1: 2; /**< Choice of input for Input-2 */ + uint32_t input2: 2; /**< Choice of input for Input-3 */ + uint32_t :14; + uint32_t filter: 3; /**< Input filter configuration */ + uint32_t: 1; + }; + uint32_t pconf; + }; +} XMC_POSIF_CONFIG_t; + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param peripheral Pointer to an instance of POSIF module of type @ref XMC_POSIF_t + * @retval None + * + * \parDescription
+ * De-asserts the POSIF module from reset and enables the clock.\n + * Configures \a PRCLR0 register's \a POSIF0RS or \a POSIF1RS bit field depends upon \a peripheral. + * If running on other than XMC45 device then it will ungate the peripheral clock. + * + * \parNote
+ * This is the first API which application must invoke to configure POSIF. + * It is internally called by XMC_POSIF_Init(). + * + * \parRelated APIs:
+ * XMC_POSIF_Disable(),XMC_POSIF_Init() \n\n\n + */ +void XMC_POSIF_Enable(XMC_POSIF_t *const peripheral); + +/** + * @param peripheral Pointer to an instance of POSIF module of type @ref XMC_POSIF_t + * @retval None + * + * \parDescription
+ * Asserts the POSIF module into reset and disables the clock.\n + * If running on other than XMC45 device then in addition it will gate the peripheral clock. + * Configures \a PRCLR0 register's \a POSIF0RS or \a POSIF1RS bitfield depends upon \a peripheral. + * + * \parRelated APIs:
+ * XMC_POSIF_Enable()\n\n\n + */ +void XMC_POSIF_Disable(XMC_POSIF_t *const peripheral); + +/** + * @param peripheral Pointer to an instance of POSIF module of type @ref XMC_POSIF_t + * @param config Pointer to POSIF configuration data(operation mode,input selection and filter configuration) + * @retval None + * + * \parDescription
+ * Initialize POSIF module with \a config.\n + * Configures POSIF global registers.This is the first API which application must invoke to configure POSIF. + * It sets up parameters common to all the POSIF modes - hall sensor,quadrature decoder and multi-channel modes of operation. + * Configures \a PCONF register with mode of operation,input selection and filter configuration. + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_Init(),XMC_POSIF_QD_Init(),XMC_POSIF_MCM_Init() \n\n\n +*/ +void XMC_POSIF_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_CONFIG_t * const config); + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param config Pointer to hall sensor control initialization data of type @ref XMC_POSIF_HSC_CONFIG_t + * @retval XMC_POSIF_STATUS_t Returns @ref XMC_POSIF_STATUS_OK if configured in Hall Sensor Mode + * else return @ref XMC_POSIF_STATUS_ERROR. + * + * \parDescription
+ * Initializes hall sensor control mode.\n + * Configures \a PCONF register with which POSIF input trigger to be used for + * sampling hall pattern.Configures \a PCONF register for idle signal generation for wrong hall event. + * + * \parNote
+ * It is necessary to have called XMC_POSIF_Init first with Hall sensor mode before invocation of this API. + * + * \parRelated APIs:
+ * XMC_POSIF_Init() \n\n\n + */ +XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_HSC_CONFIG_t * const config); + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param config Pointer to quadrature decoder initialization data + * @retval XMC_POSIF_STATUS_t Returns quadrature mode initialization status of type @ref XMC_POSIF_STATUS_t + * + * \parDescription
+ * Initializes quadrature decoder control mode.\n + * Configures \a PCONF register with quadrature mode using @ref XMC_POSIF_QD_MODE_t data structure. + * Initializes \a QDC register with quadrature mode configuration using @ref XMC_POSIF_QD_CONFIG_t structure. + * + * \parNote
+ * It is necessary to have called XMC_POSIF_Init first with Quadrature decoder mode before invocation of this API. + * + * \parRelated APIs:
+ * XMC_POSIF_Init() \n\n\n + */ +XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_QD_CONFIG_t * const config); + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param config Pointer to quadrature decoder initialization data + * @retval XMC_POSIF_STATUS_t Returns multi channel pattern initialization status of type @ref XMC_POSIF_STATUS_t + * + * \parDescription
+ * Initializes multi channel mode in Hall mode, standalone multi-channel mode and quadrature with multi-channel mode.\n + * Configures \a PCONF register with multi channel mode using @ref XMC_POSIF_MCM_CONFIG_t data structure. + * + * \parNote
+ * It is necessary to call XMC_POSIF_Init first before invocation of this API. + * For XMC_POSIF_MODE_HALL_SENSOR, it is necessary to have called XMC_POSIF_HSC_Init before invocation of this API. + * For XMC_POSIF_MODE_MCM_QD, it is necessary to have called XMC_POSIF_QD_Init before invocation of this API. + * + * \parRelated APIs:
+ * XMC_POSIF_Init(),XMC_POSIF_HSC_Init(),XMC_POSIF_QD_Init() \n\n\n + */ +XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_MCM_CONFIG_t * const config); + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param mode POSIF operating mode of type @ref XMC_POSIF_MODE_t + * @retval None + * + * \parDescription
+ * Configures POSIF module for \a mode.\n + * Configures \a PCONF register's a\ FSEL bitfield with \a mode. + * Refer @ref XMC_POSIF_MODE_t for available options. + * + * \parNote
+ * POSIF module should be in stopped state while changing the operating mode. + * + * \parRelated APIs:
+ * XMC_POSIF_Stop() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_SetMode(XMC_POSIF_t *const peripheral, const XMC_POSIF_MODE_t mode) +{ + peripheral->PCONF = ((peripheral->PCONF & ~(uint32_t)(POSIF_PCONF_FSEL_Msk)) | + (((uint32_t)mode << POSIF_PCONF_FSEL_Pos) & (uint32_t)POSIF_PCONF_FSEL_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param input0 Choice of input for input 0 [0-3] + * @param input1 Choice of input for input 1 [0-3] + * @param input2 Choice of input for input 2 [0-3] + * @retval None + * + * \parDescription
+ * Configures which input to be connected to POSIF module. \n + * Configures \a PCONF register's INSEL0,INSEL1,INSEL2 bit fields with source for the input connection for \a input0 + * \a input1, \a input2 respectively. + * + * \parNote
+ * Configures which input is used for the Phase X or Hall input X function depending upon the module is + * set for Quadrature Decoder or Hall Sensor Mode. + * + * \parRelated APIs:
+ * XMC_POSIF_Init() \n\n\n + */ +void XMC_POSIF_SelectInputSource(XMC_POSIF_t *const peripheral, const XMC_POSIF_INPUT_PORT_t input0, + const XMC_POSIF_INPUT_PORT_t input1, const XMC_POSIF_INPUT_PORT_t input2); + + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval None + * + * \parDescription
+ * Starts POSIF \a peripheral functional state machine.\n + * Starts POSIF state machine for \a peripheral.Configures \a PRUNS register's \a SRB bit field with 1. + * + * \parNote
+ * Global properties of POSIF along with mode specific properties should have been initialized before starting of POSIF + * FSM. + * + * \parRelated APIs:
+ * XMC_POSIF_Stop(),XMC_POSIF_IsRunning() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_Start(XMC_POSIF_t *const peripheral) +{ + peripheral->PRUNS = (uint32_t)POSIF_PRUNS_SRB_Msk; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval None + * + * \parDescription
+ * Stops POSIF \a peripheral functional state machine.\n + * Stop POSIF functional state machine and clears current internal status of the \a peripheral. + * Configures \a PRUNC register's \a CRB bit field with 1. + * + * \parRelated APIs:
+ * XMC_POSIF_Start(),XMC_POSIF_IsRunning() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_Stop(XMC_POSIF_t *const peripheral) +{ + peripheral->PRUNC = (uint32_t)(POSIF_PRUNC_CRB_Msk | POSIF_PRUNC_CSM_Msk); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval bool Returns false: IDLE, true:RUNNING + * + * \parDescription
+ * Returns the status of POSIF module - Running or IDLE.\n + * Retrieves the status from \a PRUN register's \a SRB bit. + * + * \parRelated APIs:
+ * XMC_POSIF_Start(),XMC_POSIF_Stop() \n\n\n + */ +__STATIC_INLINE bool XMC_POSIF_IsRunning(XMC_POSIF_t *const peripheral) +{ + return ((bool)peripheral->PRUN); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns last sampled hall sensor pattern. Range : [0-7] + * + * \parDescription
+ * Returns last sampled hall sensor pattern of \a peripheral.\n + * Retrieves the last sampled hall sensor pattern from \a PDBG register's \a HSP bit field of \a peripheral. + * Applications can at any point in time retrieve the last sampled hall sensor pattern by invoking this API. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation. + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_GetCurrentPattern(),XMC_POSIF_HSC_GetExpectedPattern() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_HSC_GetLastSampledPattern(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->PDBG) & POSIF_PDBG_HSP_Msk) >> POSIF_PDBG_HSP_Pos); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns current hall sensor pattern. Range : [0-7] + * + * \parDescription
+ * Returns current sampled hall sensor pattern of \a peripheral.\n + * Retrieves the current hall sensor pattern from \a HALP register's \a HCP bit field of \a peripheral. + * Applications can at any point in time retrieve the current hall sensor pattern by invoking this API. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation. + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_GetLastSampledPattern(),XMC_POSIF_HSC_GetExpectedPattern() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_HSC_GetCurrentPattern(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->HALP & POSIF_HALP_HCP_Msk) >> POSIF_HALP_HCP_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns expected hall sensor pattern. Range : [0-7] + * + * \parDescription
+ * Returns expected hall sensor pattern of \a peripheral.\n + * Retrieves the expected hall sensor pattern from \a HALP register's \a HEP bit field of \a peripheral. + * Applications can at any point in time retrieve the expected hall sensor pattern by invoking this API. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation. + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_GetLastSampledPattern(),XMC_POSIF_HSC_GetCurrentPattern() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_HSC_GetExpectedPattern(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->HALP & POSIF_HALP_HEP_Msk) >> POSIF_HALP_HEP_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param pattern The hall sensor pattern to be programmed into current pattern [0-7] + * @retval None + * + * \parDescription
+ * Configures current Hall sensor \a pattern of \a peripheral.\n + * Configures the Current hall sensor pattern on \a HALPS shadow register's \a HCPS bit field of \a peripheral. + * Applications can set at any point in time program the current hall sensor pattern by invoking this API. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation. It may be noted that the pattern is merely + * written to the shadow register. Transfer from the shadow register is based on a hardware transfer trigger + * or software trigger through API @ref XMC_POSIF_HSC_UpdateHallPattern(). + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_GetCurrentPattern(),XMC_POSIF_HSC_SetExpectedPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_HSC_SetCurrentPattern(XMC_POSIF_t *const peripheral, const uint8_t pattern) +{ + peripheral->HALPS = ((peripheral->HALPS & ~(uint32_t)(POSIF_HALPS_HCPS_Msk)) | + (((uint32_t)pattern << POSIF_HALPS_HCPS_Pos) & (uint32_t)POSIF_HALPS_HCPS_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param pattern The hall sensor pattern to be programmed into expected pattern [0-7] + * @retval None + * + * \parDescription
+ * Configures the expected hall sensor \a pattern of \a peripheral.\n + * Applications can set at any point in time program the hall sensor expected patterns by invoking this API. + * Configures the expected hall sensor pattern on \a HALPS shadow register's \a HEPS bit field of \a peripheral. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation.It may be noted that the pattern is merely + * written to the shadow register. Transfer from the shadow register is based on a hardware transfer trigger + * or software trigger through API @ref XMC_POSIF_HSC_UpdateHallPattern(). + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_GetExpectedPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_HSC_SetExpectedPattern(XMC_POSIF_t *const peripheral, const uint8_t pattern) +{ + peripheral->HALPS = ((peripheral->HALPS & ~(uint32_t)(POSIF_HALPS_HEPS_Msk)) | + (((uint32_t)pattern << POSIF_HALPS_HEPS_Pos) & (uint32_t)POSIF_HALPS_HEPS_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param pattern_mask The hall sensor pattern mask [0-63] Format of mask: (expected_pattern << 3) | (current_pattern) + * @retval None + * + * \parDescription
+ * Configures current and expected hall pattern of \a peripheral. \n + * Configures \a HALPS register with the Current and Expected hall sensor patterns in one operation. + * Applications can at any point in time program the current and expected hall sensor pattern by invoking this API. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation. It may be noted that the pattern is merely + * written to the shadow register. Transfer from the shadow register is based on a hardware transfer trigger + * or software trigger through API @ref XMC_POSIF_HSC_UpdateHallPattern(). + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_SetExpectedPattern(),XMC_POSIF_HSC_SetCurrentPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_HSC_SetHallPatterns(XMC_POSIF_t *const peripheral, const uint8_t pattern_mask) +{ + peripheral->HALPS = (uint32_t)(pattern_mask & (POSIF_HALPS_HCPS_Msk | POSIF_HALPS_HEPS_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval None + * + * \parDescription
+ * Manually performs shadow transfer of hall sensor patterns.\n + * Configures \a MCMS register's \a STHR bit field with 1. + * Setting this bit to 1 leads to an immediate update of the fields \a HALP.HCP(Current pattern) and \a HALP.HEP(Expected pattern). + * + * \parNote
+ * The transfer of hall sensor pattern shadow registers content to the sensor pattern register happens under two + * conditions. A hardware trigger starts the shadow transfer. Alternatively, the shadow transfer can be initiated + * by application software by means of invocation of this API. + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_SetHallPatterns() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_HSC_UpdateHallPattern(XMC_POSIF_t *const peripheral) +{ + peripheral->MCMS = (uint32_t)POSIF_MCMS_STHR_Msk; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param pattern The 16b multi-channel pattern [0-65535] + * @retval None + * + * \parDescription
+ * Configures \a MCSM register with Multi-Channel Pattern.\n + * This 16b multi-channel pattern which controls the 16 outputs of all slices of a CCU8 module. + * Transfer from the shadow register is based on a hardware transfer trigger + * or software trigger through API @ref XMC_POSIF_MCM_UpdateMultiChannelPattern(). + * Every time that a Multi-Channel pattern transfer is triggered, this value is passed into the field \a MCM.MCMP of \a peripheral + * + * \parNote
+ * It may be noted that the pattern is merely written to the shadow register. + * + * \parRelated APIs:
+ * XMC_POSIF_MCM_GetMultiChannelPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_MCM_SetMultiChannelPattern(XMC_POSIF_t *const peripheral, const uint16_t pattern) +{ + peripheral->MCSM = pattern; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint16_t Returns configured multi channel pattern + * + * \parDescription
+ * Returns configured multi channel pattern of \a peripheral. \n + * Retrieves the Multi-Channel Pattern from \a MCM register's MCMP bit field of \a peripheral + * Applications can at any point in time retrieve the multi-channel pattern by invoking this API. + * + * \parRelated APIs:
+ * XMC_POSIF_MCM_SetMultiChannelPattern() \n\n\n + */ +__STATIC_INLINE uint16_t XMC_POSIF_MCM_GetMultiChannelPattern(XMC_POSIF_t *const peripheral) +{ + return ((uint16_t)(peripheral->MCM & (uint32_t)POSIF_MCM_MCMP_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint16_t Returns configured multi channel pattern present in shadow transfer register + * + * \parDescription
+ * Returns configured multi channel pattern in shadow register of \a peripheral. \n + * Retrieves the Multi-Channel Pattern from \a MCSM shadow register's \a MCMPS bit field. + * Applications can at any point in time retrieve the multi-channel pattern by invoking this API. + * + * It can be used when MCM is enabled. + * + * \parRelated APIs:
+ * XMC_POSIF_MCM_SetMultiChannelPattern() \n\n\n + */ +__STATIC_INLINE uint16_t XMC_POSIF_MCM_GetShadowMultiChannelPattern(XMC_POSIF_t *const peripheral) +{ + return ((uint16_t)(peripheral->MCSM & (uint32_t)POSIF_MCSM_MCMPS_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval None + * + * \parDescription
+ * Performs shadow transfer of the Multi-Channel Pattern register by configuring \a MCMS register's \a STMR bit field. + * + * \parNote
+ * Transfer multi-channel pattern shadow registers content to the actual pattern register of \a peripheral. \n + * The transfer of multi-channel pattern shadow registers content to the actual pattern register happens under two + * conditions. A hardware trigger starts the shadow transfer. Alternatively, the shadow transfer can be initiated + * by application software by means of invocation of this API. + * + * \parRelated APIs:
+ * XMC_POSIF_MCM_SetMultiChannelPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_MCM_UpdateMultiChannelPattern(XMC_POSIF_t *const peripheral) +{ + peripheral->MCMS |= (uint32_t)POSIF_MCMS_STMR_Msk; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval None + * + * \parDescription
+ * Enables update of the Multi-Channel Pattern by software in standalone multi-channel mode.\n + * Enabling update of multi-channel pattern happens under two conditions. A hardware trigger enables this update. + * Alternatively, this can be enabled by software by means of invocation of this API. + * + * \parNote
+ * The update is not done immediately due to the fact that the trigger that synchronizes the update with the PWM is + * still needed. + * + * \parRelated APIs:
+ * XMC_POSIF_MCM_UpdateMultiChannelPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_MCM_EnableMultiChannelPatternUpdate(XMC_POSIF_t *const peripheral) +{ + peripheral->MCMS |= (uint32_t)POSIF_MCMS_MNPS_Msk; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval XMC_POSIF_QD_DIR_t Return direction of revolution of the motor of type @ref XMC_POSIF_QD_DIR_t + * + * \parDescription
+ * Returns the direction of revolution of the motor.\n + * Retrieves direction from \a QDC register's \a DVAL bit field in quadrature mode. + * Applications can at any point in time retrieve the direction of rotation by invoking this API. + * + * \parNote
+ * This is applicable only to the quadrature decoder mode of operation. + * + */ +__STATIC_INLINE XMC_POSIF_QD_DIR_t XMC_POSIF_QD_GetDirection(XMC_POSIF_t *const peripheral) +{ + return ((XMC_POSIF_QD_DIR_t)((peripheral->QDC & POSIF_QDC_DVAL_Msk) >> POSIF_QDC_DVAL_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns current state of quadrature decoder[Phase B,Phase A] + * + * \parDescription
+ * Returns the current state of phase signals in quadrature decoder mode of \a peripheral. \n + * Retrieves current state of the quadrature decoder from \a PDBG register's \a QCSV bit fields. + * Applications can at any point in time retrieve the current state of Phase A and Phase B signals + * by invoking this API. + * + * \parNote
+ * This is applicable only to the quadrature decoder mode of operation. + * + * \parRelated APIs:
+ * XMC_POSIF_QD_GetPreviousState() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_QD_GetCurrentState(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->PDBG & POSIF_PDBG_QCSV_Msk) >> POSIF_PDBG_QCSV_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns previous state of quadrature decoder[Phase B,Phase A] + * + * \parDescription
+ * Returns the previous state of phase signals in quadrature decoder mode of \a peripheral. \n + * Retrieves previous state of the quadrature decoder from \a PDBG register's \a QPSV bit fields. + * Applications can at any point in time retrieve the previous state of Phase A and Phase B signals + * by invoking this API. + * + * \parNote
+ * This is applicable only to the quadrature decoder mode of operation. + * + * \parRelated APIs:
+ * XMC_POSIF_QD_GetCurrentState() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_QD_GetPreviousState(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->PDBG & POSIF_PDBG_QPSV_Msk) >> POSIF_PDBG_QPSV_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns the index value.[1 - New rotation started, 0 - In-between] + * + * \parDescription
+ * Returns the current index value in quadrature decoder mode of \a peripheral. \n + * Retrieves current index signal value of the quadrature decoder from \a PDBG register's \a IVAL bit field. + * Applications can at any point in time retrieve the current index signal value of the quadrature decoder by + * invoking this API. + * + * \parNote
+ * This is applicable only to the quadrature decoder mode of operation. + * + */ +__STATIC_INLINE uint8_t XMC_POSIF_QD_GetCurrentIndexValue(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->PDBG & POSIF_PDBG_IVAL_Msk) >> POSIF_PDBG_IVAL_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param event Event to be enabled + * @retval None + * + * \parDescription
+ * Enables \a event generation of \a peripheral. \n + * Enables an IRQ generation capable \a event by configuring 1 to \a PFLGE register's \a event bit field. + * + * \parRelated APIs:
+ * XMC_POSIF_DisableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_EnableEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) +{ + peripheral->PFLGE |= (uint32_t)1 << (uint8_t)event; +} + +/** + * @brief Disables an IRQ generation capable event + * @param peripheral Pointer to an instance of POSIF module + * @param event Event to be disabled + * @retval None + * + * \parDescription
+ * Disables \a event generation of \a peripheral.\n + * Disables an IRQ generation capable \a event by configuring 0 to \a PFLGE register's \a event bit field. + * + * \parRelated APIs:
+ * XMC_POSIF_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_DisableEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) +{ + peripheral->PFLGE &= ~((uint32_t)1 << (uint8_t)event); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param event Event to be manually asserted + * @retval None + * + * \parDescription
+ * Manually generates \a event of \a peripheral. \n + * Manually asserts an IRQ generation capable event by configuring 1 to \a SPFLG register's \a event bit field. + * + * \parRelated APIs:
+ * XMC_POSIF_ClearEvent() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_SetEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) +{ + peripheral->SPFLG = (uint32_t)1 << (uint8_t)event; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param event Event to be acknowledged + * @retval None + * + * \parDescription
+ * Clears \a event by acknowledgment of \a peripheral. \n + * Acknowledges an IRQ event by configuring 1 to \a RPFLG register's \a event bit field. + * + * \parRelated APIs:
+ * XMC_POSIF_SetEvent() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_ClearEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) +{ + peripheral->RPFLG = (uint32_t)1 << (uint8_t)event; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param event Event ID to be checked for status + * @retval uint8_t Returns event status + * + * \parDescription
+ * Returns \a event status of \a peripheral. \n + * Determines if IRQ event is asserted by retrieving data from \a PFLG register's \a event bit field. + * + * \parRelated APIs:
+ * XMC_POSIF_SetEvent(),XMC_POSIF_ClearEvent() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_GetEventStatus(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) +{ + return ((uint8_t)((peripheral->PFLG >> (uint8_t)event) & 1U)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param event Event to be acknowledged of type @ref XMC_POSIF_IRQ_EVENT_t + * @param sr Service request line of type @ref XMC_POSIF_SR_ID_t + * @retval None + * + * \parDescription
+ * Configures \a event to generate \a sr (service request) of \a peripheral. \n + * Binds an IRQ event to a service request line by configuring \a PFLGE register's \a event bit field. + */ +void XMC_POSIF_SetInterruptNode(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event, const XMC_POSIF_SR_ID_t sr); + +#ifdef __cplusplus +} +#endif /* #if defined(POSIF0) */ + +/** + * @} + */ + +/** + * @} + */ + +#endif + +#endif /* XMC_POSIF_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_rtc.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_rtc.h new file mode 100644 index 00000000..f0b7d3a5 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_rtc.h @@ -0,0 +1,683 @@ +/** + * @file xmc_rtc.h + * @date 2016-05-19 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial + * + * 2015-05-20: + * - Documentation updates
+ * - In xmc1_rtc file XMC_RTC_Init function + * is modified by adding the RTC running condition check + * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2016-05-19: + * - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat() + * + * @endcond + * + */ + +#ifndef XMC_RTC_H +#define XMC_RTC_H + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ + +#include +#include + +/** + * + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup RTC + * @brief RTC driver for XMC microcontroller family. + * + * Real-time clock (RTC) is a clock that keeps track of the current time. Precise + * real time keeping is with a 32.768 KHz external crystal clock or a 32.768 KHz + * high precision internal clock. It provides a periodic time based interrupt and + * a programmable alarm interrupt on time match. It also supports wakeup from + * hibernate. + * + * The RTC low level driver provides functions to configure and initialize the RTC + * hardware peripheral. + * + * @{ + */ + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ + +/********************************************************************************************************************* + * ENUMS + *********************************************************************************************************************/ + +/** + * Status return values for RTC low level driver + */ +typedef enum XMC_RTC_STATUS +{ + XMC_RTC_STATUS_OK = 0U, /**< Operation successful */ + XMC_RTC_STATUS_ERROR = 1U, /**< Operation unsuccessful */ + XMC_RTC_STATUS_BUSY = 2U /**< Busy with a previous request */ +} XMC_RTC_STATUS_t; + +/** + * Events which enables interrupt request generation + */ +typedef enum XMC_RTC_EVENT +{ + XMC_RTC_EVENT_PERIODIC_SECONDS = RTC_MSKSR_MPSE_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_PERIODIC_MINUTES = RTC_MSKSR_MPMI_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_PERIODIC_HOURS = RTC_MSKSR_MPHO_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_PERIODIC_DAYS = RTC_MSKSR_MPDA_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_PERIODIC_MONTHS = RTC_MSKSR_MPMO_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_PERIODIC_YEARS = RTC_MSKSR_MPYE_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_ALARM = RTC_MSKSR_MAI_Msk /**< Mask value to enable an event on periodic seconds */ +} XMC_RTC_EVENT_t; + +/** + * Months used to program the date + */ +typedef enum XMC_RTC_MONTH +{ + XMC_RTC_MONTH_JANUARY = 0U, + XMC_RTC_MONTH_FEBRUARY = 1U, + XMC_RTC_MONTH_MARCH = 2U, + XMC_RTC_MONTH_APRIL = 3U, + XMC_RTC_MONTH_MAY = 4U, + XMC_RTC_MONTH_JUNE = 5U, + XMC_RTC_MONTH_JULY = 6U, + XMC_RTC_MONTH_AUGUST = 7U, + XMC_RTC_MONTH_SEPTEMBER = 8U, + XMC_RTC_MONTH_OCTOBER = 9U, + XMC_RTC_MONTH_NOVEMBER = 10U, + XMC_RTC_MONTH_DECEMBER = 11U +} XMC_RTC_MONTH_t; + +/** + * Week days used program the date + */ +typedef enum XMC_RTC_WEEKDAY +{ + XMC_RTC_WEEKDAY_SUNDAY = 0U, + XMC_RTC_WEEKDAY_MONDAY = 1U, + XMC_RTC_WEEKDAY_TUESDAY = 2U, + XMC_RTC_WEEKDAY_WEDNESDAY = 3U, + XMC_RTC_WEEKDAY_THURSDAY = 4U, + XMC_RTC_WEEKDAY_FRIDAY = 5U, + XMC_RTC_WEEKDAY_SATURDAY = 6U +} XMC_RTC_WEEKDAY_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + *********************************************************************************************************************/ +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + + +/** + * Alarm time values of RTC
+ * + * The structure presents a convenient way to set/obtain the + * alarm time values for seconds, minutes, hours, days, month and year of RTC. + * The XMC_RTC_SetAlarm() and XMC_RTC_GetAlarm() can be + * used to populate the structure with the alarm time value of + * RTC + */ +typedef struct XMC_RTC_ALARM +{ + union + { + uint32_t raw0; + struct + { + uint32_t seconds : 6; /**< Alarm seconds compare value (0-59: Above this causes this bitfield to be set with 0)*/ + uint32_t : 2; + uint32_t minutes : 6; /**< Alarm minutes compare value (0-59: Above this causes this bitfield to be set with 0)*/ + uint32_t : 2; + uint32_t hours : 5; /**< Alarm hours compare value (0-23: Above this causes this bitfield to be set with 0)*/ + uint32_t : 3; + uint32_t days : 5; /**< Alarm days compare value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/ + uint32_t : 3; + }; + }; + + union + { + uint32_t raw1; + struct + { + uint32_t : 8; + uint32_t month : 4; /**< Alarm month compare value (0-11: Above this causes this bitfield to be set with 0) */ + uint32_t : 4; + uint32_t year : 16; /**< Alarm year compare value */ + }; + }; +} XMC_RTC_ALARM_t; + +/** + * Time values of RTC
+ * + * The structure presents a convenient way to set/obtain the + * time values for seconds, minutes, hours, days, month and year of RTC. + * The XMC_RTC_SetTime() and XMC_RTC_GetTime() can be + * used to populate the structure with the time value of + * RTC + */ +typedef struct XMC_RTC_TIME +{ + union + { + uint32_t raw0; + struct + { + uint32_t seconds : 6; /**< Seconds time value (0-59: Above this causes this bitfield to be set with 0) */ + uint32_t : 2; + uint32_t minutes : 6; /**< Minutes time value (0-59: Above this causes this bitfield to be set with 0) */ + uint32_t : 2; + uint32_t hours : 5; /**< Hours time value (0-23: Above this causes this bitfield to be set with 0) */ + uint32_t : 3; + uint32_t days : 5; /**< Days time value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/ + uint32_t : 3; + }; + }; + + union + { + uint32_t raw1; + struct + { + uint32_t daysofweek : 3; /**< Days of week time value (0-6: Above this causes this bitfield to be set with 0) */ + uint32_t : 5; + uint32_t month : 4; /**< Month time value (0-11: Above this causes this bitfield to be set with 0) */ + uint32_t : 4; + uint32_t year : 16; /**< Year time value */ + }; + }; +} XMC_RTC_TIME_t; +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +/** + * RTC initialization with time, alarm and clock divider(prescaler) configurations
+ * + * The structure presents a convenient way to set/obtain the time and alarm configurations + * for RTC. The XMC_RTC_Init() can be used to populate the structure with the time and alarm + * values of RTC. + */ +typedef struct XMC_RTC_CONFIG +{ + XMC_RTC_TIME_t time; + XMC_RTC_ALARM_t alarm; + uint16_t prescaler; +} XMC_RTC_CONFIG_t; + +/******************************************************************************* + * EXTENSIONS + *******************************************************************************/ + +#if UC_FAMILY == XMC1 +#include "xmc1_rtc.h" +#endif + +#if UC_FAMILY == XMC4 +#include "xmc4_rtc.h" +#endif + +/******************************************************************************* + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param config Constant pointer to a constant ::XMC_RTC_CONFIG_t structure containing the + * time, alarm time and clock divider(prescaler) configuration. + * @return XMC_RTC_STATUS_t Always returns XMC_RTC_STATUS_OK (It contains only register assignment statements) + * + * \parDescription:
+ * Initialize the RTC peripheral
+ * + * \par \if XMC4 + * The function enables the hibernate domain for accessing RTC peripheral registers, configures + * internal clock divider, time and alarm values by writing to the CTR.DIV, TIM0, TIM1, ATIM0 and + * ATIM1 registers. + * \endif + * + * \if XMC1 + * The function ungates the peripheral clock for RTC, configures + * internal clock divider, time and alarm values by writing to the CTR.DIV, TIM0, TIM1, ATIM0 and + * ATIM1 registers. + * \endif + */ +XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config); + +/** + * @return None + * + * \parDescription
+ * Enables RTC peripheral for programming its registers
+ * + * \par \if XMC4 + * Enables the hibernate domain for accessing RTC peripheral registers. + * \endif + * + * \if XMC1 + * Ungates the peripheral clock. + * \endif + * + * \parRelated APIs:
+ * XMC_RTC_Disable(), XMC_SCU_RESET_DeassertPeripheralReset() + */ +void XMC_RTC_Enable(void); + +/** + * @return None + * + * \parDescription
+ * Disables RTC peripheral for programming its registers
+ * + * \par \if XMC4 + * Empty function (Hibernate domain is not disabled). + * \endif + * + * \if XMC1 + * Gates the peripheral clock. + * \endif + * + * \parRelated APIs:
+ * XMC_RTC_Enable(), XMC_SCU_RESET_AssertPeripheralReset() + */ +void XMC_RTC_Disable(void); + +/** + * @return None + * + * \parDescription
+ * Checks RTC peripheral is enabled for programming its registers
+ * + * \par \if XMC4 + * Checks the hibernate domain is enabled or not. + * \endif + * + * \if XMC1 + * Checks peripheral clock is ungated or not. + * \endif + * + * \parRelated APIs:
+ * XMC_RTC_Enable(), XMC_RTC_Disable(), XMC_SCU_RESET_DeassertPeripheralReset(), + * XMC_SCU_RESET_AssertPeripheralReset() + */ +bool XMC_RTC_IsEnabled(void); + +/** + * @return None + * + * \parDescription
+ * Enables RTC peripheral to start counting time
+ * + * \par + * The function starts the RTC for counting time by setting + * CTR.ENB bit. Before starting the RTC, it should not be in + * running mode and also hibernate domain should be enabled. + * + * \parRelated APIs:
+ * XMC_RTC_Enable(), XMC_RTC_Stop(), XMC_SCU_RESET_DeassertPeripheralReset() + */ +void XMC_RTC_Start(void); + +/** + * @return None + * + * \parDescription
+ * Disables RTC peripheral to start counting time
+ * + * \par + * The function stops the RTC for counting time by resetting + * CTR.ENB. Before stopping the RTC, hibernate domain should be enabled. + * + * \parRelated APIs:
+ * XMC_RTC_Enable(), XMC_RTC_Start(), XMC_SCU_RESET_AssertPeripheralReset() + */ +void XMC_RTC_Stop(void); + +/** + * @param prescaler Prescaler value to be set + * @return None + * + * \parDescription:
+ * Sets the RTC module prescaler value
+ * + * \par + * The function sets the CTR.DIV bitfield to configure the prescalar value. + * The default value for the prescalar with the 32.768kHz crystal (or the internal clock) + * is 7FFFH for a time interval of 1 sec. Before setting the prescaler value RTC should be + * in stop mode and hibernate domain should be enabled. + * + * \parRelated APIs:
+ * XMC_RTC_Stop(), XMC_RTC_Enable(), XMC_RTC_GetPrescaler() + */ +void XMC_RTC_SetPrescaler(uint16_t prescaler); + +/** + * @return None + * + * \parDescription:
+ * Gets the RTC module prescaler value
+ * + * \par + * The function reads the CTR.DIV bitfield to get the prescalar value. The default value + * for the prescalar with the 32.768kHz crystal (or the internal clock) is 7FFFH for a + * time interval of 1 sec. + * + * \parRelated APIs:
+ * XMC_RTC_SetPrescaler() + */ +__STATIC_INLINE uint32_t XMC_RTC_GetPrescaler(void) +{ + return (uint32_t)(((uint32_t)RTC->CTR & (uint32_t)RTC_CTR_DIV_Msk) >> (uint32_t)RTC_CTR_DIV_Pos); +} + +/** + * @param timeval Contstant pointer to a constant ::XMC_RTC_TIME_t structure containing the + * time parameters seconds, minutes, hours, days, daysofweek, month and year. + * @return None + * + * \parDescription:
+ * Sets the RTC module time values
+ * + * \par + * The function sets the TIM0, TIM1 registers with time values. + * The values can only be written when RTC is disabled. + * See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters.
+ * + * \parRelated APIs:
+ * XMC_RTC_GetTime(), XMC_RTC_Stop() + */ +void XMC_RTC_SetTime(const XMC_RTC_TIME_t *const timeval); + +/** + * @param time Pointer to a constant ::XMC_RTC_TIME_t structure containing the time parameters + * seconds, minutes, hours, days, daysofweek, month and year. + * @return None + * + * \parDescription:
+ * Gets the RTC module time value
+ * + * \par + * The function gets the time values from TIM0, TIM1 registers. + * See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters.
+ * + * \parRelated APIs:
+ * XMC_RTC_SetTime() + */ +void XMC_RTC_GetTime(XMC_RTC_TIME_t *const time); + +/** + * @param stdtime Pointer to a ::tm structure containing the time parameters seconds, + * minutes, hours, days, daysofweek, month, year(since 1900) and days in a + * year in standard format. + * @return None + * + * \parDescription:
+ * Sets the RTC module time value in standard format
+ * + * \par + * The function sets the time values from TIM0, TIM1 registers. + * + * \parRelated APIs:
+ * XMC_RTC_SetTime(), XMC_RTC_GetTime() + */ +void XMC_RTC_SetTimeStdFormat(const struct tm *const stdtime); + +/** + * @param stdtime Pointer to a constant ::tm structure containing the time parameters seconds, + * minutes, hours, days, daysofweek, month, year(since 1900) and days in a + * year in standard format. + * @return None + * + * \parDescription:
+ * Gets the RTC module time value in standard format
+ * + * \par + * The function gets the time values from TIM0, TIM1 registers. + * See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters.
+ * For days the valid range is (1 - Actual days of month), year (since 1900) and + * daysinyear (0 -365). + * + * \parRelated APIs:
+ * XMC_RTC_SetTime(), XMC_RTC_GetTime() + */ +void XMC_RTC_GetTimeStdFormat(struct tm *const stdtime); + +/** + * @param alarm Constant pointer to a constant ::XMC_RTC_ALARM_t structure containing the + * alarm time parameters alarm seconds, alarm minutes, alarm hours, alarm days, + * alarm daysofweek, alarm month and alarm year. + * @return None + * + * \parDescription:
+ * Sets the RTC module alarm time value
+ * + * \par + * The function sets the ATIM0, ATIM1 registers with alarm time values. + * See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters.
+ * + * \parRelated APIs:
+ * XMC_RTC_GetAlarm() + */ +void XMC_RTC_SetAlarm(const XMC_RTC_ALARM_t *const alarm); + +/** + * @param alarm Pointer to a constant ::XMC_RTC_ALARM_t structure containing the + * time parameters alarm seconds, alarm minutes, alarm hours, alarm days, + * alarm daysofweek, alarm month and alarm year. + * @return None + * + * \parDescription:
+ * Gets the RTC module alarm time value
+ * + * \par + * The function gets the alarm time values from ATIM0, ATIM1 registers. + * See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters.
+ * + * \parRelated APIs:
+ * XMC_RTC_SetAlarm() + */ +void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm); + +/** + * @param stdtime Pointer to a ::tm structure containing the time parameters alarm seconds, + * alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month, + * alarm year(since 1900) and alarm days in a year in standard format. + * @return None + * + * \parDescription:
+ * Sets the RTC module alarm time value in standard format
+ * + * \par + * The function sets the alarm time values from ATIM0, ATIM1 registers. + * + * \parRelated APIs:
+ * XMC_RTC_SetAlarm(), XMC_RTC_GetAlarm() + */ +void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime); + +/** + * @param stdtime Pointer to a constant ::tm structure containing the time parameters alarm seconds, + * alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month, + * alarm year(since 1900) and alarm days in a year in standard format. + * @return None + * + * \parDescription:
+ * Gets the RTC module alarm time value in standard format
+ * + * \par + * The function gets the alarm time values from ATIM0, ATIM1 registers. + * See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters.
+ * For days the valid range is (1 - Actual days of month), year (since 1900) and + * daysinyear (0 -365). + * + * \parRelated APIs:
+ * XMC_RTC_SetAlarm(), XMC_RTC_GetAlarm() + */ +void XMC_RTC_GetAlarmStdFormat(struct tm *const stdtime); + +/** + * @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Enable RTC periodic and alarm event(s)
+ * + * \par + * The function sets the bitfields of MSKSR register to enable interrupt generation + * for requested RTC event(s). + * Setting the masking value for the event(s) containing in the ::XMC_RTC_EVENT_t leads + * to a generation of the interrupt. + * + * \parRelated APIs:
+ * XMC_RTC_DisableEvent() + */ +void XMC_RTC_EnableEvent(const uint32_t event); + +/** + * @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Disable RTC periodic and alarm event(s)
+ * + * \par + * The function resets the bitfields of MSKSR register to disable interrupt generation + * for requested RTC event(s). + * Resetting the masking value for the the event(s) containing in the ::XMC_RTC_EVENT_t blocks + * the generation of the interrupt. + * + * \parRelated APIs:
+ * XMC_RTC_EnableEvent() + */ +void XMC_RTC_DisableEvent(const uint32_t event); + +/** + * @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Clears periodic and alarm event(s) status
+ * + * \par + * The function sets the bitfields of CLRSR register to clear status bits in RAWSTAT and STSSR registers. + * Setting the value for the the RTC event(s) containing in the ::XMC_RTC_EVENT_t clears the + * corresponding status bits in RAWSTAT and STSSR registers. + * + * \parRelated APIs:
+ * XMC_RTC_GetEventStatus() + */ +void XMC_RTC_ClearEvent(const uint32_t event); + +/** + * @return None + * + * \parDescription:
+ * Gets the RTC periodic and alarm event(s) status
+ * + * \par + * The function reads the bitfields of STSSR register + * to get the status of RTC events. + * Reading the value of the register STSSR gives the status of the event(s) containing in the ::XMC_RTC_EVENT_t. + * + * \parRelated APIs:
+ * XMC_RTC_ClearEvent() + */ +uint32_t XMC_RTC_GetEventStatus(void); + +/** + * @return bool true if RTC is running + * false if RTC is not running + * + * \parDescription:
+ * Checks the running status of the RTC
+ * + * \par + * The function reads the bitfield ENB of CTR register + * to get the running status of RTC. + * + * \parRelated APIs:
+ * XMC_RTC_Start(), XMC_RTC_Stop() + */ +__STATIC_INLINE bool XMC_RTC_IsRunning(void) +{ + return (bool)(RTC->CTR & RTC_CTR_ENB_Msk); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XMC_RTC_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_scu.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_scu.h new file mode 100644 index 00000000..cacb0cf2 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_scu.h @@ -0,0 +1,598 @@ +/** + * @file xmc_scu.h + * @date 2016-03-09 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - Documentation improved
+ * - XMC_ASSERT() hanging issues have fixed for XMC4 devices.
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * - Removed STATIC_INLINE property for the below APIs and declared as void + * XMC_SCU_INTERRUPT_EnableEvent, XMC_SCU_INTERRUPT_DisableEvent, + * XMC_SCU_INTERRUPT_TriggerEvent, XMC_SCU_INTERUPT_GetEventStatus, + * XMC_SCU_INTERUPT_ClearEventStatus + * + * 2015-11-30: + * - Documentation improved
+ * + * 2016-03-09: + * - Optimization of write only registers + * + * @endcond + * + */ +#ifndef XMC_SCU_H +#define XMC_SCU_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup SCU + * @brief System Control Unit(SCU) driver for XMC microcontroller family. + * + * System control unit is the SoC power, reset and a clock manager with additional responsibility of + * providing system stability protection and other auxiliary functions.
+ * SCU provides the following features, + * -# Power control + \if XMC4 + * -# Hibernate control + \endif + * -# Reset control + * -# Clock control + * -# Miscellaneous control(boot mode, system interrupts etc.)

+ * + * The SCU driver is divided in to clock control logic, reset control logic, system interrupt control logic + \if XMC4 + * , hibernate control logic, trap control logic, parity control logic + \endif + * and miscellaneous control logic.
+ * + * Clock driver features: + * -# Allows clock configuration using the structure XMC_SCU_CLOCK_CONFIG_t and API XMC_SCU_CLOCK_Init() + \if XMC4 + * -# Provides structure XMC_SCU_CLOCK_SYSPLL_CONFIG_t for configuring the system PLL + * -# Allows selection of clock source for system PLL, XMC_SCU_CLOCK_GetSystemPllClockSource() + * -# Provides APIs for configuring different module clock frequencies XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetUsbClockDivider() + * -# Allows selection of clock source for external output, XMC_SCU_CLOCK_SetExternalOutputClockSource() + * -# Provides APIs for enabling external high power oscillator and ultra low power oscillator, XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_EnableLowPowerOscillator() + * -# Provides APIs for getting various clock frequencies XMC_SCU_CLOCK_GetPeripheralClockFrequency(), + XMC_SCU_CLOCK_GetCpuClockFrequency(), XMC_SCU_CLOCK_GetSystemClockFrequency()
+ \endif + \if XMC1 + * -# Allows selection of peripheral clock frequency, XMC_SCU_CLOCK_SetFastPeripheralClockSource() + * -# Provides API to get the peripheral clock frequency, XMC_SCU_CLOCK_GetFastPeripheralClockFrequency() + \endif + * + * Reset driver features: + \if XMC4 + * -# Allows to handle peripheral reset XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset() + * -# Allows configuration of NMI generation for selected events, XMC_SCU_INTERRUPT_EnableNmiRequest() + \endif + \if XMC1 + * -# Allows to trigger device reset XMC_SCU_RESET_AssertMasterReset() + * -# Allows to configure multiple sources for reset, XMC_SCU_RESET_EnableResetRequest() + \endif
+ * + * Interrupt driver features: + * -# Provides APIs for enabling/ disabling interrupt event generation XMC_SCU_INTERRUPT_EnableEvent(), + XMC_SCU_INTERRUPT_DisableEvent() + * -# Provides API for registering callback function for events XMC_SCU_INTERRUPT_SetEventHandler()
+ * + \if XMC4 + * Hibernate driver features: + * -# Allows configuration of hibernate domain XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain() + * -# Allows selection of standby clock source, XMC_SCU_HIB_SetStandbyClockSource() + * -# Allows selection of RTC clock source, XMC_SCU_HIB_SetRtcClockSource() + * -# Provides API for enabling slow internal clock used for backup clock, XMC_SCU_HIB_EnableInternalSlowClock()
+ * + * Trap driver features: + * -# Allows handling of trap XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_GetStatus(), XMC_SCU_TRAP_Trigger()
+ * + * Parity driver features: + * -# Parity error generated by on-chip RAM can be monitored, XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_GetStatus() + * -# Allows configuration of trap generation on detection of parity error, XMC_SCU_PARITY_EnableTrapGeneration() + * + * Power driver features: + * -# Allows to power the USB module XMC_SCU_POWER_EnableUsb(), XMC_SCU_POWER_DisableUsb() + \endif + * + * Miscellaneous features: + * -# Allows to trigger multiple capture compare unit(CCU) channels to be started together XMC_SCU_SetCcuTriggerHigh() + \if XMC4 + * -# Enables configuration of out of range comparator (ORC) XMC_SCU_EnableOutOfRangeComparator() + * -# Enables configuration of die temperature sensor XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor() + * -# Enables configuration of device boot mode XMC_SCU_SetBootMode()
+ \endif + \if XMC1 + * -# Enables configuration of die temperature sensor XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits() + * -# Allows configuring supply monitor unit using the structure XMC_SCU_SUPPLYMONITOR_t and API XMC_SCU_SupplyMonitorInit() + * -# Allows handling of protected bits XMC_SCU_LockProtectedBits(), XMC_SCU_UnlockProtectedBits()
+ \endif + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +/** + * Defines the status of SCU API execution, used to verify the SCU related API calls. + */ +typedef enum XMC_SCU_STATUS +{ + XMC_SCU_STATUS_OK = 0UL, /**< SCU related operation successfully completed.*/ + XMC_SCU_STATUS_ERROR, /**< SCU related operation failed. When API cannot fulfill request, this value is returned. */ + XMC_SCU_STATUS_BUSY, /**< Cannot execute the SCU related operation request because + another operation is in progress. \a XMC_SCU_STATUS_BUSY is returned when API is busy + processing another request. */ +} XMC_SCU_STATUS_t; + + +/********************************************************************************************************************* + * DATA TYPES + ********************************************************************************************************************/ + +/** + * Function pointer type used for registering callback functions on SCU event occurrence. + */ +typedef void (*XMC_SCU_INTERRUPT_EVENT_HANDLER_t)(void); + +/********************************************************************************************************************* + * DEVICE EXTENSIONS + ********************************************************************************************************************/ + +#if (UC_FAMILY == XMC1) +#include +#elif (UC_FAMILY == XMC4) +#include +#else +#error "Unspecified chipset" +#endif + +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * + * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits + * in the register CCUCON.
+ * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be + * combined using \a OR operation. + * + * @return None + * + * \parDescription
+ * Generates active edge(low to high) trigger for multiple CCU units at the same time.\n\n + * Before executing this API, all the required CCU timers should configure external start. + * The edge of the start signal should be selected as active edge. + * The input signal for the CCU slice should be selected as SCU input. + * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). + * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering + * the timer using this API.
+ * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerLow()\n\n\n + */ +__STATIC_INLINE void XMC_SCU_SetCcuTriggerHigh(const uint32_t trigger) +{ + SCU_GENERAL->CCUCON |= (uint32_t)trigger; +} + +/** + * + * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits + * in the register CCUCON.
+ * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be + * combined using \a OR operation. + * + * @return None + * + * \parDescription
+ * Generates passive edge(high to low) trigger for multiple CCU units at the same time.\n\n + * Before executing this API, all the required CCU timers should configure external start. + * The edge of the start signal should be selected as passive edge. + * The input signal for the CCU slice should be selected as SCU input. + * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). + * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering + * the timer using this API.
+ * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerHigh()\n\n\n + */ +__STATIC_INLINE void XMC_SCU_SetCcuTriggerLow(const uint32_t trigger) +{ + SCU_GENERAL->CCUCON &= (uint32_t)~trigger; +} + +/** + * + * @param config Pointer to structure holding the clock prescaler values and divider values for + * configuring clock generators and clock tree.\n + * \b Range: Configure the members of structure @ref XMC_SCU_CLOCK_CONFIG_t for various + * parameters of clock setup. + * + * @return None + * + * \parDescription
+ * Initializes clock generators and clock tree.\n\n + * \if XMC1 + * Peripheral clock and system clock are configured based on the input configuration \a config. + * The system clock frequency is tuned by configuring the FDIV and IDIV values of CLKCR register. + * The values of FDIV and IDIV can be provided as part of input configuration. + * The PCLK divider determines the ratio of peripheral clock to the system clock. + * The source of RTC clock is set based on the input configuration. + * \a SystemCoreClock variable will be updated with the value of + * system clock frequency. Access to protected bit fields are handled internally. + * \endif + * \if XMC4 + * Enables the high precision oscillator(fOHP) input and configures the system and peripheral clock frequencies. + * Based on the system clock source selected in \a config, either fPLL or fOFI will be chosen as system clock. + * Based on PLL mode(normal or prescaler mode) used, PLL ramps up in steps to achieve target frequency. + * The clock dividers for CPU, CCU and peripheral clocks will be set based on the input configuration. + * The \a SystemCoreClock variable is set with the value of system clock frequency. + * \endif + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency() \n\n\n + */ +void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config); + +/** + * + * @param event Bit mask of the event to enable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t + * for providing the input value. Multiple events can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Enables the generation of interrupt for the input events.\n\n + * The events are enabled by setting the respective bit fields in the SRMSK register. \n + * Note: User should separately enable the NVIC node responsible for handling the SCU interrupt. + * The interrupt will be generated when the respective event occurs. + * \parRelated APIs:
+ * NVIC_EnableIRQ(), XMC_SCU_INTERRUPT_DisableEvent()\n\n\n + */ +void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event); + + +/** + * + * @param event Bit mask of the event to disable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t + * for providing the input value. Multiple events can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Disables generation of interrupt on occurrence of the input event.\n\n + * The events are disabled by resetting the respective bit fields in the SRMSK register. \n + * \parRelated APIs:
+ * NVIC_DisableIRQ(), XMC_SCU_INTERRUPT_EnableEvent()\n\n\n + */ +void XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event); + +/** + * + * @param event Bit mask of the event to be triggered. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t + * for providing the input value. Multiple events can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Triggers the event as if the hardware raised it.\n\n + * Event will be triggered by setting the respective bitfield in the SRSET register.\n + * Note: User should enable the NVIC node that handles the respective event for interrupt generation. + * \parRelated APIs:
+ * NVIC_EnableIRQ(), XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_ClearEventStatus() \n\n\n + */ +void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event); + +/** + * @return uint32_t Status of the SCU events. + * + * \parDescription
+ * Provides the status of all SCU events.\n\n + * The status is read from the SRRAW register. To check the status of a particular + * event, the returned value should be masked with the bit mask of the event. The bitmask + * of events can be obtained using the type @ref XMC_SCU_INTERRUPT_EVENT_t. Multiple events' + * status can be checked by combining the bit masks using \a OR operation. + * After detecting the event, the event status should be cleared using software to detect the event again. + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_ClearEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n + */ +XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus(void); + +/** + * + * @param event Bit mask of the events to clear. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t + * for providing the input value. Multiple events can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Clears the event status bit in SRRAW register.\n\n + * The events are cleared by writing value 1 to their bit positions in the SRCLR register. + * The API can be used when polling method is used. After detecting the event, the event status + * should be cleared using software to detect the event again. + * + * \parRelated APIs:
+ * XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent() \n\n\n + */ +void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event); + +/** + * + * @return uint32_t Status representing the reason for device reset. + * + * \parDescription
+ * Provides the value representing the reason for device reset.\n\n + * The return value is an encoded word, which can indicate multiple reasons for the last reset. Each bit position of the + * returned word is representative of a last reset cause. The returned value should be appropriately masked to check + * the cause of reset. + * The cause of the last reset gets automatically stored in + * the \a SCU_RSTSTAT register. The reset status shall be reset after each + * startup in order to ensure consistent source indication after the next reset. + * \b Range: The type @ref XMC_SCU_RESET_REASON_t can be used to get the bit masks of the reset cause. + * + * \parRelated APIs:
+ * XMC_SCU_RESET_ClearDeviceResetReason() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_RESET_GetDeviceResetReason(void) +{ + return ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_RSTSTAT_Msk); +} +/** + * @return None + * + * \parDescription
+ * Clears the reset reason bits in the reset status register. \n\n + * Clearing of the reset status information in the \a SCU_RSTSTAT register via register bit \a RSTCLR.RSCLR is strongly + * recommended to ensure a clear indication of the cause of next reset. + * + * \parRelated APIs:
+ * XMC_SCU_RESET_GetDeviceResetReason() \n\n\n + */ +__STATIC_INLINE void XMC_SCU_RESET_ClearDeviceResetReason(void) +{ + /* Clear RSTSTAT.RSTSTAT bitfield */ + SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk; +} + +/** + * @return uint32_t Value of CPU clock frequency. + * + * \parDescription
+ * Provides the vlaue of CPU clock frequency.\n\n + * The value is stored in a global variable \a \b SystemCoreClock. + * It is updated when the clock configuration is done using the SCU LLD APIs. + * The value represents the frequency of clock used for CPU operation. + * \b Range: Value is of type uint32_t, and gives the value of frequency in Hertz. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockFrequency(void) +{ + return SystemCoreClock; +} + +/** + * @return uint32_t Value of peripheral clock frequency in Hertz. + * + * \parDescription
+ * Provides the vlaue of clock frequency at which the peripherals are working.\n\n + * The value is derived from the CPU frequency. \b Range: Value is of type uint32_t. It is represented in Hertz. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetCpuClockFrequency(),XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void); + +#if(UC_SERIES != XMC45) + +/** + * + * @param peripheral The peripheral for which the clock has to be gated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t + * to identify the peripheral clock to be gated. + * + * @return None + * + * \parDescription
+ * Blocks the supply of clock to the selected peripheral.\n\n + * Clock gating helps in reducing the power consumption. User can selectively gate the clocks of unused peripherals. + * \if XMC1 + * fPCLK is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks + * the clock supply for the selected peripheral. + * Software can request for individual gating of such peripheral clocks by enabling the \a SCU_CGATSET0 + * register bit field. Every bit in \a SCU_CGATSET0 register is protected by the bit protection scheme. Access to protected + * bit fields are handled internally. + * \endif + * \if XMC4 + * fPERI is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks + * the clock supply for the selected peripheral. + * Software can request for individual gating of such peripheral clocks by enabling one of the \a + * SCU_CGATSET0, \a SCU_CGATSET1 or \a SCU_CGATSET2 register bitfields. + * + * \endif + * Note: Clock gating shall not be activated unless the module is in reset state. So use \a + * XMC_SCU_CLOCK_IsPeripheralClockGated() API before enabling the gating of any peripheral. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_UngatePeripheralClock() \n\n\n + */ +void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral); + +/** + * + * @param peripheral The peripheral for which the clock has to be ungated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t + * to identify the peripheral. + * + * @return None + * + * \parDescription
+ * Enables the supply of clock to the selected peripheral.\n\n + * By default when the device powers on, the peripheral clock will be gated for the + * peripherals that support clock gating. + * The peripheral clock should be enabled before using it for any functionality. + * \if XMC1 + * fPCLK is the source of clock to various peripherals. Some peripherals support clock gate. + * Software can request for individual ungating of such peripheral clocks by setting respective bits + * in the \a SCU_CGATCLR0 register. + * \endif + * \if XMC4 + * fPERI is the source of clock to various peripherals. Some peripherals support clock gate. + * Software can request for individual ungating of such peripheral clocks by setting the respective bits in one of \a + * SCU_CGATCLR0, \a SCU_CGATCLR1 or \a SCU_CGATCLR2 registers. + * \endif + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n + */ +void XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral); + +/** + * + * @param peripheral The peripheral for which the check for clock gating has to be done. + * \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral. + * + * @return bool Status of the peripheral clock gating. \b Range: true if the peripheral clock is gated. + * false if the peripheral clock ungated(gate de-asserted). + * + * \parDescription
+ * Gives the status of peripheral clock gating.\n\n + * \if XMC1 + * Checks the status of peripheral clock gating using the register CGATSTAT0. + * \endif + * \if XMC4 + * Checks the status of peripheral clock gating using one of CGATSTAT0, CGATSTAT1 or CGATSTAT2 registers. + * \endif + * It is recommended to use this API before + * enabling the gating of any peripherals through \a XMC_SCU_CLOCK_GatePeripheralClock() API. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_UngatePeripheralClock(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n + */ +bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral); +#endif + + +/** + * @return uint32_t Status of the register mirror update.\n + * \b Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register for the mirror update event of + * interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple update events can be combined + * using \a OR operation. + * + * \parDescription
+ * Provides the status of hibernate domain register update, when the respective mirror registers are changed. \n\n + * The hibernate domain is connected to the core domain via SPI serial communication. MIRRSTS is a status register + * representing the communication of changed value of a mirror register to its corresponding register in the + * hibernate domain. The bit fields of the register indicate + * that a corresponding register of the hibernate domain is ready to accept a write or that the communication interface + * is busy with executing the previous operation.\n + * Note: There is no hibernate domain in XMC1x devices. This register is retained for legacy purpose. + */ +__STATIC_INLINE uint32_t XMC_SCU_GetMirrorStatus(void) +{ + return(SCU_GENERAL->MIRRSTS); +} + +/** + * @param event The event for which the interrupt handler is to be configured. \n + * \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t for identifying the event. + * @param handler Name of the function to be executed when the event if detected. \n + * \b Range: The function accepts no arguments and returns no value. + * @return XMC_SCU_STATUS_t Status of configuring the event handler function for the selected event.\n + * \b Range: \a XMC_SCU_STATUS_OK if the event handler is successfully configured.\n + * \a XMC_SCU_STATUS_ERROR if the input event is invalid.\n + * \parDescription
+ * Assigns the event handler function to be executed on occurrence of the selected event.\n\n + * If the input event is valid, the handler function will be assigned to a table to be executed + * when the interrupt is generated and the event status is set in the event status register. By using this API, + * polling for a particular event can be avoided. This way the CPU utilization will be optimized. Multiple SCU events + * can generate a common interrupt. When the interrupt is generated, a common interrupt service routine is executed. + * It checks for status flags of events which can generate the interrupt. The handler function will be executed if the + * event flag is set. + * + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERUPT_GetEventStatus() \n\n\n + */ +XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t event, const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler); + +/** + * @param sr_num Service request number identifying the SCU interrupt generated.\n + * \b Range: 0 to 2. XMC4x devices have one common SCU interrupt, so the value should be 0.\n + * But XMC1x devices support 3 interrupt nodes. + * @return None + * \parDescription
+ * A common function to execute callback functions for multiple events.\n\n + * It checks for the status of events which can generate the interrupt with the selected service request. + * If the event is set, the corresponding callback function will be executed. It also clears the event status bit.\n + * \b Note: This is an internal function. It should not be called by the user application. + * + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n + */ +void XMC_SCU_IRQHandler(uint32_t sr_num); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* SCU_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_sdmmc.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_sdmmc.h new file mode 100644 index 00000000..0881a2f3 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_sdmmc.h @@ -0,0 +1,1656 @@ + +/** + * @file xmc_sdmmc.h + * @date 2017-02-14 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial version + * - Documentation updates + * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2016-01-16: + * - Added the following APIs to the XMC_SDMMC low level driver
+ * 1) XMC_SDMMC_EnableDelayCmdDatLines
+ * 2) XMC_SDMMC_DisableDelayCmdDatLines
+ * 3) XMC_SDMMC_SetDelay
+ * 4) XMC_SDMMC_EnableHighSpeed
+ * 5) XMC_SDMMC_DisableHighSpeed
+ * + * 2016-04-07: + * - Added XMC_SDMMC_COMMAND_RESPONSE_t
+ * + * 2016-07-11: + * - Adjust masks for the following functions:
+ * 1) XMC_SDMMC_SetBusVoltage
+ * 2) XMC_SDMMC_SetDataLineTimeout
+ * 3) XMC_SDMMC_SDClockFreqSelect
+ * + * 2017-02-14: + * - Added:
+ * 1) XMC_SDMMC_SetCardDetectionStatus()
+ * 2) XMC_SDMMC_SetCardDetectionSource()
+ + * @endcond + */ + +#ifndef XMC_SDMMC_H +#define XMC_SDMMC_H + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_common.h" + +#if defined (SDMMC) + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup SDMMC + * @brief Secure Digital/Multi Media Card (SDMMC) driver for the XMC4500 microcontroller + * + * The SDMMC peripheral provides an interface between SD/SDIO/MMC cards and the AHB. It handles + * the SD/SDIO protocol at transmission level. It automatically packs data and checks for CRC, + * start/end bits and format correctness. For SD cards, a maximum transfer rate of 24MB/sec is + * supported and for MMC cards, 48MB/sec. + * + * The peripheral can be used for applications that require large storage memory; e.g. Data logging, + * firmware updates or an embedded database. + * + * The SDMMC low level driver provides functions to configure and initialize the SDMMC hardware + * peripheral. + * @{ + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/** + * A convenient symbol for the SDMMC peripheral base address + */ +#if defined (SDMMC) +# define XMC_SDMMC ((XMC_SDMMC_t *)SDMMC_BASE) +#else +# error 'SDMMC' base peripheral pointer not defined +#endif + +/* + * Check for valid ACMD errors
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_MODULE_PTR(p) ((p) == XMC_SDMMC) + +/* + * Check for valid ACMD errors
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_ACMD_ERR(v)\ + ((v == XMC_SDMMC_ACMD12_NOT_EXEC_ERR) ||\ + (v == XMC_SDMMC_ACMD_TIMEOUT_ERR) ||\ + (v == XMC_SDMMC_ACMD_CRC_ERR) ||\ + (v == XMC_SDMMC_ACMD_END_BIT_ERR) ||\ + (v == XMC_SDMMC_ACMD_IND_ERR) ||\ + (v == XMC_SDMMC_CMD_NOT_ISSUED_BY_ACMD12_ERR)) + +/* + * Check for valid SDCLK divider frequency
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_SDCLK_FREQ(f)\ + ((f == XMC_SDMMC_CLK_DIV_1) ||\ + (f == XMC_SDMMC_CLK_DIV_2) ||\ + (f == XMC_SDMMC_CLK_DIV_4) ||\ + (f == XMC_SDMMC_CLK_DIV_8) ||\ + (f == XMC_SDMMC_CLK_DIV_16) ||\ + (f == XMC_SDMMC_CLK_DIV_32) ||\ + (f == XMC_SDMMC_CLK_DIV_64) ||\ + (f == XMC_SDMMC_CLK_DIV_128) ||\ + (f == XMC_SDMMC_CLK_DIV_256)) + +/* + * Check for valid bus voltage levels
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_BUS_VOLTAGE(v)\ + (v == XMC_SDMMC_BUS_VOLTAGE_3_3_VOLTS) + +/* + * Check for valid data timeout counter values
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_DAT_TIMEOUT_COUNTER(c)\ + ((c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_13) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_14) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_15) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_16) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_17) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_18) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_19) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_20) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_21) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_22) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_23) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_24) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_25) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_26) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_27)) + +/* + * Valid number of data lines
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_DATA_LINES(l)\ + ((l == XMC_SDMMC_DATA_LINES_1) ||\ + (l == XMC_SDMMC_DATA_LINES_4) ||\ + (l == XMC_SDMMC_DATA_LINES_8)) + +/* + * Check data transfer dir: Host to card and vice-versa
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_DATA_TRANSFER_DIR(d)\ + ((d == XMC_SDMMC_DATA_TRANSFER_HOST_TO_CARD) ||\ + (d == XMC_SDMMC_DATA_TRANSFER_CARD_TO_HOST)) + +/* + * Min and max number of delay elements
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_MIN_DELAY_ELEMENTS (0U) +#define XMC_SDMMC_MAX_DELAY_ELEMENTS (15U) + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * Number of data lines for SDMMC data transfer + */ +typedef enum +{ + XMC_SDMMC_DATA_LINES_1 = 0x00U, /**< Single data line mode */ + XMC_SDMMC_DATA_LINES_4 = 0x02U, /**< 4-bit mode */ + XMC_SDMMC_DATA_LINES_8 = 0x20U /**< SD 8-bit mode */ +} XMC_SDMMC_DATA_LINES_t; + +/** + * Valid SD clock frequency divider selection + */ +typedef enum +{ + XMC_SDMMC_CLK_DIV_1 = 0x00U, /**< Base clock (10 Mhz -> 63 Mhz) */ + XMC_SDMMC_CLK_DIV_2 = 0x01U, /**< Base clock divided by 2 */ + XMC_SDMMC_CLK_DIV_4 = 0x02U, /**< Base clock divided by 4 */ + XMC_SDMMC_CLK_DIV_8 = 0x04U, /**< Base clock divided by 8 */ + XMC_SDMMC_CLK_DIV_16 = 0x08U, /**< Base clock divided by 16 */ + XMC_SDMMC_CLK_DIV_32 = 0x10U, /**< Base clock divided by 32 */ + XMC_SDMMC_CLK_DIV_64 = 0x20U, /**< Base clock divided by 64 */ + XMC_SDMMC_CLK_DIV_128 = 0x40U, /**< Base clock divided by 128 */ + XMC_SDMMC_CLK_DIV_256 = 0x80U /**< Base clock divided by 256 */ +} XMC_SDMMC_SDCLK_FREQ_SEL_t; + +/** + * Status return values for the SDMMC low level driver + */ +typedef enum +{ + XMC_SDMMC_STATUS_SUCCESS = 0U, /**< Operation successful */ + XMC_SDMMC_STATUS_CMD_LINE_BUSY, /**< Command line busy */ + XMC_SDMMC_STATUS_DAT_LINE_BUSY /**< Data line busy */ +} XMC_SDMMC_STATUS_t; + +/** + * SDMMC events (Normal and error events) + */ +typedef enum +{ + XMC_SDMMC_CMD_COMPLETE = 0x01U, /**< Command complete event */ + XMC_SDMMC_TX_COMPLETE = 0x02U, /**< Transmit complete event */ + XMC_SDMMC_BLOCK_GAP_EVENT = 0x04U, /**< Block gap event */ + XMC_SDMMC_BUFFER_WRITE_READY = 0x10U, /**< Buffer write ready event */ + XMC_SDMMC_BUFFER_READ_READY = 0x20U, /**< Buffer read ready event */ + XMC_SDMMC_CARD_INS = 0x40U, /**< Card insert event */ + XMC_SDMMC_CARD_REMOVAL = 0x80U, /**< Card removal event */ + XMC_SDMMC_CARD_INT = 0x100U, /**< Card INT event */ + XMC_SDMMC_CARD_ERR = 0x8000U, /**< Card error interrupt */ + XMC_SDMMC_CMD_TIMEOUT_ERR = ((uint32_t)0x01 << 16U), /**< Command time-out error */ + XMC_SDMMC_CMD_CRC_ERR = ((uint32_t)0x02U << 16U), /**< Command CRC error */ + XMC_SDMMC_CMD_END_BIT_ERR = ((uint32_t)0x04U << 16U), /**< Command end bit error */ + XMC_SDMMC_CMD_IND_ERR = ((uint32_t)0x08U << 16U), /**< Command index error */ + XMC_SDMMC_DATA_TIMEOUT_ERR = ((uint32_t)0x10U << 16U), /**< Data time-out error */ + XMC_SDMMC_DATA_CRC_ERR = ((uint32_t)0x20U << 16U), /**< Data CRC error */ + XMC_SDMMC_DATA_END_BIT_ERR = ((uint32_t)0x40U << 16U), /**< Data end bit error */ + XMC_SDMMC_CURRENT_LIMIT_ERR = ((uint32_t)0x80U << 16U), /**< Current limit error */ + XMC_SDMMC_ACMD_ERR = ((uint32_t)0x100U << 16U), /**< ACMD error */ + XMC_SDMMC_TARGET_RESP_ERR = ((uint32_t)0x1000U << 16U) /**< Target response error */ +} XMC_SDMMC_EVENT_t; + +/** + * SDMMC wakeup events + */ +typedef enum +{ + XMC_SDMMC_WAKEUP_EN_CARD_INT = SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Msk, /**< Wakeup on card interrupt */ + XMC_SDMMC_WAKEUP_EN_CARD_INS = SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Msk, /**< Wakeup on SD card insertion */ + XMC_SDMMC_WAKEUP_EN_CARD_REM = SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Msk /**< Wakeup SD card removal */ +} XMC_SDMMC_WAKEUP_EVENT_t; + +/** + * SDMMC software reset modes + */ +typedef enum +{ + XMC_SDMMC_SW_RESET_ALL = SDMMC_SW_RESET_SW_RST_ALL_Msk, /**< Software reset all */ + XMC_SDMMC_SW_RST_CMD_LINE = SDMMC_SW_RESET_SW_RST_CMD_LINE_Msk, /**< Software reset command line */ + XMC_SDMMC_SW_RST_DAT_LINE = SDMMC_SW_RESET_SW_RST_DAT_LINE_Msk /**< Software reset data line */ +} XMC_SDMMC_SW_RESET_t; + +/** + * CMD12 response errors of Auto CMD12 + */ +typedef enum +{ + XMC_SDMMC_ACMD12_NOT_EXEC_ERR = SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Msk, /**< ACMD12 not executed error */ + XMC_SDMMC_ACMD_TIMEOUT_ERR = SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Msk, /**< ACMD timeout error */ + XMC_SDMMC_ACMD_CRC_ERR = SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Msk, /**< ACMD CRC error */ + XMC_SDMMC_ACMD_END_BIT_ERR = SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Msk, /**< ACMD end bit error */ + XMC_SDMMC_ACMD_IND_ERR = SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Msk, /**< ACMD IND error */ + XMC_SDMMC_CMD_NOT_ISSUED_BY_ACMD12_ERR = SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Msk /**< CMD not issued by ACMD12 */ +} XMC_SDMMC_ACMD_ERR_t; + +/** + * SDMMC response types + */ +typedef enum +{ + XMC_SDMMC_RESPONSE_TYPE_NO_RESPONSE = 0U, /**< No response */ + XMC_SDMMC_RESPONSE_TYPE_R1, /**< Response type: R1 */ + XMC_SDMMC_RESPONSE_TYPE_R1b, /**< Response type: R1b */ + XMC_SDMMC_RESPONSE_TYPE_R2, /**< Response type: R2 */ + XMC_SDMMC_RESPONSE_TYPE_R3, /**< Response type: R3 */ + XMC_SDMMC_RESPONSE_TYPE_R6, /**< Response type: R6 */ + XMC_SDMMC_RESPONSE_TYPE_R7 /**< Response type: R7 */ +} XMC_SDMMC_RESPONSE_TYPE_t; + +/** +* Command response selection +*/ +typedef enum XMC_SDMMC_COMMAND_RESPONSE +{ + XMC_SDMMC_COMMAND_RESPONSE_NONE = 0, /**< No Response */ + XMC_SDMMC_COMMAND_RESPONSE_LONG = 1, /**< Response length 136 */ + XMC_SDMMC_COMMAND_RESPONSE_SHORT = 2, /**< Response length 48 */ + XMC_SDMMC_COMMAND_RESPONSE_SHORT_BUSY = 3, /**< Response length 48 check Busy after response */ +} XMC_SDMMC_COMMAND_RESPONSE_t; + +/** + * Types of SDMMC commands + */ +typedef enum +{ + XMC_SDMMC_COMMAND_TYPE_NORMAL = 0U, /**< Command normal */ + XMC_SDMMC_COMMAND_TYPE_SUSPEND, /**< Command suspend */ + XMC_SDMMC_COMMAND_TYPE_RESUME, /**< Command resume */ + XMC_SDMMC_COMMAND_TYPE_ABORT /**< Command abort */ +} XMC_SDMMC_COMMAND_TYPE_t; + +/** + * SDMMC transfer modes + */ +typedef enum +{ + XMC_SDMMC_TRANSFER_MODE_TYPE_SINGLE = 0x00U, /**< Transfer mode type: single */ + XMC_SDMMC_TRANSFER_MODE_TYPE_INFINITE = 0x20U, /**< Transfer mode type: infinite */ + XMC_SDMMC_TRANSFER_MODE_TYPE_MULTIPLE = 0x22U, /**< Transfer mode type: multiple */ + XMC_SDMMC_TRANSFER_MODE_TYPE_STOP_MULTIPLE = 0x22U /**< Transfer mode type: multiple stop */ +} XMC_SDMMC_TRANSFER_MODE_TYPE_t; + +/** + * Auto command transfer modes + */ +typedef enum +{ + XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_DISABLED = 0x00U, /**< ACMD mode disabled */ + XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_12 /**< ACMD12 mode */ +} XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_t; + +/** + * SDMMC bus voltage level + */ +typedef enum +{ + XMC_SDMMC_BUS_VOLTAGE_3_3_VOLTS = 0x07U +} XMC_SDMMC_BUS_VOLTAGE_t; + +/** + * Data line timeout counter values + */ +typedef enum +{ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_13 = 0U, /** SDCLK * (2 ^ 13) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_14 = 1U, /** SDCLK * (2 ^ 14) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_15 = 2U, /** SDCLK * (2 ^ 15) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_16 = 3U, /** SDCLK * (2 ^ 16) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_17 = 4U, /** SDCLK * (2 ^ 17) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_18 = 5U, /** SDCLK * (2 ^ 18) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_19 = 6U, /** SDCLK * (2 ^ 19) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_20 = 7U, /** SDCLK * (2 ^ 20) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_21 = 8U, /** SDCLK * (2 ^ 21) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_22 = 9U, /** SDCLK * (2 ^ 22) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_23 = 10U, /** SDCLK * (2 ^ 23) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_24 = 11U, /** SDCLK * (2 ^ 24) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_25 = 12U, /** SDCLK * (2 ^ 25) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_26 = 13U, /** SDCLK * (2 ^ 26) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_27 = 14U, /** SDCLK * (2 ^ 27) */ +} XMC_SDMMC_DAT_TIMEOUT_COUNTER_t; + +/** + * SDMMC data transfer direction + */ +typedef enum +{ + XMC_SDMMC_DATA_TRANSFER_HOST_TO_CARD = 0U, /** Host to card */ + XMC_SDMMC_DATA_TRANSFER_CARD_TO_HOST /** Card to host */ +} XMC_SDMMC_DATA_TRANSFER_DIR_t; + +/** + * SDMMC card detection signal source + */ +typedef enum XMC_SDMMC_CD_SOURCE +{ + XMC_SDMMC_CD_SOURCE_PIN = 0, + XMC_SDMMC_CD_SOURCE_SW = 1 << SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos +} XMC_SDMMC_CD_SOURCE_t; + +/** + * SDMMC card detection status + */ +typedef enum XMC_SDMMC_CD_STATUS +{ + XMC_SDMMC_CD_STATUS_NO_CARD = 0, + XMC_SDMMC_CD_STATUS_INSERTED = 1 << SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos +} XMC_SDMMC_CD_STATUS_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ + +/** + * SDMMC device structure
+ * + * The structure represents a collection of all hardware registers used + * to configure the SDMMC peripheral on the XMC4500 microcontroller. The + * registers can be accessed with ::XMC_SDMMC. + */ +typedef struct +{ + __I uint32_t RESERVED0; + __IO uint16_t BLOCK_SIZE; + __IO uint16_t BLOCK_COUNT; + __IO uint32_t ARGUMENT1; + __IO uint16_t TRANSFER_MODE; + __IO uint16_t COMMAND; + __I uint32_t RESPONSE[4]; + __IO uint32_t DATA_BUFFER; + __I uint32_t PRESENT_STATE; + __IO uint8_t HOST_CTRL; + __IO uint8_t POWER_CTRL; + __IO uint8_t BLOCK_GAP_CTRL; + __IO uint8_t WAKEUP_CTRL; + __IO uint16_t CLOCK_CTRL; + __IO uint8_t TIMEOUT_CTRL; + __IO uint8_t SW_RESET; + __IO uint16_t INT_STATUS_NORM; + __IO uint16_t INT_STATUS_ERR; + __IO uint16_t EN_INT_STATUS_NORM; + __IO uint16_t EN_INT_STATUS_ERR; + __IO uint16_t EN_INT_SIGNAL_NORM; + __IO uint16_t EN_INT_SIGNAL_ERR; + __I uint16_t ACMD_ERR_STATUS; + __I uint16_t RESERVED1[9]; + __O uint16_t FORCE_EVENT_ACMD_ERR_STATUS; + __O uint16_t FORCE_EVENT_ERR_STATUS; + __I uint32_t RESERVED2[8]; + __O uint32_t DEBUG_SEL; + __I uint32_t RESERVED3[30]; + __IO uint32_t SPI; + __I uint32_t RESERVED4[2]; + __I uint16_t SLOT_INT_STATUS; +} XMC_SDMMC_t; + +/* Anonymous structure/union guard start */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__TASKING__) + #pragma warning 586 +#endif + +/** + * Present state of the SDMMC host controller
+ * + * The structure presents a convenient way to obtain the SDMMC peripheral's + * present state information (for example, the write protect pin level). The + * XMC_SDMMC_GetPresentState() API can be used to populate the structure + * with the state of the SD host controller. + */ +typedef union +{ + struct + { + uint32_t command_inihibit_cmd : 1; /**< Command: Inhibit command */ + uint32_t command_inihibit_dat : 1; /**< Command: Inhibit data */ + uint32_t dat_line_active : 1; /**< Data line active */ + uint32_t : 5; + uint32_t write_transfer_active : 1; /**< Write transfer active */ + uint32_t read_transfer_active : 1; /**< Read transfer active */ + uint32_t buffer_write_enable : 1; /**< Buffer write enable */ + uint32_t buffer_read_enable : 1; /**< Buffer read enable */ + uint32_t : 4; + uint32_t card_inserted : 1; /**< Card inserted */ + uint32_t card_state_stable : 1; /**< Card state stable */ + uint32_t card_detect_pin_level : 1; /**< Card detect pin level */ + uint32_t write_protect_pin_level : 1; /**< Write protect pin level */ + uint32_t dat_3_0_pin_level : 4; /**< Data 3_0 pin level */ + uint32_t cmd_line_level : 1; /**< Command line level */ + uint32_t dat7_4_pin_level : 4; /**< Data 7_4 pin level */ + uint32_t : 3; + }; + uint32_t b32; +} XMC_SDMMC_PRESENT_STATE_t; + +/** + * SDMMC transfer mode configuration + */ +typedef struct +{ + uint32_t block_size; + uint32_t num_blocks; + XMC_SDMMC_TRANSFER_MODE_TYPE_t type; + XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_t auto_cmd; + XMC_SDMMC_DATA_TRANSFER_DIR_t direction; +} XMC_SDMMC_TRANSFER_MODE_t; + +/** + * Represent an SDMMC command
+ * + * The structure holds the configuration for an SDMMC command. The SDMMC + * COMMAND register is a 16-bit register which is responsible for enabling + * configuration parameters like command type, response type, index check + * enable (and a few more). Once SDMMC.COMMAND is configured, the + * XMC_SDMMC_SendCommand() function can be used to send the command. + */ +typedef union +{ + struct + { + uint16_t response_type_sel : 2; /**< Response type select ::XMC_SDMMC_COMMAND_RESPONSE_t */ + uint16_t : 1; + uint16_t crc_check_en : 1; /**< Command CRC check enable */ + uint16_t index_check_en : 1; /**< Command index check enable */ + uint16_t dat_present_sel : 1; /**< Data present select */ + uint16_t cmd_type : 2; /**< Command type ::XMC_SDMMC_COMMAND_TYPE_t */ + uint16_t cmd_index : 6; /**< Command index */ + uint16_t : 2; + }; + uint16_t cmd; +} XMC_SDMMC_COMMAND_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__TASKING__) + #pragma warning restore +#endif + +/** + * Card response structure + */ +typedef struct +{ + uint32_t response_0; + uint32_t response_2; + uint32_t response_4; + uint32_t response_6; +} XMC_SDMMC_RESPONSE_t; + +/** + * SDMMC configuration data structure
+ * + * The structure is used to configure the bus width and the clock divider. + */ +typedef struct +{ + uint8_t bus_width; /**< SDMMC bus width */ + XMC_SDMMC_SDCLK_FREQ_SEL_t clock_divider; /**< SDMMC clock divider */ +} XMC_SDMMC_CONFIG_t; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool + * + * \parDescription:
+ * Get power status of the SDMMC peripheral
+ * + * \par + * The function checks the SD_BUS_POWER bit-field of the POWER_CTRL register and returns + * a boolean value - "on" or "off". + */ +bool XMC_SDMMC_GetPowerStatus(XMC_SDMMC_t *const sdmmc); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Enable SDMMC peripheral
+ * + * \par + * The function de-asserts the peripheral reset. The peripheral needs to be initialized. + */ +void XMC_SDMMC_Enable(XMC_SDMMC_t *const sdmmc); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Disable SDMMC peripheral
+ * + * \par + * The function asserts the peripheral reset. + */ +void XMC_SDMMC_Disable(XMC_SDMMC_t *const sdmmc); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param config A pointer to a constant XMC_SDMMC_CONFIG_t structure containing the + * bus width and clock divider configuration + * @return ::XMC_SDMMC_STATUS_SUCCESS + * + * \parDescription:
+ * Initialize the SDMMC peripheral
+ * + * \par + * The function enables the SDMMC peripheral, sets the internal clock divider register + * and sets the bus width. + */ +XMC_SDMMC_STATUS_t XMC_SDMMC_Init(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_CONFIG_t *config); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Enable SDMMC normal and error event(s)
+ * + * \par + * The function first sets the bit-fields of EN_INT_STATUS_NORM and EN_INT_STATUS_ERR + * registers to enable interrupt status for requested normal/error SDMMC events. It then + * sets the bit-fields of EN_INT_SIGNAL_NORM and EN_INT_SIGNAL_ERR to enable the + * interrupt generation for the requested events. + */ +void XMC_SDMMC_EnableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Disable normal and error SDMMC event(s)
+ * + * \par + * The function disables the interrupt generation for the requested events by clearing + * the bit-fields of EN_INT_SIGNAL_NORM and EN_INT_SIGNAL_ERR registers. + * + * \parNote:
+ * The XMC_SDMMC_DisableEvent() function doesn't reset the the interrupt status. One + * may still use XMC_SDMMC_GetEvent() to check the status of requested events even if + * the interrupt generation is already disabled. + */ +void XMC_SDMMC_DisableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Clear SDMMC event(s)
+ * + * \par + * The function clears requested normal/error events by settings the bit-fields of + * the INT_STATUS register. Please check SDMMC_INT_STATUS_NORM in the XMC45000 + * manual for more details. + */ +void XMC_SDMMC_ClearEvent(XMC_SDMMC_t *const sdmmc, uint32_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) + * @return bool + * + * \parDescription:
+ * Get SDMMC event status
+ * + * \par + * The function returns the status of a single requested (normal/error) event by + * reading the appropriate bit-fields of the INT_STATUS register. + */ +bool XMC_SDMMC_GetEvent(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_EVENT_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Enable event status
+ * + * \par + * The function sets the bit-fields of EN_INT_STATUS_NORM and EN_INT_STATUS_ERR + * registers to enable interrupt status for requested normal/error SDMMC events. + */ +void XMC_SDMMC_EnableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Disable event status
+ * + * \par + * The function resets the bit-fields of EN_INT_STATUS_NORM and EN_INT_STATUS_ERR + * registers to disable interrupt status for requested normal/error SDMMC events. + */ +void XMC_SDMMC_DisableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (::XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Trigger SDMMC error events
+ * + * \par + * The SDMMC peripheral supports triggering of following error events:
+ * + * ::XMC_SDMMC_CMD_TIMEOUT_ERR, ::XMC_SDMMC_CMD_CRC_ERR, ::XMC_SDMMC_CMD_END_BIT_ERR, + * ::XMC_SDMMC_CMD_IND_ERR, ::XMC_SDMMC_DATA_TIMEOUT_ERR, ::XMC_SDMMC_DATA_CRC_ERR, + * ::XMC_SDMMC_DATA_END_BIT_ERR, ::XMC_SDMMC_CURRENT_LIMIT_ERR, ::XMC_SDMMC_ACMD_ERR, + * ::XMC_SDMMC_TARGET_RESP_ERR + * + * For triggering Auto CMD12 error, see XMC_SDMMC_TriggerACMDErr() + */ +__STATIC_INLINE void XMC_SDMMC_TriggerEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_TriggerEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->FORCE_EVENT_ERR_STATUS |= (uint16_t)(event >> 16U); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param source A valid SDMMC card detection signal source (::XMC_SDMMC_CD_SOURCE_t) + * @return None + * + * \parDescription:
+ * Selects source for card detection + */ +__STATIC_INLINE void XMC_SDMMC_SetCardDetectionSource(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_CD_SOURCE_t source) +{ + XMC_ASSERT("XMC_SDMMC_TriggerEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->HOST_CTRL |= (sdmmc->HOST_CTRL & (uint32_t)~SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Msk) | source; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param status A valid SDMMC card detection status (::XMC_SDMMC_CD_STATUS_t) + * @return None + * + * \parDescription:
+ * Sets the card detection status indicating whether card is inserted or not. + * Generates (card ins or card removal) interrupt when the normal interrupt is enabled. + * @note Only valid if SDMMC card detection signal source is set to XMC_SDMMC_CD_SOURCE_SW
+ * + */ +__STATIC_INLINE void XMC_SDMMC_SetCardDetectionStatus(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_CD_STATUS_t status) +{ + XMC_ASSERT("XMC_SDMMC_TriggerEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->HOST_CTRL |= (sdmmc->HOST_CTRL & (uint32_t)~SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Msk) | status; +} + + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool + * + * \parDescription:
+ * Check if any error event has occured
+ * + * \par + * The function can typically be used for writing an error interrupt recovery routine. + * Should any error be indicated (If XMC_SDMMC_IsAnyErrorEvent() returns true), the + * routine may then clear the event after indicating the error event and reset the + * SDMMC command and data lines. + */ +__STATIC_INLINE bool XMC_SDMMC_IsAnyErrorEvent(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_IsAnyErrorEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (bool)(sdmmc->INT_STATUS_ERR); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC wakeup event (::XMC_SDMMC_WAKEUP_EVENT_t) or a valid combination + * of logically OR'd wakeup events + * @return None + * + * \parDescription:
+ * Enable wakeup event(s)
+ * + * \par + * The function enables SDMMC wakeup events by setting appropriate bit-fields of the WAKEUP_CTRL + * register.
+ * + * List of supported wakeup events -> Wakeup on:
+ * 1) Card interrupt
+ * 2) SD card insertion
+ * 3) SD card removal
+ */ +__STATIC_INLINE void XMC_SDMMC_EnableWakeupEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_EnableWakeupEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->WAKEUP_CTRL |= (uint8_t)event; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC wakeup event (::XMC_SDMMC_WAKEUP_EVENT_t) or a valid combination + * of logically OR'd wakeup events + * @return None + * + * \parDescription:
+ * Disable wakeup event(s)
+ * + * \par + * The function disables SDMMC wakeup events by clearing appropriate bit-fields of the WAKEUP_CTRL + * register.
+ * + * List of supported wakeup events -> Wakeup on:
+ * 1) Card interrupt
+ * 2) SD card insertion
+ * 3) SD card removal
+ */ +__STATIC_INLINE void XMC_SDMMC_DisableWakeupEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_DisableWakeupEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->WAKEUP_CTRL &= (uint8_t)~event; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param error A valid SDMMC ACMD error (::XMC_SDMMC_ACMD_ERR_t) + * @return bool + * + * \parDescription:
+ * Get status of Auto CMD12 errors
+ * + * \par + * The function detects the presence of an Auto CMD12 error. A boolean is returned to + * indicate if an error is detected. + */ +__STATIC_INLINE bool XMC_SDMMC_GetACMDErrStatus(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_ACMD_ERR_t error) +{ + XMC_ASSERT("XMC_SDMMC_GetACMDErrStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_GetACMDErrStatus: Invalid ACMD response error", XMC_SDMMC_CHECK_ACMD_ERR(error)); + + return (bool)(sdmmc->ACMD_ERR_STATUS & (uint16_t)error); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param error A valid SDMMC ACMD error (::XMC_SDMMC_ACMD_ERR_t) or a valid combination + * of logically OR'd ACMD error events + * @return None + * + * \parDescription:
+ * Triggers Auto CMD12 error(s)
+ * + * \par + * This function triggers Auto CMD12 error(s) by setting appropriate bit-fields of the + * FORCE_EVENT_ACMD_ERR_STATUS register. + * + * \parRelated APIs:
+ * XMC_SDMMC_TriggerEvent() + */ +__STATIC_INLINE void XMC_SDMMC_TriggerACMDErr(XMC_SDMMC_t *const sdmmc, uint32_t error) +{ + XMC_ASSERT("XMC_SDMMC_TriggerACMDErr: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->FORCE_EVENT_ACMD_ERR_STATUS |= (uint16_t)error; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return uint32_t The value held in the SDMMC FIFO + * + * \parDescription:
+ * Use this function to read a single word (32 bits) from the SDMMC FIFO.
+ */ +__STATIC_INLINE uint32_t XMC_SDMMC_ReadFIFO(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_ReadFIFO: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (sdmmc->DATA_BUFFER); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param data Pointer to a data word (32 bits) that needs to be written to the FIFO + * @return None + * + * \parDescription:
+ * Use this function to write a single word (32 bits) to the SDMMC FIFO.
+ */ +__STATIC_INLINE void XMC_SDMMC_WriteFIFO(XMC_SDMMC_t *const sdmmc, uint32_t *data) +{ + XMC_ASSERT("XMC_SDMMC_WriteFIFO: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->DATA_BUFFER = *data; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Enable SDMMC bus power
+ * + * \par + * The function sets the SD_BUS_POWER bit-field in the POWER_CTRL register, enabling the + * bus power. It may be invoked after enabling the SD clock (XMC_SDMMC_SDClockEnable()). + */ +__STATIC_INLINE void XMC_SDMMC_BusPowerOn(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_BusPowerOn: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->POWER_CTRL |= (uint8_t)(SDMMC_POWER_CTRL_SD_BUS_POWER_Msk); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Disable SDMMC bus power
+ * + * \par + * The function resets the SD_BUS_POWER bit-field in the POWER_CTRL register, disabling the + * bus power. + */ +__STATIC_INLINE void XMC_SDMMC_BusPowerOff(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_BusPowerOff: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->POWER_CTRL &= (uint8_t)~SDMMC_POWER_CTRL_SD_BUS_POWER_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Enable the internal SDMMC clock
+ * + * \par + * The function enables the internal clock of the SDMMC peripheral. To check if the + * clock is stable, use XMC_SDMMC_GetClockStability(). + * + * \parNote:
+ * Invoke XMC_SDMMC_Init() before using this function. + */ +__STATIC_INLINE void XMC_SDMMC_Start(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_Start: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + /* Enable internal clock */ + sdmmc->CLOCK_CTRL |= (uint16_t)SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool + * + * \parDescription:
+ * Check internal clock stability
+ * + * \par + * Use this function to check the internal SDMMC clock stability. The function returns a + * boolean value indicating internal clock stability (true = stable) + */ +__STATIC_INLINE bool XMC_SDMMC_GetClockStability(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetClockStability: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + /* Return clock stability */ + return (bool)(sdmmc->CLOCK_CTRL & SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Msk); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Disable internal SDMMC clock
+ * + * \par + * The function disables the internal clock of the SDMMC peripheral. The SDMMC registers + * can still be read and written even if the internal clock is disabled. + */ +__STATIC_INLINE void XMC_SDMMC_Stop(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_Stop: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->CLOCK_CTRL &= (uint16_t)~SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Enable the SD clock
+ * + * \par + * The function sets the SDCLOCK_EN bit-field of the CLOCK_CTRL register, enabling the + * SD clock. It can be invoked after the internal clock has achieved stability. SD card + * initialization process may then follow. + */ +__STATIC_INLINE void XMC_SDMMC_SDClockEnable(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_SDClockEnable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->CLOCK_CTRL |= (uint16_t)SDMMC_CLOCK_CTRL_SDCLOCK_EN_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Disable the SD clock
+ * + * \par + * The function resets the SDCLOCK_EN bit-field of the CLOCK_CTRL register, disabling the + * SD clock. It can be used alongside a SD card information reset routine (if required). + */ +__STATIC_INLINE void XMC_SDMMC_SDClockDisable(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_SDClockDisable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->CLOCK_CTRL &= (uint16_t)~SDMMC_CLOCK_CTRL_SDCLOCK_EN_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param reset_mode Reset mode or a bitwise combination of modes + * @return None + * + * \parDescription:
+ * Set SDMMC software reset request
+ * + * \par + * The function sets in the SDMMC SW_RESET register:
+ * 1) bit 0 to reset all
+ * 2) bit 1 to reset CMD line
+ * 3) bit 2 reset DAT line
+ * + * It is typically used to reset the SD HOST controller's registers. + */ +__STATIC_INLINE void XMC_SDMMC_SetSWReset(XMC_SDMMC_t *const sdmmc, uint32_t reset_mode) +{ + XMC_ASSERT("XMC_SDMMC_SetSWReset: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->SW_RESET |= (uint8_t)reset_mode; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return Software reset status + * + * \parDescription:
+ * Get SDMMC software reset status
+ * + * \par + * The SD host takes some time to reset its registers after invoking XMC_SDMMC_SetSWReset(). + * Since XMC_SDMMC_SetSWReset() is a non-blocking function, XMC_SDMMC_GetSWResetStatus() has + * been provided to check the software reset status. The return value needs to be masked + * with the reset mode (XMC_SDMMC_SW_RESET_t) to get a specific software reset status value. + */ +__STATIC_INLINE uint32_t XMC_SDMMC_GetSWResetStatus(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetSWResetStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (uint32_t)(sdmmc->SW_RESET); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return XMC_SDMMC_PRESENT_STATE_t A structure storing the present state of the host controller + * + * \parDescription:
+ * Get the present state of the SDMMC host controller
+ * + * \par + * Get the values of each bit-field in SDMMC_PRESENT_STATE register + * The function call populates an instance of the XMC_SDMMC_PRESENT_STATE_t structure with + * the state of the SD host controller and returns it to the caller. + */ +__STATIC_INLINE XMC_SDMMC_PRESENT_STATE_t XMC_SDMMC_GetPresentState(const XMC_SDMMC_t *const sdmmc) +{ + XMC_SDMMC_PRESENT_STATE_t result; + + XMC_ASSERT("XMC_SDMMC_GetPresentState: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + result.b32 = (uint32_t)sdmmc->PRESENT_STATE; + + return result; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool SDMMC command line status + * + * \parDescription:
+ * Check if the command line is busy
+ * + * \par + * The function reads the SDMMC PRESENT_STATE register and returns "true" if the command + * line is busy ("false" otherwise). The command line must be free before sending an SDMMC + * command with XMC_SDMMC_SendCommand(). + */ +__STATIC_INLINE bool XMC_SDMMC_IsCommandLineBusy(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_IsCommandLineBusy: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (bool)(sdmmc->PRESENT_STATE & SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Msk); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool SDMMC data line status + * + * \parDescription:
+ * Check if the data line is busy
+ * + * \par + * The function reads the SDMMC PRESENT_STATE register and returns "true" if the data + * line is busy ("false" otherwise). The data line must be free before sending an SDMMC + * command with XMC_SDMMC_SendCommand(). + */ +__STATIC_INLINE bool XMC_SDMMC_IsDataLineBusy(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_IsDataLineBusy: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (bool)(sdmmc->PRESENT_STATE & SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Msk); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool Status of all data lines + * + * \parDescription:
+ * Check if all data line are high
+ * + * \par + * The function reads the SDMMC PRESENT_STATE register and returns "true" if all data + * lines are high. It can be used to handle SDMMC error conditions. For example, if an + * error event (XMC_SDMMC_IsAnyErrorEvent()) is detected and all data lines are high, + * the user code can conclude that the error is of a "recoverable" type. + */ +__STATIC_INLINE bool XMC_SDMMC_IsAllDataLinesHigh(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_IsAllDataLinesHigh: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return ((((sdmmc->PRESENT_STATE & SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Msk) >> + SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos) == 0x0FU) ? true : false); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param command A pointer to a constant of type XMC_SDMMC_COMMAND_t, pointing to the command configuration + * @param arg Command argument + * @return ::XMC_SDMMC_STATUS_SUCCESS + * + * \parDescription:
+ * Send normal SDMMC command
+ * + * \par + * Use this function to send a normal SDMMC command. This non-blocking function sets the + * ARGUMENT1 and COMMAND registers. It is the user's responsibility to check if the command + * and data lines are busy (XMC_SDMMC_IsDataLineBusy(), XMC_SDMMC_IsCommandLineBusy()). + */ +XMC_SDMMC_STATUS_t XMC_SDMMC_SendCommand(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_COMMAND_t *command, uint32_t arg); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return uint32_t SDMMC command response + * + * \parDescription:
+ * Get card response (no Auto command)
+ * + * \par + * This function returns [39:8] bits of the card response. The others are checked automatically + * by the peripheral. This function can be used with response type R1, R1b, R3, R4, R5, R5b, R6 + * but it doesn't support the retrieving of R1 of Auto CMD 23 and R1b of Auto CMD 12. To get + * these responses, use XMC_SDMMC_GetAutoCommandResponse(). + */ +__STATIC_INLINE uint32_t XMC_SDMMC_GetCommandResponse(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetCommandResponse: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (sdmmc->RESPONSE[0]); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return uint32_t Auto command response value + * + * \parDescription:
+ * Get card response of Auto commands
+ * + * \par + * This function returns card response [39:8] bits of auto commands: R1 of Auto CMD 23 and + * R1b of Auto CMD 12. + */ +__STATIC_INLINE uint32_t XMC_SDMMC_GetAutoCommandResponse(const XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetAutoCommandResponse: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (sdmmc->RESPONSE[3]); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param response Pointer to structure type XMC_SDMMC_RESPONSE_t to store the full response + * @return None + * + * \parDescription:
+ * Get card R2 response
+ * + * \par + * The R2 response is 120 bits wide. The function reads all peripheral registers and store in + * the response data structure. + */ +void XMC_SDMMC_GetR2Response(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_RESPONSE_t *const response); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param transfer_mode Transfer mode configuration + * @return None + * + * \parDescription:
+ * Configure data transfer mode
+ * + * \par + * The function configures block size, block count, type of data transfer, response type + * and sets the auto command configuration. Use this function to configure a multi-block + * SDMMC transfer. + */ +void XMC_SDMMC_SetDataTransferMode(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_TRANSFER_MODE_t *const transfer_mode); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return uint32_t Number of blocks that need to be transferred + * + * \parDescription:
+ * Get the number of blocks that need to be transferred
+ * + * \par + * This function is valid only for multiple block transfers. The host controller + * decrements the block count after each block transfer and stops when the count reaches + * zero. It can only be accessed when no transaction is happening (i.e after a transaction + * has stopped). This function returns an invalid value during the transfer.
+ * + * When saving transfer context as a result of the suspend command, the number of blocks + * yet to be transferred can be determined by using this function. + */ +__STATIC_INLINE uint32_t XMC_SDMMC_GetTransferBlocksNum(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetTransferBlocksNum: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (uint32_t)(sdmmc->BLOCK_COUNT); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param enabled "true" to enable read wait control, "false" to disable read wait control. + * @return None + * + * \parDescription:
+ * Configure read wait control
+ * + * \par + * The read wait function is optional for SDIO cards. If the card supports read wait and + * XMC_SDMMC_GetTransferBlocksNum() is executed, the SDMMC peripheral will stop read data + * using DAT[2] line. If this feature is not enabled the peripheral has to stop the SD + * clock to hold read data, restricting commands generation.
+ * + * When the host driver detects an SD card insertion, it sets this bit according to the + * CCCR of the SDIO card. If the card does not support read wait, this feature shall + * never be enabled otherwise a DAT line conflict may occur. If this feature is disabled, + * Suspend/Resume cannot be supported. + */ +__STATIC_INLINE void XMC_SDMMC_SetReadWaitControl(XMC_SDMMC_t *const sdmmc, bool enabled) +{ + XMC_ASSERT("XMC_SDMMC_SetReadWaitControl: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->BLOCK_GAP_CTRL = (uint8_t)((sdmmc->BLOCK_GAP_CTRL & (uint8_t)~SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Msk) | + (uint8_t)((uint8_t)enabled << SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param enabled "true" to set stop at block gap, "false" for transfer + * @return None + * + * \parDescription:
+ * Stop at block gap request
+ * + * \par + * The function is used to terminate a transaction execution at the next block gap for + * non-DMA transfers. + */ +__STATIC_INLINE void XMC_SDMMC_SetStopAtBlockGap(XMC_SDMMC_t *const sdmmc, bool enabled) +{ + XMC_ASSERT("XMC_SDMMC_SetStopAtBlockGap: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->BLOCK_GAP_CTRL = (uint8_t)((sdmmc->BLOCK_GAP_CTRL & (uint8_t)~SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Msk) | + (uint8_t)((uint8_t)enabled << SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param enabled "true" to restart transaction, "false" is ignored + * @return None + * + * \parDescription:
+ * Issue a continue request
+ * + * \par + * The function is used to restart a transaction which was stopped using the "Stop at + * block gap" request. (XMC_SDMMC_SetStopAtBlockGap()) + */ +__STATIC_INLINE void XMC_SDMMC_SetContinueRequest(XMC_SDMMC_t *const sdmmc, bool enabled) +{ + XMC_ASSERT("XMC_SDMMC_SetContinueRequest: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->BLOCK_GAP_CTRL = ((sdmmc->BLOCK_GAP_CTRL & (uint8_t)~SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Msk) | + (uint8_t)((uint8_t)enabled << SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool + * + * \parDescription:
+ * Get continue request
+ * + * \par + * The function returns the status of the BLOCK_GAP_CTRL.CONTINUE_REQ bit-field. It + * returns "true" if the transaction is restarted after a "stop at block gap" request. + */ +__STATIC_INLINE bool XMC_SDMMC_GetContinueRequest(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetContinueRequest: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (bool)(sdmmc->BLOCK_GAP_CTRL & (uint8_t)(1U << SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param config A pointer to the SDMMC configuration structure (::XMC_SDMMC_CONFIG_t) + * @return None + * + * \parDescription:
+ * Enable interrupt at block gap
+ * + * \par + * The function sets the BLOCK_GAP_CTRL.INT_AT_BLOCK_GAP bit-field to enable interrupt + * at block gap for a multi-block transfer. This bit is only valid in a 4-bit mode of + * the SDIO card. + */ +__STATIC_INLINE void XMC_SDMMC_EnableInterruptAtBlockGap(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_CONFIG_t *config) +{ + XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: This operation is only valid in 4-bit mode", + (config->bus_width == XMC_SDMMC_DATA_LINES_1)); + + sdmmc->BLOCK_GAP_CTRL |= (uint8_t)SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param config A pointer to the SDMMC configuration structure (::XMC_SDMMC_CONFIG_t) + * @return None + * + * \parDescription:
+ * Disable interrupt at block gap
+ * + * \par + * The function resets the BLOCK_GAP_CTRL.INT_AT_BLOCK_GAP bit-field to disable interrupt + * at block gap. This bit is only valid in a 4-bit mode of the SDIO card. + */ +__STATIC_INLINE void XMC_SDMMC_DisableInterruptAtBlockGap(XMC_SDMMC_t *const sdmmc, + const XMC_SDMMC_CONFIG_t *config) + +{ + XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: This operation is only valid in 4-bit mode", + (config->bus_width == XMC_SDMMC_DATA_LINES_1)); + + sdmmc->BLOCK_GAP_CTRL &= (uint8_t)~SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param clk Desired clock frequency (::XMC_SDMMC_SDCLK_FREQ_SEL_t) + * @return None + * + * \parDescription:
+ * Set SD clock frequency
+ * + * \par + * The function sets the CLOCK_CTRL register to configure the frequency of the SD clock + * pin. The register is programmed with the divisor of the base clock frequency (clk). + * + * The following settings are permitted (8-bit divided clock mode):
+ * 00H: base clock (10MHz->63MHz)
+ * 01H: base clock divided by 2
+ * 10H: base clock divided by 32
+ * 02H: base clock divided by 4
+ * 04H: base clock divided by 8
+ * 08H: base clock divided by 16
+ * 20H: base clock divided by 64
+ * 40H: base clock divided by 128
+ * 80H: base clock divided by 256
+ * + * \parNote:
+ * The internal clock should be disabled before updating frequency clock select. Please + * see section 2.2.14 -> "Clock Control Register" in the SD HOST specification for more + * information. + */ +__STATIC_INLINE void XMC_SDMMC_SDClockFreqSelect(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_SDCLK_FREQ_SEL_t clk) +{ + XMC_ASSERT("XMC_SDMMC_SDClockFreqSelect: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SDClockFreqSelect: Invalid clock frequency selection", XMC_SDMMC_CHECK_SDCLK_FREQ(clk)); + + sdmmc->CLOCK_CTRL = (uint16_t)((sdmmc->CLOCK_CTRL & (uint32_t)~SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Msk) | + (uint32_t)(clk << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param bus_voltage Desired bus voltage (::XMC_SDMMC_BUS_VOLTAGE_t) + * @return None + * + * \parDescription:
+ * Set SDMMC bus voltage
+ * + * \par + * The function sets the CLOCK_CTRL register to configure the bus voltage. Currently, + * 3.3 volts is the supported voltage level. This function is relevant within the host + * controller initialization routine. + */ +__STATIC_INLINE void XMC_SDMMC_SetBusVoltage(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_BUS_VOLTAGE_t bus_voltage) +{ + XMC_ASSERT("XMC_SDMMC_SetBusVoltage: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetBusVoltage: Invalid bus voltage", XMC_SDMMC_CHECK_BUS_VOLTAGE(bus_voltage)); + + sdmmc->POWER_CTRL = (uint8_t)((sdmmc->POWER_CTRL & (uint32_t)~SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Msk) | + (uint32_t)(bus_voltage << SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param timeout Data line timeout value + * @return None + * + * \parDescription:
+ * Set data line timeout
+ * + * \par + * Use the function to set the interval by which the data line timeouts are detected. The + * timeout clock frequency is generated by dividing the SD clock (TMCLK) by the timeout argument. + * This function must be called before setting the bus voltage (XMC_SDMMC_SetBusVoltage()). + */ +__STATIC_INLINE void XMC_SDMMC_SetDataLineTimeout(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_DAT_TIMEOUT_COUNTER_t timeout) +{ + XMC_ASSERT("XMC_SDMMC_SetDataLineTimeout: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetDataLineTimeout: Invalid timeout", XMC_SDMMC_CHECK_DAT_TIMEOUT_COUNTER(timeout)); + + sdmmc->TIMEOUT_CTRL = (uint8_t)((sdmmc->TIMEOUT_CTRL & (uint32_t)~SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Msk) | + (uint32_t)(timeout << SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param lines Number of data lines to use (::XMC_SDMMC_DATA_LINES_t) + * @return None + * + * \parDescription:
+ * Set data transfer width
+ * + * \par + * Use the function to set the data transfer width. Before using this function, an ACMD6 + * command (with R1 response type) must be sent to switch the bus width. + */ +__STATIC_INLINE void XMC_SDMMC_SetDataTransferWidth(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_DATA_LINES_t lines) +{ + XMC_ASSERT("XMC_SDMMC_SetDataTransferWidth: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetDataTransferWidth: Invalid no. of data lines", XMC_SDMMC_CHECK_DATA_LINES(lines)); + + sdmmc->HOST_CTRL &= (uint8_t)~(XMC_SDMMC_DATA_LINES_1 | XMC_SDMMC_DATA_LINES_4 | XMC_SDMMC_DATA_LINES_8); + sdmmc->HOST_CTRL |= (uint8_t)lines; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param dir Transfer direction (::XMC_SDMMC_DATA_TRANSFER_DIR_t) + * @return None + * + * \parDescription:
+ * Set data transfer direction
+ * + * \par + * Use the function to set the data transfer direction: host to card OR card to host. It + * is typically used to configure block operations (read/write) on the SD card. For + * example, XMC_SDMMC_DATA_TRANSFER_HOST_TO_CARD must be used for a write block operation. + */ +__STATIC_INLINE void XMC_SDMMC_SetDataTransferDirection(XMC_SDMMC_t *const sdmmc, + XMC_SDMMC_DATA_TRANSFER_DIR_t dir) +{ + XMC_ASSERT("XMC_SDMMC_SetDataTransferDirection: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetDataTransferDirection: Invalid direction", XMC_SDMMC_CHECK_DATA_TRANSFER_DIR(dir)); + + sdmmc->TRANSFER_MODE = (uint16_t)((sdmmc->TRANSFER_MODE & (uint16_t)~SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Msk) | + (uint16_t)((uint16_t)dir << SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos)); +} + +/** + * @param None + * @return None + * + * \parDescription:
+ * Enable delay on the command/data out lines
+ * + * \par + * Use the function to enable delay on the command/data out lines. Invoke this function + * before selecting the number of delay elements. + */ +__STATIC_INLINE void XMC_SDMMC_EnableDelayCmdDatLines(void) +{ + SCU_GENERAL->SDMMCDEL |= (uint32_t)SCU_GENERAL_SDMMCDEL_TAPEN_Msk; +} + +/** + * @param None + * @return None + * + * \parDescription:
+ * Disable delay on the command/data out lines
+ * + * \par + * Use the function to disable delay on the command/data out lines. + */ +__STATIC_INLINE void XMC_SDMMC_DisableDelayCmdDatLines(void) +{ + SCU_GENERAL->SDMMCDEL &= (uint32_t)~SCU_GENERAL_SDMMCDEL_TAPEN_Msk; +} + +/** + * @param tapdel Number of delay elements to select + * @return None + * + * \parDescription:
+ * Set number of delay elements on the command/data out lines
+ * + * \par + * Use the function to set the number of delay elements on the command/data out lines. + * The function writes the delay value to the SDMMC delay control register (SDMMCDEL) + * within the realm of the SCU peripheral. A delay of tapdel + 1 is considered as the + * final selected number of delay elements. + */ +__STATIC_INLINE void XMC_SDMMC_SetDelay(uint8_t tapdel) +{ + SCU_GENERAL->SDMMCDEL = (uint32_t)((SCU_GENERAL->SDMMCDEL & (uint32_t)~SCU_GENERAL_SDMMCDEL_TAPDEL_Msk) | + (uint32_t)(tapdel << SCU_GENERAL_SDMMCDEL_TAPDEL_Pos)); +} + +/** + * @param None + * @return None + * + * \parDescription:
+ * High speed enable
+ * + * \par + * Use the function to enable high speed operation. The default is a normal speed operation. + * Once enabled, the host controller outputs command and data lines at the rising edge of the + * SD clock (up to 50 MHz for SD). + */ +__STATIC_INLINE void XMC_SDMMC_EnableHighSpeed(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_EnableHighSpeed: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->HOST_CTRL |= (uint8_t)SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk; +} + +/** + * @param None + * @return None + * + * \parDescription:
+ * High speed disable
+ * + * \par + * Use the function to disable high speed operation. The host controller will switch back + * to a normal speed mode. In this mode, the host controller outputs command and data lines + * at 25 MHz for SD. + */ +__STATIC_INLINE void XMC_SDMMC_DisableHighSpeed(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_DisableHighSpeed: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->HOST_CTRL &= (uint8_t)~SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* #if defined (SDMMC) */ + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_spi.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_spi.h new file mode 100644 index 00000000..ec1de7e8 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_spi.h @@ -0,0 +1,1279 @@ +/** + * @file xmc_spi.h + * @date 2016-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial + * + * 2015-05-20: + * - Documentation improved
+ * - Added XMC_SPI_CH_SetSlaveSelectDelay(), XMC_SPI_CH_TriggerServiceRequest() and + * XMC_SPI_CH_SelectInterruptNodePointer()
+ * - Added XMC_SPI_CH_SetInterwordDelaySCLK()
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-08-24: + * - Added APIs for enabling/disabling delay compensation XMC_SPI_CH_DisableDelayCompensation() and + * XMC_SPI_CH_EnableDelayCompensation()
+ * + * 2015-08-27: + * - Added APIs for external input for BRG configuration:XMC_SPI_CH_ConfigExternalInputSignalToBRG()
+ * + * 2015-09-01: + * - Modified XMC_SPI_CH_SetInputSource() for avoiding complete DXCR register overwriting.
+ * - Modified XMC_SPI_CH_EVENT_t enum for supporting XMC_SPI_CH_EnableEvent() and XMC_SPI_CH_DisableEvent() + * for supporting multiple events configuration
+ * + * 2015-09-08: + * - Adding API for configuring the receiving clock phase in the slave:XMC_SPI_CH_DataLatchedInTrailingEdge() and XMC_SPI_CH_DataLatchedInLeadingEdge()
+ * + * 2016-04-10: + * - Added an API for configuring the transmit mode:XMC_SPI_CH_SetTransmitMode()
+ * + * 2016-05-20: + * - Added XMC_SPI_CH_EnableDataTransmission() and XMC_SPI_CH_DisableDataTransmission() + * + * @endcond + * + */ + +#ifndef XMC_SPI_H +#define XMC_SPI_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ +#include "xmc_usic.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup SPI + * @brief Synchronous serial channel driver for SPI-like communication. + * + * The SPI driver uses Universal Serial Interface Channel(USIC) module. + * The USIC module supports multiple data lines for SPI communication. \n + * -# Full duplex communication with 2 separate lines for transmission and reception. + * -# Half duplex communication with 1 common line shared for transmission and reception. + * -# Dual mode communication with 2 common lines shared for transmission and reception. + * -# Quad mode communication with 4 common lines shared for transmission and reception.

+ * + * SPI driver provides structures, enumerations and APIs for configuring the USIC channel for SPI communication + * and also for data transaction.
+ * SPI driver features: + * -# Configuration structure XMC_SPI_CH_CONFIG_t and SPI initialization function XMC_SPI_CH_Init() + * -# Allows configuration of protocol word and frame length using XMC_SPI_CH_SetWordLength(), XMC_SPI_CH_SetFrameLength() + * -# Allows manipulation of data frame at runtime using XMC_SPI_CH_EnableSOF(), XMC_SPI_CH_EnableEOF(), + XMC_SPI_CH_EnableSlaveSelect(), XMC_SPI_CH_DisableSlaveSelect() + * -# Provides APIs for transmitting data and receiving data using XMC_SPI_CH_Transmit(), XMC_SPI_CH_Receive(), XMC_SPI_CH_GetReceivedData() + * -# Allows configuration of shift clock using XMC_SPI_CH_ConfigureShiftClockOutput() + * -# Provides enumeration of SPI protocol events using @ref XMC_SPI_CH_STATUS_FLAG_t + * @{ + */ + +/*********************************************************************************************************************** + * MACROS + **********************************************************************************************************************/ + +#if defined(USIC0) +#define XMC_SPI0_CH0 XMC_USIC0_CH0 /**< SPI0 channel 0 base address */ +#define XMC_SPI0_CH1 XMC_USIC0_CH1 /**< SPI0 channel 1 base address */ +#endif + +#if defined(USIC1) +#define XMC_SPI1_CH0 XMC_USIC1_CH0 /**< SPI1 channel 0 base address */ +#define XMC_SPI1_CH1 XMC_USIC1_CH1 /**< SPI1 channel 1 base address */ +#endif + +#if defined(USIC2) +#define XMC_SPI2_CH0 XMC_USIC2_CH0 /**< SPI2 channel 0 base address */ +#define XMC_SPI2_CH1 XMC_USIC2_CH1 /**< SPI2 channel 1 base address */ +#endif + +/*********************************************************************************************************************** + * ENUMS + ***********************************************************************************************************************/ + +/** + * Defines return status of SPI driver APIs + */ +typedef enum XMC_SPI_CH_STATUS +{ + XMC_SPI_CH_STATUS_OK, /**< Status of the Module: OK */ + XMC_SPI_CH_STATUS_ERROR, /**< Status of the Module: ERROR */ + XMC_SPI_CH_STATUS_BUSY /**< The Module is busy */ +} XMC_SPI_CH_STATUS_t; +/** + * Defines the SPI bus mode + */ +typedef enum XMC_SPI_CH_BUS_MODE +{ + XMC_SPI_CH_BUS_MODE_MASTER, /**< SPI Master */ + XMC_SPI_CH_BUS_MODE_SLAVE /**< SPI Slave */ +} XMC_SPI_CH_BUS_MODE_t; + +/** + * Defines the Polarity of the slave select signals SELO[7:0] in relation to the master slave select signal MSLS. + */ +typedef enum XMC_SPI_CH_SLAVE_SEL_MSLS_INV +{ + XMC_SPI_CH_SLAVE_SEL_SAME_AS_MSLS = 0x0UL, /**< The SELO outputs have the same polarity as the MSLS signal + (active high) */ + XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS = 0x1UL << USIC_CH_PCR_SSCMode_SELINV_Pos /**< The SELO outputs have the inverted + polarity to the MSLS signal + (active low)*/ +} XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t; + +/** + * Defines the Polarity of the data inputs. + */ +typedef enum XMC_SPI_CH_DATA_POLARITY +{ + XMC_SPI_CH_DATA_POLARITY_DIRECT = 0x0UL, /**< The polarity of the data line is not inverted */ + XMC_SPI_CH_DATA_POLARITY_INVERT = 0x1UL << USIC_CH_DX2CR_DPOL_Pos /**< The polarity of the data line is inverted */ +} XMC_SPI_CH_DATA_POLARITY_t; + +/** + * Defines Slave Select lines + */ +typedef enum XMC_SPI_CH_SLAVE_SELECT +{ + XMC_SPI_CH_SLAVE_SELECT_0 = 1UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 0 */ + XMC_SPI_CH_SLAVE_SELECT_1 = 2UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 1 */ + XMC_SPI_CH_SLAVE_SELECT_2 = 4UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 2 */ + XMC_SPI_CH_SLAVE_SELECT_3 = 8UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 3 */ + XMC_SPI_CH_SLAVE_SELECT_4 = 16UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 4 */ + XMC_SPI_CH_SLAVE_SELECT_5 = 32UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 5 */ + XMC_SPI_CH_SLAVE_SELECT_6 = 64UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 6 */ + XMC_SPI_CH_SLAVE_SELECT_7 = 128UL << USIC_CH_PCR_SSCMode_SELO_Pos /**< Slave Select line 7 */ +} XMC_SPI_CH_SLAVE_SELECT_t; + +/** + * Defines SPI specific events + */ +typedef enum XMC_SPI_CH_EVENT +{ + XMC_SPI_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */ + XMC_SPI_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */ + XMC_SPI_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */ + XMC_SPI_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */ + XMC_SPI_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */ + XMC_SPI_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */ + XMC_SPI_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */ + + XMC_SPI_CH_EVENT_PARITY_ERROR = USIC_CH_PCR_SSCMode_PARIEN_Msk >> 13U, /**< Parity error event */ + XMC_SPI_CH_EVENT_MSLS_CHANGE = USIC_CH_PCR_SSCMode_MSLSIEN_Msk >> 13U, /**< Master slave select(MSLS) output transition event*/ + XMC_SPI_CH_EVENT_DX2TIEN_ACTIVATED = USIC_CH_PCR_SSCMode_DX2TIEN_Msk >> 13U /**< Slave select input signal transition event*/ +} XMC_SPI_CH_EVENT_t; + +/** + * Defines SPI event status + */ +typedef enum XMC_SPI_CH_STATUS_FLAG +{ + XMC_SPI_CH_STATUS_FLAG_MSLS = USIC_CH_PSR_SSCMode_MSLS_Msk, /**< Status of Master slave + select(MSLS) signal */ + XMC_SPI_CH_STATUS_FLAG_DX2S = USIC_CH_PSR_SSCMode_DX2S_Msk, /**< Status of slave select + input(DX2) signal*/ + XMC_SPI_CH_STATUS_FLAG_MSLS_EVENT_DETECTED = USIC_CH_PSR_SSCMode_MSLSEV_Msk, /**< Status for master slave select + output signal transition*/ + XMC_SPI_CH_STATUS_FLAG_DX2T_EVENT_DETECTED = USIC_CH_PSR_SSCMode_DX2TEV_Msk, /**< Status for slave select + input signal transition */ + XMC_SPI_CH_STATUS_FLAG_PARITY_ERROR_EVENT_DETECTED = USIC_CH_PSR_SSCMode_PARERR_Msk, /**< Indicates status of the + parity error */ + XMC_SPI_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_SSCMode_RSIF_Msk, /**< Status for receive start + event */ + XMC_SPI_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_SSCMode_DLIF_Msk, /**< Status for data lost event*/ + XMC_SPI_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_SSCMode_TSIF_Msk, /**< Status for transmit shift + event */ + XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_SSCMode_TBIF_Msk, /**< Status for transmit buffer + event */ + XMC_SPI_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_SSCMode_RIF_Msk, /**< Status for receive event */ + XMC_SPI_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_SSCMode_AIF_Msk, /**< Status for alternative + receive event */ + XMC_SPI_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_SSCMode_BRGIF_Msk/**< Status for baud rate + generation error event */ +} XMC_SPI_CH_STATUS_FLAG_t; + +/** + * Defines input frequency sources for slave select signal delay configuration. + */ +typedef enum XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY +{ + XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPDIV = 0x0UL, /**< Output of PDIV divider: FPDIV */ + XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPPP = 0x1UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos, /**< Peripheral clock: FPPP */ + XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FSCLK = 0x2UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos, /**< Shift clock: FSCLK */ + XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FMCLK = 0x3UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos /**< Master clock: FMCLK */ +} XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_t; + +/** + * Define data and clock input stages + */ +typedef enum XMC_SPI_CH_INPUT +{ + XMC_SPI_CH_INPUT_DIN0 = 0UL, /**< Data input stage 0 */ + XMC_SPI_CH_INPUT_SLAVE_SCLKIN = 1UL, /**< Clock input stage */ + XMC_SPI_CH_INPUT_SLAVE_SELIN = 2UL, /**< Slave select input stage */ + XMC_SPI_CH_INPUT_DIN1 = 3UL, /**< Data input stage 1 */ + XMC_SPI_CH_INPUT_DIN2 = 4UL, /**< Data input stage 2 */ + XMC_SPI_CH_INPUT_DIN3 = 5UL /**< Data input stage 3 */ +} XMC_SPI_CH_INPUT_t; + +/** + * Define SPI data transfer mode + */ +typedef enum XMC_SPI_CH_MODE +{ + XMC_SPI_CH_MODE_STANDARD = 0UL, /**< SPI standard full duplex mode */ + XMC_SPI_CH_MODE_STANDARD_HALFDUPLEX = 4UL, /**< SPI standard half duplex mode */ + XMC_SPI_CH_MODE_DUAL= 6UL, /**< SPI half duplex mode with dual data lines */ + XMC_SPI_CH_MODE_QUAD= 7UL /**< SPI half duplex mode with quad data lines */ +} XMC_SPI_CH_MODE_t; + + +/** + * SPI Baudrate Generator shift clock passive level + */ +typedef enum XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL +{ + /**< Passive clock level 0, delay disabled */ + XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED, + /**< Passive clock level 1, delay disabled */ + XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED, + /**< Passive clock level 0, delay enabled */ + XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED, + /**< Passive clock level 1, delay enabled */ + XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED +} XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t; + +/** + * SPI Baudrate Generator shift clock output +*/ +typedef enum XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT +{ + XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK, /**< Baudrate Generator shift clock output: SCLK*/ + XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 /**< Clock obtained as input from master: DX1*/ +} XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t; + +/** + * SPI channel interrupt node pointers + */ +typedef enum XMC_SPI_CH_INTERRUPT_NODE_POINTER +{ + XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */ + XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */ + XMC_SPI_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */ + XMC_SPI_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */ + XMC_SPI_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */ +} XMC_SPI_CH_INTERRUPT_NODE_POINTER_t; + +/********************************************************************************************************************** + * DATA STRUCTURES +**********************************************************************************************************************/ + +/** + * Structure for initializing SPI channel. + */ +typedef struct XMC_SPI_CH_CONFIG +{ + uint32_t baudrate; /**< Module baud rate for communication */ + XMC_SPI_CH_BUS_MODE_t bus_mode; /**< Bus mode: Master/Slave */ + XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion; /**< Enable inversion of Slave select signal relative to the internal + MSLS signal */ + XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Enable parity check for transmit and received data */ +} XMC_SPI_CH_CONFIG_t; + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param config pointer to constant SPI channel configuration data structure.\n + * Refer data structure @ref XMC_SPI_CH_CONFIG_t for detail. + * + * @return None + * + * \parDescription:
+ * Initializes the selected SPI \a channel with the \a config structure.\n\n + * Enable SPI channel by calling XMC_USIC_CH_Enable() and then configures + *
    + *
  • Baudrate,
    • + *
  • Passive data level as active high,
    • + *
  • Shift control signal as active high,
    • + *
  • Frame length as 64U,
    • + *
  • Word length as 8U,
    • + *
  • Enable Hardware port control mode,
    • + *
  • Enable transmission of data TDV(Transmit data valid) bit is set to 1,
    • + *
  • Enable invalidation of data in TBUF once loaded into shift register,
    • + *
  • Parity mode settings
    • + *
+ * And if master mode is selected, + *
    + *
  • Enables MSLS signal generation,
    • + *
  • configures slave selection as normal mode,
    • + *
  • Set polarity for the Slave signal,
    • + *
  • Enable Frame end mode(MSLS signal is kept active after transmission of a frame)
    • + *
+ */ +void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the selected USIC channel to operate in SPI mode, by setting CCR.MODE bits.\n\n + * It should be executed after XMC_SPI_CH_Init() during initialization. By invoking XMC_SPI_CH_Stop(), the MODE is set + * to IDLE state. Call XMC_SPI_CH_Start() to set the SPI mode again, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop() + */ +__STATIC_INLINE void XMC_SPI_CH_Start(XMC_USIC_CH_t *const channel) +{ + /* USIC channel in SPI mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_SPI); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for stopping is processed. \n + * XMC_SPI_CH_STATUS_OK- If the USIC channel is successfully put to IDLE mode. \n + * XMC_SPI_CH_STATUS_BUSY- If the USIC channel is busy transmitting data. + * + * \parDescription:
+ * Set the selected SPI channel to IDLE mode, by clearing CCR.MODE bits.\n\n + * After calling XMC_SPI_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_SPI_CH_Start() has to be + * invoked to start the communication again. + * + * \parRelated APIs:
+ * XMC_SPI_CH_Start() + */ +XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param rate Bus speed in bits per second + * + * @return XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for setting baudrate is processed. \n + * XMC_SPI_CH_STATUS_OK- If the baudrate is successfully changed. \n + * XMC_SPI_CH_STATUS_ERROR- If the new baudrate value is out of range. + * + * \parDescription:
+ * Sets the bus speed in bits per second + * + * \parRelated APIs:
+ * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop() + */ +XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param slave Slave select signal.\n + * Refer @ref XMC_SPI_CH_SLAVE_SELECT_t for valid values. + * + * @return None + * + * \parDescription:
+ * Enable the selected slave signal by setting PCR.SELO bits.\n\n + * Each slave is connected with one slave select signal. This is not configured in XMC_SPI_CH_Init(). Invoke + * XMC_SPI_CH_EnableSlaveSelect() with required \a slave to to start the communication. After finishing the + * communication XMC_SPI_CH_DisableSlaveSelect() can be invoked to disable the slaves. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableSlaveSelect() + */ +void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SELECT_t slave); + +/** + * @param channel A constant ponter to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Disable all the slave signals by clearing PCR.SELO bits.\n\n + * XMC_SPI_CH_EnableSlaveSelect() has to be invoked to start the communication with the desired slave again. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableSlaveSelect() + */ +void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated.\n + * Refer @ref XMC_SPI_CH_MODE_t for valid values. + * + * @return None + * + * \parDescription:
+ * In Dual and Quad modes, hardware port control(CCR.HPCEN) mode is enabled. \n\n + * By enabling this the direction of the data pin is updated by hardware itself. Before transmitting the data set the + * mode to ensure the proper communication. + * + * \parRelated APIs:
+ * XMC_SPI_CH_Transmit() + */ +__STATIC_INLINE void XMC_SPI_CH_SetTransmitMode(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_MODE_t mode) +{ + channel->CCR = (channel->CCR & (uint32_t)(~USIC_CH_CCR_HPCEN_Msk)) | + (((uint32_t) mode << USIC_CH_CCR_HPCEN_Pos) & (uint32_t)USIC_CH_CCR_HPCEN_Msk); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param data Data to be transmitted + * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated.\n + * Refer @ref XMC_SPI_CH_MODE_t for valid values. + * + * @return None + * + * \parDescription:
+ * Puts the data into FIFO, if FIFO mode is enabled or else into standard buffer, by setting the proper mode.\n\n + * In Dual and Quad modes, hardware port control(CCR.HPCEN) mode is enabled. By enabling this the direction of the data + * pin is updated by hardware itself. TCI(Transmit Control Information) allows dynamic control of both the data shift mode + * and pin direction during data transfers by writing to SCTR.DSM and SCTR.HPCDIR bit fields. To support this auto + * update, TCSR.HPCMD(Hardware Port control) will be enabled during the initialization using XMC_SPI_CH_Init() for all modes. + * + * + * \parRelated APIs:
+ * XMC_SPI_CH_Receive() + */ +void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_SPI_CH_MODE_t mode); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated.\n + * Refer @ref XMC_SPI_CH_MODE_t for valid values. + * + * @return None + * + * \parDescription:
+ * Transmits a dummy data(FFFFH) to provide clock for slave and receives the data from the slave.\n\n + * XMC_SPI_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data + * XMC_SPI_CH_GetReceivedData() can be invoked to read the data from the buffers. + * + * \parRelated APIs:
+ * XMC_SPI_CH_GetReceivedDaa() + */ +__STATIC_INLINE void XMC_SPI_CH_Receive(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_MODE_t mode) +{ + /* Transmit dummy data */ + XMC_SPI_CH_Transmit(channel, (uint16_t)0xffffU, (XMC_SPI_CH_MODE_t)((uint16_t)mode & 0xfffbU)); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return uint16_t Data read from the receive buffer. + * + * \parDescription:
+ * Reads data from the receive buffer based on the FIFO selection.\n\n + * Invocation of XMC_SPI_CH_Receive() receives the data and place it into receive buffer. After receiving the data + * XMC_SPI_CH_GetReceivedData() can be used to read the data from the buffer. + * + * \parRelated APIs:
+ * XMC_SPI_CH_Receive() + */ +uint16_t XMC_SPI_CH_GetReceivedData(XMC_USIC_CH_t *const channel); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the order of data transfer from LSB to MSB, by clearing SCTR.SDIR bit.\n\n + * This is typically based on the slave settings. Invoke XMC_SPI_CH_SetBitOrderLsbFirst() to set direction as needed in + * the program. + * + * \parRelated APIs:
+ * XMC_SPI_CH_SetBitOrderMsbFirst() + */ +__STATIC_INLINE void XMC_SPI_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t *const channel) +{ + channel->SCTR &= (uint32_t)~USIC_CH_SCTR_SDIR_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.\n\n + * This is typically based on the slave settings. This is not set during XMC_SPI_CH_Init(). + * Invoke XMC_SPI_CH_SetBitOrderMsbFirst() to set direction as needed in the program. + * + * \parRelated APIs:
+ * XMC_SPI_CH_SetBitOrderLsbFirst() + */ +__STATIC_INLINE void XMC_SPI_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t *const channel) +{ + channel->SCTR |= (uint32_t)USIC_CH_SCTR_SDIR_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param event Protocol events which have to be enabled. + * Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations of these enum items can be used + * as input. + * + * @return None + * + * \parDescription:
+ * Enables the SPI protocol specific events, by configuring PCR register.\n\n + * Events can be enabled as needed using XMC_SPI_CH_EnableEvent(). + * XMC_SPI_CH_DisableEvent() can be used to disable the events. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableEvent() + */ +void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param event Protocol events which have to be disabled. + * Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations of these enum item can be used + * as input. + * + * @return None + * + * \parDescription:
+ * Disables the SPI protocol specific events, by configuring PCR register.\n\n + * After disabling the events, XMC_SPI_CH_EnableEvent() has to be invoked to re-enable the events. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableEvent() + */ +void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return uint32_t Status of SPI protocol events. + * + * \parDescription:
+ * Returns the status of the events, by reading PSR register.\n\n + * This indicates the status of the all the events, for SPI communication. + * + * \parRelated APIs:
+ * XMC_SPI_CH_ClearStatusFlag() + */ +__STATIC_INLINE uint32_t XMC_SPI_CH_GetStatusFlag(XMC_USIC_CH_t *const channel) +{ + return channel->PSR_SSCMode; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param flag Protocol event status to be cleared for detection of next occurence. + * Refer @ XMC_SPI_CH_STATUS_FLAG_t for valid values. OR combinations of these enum item can be used + * as input. + * @return None + * + * \parDescription:
+ * Clears the events specified, by setting PSCR register.\n\n + * During communication the events occurred have to be cleared to detect their next occurence.\n + * e.g: During transmission Transmit buffer event occurs to indicating data word transfer has started. This + * event has to be cleared after transmission of each data word. Otherwise next event cannot be recognized. + * + * \parRelated APIs:
+ * XMC_SPI_CH_GetStatusFlag() + */ +__STATIC_INLINE void XMC_SPI_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag) +{ + channel->PSCR |= flag; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Enables the generation of Master clock by setting PCR.MCLK bit.\n\n + * This clock can be used as a clock reference for external devices. This is not enabled during initialization in + * XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by + * XMC_SPI_CH_DisableMasterClock(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableMasterClock() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_MCLK_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Disables the generation of Master clock by clearing PCR.MCLK bit.\n\n + * This clock can be enabled by invoking XMC_SPI_CH_EnableMasterClock() as needed in the program. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableMasterClock() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_MCLK_Msk; +} +#ifdef USIC_CH_PCR_SSCMode_SLPHSEL_Msk +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DataLatchedInLeadingEdge() + */ +__STATIC_INLINE void XMC_SPI_CH_DataLatchedInTrailingEdge(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SLPHSEL_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 + * stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are + * always latched in with the leading edge. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DataLatchedInTrailingEdge() + */ +__STATIC_INLINE void XMC_SPI_CH_DataLatchedInLeadingEdge(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode |= USIC_CH_PCR_SSCMode_SLPHSEL_Msk; +} +#endif +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Enables the delay after each word, by setting PCR.TIWEN bit.\n\n + * The inter word delay starts at the end of last SCLK cycle of data word. During this time no clock pulses are + * generated and MSLS signal stays active. If inter word delay is not enabled, last data bit of a data word is directly + * followed by the first data bit of the next data word. This is not enabled in XMC_SPI_CH_Init(). To enable + * XMC_SPI_CH_EnableInterwordDelay() has to be invoked as needed in the program. And can be disabled by invoking + * XMC_SPI_CH_DisableInterwordDelay(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableInterwordDelay() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableInterwordDelay(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_TIWEN_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Disables the delay after after each word, by clearing PCR.TIWEN bit.\n\n + * So the last data bit of a data word is directly followed by the first data bit of the next data word. If needed can + * be enabled by invoking XMC_SPI_CH_EnableInterwordDelay(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableInterwordDelay() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableInterwordDelay(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_TIWEN_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param tinterword_delay_ns delay in terms of nano seconds. + * + * @return None + * + * \parDescription:
+ * Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields.\n\n + * The inter word delay is dependent on the peripheral clock. The maximum possible value is calculated by using the + * below formula\n + * Maximum inter word delay = ((1 + PCTQ1_max)(1 + DCTQ1_max)) / peripheral clock\n + * where PCTQ1_max = 3 and DCTQ1_max = 31\n + * After configuring the inter word delay, this has to be enabled by invoking XMC_SPI_CH_EnableInterwordDelay(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_SetInterwordDelaySCLK() + */ +void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterword_delay_ns); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param sclk_period in terms of clk cycles. + * + * @return None + * + * \parDescription:
+ * Configures the inter word delay by setting PCR.DCTQ1 bit fields.\n\n + * This delay is dependent on the peripheral clock. The maximum possible value supported by this API + * is 32 clock cycles. + * After configuring the inter word delay, this has to be enabled by invoking XMC_SPI_CH_EnableInterwordDelay(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_EnableInterwordDelay() + */ +__STATIC_INLINE void XMC_SPI_CH_SetInterwordDelaySCLK(XMC_USIC_CH_t *const channel,uint32_t sclk_period) +{ + channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode) & (~(USIC_CH_PCR_SSCMode_DCTQ1_Msk | + USIC_CH_PCR_SSCMode_PCTQ1_Msk | + USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) | + (((sclk_period - 1U) << USIC_CH_PCR_SSCMode_DCTQ1_Pos) | + (0x02U << USIC_CH_PCR_SSCMode_CTQSEL1_Pos)); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param sclk_period delay in terms of sclk clock cycles. + * + * @return None + * + * \parDescription:
+ * Configures the leading/trailing delay by setting BRG.DCTQ bit field.\n\n + * This delay is dependent on the peripheral clock. The maximum possible value supported by this API + * is 30 clock cycles. + * + */ +__STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectDelay(XMC_USIC_CH_t *const channel,uint32_t sclk_period) +{ + + channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk | + USIC_CH_BRG_PCTQ_Msk)) | + (((sclk_period - 1U) << USIC_CH_BRG_DCTQ_Pos) | (0x01U << USIC_CH_BRG_PCTQ_Pos)); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * + * Configure to keep MSLS(Slave select signal) active even after finishing the current data frame, + * by setting PCR.FEM bit.\n\n + * This is typically used during the transmission of multi-data word frames, where there is possibility of delay in + * delivering the data. Frame end mode is enabled in XMC_SPI_CH_Init() during initialization. To disable + * XMC_SPI_CH_DisableFEM() can be invoked as needed in the program. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableFEM() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableFEM(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_FEM_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Configure to disable the MSLS(Slave select signal) if the current data frame is considered as finished, + * by setting PCR.FEM bit.\n\n + * + * When the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data, is + * considered as frame is ended and MSLS(Slave select signal) is disabled. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableFEM() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableFEM(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_FEM_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param passive_level polarity and delay of the selected shift clock.\n + * Refer @ref XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t for valid inputs. + * @param clock_output shift clock source.\n + * Refer @ref XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t for valid inputs. + * + * @return None + * + * \parDescription:
+ * Configures the shift clock source with the selected polarity and delay by setting BRG.SCLKOSEL and BRG.SCLKCFG.\n\n + * In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available + * for external slave devices by SCLKOUT signal.\n + * In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.\n + * The shift clock output(SCLKOUT) signal polarity can be set relative to SCLK, with the delay of half the shift clock + * period. These settings are applicable only in master mode. + */ +__STATIC_INLINE void XMC_SPI_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level, + const XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) +{ + XMC_USIC_CH_ConfigureShiftClockOutput(channel, (XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t)passive_level, + (XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param word_length Number of bits to be configured for a data word. \n + * \b Range: 1 to 16. + * + * @return None + * + * \parDescription
+ * Defines the data word length.\n\n + * Sets the number of bits to represent a data word. Frame length should be a multiple of word length. + * + * \parRelated APIs:
+ * XMC_SPI_CH_SetFrameLength() + */ +__STATIC_INLINE void XMC_SPI_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length) +{ + XMC_USIC_CH_SetWordLength(channel, word_length); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param frame_length Number of bits in a frame. \n + * \b Range: 1 to 64. If the value 64 is configured, then the frame does not + * automatically end. User should explicitly end the frame. + * + * @return None + * + * \parDescription
+ * Define the data frame length.\n\n + * Set the number of bits to be serially transmitted in a frame. + * The frame length should be multiples of word length. If the value is set to 64, the frame does not + * automatically end. Use XMC_SPI_CH_DisableSlaveSelect() to end the frame after all the data + * is transmitted. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetWordLength(), XMC_USIC_CH_EnableFrameLengthControl(), XMC_SPI_CH_DisableSlaveSelect() + */ +__STATIC_INLINE void XMC_SPI_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length) +{ + XMC_USIC_CH_SetFrameLength(channel, frame_length); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * Configure the handling of start of frame through software, by setting TCSR.SOF bit.\n\n + * This can be used if the software handles the TBUF data without FIFO. If SOF is set, a valid content of the TBUF is + * considered as first word of a new frame by finishing the currently running frame. For software handling of SOF bit, + * it is recommended to configure TCSR.WLEMD as 0. This is not configured during initialization. XMC_SPI_CH_EnableSOF() + * can be called as needed in the program and can be disabled by XMC_SPI_CH_DisableSOF(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableSOF() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableSOF(XMC_USIC_CH_t *const channel) +{ + channel->TCSR |= (uint32_t)USIC_CH_TCSR_SOF_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * Set the control of the handling start of frame through hardware, by clearing TCSR.SOF bit.\n\n + * Typically this can be disabled, where the transmission control is done by the hardware. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableSOF() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableSOF(XMC_USIC_CH_t *const channel) +{ + channel->TCSR &= (uint32_t)~USIC_CH_TCSR_SOF_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * Configure the handling of end of frame through software, by setting TCSR.EOF bit.\n\n + * This can be used if the software handles the TBUF data without FIFO. If EOF is set, a valid content of the TBUF is + * considered as last word of a frame. After transfer of the last word, MSLS signal becomes inactive. For software + * handling of EOF bit, it is recommended to configure TCSR.WLEMD as 0. \n + * \b Note: The API should be called before putting the last data word of the frame to TBUF. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableEOF() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableEOF(XMC_USIC_CH_t *const channel) +{ + channel->TCSR |= (uint32_t)USIC_CH_TCSR_EOF_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * Configure the handling of end of frame through hardware, by clearing TCSR.EOF bit.\n\n + * Typically this can be disabled, where the transmission control is done by the hardware. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableEOF() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableEOF(XMC_USIC_CH_t *const channel) +{ + channel->TCSR &= (uint32_t)~USIC_CH_TCSR_EOF_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input SPI channel input stage.\n + * Refer @ref XMC_SPI_CH_INPUT_t for valid values + * @param source Input source select for the input stage. + * Range : [0 to 7] + * + * @return None + * + * \parDescription
+ * Selects the data source for SPI input stage, by configuring DXCR.DSEL bits.\n\n + * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the + * input stages like DX0CR, DX1CR etc. This is not done during initialization. This has to be configured before starting + * the SPI communication. + */ +__STATIC_INLINE void XMC_SPI_CH_SetInputSource(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_INPUT_t input, + const uint8_t source) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_DSEN_Msk)) | USIC_CH_DX0CR_INSW_Msk; + XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param selo_inversion Polarity of the slave select signal relative to the MSLS signal.\n + * Refer @ref XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t for valid values + * + * @return None + * + * \parDescription
+ * Set the polarity of the slave select signal, by configuring PCR.SELINV bit.\n\n + * Normally MSLS signal is active low level signal. SO based on the slave inversion has to be applied. This is configured + * in XMC_SPI_CH_Init() during initialization. Invoke XMC_SPI_CH_SetSlaveSelectPolarity() with desired settings as + * needed later in the program. + */ +__STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectPolarity(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion) +{ + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode & (~USIC_CH_PCR_SSCMode_SELINV_Msk)) | (uint32_t)selo_inversion); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input SPI channel input stage.\n + * Refer @ref XMC_SPI_CH_INPUT_t for valid inputs. + * + * @return None + * + * \parDescription
+ * Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y = \a input).\n\n + * This is not set in XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableInputInversion() as needed later in the program. To + * disable the inversion XMC_SPI_CH_DisableInputInversion() can be invoked. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableInputInversion() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_INPUT_t input) +{ + XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input SPI channel input stage.\n + * Refer @ref XMC_SPI_CH_INPUT_t for valid inputs. + * + * @return None + * + * \parDescription
+ * Disables the polarity inversion of input data signal, by clearing DXyCR.DPOL(where y = \a input).\n\n + * Resets the input data polarity. Invoke XMC_SPI_CH_EnableInputInversion() to apply inversion. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableInputInversion() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_INPUT_t input) +{ + XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param service_request Service request number. + Range: [0 to 5] + * + * @return None + * + * \parDescription
+ * Sets the interrupt node for SPI channel events.\n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so. This is not configured in XMC_SPI_CH_Init() during + * initialization. + * + * \parNote::
+ * 1. NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableEvent() + */ +__STATIC_INLINE void XMC_SPI_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const uint8_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, (uint32_t)service_request); +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @param interrupt_node Interrupt node pointer to be configured. \n + * \b Range: @ref XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, + * @ref XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc. + * @param service_request Service request number.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for USIC channel events. \n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, + (uint32_t)service_request); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @param service_request_line service request number of the event to be triggered. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Trigger a SPI interrupt service request.\n\n + * When the SPI service request is triggered, the NVIC interrupt associated with it will be + * generated if enabled. + * + * \parRelated APIs:
+ * XMC_SPI_CH_SelectInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line) +{ + XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @return None + * + * \parDescription
+ * Enables delay compensation. \n\n + * + * Delay compensation can be applied to the receive path. + * \parRelated APIs:
+ * XMC_SPI_CH_DisableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_EnableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_EnableDelayCompensation(channel); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @return None + * + * \parDescription
+ * Disables delay compensation.. \n\n + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_DisableDelayCompensation(channel); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @param pdiv Desired divider for the external frequency input. \b Range: minimum value = 1, maximum value = 1024 \n + * @param combination_mode USIC channel input combination mode \n + * + * @return None + * + * \parDescription
+ * Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and + * the combination mode of the USIC channel. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, + const uint16_t pdiv, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) +{ + XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel,pdiv,2U,combination_mode); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * The SELOx lines (with x = 1-7) can be used as addresses for an external address + * decoder to increase the number of external slave devices. + */ +__STATIC_INLINE void XMC_SPI_CH_EnableSlaveSelectCodedMode(XMC_USIC_CH_t *const channel) +{ + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode = (uint32_t)(channel->PCR_SSCMode & (~USIC_CH_PCR_SSCMode_SELCTR_Msk)); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * Each SELOx line (with x = 0-7) can be directly connected to an external slave device. + */ +__STATIC_INLINE void XMC_SPI_CH_DisableSlaveSelectCodedMode(XMC_USIC_CH_t *const channel) +{ + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_SELCTR_Msk; +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @return None + * + * \parDescription
+ * Enable data transmission.\n\n + * Use this function in combination with XMC_SPI_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode() + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @return None + * + * \parDescription
+ * Disable data transmission.\n\n + * Use this function in combination with XMC_SPI_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_uart.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_uart.h new file mode 100644 index 00000000..387be642 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_uart.h @@ -0,0 +1,810 @@ + /** + * @file xmc_uart.h + * @date 2016-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial + * + * 2015-05-20: + * - Description updated
+ * - Added XMC_UART_CH_TriggerServiceRequest() and XMC_UART_CH_SelectInterruptNodePointer
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-09-01: + * - Modified XMC_UART_CH_SetInputSource() for avoiding complete DXCR register overwriting.
+ * - Modified XMC_UART_CH_EVENT_t enum for supporting XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent() + * for supporting multiple events configuration
+ * + * 2016-05-20: + * - Added XMC_UART_CH_EnableDataTransmission() and XMC_UART_CH_DisableDataTransmission() + * + * @endcond + * + */ + +#ifndef XMC_UART_H +#define XMC_UART_H + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_usic.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup UART + * @brief Universal Asynchronous Receiver/Transmitter (UART) driver for XMC microcontroller family. + * + * The UART driver uses Universal Serial Interface Channel(USIC) module to implement UART protocol. + * It provides APIs to configure USIC channel for UART communication. The driver enables the user + * in getting the status of UART protocol events, configuring interrupt service requests, protocol + * related parameter configuration etc. + * + * UART driver features: + * -# Configuration structure XMC_UART_CH_CONFIG_t and initialization function XMC_UART_CH_Init() + * -# Enumeration of events with their bit masks @ref XMC_UART_CH_EVENT_t, @ref XMC_UART_CH_STATUS_FLAG_t + * -# Allows the selection of input source for the DX0 input stage using the API XMC_UART_CH_SetInputSource() + * -# Allows configuration of baudrate using XMC_UART_CH_SetBaudrate() and configuration of data length using + XMC_UART_CH_SetWordLength() and XMC_UART_CH_SetFrameLength() + * -# Provides the status of UART protocol events, XMC_UART_CH_GetStatusFlag() + * -# Allows transmission of data using XMC_UART_CH_Transmit() and gets received data using XMC_UART_CH_GetReceivedData() + * + * @{ + */ + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ + +#if defined(USIC0) +#define XMC_UART0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */ +#define XMC_UART0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */ +#endif + +#if defined(USIC1) +#define XMC_UART1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */ +#define XMC_UART1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */ +#endif + +#if defined(USIC2) +#define XMC_UART2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */ +#define XMC_UART2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */ +#endif + +/********************************************************************************************************************* + * ENUMS + *********************************************************************************************************************/ + +/** + * UART driver status + */ +typedef enum XMC_UART_CH_STATUS +{ + XMC_UART_CH_STATUS_OK, /**< UART driver status : OK*/ + XMC_UART_CH_STATUS_ERROR, /**< UART driver status : ERROR */ + XMC_UART_CH_STATUS_BUSY /**< UART driver status : BUSY */ +} XMC_UART_CH_STATUS_t; + +/** +* UART portocol status. The enum values can be used for getting the status of UART channel. +* +*/ +typedef enum XMC_UART_CH_STATUS_FLAG +{ + XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE = USIC_CH_PSR_ASCMode_TXIDLE_Msk, /**< UART Protocol Status transmit IDLE*/ + XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE = USIC_CH_PSR_ASCMode_RXIDLE_Msk, /**< UART Protocol Status receive IDLE*/ + XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED = USIC_CH_PSR_ASCMode_SBD_Msk, /**< UART Protocol Status synchronization break detected*/ + XMC_UART_CH_STATUS_FLAG_COLLISION_DETECTED = USIC_CH_PSR_ASCMode_COL_Msk, /**< UART Protocol Status collision detected*/ + XMC_UART_CH_STATUS_FLAG_RECEIVER_NOISE_DETECTED = USIC_CH_PSR_ASCMode_RNS_Msk, /**< UART Protocol Status receiver noise detected */ + XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_0 = USIC_CH_PSR_ASCMode_FER0_Msk, /**< UART Protocol Status format error in stop bit 0 */ + XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_1 = USIC_CH_PSR_ASCMode_FER1_Msk, /**< UART Protocol Status format error in stop bit 1 */ + XMC_UART_CH_STATUS_FLAG_RECEIVE_FRAME_FINISHED = USIC_CH_PSR_ASCMode_RFF_Msk, /**< UART Protocol Status receive frame finished */ + XMC_UART_CH_STATUS_FLAG_TRANSMITTER_FRAME_FINISHED = USIC_CH_PSR_ASCMode_TFF_Msk, /**< UART Protocol Status transmit frame finished */ + XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY = USIC_CH_PSR_ASCMode_BUSY_Msk, /**< UART Protocol Status transfer status busy */ + XMC_UART_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_ASCMode_RSIF_Msk, /**< UART Protocol Status receive start indication flag*/ + XMC_UART_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_ASCMode_DLIF_Msk, /**< UART Protocol Status data lost indication flag*/ + XMC_UART_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_ASCMode_TSIF_Msk, /**< UART Protocol Status transmit shift indication flag*/ + XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_ASCMode_TBIF_Msk, /**< UART Protocol Status transmit buffer indication flag*/ + XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_RIF_Msk, /**< UART Protocol Status receive indication flag*/ + XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_AIF_Msk, /**< UART Protocol Status alternative receive indication flag*/ + XMC_UART_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_ASCMode_BRGIF_Msk /**< UART Protocol Status baudrate generator indication flag*/ +} XMC_UART_CH_STATUS_FLAG_t; + +/** +* UART configuration events. The enums can be used for configuring events using the CCR register. +*/ +typedef enum XMC_CH_UART_EVENT +{ + XMC_UART_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */ + XMC_UART_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */ + XMC_UART_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */ + XMC_UART_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */ + XMC_UART_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */ + XMC_UART_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */ + XMC_UART_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */ + + XMC_UART_CH_EVENT_SYNCHRONIZATION_BREAK = USIC_CH_PCR_ASCMode_SBIEN_Msk, /**< Event synchronization break */ + XMC_UART_CH_EVENT_COLLISION = USIC_CH_PCR_ASCMode_CDEN_Msk, /**< Event collision */ + XMC_UART_CH_EVENT_RECEIVER_NOISE = USIC_CH_PCR_ASCMode_RNIEN_Msk, /**< Event receiver noise */ + XMC_UART_CH_EVENT_FORMAT_ERROR = USIC_CH_PCR_ASCMode_FEIEN_Msk, /**< Event format error */ + XMC_UART_CH_EVENT_FRAME_FINISHED = USIC_CH_PCR_ASCMode_FFIEN_Msk /**< Event frame finished */ +} XMC_UART_CH_EVENT_t; + +/** + * UART Input sampling frequency options + */ +typedef enum XMC_UART_CH_INPUT_SAMPLING_FREQ +{ + XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH = XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH, /**< Sampling frequency input fperiph*/ + XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER = XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER /**< Sampling frequency input fractional divider*/ +} XMC_UART_CH_INPUT_SAMPLING_FREQ_t; + +/** + * UART input stages + */ +typedef enum XMC_UART_CH_INPUT +{ + XMC_UART_CH_INPUT_RXD = 0UL /**< UART input stage DX0*/ +#if UC_FAMILY == XMC1 + , + XMC_UART_CH_INPUT_RXD1 = 3UL, /**< UART input stage DX3*/ + XMC_UART_CH_INPUT_RXD2 = 5UL /**< UART input stage DX5*/ +#endif +} XMC_UART_CH_INPUT_t; + + +/** + * UART channel interrupt node pointers + */ +typedef enum XMC_UART_CH_INTERRUPT_NODE_POINTER +{ + XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */ + XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */ + XMC_UART_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */ + XMC_UART_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */ + XMC_UART_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */ +} XMC_UART_CH_INTERRUPT_NODE_POINTER_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + *********************************************************************************************************************/ + +/** + * UART initialization structure +*/ +typedef struct XMC_UART_CH_CONFIG +{ + uint32_t baudrate; /**< Desired baudrate. \b Range: minimum= 100, maximum= (fPERIPH * 1023)/(1024 * oversampling) */ + uint8_t data_bits; /**< Number of bits for the data field. Value configured as USIC channel word length. \n + \b Range: minimum= 1, maximum= 16*/ + uint8_t frame_length; /**< Indicates nmber of bits in a frame. Configured as USIC channel frame length. \n + \b Range: minimum= 1, maximum= 63*/ + uint8_t stop_bits; /**< Number of stop bits. \b Range: minimum= 1, maximum= 2 */ + uint8_t oversampling; /**< Number of samples for a symbol(DCTQ).\b Range: minimum= 1, maximum= 32*/ + XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Parity mode. \b Range: @ref XMC_USIC_CH_PARITY_MODE_NONE, @ref XMC_USIC_CH_PARITY_MODE_EVEN, \n + @ref XMC_USIC_CH_PARITY_MODE_ODD*/ +} XMC_UART_CH_CONFIG_t; + +/********************************************************************************************************************* + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1,XMC_UART1_CH0, XMC_UART1_CH1,XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param config Constant pointer to UART configuration structure of type @ref XMC_UART_CH_CONFIG_t. + * @return XMC_UART_CH_STATUS_t Status of initializing the USIC channel for UART protocol.\n + * \b Range: @ref XMC_UART_CH_STATUS_OK if initialization is successful.\n + * @ref XMC_UART_CH_STATUS_ERROR if configuration of baudrate failed. + * + * \parDescription
+ * Initializes the USIC channel for UART protocol.\n\n + * During the initialization, USIC channel is enabled, baudrate is configured with the defined oversampling value + * in the intialization structure. If the oversampling value is set to 0 in the structure, the default oversampling of 16 + * is considered. Sampling point for each symbol is configured at the half of sampling period. Symbol value is decided by the + * majority decision among 3 samples. + * Word length is configured with the number of data bits. If the value of \a frame_length is 0, then USIC channel frame length + * is set to the same value as word length. If \a frame_length is greater than 0, it is set as the USIC channel frame length. + * Parity mode is set to the value configured for \a parity_mode. + * The USIC channel should be set to UART mode by calling the XMC_UART_CH_Start() API after the initialization. + * + * \parRelated APIs:
+ * XMC_UART_CH_Start(), XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n + */ +void XMC_UART_CH_Init(XMC_USIC_CH_t *const channel, const XMC_UART_CH_CONFIG_t *const config); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return None + * + * \parDescription
+ * Sets the USIC channel operation mode to UART mode.\n\n + * CCR register bitfield \a Mode is set to 2(UART mode). This API should be called after configuring + * the USIC channel. Transmission and reception can happen only when the UART mode is set. + * This is an inline function. + * + * \parRelated APIs:
+ * XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_Start(XMC_USIC_CH_t *const channel) +{ + channel->CCR = (uint32_t)(((channel->CCR) & (~USIC_CH_CCR_MODE_Msk)) | (uint32_t)XMC_USIC_CH_OPERATING_MODE_UART); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return XMC_UART_CH_STATUS_t Status to indicate if the communication channel is stopped successfully.\n + * @ref XMC_UART_CH_STATUS_OK if the communication channel is stopped. + * @ref XMC_UART_CH_STATUS_BUSY if the communication channel is busy. + * + * \parDescription
+ * Stops the UART communication.\n\n + * CCR register bitfield \a Mode is reset. This disables the communication. + * Before starting the communication again, the channel has to be reconfigured. + * + * \parRelated APIs:
+ * XMC_UART_CH_Init() \n\n\n + */ +XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1 ,XMC_UART1_CH0, XMC_UART1_CH1, XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param rate Desired baudrate. \n + * \b Range: minimum value = 100, maximum value depends on the peripheral clock frequency\n + * and \a oversampling. Maximum baudrate can be derived using the formula: (fperiph * 1023)/(1024 * oversampling) + * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data.\n + * This can be related to the number of samples for each logic state of the data signal.\n + * \b Range: 4 to 32. Value should be chosen based on the protocol used. + * @return XMC_UART_CH_STATUS_t Status indicating the baudrate configuration.\n + * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured, + * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid. + * + * \parDescription:
+ * Sets the bus speed in bits per second.\n\n + * Derives the values of \a STEP and PDIV to arrive at the optimum realistic speed possible. + * \a oversampling is the number of samples to be taken for each symbol of UART protocol. + * Default \a oversampling of 16 is considered if the input \a oversampling is less than 4. It is recommended to keep + * a minimum oversampling of 4 for UART. + * + * \parRelated APIs:
+ * XMC_UART_CH_Init(), XMC_UART_CH_Stop() + */ +XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param data Data to be transmitted. \n + * \b Range: 16 bit unsigned data within the range 0 to 65535. Actual size of + * data transmitted depends on the configured number of bits for the UART protocol in the register SCTR. + * @return None + * + * \parDescription
+ * Transmits data over serial communication channel using UART protocol.\n\n + * Based on the channel configuration, data is either put to the transmit FIFO or to TBUF register. + * Before putting data to TBUF, the API waits for TBUF to finish shifting its contents to shift register. + * So user can continuously execute the API without checking for TBUF busy status. Based on the number of + * data bits configured, the lower significant bits will be extracted for transmission. + * + * Note: When FIFO is not configured, the API waits for the TBUF to be available. + * This makes the execution a blocking call. + * + * \parRelated APIs:
+ * XMC_UART_CH_GetReceivedData() \n\n\n + */ +void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return uint16_t Received data over UART communication channel. + * \parDescription
+ * Provides one word of data received over UART communication channel.\n\n + * Based on the channel configuration, data is either read from the receive FIFO or RBUF register. + * Before returning the value, there is no check for data validity. User should check the appropriate + * data receive flags(standard receive/alternative receive/FIFO standard receive/FIFO alternative receive) + * before executing the API. Reading from an empty receive FIFO can generate a receive error event. + * + * \parRelated APIs:
+ * XMC_UART_CH_GetStatusFlag(), XMC_UART_CH_Transmit() \n\n\n + */ +uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param word_length Data word length. \n + * \b Range: minimum= 1, maximum= 16. + * @return None + * + * \parDescription
+ * Sets the data word length in number of bits.\n\n + * Word length can range from 1 to 16. It indicates the number of data bits in a data word. + * The value of \a word_length will be decremented by 1 before setting the value to \a SCTR register. + * If the UART data bits is more than 16, then the frame length should be set to the actual number of bits and + * word length should be configured with the number of bits expected in each transaction. For example, if number of data bits + * for UART communication is 20 bits, then the frame length should be set as 20. Word length can be set based on the + * transmit and receive handling. If data is stored as 8bit array, then the word length can be set to 8. In this case, + * a full message of UART data should be transmitted/ received as 3 data words. + * + * \parRelated APIs:
+ * XMC_UART_CH_SetFrameLength() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length) +{ + XMC_USIC_CH_SetWordLength(channel, word_length); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param frame_length Number of data bits in each UART frame. \n + * \b Range: minimum= 1, maximum= 64. + * @return None + * + * \parDescription
+ * Sets the number of data bits for UART communication.\n\n + * The frame length is configured by setting the input value to \a SCTR register. + * The value of \a frame_length will be decremented by 1, before setting it to the register. + * Frame length should not be set to 64 for UART communication. + * + * \parRelated APIs:
+ * XMC_UART_CH_SetWordLength() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length) +{ + XMC_USIC_CH_SetFrameLength(channel, frame_length); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param event Event bitmasks to enable. Use the type @ref XMC_UART_CH_EVENT_t for naming events. \n + * \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref XMC_UART_CH_EVENT_DATA_LOST, + * @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref XMC_UART_CH_EVENT_TRANSMIT_BUFFER, + * etc. + * @return None + * + * \parDescription
+ * Enables interrupt events for UART communication.\n\n + * Multiple events can be combined using the bitwise OR operation and configured in one function call. + * @ref XMC_UART_CH_EVENT_t enumerates multiple event bitmasks. These enumerations can be used as input to the API. + * Events are configured by setting bits in the CCR register. + * \parRelated APIs:
+ * XMC_UART_CH_DisableEvent(), XMC_UART_CH_SetInterruptNodePointer(), XMC_UART_CH_GetStatusFlag() \n\n\n + */ +void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param event Bitmask of events to disable. Use the type @ref XMC_UART_CH_EVENT_t for naming events.\n + * \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref XMC_UART_CH_EVENT_DATA_LOST, + * @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref XMC_UART_CH_EVENT_TRANSMIT_BUFFER, + * etc. + * @return None + * + * \parDescription
+ * Disables the interrupt events by clearing the bits in CCR register.\n\n + * Multiple events can be combined using the bitwise OR operation and configured in one function call. + * XMC_UART_CH_EVENT_FLAG_t enumerates multiple event bitmasks. These enumerations can be used as input to the API. + * + * \parRelated APIs:
+ * XMC_UART_CH_ClearStatusFlag(), XMC_UART_CH_EnableEvent() \n\n\n + */ +void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param service_request Service request number for generating protocol interrupts.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for UART channel protocol events.\n\n + * For all the protocol events enlisted in the enumeration XMC_UART_CH_EVENT_t, one common + * interrupt gets generated. The service request connects the interrupt node to the UART + * protocol events. + * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const uint8_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, + (uint32_t)service_request); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param interrupt_node Interrupt node pointer to be configured. \n + * \b Range: @ref XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, + * @ref XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc. + * @param service_request Service request number.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for USIC channel events. \n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_UART_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, + (uint32_t)service_request); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param service_request_line service request number of the event to be triggered. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Trigger a UART interrupt service request.\n\n + * When the UART service request is triggered, the NVIC interrupt associated with it will be + * generated if enabled. + * + * \parRelated APIs:
+ * XMC_UART_CH_SelectInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line) +{ + XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return Status of UART channel events. \n + * \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for + * event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE, @ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE, + * @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc. + * + * \parDescription
+ * Provides the status of UART channel events.\n\n + * Status provided by the API represents the status of multiple events at their bit positions. The bitmasks can be + * obtained using the enumeration XMC_UART_CH_STATUS_FLAG_t. Event status is obtained by reading + * the register PSR_ASCMode. + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableEvent(), XMC_UART_CH_ClearStatusFlag()\n\n\n + */ +__STATIC_INLINE uint32_t XMC_UART_CH_GetStatusFlag(XMC_USIC_CH_t *const channel) +{ + return channel->PSR_ASCMode; +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param flag UART events to be cleared. \n + * \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for + * event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE, @ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE, + * @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc. + * @return None + * + * \parDescription
+ * Clears the status of UART channel events.\n\n + * Multiple events can be combined using the bitwise OR operation and configured in one function call. + * XMC_UART_CH_STATUS_FLAG_t enumerates multiple event bitmasks. These enumerations can be used as input to the API. + * Events are cleared by setting the bitmask to the PSCR register. + * + * \parRelated APIs:
+ * XMC_UART_CH_DisableEvent(), XMC_UART_CH_GetStatusFlag()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag) +{ + channel->PSCR = flag; +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @param source Input source select for the input stage. The table provided below maps the decimal value with the input source. + * + * + *
0DXnA
1DXnB
2DXnC
3DXnD
4DXnE
5DXnF
6DXnG
7Always 1
+ * @return None + * + * \parDescription
+ * Sets input soource for the UART communication.\n\n + * It is used for configuring the input stage for data reception. + * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. + * The API can be used for the input stages DX0, DX3 and DX5. + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputInversion() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input, const uint8_t source) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~(USIC_CH_DX0CR_INSW_Msk|USIC_CH_DX0CR_DSEN_Msk))); + XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param pulse_length Length of the zero pulse in number of time quanta. \n + * \b Range: 0 to 7. + * @return None + * + * \parDescription
+ * Sets the length of zero pulse in number of time quanta. Value 0 indicates one time quanta.\n\n + * Maximum possible is 8 time quanta with the value configured as 7.\n + * The value is set to PCR_ASCMode register. + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n + * +*/ +__STATIC_INLINE void XMC_UART_CH_SetPulseLength(XMC_USIC_CH_t *const channel, const uint8_t pulse_length) +{ + channel->PCR_ASCMode = (uint32_t)(channel->PCR_ASCMode & (~USIC_CH_PCR_ASCMode_PL_Msk)) | + ((uint32_t)pulse_length << USIC_CH_PCR_ASCMode_PL_Pos); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param sample_point Sample point among the number of samples. \n + * \b Range: minimum= 0, maximum= \a oversampling (DCTQ). + * @return None + * + * \parDescription
+ * Sets the sample point among the multiple samples for each UART symbol.\n\n + * The sample point is the one sample among number of samples set as oversampling. The value should be less than + * the oversampling value. XMC_UART_CH_Init() sets the sample point to the sample at the centre. For + * example if the oversampling is 16, then the sample point is set to 9. + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetSamplePoint(XMC_USIC_CH_t *const channel, const uint32_t sample_point) +{ + channel->PCR_ASCMode = (uint32_t)((channel->PCR_ASCMode & (uint32_t)(~USIC_CH_PCR_ASCMode_SP_Msk)) | + (sample_point << USIC_CH_PCR_ASCMode_SP_Pos)); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * + * \parDescription
+ * Enables input inversion for UART input data signal.\n\n + * Polarity of the input source can be changed to provide inverted data input. + * \parRelated APIs:
+ * XMC_UART_CH_DisableInputInversion()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * + * \parDescription
+ * Disables input inversion for UART input data signal.\n\n + * Resets the input data polarity for the UART input data signal. + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputInversion()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * + * \parDescription
+ * Enables the digital filter for UART input stage.\n\n + * + * \parRelated APIs:
+ * XMC_UART_CH_DisableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_EnableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input); +} +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * + * \parDescription
+ * Disables the digital filter for UART input stage.\n\n + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_DisableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input); +} +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * \parDescription
+ * Enables synchronous input for the UART input stage.\n\n + * + * \parRelated APIs:
+ * XMC_UART_CH_DisableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_EnableInputSync(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_EnableInputSync(channel, (XMC_USIC_CH_INPUT_t)input); +} +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * + * \parDescription
+ * Disables synchronous input for the UART input stage.\n\n + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_DisableInputSync(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_DisableInputSync(channel, (XMC_USIC_CH_INPUT_t)input); +} +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @param sampling_freq Input sampling frequency. \n + * \b Range: @ref XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH, @ref XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER. + * @return None + * + * \parDescription
+ * Sets the sampling frequency for the UART input stage.\n\n + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel, + const XMC_UART_CH_INPUT_t input, + const XMC_UART_CH_INPUT_SAMPLING_FREQ_t sampling_freq) +{ + XMC_USIC_CH_SetInputSamplingFreq(channel, (XMC_USIC_CH_INPUT_t)input, (XMC_USIC_CH_INPUT_SAMPLING_FREQ_t)sampling_freq); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return None + * + * \parDescription
+ * Enable data transmission.\n\n + * Use this function in combination with XMC_UART_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode() + * + * \parRelated APIs:
+ * XMC_UART_CH_DisableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return None + * + * \parDescription
+ * Disable data transmission.\n\n + * Use this function in combination with XMC_UART_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usbd.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usbd.h new file mode 100644 index 00000000..5e94b5af --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usbd.h @@ -0,0 +1,989 @@ +/** + * @file xmc_usbd.h + * @date 2015-06-20 + * + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-16: + * - Initial Version.
+ * 2015-03-18: + * - Updated the doxygen comments for documentation.
+ * - Updated the XMC_USBD_PATCH_VERSION to 4.
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API.
+ * - Updated the doxygen comments for API XMC_USBD_IsEnumDone().
+ * - Updated the copy right in the file header.
+ * + * @endcond + * + */ + +#ifndef XMC_USBD_H +#define XMC_USBD_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ +#include "xmc_common.h" + +#if defined(USB0) + +#include +#include +#include "xmc_usbd_regs.h" +#include "xmc_scu.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup USBD + * @brief Universal Serial Bus Device (USBD) driver for the XMC4000 microcontroller family. + * + * The USBD is the device driver for the USB0 hardware module on XMC4000 family of microcontrollers. + * The USB0 module can be used to establish a USB interface between outside world and XMC4000 family of controllers. + * The USB module includes the following features in device mode: + * -# Complies with the USB 2.0 Specification. + * -# Support for the Full-Speed (12-Mbps) mode. + * -# Supports up to 7 bidirectional endpoints, including control endpoint 0. + * -# Supports SOFs in Full-Speed modes. + * -# Supports clock gating for power saving. + * -# Supports USB suspend/resume. + * -# Supports USB soft disconnect. + * -# Supports DMA mode. + * -# Supports FIFO mode. + * + * The below figure shows the overview of USB0 module in XMC4 microntroller. + * @image html USB_module_overview.png + * @image latex ../images/USB_module_overview.png + * + * The below figure shows the USB device connection of USB0 module. + * @image html USB_device_connection.png + * @image latex ../images/USB_device_connection.png + * + * The USBD device driver supports the following features:\n + * -# Initialize/Uninitialize the USB0 module on XMC4000 device. + * -# Connect the USB device to host. + * -# Get USB device state. + * -# Set the USB device address. + * -# Configure/Unconfigure the USB endpoints. + * -# Stall/Abort the USB endpoints. + * -# USB IN transfers on EP0 and non EP0 endpoints. + * -# USB OUT transfers on EP0 and non EP0 endpoints. + * + * The USBD device driver provides the configuration structure ::XMC_USBD_t which user need to configure before initializing the USB.\n + * The following elements of configuration structure need to be initialized before calling the ::XMC_USBD_Init API: + * -# cb_xmc_device_event of type ::XMC_USBD_SignalDeviceEvent_t. + * -# cb_endpoint_event of type ::XMC_USBD_SignalEndpointEvent_t. + * -# usbd_max_num_eps of type ::XMC_USBD_MAX_NUM_EPS_t. + * -# usbd_transfer_mode of type ::XMC_USBD_TRANSFER_MODE_t. + * + * @{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +#define XMC_USBD_NUM_TX_FIFOS (7U) /**< Number of hardware transmission endpoint fifos */ + +#define XMC_USBD_MAX_FIFO_SIZE (2048U) /**< Maximum USBD endpoint fifo size */ + +#define XMC_USBD_NUM_EPS (7U) /**< Number of hardware endpoints */ + +#define XMC_USBD_MAX_PACKET_SIZE (64U) /**< Maximum packet size for all endpoints + (including ep0) */ + +/**< Maximum transfer size for endpoints. + * + * It's based on the maximum payload, due to the fact, + * that we only can transfer 2^10 - 1 packets and this is less than the + * transfer size field can hold. + */ +#define XMC_USBD_MAX_TRANSFER_SIZE (((uint32_t)((uint32_t)1U << (uint32_t)10U) - 1U) * (uint32_t)XMC_USBD_MAX_PACKET_SIZE) + +#define XMC_USBD_MAX_TRANSFER_SIZE_EP0 (64U) /**< Maximum transfer size for endpoint 0*/ + +#define XMC_USBD_SETUP_COUNT (3U) /**< The number of USB setup packets */ + +#define XMC_USBD_SETUP_SIZE (8U) /**< The size of USB setup data */ + +#define XMC_USBD_EP_NUM_MASK (0x0FU) /**< USB Endpoint number mask. */ + +#define XMC_USBD_EP_DIR_MASK (0x80U) /**< USB Endpoint direction mask */ + +#define XMC_USBD_DCFG_DEVSPD_FS (0x3U) /*USB Full Speed device flag in DCFG register */ + +#define XMC_USBD_TX_FIFO_REG_OFFSET (0x1000U)/* First endpoint fifo register offset from base address */ + +#define XMC_USBD_TX_FIFO_OFFSET (0x1000U)/* Offset for each fifo register */ + +#define XMC_USBD_ENDPOINT_NUMBER_MASK (0x0FU) /**< USB Endpoint number mask to get the EP number from address. */ + +#define XMC_USBD_ENDPOINT_DIRECTION_MASK (0x80U) /**< USB Endpoint direction mask to get the EP direction from address. */ + +#define XMC_USBD_ENDPOINT_MAX_PACKET_SIZE_MASK (0x07FFU)/**< USB Endpoint Maximum Packet Size mask */ + +#define XMC_USBD_ENDPOINT_MFRAME_TR_MASK (0x1800U)/* USB Endpoint micro frame TR mask */ +#define XMC_USBD_ENDPOINT_MFRAME_TR_1 (0x0000U)/* Selects USB Endpoint micro frame TR1 */ +#define XMC_USBD_ENDPOINT_MFRAME_TR_2 (0x0800U)/* Selects USB Endpoint micro frame TR2 */ +#define XMC_USBD_ENDPOINT_MFRAME_TR_3 (0x1000U)/* Selects USB Endpoint micro frame TR3 */ + + +#define XMC_USBD_SPEED_FULL (1U) /**< Speed Mode. Full Speed */ + +#define XMC_USBD_EP0_BUFFER_SIZE (64U) /* Endpoint 0 buffer size */ + +#define XMC_USBD_EP1_BUFFER_SIZE (64U) /* Endpoint 1 buffer size */ + +#define XMC_USBD_EP2_BUFFER_SIZE (64U) /* Endpoint 2 buffer size */ + +#define XMC_USBD_EP3_BUFFER_SIZE (64U) /* Endpoint 3 buffer size */ + +#define XMC_USBD_EP4_BUFFER_SIZE (64U) /* Endpoint 4 buffer size */ + +#define XMC_USBD_EP5_BUFFER_SIZE (64U) /* Endpoint 5 buffer size */ + +#define XMC_USBD_EP6_BUFFER_SIZE (64U) /* Endpoint 6 buffer size */ + + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + +/** + * Defines the options for the global receive fifo packet status. + * Use type ::XMC_USBD_GRXSTS_PKTSTS_t for this enum. + * */ +typedef enum XMC_USBD_GRXSTS_PKTSTS { + XMC_USBD_GRXSTS_PKTSTS_GOUTNAK = 0x1U, /**< Global out nack send ( triggers an interrupt ) */ + XMC_USBD_GRXSTS_PKTSTS_OUTDATA = 0x2U, /**< OUT data packet received */ + XMC_USBD_GRXSTS_PKTSTS_OUTCMPL = 0x3U, /**< OUT transfer completed (triggers an interrupt) */ + XMC_USBD_GRXSTS_PKTSTS_SETUPCMPL = 0x4U, /**< SETUP transaction completed (triggers an interrupt) */ + XMC_USBD_GRXSTS_PKTSTS_SETUP = 0x6U /**< SETUP data packet received */ +} XMC_USBD_GRXSTS_PKTSTS_t; + +/** +* Defines the options for the USB endpoint type. The values are from the USB 2.0 specification. +* Use type ::XMC_USBD_ENDPOINT_TYPE_t for this enum. +*/ +typedef enum XMC_USBD_ENDPOINT_TYPE { + XMC_USBD_ENDPOINT_TYPE_CONTROL = 0x0U, /**< Control endpoint */ + XMC_USBD_ENDPOINT_TYPE_ISOCHRONOUS = 0x01U, /**< Isochronous endpoint */ + XMC_USBD_ENDPOINT_TYPE_BULK = 0x02U, /**< Bulk endpoint */ + XMC_USBD_ENDPOINT_TYPE_INTERRUPT = 0x03U /**< Interrupt endpoint */ +} XMC_USBD_ENDPOINT_TYPE_t; + + +/** +* Defines the options for USB device state while setting the address. +* Use type ::XMC_USBD_SET_ADDRESS_STAGE_t for this enum. +*/ +typedef enum XMC_USBD_SET_ADDRESS_STAGE { + XMC_USBD_SET_ADDRESS_STAGE_SETUP, /**< Setup address */ + XMC_USBD_SET_ADDRESS_STAGE_STATUS /**< Status address */ +} XMC_USBD_SET_ADDRESS_STAGE_t; + + +/** +* Defines the USB Device Status of executed operation. +* Use type ::XMC_USBD_STATUS_t for this enum. +*/ +typedef enum XMC_USBD_STATUS { + XMC_USBD_STATUS_OK = 0U, /**< USBD Status: Operation succeeded*/ + XMC_USBD_STATUS_BUSY = 2U, /**< Driver is busy and cannot handle request */ + XMC_USBD_STATUS_ERROR = 1U /**< USBD Status: Unspecified error*/ +} XMC_USBD_STATUS_t; + + +/** +* Defines the USB Device events. +* Use type ::XMC_USBD_EVENT_t for this enum. +*/ +typedef enum XMC_USBD_EVENT { + XMC_USBD_EVENT_POWER_ON, /**< USB Device Power On */ + XMC_USBD_EVENT_POWER_OFF, /**< USB Device Power Off */ + XMC_USBD_EVENT_CONNECT, /**< USB Device connected */ + XMC_USBD_EVENT_DISCONNECT, /**< USB Device disconnected */ + XMC_USBD_EVENT_RESET, /**< USB Reset occurred */ + XMC_USBD_EVENT_HIGH_SPEED, /**< USB switch to High Speed occurred */ + XMC_USBD_EVENT_SUSPEND, /**< USB Suspend occurred */ + XMC_USBD_EVENT_RESUME, /**< USB Resume occurred */ + XMC_USBD_EVENT_REMOTE_WAKEUP, /**< USB Remote wakeup */ + XMC_USBD_EVENT_SOF, /**< USB Start of frame event */ + XMC_USBD_EVENT_EARLYSUSPEND, /**< USB Early suspend */ + XMC_USBD_EVENT_ENUMDONE, /**< USB enumeration done */ + XMC_USBD_EVENT_ENUMNOTDONE, /**< USB enumeration not done */ + XMC_USBD_EVENT_OUTEP, /**< USB OUT endpoint */ + XMC_USBD_EVENT_INEP /**< USB IN endpoint */ +} XMC_USBD_EVENT_t; + +/** +* Defines the USB IN endpoint events. +* Use type ::XMC_USBD_EVENT_IN_EP_t for this enum. +*/ +typedef enum XMC_USBD_EVENT_IN_EP { + XMC_USBD_EVENT_IN_EP_TX_COMPLET = 1U, /**< USB IN ep transmission complete */ + XMC_USBD_EVENT_IN_EP_DISABLED = 2U, /**< USB IN ep disabled */ + XMC_USBD_EVENT_IN_EP_AHB_ERROR = 4U, /**< USB IN ep AHB error */ + XMC_USBD_EVENT_IN_EP_TIMEOUT = 8U, /**< USB IN ep timeout */ +} XMC_USBD_EVENT_IN_EP_t; + +/** +* Defines the USB OUT endpoint events. +* Use type ::XMC_USBD_EVENT_OUT_EP_t for this enum. +*/ +typedef enum XMC_USBD_EVENT_OUT_EP { + XMC_USBD_EVENT_OUT_EP_TX_COMPLET = 1U, /**< USB OUT ep transmission complete */ + XMC_USBD_EVENT_OUT_EP_DISABLED = 2U, /**< USB OUT ep disabled */ + XMC_USBD_EVENT_OUT_EP_AHB_ERROR = 4U, /**< USB OUT ep AHB error */ + XMC_USBD_EVENT_OUT_EP_SETUP = 8U, /**< USB OUT ep setup */ +} XMC_USBD_EVENT_OUT_EP_t; + + +/** +* Defines the generic USB endpoint events. +* Use type ::XMC_USBD_EP_EVENT_t for this enum. +*/ +typedef enum XMC_USBD_EP_EVENT { + XMC_USBD_EP_EVENT_SETUP, /**< SETUP packet*/ + XMC_USBD_EP_EVENT_OUT, /**< OUT packet*/ + XMC_USBD_EP_EVENT_IN /**< IN packet*/ +} XMC_USBD_EP_EVENT_t; + +/** +* Defines the options for the USB data transfer modes. +* Use type ::XMC_USBD_TRANSFER_MODE_t for this enum. +*/ +typedef enum XMC_USBD_TRANSFER_MODE { + XMC_USBD_USE_DMA, /**< Transfer by DMA*/ + XMC_USBD_USE_FIFO /**< Transfer by FIFO*/ +} XMC_USBD_TRANSFER_MODE_t; + +/** +* Defines the options for the maximum number of endpoints used. +* Use type ::XMC_USBD_MAX_NUM_EPS_t for this enum. +*/ +typedef enum XMC_USBD_MAX_NUM_EPS { + XMC_USBD_MAX_NUM_EPS_1 = 1U, /**< Maximum 1 endpoint used*/ + XMC_USBD_MAX_NUM_EPS_2 = 2U, /**< Maximum 2 endpoints used*/ + XMC_USBD_MAX_NUM_EPS_3 = 3U, /**< Maximum 3 endpoints used*/ + XMC_USBD_MAX_NUM_EPS_4 = 4U, /**< Maximum 4 endpoints used*/ + XMC_USBD_MAX_NUM_EPS_5 = 5U, /**< Maximum 5 endpoints used*/ + XMC_USBD_MAX_NUM_EPS_6 = 6U, /**< Maximum 6 endpoints used*/ + XMC_USBD_MAX_NUM_EPS_7 = 7U /**< Maximum 2 endpoints used*/ +} XMC_USBD_MAX_NUM_EPS_t; + +/** +* USB device/endpoint event function pointers +*/ +typedef void (*XMC_USBD_SignalDeviceEvent_t) (XMC_USBD_EVENT_t event);/**< Pointer to USB device event call back. + Uses type ::XMC_USBD_EVENT_t as the argument of callback.*/ +typedef void (*XMC_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, XMC_USBD_EP_EVENT_t ep_event);/**< Pointer to USB endpoint event call back. + Uses type ::XMC_USBD_EP_EVENT_t and EP address as the argument of callback.*/ + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ + +/** + * Describes the USB Device Driver Capabilities. + */ +typedef struct XMC_USBD_CAPABILITIES { + uint32_t event_power_on : 1; /**< Signal Power On event*/ + uint32_t event_power_off : 1; /**< Signal Power Off event*/ + uint32_t event_connect : 1; /**< Signal Connect event*/ + uint32_t event_disconnect : 1; /**< Signal Disconnect event*/ + uint32_t event_reset : 1; /**< Signal Reset event*/ + uint32_t event_high_speed : 1; /**< Signal switch to High-speed event*/ + uint32_t event_suspend : 1; /**< Signal Suspend event*/ + uint32_t event_resume : 1; /**< Signal Resume event*/ + uint32_t event_remote_wakeup : 1; /**< Signal Remote Wake up event*/ + uint32_t reserved : 23; /**< Reserved for future use*/ +} XMC_USBD_CAPABILITIES_t; + +/** + * Describes the current USB Device State. + */ +typedef struct XMC_USBD_STATE { + uint32_t powered : 1; /**< USB Device powered flag*/ + uint32_t connected : 1; /**< USB Device connected flag*/ + uint32_t active : 1; /**< USB Device active lag*/ + uint32_t speed : 2; /**< USB Device speed */ +} XMC_USBD_STATE_t; + +/** + * Describes a USB endpoint
+ * + * All information to control an endpoint is stored in this structure. + * It contains information about the endpoints and the status of the device. + */ +typedef struct { + union { + uint32_t address : 8; /**< The endpoint address including the direction */ + struct { + uint32_t number : 4; /**< The endpoint number.It can be from 0 to 6 */ + uint32_t pading : 3; /**< Padding between number and direction */ + uint32_t direction : 1; /**< The endpoint direction */ + } address_st; + } address_u; + uint32_t type : 2; /**< The endpoint type */ + uint32_t isConfigured : 1; /**< The flag showing, if the endpoint is configured */ + volatile uint32_t inInUse : 1; /**< Sets if the selected USB IN endpoint is currently in use */ + volatile uint32_t outInUse : 1; /**< Sets if the selected USB OUT endpoint is currently in use */ + uint32_t isStalled : 1; /**< Sets if the selected USB endpoint is stalled. */ + uint32_t txFifoNum : 4; /**< Endpoint transmit Fifo Number */ + uint32_t sendZeroLengthPacket : 1; /**< If set, a zero length packet will be send at the end of the transfer */ + uint32_t maxPacketSize : 7; /**< The maximum size of packet for USB endpoint ( due to FS Speed device only 64 Byte )*/ + uint32_t maxTransferSize : 19; /**< The maximum amount of data the core can send at once.*/ + uint8_t *outBuffer; /**< The buffer for operation as OUT endpoint */ + uint32_t outBytesAvailable; /**< The number of bytes available in the EP OUT buffer */ + uint32_t outBufferSize; /**< The size of the EP OUT buffer */ + uint32_t outOffset; /**< The read offset of the EP OUT buffer */ + uint8_t *inBuffer; /**< The buffer for operation as IN endpoint */ + uint32_t inBufferSize; /**< The size of the EP IN buffer */ + uint8_t *xferBuffer; /**< The buffer of the current transfer */ + uint32_t xferLength; /**< The length of the current transfer */ + uint32_t xferCount; /**< Bytes transfered of the current USB data transfer */ + uint32_t xferTotal; /**< The length of total data in buffer */ +} XMC_USBD_EP_t; + +/** + * Describes the XMC USB device
+ * + * All information to control an XMC USB device is stored in + * this structure. It contains register, callbacks, information + * about the endpoints and the status of the device. + */ +typedef struct XMC_USBD_DEVICE { + XMC_USBD_EP_t ep[8]; /**< Endpoints of the USB device. It is of type ::XMC_USBD_EP_t */ + dwc_otg_core_global_regs_t *global_register; /**< Global register interface */ + dwc_otg_device_global_regs_t *device_register; /**< Device register interface */ + dwc_otg_dev_in_ep_regs_t *endpoint_in_register[(uint8_t)XMC_USBD_NUM_EPS];/**< IN Endpoint register interface */ + dwc_otg_dev_out_ep_regs_t *endpoint_out_register[(uint8_t)XMC_USBD_NUM_EPS];/**< OUT Endpoint register interface */ + volatile uint32_t *fifo[(uint8_t)XMC_USBD_NUM_TX_FIFOS]; /**< Transmit fifo interface */ + uint16_t txfifomsk; /**< Mask of used TX fifos */ + uint32_t IsConnected : 1; /**< Sets if device is connected */ + uint32_t IsActive : 1; /**< Sets if device is currently active */ + uint32_t IsPowered : 1; /**< Sets if device is powered by Vbus */ + XMC_USBD_SignalDeviceEvent_t DeviceEvent_cb; /**< The USB device event callback. */ + XMC_USBD_SignalEndpointEvent_t EndpointEvent_cb; /**< The USB endpoint event callback. */ +} XMC_USBD_DEVICE_t; + + +/** + * USB device initialization structure + */ +typedef struct XMC_USBD_OBJ +{ + USB0_GLOBAL_TypeDef *const usbd; /**< USB Module Pointer. The USB0 module base address. */ + XMC_USBD_SignalDeviceEvent_t cb_xmc_device_event; /**< USB device event callback. Use ::XMC_USBD_SignalDeviceEvent_t type of function pointer. */ + XMC_USBD_SignalEndpointEvent_t cb_endpoint_event; /**< USB endpoint event callback. Use ::XMC_USBD_SignalEndpointEvent_t type of function pointer.*/ + XMC_USBD_MAX_NUM_EPS_t usbd_max_num_eps; /**< Maximum number of end points used. The maximum range can be 7.*/ + XMC_USBD_TRANSFER_MODE_t usbd_transfer_mode; /**< USB data transfer mode.Use ::XMC_USBD_TRANSFER_MODE_t type to specify the transfer mode. */ +} XMC_USBD_t; + +/** + * Defines the access structure of the USB Device Driver. + */ +typedef struct XMC_USBD_DRIVER { + + + XMC_USBD_CAPABILITIES_t (*GetCapabilities) (void); /**< Pointer to @ref XMC_USBD_GetCapabilities : Get driver capabilities.*/ + + + XMC_USBD_STATUS_t (*Initialize) (XMC_USBD_t *obj); /**< Pointer to @ref XMC_USBD_Init : Initialize USB Device Interface.*/ + + + XMC_USBD_STATUS_t (*Uninitialize) (void); /**< Pointer to @ref XMC_USBD_Uninitialize : De-initialize USB Device Interface.*/ + + + XMC_USBD_STATUS_t (*DeviceConnect) (void); /**< Pointer to @ref XMC_USBD_DeviceConnect : Connect USB Device.*/ + + + XMC_USBD_STATUS_t (*DeviceDisconnect) (void); /**< Pointer to @ref XMC_USBD_DeviceDisconnect : Disconnect USB Device.*/ + + + XMC_USBD_STATE_t (*DeviceGetState) (const XMC_USBD_t *const obj); /**< Pointer to @ref XMC_USBD_DeviceGetState : Get current USB Device State.*/ + + + XMC_USBD_STATUS_t (*DeviceSetAddress) (uint8_t dev_addr, XMC_USBD_SET_ADDRESS_STAGE_t stage);/**< Pointer to @ref XMC_USBD_DeviceSetAddress : Set USB Device Address.*/ + + + XMC_USBD_STATUS_t (*EndpointConfigure) (uint8_t ep_addr,XMC_USBD_ENDPOINT_TYPE_t ep_type, uint16_t ep_max_packet_size);/**< Pointer to @ref XMC_USBD_EndpointConfigure : Configure USB Endpoint.*/ + + + XMC_USBD_STATUS_t (*EndpointUnconfigure)(uint8_t ep_addr); /**< Pointer to @ref XMC_USBD_EndpointUnconfigure : Unconfigure USB Endpoint.*/ + + + XMC_USBD_STATUS_t (*EndpointStall) (uint8_t ep_addr, bool stall); /**< Pointer to @ref XMC_USBD_EndpointStall : Set/Clear Stall for USB Endpoint.*/ + + + XMC_USBD_STATUS_t (*EndpointReadStart) (uint8_t ep_addr, uint32_t len); /**< Pointer to @ref XMC_USBD_EndpointReadStart : Start USB Endpoint Read operation.*/ + + + int32_t (*EndpointRead) (uint8_t ep_addr, uint8_t *buf, uint32_t len);/**< Pointer to @ref XMC_USBD_EndpointRead : Read data from USB Endpoint.*/ + + + int32_t (*EndpointWrite) (uint8_t ep_addr, const uint8_t *buf, uint32_t len); /**< Pointer to @ref XMC_USBD_EndpointWrite : Write data to USB Endpoint.*/ + + + XMC_USBD_STATUS_t (*EndpointAbort) (uint8_t ep_addr); /**< Pointer to @ref XMC_USBD_EndpointAbort : Abort current USB Endpoint transfer.*/ + + + uint16_t (*GetFrameNumber) (void); /**< Pointer to @ref XMC_USBD_GetFrameNumber : Get current USB Frame Number.*/ + + + uint32_t (*IsEnumDone) (void); /**< Pointer to @ref XMC_USBD_IsEnumDone : Is enumeration done in Host?.*/ +} const XMC_USBD_DRIVER_t; + +/** + * Defines the driver interface function table. + * To access the XMC device controller driver interface use this table of functions. + **/ +extern const XMC_USBD_DRIVER_t Driver_USBD0; + + +/** + * Defines the XMC USB device data + * The instance of ::XMC_USBD_DEVICE_t structure describing the XMC device. + **/ +extern XMC_USBD_DEVICE_t xmc_device; + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param None. + * + * @return None. + * + * \parDescription:
+ * Enables the USB module in the XMC controller.
+ * It de-asserts the peripheral reset on USB0 module and enables the USB power. + * + * \parNote:
+ * This API is called inside the XMC_USBD_Init().\n + * + * \parRelated APIs:
+ * XMC_USBD_Disable()\n + **/ +void XMC_USBD_Enable(void); + +/** + * @param None. + * + * @return None. + * + * \parDescription:
+ * Disables the USB module in the XMC controller.
+ * It asserts the peripheral reset on USB0 module and disables the USB power. + * + * \parRelated APIs:
+ * XMC_USBD_Enable()\n + **/ +void XMC_USBD_Disable(void); + +/** + * @param event The single event that needs to be cleared. Use ::XMC_USBD_EVENT_t as argument.\n + * + * @return None. + * + * \parDescription:
+ * Clears the selected USBD \a event.
+ * It clears the event by writing to the GINTSTS register. + * + * \parNote:
+ * This API is called inside the USB interrupt handler to clear the event XMC_USBD_EVENT_t + * and maintain the device state machine.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_ClearEventOUTEP(),::XMC_USBD_ClearEventINEP()\n + **/ +void XMC_USBD_ClearEvent(XMC_USBD_EVENT_t event); + + +/** + * @param event The single event or multiple events that need to be cleared. + * + * @param ep_num The IN endpoint number on which the events to be cleared. + * + * @return None. + * + * \parDescription:
+ * Clears the single event or multiple events of the selected IN endpoint.
+ * The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_IN_EP_t elements.\n + * It clears the event by programming DIEPINT register.\n + * + * \parNote:
+ * This API is called inside the USB IN EP interrupt handler to clear the ::XMC_USBD_EVENT_IN_EP_t event + * and maintain the device state machine.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_ClearEventOUTEP()\n + **/ +void XMC_USBD_ClearEventINEP(uint32_t event,uint8_t ep_num); + + +/** + * @param event The single event or multiple events that need to be cleared. + * + * @param ep_num The OUT endpoint number on which the events to be cleared. + * + * @return None. + * + * \parDescription:
+ * Clears the single \a event or multiple events of the selected OUT endpoint.
+ * The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_OUT_EP_t elements. + * It clears the event by writing to DOEPINT register. + * + * \parNote:
+ * This API is called inside the USB OUT EP interrupt handler to clear the ::XMC_USBD_EVENT_OUT_EP_t event + * and maintain the device state machine.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_ClearEventINEP()\n + **/ +void XMC_USBD_ClearEventOUTEP(uint32_t event,uint8_t ep_num); + +/** + * @param event The single event or multiple events that need to be enabled. + * + * @return None. + * + * \parDescription:
+ * Enables the event or multiple events of the OUT endpoints.
+ * The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_OUT_EP_t elements. + * It enables the event by programming DOEPMSK register. + * + * \parNote:
+ * This API is called inside the ::XMC_USBD_Init() to enable the OUT EP interrupts.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_EnableEventINEP()\n + **/ +void XMC_USBD_EnableEventOUTEP(uint32_t event); + +/** + * @param event The single event or multiple events that need to be enabled. + * + * @return None. + * + * \parDescription:
+ * Enables the \a event or multiple events of the USB IN endpoints.
+ * The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_IN_EP_t elements. + * It enables the event by programming DIEPMSK register. + * + * \parNote:
+ * This API is called inside the ::XMC_USBD_Init() to enable the IN EP interrupts.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_EnableEventOUTEP()\n + **/ +void XMC_USBD_EnableEventINEP(uint32_t event); + +/** + * @param None. + * + * @return ::XMC_USBD_CAPABILITIES_t. + * + * \parDescription:
+ * Retrieves the USB device capabilities of type \a XMC_USBD_CAPABILITIES_t
+ * The USB device capabilities supported by the USBD driver, like power on/off, connect/disconnect, + * reset,suspend/resume,USB speed etc are retrieved. + * + * It can be called after initializing the USB device to get the information on the USBD capabilities. + * + **/ +XMC_USBD_CAPABILITIES_t XMC_USBD_GetCapabilities(void); + + +/** + * @param obj The pointer to the USB device handle ::XMC_USBD_t. + * + * @return XMC_USBD_STATUS_t The USB device status of type ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Initializes the USB device to get ready for connect to USB host.
+ * Enables the USB module,sets the EP buffer sizes,registers the device and EP event call backs. + * Initializes the global,device and FIFO register base addresses. + * Configures the global AHB,enables the global interrupt and DMA by programming GAHBCFG register. + * Configures the USB in to device mode and enables the session request protocol by programming GUSBCFG register. + * Configures the USB device speed to full speed by programming DCFG register. + * Disconnects the USB device by programming DCTL register. + * Enables the USB common and device interrupts by programming GINTMSK register. + * + * \parNote:
+ * This API makes the USB device ready to connect to host.The user has to explicitly call + * the ::XMC_USBD_DeviceConnect() after the USB initialization to connect to USB host.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_DeviceConnect()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_Init(XMC_USBD_t *obj); + +/** + * @param None. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Uninitialises the USB device.
+ * Disconnects the USB device by programming DCTL register and resets the XMC USB device data. + * + * \parNote:
+ * Once this API is called, USB device will not be accessible from host.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_Init()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_Uninitialize(void); + +/** + * @param None. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Connects the USB device to host and triggers the USB enumeration.
+ * Connects the USB device to host by programming DCTL register.\n + * It resets the soft disconnect bit, which activates the speed pull up at d+ line of USB. + * ::XMC_USBD_Init() should be called before calling this API. + * + * \parNote:
+ * Once this API is called, USB host starts the enumeration process and the device should + * handle the descriptor requests.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_Init()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceConnect(void); + +/** + * @param None. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Disconnects the USB device from host.
+ * By programming DCTL register, it sets the soft disconnect bit, which deactivates\n + * the speed pull up at d+ line of USB. + * + * \parNote:
+ * Once this API is called, USB device will not be accessible from host.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_DeviceConnect()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceDisconnect(void); + +/** + * @param obj The pointer to the USB device handle structure \a XMC_USBD_t. + * + * @return ::XMC_USBD_STATE_t. + * + * \parDescription:
+ * Retrieves the current USB device state.
+ * Power,active,speed and connection status data are retrieved.\n + * + * \parNote:
+ * Before calling this API, USB should be initialized with ::XMC_USBD_Init.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_Init()\n + **/ +XMC_USBD_STATE_t XMC_USBD_DeviceGetState(const XMC_USBD_t *const obj); + + +/** + * @param address The address to be set for the USB device . + * @param stage The device request stage-setup or status ::XMC_USBD_SET_ADDRESS_STAGE_t. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Sets the USB device address.
+ * The device address is programmed in the DCFG register.
+ * + * The address should be more than 0; as 0 is the default USB device address at the starting of enumeration. + * As part of enumeration, host sends the control request to the device to set the USB address; and in turn,\n + * in the USB device event call back handler, user has to set the address using this API for the set address request.
+ * + * The stage parameter should be XMC_USBD_SET_ADDRESS_STAGE_SETUP from the enum ::XMC_USBD_SET_ADDRESS_STAGE_t. + * + * \parNote:
+ * Before calling this API, USB should be initialized with ::XMC_USBD_Init () and connected to + * USB host using ::XMC_USBD_DeviceConnect() \n + * + * \parRelated APIs:
+ * ::XMC_USBD_Init(), ::XMC_USBD_DeviceConnect()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceSetAddress(uint8_t address,XMC_USBD_SET_ADDRESS_STAGE_t stage); + +/** + * @param ep_addr The address of the USB endpoint, which needs to be configured. + * @param ep_type The ::XMC_USBD_ENDPOINT_TYPE_t. + * @param ep_max_packet_size The maximum packet size of endpoint in USB full speed. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Configures the USB endpoint.
+ * The endpoint is configured by programming the DAINT,DIEPCTL and DOEPCTL registers.
+ * + * Configures the EP type, FIFO number,maximum packet size, enables endpoint and sets the DATA0 PID. + * This function also initializes the internal buffer handling for the specified endpoint, + * but does not start any transfers.
+ * + * As part of enumeration, host sends the control request to the device to set the configuration; and in turn,\n + * in the USB device event call back handler, user has to set the configuration and configure the endpoints \n + * required for the device.\n + * + * \parNote:
+ * This API should only be used as part of enumeration.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_Init(),::XMC_USBD_DeviceConnect(),::XMC_USBD_EndpointUnconfigure()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointConfigure(uint8_t ep_addr, + XMC_USBD_ENDPOINT_TYPE_t ep_type, + uint16_t ep_max_packet_size); + +/** + * @param ep_addr The address of the USB endpoint, which needs to be unconfigured. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Unconfigures the USB endpoint.
+ * The endpoint is unconfigured by programming the DAINT,DIEPCTL and DOEPCTL registers.\n + * Disables the endpoint, unassign the fifo, deactivate it and only send nacks.\n + * Waits until the endpoint has finished operation and disables it. All (eventuallly) allocated buffers gets freed. + * Forces the endpoint to stop immediately, any pending transfers are killed(Can cause device reset). + * + * \parRelated APIs:
+ * ::XMC_USBD_EndpointConfigure()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointUnconfigure(uint8_t ep_addr); + +/** + * @param ep_addr The address of the USB endpoint, on which stall needs to be set or cleared. + * @param stall The boolean variable to decide on set or clear of stall on EP. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Set or Clear stall on the USB endpoint \a ep_addr, based on \a stall parameter.
+ * + * By programming stall bit in the doepctl and diepctl, it sets or clears the stall on the endpoint. + * The endpoint can be stalled when a non supported request comes from the USB host. + * The XMC_USBD_EndpointStall() should be called with \a stall set to 0, in the clear feature standard request + * in the USB device event call back handler. * + * + * \parNote:
+ * The host should clear the stall set on the endpoint by sending the clear feature standard + * request on the non EP0 endpoints. On EP0, the stall will automatically gets cleared on the next control request.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_EndpointAbort()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointStall(uint8_t ep_addr, bool stall); + + +/** + * @param ep_addr The address of the USB endpoint, from which data need to be read. + * @param size The number of bytes to be read. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Prepares an endpoint to receive OUT tokens from the USB host.
+ * The selected endpoint gets configured, so that it receives the specified amount of data from the host. + * As part of streaming of OUT data, after reading the current OUT buffer using ::XMC_USBD_EndpointRead(),\n + * user can prepare endpoint for the next OUT packet by using ::XMC_USBD_EndpointReadStart(). + * + * The registers DOEPDMA,DOEPTSIZ and DOEPCTL are programmed to start a new read request. + * + * \parNote:
+ * For the data received on OUT EP buffer, use ::XMC_USBD_EndpointRead().\n + * + * \parRelated APIs:
+ * XMC_USBD_EndpointRead()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointReadStart(const uint8_t ep_addr, uint32_t size); + + +/** + * @param ep_addr The address of the USB OUT endpoint, from which data need to be read. + * @param buffer The pointer to the user buffer,in which data need to be received. + * @param length The number of bytes to be read from OUT EP. + * + * @return
+ * The actual number of bytes received. + * + * \parDescription:
+ * Read \a length number of bytes from an OUT endpoint \a ep_addr.
+ * If data has been received for this endpoint, it gets copied into the user buffer until its full + * or no data is left in the driver buffer. + * + * \parNote:
+ * For preparing the next OUT token, use ::XMC_USBD_EndpointReadStart() after ::XMC_USBD_EndpointRead().\n + * + * + * \parRelated APIs:
+ * ::XMC_USBD_EndpointReadStart()\n + **/ +int32_t XMC_USBD_EndpointRead(const uint8_t ep_addr,uint8_t * buffer, uint32_t length); + + +/** + * @param ep_addr The address of the USB IN endpoint, on which data should be sent. + * @param buffer The pointer to the data buffer, to write to the endpoint. + * @param length The number of bytes to be written to IN EP. + * + * @return
+ * The actual amount of data written to the endpoint buffer. + * + * \parDescription:
+ * Write the \a length bytes of data to an IN endpoint \a ep_addr.
+ * The User data gets copied into the driver buffer or will be send directly based on the buffer concept + * selected in the ::XMC_USBD_TRANSFER_MODE_t configuration. + * + * Then the endpoint is set up to transfer the data to the host.\n + * DIEPDMA,DIEPTSIZ and DIEPCTL registers are programmed to start the IN transfer. + * + * + * \parRelated APIs:
+ * ::XMC_USBD_EndpointRead()\n + **/ +int32_t XMC_USBD_EndpointWrite(const uint8_t ep_addr,const uint8_t * buffer,uint32_t length); + + +/** + * @param ep_addr The address of the USB endpoint, on which the data need to be aborted. + * + * @return ::XMC_USBD_STATUS_t + * + * \parDescription:
+ * Abort the transfer on endpoint \a ep_addr.
+ * On any failure with the USB transmission user can reset the endpoint into default state and clear all + * assigned buffers, to start from a clean point. The endpoint will not be unconfigured or disabled. + * + * \parRelated APIs:
+ * ::XMC_USBD_EndpointUnconfigure()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointAbort(uint8_t ep_addr); + +/** + * @param None. + * + * @return The 16 bit current USB frame number. + * + * \parDescription:
+ * Read the current USB frame number.
* + * Reads the device status register (DSTS) and returns the SOFFN field. + * + **/ +uint16_t XMC_USBD_GetFrameNumber(void); + +/** + * @param None. + * + * @return Returns 1, if the speed enumeration is done and 0 otherwise. + * + * \parDescription:
+ * Gets the speed enumeration completion status of the USB device.
+ * + * \parNote:
+ * This should not be used for the actual USB enumeration completion status. For the actual USB enumeration status, + * the application layer should check for the completion of USB standard request 'Set configuration'.\n + * + **/ +uint32_t XMC_USBD_IsEnumDone(void); + + +/** + * @param obj The pointer to the USB device handle structure. + * + * @return None. + * + * \parDescription:
+ * USB device default IRQ handler.
+ * USBD Peripheral LLD provides default implementation of ISR. + * The user needs to explicitly either use our default implementation or use its own one using the LLD APIs. + * + * For example: + * XMC_USBD_t *obj; + * void USB0_0_IRQHandler(void) + * { + * XMC_USBD_IRQHandler(obj); + * } + * + * \parNote:
+ * The user should initialize the XMC USB device configuration structure before calling + * ::XMC_USBD_IRQHandler() in the actual USB0 IRQ handler. + * + **/ +void XMC_USBD_IRQHandler(const XMC_USBD_t *const obj); + +#ifdef __cplusplus +} +#endif + +/** + * MISRA C 2004 Deviations + * + * 1. Function like macro- defined- MISRA Advisory Rule 19.7 + * 2. usage of unions - MISRA Required Rule 18.4 + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(USB0) */ + +#endif /* XMC_USBD_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usbd_regs.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usbd_regs.h new file mode 100644 index 00000000..df31cb45 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usbd_regs.h @@ -0,0 +1,2595 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ + * $Revision: #91 $ + * $Date: 2010/11/29 $ + * $Change: 1636033 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +/* + * @file xmc_usbd_regs.h + * @date 2015-02-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial version + * + * @endcond + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + + +/** + * @file + * + * This file contains the data structures for accessing the DWC_otg core registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/** Register Definitions */ +/** Maximum endpoint channel */ +#define MAX_EPS_CHANNELS ( 7U ) +/** Maximum periodic fifos in usb core */ +#define MAX_PERIO_FIFOS ( 1U ) +/** Maximum tx fifos */ +#define MAX_TX_FIFOS ( 14U ) +/* dwc_dma_t type definition and register header file inclusion */ +typedef void* dwc_dma_t; + +/****************************************************************************/ +/** DWC_otg Core registers . + * The dwc_otg_core_global_regs structure defines the size + * and relative field offsets for the Core Global registers. + */ +typedef struct dwc_otg_core_global_regs { + /** OTG Control and Status Register. Offset: 000h */ + volatile uint32_t gotgctl; + /** OTG Interrupt Register. Offset: 004h */ + volatile uint32_t gotgint; + /**Core AHB Configuration Register. Offset: 008h */ + volatile uint32_t gahbcfg; + +#define DWC_GLBINTRMASK 0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 +#define DWC_PTXEMPTYLVL_EMPTY 0x0100 +#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 + + /**Core USB Configuration Register. Offset: 00Ch */ + volatile uint32_t gusbcfg; + /**Core Reset Register. Offset: 010h */ + volatile uint32_t grstctl; + /**Core Interrupt Register. Offset: 014h */ + volatile uint32_t gintsts; + /**Core Interrupt Mask Register. Offset: 018h */ + volatile uint32_t gintmsk; + /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ + volatile uint32_t grxstsr; + /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ + volatile uint32_t grxstsp; + /**Receive FIFO Size Register. Offset: 024h */ + volatile uint32_t grxfsiz; + /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ + volatile uint32_t gnptxfsiz; + /**Non Periodic Transmit FIFO/Queue Status Register (Read + * Only). Offset: 02Ch */ + volatile uint32_t gnptxsts; + /**I2C Access Register. Offset: 030h */ + volatile uint32_t gi2cctl; + /**PHY Vendor Control Register. Offset: 034h */ + volatile uint32_t gpvndctl; + /**General Purpose Input/Output Register. Offset: 038h */ + volatile uint32_t ggpio; + /**User ID Register. Offset: 03Ch */ + volatile uint32_t guid; + /**Synopsys ID Register (Read Only). Offset: 040h */ + volatile uint32_t gsnpsid; + /**User HW Config1 Register (Read Only). Offset: 044h */ + volatile uint32_t ghwcfg1; + /**User HW Config2 Register (Read Only). Offset: 048h */ + volatile uint32_t ghwcfg2; +#define DWC_SLAVE_ONLY_ARCH 0 +#define DWC_EXT_DMA_ARCH 1 +#define DWC_INT_DMA_ARCH 2 + +#define DWC_MODE_HNP_SRP_CAPABLE 0 +#define DWC_MODE_SRP_ONLY_CAPABLE 1 +#define DWC_MODE_NO_HNP_SRP_CAPABLE 2 +#define DWC_MODE_SRP_CAPABLE_DEVICE 3 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 +#define DWC_MODE_SRP_CAPABLE_HOST 5 +#define DWC_MODE_NO_SRP_CAPABLE_HOST 6 + + /**User HW Config3 Register (Read Only). Offset: 04Ch */ + volatile uint32_t ghwcfg3; + /**User HW Config4 Register (Read Only). Offset: 050h*/ + volatile uint32_t ghwcfg4; + /** Core LPM Configuration register Offset: 054h*/ + volatile uint32_t glpmcfg; + /** Global PowerDn Register Offset: 058h */ + volatile uint32_t gpwrdn; + /** Global DFIFO SW Config Register Offset: 05Ch */ + volatile uint32_t gdfifocfg; + /** ADP Control Register Offset: 060h */ + volatile uint32_t adpctl; + /** Reserved Offset: 064h-0FFh */ + volatile uint32_t reserved39[39]; + /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ + volatile uint32_t hptxfsiz; + /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, + otherwise Device Transmit FIFO#n Register. + * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ + volatile uint32_t dtxfsiz[15]; +} dwc_otg_core_global_regs_t; + +/** + * This union represents the bit fields of the Core OTG Control + * and Status Register (GOTGCTL). Set the bits using the bit + * fields then write the d32 value to the register. + */ +typedef union gotgctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned sesreqscs:1; + unsigned sesreq:1; + unsigned vbvalidoven:1; + unsigned vbvalidovval:1; + unsigned avalidoven:1; + unsigned avalidovval:1; + unsigned bvalidoven:1; + unsigned bvalidovval:1; + unsigned hstnegscs:1; + unsigned hnpreq:1; + unsigned hstsethnpen:1; + unsigned devhnpen:1; + unsigned reserved12_15:4; + unsigned conidsts:1; + unsigned dbnctime:1; + unsigned asesvld:1; + unsigned bsesvld:1; + unsigned otgver:1; + unsigned reserved1:1; + unsigned multvalidbc:5; + unsigned chirpen:1; + unsigned reserved28_31:4; + } b; +} gotgctl_data_t; + +/** + * This union represents the bit fields of the Core OTG Interrupt Register + * (GOTGINT). Set/clear the bits using the bit fields then write the d32 + * value to the register. + */ +typedef union gotgint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Current Mode */ + unsigned reserved0_1:2; + + /** Session End Detected */ + unsigned sesenddet:1; + + unsigned reserved3_7:5; + + /** Session Request Success Status Change */ + unsigned sesreqsucstschng:1; + /** Host Negotiation Success Status Change */ + unsigned hstnegsucstschng:1; + + unsigned reserved10_16:7; + + /** Host Negotiation Detected */ + unsigned hstnegdet:1; + /** A-Device Timeout Change */ + unsigned adevtoutchng:1; + /** Debounce Done */ + unsigned debdone:1; + /** Multi-Valued input changed */ + unsigned mvic:1; + + + unsigned reserved31_21:11; + + } b; +} gotgint_data_t; + +/** + * This union represents the bit fields of the Core AHB Configuration + * Register (GAHBCFG). Set/clear the bits using the bit fields then + * write the d32 value to the register. + */ +typedef union gahbcfg_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned glblintrmsk:1; +#define DWC_GAHBCFG_GLBINT_ENABLE 1 + + unsigned hburstlen:4; +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 + + unsigned dmaenable:1; +#define DWC_GAHBCFG_DMAENABLE 1 + unsigned reserved:1; + unsigned nptxfemplvl_txfemplvl:1; + unsigned ptxfemplvl:1; +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 + unsigned reserved9_20:12; + unsigned remmemsupp:1; + unsigned notialldmawrit:1; + unsigned reserved23_31:9; + } b; +} gahbcfg_data_t; + +/** + * This union represents the bit fields of the Core USB Configuration + * Register (GUSBCFG). Set the bits using the bit fields then write + * the d32 value to the register. + */ +typedef union gusbcfg_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned toutcal:3; + unsigned phyif:1; + unsigned ulpi_utmi_sel:1; + unsigned fsintf:1; + unsigned physel:1; + unsigned ddrsel:1; + unsigned srpcap:1; + unsigned hnpcap:1; + unsigned usbtrdtim:4; + unsigned reserved1:1; + unsigned phylpwrclksel:1; + unsigned otgutmifssel:1; + unsigned ulpi_fsls:1; + unsigned ulpi_auto_res:1; + unsigned ulpi_clk_sus_m:1; + unsigned ulpi_ext_vbus_drv:1; + unsigned ulpi_int_vbus_indicator:1; + unsigned term_sel_dl_pulse:1; + unsigned indicator_complement:1; + unsigned indicator_pass_through:1; + unsigned ulpi_int_prot_dis:1; + unsigned ic_usb_cap:1; + unsigned ic_traffic_pull_remove:1; + unsigned tx_end_delay:1; + unsigned force_host_mode:1; + unsigned force_dev_mode:1; + unsigned reserved31:1; + } b; +} gusbcfg_data_t; + +/** + * This union represents the bit fields of the Core Reset Register + * (GRSTCTL). Set/clear the bits using the bit fields then write the + * d32 value to the register. + */ +typedef union grstctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Core Soft Reset (CSftRst) (Device and Host) + * + * The application can flush the control logic in the + * entire core using this bit. This bit resets the + * pipelines in the AHB Clock domain as well as the + * PHY Clock domain. + * + * The state machines are reset to an IDLE state, the + * control bits in the CSRs are cleared, all the + * transmit FIFOs and the receive FIFO are flushed. + * + * The status mask bits that control the generation of + * the interrupt, are cleared, to clear the + * interrupt. The interrupt status bits are not + * cleared, so the application can get the status of + * any events that occurred in the core after it has + * set this bit. + * + * Any transactions on the AHB are terminated as soon + * as possible following the protocol. Any + * transactions on the USB are terminated immediately. + * + * The configuration settings in the CSRs are + * unchanged, so the software doesn't have to + * reprogram these registers (Device + * Configuration/Host Configuration/Core System + * Configuration/Core PHY Configuration). + * + * The application can write to this bit, any time it + * wants to reset the core. This is a self clearing + * bit and the core clears this bit after all the + * necessary logic is reset in the core, which may + * take several clocks, depending on the current state + * of the core. + */ + unsigned csftrst:1; + /** Hclk Soft Reset + * + * The application uses this bit to reset the control logic in + * the AHB clock domain. Only AHB clock domain pipelines are + * reset. + */ + unsigned hsftrst:1; + /** Host Frame Counter Reset (Host Only)
+ * + * The application can reset the (micro)frame number + * counter inside the core, using this bit. When the + * (micro)frame counter is reset, the subsequent SOF + * sent out by the core, will have a (micro)frame + * number of 0. + */ + unsigned hstfrm:1; + /** In Token Sequence Learning Queue Flush + * (INTknQFlsh) (Device Only) + */ + unsigned intknqflsh:1; + /** RxFIFO Flush (RxFFlsh) (Device and Host) + * + * The application can flush the entire Receive FIFO + * using this bit. The application must first + * ensure that the core is not in the middle of a + * transaction. The application should write into + * this bit, only after making sure that neither the + * DMA engine is reading from the RxFIFO nor the MAC + * is writing the data in to the FIFO. The + * application should wait until the bit is cleared + * before performing any other operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) + * to clear. + */ + unsigned rxfflsh:1; + /** TxFIFO Flush (TxFFlsh) (Device and Host). + * + * This bit is used to selectively flush a single or + * all transmit FIFOs. The application must first + * ensure that the core is not in the middle of a + * transaction. The application should write into + * this bit, only after making sure that neither the + * DMA engine is writing into the TxFIFO nor the MAC + * is reading the data out of the FIFO. The + * application should wait until the core clears this + * bit, before performing any operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) + * to clear. + */ + unsigned txfflsh:1; + + /** TxFIFO Number (TxFNum) (Device and Host). + * + * This is the FIFO number which needs to be flushed, + * using the TxFIFO Flush bit. This field should not + * be changed until the TxFIFO Flush bit is cleared by + * the core. + * - 0x0 : Non Periodic TxFIFO Flush + * - 0x1 : Periodic TxFIFO #1 Flush in device mode + * or Periodic TxFIFO in host mode + * - 0x2 : Periodic TxFIFO #2 Flush in device mode. + * - ... + * - 0xF : Periodic TxFIFO #15 Flush in device mode + * - 0x10: Flush all the Transmit NonPeriodic and + * Transmit Periodic FIFOs in the core + */ + unsigned txfnum:5; + /** Reserved */ + unsigned reserved11_29:19; + /** DMA Request Signal. Indicated DMA request is in + * probress. Used for debug purpose. */ + unsigned dmareq:1; + /** AHB Master Idle. Indicates the AHB Master State + * Machine is in IDLE condition. */ + unsigned ahbidle:1; + } b; +} grstctl_t; + +/** + * This union represents the bit fields of the Core Interrupt Mask + * Register (GINTMSK). Set/clear the bits using the bit fields then + * write the d32 value to the register. + */ +typedef union gintmsk_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved0:1; + unsigned modemismatch:1; + unsigned otgintr:1; + unsigned sofintr:1; + unsigned rxstsqlvl:1; + unsigned nptxfempty:1; + unsigned ginnakeff:1; + unsigned goutnakeff:1; + unsigned ulpickint:1; + unsigned i2cintr:1; + unsigned erlysuspend:1; + unsigned usbsuspend:1; + unsigned usbreset:1; + unsigned enumdone:1; + unsigned isooutdrop:1; + unsigned eopframe:1; + unsigned restoredone:1; + unsigned epmismatch:1; + unsigned inepintr:1; + unsigned outepintr:1; + unsigned incomplisoin:1; + unsigned incomplisoout:1; + unsigned fetsusp:1; + unsigned resetdet:1; + unsigned portintr:1; + unsigned hcintr:1; + unsigned ptxfempty:1; + unsigned lpmtranrcvd:1; + unsigned conidstschng:1; + unsigned disconnect:1; + unsigned sessreqintr:1; + unsigned wkupintr:1; + } b; +} gintmsk_data_t; +/** + * This union represents the bit fields of the Core Interrupt Register + * (GINTSTS). Set/clear the bits using the bit fields then write the + * d32 value to the register. + */ +typedef union gintsts_data { + /** raw register data */ + uint32_t d32; +#define DWC_SOF_INTR_MASK 0x0008 + /** register bits */ + struct { +#define DWC_HOST_MODE 1 + unsigned curmode:1; + unsigned modemismatch:1; + unsigned otgintr:1; + unsigned sofintr:1; + unsigned rxstsqlvl:1; + unsigned nptxfempty:1; + unsigned ginnakeff:1; + unsigned goutnakeff:1; + unsigned ulpickint:1; + unsigned i2cintr:1; + unsigned erlysuspend:1; + unsigned usbsuspend:1; + unsigned usbreset:1; + unsigned enumdone:1; + unsigned isooutdrop:1; + unsigned eopframe:1; + unsigned restoredone:1; + unsigned epmismatch:1; + unsigned inepint:1; + unsigned outepintr:1; + unsigned incomplisoin:1; + unsigned incomplisoout:1; + unsigned fetsusp:1; + unsigned resetdet:1; + unsigned portintr:1; + unsigned hcintr:1; + unsigned ptxfempty:1; + unsigned lpmtranrcvd:1; + unsigned conidstschng:1; + unsigned disconnect:1; + unsigned sessreqintr:1; + unsigned wkupintr:1; + } b; +} gintsts_data_t; + +/** + * This union represents the bit fields in the Device Receive Status Read and + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 + * element then read out the bits using the bit elements. + */ +typedef union device_grxsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned epnum:4; + unsigned bcnt:11; + unsigned dpid:2; + +#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet +#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete + +#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK +#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete +#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet + unsigned pktsts:4; + unsigned fn:4; + unsigned reserved25_31:7; + } b; +} device_grxsts_data_t; + +/** + * This union represents the bit fields in the Host Receive Status Read and + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 + * element then read out the bits using the bit elements. + */ +typedef union host_grxsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned chnum:4; + unsigned bcnt:11; + unsigned dpid:2; + + unsigned pktsts:4; +#define DWC_GRXSTS_PKTSTS_IN 0x2 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 +#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 + + unsigned reserved21_31:11; + } b; +} host_grxsts_data_t; + +/** + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, + * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the d32 element then + * read out the bits using the bit elements. + */ +typedef union fifosize_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned startaddr:16; + unsigned depth:16; + } b; +} fifosize_data_t; + +/** + * This union represents the bit fields in the Non-Periodic Transmit + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the + * d32 element then read out the bits using the bit + * elements. + */ +typedef union gnptxsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned nptxfspcavail:16; + unsigned nptxqspcavail:8; + /** Top of the Non-Periodic Transmit Request Queue + * - bit 24 - Terminate (Last entry for the selected + * channel/EP) + * - bits 26:25 - Token Type + * - 2'b00 - IN/OUT + * - 2'b01 - Zero Length OUT + * - 2'b10 - PING/Complete Split + * - 2'b11 - Channel Halt + * - bits 30:27 - Channel/EP Number + */ + unsigned nptxqtop_terminate:1; + unsigned nptxqtop_token:2; + unsigned nptxqtop_chnep:4; + unsigned reserved:1; + } b; +} gnptxsts_data_t; + +/** + * This union represents the bit fields in the Transmit + * FIFO Status Register (DTXFSTS). Read the register into the + * d32 element then read out the bits using the bit + * elements. + */ +typedef union dtxfsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned txfspcavail:16; + unsigned reserved:16; + } b; +} dtxfsts_data_t; + +/** + * This union represents the bit fields in the I2C Control Register + * (I2CCTL). Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union gi2cctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned rwdata:8; + unsigned regaddr:8; + unsigned addr:7; + unsigned i2cen:1; + unsigned ack:1; + unsigned i2csuspctl:1; + unsigned i2cdevaddr:2; + unsigned i2cdatse0:1; + unsigned reserved:1; + unsigned rw:1; + unsigned bsydne:1; + } b; +} gi2cctl_data_t; + +/** + * This union represents the bit fields in the PHY Vendor Control Register + * (GPVNDCTL). Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union gpvndctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned regdata:8; + unsigned vctrl:8; + unsigned regaddr16_21:6; + unsigned regwr:1; + unsigned reserved23_24:2; + unsigned newregreq:1; + unsigned vstsbsy:1; + unsigned vstsdone:1; + unsigned reserved28_30:3; + unsigned disulpidrvr:1; + } b; +} gpvndctl_data_t; + +/** + * This union represents the bit fields in the General Purpose + * Input/Output Register (GGPIO). + * Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union ggpio_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned gpi:16; + unsigned gpo:16; + } b; +} ggpio_data_t; + +/** + * This union represents the bit fields in the User ID Register + * (GUID). Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union guid_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned rwdata:32; + } b; +} guid_data_t; + +/** + * This union represents the bit fields in the Synopsys ID Register + * (GSNPSID). Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union gsnpsid_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned rwdata:32; + } b; +} gsnpsid_data_t; + +/** + * This union represents the bit fields in the User HW Config1 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg1_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned ep_dir0:2; + unsigned ep_dir1:2; + unsigned ep_dir2:2; + unsigned ep_dir3:2; + unsigned ep_dir4:2; + unsigned ep_dir5:2; + unsigned ep_dir6:2; + unsigned ep_dir7:2; + unsigned ep_dir8:2; + unsigned ep_dir9:2; + unsigned ep_dir10:2; + unsigned ep_dir11:2; + unsigned ep_dir12:2; + unsigned ep_dir13:2; + unsigned ep_dir14:2; + unsigned ep_dir15:2; + } b; +} hwcfg1_data_t; + +/** + * This union represents the bit fields in the User HW Config2 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg2_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /* GHWCFG2 */ + unsigned op_mode:3; +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 + + unsigned architecture:2; + unsigned point2point:1; + unsigned hs_phy_type:2; +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 + + unsigned fs_phy_type:2; + unsigned num_dev_ep:4; + unsigned num_host_chan:4; + unsigned perio_ep_supported:1; + unsigned dynamic_fifo:1; + unsigned multi_proc_int:1; + unsigned reserved21:1; + unsigned nonperio_tx_q_depth:2; + unsigned host_perio_tx_q_depth:2; + unsigned dev_token_q_depth:5; + unsigned otg_enable_ic_usb:1; + } b; +} hwcfg2_data_t; + +/** + * This union represents the bit fields in the User HW Config3 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg3_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /* GHWCFG3 */ + unsigned xfer_size_cntr_width:4; + unsigned packet_size_cntr_width:3; + unsigned otg_func:1; + unsigned i2c:1; + unsigned vendor_ctrl_if:1; + unsigned optional_features:1; + unsigned synch_reset_type:1; + unsigned adp_supp:1; + unsigned otg_enable_hsic:1; + unsigned otg_ver_support:1; + unsigned otg_lpm_en:1; + unsigned dfifo_depth:16; + } b; +} hwcfg3_data_t; + +/** + * This union represents the bit fields in the User HW Config4 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg4_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned num_dev_perio_in_ep:4; + unsigned power_optimiz:1; + unsigned min_ahb_freq:1; + unsigned part_power_down:1; + unsigned reserved:7; + unsigned utmi_phy_data_width:2; + unsigned num_dev_mode_ctrl_ep:4; + unsigned iddig_filt_en:1; + unsigned vbus_valid_filt_en:1; + unsigned a_valid_filt_en:1; + unsigned b_valid_filt_en:1; + unsigned session_end_filt_en:1; + unsigned ded_fifo_en:1; + unsigned num_in_eps:4; + unsigned desc_dma:1; + unsigned desc_dma_dyn:1; + } b; +} hwcfg4_data_t; + +/** + * This union represents the bit fields of the Core LPM Configuration + * Register (GLPMCFG). Set the bits using bit fields then write + * the d32 value to the register. + */ +typedef union glpmctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** LPM-Capable (LPMCap) (Device and Host) + * The application uses this bit to control + * the DWC_otg core LPM capabilities. + */ + unsigned lpm_cap_en:1; + /** LPM response programmed by application (AppL1Res) (Device) + * Handshake response to LPM token pre-programmed + * by device application software. + */ + unsigned appl_resp:1; + /** Host Initiated Resume Duration (HIRD) (Device and Host) + * In Host mode this field indicates the value of HIRD + * to be sent in an LPM transaction. + * In Device mode this field is updated with the + * Received LPM Token HIRD bmAttribute + * when an ACK/NYET/STALL response is sent + * to an LPM transaction. + */ + unsigned hird:4; + /** RemoteWakeEnable (bRemoteWake) (Device and Host) + * In Host mode this bit indicates the value of remote + * wake up to be sent in wIndex field of LPM transaction. + * In Device mode this field is updated with the + * Received LPM Token bRemoteWake bmAttribute + * when an ACK/NYET/STALL response is sent + * to an LPM transaction. + */ + unsigned rem_wkup_en:1; + /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) + * The application uses this bit to control + * the utmi_sleep_n assertion to the PHY when in L1 state. + */ + unsigned en_utmi_sleep:1; + /** HIRD Threshold (HIRD_Thres) (Device and Host) + */ + unsigned hird_thres:5; + /** LPM Response (CoreL1Res) (Device and Host) + * In Host mode this bit contains handsake response to + * LPM transaction. + * In Device mode the response of the core to + * LPM transaction received is reflected in these two bits. + - 0x0 : ERROR (No handshake response) + - 0x1 : STALL + - 0x2 : NYET + - 0x3 : ACK + */ + unsigned lpm_resp:2; + /** Port Sleep Status (SlpSts) (Device and Host) + * This bit is set as long as a Sleep condition + * is present on the USB bus. + */ + unsigned prt_sleep_sts:1; + /** Sleep State Resume OK (L1ResumeOK) (Device and Host) + * Indicates that the application or host + * can start resume from Sleep state. + */ + unsigned sleep_state_resumeok:1; + /** LPM channel Index (LPM_Chnl_Indx) (Host) + * The channel number on which the LPM transaction + * has to be applied while sending + * an LPM transaction to the local device. + */ + unsigned lpm_chan_index:4; + /** LPM Retry Count (LPM_Retry_Cnt) (Host) + * Number host retries that would be performed + * if the device response was not valid response. + */ + unsigned retry_count:3; + /** Send LPM Transaction (SndLPM) (Host) + * When set by application software, + * an LPM transaction containing two tokens + * is sent. + */ + unsigned send_lpm:1; + /** LPM Retry status (LPM_RetryCnt_Sts) (Host) + * Number of LPM Host Retries still remaining + * to be transmitted for the current LPM sequence + */ + unsigned retry_count_sts:3; + unsigned reserved28_29:2; + /** In host mode once this bit is set, the host + * configures to drive the HSIC Idle state on the bus. + * It then waits for the device to initiate the Connect sequence. + * In device mode once this bit is set, the device waits for + * the HSIC Idle line state on the bus. Upon receving the Idle + * line state, it initiates the HSIC Connect sequence. + */ + unsigned hsic_connect:1; + /** This bit overrides and functionally inverts + * the if_select_hsic input port signal. + */ + unsigned inv_sel_hsic:1; + } b; +} glpmcfg_data_t; + +/** + * This union represents the bit fields of the Core ADP Timer, Control and + * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write + * the d32 value to the register. + */ +typedef union adpctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Probe Discharge (PRB_DSCHG) + * These bits set the times for TADP_DSCHG. + * These bits are defined as follows: + * 2'b00 - 4 msec + * 2'b01 - 8 msec + * 2'b10 - 16 msec + * 2'b11 - 32 msec + */ + unsigned prb_dschg:2; + /** Probe Delta (PRB_DELTA) + * These bits set the resolution for RTIM value. + * The bits are defined in units of 32 kHz clock cycles as follows: + * 2'b00 - 1 cycles + * 2'b01 - 2 cycles + * 2'b10 - 3 cycles + * 2'b11 - 4 cycles + * For example if this value is chosen to 2'b01, it means that RTIM + * increments for every 3(three) 32Khz clock cycles. + */ + unsigned prb_delta:2; + /** Probe Period (PRB_PER) + * These bits sets the TADP_PRD as shown in Figure 4 as follows: + * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) + * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) + * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) + * 2'b11 - Reserved + */ + unsigned prb_per:2; + /** These bits capture the latest time it took for VBUS to ramp from VADP_SINK + * to VADP_PRB. The bits are defined in units of 32 kHz clock cycles as follows: + * 0x000 - 1 cycles + * 0x001 - 2 cycles + * 0x002 - 3 cycles + * etc + * 0x7FF - 2048 cycles + * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. + */ + unsigned rtim:11; + /** Enable Probe (EnaPrb) + * When programmed to 1'b1, the core performs a probe operation. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned enaprb:1; + /** Enable Sense (EnaSns) + * When programmed to 1'b1, the core performs a Sense operation. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned enasns:1; + /** ADP Reset (ADPRes) + * When set, ADP controller is reset. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adpres:1; + /** ADP Enable (ADPEn) + * When set, the core performs either ADP probing or sensing + * based on EnaPrb or EnaSns. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adpen:1; + /** ADP Probe Interrupt (ADP_PRB_INT) + * When this bit is set, it means that the VBUS + * voltage is greater than VADP_PRB or VADP_PRB is reached. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_prb_int:1; + /** + * ADP Sense Interrupt (ADP_SNS_INT) + * When this bit is set, it means that the VBUS voltage is greater than + * VADP_SNS value or VADP_SNS is reached. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_sns_int:1; + /** ADP Tomeout Interrupt (ADP_TMOUT_INT) + * This bit is relevant only for an ADP probe. + * When this bit is set, it means that the ramp time has + * completed ie ADPCTL.RTIM has reached its terminal value + * of 0x7FF. This is a debug feature that allows software + * to read the ramp time after each cycle. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_tmout_int:1; + /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) + * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_prb_int_msk:1; + /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) + * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_sns_int_msk:1; + /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) + * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_tmout_int_msk:1; + /** Access Request + * 2'b00 - Read/Write Valid (updated by the core) + * 2'b01 - Read + * 2'b00 - Write + * 2'b00 - Reserved + */ + unsigned ar:2; + /** Reserved */ + unsigned reserved29_31:3; + } b; +} adpctl_data_t; + +//////////////////////////////////////////// +// Device Registers +/** + * Device Global Registers. Offsets 800h-BFFh + * + * The following structures define the size and relative field offsets + * for the Device Mode Registers. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_global_regs { + /** Device Configuration Register. Offset 800h */ + volatile uint32_t dcfg; + /** Device Control Register. Offset: 804h */ + volatile uint32_t dctl; + /** Device Status Register (Read Only). Offset: 808h */ + volatile uint32_t dsts; + /** Reserved. Offset: 80Ch */ + uint32_t unused; + /** Device IN Endpoint Common Interrupt Mask + * Register. Offset: 810h */ + volatile uint32_t diepmsk; + /** Device OUT Endpoint Common Interrupt Mask + * Register. Offset: 814h */ + volatile uint32_t doepmsk; + /** Device All Endpoints Interrupt Register. Offset: 818h */ + volatile uint32_t daint; + /** Device All Endpoints Interrupt Mask Register. Offset: + * 81Ch */ + volatile uint32_t daintmsk; + /** Device IN Token Queue Read Register-1 (Read Only). + * Offset: 820h */ + volatile uint32_t dtknqr1; + /** Device IN Token Queue Read Register-2 (Read Only). + * Offset: 824h */ + volatile uint32_t dtknqr2; + /** Device VBUS discharge Register. Offset: 828h */ + volatile uint32_t dvbusdis; + /** Device VBUS Pulse Register. Offset: 82Ch */ + volatile uint32_t dvbuspulse; + /** Device IN Token Queue Read Register-3 (Read Only). / + * Device Thresholding control register (Read/Write) + * Offset: 830h */ + volatile uint32_t dtknqr3_dthrctl; + /** Device IN Token Queue Read Register-4 (Read Only). / + * Device IN EPs empty Inr. Mask Register (Read/Write) + * Offset: 834h */ + volatile uint32_t dtknqr4_fifoemptymsk; + /** Device Each Endpoint Interrupt Register (Read Only). / + * Offset: 838h */ + volatile uint32_t deachint; + /** Device Each Endpoint Interrupt mask Register (Read/Write). / + * Offset: 83Ch */ + volatile uint32_t deachintmsk; + /** Device Each In Endpoint Interrupt mask Register (Read/Write). / + * Offset: 840h */ + volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; + /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / + * Offset: 880h */ + volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; +} dwc_otg_device_global_regs_t; + +/** + * This union represents the bit fields in the Device Configuration + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. Write the + * d32 member to the dcfg register. + */ +typedef union dcfg_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Device Speed */ + unsigned devspd:2; + /** Non Zero Length Status OUT Handshake */ + unsigned nzstsouthshk:1; +#define DWC_DCFG_SEND_STALL 1 + + unsigned ena32khzs:1; + /** Device Addresses */ + unsigned devaddr:7; + /** Periodic Frame Interval */ + unsigned perfrint:2; +#define DWC_DCFG_FRAME_INTERVAL_80 0 +#define DWC_DCFG_FRAME_INTERVAL_85 1 +#define DWC_DCFG_FRAME_INTERVAL_90 2 +#define DWC_DCFG_FRAME_INTERVAL_95 3 + + unsigned reserved13_17:5; + /** In Endpoint Mis-match count */ + unsigned epmscnt:5; + /** Enable Descriptor DMA in Device mode */ + unsigned descdma:1; + unsigned perschintvl:2; + unsigned resvalid:6; + } b; +} dcfg_data_t; + +/** + * This union represents the bit fields in the Device Control + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union dctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Remote Wakeup */ + unsigned rmtwkupsig:1; + /** Soft Disconnect */ + unsigned sftdiscon:1; + /** Global Non-Periodic IN NAK Status */ + unsigned gnpinnaksts:1; + /** Global OUT NAK Status */ + unsigned goutnaksts:1; + /** Test Control */ + unsigned tstctl:3; + /** Set Global Non-Periodic IN NAK */ + unsigned sgnpinnak:1; + /** Clear Global Non-Periodic IN NAK */ + unsigned cgnpinnak:1; + /** Set Global OUT NAK */ + unsigned sgoutnak:1; + /** Clear Global OUT NAK */ + unsigned cgoutnak:1; + + /** Power-On Programming Done */ + unsigned pwronprgdone:1; + /** Reserved */ + unsigned reserved:1; + /** Global Multi Count */ + unsigned gmc:2; + /** Ignore Frame Number for ISOC EPs */ + unsigned ifrmnum:1; + /** NAK on Babble */ + unsigned nakonbble:1; + + unsigned reserved17_31:15; + } b; +} dctl_data_t; + +/** + * This union represents the bit fields in the Device Status + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union dsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Suspend Status */ + unsigned suspsts:1; + /** Enumerated Speed */ + unsigned enumspd:2; +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 + /** Erratic Error */ + unsigned errticerr:1; + unsigned reserved4_7:4; + /** Frame or Microframe Number of the received SOF */ + unsigned soffn:14; + unsigned reserved22_31:10; + } b; +} dsts_data_t; + +/** + * This union represents the bit fields in the Device IN EP Interrupt + * Register and the Device IN EP Common Mask Register. + * + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union diepint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer complete mask */ + unsigned xfercompl:1; + /** Endpoint disable mask */ + unsigned epdisabled:1; + /** AHB Error mask */ + unsigned ahberr:1; + /** TimeOUT Handshake mask (non-ISOC EPs) */ + unsigned timeout:1; + /** IN Token received with TxF Empty mask */ + unsigned intktxfemp:1; + /** IN Token Received with EP mismatch mask */ + unsigned intknepmis:1; + /** IN Endpoint NAK Effective mask */ + unsigned inepnakeff:1; + /** Reserved */ + unsigned emptyintr:1; + + unsigned txfifoundrn:1; + + /** BNA Interrupt mask */ + unsigned bna:1; + + unsigned reserved10_12:3; + /** BNA Interrupt mask */ + unsigned nak:1; + + unsigned reserved14_31:18; + } b; +} diepint_data_t; + +/** + * This union represents the bit fields in the Device IN EP + * Common/Dedicated Interrupt Mask Register. + */ +typedef union diepint_data diepmsk_data_t; + +/** + * This union represents the bit fields in the Device OUT EP Interrupt + * Registerand Device OUT EP Common Interrupt Mask Register. + * + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union doepint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer complete */ + unsigned xfercompl:1; + /** Endpoint disable */ + unsigned epdisabled:1; + /** AHB Error */ + unsigned ahberr:1; + /** Setup Phase Done (contorl EPs) */ + unsigned setup:1; + /** OUT Token Received when Endpoint Disabled */ + unsigned outtknepdis:1; + + unsigned stsphsercvd:1; + /** Back-to-Back SETUP Packets Received */ + unsigned back2backsetup:1; + + unsigned reserved7:1; + /** OUT packet Error */ + unsigned outpkterr:1; + /** BNA Interrupt */ + unsigned bna:1; + + unsigned reserved10:1; + /** Packet Drop Status */ + unsigned pktdrpsts:1; + /** Babble Interrupt */ + unsigned babble:1; + /** NAK Interrupt */ + unsigned nak:1; + /** NYET Interrupt */ + unsigned nyet:1; + + unsigned reserved15_31:17; + } b; +} doepint_data_t; + +/** + * This union represents the bit fields in the Device OUT EP + * Common/Dedicated Interrupt Mask Register. + */ +typedef union doepint_data doepmsk_data_t; + +/** + * This union represents the bit fields in the Device All EP Interrupt + * and Mask Registers. + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union daint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** IN Endpoint bits */ + unsigned in:16; + /** OUT Endpoint bits */ + unsigned out:16; + } ep; + struct { + /** IN Endpoint bits */ + unsigned inep0:1; + unsigned inep1:1; + unsigned inep2:1; + unsigned inep3:1; + unsigned inep4:1; + unsigned inep5:1; + unsigned inep6:1; + unsigned inep7:1; + unsigned inep8:1; + unsigned inep9:1; + unsigned inep10:1; + unsigned inep11:1; + unsigned inep12:1; + unsigned inep13:1; + unsigned inep14:1; + unsigned inep15:1; + /** OUT Endpoint bits */ + unsigned outep0:1; + unsigned outep1:1; + unsigned outep2:1; + unsigned outep3:1; + unsigned outep4:1; + unsigned outep5:1; + unsigned outep6:1; + unsigned outep7:1; + unsigned outep8:1; + unsigned outep9:1; + unsigned outep10:1; + unsigned outep11:1; + unsigned outep12:1; + unsigned outep13:1; + unsigned outep14:1; + unsigned outep15:1; + } b; +} daint_data_t; + +/** + * This union represents the bit fields in the Device IN Token Queue + * Read Registers. + * - Read the register into the d32 member. + * - READ-ONLY Register + */ +typedef union dtknq1_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** In Token Queue Write Pointer */ + unsigned intknwptr:5; + /** Reserved */ + unsigned reserved05_06:2; + /** write pointer has wrapped. */ + unsigned wrap_bit:1; + /** EP Numbers of IN Tokens 0 ... 4 */ + unsigned epnums0_5:24; + } b; +} dtknq1_data_t; + +/** + * This union represents Threshold control Register + * - Read and write the register into the d32 member. + * - READ-WRITABLE Register + */ +typedef union dthrctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** non ISO Tx Thr. Enable */ + unsigned non_iso_thr_en:1; + /** ISO Tx Thr. Enable */ + unsigned iso_thr_en:1; + /** Tx Thr. Length */ + unsigned tx_thr_len:9; + /** AHB Threshold ratio */ + unsigned ahb_thr_ratio:2; + /** Reserved */ + unsigned reserved13_15:3; + /** Rx Thr. Enable */ + unsigned rx_thr_en:1; + /** Rx Thr. Length */ + unsigned rx_thr_len:9; + unsigned reserved26:1; + /** Arbiter Parking Enable*/ + unsigned arbprken:1; + /** Reserved */ + unsigned reserved28_31:4; + } b; +} dthrctl_data_t; + +/** + * Device Logical IN Endpoint-Specific Registers. Offsets + * 900h-AFCh + * + * There will be one set of endpoint registers per logical endpoint + * implemented. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_in_ep_regs { + /** Device IN Endpoint Control Register. Offset:900h + + * (ep_num * 20h) + 00h */ + volatile uint32_t diepctl; + /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ + uint32_t reserved04; + /** Device IN Endpoint Interrupt Register. Offset:900h + + * (ep_num * 20h) + 08h */ + volatile uint32_t diepint; + /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ + uint32_t reserved0C; + /** Device IN Endpoint Transfer Size + * Register. Offset:900h + (ep_num * 20h) + 10h */ + volatile uint32_t dieptsiz; + /** Device IN Endpoint DMA Address Register. Offset:900h + + * (ep_num * 20h) + 14h */ + volatile uint32_t diepdma; + /** Device IN Endpoint Transmit FIFO Status Register. Offset:900h + + * (ep_num * 20h) + 18h */ + volatile uint32_t dtxfsts; + /** Device IN Endpoint DMA Buffer Register. Offset:900h + + * (ep_num * 20h) + 1Ch */ + volatile uint32_t diepdmab; +} dwc_otg_dev_in_ep_regs_t; + +/** + * Device Logical OUT Endpoint-Specific Registers. Offsets: + * B00h-CFCh + * + * There will be one set of endpoint registers per logical endpoint + * implemented. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_out_ep_regs { + /** Device OUT Endpoint Control Register. Offset:B00h + + * (ep_num * 20h) + 00h */ + volatile uint32_t doepctl; + /** Device OUT Endpoint Frame number Register. Offset: + * B00h + (ep_num * 20h) + 04h */ + volatile uint32_t doepfn; + /** Device OUT Endpoint Interrupt Register. Offset:B00h + + * (ep_num * 20h) + 08h */ + volatile uint32_t doepint; + /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ + uint32_t reserved0C; + /** Device OUT Endpoint Transfer Size Register. Offset: + * B00h + (ep_num * 20h) + 10h */ + volatile uint32_t doeptsiz; + /** Device OUT Endpoint DMA Address Register. Offset:B00h + * + (ep_num * 20h) + 14h */ + volatile uint32_t doepdma; + /** Reserved. Offset:B00h + * (ep_num * 20h) + 18h */ + uint32_t unused; + /** Device OUT Endpoint DMA Buffer Register. Offset:B00h + * + (ep_num * 20h) + 1Ch */ + uint32_t doepdmab; +} dwc_otg_dev_out_ep_regs_t; + +/** + * This union represents the bit fields in the Device EP Control + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union depctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Maximum Packet Size + * IN/OUT EPn + * IN/OUT EP0 - 2 bits + * 2'b00: 64 Bytes + * 2'b01: 32 + * 2'b10: 16 + * 2'b11: 8 */ + unsigned mps:11; +#define DWC_DEP0CTL_MPS_64 0 +#define DWC_DEP0CTL_MPS_32 1 +#define DWC_DEP0CTL_MPS_16 2 +#define DWC_DEP0CTL_MPS_8 3 + + /** Next Endpoint + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned nextep:4; + + /** USB Active Endpoint */ + unsigned usbactep:1; + + /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) + * This field contains the PID of the packet going to + * be received or transmitted on this endpoint. The + * application should program the PID of the first + * packet going to be received or transmitted on this + * endpoint , after the endpoint is + * activated. Application use the SetD1PID and + * SetD0PID fields of this register to program either + * D0 or D1 PID. + * + * The encoding for this field is + * - 0: D0 + * - 1: D1 + */ + unsigned dpid:1; + + /** NAK Status */ + unsigned naksts:1; + + /** Endpoint Type + * 2'b00: Control + * 2'b01: Isochronous + * 2'b10: Bulk + * 2'b11: Interrupt */ + unsigned eptype:2; + + /** Snoop Mode + * OUT EPn/OUT EP0 + * IN EPn/IN EP0 - reserved */ + unsigned snp:1; + + /** Stall Handshake */ + unsigned stall:1; + + /** Tx Fifo Number + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned txfnum:4; + + /** Clear NAK */ + unsigned cnak:1; + /** Set NAK */ + unsigned snak:1; + /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA0. Set Even + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) + * frame. + */ + unsigned setd0pid:1; + /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA1 Set Odd + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to odd (micro) frame. + */ + unsigned setd1pid:1; + + /** Endpoint Disable */ + unsigned epdis:1; + /** Endpoint Enable */ + unsigned epena:1; + } b; +} depctl_data_t; + +/** + * This union represents the bit fields in the Device EP Transfer + * Size Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union deptsiz_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer size */ + unsigned xfersize:19; + /** Packet Count */ + unsigned pktcnt:10; + /** Multi Count - Periodic IN endpoints */ + unsigned mc:2; + unsigned reserved:1; + } b; +} deptsiz_data_t; + +/** + * This union represents the bit fields in the Device EP 0 Transfer + * Size Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union deptsiz0_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer size */ + unsigned xfersize:7; + /** Reserved */ + unsigned reserved7_18:12; + /** Packet Count */ + unsigned pktcnt:2; + /** Reserved */ + unsigned reserved21_28:8; + /**Setup Packet Count (DOEPTSIZ0 Only) */ + unsigned supcnt:2; + unsigned reserved31; + } b; +} +#if __GNUC__ /*GCC*/ +__attribute__((__may_alias__)) deptsiz0_data_t; +#else + deptsiz0_data_t; +#endif +///////////////////////////////////////////////// +// DMA Descriptor Specific Structures +// + +/** Buffer status definitions */ + +#define BS_HOST_READY 0x0 +#define BS_DMA_BUSY 0x1 +#define BS_DMA_DONE 0x2 +#define BS_HOST_BUSY 0x3 + +/** Receive/Transmit status definitions */ + +#define RTS_SUCCESS 0x0 +#define RTS_BUFFLUSH 0x1 +#define RTS_RESERVED 0x2 +#define RTS_BUFERR 0x3 + +/** + * This union represents the bit fields in the DMA Descriptor + * status quadlet. Read the quadlet into the d32 member then + * set/clear the bits using the bit, b_iso_out and + * b_iso_in elements. + */ +typedef union dev_dma_desc_sts { + /** raw register data */ + uint32_t d32; + /** quadlet bits */ + struct { + /** Received number of bytes */ + unsigned bytes:16; + + unsigned reserved16_22:7; + /** Multiple Transfer - only for OUT EPs */ + unsigned mtrf:1; + /** Setup Packet received - only for OUT EPs */ + unsigned sr:1; + /** Interrupt On Complete */ + unsigned ioc:1; + /** Short Packet */ + unsigned sp:1; + /** Last */ + unsigned l:1; + /** Receive Status */ + unsigned sts:2; + /** Buffer Status */ + unsigned bs:2; + } b; + +//#ifdef DWC_EN_ISOC + /** iso out quadlet bits */ + struct { + /** Received number of bytes */ + unsigned rxbytes:11; + + unsigned reserved11:1; + /** Frame Number */ + unsigned framenum:11; + /** Received ISO Data PID */ + unsigned pid:2; + /** Interrupt On Complete */ + unsigned ioc:1; + /** Short Packet */ + unsigned sp:1; + /** Last */ + unsigned l:1; + /** Receive Status */ + unsigned rxsts:2; + /** Buffer Status */ + unsigned bs:2; + } b_iso_out; + + /** iso in quadlet bits */ + struct { + /** Transmited number of bytes */ + unsigned txbytes:12; + /** Frame Number */ + unsigned framenum:11; + /** Transmited ISO Data PID */ + unsigned pid:2; + /** Interrupt On Complete */ + unsigned ioc:1; + /** Short Packet */ + unsigned sp:1; + /** Last */ + unsigned l:1; + /** Transmit Status */ + unsigned txsts:2; + /** Buffer Status */ + unsigned bs:2; + } b_iso_in; +//#endif /* DWC_EN_ISOC */ +} dev_dma_desc_sts_t; + +/** + * DMA Descriptor structure + * + * DMA Descriptor structure contains two quadlets: + * Status quadlet and Data buffer pointer. + */ +typedef struct dwc_otg_dev_dma_desc { + /** DMA Descriptor status quadlet */ + dev_dma_desc_sts_t status; + /** DMA Descriptor data buffer pointer */ + uint32_t buf; +} dwc_otg_dev_dma_desc_t; + +/** + * The dwc_otg_dev_if structure contains information needed to manage + * the DWC_otg controller acting in device mode. It represents the + * programming view of the device-specific aspects of the controller. + */ +typedef struct dwc_otg_dev_if { + /** Pointer to device Global registers. + * Device Global Registers starting at offset 800h + */ + dwc_otg_device_global_regs_t *dev_global_regs; +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800 + + /** + * Device Logical IN Endpoint-Specific Registers 900h-AFCh + */ + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; +#define DWC_DEV_IN_EP_REG_OFFSET 0x900 +#define DWC_EP_REG_OFFSET 0x20 + + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ + dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 + + /* Device configuration information */ + uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ + uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ + uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ + + /** Size of periodic FIFOs (Bytes) */ + uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; + + /** Size of Tx FIFOs (Bytes) */ + uint16_t tx_fifo_size[MAX_TX_FIFOS]; + + /** Thresholding enable flags and length varaiables **/ + uint16_t rx_thr_en; + uint16_t iso_tx_thr_en; + uint16_t non_iso_tx_thr_en; + + uint16_t rx_thr_length; + uint16_t tx_thr_length; + + /** + * Pointers to the DMA Descriptors for EP0 Control + * transfers (virtual and physical) + */ + + /** 2 descriptors for SETUP packets */ + dwc_dma_t dma_setup_desc_addr[2]; + dwc_otg_dev_dma_desc_t *setup_desc_addr[2]; + + /** Pointer to Descriptor with latest SETUP packet */ + dwc_otg_dev_dma_desc_t *psetup; + + /** Index of current SETUP handler descriptor */ + uint32_t setup_desc_index; + + /** Descriptor for Data In or Status In phases */ + dwc_dma_t dma_in_desc_addr; + dwc_otg_dev_dma_desc_t *in_desc_addr; + + /** Descriptor for Data Out or Status Out phases */ + dwc_dma_t dma_out_desc_addr; + dwc_otg_dev_dma_desc_t *out_desc_addr; + + /** Setup Packet Detected - if set clear NAK when queueing */ + uint32_t spd; + +} dwc_otg_dev_if_t; + +///////////////////////////////////////////////// +// Host Mode Register Structures +// +/** + * The Host Global Registers structure defines the size and relative + * field offsets for the Host Mode Global Registers. Host Global + * Registers offsets 400h-7FFh. +*/ +typedef struct dwc_otg_host_global_regs { + /** Host Configuration Register. Offset: 400h */ + volatile uint32_t hcfg; + /** Host Frame Interval Register. Offset: 404h */ + volatile uint32_t hfir; + /** Host Frame Number / Frame Remaining Register. Offset: 408h */ + volatile uint32_t hfnum; + /** Reserved. Offset: 40Ch */ + uint32_t reserved40C; + /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ + volatile uint32_t hptxsts; + /** Host All Channels Interrupt Register. Offset: 414h */ + volatile uint32_t haint; + /** Host All Channels Interrupt Mask Register. Offset: 418h */ + volatile uint32_t haintmsk; + /** Host Frame List Base Address Register . Offset: 41Ch */ + volatile uint32_t hflbaddr; +} dwc_otg_host_global_regs_t; + +/** + * This union represents the bit fields in the Host Configuration Register. + * Read the register into the d32 member then set/clear the bits using + * the bit elements. Write the d32 member to the hcfg register. + */ +typedef union hcfg_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** FS/LS Phy Clock Select */ + unsigned fslspclksel:2; +#define DWC_HCFG_30_60_MHZ 0 +#define DWC_HCFG_48_MHZ 1 +#define DWC_HCFG_6_MHZ 2 + + /** FS/LS Only Support */ + unsigned fslssupp:1; + unsigned reserved3_6:4; + /** Enable 32-KHz Suspend Mode */ + unsigned ena32khzs:1; + /** Resume Validation Periiod */ + unsigned resvalid:8; + unsigned reserved16_22:7; + /** Enable Scatter/gather DMA in Host mode */ + unsigned descdma:1; + /** Frame List Entries */ + unsigned frlisten:2; + /** Enable Periodic Scheduling */ + unsigned perschedena:1; + unsigned reserved27_30:4; + unsigned modechtimen:1; + } b; +} hcfg_data_t; + +/** + * This union represents the bit fields in the Host Frame Remaing/Number + * Register. + */ +typedef union hfir_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned frint:16; + unsigned hfirrldctrl:1; + unsigned reserved:15; + } b; +} hfir_data_t; + +/** + * This union represents the bit fields in the Host Frame Remaing/Number + * Register. + */ +typedef union hfnum_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned frnum:16; +#define DWC_HFNUM_MAX_FRNUM 0x3FFF + unsigned frrem:16; + } b; +} hfnum_data_t; + +typedef union hptxsts_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned ptxfspcavail:16; + unsigned ptxqspcavail:8; + /** Top of the Periodic Transmit Request Queue + * - bit 24 - Terminate (last entry for the selected channel) + * - bits 26:25 - Token Type + * - 2'b00 - Zero length + * - 2'b01 - Ping + * - 2'b10 - Disable + * - bits 30:27 - Channel Number + * - bit 31 - Odd/even microframe + */ + unsigned ptxqtop_terminate:1; + unsigned ptxqtop_token:2; + unsigned ptxqtop_chnum:4; + unsigned ptxqtop_odd:1; + } b; +} hptxsts_data_t; + +/** + * This union represents the bit fields in the Host Port Control and Status + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hprt0 register. + */ +typedef union hprt0_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned prtconnsts:1; + unsigned prtconndet:1; + unsigned prtena:1; + unsigned prtenchng:1; + unsigned prtovrcurract:1; + unsigned prtovrcurrchng:1; + unsigned prtres:1; + unsigned prtsusp:1; + unsigned prtrst:1; + unsigned reserved9:1; + unsigned prtlnsts:2; + unsigned prtpwr:1; + unsigned prttstctl:4; + unsigned prtspd:2; +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1 +#define DWC_HPRT0_PRTSPD_LOW_SPEED 2 + unsigned reserved19_31:13; + } b; +} hprt0_data_t; + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union haint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned ch0:1; + unsigned ch1:1; + unsigned ch2:1; + unsigned ch3:1; + unsigned ch4:1; + unsigned ch5:1; + unsigned ch6:1; + unsigned ch7:1; + unsigned ch8:1; + unsigned ch9:1; + unsigned ch10:1; + unsigned ch11:1; + unsigned ch12:1; + unsigned ch13:1; + unsigned ch14:1; + unsigned ch15:1; + unsigned reserved:16; + } b; + + struct { + unsigned chint:16; + unsigned reserved:16; + } b2; +} haint_data_t; + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union haintmsk_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned ch0:1; + unsigned ch1:1; + unsigned ch2:1; + unsigned ch3:1; + unsigned ch4:1; + unsigned ch5:1; + unsigned ch6:1; + unsigned ch7:1; + unsigned ch8:1; + unsigned ch9:1; + unsigned ch10:1; + unsigned ch11:1; + unsigned ch12:1; + unsigned ch13:1; + unsigned ch14:1; + unsigned ch15:1; + unsigned reserved:16; + } b; + + struct { + unsigned chint:16; + unsigned reserved:16; + } b2; +} haintmsk_data_t; + +/** + * Host Channel Specific Registers. 500h-5FCh + */ +typedef struct dwc_otg_hc_regs { + /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ + volatile uint32_t hcchar; + /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ + volatile uint32_t hcsplt; + /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ + volatile uint32_t hcint; + /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ + volatile uint32_t hcintmsk; + /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ + volatile uint32_t hctsiz; + /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ + volatile uint32_t hcdma; + volatile uint32_t reserved; + /** Host Channel 0 DMA Buffer Address Register. Offset: 500h + (chan_num * 20h) + 1Ch */ + volatile uint32_t hcdmab; +} dwc_otg_hc_regs_t; + +/** + * This union represents the bit fields in the Host Channel Characteristics + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcchar register. + */ +typedef union hcchar_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Maximum packet size in bytes */ + unsigned mps:11; + + /** Endpoint number */ + unsigned epnum:4; + + /** 0: OUT, 1: IN */ + unsigned epdir:1; + + unsigned reserved:1; + + /** 0: Full/high speed device, 1: Low speed device */ + unsigned lspddev:1; + + /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ + unsigned eptype:2; + + /** Packets per frame for periodic transfers. 0 is reserved. */ + unsigned multicnt:2; + + /** Device address */ + unsigned devaddr:7; + + /** + * Frame to transmit periodic transaction. + * 0: even, 1: odd + */ + unsigned oddfrm:1; + + /** Channel disable */ + unsigned chdis:1; + + /** Channel enable */ + unsigned chen:1; + } b; +} hcchar_data_t; + +typedef union hcsplt_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Port Address */ + unsigned prtaddr:7; + + /** Hub Address */ + unsigned hubaddr:7; + + /** Transaction Position */ + unsigned xactpos:2; +#define DWC_HCSPLIT_XACTPOS_MID 0 +#define DWC_HCSPLIT_XACTPOS_END 1 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2 +#define DWC_HCSPLIT_XACTPOS_ALL 3 + + /** Do Complete Split */ + unsigned compsplt:1; + + /** Reserved */ + unsigned reserved:14; + + /** Split Enble */ + unsigned spltena:1; + } b; +} hcsplt_data_t; + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union hcint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer Complete */ + unsigned xfercomp:1; + /** Channel Halted */ + unsigned chhltd:1; + /** AHB Error */ + unsigned ahberr:1; + /** STALL Response Received */ + unsigned stall:1; + /** NAK Response Received */ + unsigned nak:1; + /** ACK Response Received */ + unsigned ack:1; + /** NYET Response Received */ + unsigned nyet:1; + /** Transaction Err */ + unsigned xacterr:1; + /** Babble Error */ + unsigned bblerr:1; + /** Frame Overrun */ + unsigned frmovrun:1; + /** Data Toggle Error */ + unsigned datatglerr:1; + /** Buffer Not Available (only for DDMA mode) */ + unsigned bna:1; + /** Exessive transaction error (only for DDMA mode) */ + unsigned xcs_xact:1; + /** Frame List Rollover interrupt */ + unsigned frm_list_roll:1; + /** Reserved */ + unsigned reserved14_31:18; + } b; +} hcint_data_t; + +/** + * This union represents the bit fields in the Host Channel Interrupt Mask + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcintmsk register. + */ +typedef union hcintmsk_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned xfercompl:1; + unsigned chhltd:1; + unsigned ahberr:1; + unsigned stall:1; + unsigned nak:1; + unsigned ack:1; + unsigned nyet:1; + unsigned xacterr:1; + unsigned bblerr:1; + unsigned frmovrun:1; + unsigned datatglerr:1; + unsigned bna:1; + unsigned xcs_xact:1; + unsigned frm_list_roll:1; + unsigned reserved14_31:18; + } b; +} hcintmsk_data_t; + +/** + * This union represents the bit fields in the Host Channel Transfer Size + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcchar register. + */ + +typedef union hctsiz_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Total transfer size in bytes */ + unsigned xfersize:19; + + /** Data packets to transfer */ + unsigned pktcnt:10; + + /** + * Packet ID for next data packet + * 0: DATA0 + * 1: DATA2 + * 2: DATA1 + * 3: MDATA (non-Control), SETUP (Control) + */ + unsigned pid:2; +#define DWC_HCTSIZ_DATA0 0 +#define DWC_HCTSIZ_DATA1 2 +#define DWC_HCTSIZ_DATA2 1 +#define DWC_HCTSIZ_MDATA 3 +#define DWC_HCTSIZ_SETUP 3 + + /** Do PING protocol when 1 */ + unsigned dopng:1; + } b; + + /** register bits */ + struct { + /** Scheduling information */ + unsigned schinfo:8; + + /** Number of transfer descriptors. + * Max value: + * 64 in general, + * 256 only for HS isochronous endpoint. + */ + unsigned ntd:8; + + /** Data packets to transfer */ + unsigned reserved16_28:13; + + /** + * Packet ID for next data packet + * 0: DATA0 + * 1: DATA2 + * 2: DATA1 + * 3: MDATA (non-Control) + */ + unsigned pid:2; + + /** Do PING protocol when 1 */ + unsigned dopng:1; + } b_ddma; +} hctsiz_data_t; + +/** + * This union represents the bit fields in the Host DMA Address + * Register used in Descriptor DMA mode. + */ +typedef union hcdma_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved0_2:3; + /** Current Transfer Descriptor. Not used for ISOC */ + unsigned ctd:8; + /** Start Address of Descriptor List */ + unsigned dma_addr:21; + } b; +} hcdma_data_t; + +/** + * This union represents the bit fields in the DMA Descriptor + * status quadlet for host mode. Read the quadlet into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union host_dma_desc_sts { + /** raw register data */ + uint32_t d32; + /** quadlet bits */ + + /* for non-isochronous */ + struct { + /** Number of bytes */ + unsigned n_bytes:17; + /** QTD offset to jump when Short Packet received - only for IN EPs */ + unsigned qtd_offset:6; + /** + * Set to request the core to jump to alternate QTD if + * Short Packet received - only for IN EPs + */ + unsigned a_qtd:1; + /** + * Setup Packet bit. When set indicates that buffer contains + * setup packet. + */ + unsigned sup:1; + /** Interrupt On Complete */ + unsigned ioc:1; + /** End of List */ + unsigned eol:1; + unsigned reserved27:1; + /** Rx/Tx Status */ + unsigned sts:2; +#define DMA_DESC_STS_PKTERR 1 + unsigned reserved30:1; + /** Active Bit */ + unsigned a:1; + } b; + /* for isochronous */ + struct { + /** Number of bytes */ + unsigned n_bytes:12; + unsigned reserved12_24:13; + /** Interrupt On Complete */ + unsigned ioc:1; + unsigned reserved26_27:2; + /** Rx/Tx Status */ + unsigned sts:2; + unsigned reserved30:1; + /** Active Bit */ + unsigned a:1; + } b_isoc; +} host_dma_desc_sts_t; + +#define MAX_DMA_DESC_SIZE 131071 +#define MAX_DMA_DESC_NUM_GENERIC 64 +#define MAX_DMA_DESC_NUM_HS_ISOC 256 +#define MAX_FRLIST_EN_NUM 64 +/** + * Host-mode DMA Descriptor structure + * + * DMA Descriptor structure contains two quadlets: + * Status quadlet and Data buffer pointer. + */ +typedef struct dwc_otg_host_dma_desc { + /** DMA Descriptor status quadlet */ + host_dma_desc_sts_t status; + /** DMA Descriptor data buffer pointer */ + uint32_t buf; +} dwc_otg_host_dma_desc_t; + +/** OTG Host Interface Structure. + * + * The OTG Host Interface Structure structure contains information + * needed to manage the DWC_otg controller acting in host mode. It + * represents the programming view of the host-specific aspects of the + * controller. + */ +typedef struct dwc_otg_host_if { + /** Host Global Registers starting at offset 400h.*/ + dwc_otg_host_global_regs_t *host_global_regs; +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 + + /** Host Port 0 Control and Status Register */ + volatile uint32_t *hprt0; +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 + + /** Host Channel Specific Registers at offsets 500h-5FCh. */ + dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20 + + /* Host configuration information */ + /** Number of Host Channels (range: 1-16) */ + uint8_t num_host_channels; + /** Periodic EPs supported (0: no, 1: yes) */ + uint8_t perio_eps_supported; + /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ + uint16_t perio_tx_fifo_size; + +} dwc_otg_host_if_t; + +/** + * This union represents the bit fields in the Power and Clock Gating Control + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union pcgcctl_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Stop Pclk */ + unsigned stoppclk:1; + /** Gate Hclk */ + unsigned gatehclk:1; + /** Power Clamp */ + unsigned pwrclmp:1; + /** Reset Power Down Modules */ + unsigned rstpdwnmodule:1; + /** Reserved */ + unsigned reserved:1; + /** Enable Sleep Clock Gating (Enbl_L1Gating) */ + unsigned enbl_sleep_gating:1; + /** PHY In Sleep (PhySleep) */ + unsigned phy_in_sleep:1; + /** Deep Sleep*/ + unsigned deep_sleep:1; + unsigned resetaftsusp:1; + unsigned restoremode:1; + unsigned reserved10_12:3; + unsigned ess_reg_restored:1; + unsigned prt_clk_sel:2; + unsigned port_power:1; + unsigned max_xcvrselect:2; + unsigned max_termsel:1; + unsigned mac_dev_addr:7; + unsigned p2hd_dev_enum_spd:2; + unsigned p2hd_prt_spd:2; + unsigned if_dev_mode:1; + } b; +} pcgcctl_data_t; + +/** + * This union represents the bit fields in the Global Data FIFO Software Configuration Register. + * Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union gdfifocfg_data { + /* raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** OTG Data FIFO depth */ + unsigned gdfifocfg:16; + /** Start address of EP info controller */ + unsigned epinfobase:16; + } b; +} gdfifocfg_data_t; + +/** + * This union represents the bit fields in the Global Power Down Register + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union gpwrdn_data { + /* raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** PMU Interrupt Select */ + unsigned pmuintsel:1; + /** PMU Active */ + unsigned pmuactv:1; + /** Restore */ + unsigned restore:1; + /** Power Down Clamp */ + unsigned pwrdnclmp:1; + /** Power Down Reset */ + unsigned pwrdnrstn:1; + /** Power Down Switch */ + unsigned pwrdnswtch:1; + /** Disable VBUS */ + unsigned dis_vbus:1; + /** Line State Change */ + unsigned lnstschng:1; + /** Line state change mask */ + unsigned lnstchng_msk:1; + /** Reset Detected */ + unsigned rst_det:1; + /** Reset Detect mask */ + unsigned rst_det_msk:1; + /** Disconnect Detected */ + unsigned disconn_det:1; + /** Disconnect Detect mask */ + unsigned disconn_det_msk:1; + /** Connect Detected*/ + unsigned connect_det:1; + /** Connect Detected Mask*/ + unsigned connect_det_msk:1; + /** SRP Detected */ + unsigned srp_det:1; + /** SRP Detect mask */ + unsigned srp_det_msk:1; + /** Status Change Interrupt */ + unsigned sts_chngint:1; + /** Status Change Interrupt Mask */ + unsigned sts_chngint_msk:1; + /** Line State */ + unsigned linestate:2; + /** Indicates current mode(status of IDDIG signal) */ + unsigned idsts:1; + /** B Session Valid signal status*/ + unsigned bsessvld:1; + /** ADP Event Detected */ + unsigned adp_int:1; + /** Multi Valued ID pin */ + unsigned mult_val_id_bc:5; + /** Reserved 24_31 */ + unsigned reserved29_31:3; + } b; +} gpwrdn_data_t; + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usbh.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usbh.h new file mode 100644 index 00000000..06641fe4 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usbh.h @@ -0,0 +1,416 @@ +/** + * @file xmc_usbh.h + * @date 2016-06-30 + * + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2016-06-30: + * - Initial Version.
+ * 2016-09-01: + * - Removed Keil specific inclusions and macros
+ * + * @endcond + * + */ + +#ifndef XMC_USBH_H +#define XMC_USBH_H + +#include +#include "xmc_common.h" +#include "xmc_scu.h" +#include "xmc_gpio.h" + +#if((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC43) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || defined(DOXYGEN)) +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup USBH + * @brief Universal Serial Bus Host (USBH) driver for the XMC4000 microcontroller family. + * + * The USBH is the host mode device driver for the USB0 hardware module on XMC4000 family of microcontrollers. + * The USB0 module can be used to establish a USB interface between outside world and XMC4000 family of controllers. + * The USB module includes the following features in host mode: + * -# Complies with the USB 2.0 Specification. + * -# Supports up to 14 bidirectional pipes, including control pipe 0. + * -# Supports SOFs in Full-Speed modes. + * -# Supports clock gating for power saving. + * -# Supports FIFO mode data transaction. + * + * The below figure shows the overview of USB0 module in XMC4 microntroller. + * @image html USB_module_overview.png + * @image latex ../images/USB_module_overview.png + * + * + * The USBH device driver supports the following features:\n + * -# Initialize/Uninitialize the USB0 module on XMC4000 device. + * -# Control VBUS state. + * -# Reset USB port. + * -# Set the USB device address. + * -# Allocate pipe for new endpoint communication. + * -# Modify an existing pipe. + * -# Transfer data on selected pipe. + * -# Abort ongoing data transaction. + * -# Handle multi packet data transaction by updating toggle information. + * + * The USBH device driver expects registration of callback functions ::XMC_USBH_SignalPortEvent_t and ::XMC_USBH_SignalPipeEvent_t to be executed + * when there is port event interrupt and pipe event interrupt respectively.\n + * The USBH driver is CMSIS API compatible. Please use Driver_USBH0 to access the USBH API.\n + * For example, to initialize the USB host controller, use Driver_USBH0.Initialize().\n + * + * @{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ +/*Drive VBUS*/ +#define XMC_USB_DRIVE_PORT1 P3_2 /**< Default port(PORT3, pin 2) used to enable VBUS voltage regulator on the board */ +#define XMC_USB_DRIVE_PORT2 P0_1 /**< Alternate port that can be used to enable VBUS voltage regulator(PORT0, pin 1) */ + +#ifndef USBH0_MAX_PIPE_NUM +#define USBH0_MAX_PIPE_NUM (14U) /**< Representation of number of pipes available */ +#endif +#if (USBH0_MAX_PIPE_NUM > 14U) +#error Too many Pipes, maximum Pipes that this driver supports is 14 !!! +#endif + +#define XMC_USBH_CLOCK_GATING_ENABLE 1 /**< Used to enable clock gating when the driver is powered down*/ +#define XMC_USBH_CLOCK_GATING_DISABLE 0 /**< Used to disable clock gating when the driver is fully powered*/ + +#define USB_CH_HCCHARx_MPS(x) (((uint32_t) x ) & (uint32_t)USB_CH_HCCHAR_MPS_Msk) /**< Masks maximum packet size information from the HCCHAR register value provided as input */ +#define USB_CH_HCCHARx_EPNUM(x) (((uint32_t) x << USB_CH_HCCHAR_EPNum_Pos) & (uint32_t)USB_CH_HCCHAR_EPNum_Msk) /**< Shifts the value to the position of endpoint number(EPNum) in the HCCHAR register*/ +#define USB_CH_HCCHARx_EPTYPE(x) (((uint32_t) x << USB_CH_HCCHAR_EPType_Pos) & (uint32_t)USB_CH_HCCHAR_EPType_Msk) /**< Shifts the value to the position of endpoint type(EPType) in the HCCHAR register*/ +#define USB_CH_HCCHARx_MCEC(x) (((uint32_t) x << USB_CH_HCCHAR_MC_EC_Pos) & (uint32_t)USB_CH_HCCHAR_MC_EC_Msk) /**< Shifts the value to the position of multi-count(MC_EC) field in the HCCHAR register*/ +#define USB_CH_HCCHARx_DEVADDR(x) (((uint32_t) x << USB_CH_HCCHAR_DevAddr_Pos) & (uint32_t)USB_CH_HCCHAR_DevAddr_Msk) /**< Shifts the value to the position of endpoint type(EPType) in the HCCHAR register*/ +#define USB_CH_HCCHARx_EPDIR(x) (((uint32_t) x << USB_CH_HCCHAR_EPDir_Pos) & (uint32_t)USB_CH_HCCHAR_EPDir_Msk) /**< Shifts the value to the position of endpoint direction(EPDir) in the HCCHAR register*/ +#define USB_CH_HCCHAR_LSDEV_Msk (((uint32_t) 0x1 << 15U) & 0x1U) +#define USB_CH_HCTSIZx_DPID(x) (((uint32_t) x << USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos) & (uint32_t)USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk) /**< Shifts the value to the position of packet ID (PID) in the HCTSIZ register*/ +#define USB_CH_HCTSIZx_DPID_DATA0 (USB_CH_HCTSIZx_DPID(0U)) /**< Represents DATA toggle DATA0 as in HCTSIZ register*/ +#define USB_CH_HCTSIZx_DPID_DATA2 (USB_CH_HCTSIZx_DPID(1U)) /**< Represents DATA toggle DATA2 as in HCTSIZ register*/ +#define USB_CH_HCTSIZx_DPID_DATA1 (USB_CH_HCTSIZx_DPID(2U)) /**< Represents DATA toggle DATA1 as in HCTSIZ register*/ +#define USB_CH_HCTSIZx_DPID_MDATA (USB_CH_HCTSIZx_DPID(3U)) /**< Represents DATA toggle MDATA as in HCTSIZ register*/ +#define USB_CH_HCTSIZx_DPID_SETUP (USB_CH_HCTSIZx_DPID(3U)) /**< Represents SETUP token as in HCTSIZ register*/ +#define USB_GRXSTSR_HOSTMODE_PktSts_IN_DATA_PKT 0x2 /**< Represents IN data token as in receive status pop register(GRXSTSP)*/ +#define USB_GRXSTSR_HOSTMODE_PktSts_IN_TRSF_CPL 0x3 /**< Represents paket status information as in receive status pop register(GRXSTSP)*/ + + +#define USB_CH_HCFG_FSLSSUP(x) (((uint32_t) x << USB_HCFG_FSLSSupp_Pos) & USB_HCFG_FSLSSupp_Msk) /**< Provides register value to update USB full speed related mask FLSSupp of register HCFG*/ +#define USB_CH_HCFG_FSLSPCS(x) (((uint32_t) x ) & USB_HCFG_FSLSPclkSel_Msk) /**< Provides register value to update PHY clock selection in register HCFG*/ + +#define USB_CH_HCINTx_ALL (USB_CH_HCINTMSK_XferComplMsk_Msk | \ + USB_CH_HCINTMSK_ChHltdMsk_Msk | \ + USB_CH_HCINTMSK_StallMsk_Msk | \ + USB_CH_HCINTMSK_NakMsk_Msk | \ + USB_CH_HCINTMSK_AckMsk_Msk | \ + USB_CH_HCINTMSK_XactErrMsk_Msk | \ + USB_CH_HCINTMSK_BblErrMsk_Msk | \ + USB_CH_HCINTMSK_FrmOvrunMsk_Msk | \ + USB_CH_HCINTMSK_DataTglErrMsk_Msk) /**< Mask for selecting all channel related events*/ + +#define USB_CH_HCINTx_ERRORS (USB_CH_HCINTMSK_XactErrMsk_Msk | \ + USB_CH_HCINTMSK_BblErrMsk_Msk | \ + USB_CH_HCINTMSK_FrmOvrunMsk_Msk | \ + USB_CH_HCINTMSK_DataTglErrMsk_Msk) /**< Mask for selecting all channel error related events*/ +/*Macro to find pipe index using handle*/ +#define USBH_PIPE_GET_INDEX(handle) (((uint32_t)handle - (uint32_t)USB0_CH0_BASE)/(0x20U)) /**< Macro provides index of the USB channel based on its base address*/ + +#define XMC_USBH_API_VERSION ((uint16_t)((uint16_t)XMC_LIB_MAJOR_VERSION << 8U) |XMC_LIB_MINOR_VERSION) /**< USBH low level driver API version */ + +/* General return codes */ +#define XMC_USBH_DRIVER_OK 0 /**< Operation succeeded */ +#define XMC_USBH_DRIVER_ERROR -1 /**< Unspecified error */ +#define XMC_USBH_DRIVER_ERROR_BUSY -2 /**< Driver is busy*/ +#define XMC_USBH_DRIVER_ERROR_TIMEOUT -3 /**< Timeout occurred */ +#define XMC_USBH_DRIVER_ERROR_UNSUPPORTED -4 /**< Operation not supported*/ +#define XMC_USBH_DRIVER_ERROR_PARAMETER -5 /**< Parameter error*/ +#define XMC_USBH_DRIVER_ERROR_SPECIFIC -6 /**< Start of driver specific errors*/ + +/* USB Speed */ +#define XMC_USBH_SPEED_LOW 0U /**< Low-speed USB*/ +#define XMC_USBH_SPEED_FULL 1U /**< Full-speed USB*/ +#define XMC_USBH_SPEED_HIGH 2U /**< High-speed USB*/ + +/* USB Endpoint Type */ +#define XMC_USBH_ENDPOINT_CONTROL 0 /**< Control Endpoint*/ +#define XMC_USBH_ENDPOINT_ISOCHRONOUS 1 /**< Isochronous Endpoint*/ +#define XMC_USBH_ENDPOINT_BULK 2 /**< Bulk Endpoint*/ +#define XMC_USBH_ENDPOINT_INTERRUPT 3 /**< Interrupt Endpoint*/ + +#define XMC_USBH_SignalEndpointEvent_t XMC_USBH_SignalPipeEvent_t /**< Legacy name for the pipe event handler*/ + +/****** USB Host Packet Information *****/ +#define XMC_USBH_PACKET_TOKEN_Pos 0 /**< Packet token position*/ +#define XMC_USBH_PACKET_TOKEN_Msk (0x0FUL << XMC_USBH_PACKET_TOKEN_Pos) /**< Packet token mask*/ +#define XMC_USBH_PACKET_SETUP (0x01UL << XMC_USBH_PACKET_TOKEN_Pos) /**< SETUP Packet*/ +#define XMC_USBH_PACKET_OUT (0x02UL << XMC_USBH_PACKET_TOKEN_Pos) /**< OUT Packet*/ +#define XMC_USBH_PACKET_IN (0x03UL << XMC_USBH_PACKET_TOKEN_Pos) /**< IN Packet*/ +#define XMC_USBH_PACKET_PING (0x04UL << XMC_USBH_PACKET_TOKEN_Pos) /**< PING Packet*/ + +#define XMC_USBH_PACKET_DATA_Pos 4 /**< Packet data PID position*/ +#define XMC_USBH_PACKET_DATA_Msk (0x0FUL << XMC_USBH_PACKET_DATA_Pos) /**< Packet data PID mask*/ +#define XMC_USBH_PACKET_DATA0 (0x01UL << XMC_USBH_PACKET_DATA_Pos) /**< DATA0 PID */ +#define XMC_USBH_PACKET_DATA1 (0x02UL << XMC_USBH_PACKET_DATA_Pos) /**< DATA1 PID */ + +#define XMC_USBH_PACKET_SPLIT_Pos 8 +#define XMC_USBH_PACKET_SPLIT_Msk (0x0FUL << XMC_USBH_PACKET_SPLIT_Pos) +#define XMC_USBH_PACKET_SSPLIT (0x08UL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet */ +#define XMC_USBH_PACKET_SSPLIT_S (0x09UL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet: Data Start */ +#define XMC_USBH_PACKET_SSPLIT_E (0x0AUL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet: Data End */ +#define XMC_USBH_PACKET_SSPLIT_S_E (0x0BUL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet: Data All */ +#define XMC_USBH_PACKET_CSPLIT (0x0CUL << XMC_USBH_PACKET_SPLIT_Pos) /**< CSPLIT Packet */ + +#define XMC_USBH_PACKET_PRE (1UL << 12) /**< PRE Token */ + + +/****** USB Host Port Event *****/ +#define XMC_USBH_EVENT_CONNECT (1UL << 0) /**< USB Device Connected to Port */ +#define XMC_USBH_EVENT_DISCONNECT (1UL << 1) /**< USB Device Disconnected from Port */ +#define XMC_USBH_EVENT_OVERCURRENT (1UL << 2) /**< USB Device caused Overcurrent */ +#define XMC_USBH_EVENT_RESET (1UL << 3) /**< USB Reset completed */ +#define XMC_USBH_EVENT_SUSPEND (1UL << 4) /**< USB Suspend occurred */ +#define XMC_USBH_EVENT_RESUME (1UL << 5) /**< USB Resume occurred */ +#define XMC_USBH_EVENT_REMOTE_WAKEUP (1UL << 6) /**< USB Device activated Remote Wakeup */ + +/****** USB Host Pipe Event *****/ +#define XMC_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0) /**< Transfer completed */ +#define XMC_USBH_EVENT_HANDSHAKE_NAK (1UL << 1) /**< NAK Handshake received */ +#define XMC_USBH_EVENT_HANDSHAKE_NYET (1UL << 2) /**< NYET Handshake received */ +#define XMC_USBH_EVENT_HANDSHAKE_MDATA (1UL << 3) /**< MDATA Handshake received */ +#define XMC_USBH_EVENT_HANDSHAKE_STALL (1UL << 4) /**< STALL Handshake received */ +#define XMC_USBH_EVENT_HANDSHAKE_ERR (1UL << 5) /**< ERR Handshake received */ +#define XMC_USBH_EVENT_BUS_ERROR (1UL << 6) /**< Bus Error detected */ +/******************************************************************************* + * ENUMS + *******************************************************************************/ +/** + * @brief General power states of USB peripheral driver +*/ +typedef enum XMC_USBH_POWER_STATE { + XMC_USBH_POWER_OFF, /**< Power off: no operation possible */ + XMC_USBH_POWER_LOW, /**< Low Power mode: retain state, detect and signal wake-up events */ + XMC_USBH_POWER_FULL /**< Power on: full operation at maximum performance */ +} XMC_USBH_POWER_STATE_t; +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ +/** + * @brief USB host Driver Version +*/ +typedef struct XMC_USBH_DRIVER_VERSION { + uint16_t api; /**< API version */ + uint16_t drv; /**< Driver version */ +} XMC_USBH_DRIVER_VERSION_t; + + +/** + * @brief USB Host Port State +*/ +typedef struct XMC_USBH_PORT_STATE { + uint32_t connected : 1; /**< USB Host Port connected flag */ + uint32_t overcurrent : 1; /**< USB Host Port overcurrent flag */ + uint32_t speed : 2; /**< USB Host Port speed setting (ARM_USB_SPEED_xxx) */ +} XMC_USBH_PORT_STATE_t; + +/** + * @brief USB Host Pipe Handle. It represents the physical address of a USB channel +*/ +typedef uint32_t XMC_USBH_PIPE_HANDLE; +#define XMC_USBH_EP_HANDLE XMC_USBH_PIPE_HANDLE /**< Legacy name for pipe handle used by CMSIS*/ + +/** + * @brief USB Host Driver Capabilities. +*/ +typedef struct XMC_USBH_CAPABILITIES { + uint32_t port_mask : 15; /**< Root HUB available Ports Mask */ + uint32_t auto_split : 1; /**< Automatic SPLIT packet handling */ + uint32_t event_connect : 1; /**< Signal Connect event */ + uint32_t event_disconnect : 1; /**< Signal Disconnect event */ + uint32_t event_overcurrent : 1; /**< Signal Overcurrent event */ +} XMC_USBH_CAPABILITIES_t; + + +typedef void (*XMC_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event); /**< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event. */ +typedef void (*XMC_USBH_SignalPipeEvent_t) (XMC_USBH_PIPE_HANDLE pipe_hndl, uint32_t event); /**< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event. */ + +/** + * @brief Access structure of USB Host Driver. +*/ +typedef struct XMC_USBH_DRIVER { + XMC_USBH_DRIVER_VERSION_t (*GetVersion) (void); /**< Pointer to \ref ARM_USBH_GetVersion : Get driver version. */ + XMC_USBH_CAPABILITIES_t (*GetCapabilities) (void); /**< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities. */ + int32_t (*Initialize) (XMC_USBH_SignalPortEvent_t cb_port_event, + XMC_USBH_SignalPipeEvent_t cb_pipe_event); /**< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface. */ + int32_t (*Uninitialize) (void); /**< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface. */ + int32_t (*PowerControl) (XMC_USBH_POWER_STATE_t state); /**< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power. */ + int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); /**< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off. */ + int32_t (*PortReset) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset. */ + int32_t (*PortSuspend) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs). */ + int32_t (*PortResume) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs). */ + XMC_USBH_PORT_STATE_t (*PortGetState) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State. */ + XMC_USBH_PIPE_HANDLE (*PipeCreate) (uint8_t dev_addr, + uint8_t dev_speed, + uint8_t hub_addr, + uint8_t hub_port, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_max_packet_size, + uint8_t ep_interval); /**< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System. */ + int32_t (*PipeModify) (XMC_USBH_PIPE_HANDLE pipe_hndl, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t hub_addr, + uint8_t hub_port, + uint16_t ep_max_packet_size); /**< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System. */ + int32_t (*PipeDelete) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System. */ + int32_t (*PipeReset) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe. */ + int32_t (*PipeTransfer) (XMC_USBH_PIPE_HANDLE pipe_hndl, + uint32_t packet, + uint8_t *data, + uint32_t num); /**< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe. */ + uint32_t (*PipeTransferGetResult) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer. */ + int32_t (*PipeTransferAbort) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer. */ + uint16_t (*GetFrameNumber) (void); /**< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number. */ +} const XMC_USBH_DRIVER_t; + + +/** + * @brief Structure to handle various states of USB host driver. An instance exists for each USB channel + */ +typedef struct XMC_USBH0_pipe { + uint32_t packet; /**< Holds packet token and PID information of ongoing data packet transaction*/ + uint8_t *data; /**< Holds address of data buffer. It represents source buffer for OUT or SETUP transfer and + destination address for IN transfer*/ + uint32_t num; /**< Number of bytes of data to be transmitted*/ + uint32_t num_transferred_total; /**< Number of bytes transmitted or received at the moment*/ + uint32_t num_transferring; /**< Number of bytes being transmitted currently*/ + uint16_t ep_max_packet_size; /**< Maximum packet size for the selected pipe*/ + uint16_t interval_reload; /**< For INTERRUPT or ISOCHRONOUS pipe, it represents the period for repeated transfer*/ + uint16_t interval; /**< For INTERRUPT or ISOCHRONOUS pipe, it represents the decrementing count to reach 0 for initiating retransmission*/ + uint8_t ep_type; /**< Endpoint type for selected pipe*/ + uint8_t in_use; /**< Set to true when transfer is in progress and reset only after the /ref num of bytes is transferred*/ + uint8_t transfer_active; /**< Set to true when a transfer has been initiated and reset when event for transfer complete occurs*/ + uint8_t interrupt_triggered; /**< For INTERRUPT or ISOCHRONOUS pipe, indicates if retransmit timeout has occurred*/ + uint8_t event; /**< Holds pipe specific event flags*/ +} XMC_USBH0_pipe_t; + + +typedef struct xmc_usb_host_device { + USB0_GLOBAL_TypeDef *global_register; /**< Global register interface */ + USB0_CH_TypeDef *host_channel_registers; /**< Host channel interface */ + XMC_USBH_SignalPortEvent_t SignalPortEvent_cb; /**< Port event callback; set during init */ + XMC_USBH_SignalPipeEvent_t SignalPipeEvent_cb; /**< Pipe event callback; set during init */ + bool init_done; /**< init status */ + XMC_USBH_POWER_STATE_t power_state; /**< USB Power status */ + bool port_reset_active; /**< Port reset state */ +} XMC_USBH0_DEVICE_t; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param gintsts USB global interrupt status. + * @return None. + * + * \parDescription:
+ * Updates logical state of the USB host driver based on the input status value. It handles port interrupt + * and channel interrupt. It responsible for updating data toggle information for multi-packet data transmission. + * It executes the callback function on transfer completion and reception of data. It also does error management and + * calls the relevant callback functions to indicate it to the application. + */ +void XMC_USBH_HandleIrq (uint32_t gintsts); +/** + * @param ms Delay in milliseconds. + * @return uint8_t Value has no significance for the low level driver. + * + * \parDescription:
+ * Function implements time delay logic. The USB host low level driver provides a weak definition + * for delay which has to re-implemented with time delay logic. The low level driver expects blocking + * implementation of the delay. + */ + uint8_t XMC_USBH_osDelay(uint32_t ms); + +/** + * @param port Address of the port which has the pin used to enable VBUS charge pump. + * @param pin Pin number in the port selected in previous argument using which the VBUS charge pump has to be enabled. + * @return None + * + * \parDescription:
+ * Configures the port pin with alternate output function 1. VBUS enabling pins work with alternate output function 1. \n + * Note:The input port pin should support USB VBUS as an alternate function. \n + * Typical ports that support VBUS enable are: P3_2 and P0_1. + * + */ +void XMC_USBH_Select_VBUS(XMC_GPIO_PORT_t* port, uint32_t pin); + +/** + * @return USB host mode interrupt status. Bit field USB0_BASE->GINTSTS_HOSTMODE + * + * \parDescription:
+ * Provides USB host global interrupt status. \n + * This value can be used to provide interrupt status to the IRQ handler function XMC_USBH_HandleIrq(). + * + */ +uint32_t XMC_USBH_GetInterruptStatus(void); + +/** + * @return None + * + * \parDescription:
+ * De-asserts resume bit. \n + * The function shall be called 20ms after detecting port remote wakeup event. \n + * + */ +void XMC_USBH_TurnOffResumeBit(void); +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +/** + * @} + */ +#endif +#endif /* XMC_USBH_H */ + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usic.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usic.h new file mode 100644 index 00000000..6eeb2daa --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_usic.h @@ -0,0 +1,2089 @@ +/** + * @file xmc_usic.h + * @date 2017-02-10 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * - Documentation improved
+ * + * 2015-05-08: + * - Added XMC_USIC_CH_SetInputTriggerCombinationMode() and XMC_USIC_CH_SetTransmitBufferStatus()
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-08-17: + * - Bug fixed in XMC_USIC_CH_SetTransmitBufferStatus API. OR operator removed. + * + * 2015-08-24: + * - Added APIs for enabling/disabling delay compensation XMC_USIC_CH_DisableDelayCompensation() and + * XMC_USIC_CH_DisableDelayCompensation() + * + * 2015-08-25: + * - Added APIs for defining if the data shift unit input is derived + * from the input data path DXn or from the selected protocol pre-processors: XMC_USIC_CH_ConnectInputDataShiftToPPP() + * and XMC_USIC_CH_ConnectInputDataShiftToDataInput() + * + * 2015-08-27: + * - Fixed bug in XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T value. + * - Added APIs for direct TBUF access: XMC_USIC_CH_WriteToTBUF() and XMC_USIC_CH_WriteToTBUFTCI() + * - Added APIs for external input for BRG configuration:XMC_USIC_CH_ConfigExternalInputSignalToBRG() and XMC_USIC_CH_SetBRGInputClockSource() + * + * 2015-08-28: + * - Added API for enabling the transfer trigger unit to set bit TCSR.TE if the trigger signal DX2T becomes active. Feature used for RS-232 + * Clear to Send (CTS) signal: XMC_USIC_CH_EnableTBUFDataValidTrigger() and XMC_USIC_CH_DisableTBUFDataValidTrigger(). + * + * 2016-03-09: + * - Optimization of write only registers + * + * 2016-04-10: + * - Added an API to put the data into FIFO when hardware port control is enabled: XMC_USIC_CH_TXFIFO_PutDataHPCMode()
+ * + * 2017-02-10: + * - Added XMC_USIC_CH_SetShiftDirection() to allow selection of shift direction of the data words for transmision and reception + * - Added XMC_USIC_CH_GetCaptureTimerValue() and XMC_USIC_CH_SetFractionalDivider() + * + * @endcond + * + */ + +#ifndef XMC_USIC_H +#define XMC_USIC_H +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_common.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup USIC + * @brief Universal Serial Interface Channel(USIC) driver for serial communication. + * + * The Universal Serial Interface Channel(USIC) module is a flexible interface module + * covering several serial communication protocols. A USIC module contains two + * independent communication channels named USICx_CH0 and USICx_CH1, with x + * being the number of the USIC module. The user can program, during run-time, which protocol will be handled + * by each communication channel and which pins are used. + * The driver provides APIs, configuration structures and enumerations to configure common features of multiple serial + * communication protocols. + * + * USIC driver features: + * -# Allows configuration of FIFO for transmit and receive functions. + * -# Provides a structure type XMC_USIC_CH_t to represent the USIC channel registers in a programmer + friendly format. + * -# Allows configuration of automatic update for frame length, word length, slave select or slave address. + * -# Allows transmission of data to FIFO using XMC_USIC_CH_TXFIFO_PutData() and XMC_USIC_CH_TXFIFO_PutDataFLEMode() + * -# Allows reading of received data in FIFO using XMC_USIC_CH_RXFIFO_GetData() + * -# Allows configuration of baudrate using XMC_USIC_CH_SetBaudrate() + * -# Provides API to trigger interrupts using XMC_USIC_CH_TriggerServiceRequest() + * @{ + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define XMC_USIC0 ((XMC_USIC_t *)USIC0_BASE) /**< USIC0 module base address */ +#define XMC_USIC0_CH0 ((XMC_USIC_CH_t *)USIC0_CH0_BASE) /**< USIC0 channel 0 base address */ +#define XMC_USIC0_CH1 ((XMC_USIC_CH_t *)USIC0_CH1_BASE) /**< USIC0 channel 1 base address */ + +#if defined(USIC1) +#define XMC_USIC1 ((XMC_USIC_t *)USIC1_BASE) /**< USIC1 module base address */ +#define XMC_USIC1_CH0 ((XMC_USIC_CH_t *)USIC1_CH0_BASE) /**< USIC1 channel 0 base address */ +#define XMC_USIC1_CH1 ((XMC_USIC_CH_t *)USIC1_CH1_BASE) /**< USIC1 channel 1 base address */ +#endif + +#if defined(USIC2) +#define XMC_USIC2 ((XMC_USIC_t *)USIC2_BASE) /**< USIC2 module base address */ +#define XMC_USIC2_CH0 ((XMC_USIC_CH_t *)USIC2_CH0_BASE) /**< USIC2 channel 0 base address */ +#define XMC_USIC2_CH1 ((XMC_USIC_CH_t *)USIC2_CH1_BASE) /**< USIC2 channel 1 base address */ +#endif + +#define USIC_CH_DXCR_DSEL_Msk USIC_CH_DX0CR_DSEL_Msk /**< Common mask for DSEL bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_DSEL_Pos USIC_CH_DX0CR_DSEL_Pos /**< Common mask for DSEL bitfield position in DXnCR register */ +#define USIC_CH_DXCR_SFSEL_Pos USIC_CH_DX0CR_SFSEL_Pos /**< Common mask for SFSEL bitfield position in DXnCR register */ +#define USIC_CH_DXCR_SFSEL_Msk USIC_CH_DX0CR_SFSEL_Msk /**< Common mask for SFSEL bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_DPOL_Msk USIC_CH_DX0CR_DPOL_Msk /**< Common mask for DPOL bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_DFEN_Msk USIC_CH_DX0CR_DFEN_Msk /**< Common mask for DFEN bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_DSEN_Msk USIC_CH_DX0CR_DSEN_Msk /**< Common mask for DSEN bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_CM_Pos USIC_CH_DX0CR_CM_Pos /**< Common mask for CM bitfield position in DXnCR register */ +#define USIC_CH_DXCR_CM_Msk USIC_CH_DX0CR_CM_Msk /**< Common mask for CM bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_INSW_Msk USIC_CH_DX0CR_INSW_Msk /**< Common mask for INSW bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_INSW_pos USIC_CH_DX0CR_INSW_Pos /**< Common mask for INSW bitfield position in DXnCR register */ + +#if UC_FAMILY == XMC1 + #include "xmc1_usic_map.h" +#endif + +#if UC_FAMILY == XMC4 + #include "xmc4_usic_map.h" +#endif + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * USIC channel driver status + */ +typedef enum XMC_USIC_CH_STATUS +{ + XMC_USIC_CH_STATUS_OK, /**< USIC driver status : OK */ + XMC_USIC_CH_STATUS_ERROR, /**< USIC driver status : ERROR */ + XMC_USIC_CH_STATUS_BUSY /**< USIC driver status : BUSY */ +} XMC_USIC_CH_STATUS_t; + +/** +* USIC channel kernel mode +*/ +typedef enum XMC_USIC_CH_KERNEL_MODE +{ + XMC_USIC_CH_KERNEL_MODE_RUN_0 = 0x0UL, /**< Run mode 0 (transmission and reception possible)*/ + XMC_USIC_CH_KERNEL_MODE_RUN_1 = 0x1UL << USIC_CH_KSCFG_NOMCFG_Pos, /**< Run mode 1 (transmission and reception possible)*/ + XMC_USIC_CH_KERNEL_MODE_STOP_0 = 0x2UL << USIC_CH_KSCFG_NOMCFG_Pos, /**< Stop mode 0 (no transmission, but reception possible)*/ + XMC_USIC_CH_KERNEL_MODE_STOP_1 = 0x3UL << USIC_CH_KSCFG_NOMCFG_Pos /**< Stop mode 1 (both transmission and reception not possible)*/ +} XMC_USIC_CH_KERNEL_MODE_t; + +/** + * USIC channel operating mode + */ +typedef enum XMC_USIC_CH_OPERATING_MODE +{ + XMC_USIC_CH_OPERATING_MODE_IDLE = 0x0UL, /**< USIC channel idle */ + XMC_USIC_CH_OPERATING_MODE_SPI = 0x1UL << USIC_CH_CCR_MODE_Pos, /**< SPI mode */ + XMC_USIC_CH_OPERATING_MODE_UART = 0x2UL << USIC_CH_CCR_MODE_Pos, /**< UART mode */ + XMC_USIC_CH_OPERATING_MODE_I2S = 0x3UL << USIC_CH_CCR_MODE_Pos, /**< I2S mode */ + XMC_USIC_CH_OPERATING_MODE_I2C = 0x4UL << USIC_CH_CCR_MODE_Pos /**< I2C mode */ +} XMC_USIC_CH_OPERATING_MODE_t; + +/** + * USIC channel inputs + */ +typedef enum XMC_USIC_CH_INPUT +{ + XMC_USIC_CH_INPUT_DX0, /**< DX0 input */ + XMC_USIC_CH_INPUT_DX1, /**< DX1 input */ + XMC_USIC_CH_INPUT_DX2, /**< DX2 input */ + XMC_USIC_CH_INPUT_DX3, /**< DX3 input */ + XMC_USIC_CH_INPUT_DX4, /**< DX4 input */ + XMC_USIC_CH_INPUT_DX5 /**< DX5 input */ +} XMC_USIC_CH_INPUT_t; + +/** + * USIC channel input source sampling frequency + */ +typedef enum XMC_USIC_CH_INPUT_SAMPLING_FREQ +{ + XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH = 0x0UL, /**< Use fperiph frequency for input source sampling*/ + XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER = 0x1UL << USIC_CH_DXCR_SFSEL_Pos /**< Use fFD(fractional divider) frequency for input source sampling*/ +} XMC_USIC_CH_INPUT_SAMPLING_FREQ_t; + +/** + * USIC channel input combination mode + */ +typedef enum XMC_USIC_CH_INPUT_COMBINATION_MODE +{ + XMC_USIC_CH_INPUT_COMBINATION_MODE_TRIGGER_DISABLED = 0x0UL, /**< The trigger activation is disabled.*/ + XMC_USIC_CH_INPUT_COMBINATION_MODE_RISING_EDGE = 0x1UL, /**< A rising edge activates DXnT*/ + XMC_USIC_CH_INPUT_COMBINATION_MODE_FALLING_EDGE = 0x2UL, /**< A falling edge activates DXnT*/ + XMC_USIC_CH_INPUT_COMBINATION_MODE_BOTH_EDGES = 0x3UL, /**< Both edges activate DXnT*/ +} XMC_USIC_CH_INPUT_COMBINATION_MODE_t; + +/** + * USIC channel data transmission start modes. + * Data shifted out of the transmit pin depends on the value configured for the + * TDEN bitfield of the TCSR register. Following enum values are used for configuring + * the TCSR->TDEN bitfield. + */ +typedef enum XMC_USIC_CH_START_TRANSMISION_MODE +{ + XMC_USIC_CH_START_TRANSMISION_DISABLED = 0x0U, /**< Passive data level is sent out on transmission. */ + XMC_USIC_CH_START_TRANSMISION_ON_TDV = 0x1UL << USIC_CH_TCSR_TDEN_Pos, /**< Transmission of the data word in TBUF can be started if TDV = 1 */ + XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0 = 0x2UL << USIC_CH_TCSR_TDEN_Pos, /**< Transmission of the data word in TBUF can be started if TDV = 1 while DX2S_0 */ + XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1 = 0x3UL << USIC_CH_TCSR_TDEN_Pos /**< Transmission of the data word in TBUF can be started if TDV = 1 while DX2S_1 */ +} XMC_USIC_CH_START_TRANSMISION_MODE_t; + +/** + * USIC channel interrupt node pointers + */ +typedef enum XMC_USIC_CH_INTERRUPT_NODE_POINTER +{ + XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = USIC_CH_INPR_TSINP_Pos, /**< Node pointer for transmit shift interrupt */ + XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = USIC_CH_INPR_TBINP_Pos, /**< Node pointer for transmit buffer interrupt */ + XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE = USIC_CH_INPR_RINP_Pos, /**< Node pointer for receive interrupt */ + XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = USIC_CH_INPR_AINP_Pos, /**< Node pointer for alternate receive interrupt */ + XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL = USIC_CH_INPR_PINP_Pos /**< Node pointer for protocol related interrupts */ +} XMC_USIC_CH_INTERRUPT_NODE_POINTER_t; + +/** + * USIC channel events + */ +typedef enum XMC_USIC_CH_EVENT +{ + XMC_USIC_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */ + XMC_USIC_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */ + XMC_USIC_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */ + XMC_USIC_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */ + XMC_USIC_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */ + XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */ + XMC_USIC_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk /**< Baudrate generator event */ +} XMC_USIC_CH_EVENT_t; + +/** +* USIC channel parity mode +*/ +typedef enum XMC_USIC_CH_PARITY_MODE +{ + XMC_USIC_CH_PARITY_MODE_NONE = 0x0UL, /**< Disable parity mode */ + XMC_USIC_CH_PARITY_MODE_EVEN = 0x2UL << USIC_CH_CCR_PM_Pos, /**< Enable even parity mode */ + XMC_USIC_CH_PARITY_MODE_ODD = 0x3UL << USIC_CH_CCR_PM_Pos /**< Enable odd parity mode */ +} XMC_USIC_CH_PARITY_MODE_t; + +/** +* USIC channel data output mode +*/ +typedef enum XMC_USIC_CH_DATA_OUTPUT_MODE +{ + XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL = 0x0UL, /**< Data output normal mode */ + XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED = 0x1UL << USIC_CH_SCTR_DOCFG_Pos /**< Data output inverted mode */ +} XMC_USIC_CH_DATA_OUTPUT_MODE_t; + +/** +* USIC channel data transmit buffer status +*/ +typedef enum XMC_USIC_CH_TBUF_STATUS +{ + XMC_USIC_CH_TBUF_STATUS_IDLE = 0x0UL, /**< Transfer buffer is currently idle*/ + XMC_USIC_CH_TBUF_STATUS_BUSY = USIC_CH_TCSR_TDV_Msk /**< Transfer buffer is currently busy*/ +} XMC_USIC_CH_TBUF_STATUS_t; + + + +/** +* USIC channel data transmit buffer status modification +*/ +typedef enum XMC_USIC_CH_TBUF_STATUS_SET +{ + XMC_USIC_CH_TBUF_STATUS_SET_BUSY = 0x1UL, /**< Set Transfer buffer status to busy*/ + XMC_USIC_CH_TBUF_STATUS_SET_IDLE = 0x2UL /**< Set Transfer buffer status to idle*/ +} XMC_USIC_CH_TBUF_STATUS_SET_t; + +/** +* USIC channel receive buffer status +*/ +typedef enum XMC_USIC_CH_RBUF_STATUS +{ + XMC_USIC_CH_RBUF_STATUS_DATA_VALID0 = USIC_CH_RBUFSR_RDV0_Msk, /**< RBUF0 data has not yet been read out*/ + XMC_USIC_CH_RBUF_STATUS_DATA_VALID1 = USIC_CH_RBUFSR_RDV1_Msk /**< RBUF1 data has not yet been read out*/ +} XMC_USIC_CH_RBUF_STATUS_t; + +/** + * USIC channel output signal passive data level +*/ +typedef enum XMC_USCI_CH_PASSIVE_DATA_LEVEL +{ + XMC_USIC_CH_PASSIVE_DATA_LEVEL0 = 0x0UL, /**< Passive level(idle mode signal level) 0 */ + XMC_USIC_CH_PASSIVE_DATA_LEVEL1 = 0x1UL << USIC_CH_SCTR_PDL_Pos /**< Passive level(idle mode signal level) 1 */ +} XMC_USIC_CH_PASSIVE_DATA_LEVEL_t; + +/** +* USIC channel receive FIFO size +*/ +typedef enum XMC_USIC_CH_FIFO_SIZE +{ + XMC_USIC_CH_FIFO_DISABLED = 0x0U, /**< FIFO Disabled */ + XMC_USIC_CH_FIFO_SIZE_2WORDS = 0x1U, /**< FIFO size: 2 words */ + XMC_USIC_CH_FIFO_SIZE_4WORDS = 0x2U, /**< FIFO size: 4 words */ + XMC_USIC_CH_FIFO_SIZE_8WORDS = 0x3U, /**< FIFO size: 8 words */ + XMC_USIC_CH_FIFO_SIZE_16WORDS = 0x4U, /**< FIFO size: 16 words */ + XMC_USIC_CH_FIFO_SIZE_32WORDS = 0x5U, /**< FIFO size: 32 words */ + XMC_USIC_CH_FIFO_SIZE_64WORDS = 0x6U /**< FIFO size: 64 words */ +} XMC_USIC_CH_FIFO_SIZE_t; + +/** +* USIC channel transmit FIFO interrupt node pointers +*/ +typedef enum XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER +{ + XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD = USIC_CH_TBCTR_STBINP_Pos, /**< Node pointer for FIFO standard transmit interrupt */ + XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE = USIC_CH_TBCTR_ATBINP_Pos /**< Node pointer for transmit FIFO error interrupt */ +} XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t; + +/** +* USIC channel transmit FIFO event configuration +*/ +typedef enum XMC_USIC_CH_TXFIFO_EVENT_CONF +{ + XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD = USIC_CH_TBCTR_STBIEN_Msk, /**< Enable FIFO standard transmit interrupt */ + XMC_USIC_CH_TXFIFO_EVENT_CONF_ERROR = (int32_t)USIC_CH_TBCTR_TBERIEN_Msk /**< Enable transmit FIFO error interrupt */ +} XMC_USIC_CH_TXFIFO_EVENT_CONF_t; + +/** +* USIC channel transmit FIFO status +*/ +typedef enum XMC_USIC_CH_TXFIFO_EVENT +{ + XMC_USIC_CH_TXFIFO_EVENT_STANDARD = USIC_CH_TRBSR_STBI_Msk, /**< Transmit FIFO status: Standard event */ + XMC_USIC_CH_TXFIFO_EVENT_ERROR = USIC_CH_TRBSR_TBERI_Msk /**< Transmit FIFO status: Error event */ +} XMC_USIC_CH_TXFIFO_EVENT_t; + +/** +* USIC channel receive FIFO interrupt node pointers +*/ +typedef enum XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER +{ + XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD = USIC_CH_RBCTR_SRBINP_Pos, /**< Node pointer for FIFO standard receive interrupt */ + XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE = USIC_CH_RBCTR_ARBINP_Pos /**< Node pointer for FIFO alternative receive interrupt */ +} XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t; + +/** +* USIC channel receive FIFO event configuration +*/ +typedef enum XMC_USIC_CH_RXFIFO_EVENT_CONF +{ + XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD = USIC_CH_RBCTR_SRBIEN_Msk, /**< Enable FIFO standard receive interrupt */ + XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR = (int32_t)USIC_CH_RBCTR_RBERIEN_Msk, /**< Enable receive FIFO error interrupt */ + XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE = USIC_CH_RBCTR_ARBIEN_Msk /**< Enable FIFO alternative receive interrupt */ +} XMC_USIC_CH_RXFIFO_EVENT_CONF_t; + +/** +* USIC channel receive FIFO status +*/ +typedef enum XMC_USIC_CH_RXFIFO_EVENT +{ + XMC_USIC_CH_RXFIFO_EVENT_STANDARD = USIC_CH_TRBSR_SRBI_Msk, /**< Receive FIFO status: Standard event */ + XMC_USIC_CH_RXFIFO_EVENT_ERROR = USIC_CH_TRBSR_RBERI_Msk, /**< Receive FIFO status: Error event */ + XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE = USIC_CH_TRBSR_ARBI_Msk /**< Receive FIFO status: Alternative event */ +} XMC_USIC_CH_RXFIFO_EVENT_t; + +/** +* USIC channel baudrate generator clock source +*/ +typedef enum XMC_USIC_CH_BRG_CLOCK_SOURCE +{ + XMC_USIC_CH_BRG_CLOCK_SOURCE_DIVIDER = 0x0UL, /**< Baudrate generator clock source : Source divider. (Internal clock source)*/ + XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T = 0x2UL << USIC_CH_BRG_CLKSEL_Pos /**< Baudrate generator clock source : DX1T. (External clock source) */ +} XMC_USIC_CH_BRG_CLOCK_SOURCE_t; + +/** +* USIC channel baudrate generator divider mode +*/ +typedef enum XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE +{ + XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_DISABLED = 0x0UL, /**< Baudrate generator clock divider: Disabled */ + XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL = 0x1UL << USIC_CH_FDR_DM_Pos, /**< Baudrate generator clock divider: Normal mode */ + XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL = 0x2UL << USIC_CH_FDR_DM_Pos /**< Baudrate generator clock divider: Fractional mode */ +} XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t; + +/** +* USIC channel baudrate generator master clock passive level +*/ +typedef enum XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL +{ + XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0 = 0x0UL, /**< Baudrate generator master clock passive level(idle mode signal level) 0*/ + XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1 = 0x1UL << USIC_CH_BRG_MCLKCFG_Pos /**< Baudrate generator master clock passive level((idle mode signal level)) 1*/ +} XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t; + +/** +* USIC channel baudrate generator shift clock passive level +*/ +typedef enum XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL +{ + XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED = 0x0UL, /**< Shift clock passive level 0, delay disabled */ + XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED = 0x1UL << USIC_CH_BRG_SCLKCFG_Pos, /**< Shift clock passive level 1, delay disabled */ + XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED = (int32_t)(0x2UL << USIC_CH_BRG_SCLKCFG_Pos), /**< Shift clock passive level 0, delay enabled */ + XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED = (int32_t)(0x3UL << USIC_CH_BRG_SCLKCFG_Pos) /**< Shift clock passive level 1, delay enabled */ +} XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t; + +/** +* USIC channel baudrate generator shift clock output +*/ +typedef enum XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT +{ + XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = 0x0UL, /**< Baudrate generator shift clock output: SCL.(Internally generated shift clock)*/ + XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = 0x1UL << USIC_CH_BRG_SCLKOSEL_Pos /**< Baudrate generator shift clock output: DX1. (External input shift clock)*/ +} XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t; + +/** +* USIC channel shift direction. +* Defines the shift direction of the data words for transmission and reception +*/ +typedef enum XMC_USIC_CH_SHIFT_DIRECTION +{ + XMC_USIC_CH_SHIFT_DIRECTION_LSB_FIRST = 0x0UL, /**< Shift LSB first. The first data bit of a data word is located at bit position 0. */ + XMC_USIC_CH_SHIFT_DIRECTION_MSB_FIRST = 0x1UL << USIC_CH_SCTR_SDIR_Msk /**< Shift MSB first. The first data bit of a data word is located at the bit position given by the configured word length. */ +} XMC_USIC_CH_SHIFT_DIRECTION_t; + + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * USIC module structure + */ +typedef USIC_GLOBAL_TypeDef XMC_USIC_t; + +/** + * USIC channel structure.
The members of the structure are same as in the device header file, + * except for some registers. + * DX0CR, DX1CR, DX2CR, DX3CR, DX4CR and DX5CR are replaced with the array DXCR[6]. + * TBUF0 to TBUF31 are replaced with TBUF[32]. + * IN0 to IN31 are replaced with IN[32]. + */ +typedef struct XMC_USIC_CH +{ + __I uint32_t RESERVED0; + __I uint32_t CCFG; /**< Channel configuration register*/ + __I uint32_t RESERVED1; + __IO uint32_t KSCFG; /**< Kernel state configuration register*/ + __IO uint32_t FDR; /**< Fractional divider configuration register*/ + __IO uint32_t BRG; /**< Baud rate generator register*/ + __IO uint32_t INPR; /**< Interrupt node pointer register*/ + __IO uint32_t DXCR[6]; /**< Input control registers DX0 to DX5.*/ + __IO uint32_t SCTR; /**< Shift control register*/ + __IO uint32_t TCSR; + + union { + __IO uint32_t PCR_IICMode; /**< I2C protocol configuration register*/ + __IO uint32_t PCR_IISMode; /**< I2S protocol configuration register*/ + __IO uint32_t PCR_SSCMode; /**< SPI protocol configuration register*/ + __IO uint32_t PCR; /**< Protocol configuration register*/ + __IO uint32_t PCR_ASCMode; /**< UART protocol configuration register*/ + }; + __IO uint32_t CCR; /**< Channel control register*/ + __IO uint32_t CMTR; /**< Capture mode timer register*/ + + union { + __IO uint32_t PSR_IICMode; /**< I2C protocol status register*/ + __IO uint32_t PSR_IISMode; /**< I2S protocol status register*/ + __IO uint32_t PSR_SSCMode; /**< SPI protocol status register*/ + __IO uint32_t PSR; /**< Protocol status register*/ + __IO uint32_t PSR_ASCMode; /**< UART protocol status register*/ + }; + __O uint32_t PSCR; /**< Protocol status clear register*/ + __I uint32_t RBUFSR; /**< Receive buffer status register*/ + __I uint32_t RBUF; /**< Receive buffer register*/ + __I uint32_t RBUFD; /**< Debug mode receive buffer register*/ + __I uint32_t RBUF0; /**< Receive buffer 0*/ + __I uint32_t RBUF1; /**< Receive buffer 1*/ + __I uint32_t RBUF01SR; /**< Receive buffer status register*/ + __O uint32_t FMR; /**< Flag modification register*/ + __I uint32_t RESERVED2[5]; + __IO uint32_t TBUF[32]; /**< Tranmsit buffer registers*/ + __IO uint32_t BYP; /**< FIFO bypass register*/ + __IO uint32_t BYPCR; /**< FIFO bypass control register*/ + __IO uint32_t TBCTR; /**< Transmit FIFO control register*/ + __IO uint32_t RBCTR; /**< Receive FIFO control register*/ + __I uint32_t TRBPTR; /**< Transmit/recive buffer pointer register*/ + __IO uint32_t TRBSR; /**< Transmit/receive buffer status register*/ + __O uint32_t TRBSCR; /**< Transmit/receive buffer status clear register*/ + __I uint32_t OUTR; /**< Receive FIFO output register*/ + __I uint32_t OUTDR; /**< Receive FIFO debug output register*/ + __I uint32_t RESERVED3[23]; + __O uint32_t IN[32]; /**< Transmit FIFO input register*/ +} XMC_USIC_CH_t; + + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +/******************************************************************************* + * API PROTOTYPES + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +__STATIC_INLINE bool XMC_USIC_IsModuleValid(const XMC_USIC_t *const module) +{ + bool tmp; + + tmp = (module == XMC_USIC0); +#if defined(XMC_USIC1) + tmp = tmp || (module == XMC_USIC1); +#endif +#if defined(XMC_USIC2) + tmp = tmp || (module == XMC_USIC2); +#endif + + return tmp; +} + +__STATIC_INLINE bool XMC_USIC_IsChannelValid(const XMC_USIC_CH_t *const channel) +{ + bool tmp; + + tmp = ((channel == XMC_USIC0_CH0) || (channel == XMC_USIC0_CH1)); +#if defined(XMC_USIC1) + tmp = tmp || ((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1)); +#endif +#if defined(XMC_USIC2) + tmp = tmp || ((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1)); +#endif + + return tmp; +} + +/* Common APIs */ + +/** + * @param usic Pointer to USIC module handler of type @ref XMC_USIC_t.\n + * \b Range: @ref XMC_USIC0 to @ref XMC_USIC2 based on device support. + * @return None + * + * \parDescription
+ * Enables the USIC module.\n\n + * Enables the clock for the USIC module by following the + * clock enabling sequence for the selected device. + * + * \parRelated APIs:
+ * XMC_USIC_CH_Enable(), XMC_USIC_Disable() \n\n\n + */ +void XMC_USIC_Enable(XMC_USIC_t *const usic); +/** + * @param usic Pointer to USIC module handler of type @ref XMC_USIC_t.\n + * \b Range: @ref XMC_USIC0 to @ref XMC_USIC2 based on device support. + * @return None + * + * \parDescription
+ * Disables the USIC module.\n\n + * Disables the clock for the USIC module by following the clock + * disabling sequence for the selected device. + * + * \parRelated APIs:
+ * XMC_USIC_CH_Disable(), XMC_USIC_Enable() \n\n\n + */ +void XMC_USIC_Disable(XMC_USIC_t *const usic); +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Enables the USIC channel. \n\n + * USIC channel is enabled by setting the module enable bit in KSCFG register bitfield MODEN. + * On enabling, the channel is set to idle mode. + * + * \parRelated APIs:
+ * XMC_USIC_CH_Disable(), XMC_USIC_Enable() \n\n\n + */ +void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel); +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Disables the USIC channel.\n\n + * USIC channel is disabled by setting the module enable bit(MDEN) to 0 in the register KSCFG. + * + * \parRelated APIs:
+ * XMC_USIC_CH_Enable(), XMC_USIC_Disable() \n\n\n + */ +void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param rate Desired baudrate. \b Range: minimum value = 100, maximum value depends on the peripheral clock frequency \n + * and \a oversampling. Maximum baudrate can be derived using the formula: (fperiph * 1023)/(1024 * oversampling) + * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n + * This can be related to the number of samples for each logic state of the data signal. \n + * \b Range: 1 to 32. Value should be chosen based on the protocol used. + * @return Status indicating the baudrate configuration.\n + * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured, + * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid. + * + * \parDescription
+ * Configures the baudrate of the USIC channel. \n\n + * Baudrate is configured by considering the peripheral frequency and the desired baudrate. + * Optimum values of FDR->STEP and BRG->PDIV are calulated and used for generating the desired + * baudrate. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetStartTransmisionMode(), XMC_USIC_CH_SetInputSource() \n\n\n + */ +XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param pdiv Desired divider for the external frequency input. \b Range: minimum value = 1, maximum value = 1024 \n + * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n + * This can be related to the number of samples for each logic state of the data signal. \n + * \b Range: 1 to 32. Value should be chosen based on the protocol used. + * @param combination_mode Selects which edge of the synchronized(and optionally filtered) signal DXnS actives the trigger + * output DXnT of the input stage. + * + * @return None + * + * \parDescription
+ * Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and + * the combination mode of the USIC channel. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n + */ +void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, + const uint16_t pdiv, + const uint32_t oversampling, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @param source Input source select for the input stage. The table below maps the enum value with the input channel. + * + * + *
0DXnA
1DXnB
2DXnC
3DXnD
4DXnE
5DXnF
6DXnG
7Always 1
+ * @return None + * + * \parDescription
+ * Selects the data source for USIC input stage.\n\n + * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the input stages + * like DX0CR, DX1CR etc. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableInputInversion(), XMC_USIC_CH_EnableInputDigitalFilter(), XMC_USIC_CH_EnableInputSync(), + * XMC_USIC_CH_SetInputSamplingFreq()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input, const uint8_t source) +{ + channel->DXCR[input] = (uint32_t)((channel->DXCR[input] & (uint32_t)(~USIC_CH_DXCR_DSEL_Msk)) | + ((uint32_t)source << USIC_CH_DXCR_DSEL_Pos)); +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * The input of the data shift unit is controlled by the + * protocol pre-processor. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_ConnectInputDataShiftToDataInput()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_ConnectInputDataShiftToPPP(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_INSW_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * The input of the data shift unit is connected to + * the selected data input line. \n\n + * + * This setting is used + * if the signals are directly derived from an input + * pin without treatment by the protocol preprocessor. + * \parRelated APIs:
+ * XMC_USIC_CH_ConnectInputDataShiftToPPP()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_ConnectInputDataShiftToDataInput(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] |= USIC_CH_DXCR_INSW_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Enables input inversion for USIC channel input data signal. \n\n + * + * Polarity of the input source can be changed to provide inverted data input. + * \parRelated APIs:
+ * XMC_USIC_CH_DisableInputInversion()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] |= USIC_CH_DXCR_DPOL_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Disables input inversion for USIC channel. \n\n + * + * Resets the input data polarity for the USIC channel input data signal. + * \parRelated APIs:
+ * XMC_USIC_CH_EnableInputInversion()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DPOL_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Enables delay compensation. \n\n + * + * Delay compensation can be applied to the receive path. + * \parRelated APIs:
+ * XMC_USIC_CH_DisableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + channel->DXCR[1U] |= USIC_CH_DX1CR_DCEN_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Disables delay compensation.. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + channel->DXCR[1U] &=(uint32_t)~USIC_CH_DX1CR_DCEN_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Enables the input digital filter for USIC channel input data signal. \n\n + * Input data signal from the selected multiplexer will be digitally filtered. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] |= (uint32_t)USIC_CH_DXCR_DFEN_Msk; +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Disables the input digital filter for USIC channel input data signal. \n\n + * Input data signal from the selected multiplexer will not be digitally filtered. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DFEN_Msk; +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Enables input synchronization for the USIC channel input data signal. \n\n + * Input data signal from the selected multiplexer will be synchronized with fPERIPH. + * A noisy signal can be synchronized and filtered by enabling the digital filter. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableInputSync(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] |=(uint32_t)USIC_CH_DXCR_DSEN_Msk; +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Disables input synchronization for the USIC channel input data signal. \n\n + * Input data signal from the selected multiplexer will not be synchronized. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_DisableInputDigitalFilter() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableInputSync(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DSEN_Msk; +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @param sampling_freq Sampling frequency value of type \a XMC_USIC_CH_INPUT_SAMPLING_FREQ_t. + * @return None + * + * \parDescription
+ * Sets sampling frequency for USIC channel input data signal. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_INPUT_t input, + const XMC_USIC_CH_INPUT_SAMPLING_FREQ_t sampling_freq) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DXCR_SFSEL_Msk)) | + ((uint32_t)sampling_freq); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @param combination_mode Combination mode value of type \a XMC_USIC_CH_INPUT_COMBINATION_MODE_t. + * @return None + * + * \parDescription
+ * Selects which edge of the synchronized signal DXnS activates the trigger output DXnT of the input stage. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetInputTriggerCombinationMode(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_INPUT_t input, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DXCR_CM_Msk)) | + ((uint32_t)combination_mode << USIC_CH_DXCR_CM_Pos); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param clock_source clock source for the BRG. + * @return None + * + * \parDescription
+ * Sets the clock source for the BRG. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetInputTriggerCombinationMode(), XMC_USIC_CH_SetExternalClockBRGDivider()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetBRGInputClockSource(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_BRG_CLOCK_SOURCE_t clock_source) +{ + channel->BRG = (uint32_t)(channel->BRG & (~USIC_CH_BRG_CLKSEL_Msk)) | (uint32_t)(clock_source); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data Data to be transmitted. \n + * \b Range: 16bit unsigned data. minimum= 0, maximum= 65535 + * @return None + * + * \parDescription
+ * Writes data into the transmit buffer. \n\n + * The data provided is placed in TBUF[0U]. + * + * + * \parRelated APIs:
+ * XMC_USIC_CH_WriteToTBUFTCI() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_WriteToTBUF(XMC_USIC_CH_t *const channel, const uint16_t data) +{ + channel->TBUF[0U] = data; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data Data to be transmitted. + * @param transmit_control_information transmit control information to be configured while transmitting the data. \n + * \b Range: minimum= 0, maximum= 31. + * @return None + * + * \parDescription
+ * Writes data to the transmit buffer in a control mode. \n\n + * When the respective control mode is enabled , this API can be used. + * + * + * \parRelated APIs:
+ * XMC_USIC_CH_WriteToTBUF() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_WriteToTBUFTCI(XMC_USIC_CH_t *const channel, + const uint16_t data, + const uint32_t transmit_control_information) +{ + channel->TBUF[transmit_control_information] = data; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param word_length Number of bits to be configured for a data word. \n + * \b Range: minimum= 1, maximum= 16. \n + * e.g: For word length of 8, \a word_length should be provided as 8. + * @return None + * + * \parDescription
+ * Sets the data word length in number of bits. \n\n + * Sets the number of bits to represent a data word. Frame length should be a multiple of word length. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetFrameLength()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length) +{ + channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_WLE_Msk)) | + (uint32_t)(((uint32_t)word_length - 1UL) << USIC_CH_SCTR_WLE_Pos); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param word_length Number of bits to be configured for a data word. \n + * \b Range: minimum= 1, maximum= 16. \n + * e.g: For word length of 8, \a word_length should be provided as 8. + * @return None + * + * \parDescription
+ * Sets the data word length in number of bits. \n\n + * Sets the number of bits to represent a data word. Frame length should be a multiple of word length. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetFrameLength()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetShiftDirection(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_SHIFT_DIRECTION_t shift_direction) +{ + channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_SDIR_Msk)) | (uint32_t)shift_direction; +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Captured counter value + * + * + * \parDescription
+ * The value of the counter is captured if one of the trigger signals DX0T or DX1T are activated by the corresponding input stage. + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_GetCaptureTimerValue(const XMC_USIC_CH_t *const channel) +{ + return channel->CMTR; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param mode divider mode ::XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t \n + * @param step divider \n + * \b XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL resulting divider = 1023 - step \n + * \b XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL resulting divider = 1023 / step \n + * + * @return None + * + * \parDescription
+ * The fractional divider generates its output frequency fFD by either dividing the input frequency fPERIPH by an integer factor n or by multiplication of n/1024. + * + */ +__STATIC_INLINE void XMC_USIC_CH_SetFractionalDivider(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t mode, const uint16_t step) +{ + channel->FDR = mode | step; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param frame_length Number of bits in a frame. \n + * \b Range: minimum= 1, maximum= 0x3f. The maximum value for fixed frame size is 0x3f. \n + * e.g: For a frame length of 16, \a frame_length should be provided as 16. + * @return None + * + * \parDescription
+ * Define the data frame length.\n\n + * Set the number of bits to be serially transmitted in a frame. + * The frame length should be multiples of word length. If the value is set to 0x40, the frame length + * has to be controlled explicitly. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetWordLength(), XMC_USIC_CH_EnableFrameLengthControl() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length) +{ + channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_FLE_Msk)) | + (((uint32_t)frame_length - 0x1U) << USIC_CH_SCTR_FLE_Pos); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Bit mask of the channel events to be enabled. Use @ref XMC_USIC_CH_EVENT_t for the bit masks. \n + * \b Range: @ref XMC_USIC_CH_EVENT_RECEIVE_START, @ref XMC_USIC_CH_EVENT_DATA_LOST etc. Multiple events + * can be combined using \a OR operation. + * @return None + * + * \parDescription
+ * Enable the channel interrupt events.\n\n + * Common channel events related to serial communication can be configured using this API. + * Multiple events can be combined using the bitwise OR operation and configured in one function call. + * XMC_USIC_CH_EVENT_t enumerates multiple protocol event bitmasks. These enumerations can be used as input to the API. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableEvent(), XMC_USIC_CH_SetInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR |= event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Bit mask of the channel events to be disabled. Use @ref XMC_USIC_CH_EVENT_t for the bit masks. \n + * \b Range: @ref XMC_USIC_CH_EVENT_RECEIVE_START, @ref XMC_USIC_CH_EVENT_DATA_LOST etc. Multiple events + * can be combined using \a OR operation. + * @return None + * + * \parDescription
+ * Disable the channel interrupt events. \n\n + * Multiple events can be combined using the bitwise OR operation and configured in one function call. + * XMC_USIC_CH_EVENT_t enumerates multiple protocol event bitmasks. These enumerations can be used as input to the API. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableEvent(), XMC_USIC_CH_SetInterruptNodePointer() \n\n\n +*/ +__STATIC_INLINE void XMC_USIC_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR &= (uint32_t)~event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param interrupt_node Interrupt node pointer to be configured. \n + * \b Range: @ref XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, + * @ref XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc. + * @param service_request Service request number.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for USIC channel events. \n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableEvent() \n\n\n + */ +void XMC_USIC_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Stataus @ref XMC_USIC_CH_TBUF_STATUS_IDLE if transmit buffer is free, + * @ref XMC_USIC_CH_TBUF_STATUS_BUSY if transmit buffer is busy. + * + * \parDescription
+ * Gets transmit buffer status. \n\n + * Status indicates whether the transmit buffer is free, or busy transmitting data. + * The status depends on the value of TDV flag in TCSR register. + * This status can be used while transmitting data. Transmit data when the transmit buffer + * status is @ref XMC_USIC_CH_TBUF_STATUS_IDLE. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetDataOutputMode() \n\n\n + */ +__STATIC_INLINE XMC_USIC_CH_TBUF_STATUS_t XMC_USIC_CH_GetTransmitBufferStatus(XMC_USIC_CH_t *const channel) +{ + return (XMC_USIC_CH_TBUF_STATUS_t)(channel->TCSR & USIC_CH_TCSR_TDV_Msk); +} + +/** + * @brief API to get receive buffer status + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status of data validity check for RBUF0 and RBUF1. \n + * Returned value should be masked with RDV0 and RDV1 bits to know the status. \n + * \b Range: @ref XMC_USIC_CH_RBUF_STATUS_DATA_VALID0, @ref XMC_USIC_CH_RBUF_STATUS_DATA_VALID1. + * + * \parDescription
+ * Checks if RBUF0 and RBUF1 have valid unread data. \n\n + * It checks the bits RDV0 and RDV1 of the RBUFSR register. + * Returns the value of RBUFSR masked with bitmasks of RDV0 and RDV1. + * It can be used to decide whether 2bytes has to be read from RBUF or 1 byte. + * If both bitmasks XMC_USIC_CH_RBUF_STATUS_DATA_VALID0 and XMC_USIC_CH_RBUF_STATUS_DATA_VALID1 + * are set, then 2 bytes can be read from RBUF. If only either of them is set, then only one byte + * can be read from RBUF. + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_GetReceiveBufferStatus(XMC_USIC_CH_t *const channel) +{ + return ((uint32_t) (channel->RBUFSR & (USIC_CH_RBUFSR_RDV0_Msk | USIC_CH_RBUFSR_RDV1_Msk))); +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param start_transmision_mode Transmission mode to be enabled. \n + * \b Range: @ref XMC_USIC_CH_START_TRANSMISION_DISABLED, + * @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV, @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0, + * @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1 + * + * @return None + * + * \parDescription
+ * Configures data transmission. \n\n + * The configuration affects the data shifted on the DOUT0 pin. + * + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetDataOutputMode() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetStartTransmisionMode(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_START_TRANSMISION_MODE_t start_transmision_mode) +{ + channel->TCSR = (uint32_t)(channel->TCSR & (~USIC_CH_TCSR_TDEN_Msk)) | (uint32_t)start_transmision_mode; +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data_output_mode Data output mode. \n + * \b Range: @ref XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL, @ref XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED + * @return None + * + * \parDescription
+ * Configures the mode for data output. \n\n + * USIC channel can be configured to shift inverted data or direct data based on the input to the API. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetStartTransmisionMode() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetDataOutputMode(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_DATA_OUTPUT_MODE_t data_output_mode) +{ + channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_DOCFG_Msk)) | (uint32_t)data_output_mode; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Enables automatic update of frame length. \n\n + * When the automatic update of frame length is enabled, frame length is configured based on the + * index of the TBUF[]/IN[] register array. When the data is written to TBUF[x], frame length is configured + * with the mask value of \a x at the last 5 bit positions. Same logic is applicable if data is written to + * IN[x] register. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_TXFIFO_PutDataFLEMode() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableFrameLengthControl(XMC_USIC_CH_t *const channel) +{ + channel->TCSR = (uint32_t)(channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk | + USIC_CH_TCSR_SELMD_Msk | + USIC_CH_TCSR_WAMD_Msk | + USIC_CH_TCSR_HPCMD_Msk))) | + (uint32_t)USIC_CH_TCSR_FLEMD_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Disables automatic update of frame length. \n\n + * When automatic update of frame length is disabled, frame length has to configured explicitly. + * Frame length remains fixed until it is changed again. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_SetFrameLength() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableFrameLengthControl(XMC_USIC_CH_t *const channel) +{ + channel->TCSR &= (uint32_t)~USIC_CH_TCSR_FLEMD_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Bit TCSR.TE is set if DX2T becomes active while TDV = 1. \n\n + * Enables the transfer trigger unit to set bit TCSR.TE if the trigger signal DX2T becomes active + * for event driven transfer starts. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableTBUFDataValidTrigger()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableTBUFDataValidTrigger(XMC_USIC_CH_t *const channel) +{ + channel->TCSR |= (uint32_t)USIC_CH_TCSR_TDVTR_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Disables the trigger of TDV depending on DX2T signal. \n\n + * Bit TCSR.TE is permanently set. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableTBUFDataValidTrigger() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableTBUFDataValidTrigger(XMC_USIC_CH_t *const channel) +{ + channel->TCSR &= (uint32_t)~USIC_CH_TCSR_TDVTR_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param service_request_line service request number of the event to be triggered. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Trigger a USIC interrupt service request.\n\n + * When the USIC service request is triggered, the NVIC interrupt associated with it will be + * generated if enabled. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line) +{ + channel->FMR = (uint32_t)(USIC_CH_FMR_SIO0_Msk << service_request_line); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param transmit_buffer_status clearing or setting the TDV flag. \n + * + * @return None + * + * \parDescription
+ * Modify TCSR.TDV and TCSR.TE to control the start of a data word transmission by software. + * + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetTransmitBufferStatus(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_TBUF_STATUS_SET_t transmit_buffer_status) +{ + channel->FMR = (uint32_t)transmit_buffer_status; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param passive_level Value of passive level for the channel. \n + * \b Range: @ref XMC_USIC_CH_PASSIVE_DATA_LEVEL0, @ref XMC_USIC_CH_PASSIVE_DATA_LEVEL1 + * @return None + * + * \parDescription
+ * Set the passive data level of the output signal. \n\n + * When the USIC channel transmit stage is idle, the output signal level stays at the + * configured passive level. + * + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetStartTransmisionMode() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetPassiveDataLevel(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_PASSIVE_DATA_LEVEL_t passive_level) +{ + channel->SCTR &= (~USIC_CH_SCTR_PDL_Msk); + channel->SCTR |= (uint32_t)passive_level; +} + +/* TX FIFO APIs */ +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data_pointer Start position inside the FIFO buffer. \n + * \b Range: 0 to 63. + * @param size Required size of the transmit FIFO. \n + * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS + * @param limit Threshold of transmit FIFO filling level to be considered for generating events. \n + * \b Range: 0 to \a size -1. + * @return None + * + * \parDescription
+ * Initializes the transmit FIFO. \n\n + * Transmit FIFO is a subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module. + * Each channel can share the FIFO for transmission and reception. \a data_pointer represents the start index in the common FIFO, + * from where transmit data can be put, for the selected USIC channel. \a size represents the size of transmit FIFO as a multiple of + * 2. Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully selected. A FIFO standard transmit buffer + * event is generated when the FIFO filling level falls below the \a limit value. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_EnableEvent(), XMC_USIC_CH_TXFIFO_SetInterruptNodePointer() \n\n\n + */ +void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel, + const uint32_t data_pointer, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param size Required size of the transmit FIFO. \n + * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS + * @param limit Threshold for transmit FIFO filling level to be considered for generating events. \n + * \b Range: 0 to \a size -1. + * @return None + * + * \parDescription
+ * Sets the size and trigger limit for the transmit FIFO. \n\n + * The API is not to be called for initializing the transmit FIFO. The API shall be used for the + * runtime change of transmit FIFO trigger limit. FIFO start position will not be affected on execution. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit() \n\n\n + */ +void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit); + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Events to be enabled. Multiple events can be bitwise OR combined. @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t \n + * @return None + * + * \parDescription
+ * Enables the interrupt events related to transmit FIFO. \n\n + * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t. + * Multiple events can be enabled by providing multiple events in a single call. For providing + * multiple events, combine the events using bitwise OR operation. Events are configured in the TBCTR register.
+ * + * Note: API only enables the events. For interrupt generation, interrupt node must be configured and NVIC node + * must be enabled. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_SetInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->TBCTR |= event; +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Events to be disabled. @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t \n + * @return None + * + * \parDescription
+ * Disables the interrupt events related to transmit FIFO. \n\n + * By disabling the interrupt events, generation of interrupt is stopped. User can poll the event + * flags from the status register using the API XMC_USIC_CH_TXFIFO_GetEvent(). + * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t. For providing + * multiple events, combine the events using bitwise OR operation. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_GetEvent(), XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->TBCTR &= (uint32_t)~event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param interrupt_node Node pointer representing the transmit FIFO events. \n + * \b Range: @ref XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD, + * @ref XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE + * @param service_request The service request to be used for interrupt generation. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets an interrupt node for the transmit FIFO events.\n\n + * A node pointer represents one or more interrupt events. Service request represents the interrupt node to be used + * among the 6 interrupt nodes available for USIC module. + * API configures the service request to be used for interrupt generation for the events selected. + * A transmit FIFO event can generate an interrupt only if the interrupt node is configured for the event and + * the interrupt generation is enabled for the event. For example, transmit FIFO standard transmit buffer + * interrupt is generated if the interrupt node for the same is set and interrupt is enabled.
+ * + * Note: NVIC node should be explicitly enabled for the interrupt generation. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n + */ +void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data Data to be transmitted. \n + * \b Range: 16bit unsigned data. minimum= 0, maximum= 65535 + * @return None + * + * \parDescription
+ * Writes data into the transmit FIFO. \n\n + * The data provided is placed in the transmit FIFO. + * The transmit FIFO should be configured before calling this API. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutData(XMC_USIC_CH_t *const channel, const uint16_t data) +{ + channel->IN[0] = data; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data Data to be transmitted. + * @param frame_length Frame length to be configured while transmitting the data. \n + * \b Range: minimum= 0, maximum= 31. e.g: For a frame length of 16, set \a frame_length as 15. + * @return None + * + * \parDescription
+ * Writes data to the transmit FIFO in frame length control mode. \n\n + * When frame length control is enabled for dynamic update of frame length, this API can be used. + * \a frame_length represents the frame length to be updated by the peripheral. + * \a frame_length is used as index for the IN[] register array. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableFrameLengthControl() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_USIC_CH_t *const channel, + const uint16_t data, + const uint32_t frame_length) +{ + channel->IN[frame_length] = data; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data Data to be transmitted. + * @param frame_length Frame length to be configured while transmitting the data. \n + * \b Range: minimum= 0, maximum= 31. e.g: For a frame length of 16, set \a frame_length as 15. + * @return None + * + * \parDescription
+ * Writes data to the transmit FIFO in hardware port control mode. \n\n + * When hardware port control is enabled for dynamic update of frame length, this API can be used. + * \a frame_length represents the frame length to be updated by the peripheral. + * \a frame_length is used as index for the IN[] register array. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableFrameLengthControl() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataHPCMode(XMC_USIC_CH_t *const channel, + const uint16_t data, + const uint32_t frame_length) +{ + channel->IN[frame_length] = data; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Clears the contents of transmit FIFO. \n\n + * Transmit FIFO contents will be cleared and the filling level will be reset to 0. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_GetLevel() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_Flush(XMC_USIC_CH_t *const channel) +{ + channel->TRBSCR = (uint32_t)USIC_CH_TRBSCR_FLUSHTB_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status \a true if transmit FIFO is full + * \a false if transmit FIFO is not full. + * + * \parDescription
+ * Checks if transmit FIFO is full. \n\n + * When the transmit FIFO filling level reaches the configured size, FIFO full flag is set. + * User should not write to the FIFO when the transmit FIFO is full. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_IsEmpty(), XMC_USIC_CH_TXFIFO_Flush() \n\n\n + */ +__STATIC_INLINE bool XMC_USIC_CH_TXFIFO_IsFull(XMC_USIC_CH_t *const channel) +{ + return (bool)(channel->TRBSR & USIC_CH_TRBSR_TFULL_Msk); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status \a true if transmit FIFO is empty + * \a false if transmit FIFO has some data. + * + * \parDescription
+ * Checks if transmit FIFO is empty. \n\n + * When the transmit FIFO is empty, data can be written to FIFO. + * When the last written word to the transmit FIFO is transmitted out of the FIFO, + * FIFO empty flag is set. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData() \n\n\n + */ +__STATIC_INLINE bool XMC_USIC_CH_TXFIFO_IsEmpty(XMC_USIC_CH_t *const channel) +{ + return (bool)(channel->TRBSR & USIC_CH_TRBSR_TEMPTY_Msk); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Transmit FIFO filling level. \n + * \b Range: minimum= 0(FIFO empty), maximum= transmit FIFO size. + * + * \parDescription
+ * Gets the transmit FIFO filling level. \n\n + * For every word written to the FIFO, filling level is updated. The API gives the value + * of this filling level. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetLevel(XMC_USIC_CH_t *const channel) +{ + return ((uint32_t)(channel->TRBSR & USIC_CH_TRBSR_TBFLVL_Msk) >> USIC_CH_TRBSR_TBFLVL_Pos); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status of standard transmit and transmit buffer error events. @ref XMC_USIC_CH_TXFIFO_EVENT_t \n + * + * \parDescription
+ * Gets the transmit FIFO event status. \n\n + * Gives the status of transmit FIFO standard transmit buffer event and transmit buffer error event. + * The status bits are located at their bit positions in the TRBSR register in the returned value. + * User can make use of the @ref XMC_USIC_CH_TXFIFO_EVENT_t enumeration for checking the status of return value. + * The status can be found by using the bitwise AND operation on the returned value with the enumerated value.
+ * + * Note: Event status flags should be cleared by the user explicitly. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_ClearEvent() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetEvent(XMC_USIC_CH_t *const channel) +{ + return (uint32_t)((channel->TRBSR) & (USIC_CH_TRBSR_STBI_Msk | + USIC_CH_TRBSR_TBERI_Msk)); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Transmit FIFO events to be cleared. \n + * \b Range: @ref XMC_USIC_CH_TXFIFO_EVENT_STANDARD, @ref XMC_USIC_CH_TXFIFO_EVENT_ERROR. + * @return None + * + * \parDescription
+ * Clears the transmit FIFO event flags in the status register. \n\n + * USIC channel peripheral does not clear the event flags after they are read. + * This API clears the events provided in the \a mask value. + * XMC_USIC_CH_TXFIFO_EVENT enumeration can be used as input. Multiple events + * can be cleared by providing a mask value obtained by bitwise OR operation of + * multiple event enumerations. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_GetEvent() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_ClearEvent(XMC_USIC_CH_t *const channel, + const uint32_t event) +{ + channel->TRBSCR = event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data_pointer Start position inside the FIFO buffer. \n + * \b Range: 0 to 63. + * @param size Required size of the receive FIFO. \n + * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS + * @param limit Threshold of receive FIFO filling level to be considered for generating events. \n + * \b Range: 0 to \a size -1. + * @return None + * + * \parDescription
+ * Configures the receive FIFO. \n\n + * Receive FIFO is the subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module. + * Each channel can share the FIFO for transmission and reception. \a data_pointer represents the start index in the common FIFO, + * from where received data can be put. \a size represents the size of receive FIFO as a multiple of 2. + * Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully selected. A FIFO standard receive buffer + * event or alternative receive buffer event is generated when the FIFO filling level exceeds the \a limit value. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_EnableEvent(), XMC_USIC_CH_RXFIFO_SetInterruptNodePointer() \n\n\n +*/ +void XMC_USIC_CH_RXFIFO_Configure(XMC_USIC_CH_t *const channel, + const uint32_t data_pointer, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param size Required size of the receive FIFO. \n + * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS + * @param limit Threshold for receive FIFO filling level to be considered for generating events. \n + * \b Range: 0 to \a size -1. + * @return None + * + * \parDescription
+ * Sets the size and trigger limit for the receive FIFO. \n\n + * The API is not to be called for initializing the receive FIFO. The API shall be used for the + * runtime change of receive FIFO trigger limit. FIFO start position will not be affected on execution. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit()\ n\n\n + */ +void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Events to be enabled. Multiple events can be bitwise OR combined. @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_t\n + * @return None + * + * \parDescription
+ * Enables the interrupt events related to transmit FIFO. \n\n + * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_t. + * Multiple events can be enabled by providing multiple events in a single call. For providing + * multiple events, combine the events using bitwise OR operation.
+ * + * Note: API only enables the events. For interrupt generation, interrupt node must be configured and NVIC node + * must be enabled. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_SetInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_RXFIFO_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->RBCTR |= event; +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Events to be disabled. \n + * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD, @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR, + * @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE. + * @return None + * + * \parDescription
+ * Disables the selected interrupt events related to receive FIFO. \n\n + * By disabling the interrupt events, generation of interrupt is stopped. User can poll the event + * flags from the status register using the API XMC_USIC_CH_RXFIFO_GetEvent(). + * Event bitmasks can be constructed using the enumeration \a XMC_USIC_CH_RXFIFO_EVENT_CONF. For providing + * multiple events, combine the events using bitwise OR operation. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_GetEvent(), XMC_USIC_CH_RXFIFO_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_RXFIFO_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->RBCTR &= (uint32_t)~event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param interrupt_node Node pointer representing the receive FIFO events. \n + * \b Range: @ref XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD, + * @ref XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE + * @param service_request The service request to be used for interrupt generation.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets an interrupt node for the receive FIFO events. \n\n + * A node pointer represents one or more interrupt events. Service request represents the interrupt node to be used + * among the 6 interrupt nodes available for USIC module. + * API configures the service request to be used for interrupt generation for the events selected. + * A receive FIFO event can generate an interrupt only if the interrupt node is configured for the event and + * the interrupt generation is enabled for the event. For example, transmit FIFO standard transmit buffer + * interrupt is generated if the interrupt node for the same is set and interrupt is enabled.
+ * + * Note: NVIC node should be explicitly enabled for the interrupt generation. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_EnableEvent() \n\n\n + */ +void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Value read from the receive FIFO. \n + * \b Range: 16bit data. Length of data depends on the word length configuration. + * + * \parDescription
+ * Gets data from the receive FIFO. \n\n + * Receive FIFO should be read only if data is availble in the FIFO. This can be checked using + * the API XMC_USIC_CH_RXFIFO_IsEmpty(). Receive FIFO error flag will be set if an attempt is made + * to read from an empty receive FIFO. To read all the received data, user should keep reading data + * until receive FIFO is empty. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_ClearEvent() \n\n\n + */ +__STATIC_INLINE uint16_t XMC_USIC_CH_RXFIFO_GetData(XMC_USIC_CH_t *const channel) +{ + return (uint16_t)(channel->OUTR); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Clears the contents of receive FIFO. \n\n + * Receive FIFO contents will be cleared and the filling level will be reset to 0. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_GetLevel() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_RXFIFO_Flush(XMC_USIC_CH_t *const channel) +{ + channel->TRBSCR = (uint32_t)USIC_CH_TRBSCR_FLUSHRB_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status \a true if receive FIFO is full + * \a false if receive FIFO is not full. + * + * \parDescription
+ * Checks if receive FIFO is full. \n\n + * When the receive FIFO filling level reaches the configured size, FIFO full flag is set. + * Any data received when the receive FIFO is full, is lost. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_IsEmpty(), XMC_USIC_CH_RXFIFO_Flush() \n\n\n + */ +__STATIC_INLINE bool XMC_USIC_CH_RXFIFO_IsFull(XMC_USIC_CH_t *const channel) +{ + return (bool)(channel->TRBSR & USIC_CH_TRBSR_RFULL_Msk); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status \a true if receive FIFO is empty, + * \a false if receive FIFO has some data. + * + * \parDescription
+ * Checks if receive FIFO is empty. \n\n + * When the receive FIFO is empty, received data will be put in receive FIFO. + * When the last received word in the FIFO is read, FIFO empty flag is set. Any attempt + * to read from an empty receive FIFO will set the receive FIFO error flag. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData() \n\n\n + */ +__STATIC_INLINE bool XMC_USIC_CH_RXFIFO_IsEmpty(XMC_USIC_CH_t *const channel) +{ + return (bool)(channel->TRBSR & USIC_CH_TRBSR_REMPTY_Msk); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return uint32_t Receive FIFO filling level. \n + * \b Range: minimum= 0(FIFO empty), maximum= receive FIFO size. + * + * \parDescription
+ * Gets the receive FIFO filling level. \n\n + * For every word received, the filling level is incremented. The API gives the value + * of this filling level. The filling level is decremented when the data is read out of the + * receive FIFO. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetLevel(XMC_USIC_CH_t *const channel) +{ + return ((uint32_t)(channel->TRBSR & USIC_CH_TRBSR_RBFLVL_Msk) >> USIC_CH_TRBSR_RBFLVL_Pos); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status of standard receive buffer, alternative receive buffer and receive buffer error events. \n + * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_STANDARD, @ref XMC_USIC_CH_RXFIFO_EVENT_ERROR, + * @ref XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE. + * + * \parDescription
+ * Gets the receive FIFO events' status. \n\n + * Gives the status of receive FIFO standard receive buffer event, alternative receive buffer event and receive buffer error event. + * The status bits are located at their bitpositions in the TRBSR register in the returned value. + * User can make use of the XMC_USIC_CH_RXFIFO_EVENT enumeration for checking the status of return value. + * The status can be found by using the bitwise AND operation on the returned value with the enumerated value.
+ * + * Note: Event status flags should be cleared by the user explicitly. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_ClearEvent()\n\n\n + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetEvent(XMC_USIC_CH_t *const channel) +{ + return (uint32_t)((channel->TRBSR) & (USIC_CH_TRBSR_SRBI_Msk | + USIC_CH_TRBSR_RBERI_Msk | + USIC_CH_TRBSR_ARBI_Msk)); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Receive FIFO events to be cleared. \n + * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_STANDARD, @ref XMC_USIC_CH_RXFIFO_EVENT_ERROR, + * @ref XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE. + * @return None + * + * \parDescription
+ * Clears the receive FIFO event flags in the status register. \n\n + * USIC channel peripheral does not clear the event flags after they are read. + * This API clears the events provided in the \a mask value. + * XMC_USIC_CH_RXFIFO_EVENT enumeration can be used as input. Multiple events + * can be cleared by providing a mask value obtained by bitwise OR operation of + * multiple event enumerations. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_GetEvent() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_RXFIFO_ClearEvent(XMC_USIC_CH_t *const channel, + const uint32_t event) +{ + channel->TRBSCR = event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Enables time measurement using the capture mode timer. \n\n + * Time measurement is enabled by setting the timer enable flag in BRG register. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableTimeMeasurement() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableTimeMeasurement(XMC_USIC_CH_t *const channel) +{ + channel->BRG |= (uint32_t)USIC_CH_BRG_TMEN_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Disables time measurement using the capture mode timer. \n\n + * Time measurement is disabled by clearing the timer enable flag in BRG register. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableTimeMeasurement() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableTimeMeasurement(XMC_USIC_CH_t *const channel) +{ + channel->BRG &= (uint32_t)~USIC_CH_BRG_TMEN_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param passive_level Passive level for the master clock output. \n + * \b Range: @ref XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0, @ref XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1. + * @return None + * + * \parDescription
+ * Sets the idle mode pin level for the master clock output. \n + */ +__STATIC_INLINE void XMC_USIC_CH_SetMclkOutputPassiveLevel(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t passive_level) +{ + channel->BRG = (uint32_t)(channel->BRG & (~USIC_CH_BRG_MCLKCFG_Msk)) | (uint32_t)passive_level; +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param passive_level Passive level for the clock output. \n + * \b Range: @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED, + * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED, + * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED, + * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED, + * @param clock_output Shift clock source selection. \n + * \b Range: Use @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK, + * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 + * @return None + * + * \parDescription
+ * Sets the idle mode shift clock output level and selects the shift clock source. \n\n + * Shift clock idle mode output level can be set to logic high or low. Shift clock output can be configured to have a + * delay of half shift clock period. Both the configurations are available as enumeration values defined with type + * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t. + * This value should be configured based on the slave device requirement. + * Shift clock source can be selected between internal clock(master) and external input(slave). + * + */ +__STATIC_INLINE void XMC_USIC_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level, + const XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) +{ + channel->BRG = (uint32_t)(channel->BRG & (~(USIC_CH_BRG_SCLKCFG_Msk | + USIC_CH_BRG_SCLKOSEL_Msk))) | + (uint32_t)passive_level | + (uint32_t)clock_output; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param mode USIC channel operation mode. \n + * \b Range: @ref XMC_USIC_CH_OPERATING_MODE_IDLE, @ref XMC_USIC_CH_OPERATING_MODE_SPI, + * @ref XMC_USIC_CH_OPERATING_MODE_UART, @ref XMC_USIC_CH_OPERATING_MODE_I2S, + * @ref XMC_USIC_CH_OPERATING_MODE_I2C. + * @return None + * + * \parDescription
+ * Sets the USIC channel operation mode.\n\n + * A USIC channel can support multiple serial communication protocols like UART, SPI, I2C and I2S. + * The API sets the input operation mode to the USIC channel. + * + * \parRelated APIs:
+ * XMC_USIC_Enable(), XMC_USIC_CH_Enable() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetMode(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_OPERATING_MODE_t mode) +{ + channel->CCR = (uint32_t)(channel->CCR & (~(USIC_CH_CCR_MODE_Msk))) | (uint32_t)mode; +} +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_vadc.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_vadc.h new file mode 100644 index 00000000..dc963068 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_vadc.h @@ -0,0 +1,4962 @@ +/** + * @file xmc_vadc.h + * @date 2017-02-06 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-15: + * - Initial
+ * + * 2015-02-20: + * - Revised for XMC1201 device.
+ * + * 2015-04-27: + * - Added new APIs for SHS.
+ * - Added New APIs for trigger edge selection.
+ * - Added new APIs for Queue flush entries, boundary selection, Boundary node pointer.
+ * - Revised GatingMode APIs and EMUX Control Init API.
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * 2015-06-25: + * - BFL configuration in channel initialization fixed. + * + * 2015-07-28: + * - CLOCK_GATING_SUPPORTED and PERIPHERAL_RESET_SUPPORTED macros used + * - Clubbed the macro definitions for XMC13 XMC12 and XMC14 + * - Clubbed the macro definitions for XMC44 XMC47 and XMC48 + * - New APIs Created. + * - XMC_VADC_GLOBAL_SetIndividualBoundary + * - XMC_VADC_GROUP_SetIndividualBoundary + * - XMC_VADC_GROUP_GetAlias + * - XMC_VADC_GROUP_GetInputClass + * - XMC_VADC_GROUP_ChannelSetIclass + * - XMC_VADC_GROUP_ChannelGetResultAlignment + * - XMC_VADC_GROUP_ChannelGetInputClass + * - XMC_VADC_GROUP_SetResultSubtractionValue + * + * 2015-12-01: + * - Added: + * - XMC4300 device supported + * + * - Fixed: + * - XMC_VADC_GLOBAL_TriggerEvent API updated. OR operation removed. + * - XMC_VADC_GLOBAL_ClearEvent API updated. Multiple events triggering on clearing the event is fixed. + * - Wrong MACRO name defined in xmc_vadc_map.h file corrected for XMC4200/4100 devices. + * XMC_VADC_G3_SAMPLE renamed to XMC_VADC_G1_SAMPLE + * + * 2015-12-01: + * - New APIs Created. + * - XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled + * - XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled + * - Fixed the analog calibration voltage for XMC1100 to external reference upper supply range. + * - Fixed the XMC_VADC_GLOBAL_StartupCalibration() for XMC1100. + * + * 2016-03-09: + * - Optimization of write only registers + * + * 2016-03-18: + * - Fixed XMC_VADC_GLOBAL_SHS_IsConverterReady(): API checks the STEPCFG register for the ready bit instead of + * SHSCFG SFR. + * + * 2016-06-17: + * - New macros added XMC_VADC_SHS_FULL_SET_REG, XMC_VADC_RESULT_PRIORITY_AVAILABLE + * - New Enum added XMC_VADC_SHS_GAIN_LEVEL_t and XMC_VADC_SYNCTR_EVAL_t + * - New APIs added are: + * - XMC_VADC_GROUP_SetSyncSlaveReadySignal + * - XMC_VADC_GROUP_ChannelGetAssertedEvents + * - XMC_VADC_GROUP_GetAssertedResultEvents + * - XMC_VADC_GROUP_SetResultRegPriority + * - XMC_VADC_GROUP_SetSyncReadySignal + * - XMC_VADC_GROUP_GetSyncReadySignal + * - XMC_VADC_GROUP_GetResultRegPriority + * + * 2017-02-06: + * - Added new functions to remove channels from background request source, XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence() and XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels() + * + * @endcond + * + */ + +#ifndef XMC_VADC_H +#define XMC_VADC_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include +#include +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup VADC + * @brief Versatile Analog to Digital Converter (VADC) driver for XMC microcontroller family. + * + * The XMC microcontroller provides a series of analog input channels connected to a cluster of Analog/Digital + * Converters using the Successive Approximation Register (SAR) principle to convert analog input values (voltages) + * to discrete digital values. + * \if XMC1 + * The XMC1x is based on Sample & Hold converters, where a cluster contains 2 Sample&Hold units which share a common + * converter. + * \endif + * + * Each converter of the ADC cluster can operate independent of the others, controlled by a dedicated set of + * registers and triggered by a dedicated group request source. The results of each channel can be stored in a + * dedicated channel-specific result register or in a group-specific result register.
+ * + * The Versatile Analog to Digital Converter module (VADC) of the XMC comprises a set of converter blocks that + * can be operated either independently or via a common request source that emulates a background converter. + * Each converter block is equipped with a dedicated input multiplexer and dedicated request sources, + * which together build separate groups. + * + * \if XMC4 + * @image html "vadc_overview_xmc4x.png" + * \else + * @image html "vadc_overview_xmc1x.png" + * \endif + * + * The VADC LLD is split into GLOBAL and GROUP related APIs.
+ * GLOBAL:
+ *
    + *
  • Global APIs act on the entire ADC module. Configures global configuration registers
    • + *
  • Allows configuration of the background request source of the VADC.
    • + *
  • The clock related configurations for the VADC module are configured in the Global APIs/
    • + *
  • The Global API names are prefixed by the \b XMC_VADC_GLOBAL_ and they accept ::XMC_VADC_GLOBAL_t as + * one of its arguments.
    • + *
  • Configures the background request source of the VADC. The APIs which act on the background related registers + * are prefixed by \b XMC_VADC_GLOBAL_Background
    • + *
  • Configures the sample and hold unit of the VADC. The APIs which act on the SHS related registers + * are prefixed by \b XMC_VADC_GLOBAL_SHS_
    • + *

+ * + * GROUP:
+ *
    + *
  • Group APIs act on a VADC group. Configures the group configuration registers
    • + *
  • Configures the queue request source of the VADC. The APIs which act on the queue related registers + * are prefixed by \b XMC_VADC_GROUP_Queue
    • + *
  • Configures the scan request source of the VADC. The APIs which act on the scan related registers + * are prefixed by \b XMC_VADC_GROUP_Scan
    • + *
  • Configuration of the channels of each group are done by the API which have a prefix as + * \b XMC_VADC_GROUP_Channel.
    • + *
  • The Group API names are prefixed by the \b XMC_VADC_GROUP_ and they accept ::XMC_VADC_GROUP_t as + * one of its arguments.
    • + *

+ * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#if ((UC_SERIES == XMC42)||(UC_SERIES == XMC41) || (UC_SERIES == XMC43)) +#define XMC_VADC_GROUP_AVAILABLE (1U) /* Defines the availability of group resource in a device*/ +#define XMC_VADC_GSCAN_AVAILABLE (1U) /* Defines the availability of scan request resource in a device*/ +#define XMC_VADC_QUEUE_AVAILABLE (1U) /* Defines the availability of queue request resource in a device*/ +#define XMC_VADC_EMUX_AVAILABLE (1U) /* Defines the availability of external multiplexer support in a + device*/ +#define XMC_VADC_BOUNDARY_AVAILABLE (1U) /* Defines the availability of boundary check support in a device*/ +#define XMC_VADC_MULTIPLE_SLAVEGROUPS (1U) /* Defines the availability of synchronous request source in device*/ +#define XMC_VADC_MAXIMUM_NUM_GROUPS (2U) /* Defines the maximum number of groups available in a device*/ +#define XMC_VADC_BOUNDARY_FLAG_SELECT (1U) /* Defines the availability of boundary flags in a device*/ +#define XMC_VADC_EMUX_CH_SEL_STYLE (1U) /* Defines the external multiplexer channel selection mode of + operation for a particular device*/ +#define XMC_VADC_SHS_AVAILABLE (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_SHS_FULL_SET_REG (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_GROUP_SRCREG_AVAILABLE (1U) /* Define the availability of a source specific result register */ +#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */ +#endif + +#if (UC_SERIES == XMC44 || UC_SERIES == XMC47 || UC_SERIES == XMC48) +#define XMC_VADC_GROUP_AVAILABLE (1U) /* Defines the availability of group resource in a device*/ +#define XMC_VADC_GSCAN_AVAILABLE (1U) /* Defines the availability of scan request resource in a device*/ +#define XMC_VADC_QUEUE_AVAILABLE (1U) /* Defines the availability of queue request resource in a device*/ +#define XMC_VADC_EMUX_AVAILABLE (1U) /* Defines the availability of external multiplexer support in a + device*/ +#define XMC_VADC_BOUNDARY_AVAILABLE (1U) /* Defines the availability of boundary check support in a device*/ +#define XMC_VADC_MULTIPLE_SLAVEGROUPS (1U) /* Defines the availability of synchronous request source in device*/ +#define XMC_VADC_MAXIMUM_NUM_GROUPS (4U) /* Defines the maximum number of groups available in a device*/ +#define XMC_VADC_BOUNDARY_FLAG_SELECT (1U) /* Defines the availability of boundary flags in a device*/ +#define XMC_VADC_EMUX_CH_SEL_STYLE (1U) /* Defines the external multiplexer channel selection mode of + operation for a particular device*/ +#define XMC_VADC_SHS_AVAILABLE (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_SHS_FULL_SET_REG (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_GROUP_SRCREG_AVAILABLE (1U) /* Define the availability of a source specific result register */ +#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */ +#endif + +#if (UC_SERIES == XMC45) +#define XMC_VADC_GROUP_AVAILABLE (1U) /* Defines the availability of group resource in a device*/ +#define XMC_VADC_GSCAN_AVAILABLE (1U) /* Defines the availability of scan request resource in a device*/ +#define XMC_VADC_QUEUE_AVAILABLE (1U) /* Defines the availability of queue request resource in a device*/ +#define XMC_VADC_EMUX_AVAILABLE (1U) /* Defines the availability of external multiplexer support in a + device*/ +#define XMC_VADC_BOUNDARY_AVAILABLE (1U) /* Defines the availability of boundary check support in a device*/ +#define XMC_VADC_MULTIPLE_SLAVEGROUPS (1U) /* Defines the availability of synchronous request source in device*/ +#define XMC_VADC_MAXIMUM_NUM_GROUPS (4U) /* Defines the maximum number of groups available in a device*/ +#define XMC_VADC_BOUNDARY_FLAG_SELECT (0U) /* Defines the availability of boundary flags in a device*/ +#define XMC_VADC_EMUX_CH_SEL_STYLE (0U) /* Defines the external multiplexer channel selection mode of + operation for a particular device*/ +#define XMC_VADC_SHS_AVAILABLE (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_SHS_FULL_SET_REG (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_GROUP_SRCREG_AVAILABLE (0U) /* Define the availability of a source specific result register */ +#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */ +#endif + +#if (UC_SERIES == XMC14 || UC_SERIES == XMC13 || UC_SERIES == XMC12) +#define XMC_VADC_GROUP_AVAILABLE (1U) /* Defines the availability of group resource in a device*/ +#define XMC_VADC_GSCAN_AVAILABLE (1U) /* Defines the availability of scan request resource in a device*/ +#define XMC_VADC_QUEUE_AVAILABLE (1U) /* Defines the availability of queue request resource in a device*/ +#define XMC_VADC_EMUX_AVAILABLE (1U) /* Defines the availability of external multiplexer support in a + device*/ +#define XMC_VADC_BOUNDARY_AVAILABLE (1U) /* Defines the availability of boundary check support in a device*/ +#define XMC_VADC_MULTIPLE_SLAVEGROUPS (1U) /* Defines the availability of synchronous request source in device*/ +#define XMC_VADC_MAXIMUM_NUM_GROUPS (2U) /* Defines the maximum number of groups available in a device*/ +#define XMC_VADC_BOUNDARY_FLAG_SELECT (1U) /* Defines the availability of boundary flags in a device*/ +#define XMC_VADC_EMUX_CH_SEL_STYLE (1U) /* Defines the external multiplexer channel selection mode of + operation for a particular device*/ +#define XMC_VADC_SHS_AVAILABLE (1U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_SHS_FULL_SET_REG (1U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_GROUP_SRCREG_AVAILABLE (1U) /* Define the availability of a source specific result register */ +#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (1U) /* Define the availability of a priority for result register */ +#endif + +#if (UC_SERIES == XMC11) +#define XMC_VADC_GROUP_AVAILABLE (0U) /* Defines the availability of group resource in a device*/ +#define XMC_VADC_GSCAN_AVAILABLE (0U) /* Defines the availability of scan request resource in a device*/ +#define XMC_VADC_QUEUE_AVAILABLE (0U) /* Defines the availability of queue request resource in a device*/ +#define XMC_VADC_EMUX_AVAILABLE (0U) /* Defines the availability of external multiplexer support in a + device*/ +#define XMC_VADC_BOUNDARY_AVAILABLE (0U) /* Defines the availability of boundary check support in a device*/ +#define XMC_VADC_MULTIPLE_SLAVEGROUPS (0U) /* Defines the availability of synchronous request source in device*/ +#define XMC_VADC_MAXIMUM_NUM_GROUPS (2U) /* Defines the maximum number of groups available in a device*/ +#define XMC_VADC_BOUNDARY_FLAG_SELECT (0U) /* Defines the availability of boundary flags in a device*/ +#define XMC_VADC_SHS_START_UP_CAL_ACTIVE (3U) /* Defines the need for SHS startup calibration activation for + XMC1100 devices */ +#define XMC_VADC_CONV_ENABLE_FOR_XMC11 (*(uint32_t*) 0x40010500UL) /* Defines the additional errata setting for + XMC1100 device for effective working*/ +#define XMC_VADC_EMUX_CH_SEL_STYLE (0U) /* Defines the external multiplexer channel selection mode of + operation for a particular device*/ +#define XMC_VADC_SHS_AVAILABLE (1U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_SHS_FULL_SET_REG (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_GROUP_SRCREG_AVAILABLE (0U) /* Define the availability of a source specific result register */ +#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */ +#endif + +#define XMC_VADC_NUM_PORTS (16U) /* Defines the number of hardware ports that can be configured + as triggers and gating signals */ + +#define XMC_VADC_NUM_RESULT_REGISTERS (16U) /* Defines the number of result holding registers per ADC group */ + +#define XMC_VADC_NUM_CHANNELS_PER_GROUP (8U) /**< Defines the number of ADC channels per group */ + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +typedef uint16_t XMC_VADC_RESULT_SIZE_t; /**< Type defined the converted result size to unsigned 16 bit integer */ +typedef VADC_GLOBAL_TypeDef XMC_VADC_GLOBAL_t; /**< Type defined the device header file vadc global register structure + type to VADC type*/ + +#if(XMC_VADC_GROUP_AVAILABLE == 1U) +typedef VADC_G_TypeDef XMC_VADC_GROUP_t; /**< Type defined the device header file vadc group register structure + type to VADC Group type*/ +#endif + +#if(XMC_VADC_SHS_AVAILABLE == 1U) +typedef SHS_Type XMC_VADC_GLOBAL_SHS_t; /**< Type defined the sample and hold register structure*/ +#endif +/** + * Defines the return status after execution of VADC specific API's. Use @ref XMC_VADC_STATUS_t for this enumeration. + */ +typedef enum XMC_VADC_STATUS +{ + XMC_VADC_STATUS_SUCCESS = 0, /**< Returned when the API has been able to fulfill the callers request */ + XMC_VADC_STATUS_ERROR /**< Returned when the API cannot fulfill the request */ +} XMC_VADC_STATUS_t; + +/** + * Defines the various service requests lines. Each group can raise up to 4 service requests independently. While + * all groups together have the possibility of raising 4 module wide service requests. Use @ref XMC_VADC_SR_t for this + * enumeration. + */ +typedef enum XMC_VADC_SR +{ + XMC_VADC_SR_GROUP_SR0 = 0, /**< Group specific Service Request-0 */ + XMC_VADC_SR_GROUP_SR1, /**< Group specific Service Request-1 */ + XMC_VADC_SR_GROUP_SR2, /**< Group specific Service Request-2 */ + XMC_VADC_SR_GROUP_SR3, /**< Group specific Service Request-3 */ + XMC_VADC_SR_SHARED_SR0, /**< Module Wide Common Service Request-0 */ + XMC_VADC_SR_SHARED_SR1, /**< Module Wide Common Service Request-1 */ + XMC_VADC_SR_SHARED_SR2, /**< Module Wide Common Service Request-2 */ + XMC_VADC_SR_SHARED_SR3 /**< Module Wide Common Service Request-3 */ +} XMC_VADC_SR_t; + +/** + * Defines the mode of operation of a channel, when an ongoing conversion gets interrupted in between. + * Use @ref XMC_VADC_STARTMODE_t for this enumeration. + */ +typedef enum XMC_VADC_STARTMODE +{ + XMC_VADC_STARTMODE_WFS = 0, /**< An ongoing conversion completes without interruption */ + XMC_VADC_STARTMODE_CIR, /**< An ongoing conversion can be interrupted and resumed later*/ + XMC_VADC_STARTMODE_CNR /**< An ongoing conversion can be interrupted and never resumed */ +} XMC_VADC_STARTMODE_t; + +/** + * Defines the edge sensitivity of the trigger signal which can assert a conversion. + * Use @ref XMC_VADC_TRIGGER_EDGE_t for this enumeration. + */ +typedef enum XMC_VADC_TRIGGER_EDGE +{ + XMC_VADC_TRIGGER_EDGE_NONE = 0, /**< No external trigger. Conversion request can be asserted by software */ + XMC_VADC_TRIGGER_EDGE_FALLING, /**< The falling edge of the external trigger can assert conversion request */ + XMC_VADC_TRIGGER_EDGE_RISING, /**< The rising edge of the external trigger can assert conversion request */ + XMC_VADC_TRIGGER_EDGE_ANY /**< Both the edges can assert conversion request */ +} XMC_VADC_TRIGGER_EDGE_t; + +/** + * Defines the external trigger input selection possibilities, to assert a conversion. Refer the VADC interconnects + * section of the reference manual for details of peripherals which can be used. Also refer xmc_vadc_map.h file for + * detailed definitions of the peripherals which can take the control of these enumeration items. + * Use @ref XMC_VADC_TRIGGER_INPUT_SELECT_t for this enumeration. + */ +typedef enum XMC_VADC_TRIGGER_INPUT_SELECT +{ + XMC_VADC_REQ_TR_A = 0, /**< Trigger select signal A */ + XMC_VADC_REQ_TR_B, /**< Trigger select signal B */ + XMC_VADC_REQ_TR_C, /**< Trigger select signal C */ + XMC_VADC_REQ_TR_D, /**< Trigger select signal D */ + XMC_VADC_REQ_TR_E, /**< Trigger select signal E */ + XMC_VADC_REQ_TR_F, /**< Trigger select signal F */ + XMC_VADC_REQ_TR_G, /**< Trigger select signal G */ + XMC_VADC_REQ_TR_H, /**< Trigger select signal H */ + XMC_VADC_REQ_TR_I, /**< Trigger select signal I */ + XMC_VADC_REQ_TR_J, /**< Trigger select signal J */ + XMC_VADC_REQ_TR_K, /**< Trigger select signal K */ + XMC_VADC_REQ_TR_L, /**< Trigger select signal L */ + XMC_VADC_REQ_TR_M, /**< Trigger select signal M */ + XMC_VADC_REQ_TR_N, /**< Trigger select signal N */ + XMC_VADC_REQ_TR_O, /**< Trigger select signal O */ + XMC_VADC_REQ_TR_P /**< Trigger select signal P */ + +} XMC_VADC_TRIGGER_INPUT_SELECT_t; + +/** + * Defines the external gating input selection possibilities, to gate the conversion requests. Refer the VADC + * interconnects section of the reference manual for details of peripherals which can be used. Also refer + * xmc_vadc_map.h file for detailed definitions of the peripherals which can take the control of these enumeration + * items. Use @ref XMC_VADC_GATE_INPUT_SELECT_t for this enumeration. + */ +typedef enum XMC_VADC_GATE_INPUT_SELECT +{ + XMC_VADC_REQ_GT_A = 0, /**< Gating select signal A */ + XMC_VADC_REQ_GT_B, /**< Gating select signal B */ + XMC_VADC_REQ_GT_C, /**< Gating select signal C */ + XMC_VADC_REQ_GT_D, /**< Gating select signal D */ + XMC_VADC_REQ_GT_E, /**< Gating select signal E */ + XMC_VADC_REQ_GT_F, /**< Gating select signal F */ + XMC_VADC_REQ_GT_G, /**< Gating select signal G */ + XMC_VADC_REQ_GT_H, /**< Gating select signal H */ + XMC_VADC_REQ_GT_I, /**< Gating select signal I */ + XMC_VADC_REQ_GT_J, /**< Gating select signal J */ + XMC_VADC_REQ_GT_K, /**< Gating select signal K */ + XMC_VADC_REQ_GT_L, /**< Gating select signal L */ + XMC_VADC_REQ_GT_M, /**< Gating select signal M */ + XMC_VADC_REQ_GT_N, /**< Gating select signal N */ + XMC_VADC_REQ_GT_O, /**< Gating select signal O */ + XMC_VADC_REQ_GT_P /**< Gating select signal P */ + +} XMC_VADC_GATE_INPUT_SELECT_t; + +/** + * Defines the condition for gating the conversion requests. It can be used to set the ENGT field + * of ASMR/BSMR/QMR register respectively for auto_scan/background_scan/queue request sources. + * Use @ref XMC_VADC_GATEMODE_t for this enumeration. + */ +typedef enum XMC_VADC_GATEMODE +{ + XMC_VADC_GATEMODE_BLOCK = 0, /**< External triggers are permanently blocked */ + XMC_VADC_GATEMODE_IGNORE, /**< External triggers are unconditionally passed */ + XMC_VADC_GATEMODE_ACTIVEHIGH, /**< External trigger is passed only if the gate signal is high */ + XMC_VADC_GATEMODE_ACTIVELOW /**< External trigger is passed only if the gate signal is low */ +} XMC_VADC_GATEMODE_t; + +/** + * Defines the conversion result handling mode. Use @ref XMC_VADC_DMM_t for this enumeration. + */ +typedef enum XMC_VADC_DMM +{ + XMC_VADC_DMM_REDUCTION_MODE = 0, /**< Standard Data reduction mode*/ + XMC_VADC_DMM_FILTERING_MODE, /**< Provide option to select Finite Impulse Response Filter (FIR) or + Infinite Impulse Response Filter (IIR)*/ + XMC_VADC_DMM_DIFFERENCE_MODE, /**< Difference mode is selected*/ +} XMC_VADC_DMM_t; + +/** + * Defines the conversion mode. It defines the resolution of conversion. Use XMC_VADC_CONVMODE_t for this enumeration. + */ +typedef enum XMC_VADC_CONVMODE +{ + XMC_VADC_CONVMODE_12BIT = 0, /**< Results of conversion are 12bits wide */ + XMC_VADC_CONVMODE_10BIT = 1, /**< Results of conversion are 10bits wide */ + XMC_VADC_CONVMODE_8BIT = 2, /**< Results of conversion are 8bits wide */ + XMC_VADC_CONVMODE_FASTCOMPARE = 5 /**< Input signal compared with a preset range */ +} XMC_VADC_CONVMODE_t; + +/** + * Defines the output of a fast compare mode. Use @ref XMC_VADC_FAST_COMPARE_t for + * this enumeration. + */ +typedef enum XMC_VADC_FAST_COMPARE +{ + XMC_VADC_FAST_COMPARE_LOW = 0, /**< Input lower than than programmed reference */ + XMC_VADC_FAST_COMPARE_HIGH , /**< Input higher than than programmed reference */ + XMC_VADC_FAST_COMPARE_UNKNOWN /**< Unknown, Conversion probably still ongoing */ +} XMC_VADC_FAST_COMPARE_t; + +/** + * Defines the type of scan request source to be used. It can choose between auto scan and background scan request + * source methods. Use @ref XMC_VADC_SCAN_TYPE_t for this enumeration. + */ +typedef enum XMC_VADC_SCAN_TYPE +{ + XMC_VADC_SCAN_TYPE_GROUPSCAN = 0, /**< Auto scan mode of operation selected. Also called as Group scan*/ + XMC_VADC_SCAN_TYPE_BACKGROUND /**< Background scan mode of operation selected. Also called as Global scan*/ +} XMC_VADC_SCAN_TYPE_t; + +/** + * Defines the behavior of load event for the scan request source. Use @ref XMC_VADC_SCAN_LOAD_t for this enumeration. + */ +typedef enum XMC_VADC_SCAN_LOAD +{ + XMC_VADC_SCAN_LOAD_OVERWRITE = 0, /**< The old set of channels is discarded in favor of the new set + awaiting conversion */ + XMC_VADC_SCAN_LOAD_COMBINE /**< The new set of channels are combined with the pending channels from + previous set */ +} XMC_VADC_SCAN_LOAD_t; + +/** + * Defines the conversion classes that can be selected for each channel. The enumeration members holds the group or + * global classes. The conversion classes decides the properties of conversion, like resolution, sampling time etc + * Use @ref XMC_VADC_CHANNEL_CONV_t for this enumeration. + */ + +typedef enum XMC_VADC_CHANNEL_CONV +{ + XMC_VADC_CHANNEL_CONV_GROUP_CLASS0 = 0, /**< Conversion property set-0 specific to the group */ + XMC_VADC_CHANNEL_CONV_GROUP_CLASS1, /**< Conversion property set-1 specific to the group */ + XMC_VADC_CHANNEL_CONV_GLOBAL_CLASS0, /**< Conversion property set-0, Module wide */ + XMC_VADC_CHANNEL_CONV_GLOBAL_CLASS1 /**< Conversion property set-1, Module wide */ +} XMC_VADC_CHANNEL_CONV_t; + +/** + * Defines the references to boundary values used for limit checking feature. Each of these can be assigned as + * either an upper bound or a lower bound. Use @ref XMC_VADC_CHANNEL_BOUNDARY_t for this enumeration. + */ + +typedef enum XMC_VADC_CHANNEL_BOUNDARY +{ + XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0 = 0, /**< Group specific Boundary-0 value */ + XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND1, /**< Group specific Boundary-1 value */ + XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND0, /**< Module wide Boundary-0 value */ + XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND1 /**< Module wide Boundary-1 value */ +} XMC_VADC_CHANNEL_BOUNDARY_t; + +/** + * Defines the voltage which the capacitor is charged to. Used in Broken wire detection feature. Use + * @ref XMC_VADC_CHANNEL_BWDCH_t for this enumeration. + */ +typedef enum XMC_VADC_CHANNEL_BWDCH +{ + XMC_VADC_CHANNEL_BWDCH_VAGND = 0, /**< Capacitor pre-charged to ground*/ + XMC_VADC_CHANNEL_BWDCH_VAREF /**< Capacitor pre-charged to reference voltage*/ +} XMC_VADC_CHANNEL_BWDCH_t; + +/** + * Defines the criteria for event generation by the channel. Use @ref XMC_VADC_CHANNEL_EVGEN_t for this enumeration. + */ +typedef enum XMC_VADC_CHANNEL_EVGEN +{ + XMC_VADC_CHANNEL_EVGEN_NEVER = 0, /**< No event generated */ + XMC_VADC_CHANNEL_EVGEN_INBOUND = 1U, /**< Event generated when the result is within the normal range */ + XMC_VADC_CHANNEL_EVGEN_COMPHIGH = 1U, /**< Event generated when the result of fast compare operation is high */ + XMC_VADC_CHANNEL_EVGEN_OUTBOUND = 2U, /**< Event generated when the result is outside the normal range */ + XMC_VADC_CHANNEL_EVGEN_COMPLOW = 2U, /**< Event generated when the result result of fast compare operation is low */ + XMC_VADC_CHANNEL_EVGEN_ALWAYS = 3U /**< Event generated always after conversion - unconditionally */ +} XMC_VADC_CHANNEL_EVGEN_t; + +/** + * Defines the reference voltage selection for conversion. Use @ref XMC_VADC_CHANNEL_REF_t for this enumeration. + */ +typedef enum XMC_VADC_CHANNEL_REF +{ + XMC_VADC_CHANNEL_REF_INTREF = 0, /**< Internal VARef */ + XMC_VADC_CHANNEL_REF_ALT_CH0 /**< External voltage available on Channel-0 of the perticular group */ +} XMC_VADC_CHANNEL_REF_t; + +/** + * Defines the criteria for boundary flag assertion. Use @ref XMC_VADC_CHANNEL_BOUNDARY_CONDITION_t for this + * enumeration. + */ +typedef enum XMC_VADC_CHANNEL_BOUNDARY_CONDITION +{ + XMC_VADC_CHANNEL_BOUNDARY_CONDITION_ABOVE_BAND = 0, /**< Set Boundary condition criteria to assert above the band */ + XMC_VADC_CHANNEL_BOUNDARY_CONDITION_BELOW_BAND /**< Set Boundary condition criteria to assert below the band */ +} XMC_VADC_CHANNEL_BOUNDARY_CONDITION_t; + +/** + * Defines the event which can lead to a global service request assertion. Use @ref XMC_VADC_GLOBAL_EVENT_t for this + * enumeration. + */ +typedef enum XMC_VADC_GLOBAL_EVENT +{ + XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE = VADC_GLOBEFLAG_SEVGLB_Msk, /**< Background scan request source event */ + XMC_VADC_GLOBAL_EVENT_RESULT = VADC_GLOBEFLAG_REVGLB_Msk /**< Global result event */ +} XMC_VADC_GLOBAL_EVENT_t; + +/** + * Defines the power modes of a VADC Group. Use @ref XMC_VADC_GROUP_POWERMODE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_POWERMODE +{ + XMC_VADC_GROUP_POWERMODE_OFF = 0, /**< Group is powered down */ + XMC_VADC_GROUP_POWERMODE_RESERVED1, /**< Reserved */ + XMC_VADC_GROUP_POWERMODE_RESERVED2, /**< Reserved */ + XMC_VADC_GROUP_POWERMODE_NORMAL /**< Group is powered up */ +} XMC_VADC_GROUP_POWERMODE_t; + +/** + * Defines the status of a VADC group (also known as kernel). Use @ref XMC_VADC_GROUP_STATE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_STATE +{ + XMC_VADC_GROUP_STATE_IDLE = 0, /**< Idle and can convert if requested */ + XMC_VADC_GROUP_STATE_BUSY /**< Busy with an ongoing conversion */ +} XMC_VADC_GROUP_STATE_t; + +/** + * Defines the reference to sample time and conversion mode settings. Use @ref XMC_VADC_GROUP_CONV_t for this + * enumeration. + */ +typedef enum XMC_VADC_GROUP_CONV +{ + XMC_VADC_GROUP_CONV_STD = 0, /**< Settings pertaining to channels directly attached to VADC module */ + XMC_VADC_GROUP_CONV_EMUX /**< Settings pertaining to channels connected to VADC via EMUX */ +} XMC_VADC_GROUP_CONV_t; + +/** + * Defines the request source arbiter behavior. Use @ref XMC_VADC_GROUP_ARBMODE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_ARBMODE +{ + XMC_VADC_GROUP_ARBMODE_ALWAYS = 0, /**< Arbiter runs all the time */ + XMC_VADC_GROUP_ARBMODE_ONDEMAND /**< Arbiter runs only if a conversion request is asserted by any of the + request sources */ +} XMC_VADC_GROUP_ARBMODE_t; + +/** + * Defines the EMUX mode of operation. Use @ref XMC_VADC_GROUP_EMUXMODE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_EMUXMODE +{ + XMC_VADC_GROUP_EMUXMODE_SWCTRL = 0, /**< Perform EMUX in Software control mode*/ + XMC_VADC_GROUP_EMUXMODE_STEADYMODE, /**< Perform EMUX in Steady mode (Use EMUX set value)*/ + XMC_VADC_GROUP_EMUXMODE_SINGLEMODE, /**< Perform EMUX in Single step mode*/ + XMC_VADC_GROUP_EMUXMODE_SEQUENCEMODE, /**< Perform EMUX in Sequence mode*/ +} XMC_VADC_GROUP_EMUXMODE_t; + +/** + * Defines the EMUX channel selection encoding scheme. Use @ref XMC_VADC_GROUP_EMUXCODE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_EMUXCODE +{ + XMC_VADC_GROUP_EMUXCODE_BINARY = 0, /**< A linearly incrementing code serves are MUX-SEL */ + XMC_VADC_GROUP_EMUXCODE_GRAY /**< The MUX-SEL is gray encoded */ +} XMC_VADC_GROUP_EMUXCODE_t; + +/** + * Defines the service request set used. Use @ref XMC_VADC_GROUP_IRQ_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_IRQ +{ + XMC_VADC_GROUP_IRQ_KERNEL = 0, /**< Refers to Group specific service request */ + XMC_VADC_GROUP_IRQ_SHARED /**< Refers to Module wide service request */ +} XMC_VADC_GROUP_IRQ_t; + +/** + * Defines the alignment of the converted result. Use @ref XMC_VADC_RESULT_ALIGN_t for this enumeration. + */ +typedef enum XMC_VADC_RESULT_ALIGN +{ + XMC_VADC_RESULT_ALIGN_LEFT = 0, /**< Always align result to left */ + XMC_VADC_RESULT_ALIGN_RIGHT /**< Always align result to right */ +} XMC_VADC_RESULT_ALIGN_t; + +typedef enum XMC_VADC_RESULT_SUBTRATION +{ + XMC_VADC_RESULT_SUBTRATION_12BIT_LEFT_ALIGN = 0U, /**< Always align result to left */ + XMC_VADC_RESULT_SUBTRATION_12BIT_RIGHT_ALIGN = 0U, /**< Always align result to right */ + XMC_VADC_RESULT_SUBTRATION_10BIT_LEFT_ALIGN = 2U, /**< Always align result to left */ + XMC_VADC_RESULT_SUBTRATION_10BIT_RIGHT_ALIGN = 0U, /**< Always align result to right */ + XMC_VADC_RESULT_SUBTRATION_8BIT_LEFT_ALIGN = 4U, /**< Always align result to left */ + XMC_VADC_RESULT_SUBTRATION_8BIT_RIGHT_ALIGN = 0U, /**< Always align result to right */ +} XMC_VADC_RESULT_SUBTRATION_t; + +/** + * Defines the request source arbitration priority. Use @ref XMC_VADC_GROUP_RS_PRIORITY_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_RS_PRIORITY +{ + XMC_VADC_GROUP_RS_PRIORITY_0 = 0, /**< Lowest priority for the request source*/ + XMC_VADC_GROUP_RS_PRIORITY_1, /**< Second lowest priority for the request source*/ + XMC_VADC_GROUP_RS_PRIORITY_2, /**< Second highest priority for the request source*/ + XMC_VADC_GROUP_RS_PRIORITY_3, /**< Highest priority for the request source*/ +}XMC_VADC_GROUP_RS_PRIORITY_t; + +/** + * Defines the various modes for the boundary flag. Use @ref XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_BOUNDARY_FLAG_MODE +{ + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_DISABLED = 0, /**< Disable boundary flag*/ + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED, /**< Always enable boundary*/ + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_LOW, /**< Enable boundary flag when gate level is 0*/ + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_HIGH /**< Enable boundary flag when gate level is 1*/ +}XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_t; + + +/** + * Defines the boundary select for Channel. Use @ref XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_t for this enumeration. + */ +typedef enum XMC_VADC_BOUNDARY_SELECT +{ + XMC_VADC_BOUNDARY_SELECT_LOWER_BOUND = 0U, /**< Select the lower boundary*/ + XMC_VADC_BOUNDARY_SELECT_UPPER_BOUND = 2U /**< Selects the upper boundary*/ +}XMC_VADC_BOUNDARY_SELECT_t; + + +/** + * Defines the group indices. Use @ref XMC_VADC_GROUP_INDEX_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_INDEX +{ + XMC_VADC_GROUP_INDEX_0 = 0, + XMC_VADC_GROUP_INDEX_1, +#if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2U) + XMC_VADC_GROUP_INDEX_2, + XMC_VADC_GROUP_INDEX_3 +#endif +}XMC_VADC_GROUP_INDEX_t; + +/** +* Defines channel alias. +* All enum items are available for channels 0 and 1. Other Channels can accept only XMC_VADC_CHANNEL_ALIAS_DISABLED. +*/ +typedef enum XMC_VADC_CHANNEL_ALIAS +{ + XMC_VADC_CHANNEL_ALIAS_DISABLED = -1, + XMC_VADC_CHANNEL_ALIAS_CH0 = 0, + XMC_VADC_CHANNEL_ALIAS_CH1 = 1, + XMC_VADC_CHANNEL_ALIAS_CH2 = 2, + XMC_VADC_CHANNEL_ALIAS_CH3 = 3, + XMC_VADC_CHANNEL_ALIAS_CH4 = 4, + XMC_VADC_CHANNEL_ALIAS_CH5 = 5, + XMC_VADC_CHANNEL_ALIAS_CH6 = 6, + XMC_VADC_CHANNEL_ALIAS_CH7 = 7 +} XMC_VADC_CHANNEL_ALIAS_t; + +#if(XMC_VADC_SHS_AVAILABLE == 1U) + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/** + * Defines the gain calibration selection. + */ +typedef enum XMC_VADC_SHS_GAIN_LEVEL +{ + XMC_VADC_SHS_GAIN_LEVEL_0 = SHS_CALOC0_CALOFFVAL0_Pos, /**< Select the calibration value for gain level 0 */ + XMC_VADC_SHS_GAIN_LEVEL_1 = SHS_CALOC0_CALOFFVAL1_Pos, /**< Select the calibration value for gain level 1 */ + XMC_VADC_SHS_GAIN_LEVEL_2 = SHS_CALOC0_CALOFFVAL2_Pos, /**< Select the calibration value for gain level 2 */ + XMC_VADC_SHS_GAIN_LEVEL_3 = SHS_CALOC0_CALOFFVAL3_Pos /**< Select the calibration value for gain level 3 */ +}XMC_VADC_SHS_GAIN_LEVEL_t; +#endif + +/** + * Defines the Delta sigma loop. + */ +typedef enum XMC_VADC_SHS_LOOP_CH +{ + XMC_VADC_SHS_LOOP_CH_0 = SHS_LOOP_LPCH0_Pos, /**< Select Delta-sigma loop 0*/ + XMC_VADC_SHS_LOOP_CH_1 = SHS_LOOP_LPCH1_Pos /**< Select Delta-sigma loop 1*/ +}XMC_VADC_SHS_LOOP_CH_t; + +/** + * Provides the order in which the SHS should do the calibration + */ +typedef enum XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER +{ + XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_POST_CONV = 0, /**< Calibration occur after conversion takes place */ + XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_PRE_CONV /**< Calibration occur before conversion takes place */ +}XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_t; +#endif + +#if (XMC_VADC_BOUNDARY_FLAG_SELECT == 1U) +/** + * Provides possible routing values for the boundary flag. + */ +typedef enum XMC_VADC_BOUNDARY_NODE +{ + XMC_VADC_BOUNDARY_NODE_COMMON_BOUNDARY_FLAG_0 = 0U, /** 2U) + XMC_VADC_SYNCTR_EVAL_2 = VADC_G_SYNCTR_EVALR2_Msk, /**Range:[0x0 to 0x7] */ + uint32_t refill_needed : 1; /**< Conversion completed channel gets inserted back into the queue */ + uint32_t generate_interrupt : 1; /**< Generates a queue request source event */ + uint32_t external_trigger : 1; /**< Conversion requests are raised on an external trigger. */ + uint32_t : 24; + + }; + uint32_t qinr0; + }; +} XMC_VADC_QUEUE_ENTRY_t; + +/** + * Structure initializing a VADC queue request source. Use type @ref XMC_VADC_QUEUE_CONFIG_t. + */ +typedef struct XMC_VADC_QUEUE_CONFIG +{ + uint32_t conv_start_mode : 2; /**< One converter is shared between the queue and scan request sources of the same + group. This field determines how queue request source would request for + conversion. Uses @ref XMC_VADC_STARTMODE_t */ + uint32_t req_src_priority : 2; /**< Request source priority for the arbiter.Uses @ref XMC_VADC_GROUP_RS_PRIORITY_t */ + union + { + struct + { +#if(XMC_VADC_GROUP_SRCREG_AVAILABLE == (1U)) + uint32_t src_specific_result_reg : 4; /**< Uses any one Group related result register as the destination + for all conversions results. To use the individual result register + from each channel configuration, configure this field with 0x0 */ +#else + uint32_t : 4; +#endif + uint32_t : 4; + uint32_t trigger_signal : 4; /**< Select one of the 16 possibilities for trigger. + Uses @ref XMC_VADC_TRIGGER_INPUT_SELECT_t */ + uint32_t : 1; + uint32_t trigger_edge : 2; /**< Edge selection for trigger signal. + Uses @ref XMC_VADC_TRIGGER_EDGE_t */ + uint32_t : 1; + uint32_t gate_signal : 4; /**< Select one of the 16 possibilities for gating. + Uses @ref XMC_VADC_GATE_INPUT_SELECT_t */ + uint32_t : 8; + uint32_t timer_mode : 1; /**< Timer mode for equi-distant sampling shall be activated or not? */ + uint32_t : 3; + }; + uint32_t qctrl0; + }; + union + { + struct + { + uint32_t : 2; + uint32_t external_trigger : 1; /**< Are external triggers supported? */ + uint32_t : 29; + }; + uint32_t qmr0; + }; +} XMC_VADC_QUEUE_CONFIG_t; + + +/** + * Structure to initialize the global input class configuration. Configured parameters are sample time and + * conversion Mode. + */ +typedef struct XMC_VADC_GLOBAL_CLASS +{ + union + { + struct + { + uint32_t sample_time_std_conv : 5; /**< Sample time for channels directly connected to VADC +
Range: [0x0 to 0x1F] */ + uint32_t : 3; + uint32_t conversion_mode_standard : 3; /**< Conversion mode for channels directly connected to VADC. + Uses @ref XMC_VADC_CONVMODE_t */ + uint32_t : 5; +#if(XMC_VADC_EMUX_AVAILABLE == 1U) + uint32_t sampling_phase_emux_channel : 5; /**< Sample time for channels connected via EMUX +
Range: [0x0 to 0x1F] */ + uint32_t : 3; + uint32_t conversion_mode_emux : 3; /**< Conversion mode for channels connected via EMUX to VADC. + Uses @ref XMC_VADC_CONVMODE_t */ + uint32_t : 5; +#else + uint32_t : 16; +#endif + }; + uint32_t globiclass; + }; +} XMC_VADC_GLOBAL_CLASS_t; + +#if (XMC_VADC_GROUP_AVAILABLE != 0U) +/** + * Structure to initialize converter and arbiter clock configuration + */ +typedef struct XMC_VADC_GLOBAL_CLOCK +{ + union + { + struct + { + + uint32_t analog_clock_divider : 5; /**< Clock for the converter.
Range: [0x0 to 0x1F] */ + uint32_t : 2; + uint32_t msb_conversion_clock : 1; /**< Additional clock cycle for analog converter */ + uint32_t arbiter_clock_divider : 2; /**< Request source arbiter clock divider.
Range: [0x0 to 0x3] */ + uint32_t : 5; + uint32_t : 17; + }; + uint32_t globcfg; + }; +} XMC_VADC_GLOBAL_CLOCK_t; +#endif + + +/** + * Structure to initialize the VADC Global functions + */ +typedef struct XMC_VADC_GLOBAL_CONFIG +{ + union + { + struct + { + uint32_t boundary0 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; + uint32_t boundary1 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; + }; + uint32_t globbound; + }; +#if (XMC_VADC_GROUP_AVAILABLE != 0U) + XMC_VADC_GLOBAL_CLOCK_t clock_config; /**< ADC clock configurations*/ +#endif + XMC_VADC_GLOBAL_CLASS_t class0; /**< ADC input conversion configurations for GLOBICLASS[0]*/ + XMC_VADC_GLOBAL_CLASS_t class1; /**< ADC input conversion configurations for GLOBICLASS[1]*/ + union + { + struct + { + uint32_t : 16; + uint32_t data_reduction_control : 4; /**< Data reduction stages */ + uint32_t : 4; + uint32_t wait_for_read_mode : 1; /**< Results of the next conversion will not be overwritten in the + result register until the previous value is read*/ + uint32_t : 6; + uint32_t event_gen_enable : 1; /**< Generates an event on availability of new result. */ + }; + uint32_t globrcr; + }; + union + { + struct + { + uint32_t module_disable : 1; /**< Disables the module clock.*/ + uint32_t : 2; + uint32_t disable_sleep_mode_control : 1; /**< Set it to true in order to disable the Sleep mode */ + uint32_t : 28; + }; + uint32_t clc; + }; +} XMC_VADC_GLOBAL_CONFIG_t; + + +/** + * Structure to initialize the group input class configuration. Configured parameters are sample time and + * conversion Mode. + */ +typedef struct XMC_VADC_GROUP_CLASS +{ + union + { + struct + { + uint32_t sample_time_std_conv : 5; /**< Sample time for channels directly connected to VADC +
Range: [0x0 to 0x1F] */ + uint32_t : 3; + uint32_t conversion_mode_standard : 3; /**< Conversion mode for channels directly connected to VADC. + Uses @ref XMC_VADC_CONVMODE_t */ + uint32_t : 5; + uint32_t sampling_phase_emux_channel : 5; /**< Sample time for channels connected via EMUX +
Range: [0x0 to 0x1F] */ + uint32_t : 3; + uint32_t conversion_mode_emux : 3; /**< Conversion mode for channels connected via EMUX to VADC. + Uses @ref XMC_VADC_CONVMODE_t */ + uint32_t : 5; + }; + uint32_t g_iclass0; + }; +} XMC_VADC_GROUP_CLASS_t; + + +/** + * EMUX related configuration structure. + */ +typedef struct XMC_VADC_GROUP_EMUXCFG +{ + union + { + struct + { + uint32_t starting_external_channel : 3; /**< External channel number to which the VADC will + generate a control signal (needed to select the analog input in + the analog multiplexer)*/ + uint32_t : 13; +#if (XMC_VADC_EMUX_CH_SEL_STYLE == 1U) + uint32_t connected_channel : 10; /**< The Channel to which the EMUX is connected. */ +#else + uint32_t connected_channel : 5; /**< The Channel to which the EMUX is connected. */ + uint32_t : 5; +#endif + uint32_t emux_mode : 2; /**< Selects the external multiplexer modes: Steady, Single Mode, step etc + Uses @ref XMC_VADC_GROUP_EMUXMODE_t*/ + uint32_t emux_coding : 1; /**< Select Binary or Gray coding. Uses @ref XMC_VADC_GROUP_EMUXCODE_t*/ + uint32_t stce_usage : 1; /**< Use STCE for each conversion of an external channel */ +#if (XMC_VADC_EMUX_CH_SEL_STYLE == 1U) + uint32_t emux_channel_select_style : 1; /**< Selects the style of configuring the \b connected_channel + (Each bit represents the channel or entire field represents the channel number ) */ + uint32_t : 1; +#else + uint32_t : 2; +#endif + }; + uint32_t g_emuxctr; + }; +} XMC_VADC_GROUP_EMUXCFG_t; + + +/** + * Group Configuration Data Structures + */ + +typedef struct XMC_VADC_GROUP_CONFIG +{ + XMC_VADC_GROUP_EMUXCFG_t emux_config; /**< External multiplexer related configurations */ + XMC_VADC_GROUP_CLASS_t class0; /**< ADC input conversion configurations for GxICLASS[0]*/ + XMC_VADC_GROUP_CLASS_t class1; /**< ADC input conversion configurations for GxICLASS[1]*/ + union + { + struct + { + uint32_t boundary0 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; + uint32_t boundary1 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; + }; + uint32_t g_bound; + }; + union + { + struct + { + uint32_t : 4; + uint32_t arbitration_round_length : 2; /**< Number of arbiter slots to be considered */ + uint32_t : 1; + uint32_t arbiter_mode : 1; /**< Arbiter mode - Select either Continuous mode or Demand based. + Uses @ref XMC_VADC_GROUP_ARBMODE_t */ + uint32_t : 24; + }; + uint32_t g_arbcfg; + }; +} XMC_VADC_GROUP_CONFIG_t; + +/** + * Structure to initialize VADC Group result register. + */ + +typedef struct XMC_VADC_RESULT_CONFIG +{ + union + { + struct + { + uint32_t : 16; + uint32_t data_reduction_control : 4; /**< Configures the data reduction stages */ + uint32_t post_processing_mode : 2; /**< Result data processing mode. Uses @ref XMC_VADC_DMM_t + For normal operation select + XMC_VADC_DMM_t::XMC_VADC_DMM_REDUCTION_MODE + and data_reduction_control as 0*/ + uint32_t : 2; + uint32_t wait_for_read_mode : 1; /**< Allow the conversion only after previous results are read*/ + uint32_t part_of_fifo : 2; /**< Make the result register a part of Result FIFO? */ + uint32_t : 4; + uint32_t event_gen_enable : 1; /**< Generates an event on availability of new result. */ + }; + uint32_t g_rcr; + }; +} XMC_VADC_RESULT_CONFIG_t; + +#if(XMC_VADC_SHS_AVAILABLE == 1U) +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/** + * Structure to initialize the Stepper configurations + */ +typedef struct XMC_VADC_GLOBAL_SHS_STEP_CONFIG +{ + union + { + struct + { + uint32_t sh_unit_step0 :3; /**< Select a Sample and hold unit for the stepper's step number 0. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step0 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step1 :3; /**< Select a Sample and hold unit for the stepper's step number 1. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step1 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step2 :3; /**< Select a Sample and hold unit for the stepper's step number 2. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step2 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step3 :3; /**< Select a Sample and hold unit for the stepper's step number 3. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step3 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step4 :3; /**< Select a Sample and hold unit for the stepper's step number 4. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step4 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step5 :3; /**< Select a Sample and hold unit for the stepper's step number 5. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step5 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step6 :3; /**< Select a Sample and hold unit for the stepper's step number 6. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step6 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step7 :3; /**< Select a Sample and hold unit for the stepper's step number 7. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step7 :1; /**< Should the step be added to the sequence */ + + }; + uint32_t stepcfg; + }; +}XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t; +#endif +/** + * Sample and hold Initialization structure + */ +typedef struct XMC_VADC_GLOBAL_SHS_CONFIG +{ + union + { + struct + { + uint32_t shs_clock_divider :4; /**< The divider value for the SHS clock. Range: [0x0 to 0xF]*/ + uint32_t :6; + uint32_t analog_reference_select :2; /**< It is possible to different reference voltage for the SHS module + */ + uint32_t :20; + }; + uint32_t shscfg; + }; +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) + XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_t calibration_order; /**< order in which the calibration should be taken up*/ +#endif +}XMC_VADC_GLOBAL_SHS_CONFIG_t; + +#endif +/** + * Detailed result structure + */ + typedef struct XMC_VADC_DETAILED_RESULT +{ + union + { + struct + { + uint32_t result :16; /**< Result of the Analog to digital conversion*/ + uint32_t data_reduction_counter :4; /**< Results reduction counter value*/ + uint32_t channel_number :5; /**< Converted channel number*/ + uint32_t emux_channel_number :3; /**< Converted external multiplexer channel number. + Only applicable for GxRES[0] result register*/ + uint32_t converted_request_source :2; /**< Converted request source*/ + uint32_t fast_compare_result :1; /**< Fast compare result if conversion mode is fast compare mode.*/ + uint32_t vaild_result :1; /**< Valid flag is set when a new result is available*/ + }; + uint32_t res; + }; +}XMC_VADC_DETAILED_RESULT_t; + + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * static inline functions + ********************************************************************************************************************/ + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +__STATIC_INLINE bool XMC_VADC_CHECK_GROUP_PTR(XMC_VADC_GROUP_t *const group_ptr) +{ +#if (XMC_VADC_MAXIMUM_NUM_GROUPS == 4U) + return((group_ptr == VADC_G0) || (group_ptr == VADC_G1) || (group_ptr == VADC_G2) || (group_ptr == VADC_G3)); +#else + return((group_ptr == VADC_G0) || (group_ptr == VADC_G1)); +#endif +} +#endif +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Enables the VADC module.
\n + * This API would ungate the clock to the VADC module (if applicable). Also this API would bring + * the VADC module out of reset state(if applicable), by asserting the appropriate registers. + * This API would invoke XMC_SCU_CLOCK_UngatePeripheralClock() and XMC_SCU_RESET_DeassertPeripheralReset() + * if needed. Directly accessed register is COMPARATOR.ORCCTRL (Refer to the errata for XMC1100). + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_DisableModule(). + */ +void XMC_VADC_GLOBAL_EnableModule(void); + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Disables the VADC module.
\n + * This API would gate the clock to the VADC module (if applicable). Also this API would put + * the VADC module into the reset state(if applicable) by asserting the appropriate registers. + * This API would invoke XMC_SCU_CLOCK_GatePeripheralClock() and XMC_SCU_RESET_AssertPeripheralReset() if needed. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_EnableModule(). + */ +void XMC_VADC_GLOBAL_DisableModule(void); + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * @param config Pointer to initialization data structure + * + * @return None + * + * \parDescription:
+ * Initializes the VADC global module with the associated configuration structure pointed by \a config.\n\n It + * enables the global access to registers by configuring reset and clock un-gating for selected devices. It + * initializes global class, boundary , result resources by setting GLOBICLASS,GLOBBOUND,GLOBRCR registers. It also + * configures the global analog and digital clock dividers by setting GLOBCFG register. Refer related API's to change + * the configurations later in the program. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_ClockInit()
+ */ +void XMC_VADC_GLOBAL_Init(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CONFIG_t *config); + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Enables the VADC module clock.\n\n Call this API before any further configuration of VADC. It sets the DISR bit of CLC + * register to enable. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_Init() + * + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_EnableModuleClock(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_Enable:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->CLC &= ~((uint32_t)VADC_CLC_DISR_Msk); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Disables the VADC module clock.\n\n After this API call, no conversion will occur. Call + * XMC_VADC_GLOBAL_EnableModuleClock() to enable the VADC module later in the program. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_Init() + * + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_DisableModuleClock(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_Disable:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->CLC |= (uint32_t) ((uint32_t)1 << VADC_CLC_DISR_Pos); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Enables VADC module to sleep if a sleep request comes.\n\n + * It resets the EDIS bit of CLC register for enabling the sleep mode. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_DisableSleepMode(). + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_EnableSleepMode(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_EnableSleepMode:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->CLC &= ~((uint32_t)VADC_CLC_EDIS_Msk); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Ignores the sleep mode request for the VADC.\n\n + * With the sleep feature enabled, the module will respond to sleep + * requests by going into a low power mode. It resets the EDIS bit of CLC register for enabling the sleep mode. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_EnableSleepMode(). + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_DisableSleepMode(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_DisableSleepMode:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->CLC |= (uint32_t) ((uint32_t)1 << VADC_CLC_EDIS_Pos); +} + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +/** + * + * @param global_ptr Constant pointer to the VADC module. + * @param config Pointer to the data structure containing clock configuration data + * + * @return None + * + * \parDescription:
+ * Configures the VADC clock.
\n + * Sets up the clock configuration of the VADC module using the config structure pointed by \a config. + * The clock to the analog converter and to the request source arbiter is configured by setting the GLOBCFG register. + * + * \parRelated APIs:
+ * None + * + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_ClockInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CLOCK_t *config) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_ClockInit:Wrong Module Pointer", (global_ptr == VADC)) + + /* Write the Clock configuration into the GLOBCFG register */ + global_ptr->GLOBCFG = (uint32_t)(config->globcfg | (VADC_GLOBCFG_DIVWC_Msk)); +} +#endif + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * @param config Conversion class parameter structure + * @param conv_type configure the input call for either standard conversion or EMUX related conversion. + * @param set_num Conversion class set
+ * Range: [0x0, 0x1] + * + * \parDescription:
+ * Configures the ADC conversion settings like sample time and resolution.
\n + * Sets up the conversion settings for vadc global resource associated with \a config structure. It configures the + * conversion class properties like sampling time and resolution for selected \a conv_type channels. It initializes + * the GLOBALICLASS register specified by \a set_num with the required settings. + * + * + * \parRelated APIs:
+ * None + * + */ + +void XMC_VADC_GLOBAL_InputClassInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CLASS_t config, + const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num); + +/** + * + * @param global_ptr Constant pointer to the VADC global module + * @param config Pointer to result configuration data structure + * + * @return None + * + * \parDescription:
+ * Initializes global result register.
\n + * Initializes Global Result Register with specified settings configured in the \a config structure.\n\n This API + * results in configuration of GLOBRCR register. This helps in configuring the Data reduction mode, global result event + * , wait for read mode on the GLOBRES register. + * + * + * \parRelated APIs:
+ * None + * + */ + + __STATIC_INLINE void XMC_VADC_GLOBAL_ResultInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_RESULT_CONFIG_t *config) + { + XMC_ASSERT("XMC_VADC_GLOBAL_ResultInit:Wrong Module Pointer", (global_ptr == VADC)) + + /* Configure GLOBRCR*/ + global_ptr->GLOBRCR = config->g_rcr; + } + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Enables the startup calibration feature of the VADC module.\n\n It configures the SUCAL bit of GLOBCFG register to + * enable the startup calibration feature. After turning it on, it loops until all active groups finish calibration. + * Call XMC_VADC_GLOBAL_Enable() and XMC_VADC_GLOBAL_ClockInit() before calling this API in sequence. Calling the API + * XMC_VADC_GLOBAL_DisableStartupCalibration() can disable the calibration feature at runtime. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_Enable()
+ * XMC_VADC_GLOBAL_ClockInit()
+ * None + */ +void XMC_VADC_GLOBAL_StartupCalibration(XMC_VADC_GLOBAL_t *const global_ptr); + + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Disables the startup calibration feature of the VADC module.\n\n It configures the SUCAL bit of GLOBCFG register to + * disable the startup calibration feature. Calling the API XMC_VADC_GLOBAL_EnsableStartupCalibration() can enable the + * calibration feature at runtime. + * + * \parRelated APIs:
+ * None + */ + +__STATIC_INLINE void XMC_VADC_GLOBAL_DisableStartupCalibration(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_DisableStartupCalibration:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->GLOBCFG &= ~((uint32_t)VADC_GLOBCFG_SUCAL_Msk); +} + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param group_number group number whose post calibration feature is to be disabled.
+ * Range[0x0 to 0x3] Accepts the enum ::XMC_VADC_GROUP_INDEX_t + * + * @return None + * + * \parDescription:
+ * Disables the post calibration for a particular group specified as \a group_number.\n\n It configures the DPCAL0 bit + * of GLOBCFG register to disable the post calibration feature. Call XMC_VADC_GLOBAL_Enable() and + * XMC_VADC_GLOBAL_ClockInit() before calling this API in sequence. Calling the API + * XMC_VADC_GLOBAL_EnablePostCalibration() can enable back the calibration feature at runtime. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_Enable()
+ * XMC_VADC_GLOBAL_ClockInit()
+ * XMC_VADC_GLOBAL_DisablePostCalibration()
+ * None + */ + +__STATIC_INLINE void XMC_VADC_GLOBAL_DisablePostCalibration(XMC_VADC_GLOBAL_t *const global_ptr, uint32_t group_number) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_DisablePostCalibration:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->GLOBCFG |= (uint32_t)((uint32_t)1 << ((uint32_t)VADC_GLOBCFG_DPCAL0_Pos + group_number)); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param group_number group number whose post calibration feature is to be enabled.
+ * Range[0x0 to 0x3] Accepts the enum ::XMC_VADC_GROUP_INDEX_t + * + * @return None + * + * \parDescription:
+ * Enables the post calibration for a particular group specified as \a group_number.\n\n It configures the DPCAL0 bit + * of GLOBCFG register to enable the post calibration feature. Calling the API XMC_VADC_GLOBAL_DisablePostCalibration() + * can disable the calibration feature at runtime. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_DisablePostCalibration()
+ * None + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_EnablePostCalibration(XMC_VADC_GLOBAL_t *const global_ptr, uint32_t group_number) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_EnablePostCalibration:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->GLOBCFG &= (~ (uint32_t)((uint32_t)1 << ((uint32_t)VADC_GLOBCFG_DPCAL0_Pos + group_number))); +} +#endif + +#if (XMC_VADC_BOUNDARY_AVAILABLE == 1U) +/** + * + * @param global_ptr Constant pointer to the VADC module. + * @param boundary0 Boundary-0 Value
Range[0 - 4095] + * @param boundary1 Boundary-1 Value
Range[0 - 4095] + * + * @return None + * + * \parDescription:
+ * Programs the boundaries with \a boundary0 and boundary1 for result comparison.\n\n These two boundaries can serve as + * absolute boundaries. They define a range against which the result of a conversion can be compared. In the + * fast compare mode, the two boundaries provide hysteresis capability to a compare value. In any case, these boundary + * values entered here form a boundary pallete. There are dedicated upper and lower boundary registers GLOBBOUND0 and + * GLOBBOUND1 who will derive their values from this palette. + * + * \parRelated APIs:
+ * None + * + */ +void XMC_VADC_GLOBAL_SetBoundaries(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t boundary0, const uint32_t boundary1); + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * @param selection The boundary value selected for \b boundary_value. + * @param boundary_value Boundary Value
Range[0 - 4095] + * + * @return None + * + * \parDescription:
+ * Programs either the boundary 0 or boundary 1 for result comparison.\n\n This defines a range against which + * the result of a conversion can be compared. In the fast compare mode, the two boundaries provide hysteresis + * capability to a compare value. + * + * \parRelated APIs:
+ * None + * + */ +void XMC_VADC_GLOBAL_SetIndividualBoundary(XMC_VADC_GLOBAL_t *const global_ptr, + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value); +#endif + +#if (XMC_VADC_EMUX_AVAILABLE== 1U) +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param emuxif The EMUX interface
Range[0x0 - 0x1] + * @param group The VADC group which must be bound to the desired emux + * + * @return None + * + * \parDescription:
+ * Binds a VADC \a group to an EMUX interface specified in \a emuxif.
\n + * Selects which group's scan request source will control the EMUX interface (set of control select lines for the EMUX). + * By passing \b group it would configure that group's scan request source to control the EMUX select lines of the set + * \b emuxif. + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GLOBAL_BindGroupToEMux(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t emuxif, const uint32_t group); +#endif + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return uint32_t Complete global result register value GLOBRES + * + * \parDescription:
+ * Retrieves the complete result from the global result register associated with the \a global_ptr.\n\n This API audits + * the result register GLOBRES for the validity of the data. If the validity is assured, data is first read + * the global result register, cached locally next and subsequently returned to the caller. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_GetResult() + */ +__STATIC_INLINE uint32_t XMC_VADC_GLOBAL_GetDetailedResult(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_GetDetailedResult:Wrong Module Pointer", (global_ptr == VADC)) + + return(global_ptr->GLOBRES); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return XMC_VADC_RESULT_SIZE_t 16 bit result register value.
+ * Range[0x0 - 0X0FFF] + * + * \parDescription:
+ * Retrieves the conversion result from the global result register associated with the \a global_ptr.\n\n This is a + * lightweight version of XMC_VADC_GLOBAL_GetDetailedResult(). The behavior is exactly the same, just that it is + * only the 16 bit numeric result returned back to the application instead of the complete GLOBRES register value. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_GetDetailedResult() + */ +__STATIC_INLINE XMC_VADC_RESULT_SIZE_t XMC_VADC_GLOBAL_GetResult(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_GetResult:Wrong Module Pointer", (global_ptr == VADC)) + + return ((XMC_VADC_RESULT_SIZE_t)global_ptr->GLOBRES); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param compare_val Compare value which the result of a conversion will be compared against. + *
Range[0x0 - 0X0FFF] + * + * @return None + * + * \parDescription:
+ * Set compare value in the global result register for fast compare mode.\n\n The result of a conversion will directly + * be compared to the compare value entered as part of \a compare_val. The prerequisite is that the channel associated + * with this global register must select an ICLASS which has the conversion mode configured as fast compare mode. Call + * @ref XMC_VADC_GLOBAL_GetCompareResult() after this API to + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GLOBAL_SetCompareValue(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_RESULT_SIZE_t compare_val); + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @return compare high or low. Refer @ref XMC_VADC_FAST_COMPARE_t enum + * + * @return None + * + * \parDescription:
+ * Determines the result of fast compare operation.\n\n This API returns the result of fast compare operation provided + * the valid flag in the global result register GLOBRES is set. + * + * \parRelated APIs:
+ * None + */ +XMC_VADC_FAST_COMPARE_t XMC_VADC_GLOBAL_GetCompareResult(XMC_VADC_GLOBAL_t *const global_ptr); + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param event_type Desired event that must be manually asserted + * Use the enum ::XMC_VADC_GLOBAL_EVENT_t to create a mask to be used with this argument + * @return None + * + * \parDescription:
+ * Manually asserts an event that can lead to an interrupt.\n\n This API manually asserts the requested event + * (Background request source event or a global result event) by setting the GLOBEVFLAG register with the specified + * \a event_type. + * + * \parRelated APIs:
+ * None + */ + +__STATIC_INLINE void XMC_VADC_GLOBAL_TriggerEvent(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t event_type) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_TriggerEvent:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_TriggerEvent:Wrong Global Event", + ((XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE == event_type) || (XMC_VADC_GLOBAL_EVENT_RESULT == event_type))) + + global_ptr->GLOBEFLAG = event_type; +} + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param event_type Event that must be acknowledged + * Use the enum ::XMC_VADC_GLOBAL_EVENT_t to create a mask to be used with this argument + * + * @return None + * + * \parDescription:
+ * Acknowledges an event that has been asserted manually or automatically.\n\n This API acknowledges the requested event + * by clearing GLOBEFLAG sticky flag. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_ClearEvent(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t event_type) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_ClearEvent:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_ClearEvent:Wrong Global Event", + ((XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE == event_type) || (XMC_VADC_GLOBAL_EVENT_RESULT == event_type))) + + global_ptr->GLOBEFLAG = ((uint32_t)(event_type << (uint32_t)16)); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param sr The service request to which the global result event is connected. Refer @ref XMC_VADC_SR_t enum + * + * @return None + * + * \parDescription:
+ * Binds the global result event to one of the 4 shared service requests.\n\n This API binds the global result event + * to one of the 4 module wide shared service requests .Sets GLOBEVNP register with the corresponding \a sr line. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode() + */ +void XMC_VADC_GLOBAL_SetResultEventInterruptNode(XMC_VADC_GLOBAL_t *const global_ptr, XMC_VADC_SR_t sr); + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param sr The service request to which the global request source event is connected. Refer @ref XMC_VADC_SR_t enum + * + * @return None + * + * \parDescription:
+ * Binds the background request source event to one of the 4 shared service requests.\n\n This API binds the background + * request source event to one of the 4 module wide shared service requests. Sets GLOBEVNP register with the + * corresponding \a sr line. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SetResultEventInterruptNode() + */ +void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *const global_ptr, XMC_VADC_SR_t sr); + +#if(XMC_VADC_SHS_AVAILABLE == 1U) +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param config Struct consisting of various SHS related configurations. + * + * @return None + * + * \parDescription:
+ * Configure the basic SHS parameters.
\n + * API would initialize the clock divider configuration, the analog reference selection and + * the calibration order for the Sample and Hold unit. + * + * \parRelated APIs:
+ * None. + */ + void XMC_VADC_GLOBAL_SHS_Init(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, const XMC_VADC_GLOBAL_SHS_CONFIG_t *config); + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) + /** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param config Struct consisting of various step configurations. + * + * @return None + * + * \parDescription:
+ * Configures the stepper sequence for the converter.
\n + * Stepper of the SHS can be configured to take up a specific sequence of groups for conversion. + * The stepper sequence is configured using this API. + * + * \parRelated APIs:
+ * None. + */ + __STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetStepperSequence(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + const XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t *config) + { + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_StepperInit:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_StepperInit:Wrong config pointer", + (config == (XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t*)NULL)) + + shs_ptr->STEPCFG = (uint32_t) config->stepcfg; + } +#endif + + /** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * + * @return bool returns true if the analog converter is operable + * returns false if the analog converter is powered down + * + * \parDescription:
+ * Returns the converter status.
\n + * Returns the ANRDY bit field of the SHSCFG register. + * + * \parRelated APIs:
+ * None. + */ + __STATIC_INLINE bool XMC_VADC_GLOBAL_SHS_IsConverterReady(XMC_VADC_GLOBAL_SHS_t *const shs_ptr) + { + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_IsConverterReady:Wrong SHS Pointer",(shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + + return((bool)((shs_ptr->SHSCFG >> (uint32_t)SHS_SHSCFG_ANRDY_Pos) & (uint32_t)0x1)); + } + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num group number for which the accelerated mode needs to be enabled.
Range: [0x0 to 0x1] + * + * @return None + * + * \parDescription:
+ * Enables the Accelerated timing mode.
\n + * This API is needed when a switch from compatible mode to accelerated mode of conversion is needed. In + * this mode the ADC module will convert the input depending on the value stored in the SST bit of the SHS0_TIMCFGx. + * This API would configure the accelerated mode in the SHS0_TIMCFG0 and SHS0_TIMCFG1 registers. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr,XMC_VADC_GROUP_INDEX_t group_num); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num group number for which the accelerated mode needs to be disabled.
Range: [0x0 to 0x1] + * + * @return None + * + * \parDescription:
+ * Enables the Accelerated timing mode.
\n + * This API is needed when a switch from accelerated mode to compatible mode of conversion is needed. + * This API would clear the accelerated mode in the SHS0_TIMCFG0 and SHS0_TIMCFG1 registers. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr,XMC_VADC_GROUP_INDEX_t group_num); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num group number for which the accelerated mode needs to be enabled.
Range: [0x0 to 0x1] + * @param sst_value Value of short sample time that needs to be configured.
+ * Range: [0x0 to 0x3F] + * + * @return None + * + * \parDescription:
+ * Configures the Accelerated timing mode sample time.
\n + * This API is needed when a switch from compatible mode to accelerated mode of conversion is needed. In + * Accelerated mode the ADC module will convert the input depending on the value stored in the SST bit of the + * SHS0_TIMCFGx. This API would configure the shot sample time either in SHS0_TIMCFG0.SST or SHS0_TIMCFG1.SST . + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GLOBAL_SHS_SetShortSampleTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + uint8_t sst_value); + +#endif +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param divs_value The clock divider value that is possible + *
Range:[0x0 to 0xF] + * @return None + * + * \parDescription:
+ * Configure Sample and hold clock divider value.
\n + * API would initialize the clock divider configuration. This determines the frequency of conversion + * of the Sample and hold converter. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetClockDivider(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, uint8_t divs_value) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetClockDivider:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetClockDivider:Wrong divide factor selected", + (divs_value < (uint32_t)0x10)) + + shs_ptr->SHSCFG = (shs_ptr->SHSCFG & (~(uint32_t)SHS_SHSCFG_DIVS_Msk)) | (uint32_t)SHS_SHSCFG_SCWC_Msk; + shs_ptr->SHSCFG |= ((uint32_t)divs_value << SHS_SHSCFG_DIVS_Pos) | (uint32_t)SHS_SHSCFG_SCWC_Msk; +} + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param gain_value gain value possible + * Range:[0x0 to 0x3] + * @param group_num The Group number for which the configurations applies + * @param ch_num The channel number for which the gain has to be configured + * @return None + * + * \parDescription:
+ * Configure the gain value for SHS.
\n + * API would set the gain factor for a selected channel. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GLOBAL_SHS_SetGainFactor(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + uint8_t gain_value, + XMC_VADC_GROUP_INDEX_t group_num, + uint8_t ch_num); + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param max_calibration_time calibration time + * Range:[0x0 to 0x3F] + * @return None + * + * \parDescription:
+ * Configure the Maximum calibration timing.
\n + * API would initialize the Maximum time after which the calibration should occur. If no adc conversion + * occur during this duration then the calibration would run irrespective of conversions. The max time the + * converter can go without a calibration is set in this API. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetMaxCalTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + uint32_t max_calibration_time) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetMaxCalTime:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + + shs_ptr->CALCTR &= ~((uint32_t)SHS_CALCTR_CALMAX_Msk); + shs_ptr->CALCTR |= ((uint32_t)max_calibration_time << SHS_CALCTR_CALMAX_Pos); +} + + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num The Group number for which the configurations applies + * @return None + * + * \parDescription:
+ * Enable the Gain and offset calibration.
\n + * Enable the gain and offset calibration for all the Sample and hold units. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations()
. + */ +void XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num The Group number for which the configurations applies + * @return None + * + * \parDescription:
+ * Disable the Gain and offset calibration.
\n + * Disable the gain and offset calibration for all the Sample and hold units. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations()
. + */ +void XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num The Group number for which the configurations applies + * @param gain_level The gain level whose calibration value has to read. + * @return None + * + * \parDescription:
+ * Read the calibration value for the selected gain level.
\n + * Each gain value has a offset calibration value, this API would return the offset calibration value of the + * selected gain level. This is applicable for all the channels in the group that use the particular gain level. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue()
. + */ +uint8_t XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num The Group number for which the configurations applies + * @param gain_level The gain level whose calibration value has to read. + * @param offset_calibration_value The offset calibration value to be set. + * @return None + * + * \parDescription:
+ * Set the calibration value for the selected gain level.
\n + * Each gain value has a offset calibration value, this API would set the offset value of the selected gain level. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue()
. + */ +void XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level, + uint8_t offset_calibration_value); +#endif + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num The Group number for which the configurations applies + * @param loop_select The delta sigma loop number for which the configurations applies + * @param ch_num Channel number for which the configurations applies + * @return None + * + * \parDescription:
+ * Configures the delta sigma loop of the SHS.
\n + * There are 2 Delta-Sigma loops that can be configured. This API would configure the loop (loop_select) + * with the appropriate group_num and channel_num. + * Configures the SHS_LOOP bit fields. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop()
. + */ +void XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_LOOP_CH_t loop_select, + uint8_t ch_num); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param loop_select The delta sigma loop number for which the configurations applies + * @return None + * + * \parDescription:
+ * Enable the selected Delta-Sigma loop.
\n + * Configures the SHS_LOOP.LPENx bit field. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop()
. + * XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations()
. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_SHS_LOOP_CH_t loop_select) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop:Wrong Delta sigma loop selected", + (loop_select == XMC_VADC_SHS_LOOP_CH_0)||(loop_select == XMC_VADC_SHS_LOOP_CH_1)) + + shs_ptr->LOOP |= (uint32_t)SHS_LOOP_LPEN0_Msk << (uint32_t)loop_select; +} + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param loop_select The delta sigma loop number for which the configurations applies + * @return None + * + * \parDescription:
+ * Disable the selected delta sigma loop.
\n + * Configures the SHS_LOOP.LPENx bit field. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop()
. + * XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations()
. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_SHS_DisableSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_SHS_LOOP_CH_t loop_select) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableSigmaDeltaLoop:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableSigmaDeltaLoop:Wrong Delta sigma loop selected", + (loop_select == XMC_VADC_SHS_LOOP_CH_0)||(loop_select == XMC_VADC_SHS_LOOP_CH_1)) + + shs_ptr->LOOP &= ~((uint32_t)SHS_LOOP_LPEN0_Msk << (uint32_t)loop_select); + +} + +#endif +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +/** + * + * @param group_ptr Constant pointer to the VADC group. + * @param config Pointer to the initialization data structure + * + * @return None + * + * \parDescription:
+ * Initializes the VADC group module with the associated configuration structure pointed by \a config.\n\n It + * initializes the group specified as part of the \a group_ptr. It initializes group conversion class, arbiter + * configuration , boundary configuration by setting GxICLASS,GxARBCFG,GxBOUND, registers. It also + * configures the EMUX control register if applicable. Refer related API's to change the configurations later in the + * program. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_InputClassInit()
+ * XMC_VADC_GROUP_SetPowerMode()
+ * XMC_VADC_GROUP_SetBoundaries()
+ * XMC_VADC_GROUP_ExternalMuxControlInit()
+ */ +void XMC_VADC_GROUP_Init(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_CONFIG_t *config); + +/** + * + * @param group_ptr Constant pointer to the VADC group. + * @param config group related conversion class parameter structure + * @param conv_type Use direct channels or EMUX channels. Refer @ref XMC_VADC_GROUP_CONV_t enum + * @param set_num Conversion class set
+ * Range[0x0, 0x1] + * + * @return None + * + * \parDescription:
+ * Sets up the conversion settings for vadc group resource associated with \a config structure. It configures the + * conversion class properties like sampling time and resolution for selected \a conv_type channels. It initializes + * the G_ICLASS register specified by \a set_num with the required settings. + * + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_Init() + * + */ +void XMC_VADC_GROUP_InputClassInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_CLASS_t config, + const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num); + +/** + * + * @param group_ptr Constant pointer to the VADC Group which must be set as a slave + * @param master_grp The master group number
+ * Range: [0x0 - 0x3] + * @param slave_group The slave group number
+ * Range: [0x0 - 0x3] + * + * @return None + * + * \parDescription:
+ * Configures a VADC Group as a slave group.\n\n Conversion of identically numbered channels across groups can be + * synchronized. For example, when the trigger to convert CH-1 of Group-2 is received, it is possible to + * simultaneously request conversion of CH-1 of Group-0 and Group-3. Group-2 in this example is therefore the + * master group while Groups-0 and 3 are the slave groups. It uses the SYNCCTR register for the configuration settings. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_SetSyncMaster()
+ * XMC_VADC_GROUP_CheckSlaveReadiness()
+ * XMC_VADC_GROUP_EnableChannelSyncRequest()
+ * + */ +void XMC_VADC_GROUP_SetSyncSlave(XMC_VADC_GROUP_t *const group_ptr, uint32_t master_grp, uint32_t slave_group); + +/** + * + * @param group_ptr Constant pointer to the VADC Group. + * @param power_mode Desired power mode + * + * @return None + * + * \parDescription:
+ * Configures the power mode of a VADC group.\n\n For a VADC group to actually convert an analog signal, its analog + * converter must be turned on. + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GROUP_SetPowerMode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_POWERMODE_t power_mode); + +/** + * + * @param group_ptr Constant pointer to the VADC group. + * + * @return None + * + * \parDescription:
+ * Configures a VADC Group as a master group.
\n + * Conversion of identically numbered channels across groups can be + * synchronized. For example, when the trigger to convert CH-1 of Group-2 is received, it is possible to simultaneously + * request conversion of CH-1 of Group-0 and Group-3. Group-2 in this example is therefore the master group while + * Groups-0 and 3 are the slave groups. + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GROUP_SetSyncMaster(XMC_VADC_GROUP_t *const group_ptr); + +/** + + * @param group_ptr Pointer to the master VADC Group + * @param slave_group The slave VADC Group number + *
Range: [0x0 to 0x3] + * @return None + * + * \parDescription:
+ * Configures the ready signal for master group.
\n + * This API would read the \b slave_group number and determine which EVAL configuration to apply for the given master + * slave set. Checks the readiness of slaves in synchronized conversions. Conversion of identically numbered channels + * across groups can be synchronized. For example, when the trigger to convert CH-1 of Group-2 is received, it is + * possible to simultaneously request conversion of CH-1 of Group-0 and Group-3. Group-2 in this example is + * therefore the master group while Groups-0 and 3 are the slave groups. Before the master can request its slaves + * for synchronized conversion, it has the option of checking the readiness of the slaves. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_IgnoreSlaveReadiness()
XMC_VADC_GROUP_SetSyncMaster() + */ +void XMC_VADC_GROUP_CheckSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group); + +/** + * + * @param group_ptr Constant Pointer to the master VADC Group + * @param slave_group The slave VADC Group number + * @return None + * + * \parDescription:
+ * Clears the ready signal for master group.
\n + * Ignores the readiness of slaves in synchronized conversions.This API would read the \b slave_group number and + * determine which EVAL configuration to apply for the given master slave set. Then clears the configuration if present. + * This API is called when the master should issue the conversion request without waiting for the slave to + * assert a ready signal. The ready signal is asserted by the slave group(s) when the conversion is completed + * in these channels. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_CheckSlaveReadiness()
XMC_VADC_GROUP_SetSyncMaster()
+ */ +void XMC_VADC_GROUP_IgnoreSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group); + +/** + * + * @param group_ptr Constant Pointer to the VADC Group waiting for ready signal + * @param eval_waiting_group The VADC Group which expects a ready signal to start it's conversion. + * @param eval_origin_group The VADC Group from which the eval_waiting_group will expect a ready signal + * @return None + * + * \parDescription:
+ * Sets the ready signal in the eval_waiting_group .
\n + * For Synchronized conversion all the slaves participating need to configure the ready signal. + * A slave group will also need to configure the ready signals coming from the other slave groups. + * A call to this API would configure the Sync.slave's EVAL Bits (GxSYNCTR.EVALy). + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_CheckSlaveReadiness()
XMC_VADC_GROUP_IgnoreSlaveReadiness()
+ */ +void XMC_VADC_GROUP_SetSyncSlaveReadySignal(XMC_VADC_GROUP_t *const group_ptr, + uint32_t eval_waiting_group, + uint32_t eval_origin_group); + +/** + * + * @param group_ptr Constant Pointer to the VADC Group + * @return + * uint32_t EVAL bits for the group + * + * \parDescription:
+ * Get the Eval bits of the group.
\n + * For Synchronized conversion the master's ready signal configuration must be copied onto the slaves. + * A call to this API would return the Sync EVAL Bits (GxSYNCTR.EVALy) which can be used to set in the slaves. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_CheckSlaveReadiness()
XMC_VADC_GROUP_IgnoreSlaveReadiness()
+ */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetSyncReadySignal(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t eval_mask; + XMC_ASSERT("XMC_VADC_GROUP_GetSyncReadySignal:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + +#if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2U) + eval_mask = VADC_G_SYNCTR_EVALR1_Msk | VADC_G_SYNCTR_EVALR2_Msk | VADC_G_SYNCTR_EVALR3_Msk; +#else + eval_mask = VADC_G_SYNCTR_EVALR1_Msk; +#endif + return( group_ptr->SYNCTR & eval_mask); +} + +/** + * @param group_ptr Constant Pointer to the VADC Group + * @param eval_mask mask to configure the eval bits + * Use XMC_VADC_SYNCTR_EVAL_t to create the mask. + * @return None + * + * \parDescription:
+ * Set the Eval bits of the group.
\n + * For Synchronized conversion the master's ready signal configuration must be copied onto the slaves. + * A call to this API would configure the Sync EVAL Bits (GxSYNCTR.EVALy). + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_CheckSlaveReadiness()
XMC_VADC_GROUP_IgnoreSlaveReadiness()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_SetSyncReadySignal(XMC_VADC_GROUP_t *const group_ptr, uint32_t mask) +{ + uint32_t eval_mask; + XMC_ASSERT("XMC_VADC_GROUP_SetSyncReadySignal:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + +#if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2U) + eval_mask = VADC_G_SYNCTR_EVALR1_Msk | VADC_G_SYNCTR_EVALR2_Msk | VADC_G_SYNCTR_EVALR3_Msk; +#else + eval_mask = VADC_G_SYNCTR_EVALR1_Msk; +#endif + group_ptr->SYNCTR &= ~(eval_mask); + group_ptr->SYNCTR |= mask; +} + +/** + * + * @param group_ptr Constant pointer to the master VADC Group + * @param ch_num Channel whose conversion triggers conversion in slave groups + * @return None + * + * \parDescription:
+ * Sets up a channel for synchronized conversion.\n\n Conversion of identically numbered channels across groups + * can be synchronized. For example, when the trigger to + * convert CH-1 of Group-2 is received, it is possible to simultaneously request conversion of CH-1 of Group-0 and + * Group-3. Group-2 in this example is therefore the master group while Groups-0 and 3 are the slave groups.
+ * Before the master can request its slaves for synchronized conversion, it has the option of checking the readiness + * of the slaves. + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GROUP_EnableChannelSyncRequest(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num); + +/** + * + * @param group_ptr Pointer to the master VADC Group + * @param ch_num Channel whose conversion triggers conversion in slave groups + * @return None + * + * \parDescription:
+ * Disable the synchronization request for the particular channel specified as ch_num. To enable the synchronization + * call the API @ref XMC_VADC_GROUP_EnableChannelSyncRequest(). + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GROUP_DisableChannelSyncRequest(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num); + +/** + * + * @param group_ptr Constant pointer to the VADC group. + * + * @return retuns IDLE if converter is free else returns busy. Refer @ref XMC_VADC_GROUP_STATE_t enum + * + * \parDescription:
+ * Checks the live status of the analog to digital converter. The converter can either idle doing nothing or busy + * sampling + converting. + * + * \parRelated APIs:
+ * None + */ +XMC_VADC_GROUP_STATE_t XMC_VADC_GROUP_IsConverterBusy(XMC_VADC_GROUP_t *const group_ptr); + +/** + * + * @param group_ptr Constant pointer to the VADC group whose global boundary registers are to be programmed + * @param boundary0 Boundary-0 Value
+ * Range: [0x0 - 0x0FFF] + * @param boundary1 Boundary-1 Value
+ * Range: [0x0 - 0x0FFF] + * + * @return None + * + * \parDescription:
+ * Programs the boundaries with \a boundary0 and boundary1 for result comparison.\n\n These two boundaries can serve as + * absolute boundaries. They defines a range against which the result of a conversion can be compared. In the + * fast compare mode, the two boundaries provide hysteresis capability to a compare value. In any case, these boundary + * values entered here form a boundary pallete. There are dedicated upper and lower boundary registers G_BOUND0 and + * G_BOUND1 who will derive their values from this palette. + * + * \parRelated APIs:
+ * None + * + */ +void XMC_VADC_GROUP_SetBoundaries(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t boundary0, + const uint32_t boundary1); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param selection The boundary value selected for \b boundary_value. + * @param boundary_value Select the boundary value. + * @return + * None + * + * \parDescription:
+ * Programs the boundary with \a boundary_value for result comparison.\n\n This defines a range against which + * the result of a conversion can be compared. In the fast compare mode, the two boundaries provide hysteresis + * capability to a compare value. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_SetIndividualBoundary(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param sr_num The service request number (0 through 3) + * @param type IRQ type (Kernel specific interrupt vs Module wide shared interrupt ) + * @return None + * + * \parDescription:
+ * Activates a Service Request line(manually trigger).
\n + * VADC provides few SR lines for each group and a few more which is shared across all the groups. + * These SR lines can be connected to an NVIC node which in-turn would generate an interrupt. + * This API would manually trigger the given SR line. Could be used for evaluation and testing purposes. + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GROUP_TriggerServiceRequest(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t sr_num, + const XMC_VADC_GROUP_IRQ_t type); + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param emux_cfg EMUX configuration structure + * @return None + * + * \parDescription:
+ * Configures group EMUX parameters associated with the \a emux_cfg configuration structure.\n\n An external emux + * interface allows additional channels to be connected to a VADC group. The conversion properties + * of such channels can be different from the standard channels which are directly connected to the VADC group. + * This API configures conversion properties of channels connected via EMUX interface. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_VADC_GROUP_ExternalMuxControlInit(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_GROUP_EMUXCFG_t emux_cfg) +{ + uint32_t emux_config; + + XMC_ASSERT("XMC_VADC_GROUP_ExternalMuxControlInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + emux_config = ((uint32_t)emux_cfg.starting_external_channel << (uint32_t)VADC_G_EMUXCTR_EMUXSET_Pos) | + ((uint32_t)emux_cfg.connected_channel << (uint32_t)VADC_G_EMUXCTR_EMUXCH_Pos); + + group_ptr->EMUXCTR = emux_config; + emux_config = ((uint32_t)emux_cfg.emux_coding << (uint32_t)VADC_G_EMUXCTR_EMXCOD_Pos) | + ((uint32_t)emux_cfg.emux_mode << (uint32_t)VADC_G_EMUXCTR_EMUXMODE_Pos)| + ((uint32_t)emux_cfg.stce_usage << (uint32_t)VADC_G_EMUXCTR_EMXST_Pos); + +#if (XMC_VADC_EMUX_CH_SEL_STYLE == 1U) + emux_config |= ((uint32_t)emux_cfg.emux_channel_select_style << (uint32_t)VADC_G_EMUXCTR_EMXCSS_Pos); +#endif + group_ptr->EMUXCTR |= (emux_config | ((uint32_t)VADC_G_EMUXCTR_EMXWC_Msk)) ; +} + +#if XMC_VADC_BOUNDARY_FLAG_SELECT == 1U + +/** + * @param group_ptr Constant pointer to the VADC group + * @param boundary_flag_num The Boundary flag for which the interrupt node needs to be configured. + * Range: [0x0 to 0x3] + * @param node Service Request node Id + * @return + * None + * + * \parDescription:
+ * Connects the boundary event to the SR line of VADC or to a common boundary flag.
\n + * This API will connect a Service Request line(SR) to a boundary event. Hence to get a interrupt on this + * Service request line one has to enable the required NVIC node. A call to this API would configure the register bit + * field GxBFLNP.BFLxNP. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_SetBoundaryEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint8_t boundary_flag_num, + const XMC_VADC_BOUNDARY_NODE_t node); +#endif + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * uint32_t The complete GxALIAS register + * + * \parDescription:
+ * Returns the ALIAS values.\n The ALIAS value that is configured for Channel-0 and channel-1 are returned. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetAlias(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_GetAliasWrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return (group_ptr->ALIAS); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param conv_class conversion property to be extracted + * @return + * XMC_VADC_GROUP_CLASS_t The complete GxICLASSy register + * + * \parDescription:
+ * Returns the input class configuration values.\n + * This returns the sampling time configuration and resolution configured in the appropriate group input class + * \b conv_class. A call to this API would return the register GxICLASSy. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_VADC_GROUP_CLASS_t XMC_VADC_GROUP_GetInputClass(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_CHANNEL_CONV_t conv_class) +{ + XMC_VADC_GROUP_CLASS_t input_value; + XMC_ASSERT("XMC_VADC_GROUP_GetInputClass:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetInputClass:Wrong conv_class selected", + (XMC_VADC_CHANNEL_CONV_GROUP_CLASS0 == conv_class) || (XMC_VADC_CHANNEL_CONV_GROUP_CLASS1 == conv_class)) + + input_value.g_iclass0 = (uint32_t) 0xFFFFFFFF; + if ((XMC_VADC_CHANNEL_CONV_GROUP_CLASS0 == conv_class) || (XMC_VADC_CHANNEL_CONV_GROUP_CLASS1 == conv_class)) + { + input_value.g_iclass0 = group_ptr->ICLASS[(uint32_t)conv_class]; + } + + return (input_value); +} +#endif + +#if (XMC_VADC_GSCAN_AVAILABLE == 1U) +/** + * @param group_ptr Pointer to the VADC group + * @param config Pointer to Scan configuration + * @return None + * + * \parDescription:
+ * Initializes the VADC SCAN functional block.
\n + * The GROUP SCAN request source functional block converts channels sequentially starting with the highest numbered + * channel to the lowest. Channels must register themselves as being part of the the scan sequence. + * A call to this API will first disable the arbitration slot for queue (XMC_VADC_GROUP_ScanEnableArbitrationSlot()) + * and then it would configure all the related registers with the required configuration values. + * The arbitration slot is re-enabled at the end of init by invoking XMC_VADC_GROUP_ScanDisableArbitrationSlot(). + * A call to this API would configure the registers GxARBPR, GxASCTRL, GxASMR needed scan request source. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableArbitrationSlot()
XMC_VADC_GROUP_ScanDisableArbitrationSlot()
+ * XMC_VADC_GROUP_ScanSelectTrigger()
XMC_VADC_GROUP_ScanSelectGating()
+ */ +void XMC_VADC_GROUP_ScanInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SCAN_CONFIG_t *config); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables arbitration slot of the scan request source.
\n + * If the scan request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the scan channel can only be converted when the arbiter comes + * to the scan slot. Thus this must be enabled if any conversion need to take place. + * A call to this API would configure the register bit field GxARBPR.ASEN1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanDisableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanEnableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanEnableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ARBPR |= (uint32_t)VADC_G_ARBPR_ASEN1_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables arbitration slot of the scan request source.
\n + * If the scan request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the scan channel can only be converted when the arbiter comes + * to the scan slot.A call to this API will lead to all conversions request by scan to be blocked. + * A call to this API would configure the register bit field GxARBPR.ASEN1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanDisableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanDisableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ARBPR &= ~((uint32_t)VADC_G_ARBPR_ASEN1_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * bool returns true if the arbitration is enabled else returns false. + * + * \parDescription:
+ * Returns the arbitration status of the scan request source.
\n + * If the scan request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the scan channel can only be converted when the arbiter comes + * to the scan slot. A call to this API would return the status of the arbitration slot of scan. + * A call to this API would read the register bit field GxARBPR.ASEN1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableArbitrationSlot(),
XMC_VADC_GROUP_ScanDisableArbitrationSlot()
+ */ +__STATIC_INLINE bool XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + return ((group_ptr->ARBPR & (uint32_t)VADC_G_ARBPR_ASEN1_Msk) >> VADC_G_ARBPR_ASEN1_Pos); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param trigger_input Choice of the input earmarked as a trigger line + * @return + * None + * + * \parDescription:
+ * Select Trigger signal for scan request source.
\n + * A scan request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 16 input lines as a trigger line. This is + * needed when a hardware trigger is needed for the conversion of the scan request source. + * Refer to the reference manual to determine the signal that needs to be connected. + * A call to this API would configure the register bit field GxASCTRL.XTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanSelectGating()
XMC_VADC_GROUP_ScanEnableExternalTrigger()
+ */ +void XMC_VADC_GROUP_ScanSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_TRIGGER_INPUT_SELECT_t trigger_input); + + +/** + * @param group_ptr Constant pointer to the VADC group + * @param trigger_edge Trigger edge selection + * @return + * None + * + * \parDescription:
+ * Selects the trigger edge for scan request source.
\n + * A scan request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 4 possible trigger edges. This is + * needed when a hardware trigger is needed for the conversion of the scan request source. + * A call to this API would configure the register bit field GxASCTRL.XTMODE. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanSelectTrigger()
+ */ +void XMC_VADC_GROUP_ScanSelectTriggerEdge(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_TRIGGER_EDGE_t trigger_edge); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param gating_input Module input signal meant to be selected as gating input + * @return + * None + * + * \parDescription:
+ * Select Gating signal for scan request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. Any one of the 16 input + * lines can be chosen as a gating signal. Trigger signal can be given to the scan request source only + * when the gating signal's active level is detected. Additionally the GxASMR.ENGT has to be configured for + * the gating signal's active level. A call to this API would configure the register bit field GxASCTRL.GTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanSelectTrigger()
+ */ +void XMC_VADC_GROUP_ScanSelectGating(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_GATE_INPUT_SELECT_t gating_input); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param mode_sel Select how the gating is applied to the scan request source + * @return + * None + * + * \parDescription:
+ * Selects the gating mode of scan request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. + * This API determines how the gating signal behaves, either active low or active high. + * If gating signal needs to ignored XMC_VADC_GATEMODE_IGNORE should be used as the \a mode_sel. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanSelectGating(); + */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanSetGatingMode(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_GATEMODE_t mode_sel) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanSetGatingMode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSetGatingMode:Wrong mode selected", (mode_sel <= XMC_VADC_GATEMODE_ACTIVELOW)) + + /* Clear the existing gate configuration */ + group_ptr->ASMR &= (uint32_t) (~((uint32_t)VADC_G_ASMR_ENGT_Msk)); + /* Set the new gating mode */ + group_ptr->ASMR |= (uint32_t)((uint32_t)mode_sel << VADC_G_ASMR_ENGT_Pos); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables continuous conversion mode.
\n + * Typically for a scan request source to generate conversion request, either a hardware trigger or a software + * request is a pre-requisite. Using autoscan feature it is possible to start the conversion once and allow the + * sequence to repeat without any further triggers. Once all channels belonging to a scan request source have + * been converted, a request source completion event is generated. Generation of this event can restart the scan + * sequence. Every request source event will cause a load event to occur. A call to this API would configure + * the register bit field GxASMR.SCAN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanDisableContinuousMode()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanEnableContinuousMode(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanEnableContinuousMode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_SCAN_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables continuous conversion mode.
\n + * Typically for a scan request source to generate conversion request, either a hardware trigger or a software + * request is a pre-requisite. Using autoscan feature it is possible to start the conversion once and allow the + * sequence to repeat without any further triggers. Once all channels belonging to a scan request source have + * been converted, a request source completion event is generated. Generation of this event can restart the scan + * sequence. By invoking this feature the Autoscan mode of operations is disabled. A call to this API would configure + * the register bit field GxASMR.SCAN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableContinuousMode()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanDisableContinuousMode(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanDisableContinuousMode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_SCAN_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Generates conversion request (Software initiated conversion).
\n + * A conversion request can be raised either upon detection of a hardware trigger, or by software. This API forces + * the scan unit to generate a conversion request to the analog converter. It is assumed that the scan has already + * been filled up with entries. A call to this API would configure the register bit field GxASMR.LDEV. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanTriggerConversion(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanTriggerConversion:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_LDEV_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Aborts an ongoing scan sequence conversion.
\n + * An ongoing sequence can be aborted at any time. The scan unit picks the pending channels one by one from a + * pending register and requests for their conversion. This API essentially clears the channel pending register thus + * creating an illusion that there are no more channels left in the sequence. + * A call to this API would configure the registers GxASMR, GxASCTRL, GxARBPR to achieve the sequence abort. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ScanSequenceAbort(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num The channel meant to be added to scan sequence + *
Range: [0x0 to 0x7] + * @return + * None + * + * \parDescription:
+ * Adds a channel to the scan sequence.
\n + * Call this API to insert a new single channel into the scan request source. This will be added to the scan + * sequence. The added channel will be part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of GxASSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanAddMultipleChannels()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanAddChannelToSequence(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + XMC_ASSERT("VADC_GSCAN_AddSingleChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanAddChannelToSequence:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + group_ptr->ASSEL |= (uint32_t)((uint32_t)1 << ch_num); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_mask Mask word indicating channels which form part of scan conversion sequence + * Bit location 0/1/2/3/4/5/6/7 represents channels-0/1/2/3/4/5/6/7 respectively. + * To Add the channel to the scan sequence enable the respective bit. + * Passing a 0x0 will clear all the selected channels + *
Range: [0x0 to 0xFF] + * @return + * None + * + * \parDescription:
+ * Adds multiple channels to the scan sequence.
\n + * Call this API to insert a multiple channels into the scan request source. This will be added to a scan + * sequence. The added channels will be a part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of GxASSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanAddChannelToSequence()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanAddMultipleChannels(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_mask) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanAddMultipleChannels:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ASSEL = ch_mask; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num The channel being audited for completion of conversion + *
Range: [0x0 to 0x7] + * @return + * bool returns true if the channel is pending conversion else returns false + * + * \parDescription:
+ * Determine if the channel is pending for conversion.
\n + * This API will check if the Channel in question is awaiting conversion in the current arbitration round. + * When a load event occurs the scan sequence is pushed to a pending conversion register. + * From the pending register the channels are taken up by the converter. This API would return true + * if the channel is found in the pending register (GxASPND). + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanGetNumChannelsPending()
+ */ +__STATIC_INLINE bool XMC_VADC_GROUP_ScanIsChannelPending(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + + XMC_ASSERT("XMC_VADC_GROUP_ScanIsChannelPending:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanIsChannelPending:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + return( (bool)((uint32_t)(group_ptr->ASPND >> ch_num) & 1U)); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return
+ * uint32_t Returns the total channels pending for conversion. + *
Range: [0x0 to 0x8] + * + * \parDescription:
+ * Returns the total number of pending channels.
\n + * This API will read the pending channels register and will return the number of channels that are awaiting conversion. + * When a load event occurs the scan sequence is pushed to a pending conversion register. + * From the pending register the channels are taken up by the converter. When the API is called it would + * return the total number of channels pending (GxASPND). + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanIsChannelPending()
+ */ +uint32_t XMC_VADC_GROUP_ScanGetNumChannelsPending(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Manually asserts the conversion complete request source event.
\n + * This API will set the request source event for scan. This will trigger a interrupt if the + * service node pointer for the scan has been configured. + * A call to this API would configure the register bit field GxSEFLAG.SEV1. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanTriggerReqSrcEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanTriggerReqSrcEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->SEFLAG |= (uint32_t)VADC_G_SEFLAG_SEV1_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Acknowledges the scan conversion complete request source event.
\n + * This API will clear the request source event that occurred. This will clear a interrupt if it was raised. + * A call to this API would configure the register bit field GxSEFLAG.SEV1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanTriggerReqSrcEvent()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanClearReqSrcEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanClearReqSrcEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->SEFCLR |= (uint32_t)VADC_G_SEFCLR_SEV1_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * bool returns true if the service request event is raised. + * returns false if the service request event was not raised. + * + * \parDescription:
+ * Determines if the request source event is asserted.
+ * This API will get the status of the scan request source event. Will return a true + * if the event has occurred for scan. A call to this API would access the register bit field GxSEFLAG.SEV1. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE bool XMC_VADC_GROUP_ScanGetReqSrcEventStatus(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GSCAN_GetRSEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return( (bool)(group_ptr->SEFLAG & (uint32_t)VADC_G_SEFLAG_SEV1_Msk)); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param sr Service Request Id + * @return + * None + * + * \parDescription:
+ * Connects the scan request source event to the SR line of VADC.
\n + * This API will connect a Service Request line(SR) to a scan request source event. Hence to get a interrupt on this + * Service request line one has to enable the required NVIC node. A call to this API would configure the register bit + * field GxSEVNP.SEV1NP . + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SR_t sr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables the trigger for scan request source.
\n + * By using this API, the trigger signal will be activated for the scan request source. The trigger signal and trigger + * edge will be selected from the ASCTRL register. The Selection of a input will be done by + * XMC_VADC_GROUP_ScanSelectTrigger(). A call to this API would configure the register bit field GxASMR.ENTR. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanSelectTrigger()
XMC_VADC_GROUP_ScanDisableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanEnableExternalTrigger(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanEnableExternalTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_ENTR_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables the trigger for scan request source.
+ * By using this API the trigger will be deactivated for the scan request source. + * This will just deactivate the H/W trigger for the scan request source. If any configuration were done + * to select the trigger input in GxASCTRL, it will be not be effected by this API. + * A call to this API would configure the register bit field GxASMR.ENTR. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanDisableExternalTrigger(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanDisableExternalTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_ENTR_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param channel_num channel number to be removed from the scan sequence. + * @return + * None + * + * \parDescription:
+ * Removes a channel from the scan sequence.
+ * By using this API the it is possible to remove a single channel from the conversion sequence. + * The remaining channels will continue however they are. + * A call to this API would configure the register GxASSEL. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ScanRemoveChannel(XMC_VADC_GROUP_t *const group_ptr, const uint32_t channel_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables the scan request source event .
+ * By using this API the request source event will be activated for the scan request source. + * Other configurations w.r.t service node pointer are not done in this API. + * A call to this API would configure the register bit field GxASMR.ENSI. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanDisableEvent(),
XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanEnableEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanEnableEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->ASMR |= ((uint32_t)VADC_G_ASMR_ENSI_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables the scan request source event .
+ * By using this API the request source event will be deactivated for the scan request source. + * Other configurations w.r.t service node pointer are not done in this API. + * A call to this API would configure the register bit field GxASMR.ENSI. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableEvent(),
XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanDisableEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanDisableEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_ENSI_Msk); +} +#endif + +/** + * @param global_ptr Pointer to the VADC module + * @param config Pointer to initialization data structure + * + * \parDescription:
+ * Initializes the Background scan functional block.
\n + * The BACKGROUND SCAN request source functional block converts channels of all VADC groups that have not + * been assigned as a priority channel (priority channels can be converted only by queue and scan). Background Scan + * request source converts the unprioritized channels. Unprioritized channels however can also be used with queue + * and scan. But a channel which is prioritized can not be used with background request source. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_BackgroundEnableArbitrationSlot()
XMC_VADC_GROUP_BackgroundDisableArbitrationSlot()
+ * XMC_VADC_GLOBAL_BackgroundSelectTrigger()
XMC_VADC_GLOBAL_BackgroundSelectGating()
+ */ +void XMC_VADC_GLOBAL_BackgroundInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_BACKGROUND_CONFIG_t *config); + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +/** + * @param group_ptr Constant pointer to the VADC group which may receive a + * conversion request from background request source + * + * @return + * None + * + * \parDescription:
+ * Enables arbitration slot of the Background request source.
\n + * If the Background request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the Background channel can only be converted when the arbiter + * comes to the Background slot. Thus this must be enabled if any conversion need to take place. + * A call to this API would configure the register bit field GxARBPR.ASEN2. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_BackgroundDisableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_BackgroundEnableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_BackgroundEnableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ARBPR |= (uint32_t)VADC_G_ARBPR_ASEN2_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group which may receive a conversion request + * from background request source + * @return + * None + * + * \parDescription:
+ * Disables arbitration slot of the Background request source.
\n + * If the Background request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the Background channel can only be converted when the arbiter + * comes to the Background slot.A call to this API will lead to all conversions request by Background to be blocked. + * A call to this API would configure the register bit field GxARBPR.ASEN2 + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_BackgroundEnableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_BackgroundDisableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_BackgroundDisableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ARBPR &= ~((uint32_t)VADC_G_ARBPR_ASEN2_Msk); +} +#endif + +/** + * @param global_ptr Pointer to the VADC module + * @param input_num Choice of the input earmarked as a trigger line + * Accepts enum ::XMC_VADC_TRIGGER_INPUT_SELECT_t + * @return + * None + * + * \parDescription:
+ * Select Trigger signal for Background request source.
\n + * A Background request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 16 input lines as a trigger line. This is + * needed when a hardware trigger is needed for the conversion of the Background request source. + * Refer to the reference manual to determine the signal that needs to be connected. + * A call to this API would configure the register bit field BRSCTRL.XTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSelectGating()
XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger()
+ */ +void XMC_VADC_GLOBAL_BackgroundSelectTrigger(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t input_num); + + +/** + * @param global_ptr Pointer to the VADC module + * @param trigger_edge Select the trigger edge + * @return + * None + * + * \parDescription:
+ * Select Trigger edge for Background request source.
\n + * A Background request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 4 possible values for the trigger edge. This is + * needed when a hardware trigger is needed for the conversion of the Background request source. + * A call to this API would configure the register bit field BRSCTRL.XTMODE. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSelectGating()
XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger()
+ */ +void XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_TRIGGER_EDGE_t trigger_edge); + +/** + * @param global_ptr Pointer to the VADC module + * @param input_num Module input signal meant to be selected as gating input + * Accepts enum ::XMC_VADC_GATE_INPUT_SELECT_t + * @return + * None + * + * \parDescription:
+ * Select Gating signal for Background request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. Any one of the 16 input + * lines can be chosen as a gating signal. Trigger signal can be given to the Background request source only + * when the gating signal's active level is detected. Additionally the GxBRSMR.ENGT has to be configured for + * the gating signal's active level. A call to this API would configure the register bit field BRSCTRL.GTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSelectTrigger()
+ */ +void XMC_VADC_GLOBAL_BackgroundSelectGating(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t input_num); + +/** + * @param global_ptr Pointer to the VADC module + * @param mode_sel Select how the gating is applied to the background scan request source + * @return + * None + * + * Details of function
+ * Selects the gating mode of background request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. + * This API determines how the gating signal behaves, either active low or active high. + * If gating signal needs to ignored XMC_VADC_GATEMODE_IGNORE should be used as the \a mode_sel. + * A call to this API would configure the register bit field BRSMR.ENGT. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSelectGating(); + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundSetGatingMode(XMC_VADC_GLOBAL_t *const global_ptr, + XMC_VADC_GATEMODE_t mode_sel) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSetGatingMode:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSetGatingMode:Wrong mode selected", (mode_sel <= XMC_VADC_GATEMODE_ACTIVELOW)) + + /* Clear the existing gate configuration */ + global_ptr->BRSMR &= (uint32_t)(~((uint32_t)VADC_BRSMR_ENGT_Msk)); + /* Configure the new gating mode*/ + global_ptr->BRSMR |= (uint32_t)((uint32_t)mode_sel << VADC_BRSMR_ENGT_Pos); +} + + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Enables continuous conversion mode.
\n + * Typically for a Background request source to generate conversion request, either a hardware trigger or a software + * request is needed. Using autoscan (continuous conversion)feature it is possible to start the conversion + * once and allow the sequence to repeat without any further triggers. Once all channels belonging to a Background + * request source have been converted, a request source completion event is generated. Generation of this event + * can restart the Background configure sequence. Every request source event will cause a load event to occur. + * A call to this API would access the register bit field BRSMR.SCAN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_BackgroundDisableContinuousMode()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundEnableContinuousMode(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundEnableContinuousMode:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_SCAN_Msk; +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Disables continuous conversion mode.
\n + * Typically for a Background request source to generate conversion request, either a hardware trigger or a software + * request is a pre-requisite. Using autoscan feature it is possible to start the conversion once and allow the + * sequence to repeat without any further triggers. Once all channels belonging to a Background request source have + * been converted, a request source completion event is generated. Generation of this event can restart the Background + * sequence. By invoking this API the Autoscan mode of operations is disabled. A call to this API would configure the + * register bit field BRSMR.SCAN. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundEnableContinuousMode()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundDisableContinuousMode(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundDisableContinuousMode:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->BRSMR &= ~((uint32_t)VADC_BRSMR_SCAN_Msk); +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Generates conversion request (Software initiated conversion).
\n + * A conversion request can be raised either upon detection of a hardware trigger, or by software. This API forces + * the scan unit to generate a conversion request to the analog converter. It is assumed that the background scan + * has already been filled up with entries. A call to this API would set the register bit field BRSMR.LDEV. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundTriggerConversion(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundTriggerConversion:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_LDEV_Msk; +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Aborts an ongoing background scan conversion(sequence).
\n + * An ongoing sequence can be aborted at any time. The scan unit picks the pending channels one by one from a + * pending register and requests for their conversion. This API essentially clears the channel pending register thus + * creating an illusion that there are no more channels left in the sequence. + * A call to this API would configure the registers BRSMR, BRSCTRL, GxARBPR(if group is available) to abort the + * current scan sequence. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GLOBAL_BackgroundAbortSequence(XMC_VADC_GLOBAL_t *const global_ptr); + +/** + * @param global_ptr Pointer to the VADC module + * @param grp_num ID of the VADC group whose unprioritized channels have been assigned to background scan + * Request source + * @param ch_num The unprioritized channel meant to be added to the scan sequence + *
Range: [0x0 to 0x7] + * @return + * None + * + * \parDescription:
+ * Adds a channel to the background scan sequence.
\n + * Call this API to insert a new single channel into the background scan request source. This will be added to the scan + * sequence. The added channel will be part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of BRSSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundAddMultipleChannels()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundAddChannelToSequence(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t grp_num, + const uint32_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Group Number",((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + global_ptr->BRSSEL[grp_num] |= (uint32_t)((uint32_t)1 << ch_num); +} + +/** + * @param global_ptr Pointer to the VADC module + * @param grp_num ID of the VADC group whose unprioritized channels have been assigned to background scan + * @param ch_mask Mask word indicating channels which form part of scan conversion sequence + * Bit location 0/1/2/3/4/5/6/7 represents channels-0/1/2/3/4/5/6/7 respectively. + * To Add the channel to the scan sequence enable the respective bit. + * Passing a 0x0 will clear all the previously selected channels + *
Range: [0x0 to 0xFF] + * @return + * None + * + * \parDescription:
+ * Adds multiple channels to the scan sequence.
\n + * Call this API to insert a multiple channels into the scan request source. This will be added to a scan + * sequence. The added channels will be a part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of BRSSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgndAddMultipleChannels(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t grp_num, + const uint32_t ch_mask) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Group Number", ((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + global_ptr->BRSSEL[grp_num] |= ch_mask; +} + +/** + * @param global_ptr Pointer to the VADC module + * @param grp_num ID of the VADC group whose unprioritized channels have been assigned to background scan + * Request source + * @param ch_num The unprioritized channel meant to be added to the scan sequence + *
Range: [0x0 to 0x7] + * @return + * None + * + * \parDescription:
+ * Removes a channel to the background scan sequence.
\n + * Call this API to insert a new single channel into the background scan request source. This will be added to the scan + * sequence. The added channel will be part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of BRSSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t grp_num, + const uint32_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Group Number",((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + global_ptr->BRSSEL[grp_num] &= (uint32_t)~((uint32_t)1 << ch_num); +} + +/** + * @param global_ptr Pointer to the VADC module + * @param grp_num ID of the VADC group whose unprioritized channels have been assigned to background scan + * @param ch_mask Mask word indicating channels which form part of scan conversion sequence + * Bit location 0/1/2/3/4/5/6/7 represents channels-0/1/2/3/4/5/6/7 respectively. + * To Add the channel to the scan sequence enable the respective bit. + * Passing a 0x0 will clear all the previously selected channels + *
Range: [0x0 to 0xFF] + * @return + * None + * + * \parDescription:
+ * Removes multiple channels to the scan sequence.
\n + * Call this API to insert a multiple channels into the scan request source. This will be added to a scan + * sequence. The added channels will be a part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of BRSSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t grp_num, + const uint32_t ch_mask) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Group Number", ((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + global_ptr->BRSSEL[grp_num] &= (uint32_t)~ch_mask; +} + +/** + * @param global_ptr Pointer to the VADC module + * @param grp_num ID of the VADC group whose unprioritized channels have been assigned to background scan RS + * @param ch_num The channel being audited for completion of conversion + *
Range: [0x0 to 0x7] + * @return + * bool returns true if the channel is pending conversion else returns false + * + * \parDescription:
+ * Determine if the channel is pending.
\n + * This API will check if the Channel in question is awaiting conversion in the current arbitration round. + * When a load event occurs the scan sequence is pushed to a pending conversion register. + * From the pending register the channels are taken up by the converter. This API would return true + * if the channel is found in the pending register (BRSPND[\b grp_num]). + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending()
+ */ +__STATIC_INLINE bool XMC_VADC_GLOBAL_BackgroundIsChannelPending(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t grp_num, + const uint32_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundIsChannelPending:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundIsChannelPending:Wrong Group Number", ((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundIsChannelPending:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + return( (bool)(global_ptr->BRSPND[grp_num] & (uint32_t)((uint32_t)1 << ch_num))); +} + +/** + * @param global_ptr Pointer to the VADC module + * @return
+ * uint32_t Returns the total channels pending for conversion. + *
Range: [0x0 to (0x8*number of groups)] + * + * \parDescription:
+ * Returns the number of pending channels.
\n + * This API will read the pending channels register and will return the number of channels that are awaiting conversion. + * When a load event occurs the scan sequence is pushed to a pending conversion register. + * From the pending register the channels are taken up by the converter. When the API is called it would + * return the total number of channels pending (BRSPND[\b grp_num]). + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundIsChannelPending()
+ */ +uint32_t XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending(XMC_VADC_GLOBAL_t *const global_ptr); + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Manually asserts the conversion complete request source event.
\n + * This API will set the request source event for background scan. This will trigger a interrupt if the + * service node pointer for the scan has been configured. + * A call to this API would configure the register bit field GLOBEFLAG.SEVGLB. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundTriggerReqSrcEvent(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundTriggerReqSrcEvent:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->GLOBEFLAG |= (uint32_t)VADC_GLOBEFLAG_SEVGLB_Msk; +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Acknowledges the background scan conversion complete request source event.
\n + * This API will clear the request source event that occurred. This will clear a interrupt if it was raised. + * A call to this API would configure the register bit field GLOBEFLAG.SEVGLB + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundTriggerReqSrcEvent()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundClearReqSrcEvent(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundClearReqSrcEvent:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->GLOBEFLAG |= (uint32_t)VADC_GLOBEFLAG_SEVGLBCLR_Msk; +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * bool returns true if the service request event is raised. + * returns false if the service request event was not raised. + * + * \parDescription:
+ * Determines if the request source event is asserted.
+ * This API will get the status of the background scan request source event. Will return a true + * if the event has occurred for background scan. A call to this API would configure the register + * bit field GLOBEFLAG.SEVGLB. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE bool XMC_VADC_GLOBAL_BackgroundGetReqSrcEventStatus(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundGetReqSrcEventStatus:Wrong Module Pointer", (global_ptr == VADC)) + return((bool)(global_ptr->GLOBEFLAG & (uint32_t)VADC_GLOBEFLAG_SEVGLB_Msk)); +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Enables the trigger for background scan request source.
\n + * By using this API the trigger will be activated for the scan request source. The trigger signal and trigger + * edge will be selected from the BRSCTRL register. The Selection of a input will be done by + * XMC_VADC_GLOBAL_BackgroundSelectTrigger(). A call to this API would configure the register bit field BRSMR.ENTR. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSelectTrigger()
XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_ENTR_Msk; +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Disables the trigger for background scan request source.
+ * By using this API the trigger will be deactivated for the background scan request source. + * This will just deactivate the H/W trigger for the background scan request source. If any configuration was done + * to select the trigger input in BRSCTRL will be not be effected. A call to this API would configure the register + * bit field BRSMR.ENTR. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->BRSMR &= ~((uint32_t)VADC_BRSMR_ENTR_Msk); +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Enables the background scan request source event .
+ * By using this API the request source event will be activated for the background scan request source. + * Other configurations w.r.t service node pointer are not done in this API. + * A call to this API would configure the register bit field BRSMR.ENSI. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundEnableEvent(),
XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundEnableEvent(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundEnableEvent:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->BRSMR |= ((uint32_t)VADC_BRSMR_ENSI_Msk); +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Disables the background scan request source event .
+ * By using this API the request source event will be deactivated for the background scan request source. + * Other configurations w.r.t service node pointer are not done in this API. + * A call to this API would configure the register bit field BRSMR.ENSI. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_BackgroundEnableEvent(),
XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundDisableEvent(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundDisableEvent:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->BRSMR &= ~((uint32_t)VADC_BRSMR_ENSI_Msk); +} + +#if (XMC_VADC_QUEUE_AVAILABLE == 1U) +/** + * @param group_ptr Pointer to the VADC group + * @param config Pointer to initialization data structure + * @return + * None + * + * \parDescription:
+ * Initializes VADC QUEUE functional block.
\n + * The QUEUE request source functional block converts channels stored in a queue. The first channel entered into the + * queue is converted first. A channel once converted, can be placed back into the queue if desired(refill). + * A call to this API will first disable the arbitration slot for queue (XMC_VADC_GROUP_QueueEnableArbitrationSlot()) + * and then it would configure all the related registers with the required configuration values. + * The arbitration slot is re-enabled at the end of init by invoking XMC_VADC_GROUP_QueueDisableArbitrationSlot(). + * A call to this API would configure the registers GxARBPR, GxQCTRL0, GxQMR0 to configure the queue request + * source. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueEnableArbitrationSlot()
XMC_VADC_GROUP_QueueDisableArbitrationSlot()
+ * XMC_VADC_GROUP_QueueSelectTrigger()
XMC_VADC_GROUP_QueueSelectGating()
+ */ +void XMC_VADC_GROUP_QueueInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_QUEUE_CONFIG_t *config); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables arbitration slot of the queue request source.
\n + * If the QUEUE request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the queue channel can only be converted when the arbiter comes + * to the queue slot. Thus this must be enabled if any conversion need to take place. + * A call to this API would configure the register bit field GxARBPR.ASEN0. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueDisableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueEnableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueEnableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)); + group_ptr->ARBPR |= (uint32_t)((uint32_t)1 << VADC_G_ARBPR_ASEN0_Pos); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables arbitration slot of the queue request source.
\n + * If the QUEUE request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the queue channel can only be converted when the arbiter comes + * to the queue slot.A call to this API will lead to all conversions request by queue to be blocked. + * A call to this API would configure the register bit field GxARBPR.ASEN0. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueEnableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueDisableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueDisableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)); + group_ptr->ARBPR &= ~((uint32_t)VADC_G_ARBPR_ASEN0_Msk); +} + + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * bool returns true if the arbitration is enabled else returns false. + * + * \parDescription:
+ * Returns the arbitration status of the queue request source.
\n + * If the queue request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the queue channel can only be converted when the arbiter comes + * to the queue slot. A call to this API would return the status of the arbitration slot of queue. + * A call to this API would read the register bit field GxARBPR.ASEN1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueEnableArbitrationSlot(),
XMC_VADC_GROUP_QueueDisableArbitrationSlot()
+ */ +__STATIC_INLINE bool XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + return ((group_ptr->ARBPR & (uint32_t)VADC_G_ARBPR_ASEN0_Msk) >> VADC_G_ARBPR_ASEN0_Pos); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param input_num Choice of the input earmarked as a trigger line + * @return + * None + * + * \parDescription:
+ * Select Trigger signal for queue request source.
\n + * A queue request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 16 input lines as a trigger line. This is + * needed when a hardware trigger is needed for the conversion of the queue request source. + * Refer to the reference manual to determine the signal that needs to be connected. + * A call to this API would configure the register bit field GxQCTRL0.XTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueSelectGating()
XMC_VADC_GROUP_QueueEnableExternalTrigger()
+ */ +void XMC_VADC_GROUP_QueueSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_TRIGGER_INPUT_SELECT_t input_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param trigger_edge Choice of the trigger edge + * @return + * None + * + * \parDescription:
+ * Select Trigger signal edge for queue request source.
\n + * A queue request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 4 trigger edges. This is + * needed when a hardware trigger is needed for the conversion of the queue request source. + * Refer to the reference manual to determine the signal that needs to be connected. + * A call to this API would configure the register bit field GxQCTRL0.XTMODE. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueSelectGating()
XMC_VADC_GROUP_QueueEnableExternalTrigger()
+ */ +void XMC_VADC_GROUP_QueueSelectTriggerEdge(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_TRIGGER_EDGE_t trigger_edge); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param input_num Choice of the input earmarked as the gating line + * @return + * None + * + * \parDescription:
+ * Select Gating signal for queue request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. Any one of the 16 input + * lines can be chosen as a gating signal. Trigger signal can be given to the queue request source only + * when the gating signal's active level is detected. Additionally the GxQMR0.ENGT has to be configured for + * the gating signal's active level. A call to this API would configure the register bit field GxQCTRL0.GTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueSelectTrigger()
+ */ +void XMC_VADC_GROUP_QueueSelectGating(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GATE_INPUT_SELECT_t input_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param mode_sel Select how the gating is applied to the queue request source + * @return + * None + * + * Details of function
+ * Selects the gating mode of queue request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. + * This API determines how the gating signal behaves, either active low or active high. + * If gating signal needs to ignored XMC_VADC_GATEMODE_IGNORE should be used as the \a mode_sel. + * A call to this API would configure the register bit field GxQMR0.ENGT. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueSelectGating(); + */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueSetGatingMode(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_GATEMODE_t mode_sel) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueSetGatingMode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSetGatingMode:Wrong mode selected", (mode_sel <= XMC_VADC_GATEMODE_ACTIVELOW)) + + /* Clear the existing gate configuration */ + group_ptr->QMR0 &= (uint32_t)(~((uint32_t) VADC_G_QMR0_ENGT_Msk)); + /* Set the new gating mode */ + group_ptr->QMR0 |= (uint32_t)((uint32_t)mode_sel << VADC_G_QMR0_ENGT_Pos); +} + + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Generates conversion request (Software initiated conversion).
+ * A conversion request can be raised either upon detection of a hardware trigger, or by software. This API forces + * the queue unit to generate a conversion request to the analog converter. It is assumed that the queue has already + * been filled up with entries. A call to this API would configure the register bit field GxQMR0.TREV. + * + * \parNote:
+ * The conversion of queue entry will start immediately after the entry has been loaded into GxQINR0. + * This happens only if the queue entry has been loaded into the register without the need for the H/W trigger.\n + * If a H/W Trigger is selected while loading the entry, the conversion will occur in one of the 2 ways: + *
    + *
  • The H/W generates a trigger needed for the queue request source. + *
  • The Conversion is triggered manually by calling this API. + *
+ * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueInsertChannel()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueTriggerConversion(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueTriggerConversion:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->QMR0 |= (uint32_t)((uint32_t)1 << VADC_G_QMR0_TREV_Pos); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * uint32_t returns the total number of channels. + *
Range: [0x0 to 0x8] + * + * \parDescription:
+ * Returns the number of channels present in the queue.
\n + * This API will return the queue buffer size. This buffer will be consisting of valid queue entries which + * will be converted when a trigger event occurs. All the entries that are loaded onto the GxQINR0 will + * be added to the queue buffer. Hence if an application needs to get the number of valid queue entries + * this API would provide the interface. A call to this API would access the registers GxQBUR0, GxQSR0 in order + * to determine the queue length. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueInsertChannel()
+ */ +uint32_t XMC_VADC_GROUP_QueueGetLength(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Aborts an ongoing conversion by flushing the queue.
\n + * This API will flush the queue buffer. Ongoing conversion of the Queue request source will + * not be effected by this API. This would clear all the contents that are present in the queue buffer. + * A call to this API would configure the registers GxQCTRL0, GxQMR0, GxARBPR in order to abort + * the queue sequence. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueRemoveChannel()
XMC_VADC_GROUP_QueueFlushEntries()
+ */ +void XMC_VADC_GROUP_QueueAbortSequence(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Flushing the queue Entry.
\n + * This API will flush one entry in the queue buffer. Ongoing conversion of the Queue request source will + * not be effected by this API. This would clear all the contents that are present in the queue buffer. + * A call to this API would configure the registers GxQMR0. This is a Blocking API, i.e will only exit when + * all the entries are removed from the queue. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueRemoveChannel()
XMC_VADC_GROUP_QueueAbortSequence(0
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueFlushEntries(XMC_VADC_GROUP_t *const group_ptr) +{ + /* Initiate flushing of the queue */ + group_ptr->QMR0 |= (uint32_t)VADC_G_QMR0_FLUSH_Msk; + + while( !((group_ptr->QSR0)& (uint32_t)VADC_G_QSR0_EMPTY_Msk)) + { + /* Wait until the queue is indeed flushed */ + } +} + + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Clears the next valid channel in the queue buffer.
\n + * A queue entry lined up for conversion can be removed and replaced by its successor. The call to this API will + * first check if a valid queue entry is present in the queue backup register if present would clear its valid flag. + * If no valid queue entries are present in the backup then the first channel + * present in the queue buffer would be cleared. + * A call to this API would configure the registers GxQCTRL0, GxQMR0, GxARBPR in order to clear a + * channel from the queue. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueInsertChannel()
+ */ +void XMC_VADC_GROUP_QueueRemoveChannel(XMC_VADC_GROUP_t *const group_ptr); + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param entry Details of the node being added + * @return + * None + * + * \parDescription:
+ * Inserts a queue entry to the tail of the queue buffer.
\n + * This API will insert a new channel into the queue buffer. The Queue will start conversion of + * the channels from the head of the buffer. This Insert will place the entry after the last valid entry. + * If no valid entries are present then this API will place the Queue entry at the head of the buffer. + * Then the successive call to the insert will place the new entry after the last entry. + * A call to this API would configure the register GxQINR0 for a single queue entry. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueRemoveChannel()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueInsertChannel(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_QUEUE_ENTRY_t entry) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueInsertChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + /* Insert the channel physically and get the length of the queue*/ + group_ptr->QINR0 = entry.qinr0; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * int32_t Returns -1 if there are no channels for conversion + * Else would return the next valid channel for conversion. + *
Range: [0x0 to 0x8] + * + * \parDescription:
+ * Returns the next entry in the queue request source for conversion.
\n + * Identifies the channel in the queue lined up for conversion next. + * API will return a valid queue entry from the queue buffer. First checks for the valid channel entry + * in the backup register and returns if present. If the valid entry has not been found in the backup register + * then the queue buffer is searched for a valid entry. A call to this API would access the registers GxQ0R0, + * GxQBUR0 to determine the next channel. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueRemoveChannel()
XMC_VADC_GROUP_QueueInsertChannel()
+ */ +int32_t XMC_VADC_GROUP_QueueGetNextChannel(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * int32_t Returns -1 if there is no channel that have been interrupted. + * Else would return the channel that is interrupted. + *
Range: [0x0 to 0x8] + * + * \parDescription:
+ * Identifies the channel whose conversion was suspended.
\n + * When using cancel inject repeat mode the canceled conversion will be placed in the backup register. + * This API will return the valid queue channel number from the backup register. This happens when ever + * there is a high priority conversion interrupts the conversion of queue request source. This forces the channel + * to goto the backup register. A call to this API would access the register GxQBUR0 to determine the + * interrupted channel. + * + * \parRelated APIs:
+ * None. + */ +int32_t XMC_VADC_GROUP_QueueGetInterruptedChannel(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Manually asserts the conversion complete request source event.
\n + * This API will set the request source event for queue. This will trigger a interrupt if the + * service node pointer for the scan has been configured. + * A call to this API would configure the register bit field GxSEFLAG.SEV0. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueClearReqSrcEvent()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueTriggerReqSrcEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueTriggerReqSrcEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->SEFLAG |= 1U; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Acknowledges the conversion complete request source event.
\n + * This API will clear the request source event that occurred. This will clear a interrupt if it was raised. + * A call to this API would configure the register bit field GxSEFCLR.SEV0. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueTriggerReqSrcEvent()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueClearReqSrcEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueClearReqSrcEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->SEFCLR = (uint32_t)VADC_G_SEFCLR_SEV0_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * bool returns true if the service request event is raised. + * returns false if the service request event was not raised. + * + * \parDescription:
+ * Determines if the request source event is asserted.
+ * This API will get the status of the queue request source event. Will return a true + * if the event has occurred for queue. A call to this API would acces the register bit field GxSEFLAG.SEV0. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE bool XMC_VADC_GROUP_QueueGetReqSrcEventStatus(XMC_VADC_GROUP_t *const group_ptr) +{ + + XMC_ASSERT("XMC_VADC_GROUP_QueueGetReqSrcEventStatus:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return(group_ptr->SEFLAG & (uint32_t)VADC_G_SEFLAG_SEV0_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param sr The service request line (Common SR lines, Group specific SR lines) + * @return + * None + * + * \parDescription:
+ * Connects the event to the SR line of VADC.
\n + * This API will connect a Service Request line(SR) to a queue request source event. Hence to get a interrupt on this + * Service request line one has to enable the required NVIC node. A call to this API would configure the register + * bit field GxSEVNP.SEVNP0. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SR_t sr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables the trigger for queue request source.
\n + * By using this API the trigger will be activated for the queue request source. The trigger signal and trigger + * edge will be selected from the QCTRL register. The Selection of a input will be done by + * XMC_VADC_GROUP_QueueSelectTrigger(). A call to this API would configure the register bit field GxQMR0.ENTR + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueSelectTrigger()
XMC_VADC_GROUP_QueueDisableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueEnableExternalTrigger(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueEnableExternalTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->QMR0 |= (uint32_t)VADC_G_QMR0_ENTR_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables the trigger for queue request source.
+ * By using this API the trigger will be deactivated for the queue request source. + * This will just deactivate the H/W trigger for the queue request source. If any configuration was done + * to select the trigger input in GxQCTRL0 will be not be effected. A call to this API would configure the + * register bit field GxQMR0.ENTR + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueEnableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueDisableExternalTrigger(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueDisableExternalTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->QMR0 &= ~((uint32_t)VADC_G_QMR0_ENTR_Msk); +} +#endif + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num The channel being initialized + *
Range: [0x0 to 0x7] + * @param config Pointer to initialization data + * @return + * None + * + * \parDescription:
+ * Initializes the ADC channel for conversion.
\n + * This API will do the channel related initializations. This includes configuration of the CHCTR settings + * and boundary flag settings. This must be called in the application in order to enable the conversion of + * a channel. After a request source has been initialized this API has to be called for each channel that + * has to be converted. A call to this API would configure the registers GxCHCTR GxBFL GxALIAS GxCHASS + * GxBFLC(depending on device) in order to configure the channel. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ChannelInit(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num, + const XMC_VADC_CHANNEL_CONFIG_t *config); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param src_ch_num Channel which will be converted by \b alias_ch_num, when called by the request source. + *
Range:[0x0 to 0x7] + * @param alias_ch_num This is the alias channel (Ch-0 or Ch-1) + *
Range:[0x0, 0x1] + * @return + * None + * + * \parDescription:
+ * Sets the Alias channel(\b alias_ch_num) to convert from the source channel(\b src_ch_num).
\n + * When a alias configuration takes place the request source(queue/scan/background) will not call channel \b src_ch_num. + * The Request sources will call the channel \b alias_ch_num , this would invoke the conversion of + * the pin associated with \b src_ch_num. The configuration of the alias channel (\b alias_ch_num) will be used + * for the conversion.\n + * When an alias channel (Ch-0 or Ch-1) receives a trigger, it converts the aliased channel (\b src_ch_num). + * The properties of Ch-0 or Ch-1 (as indicated in \b alias_ch_num ) apply when \b src_ch_num is converted. + * A call to this API would configure the register GxALIAS. + * + * \parNote:
+ * Alias Channel (\b alias_ch_num) and the source channel (\b src_ch_num) cannot be the same. + * If they are, that alias feature is not used for the conversion. In order to Reset the alias + * feature that was previously selected this method can be used. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_SetChannelAlias(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t src_ch_num, + const uint32_t alias_ch_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose input was converted + *
Range: [0x0 to 0x7] + * @return + * bool Returns true if there was violation w.r.t the specified boundaries. + * + * \parDescription:
+ * Determines if the result of the channel confines with the specified boundaries.
\n + * An application may not necessarily always need to know the exact value of the converted result, but merely + * an indication if the generated result is within stipulated boundaries. Generation of Channel event can be subject + * to channel event generation criteria (Generate always, Never generate, Generate if result is out of bounds, + * Generate if result is within bounds). When interrupts are not enabled, this API can be used to determine the + * nature of the result. A call to this API would access the registers GxCHCTR and GxCEFLAG in order to determine + * if a violation has occured. + * + * \parRelated APIs:
+ * None + */ +bool XMC_VADC_GROUP_ChannelIsResultOutOfBounds(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose input is to be converted + *
Range: [0x0 to 0x7] + * @param ref Reference voltage + * @return + * None + * + * \parDescription:
+ * Selects the reference voltage for conversion.
\n + * An internal voltage reference (VARef) or an external voltage reference fed to Ch-0 can serve as a voltage reference + * for conversions. A call to this API would configure the register bit field GxCHCTR.REFSEL. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ChannelSetInputReference(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num, + const XMC_VADC_CHANNEL_REF_t ref); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose i/p is to be converted + *
Range: [0x0 to 0x7] + * @param result_reg_num Result Register associated with this channel + * @return + * None + * + * \parDescription:
+ * Selects the target result register.
\n + * There are upto 16 result registers which a channel can choose from to store the results of conversion. + * This selects only the group related result registers. A call to this API would configure the register + * bit field GxCHCTR.RESREG. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ChannelSetResultRegister(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const uint32_t result_reg_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose conversion class is to be configured + *
Range: [0x0 to 0x7] + * @param conversion_class conversion property to be associated with this channel + * @return + * None + * + * \parDescription:
+ * Selects the conversion class registers.
\n + * It configures the channel to have a particular conversion class properties like sampling + * time and resolution. A call to this API would configure the register + * bit field GxCHCTR.ICLSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelGetInputClass(). + */ +void XMC_VADC_GROUP_ChannelSetIclass(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_CHANNEL_CONV_t conversion_class); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose result alignment is to be returned + *
Range: [0x0 to 0x7] + * @return + * XMC_VADC_RESULT_ALIGN_LEFT if the result are aligned to the left + * XMC_VADC_RESULT_ALIGN_RIGHT if the result are aligned to the right + * + * \parDescription:
+ * Returns the channel result alignment.
\n + * The results are aligned either to the left or to the right. A left aligned 10bit resolution has its LSB + * at bit2 where as a left aligned 8bit resolution starts at bit4. A call to this API would return the currently + * configured alignment value. + * A call to this API would read the register bit field GxCHCTR.RESPOS. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_VADC_RESULT_ALIGN_t XMC_VADC_GROUP_ChannelGetResultAlignment(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetResultAlignment:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetResultAlignment:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + return ((XMC_VADC_RESULT_ALIGN_t)((group_ptr->CHCTR[ch_num] & (uint32_t)VADC_G_CHCTR_RESPOS_Msk) >> + (uint32_t)VADC_G_CHCTR_RESPOS_Pos) ); +} + + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose result alignment is to be returned + *
Range: [0x0 to 0x7] + * @return + * XMC_VADC_CHANNEL_CONV_t Returns the configured input class for the \b ch_num + * + * \parDescription:
+ * Returns the channel's input class for conversion for the required channel.
\n + * The sampling time and resolution can be taken from any of the 4 possible Input class registers. + * This API would return the input class register that is taken up by \b ch_num for conversion. + * A call to this API would read the register bit field GxCHCTR.RESPOS. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelSetIclass(). + */ +__STATIC_INLINE XMC_VADC_CHANNEL_CONV_t XMC_VADC_GROUP_ChannelGetInputClass(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetInputClass:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetInputClass:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + return ((XMC_VADC_CHANNEL_CONV_t)((group_ptr->CHCTR[ch_num] & (uint32_t)VADC_G_CHCTR_ICLSEL_Msk) >> + (uint32_t)VADC_G_CHCTR_ICLSEL_Pos) ); +} + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose associated result register is to be found + *
Range: [0x0 to 0x7] + * @return + * uint8_t returns the Group result register to which it is linked to. + *
Range: [0x0 to 0xF] + * + * \parDescription:
+ * Returns the result register associated with this channel.
\n + * There are upto 16 result registers which a channel can choose from to store the results of conversion. + * This returns only the group related result registers. A call to this API would access the register + * bit field GxCHCTR.RESREG. + * + * \parRelated APIs:
+ * None. + */ +uint8_t XMC_VADC_GROUP_ChannelGetResultRegister(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose channel event is to be asserted + *
Range: [0x0 to 0x7] + * @return + * None + * + * \parDescription:
+ * Manually asserts a Channel event.
\n + * It is merely the channel event which is asserted. For this asserted event to lead to an interrupt, it must + * have been bound to an SR and that SR must have been enabled. It can potentially lead to an interrupt if the + * SR line is connected to an NVIC node. A call to this API would configure the register bit fields of GxCEFLAG. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelClearEvent(). + */ +void XMC_VADC_GROUP_ChannelTriggerEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * uint32_t returns the asserted channel events + * + * \parDescription:
+ * Returns the Channel event flag register.
\n + * The return is merely the channel events which are asserted. + * A call to this API would read the register bit fields of GxCEFLAG. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelClearEvent(). + */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_ChannelGetAssertedEvents(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetAssertedEvents:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return(group_ptr->CEFLAG); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose channel event is to be acknowledged + *
Range: [0x0 to 0x7] + * @return + * None + * + * \parDescription:
+ * Acknowledges a Channel event.
\n + * When a channel event is raised after the conversion of that channel, it has to be cleared. This API would clear + * the Channel event of a particular channel if it has occurred. A call to this API would configure the register + * bit fields of GxCEFCLR. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelTriggerEvent(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_ChannelClearEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + + XMC_ASSERT("XMC_VADC_GROUP_ChannelClearEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelClearEvent:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + group_ptr->CEFCLR = (uint32_t)((uint32_t)1 << ch_num); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose channel event is to be connected to a service request line + *
Range: [0x0 to 0x7] + * @param sr The service request line to which the channel event is to be connected + * @return + * None + * + * \parDescription:
+ * Binds a channel event to a requested Service Request line.
\n + * The channel event is connected to a service request line. For an event to result in an interrupt, this service + * request line must be enabled in VADC and the NVIC node which this service request line is connected to must have + * interrupt generation enabled. A call to this API would configure the register bit fields of GxCEVNP0. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelTriggerEvent()
XMC_VADC_GROUP_ChannelClearEvent() + */ +void XMC_VADC_GROUP_ChannelSetEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_SR_t sr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose channel event is being configured + *
Range: [0x0 to 0x7] + * @param criteria The condition under which the channel may assert its channel event + * @return + * None + * + * \parDescription:
+ * Defines the conditions under which a channel may assert its channel event.
\n + * The channel event can be generated under the following conditions - Always, Never, Result Out of bounds and Result + * inside the boundaries. A call to this API would configure the register bit field GxCHCTR.CHEVMODE. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelTriggerEvent()
XMC_VADC_GROUP_ChannelClearEvent()
+ * XMC_VADC_GROUP_ChannelSetEventInterruptNode()
+ */ +void XMC_VADC_GROUP_ChannelTriggerEventGenCriteria(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_CHANNEL_EVGEN_t criteria); + + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose channel event is being configured + *
Range: [0x0 to 0x7] + * @param boundary_sel Select the upper/lower boundary configuration . + * @param selection The boundary value selected for \b boundary_sel. + * @return + * None + * + * \parDescription:
+ * Configure the boundary selection for the given channel
\n + * The channel event can be generated under the following conditions - Always, Never, Result Out of bounds and Result + * inside the boundaries. The boundary values to which results are compared can be selected from several sources. + * A call to this API would configure the register bit field GxCHCTR.BNDSELL or GxCHCTR.BNDSELU . + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ChannelSetBoundarySelection(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + XMC_VADC_BOUNDARY_SELECT_t boundary_sel, + XMC_VADC_CHANNEL_BOUNDARY_t selection); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg_num Result register which is intended to be initialized + *
Range: [0x0 to 0xF] + * @param config Pointer to initialization data + * @return + * None + * + * \parDescription:
+ * Initializes a Group Result Register.
+ * Various options needed for the working of the result result will be configured with this API. + * This would determine the result handling of the group registers. This API must be called after + * the channel Init (XMC_VADC_GROUP_ChannelInit())to initialize the result register that is selected for the channel. + * This API would also determine if the result register that is being configured has to a part of a FIFO buffer. + * In this API one can also configure the various result handling options line FIR/IIR filters and it order. + * Also configures the Data reduction to accumulate 2/3/4 results need to be done. This API will also configure + * the result event generation. A call to this API would configure the register GxRCR with the \b config . + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_AddResultToFifo()
XMC_VADC_GROUP_EnableResultEvent()
XMC_VADC_GROUP_DisableResultEvent()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ResultInit(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg_num, + const XMC_VADC_RESULT_CONFIG_t *config) +{ + XMC_ASSERT("XMC_VADC_GROUP_ResultInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->RCR[res_reg_num] = config->g_rcr; + +} + + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Register which is required to be a part of results FIFO + *
Range: [0x0 to 0xF] + * @return + * None + * + * \parDescription:
+ * Adds result register to Result FIFO.
\n + * Sometimes, the rate of consumption of results by application software may not match the rate at which the + * results are produced. A Result FIFO thus helps a slow consumer to read out results without loss of data. + * When a result register is added to fifo, it is in fact chained to its higher numbered neighbor. For example, if + * Result Register-5 is to be added to FIFO, it gets chained to Result Register-6. Results are written to Register-6 + * while the same can be read out of Register-5 leisurely by software. + * A call to this API would configure the register bit field GxRCR.FEN. + * + * \parNote:
+ * The FIFO is always read by the software with the lowest numbered result register. + * The hardware will write the results from the highest numbered result register. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_AddResultToFifo(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which event generation is to be enabled + *
Range: [0x0 to 0xF] + * @return + * None + * + * \parDescription:
+ * Enables result event generation.
\n + * Once the results of conversion are available, the result event (which is being enabled in this function) + * if connected to a service request line(Group or Shared service request) can lead to an interrupt. It is therefore + * not only necessary to enable the event, but also to connect it to a service request line. The + * service request generation capability must also be enabled and so should the corresponding NVIC node. + * A call to this API would configure the register bit field GxRCR.SRGEN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_SetResultInterruptNode(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_EnableResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + + XMC_ASSERT("XMC_VADC_GROUP_EnableResultEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_EnableResultEvent:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + group_ptr->RCR[res_reg] |= (uint32_t)VADC_G_RCR_SRGEN_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which event generation is to be disabled + *
Range: [0x0 to 0xF] + * @return + * None + * + * \parDescription:
+ * Disable result event generation.
\n + * This would just disable the event. It would not alter anything w.r.t the SR line if it was configured. + * A call to this API would configure the register bit field GxRCR.SRGEN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_EnableResultEvent(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_DisableResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + XMC_ASSERT("XMC_VADC_GROUP_DisableResultEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_DisableResultEvent:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + group_ptr->RCR[res_reg] &= ~((uint32_t)VADC_G_RCR_SRGEN_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register from which the result of conversion is to be read out + *
Range: [0x0 to 0xF] + * @return + * uint32_t returns the complete result register GxRESy. + * + * \parDescription:
+ * Returns the result register completely (result of conversion as well as other info).
\n + * The Result register will have information regarding the channel that is requesting the conversion, + * if the result is valid, if the fast compare bit, Data Reduction Counter, and the request source information. + * All these information will be returned back. And if the user is polling for the result he can use the + * result if the valid bit is set. A call to this API would return the complete register GxRES. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetResult(). + */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetDetailedResult(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + XMC_ASSERT("XMC_VADC_GROUP_GetDetailedResult:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetDetailedResult:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + return(group_ptr->RES[res_reg]); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register from which the result of conversion is to be read out + *
Range: [0x0 to 0xF] + * @return + * XMC_VADC_RESULT_SIZE_t Result register values. + *
Range:[ 0x0 to 0xFFF] (Result of single conversion. Accumulated results not considered for range) + * + * \parDescription:
+ * Returns the result of the conversion.
\n + * This API will only return the result of the conversion and will strip out the other information that is present + * in the result register. A call to this API would access the register bit field GxRES.RESULT. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetDetailedResult(). + */ +__STATIC_INLINE XMC_VADC_RESULT_SIZE_t XMC_VADC_GROUP_GetResult(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg) +{ + XMC_ASSERT("XMC_VADC_GROUP_GetResult:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetResult:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + return ((XMC_VADC_RESULT_SIZE_t)group_ptr->RES[res_reg]); +} + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which the compare value is being set + *
Range: [0x0 to 0xF] + * @param compare_val The compare value itself + *
Range: [0x0 to 0xFFF] + * @return + * None + * + * \parDescription:
+ * Configures the compare value (relevant to the Fast Compare Mode).
\n + * A channel input can be converted and its value stored in its result register. Alternatively, the channel input can + * be converted and compared against a compare value. This is the fast compare mode typically utilized by applications + * that are not interested in absolute converted value of an analog input, but rather a binary decision on how the + * input fares against a preset compare value. The channel should have had already chosen the correct ICLASS with + * the fast compare mode enabled. \b compare_val would be the compare value on which FCM bit in the result + * register will be set. The FCM bit will be set if the analog voltage is greater than the compare value. + * A call to this API would configure the register bit field GxRES.RESULT. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetFastCompareResult(). + */ +void XMC_VADC_GROUP_SetResultFastCompareValue(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg, + const XMC_VADC_RESULT_SIZE_t compare_val); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which the compare value is being set + *
Range: [0x0 to 0xF] + * @return + * ::XMC_VADC_FAST_COMPARE_t If the input is greater or lower than the compare value returns the appropriate enum. + * if the valid flag was not set then it would return XMC_VADC_FAST_COMPARE_UNKNOWN. + * + * \parDescription:
+ * Determines the input is greater/lower than the compare value.
\n + * This API determines if the input is greater/lower than the preset compare value. + * A call to this API would access the register bit field GxRES.FCM. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_SetResultFastCompareValue(). + */ +XMC_VADC_FAST_COMPARE_t XMC_VADC_GROUP_GetFastCompareResult(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg); + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param subtraction_val 12 bit subtraction value + *
Range: [0x0 to 0xFFF] + * @return + * None + * + * \parDescription:
+ * Configures the subtraction value (relevant to the Difference Mode).
\n + * A channel input can be converted and its value stored in its result register. Alternatively, the channel input can + * be converted and subtracted with the value stored in GxRES[0]. This Difference Mode typically utilized by + * applications that are not interested in absolute converted value of an analog input, but rather a difference of + * converted values. Subtraction value will always be present in the GxRES[0] and thus this API would configure + * that register. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_SetResultSubtractionValue(XMC_VADC_GROUP_t *const group_ptr, + const uint16_t subtraction_val); +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which the result event is being asserted + *
Range: [0x0 to 0xF] + * @return + * None + * + * \parDescription:
+ * Manually asserts the result event.
\n + * The result event must necessarily be connected to a SR line. The SR in turn must have been enabled along with the + * corresponding NVIC node. Only then will the assertion of RES event lead to an interrupt. + * A call to this API would access the register bit fieldS OF GxREFLAG. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ClearResultEvent(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_TriggerResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + XMC_ASSERT("XMC_VADC_GROUP_TriggerResultEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_TriggerResultEvent:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + group_ptr->REFLAG = (uint32_t)((uint32_t)1 << res_reg); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * uint32_t returns the asserted result events + * + * \parDescription:
+ * Returns the Result event flag register.
\n + * The return is merely the result events which are asserted. + * A call to this API would read the register bit fields of GxREFLAG. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_TriggerResultEvent(). + */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetAssertedResultEvents(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_GetAssertedResultEvents:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return(group_ptr->REFLAG); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which the result event is being acknowledged + *
Range: [0x0 to 0xF] + * @return + * None + * + * \parDescription:
+ * Acknowledges a Result event.
\n + * When a Result event is raised after the conversion of that associated channel has produced a result and + * it has to be cleared. This API would clear the Channel event of a particular channel if it has occurred. + * A call to this API would access the register bit fields of GxREFCLR. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelTriggerEvent(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_ClearResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + XMC_ASSERT("XMC_VADC_GROUP_ClearResultEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ClearResultEvent:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + group_ptr->REFCLR = (uint32_t)((uint32_t)1 << res_reg); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which the result event is being asserted + *
Range: [0x0 to 0xF] + * @param sr The SR line to which the result event must be connected + * @return + * None + * + * \parDescription:
+ * Binds a result event to a requested Service Request line.
\n + * The result event is connected to a service request line. For an event to result in an interrupt, this service + * request line must be enabled in VADC and the NVIC node which this service request line is connected to must have + * interrupt generation enabled. A call to this API would access the registers GxREVNP0 GxREVNP1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_TriggerResultEvent()
XMC_VADC_GROUP_ClearResultEvent() + */ +void XMC_VADC_GROUP_SetResultInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg, + const XMC_VADC_SR_t sr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register which forms a part of FIFO + *
Range: [0x0 to 0xF] + * @return + * uint32_t returns the Result register number which is the tail of the FIFO,\b res_reg is apart of this FIFO. + * + * \parDescription:
+ * Returns the the FIFO tail (register from where to read the results).
\n + * The analog converter writes to the head of the FIFO. It is the head of the FIFO which is bound to the channel. + * Applications read the result from the tail of the FIFO. This API would return the result + * register from where a user can call the API XMC_VADC_GROUP_GetResult() to read the result stored in the FIFO. + * A call to this API would access the register bit field GxRCR.FEN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetResultFifoHead()
+ */ +uint32_t XMC_VADC_GROUP_GetResultFifoTail(XMC_VADC_GROUP_t *const group_ptr, uint32_t res_reg); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register which forms a part of fifo + *
Range: [0x0 to 0xF] + * @return + * uint32_t returns the Result register number which is the head of the FIFO,\b res_reg is apart of this FIFO. + * + * \parDescription:
+ * Returns the the FIFO head (register to which the results are written by H/W).
\n + * The analog converter writes to the head of the FIFO. It is the head of the FIFO which is bound to the channel. + * Applications read the result from the tail of the FIFO. This API would just return the head of the FIFO + * from where the results are being added to the FIFO. + * A call to this API would access the register bit field GxRCR.FEN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetResultFifoHead()
+ */ +uint32_t XMC_VADC_GROUP_GetResultFifoHead(XMC_VADC_GROUP_t *const group_ptr,const uint32_t res_reg); + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register in question + *
Range: [0x0 to 0xF] + * @return + * bool returns true if the \b res_reg is the FIFO head. + * + * \parDescription:
+ * Determines if the requested register is the head of a FIFO.
\n + * The analog converter writes to the head of the FIFO. It is the head of the FIFO which is bound to the channel. + * Applications read the result from the tail of the FIFO. + * A call to this API would access the register bit field GxRCR.FEN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetResultFifoHead()
+ */ +bool XMC_VADC_GROUP_IsResultRegisterFifoHead(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg); + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register number
+ *
Range: [0x0 to 0xF] + * @return + * bool returns true if the \b res_reg is the FIFO member, else false. + * + * \parDescription:
+ * Determines whether the specified register is a FIFO member or not.
\n + * The analog converter writes to the head of the FIFO. It is the head of the FIFO which is bound to the channel. + * Applications read the result from the tail of the FIFO. + * A call to this API would access the register bit field GxRCR.FEN. + * + */ +__STATIC_INLINE bool XMC_VADC_GROUP_IsResultRegisterInFifo(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg) +{ + + XMC_ASSERT("XMC_VADC_GROUP_IsResultRegisterInFifo:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_IsResultRegisterInFifo:Wrong Result Register", + ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + return( (bool)(group_ptr->RCR[res_reg] & (uint32_t)VADC_G_RCR_FEN_Msk)); +} + +#if XMC_VADC_RESULT_PRIORITY_AVAILABLE == 1U +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Registers which need to be set for priority conversions + * Bit location 0..15 represents Result Register-0..15 respectively. + * To add the result register as priority. + * Passing a 0x0 will clear all the selected channels + *
Range: [0x0 to 0xFFFF] + * @return + * None + * + * \parDescription:
+ * Prioritize a Result register for group conversions.
\n + * Applications that need to reserve certain result registers only for Queue and scan request sources should + * use this API. A call to this API would access the register bit fields of GxRRASS. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetResultRegPriority(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_SetResultRegPriority(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_mask) +{ + XMC_ASSERT("XMC_VADC_GROUP_SetResultRegPriority:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->RRASS = (uint32_t)res_mask; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Get the priority of all Result register.
\n + * A call to this API would access the register bit fields of GxRRASS. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_SetResultRegPriority(). + */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetResultRegPriority(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_GetResultRegPriority:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return(group_ptr->RRASS); +} +#endif +#endif + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_vadc_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_vadc_map.h new file mode 100644 index 00000000..865f6688 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_vadc_map.h @@ -0,0 +1,293 @@ +/** + * @file xmc_vadc_map.h + * @date 2016-11-17 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-15: + * - Initial version + * + * 2015-12-01: + * - Added: + * - XMC4300 device supported + * + * - Fixed: + * - Wrong MACRO name corrected for XMC4200/4100 devices. + * XMC_VADC_G3_SAMPLE renamed to XMC_VADC_G1_SAMPLE + * + * 2016-11-17: + * - Fixed: Add missing support for XMC47000 + * - Fixed: Renamed XMC_CCU_41_ST2 to XMC_CCU_41_ST3 + * - Added: New macros equivalent to th existing ones but with better naming. + * Old macros are kept for backward compatibility but they deprecated. + * - Added: ECAT support for XMC48/43 + * + * @endcond + * + */ + +#ifndef XMC_ADC_MAP_H +#define XMC_ADC_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ +#if ( UC_FAMILY == XMC1 ) + +/* Group request source Gating input connection mappings */ +#define XMC_CCU_40_ST3 XMC_VADC_REQ_GT_A /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */ +#define XMC_CCU_40_ST2 XMC_VADC_REQ_GT_B /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST2 */ +#define XMC_CCU_40_ST1 XMC_VADC_REQ_GT_C /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST1 */ +#define XMC_CCU_40_ST0 XMC_VADC_REQ_GT_D /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST0 */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_CCU_80_ST3_A XMC_VADC_REQ_GT_E /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3A */ +#define XMC_CCU_81_ST3 XMC_VADC_REQ_GT_F /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3 */ +#endif +#if (UC_SERIES != XMC13 && UC_SERIES != XMC11) +#define XMC_LEDTS0_FN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS0_FN */ +#define XMC_LEDTS1_FN XMC_VADC_REQ_GT_J /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS1_FN */ +#endif +#define XMC_ERU_0_PDOUT2 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT2 */ +#define XMC_ERU_0_PDOUT3 XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT3 */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_CCU_80_ST0 XMC_VADC_REQ_GT_M /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST0 */ +#define XMC_CCU_80_ST1 XMC_VADC_REQ_GT_N /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST1 */ +#endif +#define XMC_ERU_0_PDOUT0 XMC_VADC_REQ_GT_O /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT0 */ +#define XMC_ERU_0_PDOUT1 XMC_VADC_REQ_GT_P /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT1 */ + +/* Group request source Trigger input connection mappings */ +#define XMC_CCU_40_SR2 XMC_VADC_REQ_TR_A /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR2 */ +#define XMC_CCU_40_SR3 XMC_VADC_REQ_TR_B /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR3 */ +#if (UC_SERIES != XMC11) +#define XMC_BCCU0_TRIGOUT XMC_VADC_REQ_TR_F /**< @deprecated use instead XMC_VADC_REQ_TR_BCCU0_TRIGOUT0, XMC_VADC_REQ_TR_G0_BCCU0_TRIGOUT0 or XMC_VADC_REQ_TR_G1_BCCU0_TRIGOUT1 */ +#endif +#define XMC_ERU_0_IOUT2 XMC_VADC_REQ_TR_G /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT2 */ +#define XMC_ERU_0_IOUT3 XMC_VADC_REQ_TR_H /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT3 */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_CCU_80_SR2 XMC_VADC_REQ_TR_I /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR2 */ +#define XMC_CCU_80_SR3 XMC_VADC_REQ_TR_J /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR3 */ +#endif +#define XMC_ERU_0_IOUT0 XMC_VADC_REQ_TR_M /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT0 */ +#define XMC_ERU_0_IOUT1 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT1 */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_POSIF_0_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1 */ +#endif +#define XMC_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< @deprecated use instead XMC_VADC_REQ_TR_REQ_GT_SEL */ + +/* Group request source Gating input connection mappings */ +#define XMC_VADC_REQ_GT_CCU40_ST3 XMC_VADC_REQ_GT_A /**< VADC Gating input A */ +#define XMC_VADC_REQ_GT_CCU40_ST2 XMC_VADC_REQ_GT_B /**< VADC Gating input B */ +#define XMC_VADC_REQ_GT_CCU40_ST1 XMC_VADC_REQ_GT_C /**< VADC Gating input C */ +#define XMC_VADC_REQ_GT_CCU40_ST0 XMC_VADC_REQ_GT_D /**< VADC Gating input D */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_VADC_REQ_GT_CCU80_ST3A XMC_VADC_REQ_GT_E /**< VADC Gating input E */ +#define XMC_VADC_REQ_GT_CCU80_ST3 XMC_VADC_REQ_GT_F /**< VADC Gating input F */ +#endif +#if (UC_SERIES != XMC13 && UC_SERIES != XMC11) +#define XMC_VADC_REQ_GT_LEDTS0_FN XMC_VADC_REQ_GT_I /**< VADC Gating input I */ +#define XMC_VADC_REQ_GT_LEDTS1_FN XMC_VADC_REQ_GT_J /**< VADC Gating input J */ +#endif +#define XMC_VADC_REQ_GT_ERU0_PDOUT2 XMC_VADC_REQ_GT_K /**< VADC Gating input K */ +#define XMC_VADC_REQ_GT_ERU0_PDOUT3 XMC_VADC_REQ_GT_L /**< VADC Gating input L */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_VADC_REQ_GT_CCU80_ST0 XMC_VADC_REQ_GT_M /**< VADC Gating input M */ +#define XMC_VADC_REQ_GT_CCU80_ST1 XMC_VADC_REQ_GT_N /**< VADC Gating input N */ +#endif +#define XMC_VADC_REQ_GT_ERU0_PDOUT0 XMC_VADC_REQ_GT_O /**< VADC Gating input O */ +#define XMC_VADC_REQ_GT_ERU0_PDOUT1 XMC_VADC_REQ_GT_P /**< VADC Gating input P */ + +/* Group request source Trigger input connection mappings */ +#define XMC_VADC_REQ_TR_CCU40_SR2 XMC_VADC_REQ_TR_A /**< VADC Trigger input A */ +#define XMC_VADC_REQ_TR_CCU40_SR3 XMC_VADC_REQ_TR_B /**< VADC Trigger input B */ +#if (UC_SERIES != XMC11) +#define XMC_VADC_REQ_TR_BCCU0_TRIGOUT0 XMC_VADC_REQ_TR_F /**< VADC Global Background Source Trigger input F */ +#define XMC_VADC_REQ_TR_G0_BCCU0_TRIGOUT0 XMC_VADC_REQ_TR_F /**< VADC Group 0 Trigger input F */ +#define XMC_VADC_REQ_TR_G1_BCCU0_TRIGOUT1 XMC_VADC_REQ_TR_F /**< VADC Group1 Trigger input F */ +#endif +#define XMC_VADC_REQ_TR_ERU0_IOUT2 XMC_VADC_REQ_TR_G /**< VADC Trigger input G */ +#define XMC_VADC_REQ_TR_ERU0_IOUT3 XMC_VADC_REQ_TR_H /**< VADC Trigger input H */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_VADC_REQ_TR_CCU80_SR2 XMC_VADC_REQ_TR_I /**< VADC Trigger input I */ +#define XMC_VADC_REQ_TR_CCU80_SR3 XMC_VADC_REQ_TR_J /**< VADC Trigger input J */ +#endif +#define XMC_VADC_REQ_TR_ERU0_IOUT0 XMC_VADC_REQ_TR_M /**< VADC Trigger input M */ +#define XMC_VADC_REQ_TR_ERU0_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Trigger input N */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_VADC_REQ_TR_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Trigger input O */ +#endif +#define XMC_VADC_REQ_TR_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< VADC Trigger input P */ + +#endif + +#if ( UC_FAMILY == XMC4 ) + +/* Group request source Gating input connection mappings */ +#define XMC_CCU_40_ST3 XMC_VADC_REQ_GT_A /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */ +#define XMC_CCU_41_ST3 XMC_VADC_REQ_GT_B /**< @deprecated use instead XMC_VADC_REQ_GT_CCU41_ST3 */ +#define XMC_CCU_40_SR0 XMC_VADC_REQ_GT_C /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_SR0 */ +#define XMC_CCU_41_SR1 XMC_VADC_REQ_GT_D /**< @deprecated use instead XMC_VADC_REQ_GT_CCU41_SR1 */ +#define XMC_CCU_80_ST3_A XMC_VADC_REQ_GT_E /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3A */ +#define XMC_CCU_80_ST3_B XMC_VADC_REQ_GT_F /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3B */ + +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_CCU_81_ST3_A XMC_VADC_REQ_GT_G /**< @deprecated use instead XMC_VADC_REQ_GT_CCU81_ST3A */ +#define XMC_CCU_81_ST3_B XMC_VADC_REQ_GT_H /**< @deprecated use instead XMC_VADC_REQ_GT_CCU81_ST3B */ +#endif + +#define XMC_DAC_0_SGN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_DAC0_SGN, XMC_VADC_REQ_GT_G0_DAC0_SGN or XMC_VADC_REQ_GT_G2_DAC0_SGN */ +#define XMC_DAC_1_SGN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_DAC0_SGN, XMC_VADC_REQ_GT_G1_DAC1_SGN or XMC_VADC_REQ_GT_G3_DAC1_SGN */ +#define XMC_LEDTS_FN XMC_VADC_REQ_GT_J /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS_FN */ +#define XMC_VADC_G0_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G0_VADC_G1BFLOUT0 */ +#define XMC_VADC_G1_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G1_VADC_G0BFLOUT0 */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_G2_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G2_VADC_G3BFLOUT0 */ +#define XMC_VADC_G3_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G3_VADC_G2BFLOUT0 */ +#endif +#define XMC_VADC_G0_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G0_VADC_G3SAMPLE */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_G1_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G1_VADC_G0SAMPLE */ +#define XMC_VADC_G2_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G2_VADC_G1SAMPLE */ +#define XMC_VADC_G3_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G3_VADC_G2SAMPLE */ +#endif +#define XMC_CCU_80_SR0 XMC_VADC_REQ_GT_M /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_SR0 */ +#define XMC_CCU_80_SR1 XMC_VADC_REQ_GT_N /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_SR1 */ +#define XMC_ERU_1_PDOUT0 XMC_VADC_REQ_GT_O /**< @deprecated use instead XMC_VADC_REQ_GT_ERU1_PDOUT0 */ +#define XMC_ERU_1_PDOUT1 XMC_VADC_REQ_GT_P /**< @deprecated use instead XMC_VADC_REQ_GT_ERU1_PDOUT1 */ + +/* Group request source Trigger input connection mappings */ +#define XMC_CCU_40_SR2 XMC_VADC_REQ_TR_A /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR2 */ +#define XMC_CCU_40_SR3 XMC_VADC_REQ_TR_B /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR3 */ +#define XMC_CCU_41_SR2 XMC_VADC_REQ_TR_C /**< @deprecated use instead XMC_VADC_REQ_TR_CCU41_SR2 */ +#define XMC_CCU_41_SR3 XMC_VADC_REQ_TR_D /**< @deprecated use instead XMC_VADC_REQ_TR_CCU41_SR3 */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_CCU_42_SR3 XMC_VADC_REQ_TR_E /**< @deprecated use instead XMC_VADC_REQ_TR_CCU42_SR3 */ +#define XMC_CCU_43_SR3 XMC_VADC_REQ_TR_F /**< @deprecated use instead XMC_VADC_REQ_TR_CCU43_SR3 */ +#endif +#define XMC_CCU_80_SR2 XMC_VADC_REQ_TR_I /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR2 */ +#define XMC_CCU_80_SR3 XMC_VADC_REQ_TR_J /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR3 */ +#define XMC_CCU_81_SR2 XMC_VADC_REQ_TR_K /**< @deprecated use instead XMC_VADC_REQ_TR_CCU81_SR2 */ +#define XMC_CCU_81_SR3 XMC_VADC_REQ_TR_L /**< @deprecated use instead XMC_VADC_REQ_TR_CCU81_SR3 */ +#define XMC_ERU_1_IOUT0 XMC_VADC_REQ_TR_M /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT0 */ +#define XMC_ERU_1_IOUT1 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT1, XMC_VADC_REQ_TR_G0_ERU1_IOUT1 or XMC_VADC_REQ_TR_G1_ERU1_IOUT1 */ +#define XMC_ERU_1_IOUT2 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT1, XMC_VADC_REQ_TR_G2_ERU1_IOUT2 or XMC_VADC_REQ_TR_G3_ERU1_IOUT1 */ +#if ( (UC_SERIES != XMC43) ) +#define XMC_POSIF_0_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1, XMC_VADC_REQ_TR_G0_POSIF0_SR1 or XMC_VADC_REQ_TR_G2_POSIF0_SR1 */ +#endif +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_POSIF_1_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1, XMC_VADC_REQ_TR_G1_POSIF0_SR1 or XMC_VADC_REQ_TR_G3_POSIF0_SR1 */ +#endif +#define XMC_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */ + +/* Group request source Gating input connection mappings */ +#define XMC_VADC_REQ_GT_CCU40_ST3 XMC_VADC_REQ_GT_A /**< VADC Gating input A */ +#define XMC_VADC_REQ_GT_CCU41_ST3 XMC_VADC_REQ_GT_B /**< VADC Gating input B */ +#define XMC_VADC_REQ_GT_CCU40_SR0 XMC_VADC_REQ_GT_C /**< VADC Gating input C */ +#define XMC_VADC_REQ_GT_CCU41_SR1 XMC_VADC_REQ_GT_D /**< VADC Gating input D */ +#define XMC_VADC_REQ_GT_CCU80_ST3A XMC_VADC_REQ_GT_E /**< VADC Gating input E */ +#define XMC_VADC_REQ_GT_CCU80_ST3B XMC_VADC_REQ_GT_F /**< VADC Gating input F */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_REQ_GT_CCU81_ST3A XMC_VADC_REQ_GT_G /**< VADC Gating input G */ +#define XMC_VADC_REQ_GT_CCU81_ST3B XMC_VADC_REQ_GT_H /**< VADC Gating input H */ +#endif +#define XMC_VADC_REQ_GT_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Global Background Source Gating input I */ +#define XMC_VADC_REQ_GT_G0_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Group 0 Gating input I */ +#define XMC_VADC_REQ_GT_G1_DAC1_SGN XMC_VADC_REQ_GT_I /**< VADC Group 1 Gating input I */ +#define XMC_VADC_REQ_GT_G2_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Group 2 Gating input I */ +#define XMC_VADC_REQ_GT_G3_DAC1_SGN XMC_VADC_REQ_GT_I /**< VADC Group 3 Gating input I */ +#define XMC_VADC_REQ_GT_LEDTS_FN XMC_VADC_REQ_GT_J /**< VADC Gating input J */ +#define XMC_VADC_REQ_GT_VADC_G1BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Global Background Source Gating input K */ +#define XMC_VADC_REQ_GT_G0_VADC_G1BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 0 Gating input K */ +#define XMC_VADC_REQ_GT_G1_VADC_G0BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 1 Gating input K */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_REQ_GT_G2_VADC_G3BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 2 Gating input K */ +#define XMC_VADC_REQ_GT_G3_VADC_G2BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 3 Gating input K */ +#endif +#define XMC_VADC_REQ_GT_G0_VADC_G3SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 0 Gating input L */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_REQ_GT_G1_VADC_G0SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 1 Gating input L */ +#define XMC_VADC_REQ_GT_G2_VADC_G1SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 2 Gating input L */ +#define XMC_VADC_REQ_GT_G3_VADC_G2SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 3 Gating input L */ +#endif +#define XMC_VADC_REQ_GT_CCU80_SR0 XMC_VADC_REQ_GT_M /**< VADC Gating input M */ +#define XMC_VADC_REQ_GT_CCU80_SR1 XMC_VADC_REQ_GT_N /**< VADC Gating input N */ +#define XMC_VADC_REQ_GT_ERU1_PDOUT0 XMC_VADC_REQ_GT_O /**< VADC Gating input O */ +#define XMC_VADC_REQ_GT_ERU1_PDOUT1 XMC_VADC_REQ_GT_P /**< VADC Gating input P */ + +/* Group request source Trigger input connection mappings */ +#define XMC_VADC_REQ_TR_CCU40_SR2 XMC_VADC_REQ_TR_A /**< VADC Trigger input A */ +#define XMC_VADC_REQ_TR_CCU40_SR3 XMC_VADC_REQ_TR_B /**< VADC Trigger input B */ +#define XMC_VADC_REQ_TR_CCU41_SR2 XMC_VADC_REQ_TR_C /**< VADC Trigger input C */ +#define XMC_VADC_REQ_TR_CCU41_SR3 XMC_VADC_REQ_TR_D /**< VADC Trigger input D */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_REQ_TR_CCU42_SR3 XMC_VADC_REQ_TR_E /**< VADC Trigger input E */ +#define XMC_VADC_REQ_TR_CCU43_SR3 XMC_VADC_REQ_TR_F /**< VADC Trigger input F */ +#endif +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC43)) +#define XMC_VADC_REQ_TR_ECAT_SYNC0 XMC_VADC_REQ_TR_G /**< VADC Trigger input G */ +#define XMC_VADC_REQ_TR_ECAT_SYNC1 XMC_VADC_REQ_TR_H /**< VADC Trigger input H */ +#endif +#define XMC_VADC_REQ_TR_CCU80_SR2 XMC_VADC_REQ_TR_I /**< VADC Trigger input I */ +#define XMC_VADC_REQ_TR_CCU80_SR3 XMC_VADC_REQ_TR_J /**< VADC Trigger input J */ +#define XMC_VADC_REQ_TR_CCU81_SR2 XMC_VADC_REQ_TR_K /**< VADC Trigger input K */ +#define XMC_VADC_REQ_TR_CCU81_SR3 XMC_VADC_REQ_TR_L /**< VADC Trigger input L */ +#define XMC_VADC_REQ_TR_ERU1_IOUT0 XMC_VADC_REQ_TR_M /**< VADC Trigger input M */ +#define XMC_VADC_REQ_TR_ERU1_IOUT1 XMC_VADC_REQ_TR_M /**< VADC Global Background Source Trigger input N */ +#define XMC_VADC_REQ_TR_G0_ERU1_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Group 0 Trigger input N */ +#define XMC_VADC_REQ_TR_G1_ERU1_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Group 1 Trigger input N */ +#define XMC_VADC_REQ_TR_G2_ERU1_IOUT2 XMC_VADC_REQ_TR_N /**< VADC Group 2 Trigger input N */ +#define XMC_VADC_REQ_TR_G3_ERU1_IOUT2 XMC_VADC_REQ_TR_N /**< VADC Group 3 Trigger input N */ +#if ( (UC_SERIES != XMC43) ) +#define XMC_VADC_REQ_TR_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Global Background Source Trigger input O */ +#define XMC_VADC_REQ_TR_G0_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 0 Trigger input O */ +#define XMC_VADC_REQ_TR_G1_POSIF1_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 1 Trigger input O */ +#endif +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_REQ_TR_G2_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 2 Trigger input O */ +#define XMC_VADC_REQ_TR_G3_POSIF1_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 3 Trigger input O */ +#endif +#define XMC_VADC_REQ_TR_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< VADC Trigger input P */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_wdt.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_wdt.h new file mode 100644 index 00000000..223af6e6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/inc/xmc_wdt.h @@ -0,0 +1,439 @@ +/** + * @file xmc_wdt.h + * @date 2015-08-06 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Documentation updates
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-08-06: + * - Bug fix in XMC_WDT_SetDebugMode() API, Wrong register is being configured.
+ * @endcond + */ + +#ifndef XMC_WDT_H +#define XMC_WDT_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_common.h" +#include "xmc_scu.h" +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup WDT + * @brief Watchdog driver for the XMC microcontroller family. + * + * The watchdog unit (WDT) improves the system integrity, by triggering the system reset request to bring the system + * back from the unresponsive state to normal operation. + * + * This LLD provides the Configuration structure XMC_WDT_CONFIG_t and initialization function XMC_WDT_Init().\n + * It can be used to: + * -# Start or Stop the watchdog timer. (XMC_WDT_Start() and XMC_WDT_Stop()) + * -# Service the watchdog timer. (XMC_WDT_Service()) + * -# Configure the service window upper bound and lower bound timing values. (XMC_WDT_SetWindowBounds()) + * -# Enable the generation of the pre-warning event for the first overflow of the timer. (XMC_WDT_SetMode()) + * -# Clear the pre-warning alarm event. It is mandatory to clear the flag during pre-warning alarm ISR, to stop + generating reset request for the second overflow of the timer. (XMC_WDT_ClearAlarm()) + * -# Suspend the watchdog timer during Debug HALT mode. (XMC_WDT_SetDebugMode()) + * -# Configure service indication pulse width.(XMC_WDT_SetServicePulseWidth()) + * + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#define XMC_WDT_MAGIC_WORD (0xABADCAFEU) /* Magic word to be written in Service Register (SRV), + to service or feed the watchdog. */ + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/** + * Defines working modes for watchdog. Use type XMC_WDT_MODE_t for this enum. + */ +typedef enum XMC_WDT_MODE +{ + XMC_WDT_MODE_TIMEOUT = (uint32_t)0x0 << WDT_CTR_PRE_Pos, /**< Generates reset request as soon as the timer overflow + occurs. */ + XMC_WDT_MODE_PREWARNING = (uint32_t)0x1 << WDT_CTR_PRE_Pos /**< Generates an alarm event for the first overflow. And + reset request after subsequent overflow, if not + serviced after first overflow. */ +} XMC_WDT_MODE_t; + +/** + * Defines debug behaviour of watchdog when the CPU enters HALT mode. Use type XMC_WDT_DEBUG_MODE_t for this enum. + */ +typedef enum XMC_WDT_DEBUG_MODE +{ + XMC_WDT_DEBUG_MODE_STOP = (uint32_t)0x0 << WDT_CTR_DSP_Pos, /**< Watchdog counter is paused during debug halt. */ + XMC_WDT_DEBUG_MODE_RUN = (uint32_t)0x1 << WDT_CTR_DSP_Pos /**< Watchdog counter is not paused during debug halt. */ +} XMC_WDT_DEBUG_MODE_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + /* Anonymous structure/union guard start */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Structure for initializing watchdog timer. Use type XMC_WDT_CONFIG_t for this structure. + */ +typedef struct XMC_WDT_CONFIG +{ + uint32_t window_upper_bound; /**< Upper bound for service window (WUB). Reset request is generated up on overflow of + timer. ALways upper bound value has to be more than lower bound value. If it is set + lower than WLB, triggers a system reset after timer crossed upper bound value.\n + Range: [0H to FFFFFFFFH] */ + uint32_t window_lower_bound; /**< Lower bound for servicing window (WLB). Setting the lower bound to 0H disables the + window mechanism.\n + Range: [0H to FFFFFFFFH] */ + union + { + struct + { + uint32_t : 1; + uint32_t prewarn_mode : 1; /**< Pre-warning mode (PRE). This accepts boolean values as input. */ + uint32_t : 2; + uint32_t run_in_debug_mode : 1; /**< Watchdog timer behaviour during debug (DSP). This accepts boolean values as input. */ + uint32_t : 3; + uint32_t service_pulse_width : 8; /**< Service Indication Pulse Width (SPW). Generated Pulse width is of (SPW+1), + in fwdt cycles.\n + Range: [0H to FFH] */ + uint32_t : 16; + }; + uint32_t wdt_ctr; /* Value of operation mode control register (CTR). It’s bit fields are represented by above + union members. */ + }; +} XMC_WDT_CONFIG_t; +/* Anonymous structure/union guard end */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * API PROTOTYPES + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * \if XMC4 + * Enables watchdog clock and releases watchdog reset.\n + * \endif + * \if XMC1 + * Enables watchdog clock.\n + * \endif + * \par + * This API is invoked by XMC_WDT_Init() and therefore no need to call it explicitly during watchdog initialization + * sequence. Invoke this API to enable watchdog once again if the watchdog is disabled by invoking XMC_WDT_Disable(). + * + * \parNote:
+ * \if XMC4 + * 1. It is required to configure the watchdog, again after invoking XMC_WDT_Disable(). Since all the registers are + * reset with default values. + * \endif + * \if XMC1 + * 1. Not required to configure the watchdog again after invoking XMC_WDT_Disable(). Since the registers retains with + * the configured values. + * \endif + * \parRelated APIs:
+ * XMC_WDT_Init(), XMC_WDT_Disable() + */ +void XMC_WDT_Enable(void); + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * \if XMC4 + * Disables the clock and resets watchdog timer.\n + * \endif + * \if XMC1 + * Disables the clock to the watchdog timer.\n + * \endif + * + * \parNote:
+ * \if XMC4 + * 1. Resets the registers with default values. So XMC_WDT_Init() has to be invoked again to configure the watchdog. + * \endif + * \if XMC1 + * 1. After invoking XMC_WDT_Disable(), all register values are displayed with 0F in debugger. Once enabled by + calling XMC_WDT_Enable(), previous configured register values are displayed. No need to invoke XMC_WDT_Init() + again. + * \endif + * \parRelated APIs:
+ * XMC_WDT_Enable() + */ +void XMC_WDT_Disable(void); + +/** + * @param config pointer to a constant watchdog configuration data structure. Refer data structure XMC_WDT_CONFIG_t + * for detail. + * + * @return None + * + * \parDescription:
+ * Initializes and configures watchdog with configuration data pointed by \a config.\n + * \par + * It invokes XMC_WDT_Enable() to enable clock and release reset. Then configures the lower and upper window bounds, + * working mode (timeout/pre-warning), debug behaviour and service request indication pulse width. + * + * \parNote:
+ * 1. With out invoking this XMC_WDT_Init() or XMC_WDT_Enable(), invocation of other APIs like XMC_WDT_SetWindowBounds(), + * XMC_WDT_SetMode(), XMC_WDT_SetServicePulseWidth(), XMC_WDT_SetDebugMode(), XMC_WDT_Start(), XMC_WDT_GetCounter(), + * XMC_WDT_Service(), XMC_WDT_ClearAlarm() has no affect. + */ +void XMC_WDT_Init(const XMC_WDT_CONFIG_t *const config); + +/** + * @param lower_bound specifies watchdog window lower bound in terms of watchdog clock (fWDT) cycles. + * Range: [0H to FFFFFFFFH]. + * @param upper_bound specifies watchdog window upper bound in terms of watchdog clock (fWDT) cycles. + * Range: [0H to FFFFFFFFH]. + * + * @return None + * + * \parDescription:
+ * Sets watchdog window lower and upper bounds by updating WLB and WUB registers.\n + * \par + * Window lower and upper bounds are set during initialization in XMC_WDT_Init(). Invoke this API to alter the values as + * needed later in the program. This upper bound and lower bound can be calculated by using the below formula\n + * upper_bound or lower_bound = desired_boundary_time(sec) * fwdt(hz) + * + * \parNote: + * 1. Always ensure that upper_bound is greater than the lower_bound value. If not, whenever timer crosses the + * upper_bound value it triggers the reset(wdt_rst_req) of the controller. + */ +__STATIC_INLINE void XMC_WDT_SetWindowBounds(uint32_t lower_bound, uint32_t upper_bound) +{ + WDT->WLB = lower_bound; + WDT->WUB = upper_bound; +} + +/** + * @param mode is one of the working modes of the watchdog timer, i.e timeout or pre-warning. Refer @ref XMC_WDT_MODE_t + * for valid values. + * + * @return None + * + * \parDescription:
+ * Sets watchdog working mode (timeout or pre-warning) by updating PRE bit of CTR register.\n + * \par + * The working mode is set during initialization in XMC_WDT_Init(). Invoke this API to alter the mode as needed later in + * the program. + */ +__STATIC_INLINE void XMC_WDT_SetMode(XMC_WDT_MODE_t mode) +{ + WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_PRE_Msk) | (uint32_t)mode; +} + +/** + * @param service_pulse_width specifies Service indication pulse width in terms of fwdt. + * Range: [0H – FFH]. + * @return None + * + * \parDescription:
+ * Sets service indication pulse width by updating SPW bit field of CTR register.\n + * \par + * The service indication pulse (with width service_pulse_width + 1 in fwdt cycles) is generated on successful servicing + * or feeding of watchdog. The pulse width is initially set during initialization in XMC_WDT_Init(). Invoke this API to + * alter the width as needed later in the program. + */ +__STATIC_INLINE void XMC_WDT_SetServicePulseWidth(uint8_t service_pulse_width) +{ + WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_SPW_Msk) | ((uint32_t)service_pulse_width << WDT_CTR_SPW_Pos); +} + +/** + * @param debug_mode running state of watchdog during debug halt mode. Refer @ref XMC_WDT_DEBUG_MODE_t for + * valid values. + * + * @return None + * + * \parDescription:
+ * Sets debug behaviour of watchdog by modifying DSP bit of CTR register.\n + * \par + * Depending upon DSP bit, the watchdog timer stops when CPU is in HALT mode. The debug behaviour is initially set as + * XMC_WDT_DEBUG_MODE_STOP during initialization in XMC_WDT_Init(). Invoke this API to change the debug behaviour as + * needed later in the program. + */ +__STATIC_INLINE void XMC_WDT_SetDebugMode(const XMC_WDT_DEBUG_MODE_t debug_mode) +{ + WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_DSP_Msk) | (uint32_t)debug_mode; +} + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Start the watchdog timer by setting ENB bit of CTR register.\n + * \par + * Invoke this API to start the watchdog after initialization, or to resume the watchdog when + * paused by invoking XMC_WDT_Stop(). + * + * \parRelated APIs:
+ * XMC_WDT_Init(), XMC_WDT_Stop() + */ +__STATIC_INLINE void XMC_WDT_Start(void) +{ + WDT->CTR |= (uint32_t)WDT_CTR_ENB_Msk; +} + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Pauses watchdog timer by resetting ENB bit of CTR register.\n + * \par + * Invoke this API to pause the watchdog as needed in the program e.g. debugging through software control. + * + * \parRelated APIs:
+ * XMC_WDT_Init(), XMC_WDT_Stop() + */ +__STATIC_INLINE void XMC_WDT_Stop(void) +{ + WDT->CTR &= (uint32_t)~WDT_CTR_ENB_Msk; +} + +/** + * @param None + * + * @return uint32_t Current count value of watchdog timer register (TIM). + * Range: [0H to FFFFFFFFH] + * + * \parDescription:
+ * Reads current count of timer register (TIM).\n + * \par + * Invoke this API before servicing or feeding the watchdog to check whether count is between lower and upper + * window bounds. + * + * \parRelated APIs:
+ * XMC_WDT_Service() + */ +__STATIC_INLINE uint32_t XMC_WDT_GetCounter(void) +{ + return WDT->TIM; +} + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Services or feeds the watchdog by writing the Magic word in SRV register.\n + * \par + * Service watchdog when count value of watchdog timer is between lower and upper window bounds. Successful servicing + * will reset watchdog timer (TIM register) to 0H and generate service indication pulse. + * + * \parNote:
+ * 1. invoking this API when count value of watchdog timer is less than window lower bound results + * wrong servicing and immediately triggers reset request. + * + * \parRelated APIs:
+ * XMC_WDT_GetCounter(), XMC_WDT_SetWindowBounds(), XMC_WDT_SetServicePulseWidth() + */ +__STATIC_INLINE void XMC_WDT_Service(void) +{ + WDT->SRV = XMC_WDT_MAGIC_WORD; +} + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Clears pre-warning alarm by setting ALMC bit in WDTCLR register.\n + * \par + * In pre-warning mode, first overflow of the timer upper window bound fires the pre-warning alarm. XMC_WDT_ClearAlarm() + * must be invoked to clear the alarm alarm. After clearing of the alarm, watchdog timer must be serviced within valid + * time window. Otherwise watchdog timer triggers the reset request up on crossing the upper bound value in a subsequent + * cycle. + * + * \parRelated APIs:
+ * XMC_WDT_Service(), XMC_WDT_SetMode() + */ +__STATIC_INLINE void XMC_WDT_ClearAlarm(void) +{ + WDT->WDTCLR = WDT_WDTCLR_ALMC_Msk; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XMC_WDT_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_eru.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_eru.c new file mode 100644 index 00000000..0f316c51 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_eru.c @@ -0,0 +1,84 @@ +/** + * @file xmc4_eru.c + * @date 2015-02-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * @endcond + */ +#include "xmc_eru.h" + +#if UC_FAMILY == XMC4 +#include "xmc_scu.h" + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ +/* Enable the clock and De-assert the ERU module from the reset state. */ +void XMC_ERU_Enable(XMC_ERU_t *const eru) +{ +#if defined(XMC_ERU1) + if (eru == XMC_ERU1) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ERU1); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ERU1); + } +#else + XMC_UNUSED_ARG(eru); + #endif +} + +/* Disable the clock and Reset the ERU module. */ +void XMC_ERU_Disable(XMC_ERU_t *const eru) +{ +#if defined(XMC_ERU1) + if (eru == XMC_ERU1) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ERU1); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ERU1); + #endif + } +#else + XMC_UNUSED_ARG(eru); +#endif +} + +#endif /* if( UC_FAMILY == XMC1 ) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_flash.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_flash.c new file mode 100644 index 00000000..3ad136dc --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_flash.c @@ -0,0 +1,512 @@ +/** + * @file xmc4_flash.c + * @date 2016-01-08 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-10: + * - Initial
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API + * + * 2015-08-17: + * - Added the below API's to the public interface. + * 1. XMC_FLASH_Reset + * 2. XMC_FLASH_ErasePhysicalSector + * 3. XMC_FLASH_EraseUCB + * 4. XMC_FLASH_ResumeProtection + * 5. XMC_FLASH_RepairPhysicalSector + * + * 2016-01-08: + * - Wait until operation is finished for the next functions: + * 1. XMC_FLASH_InstallProtection + * 2. XMC_FLASH_ConfirmProtection + * 3. XMC_FLASH_ProgramPage + * 4. XMC_FLASH_EraseSector + * 5. XMC_FLASH_ErasePhysicalSector + * 6. XMC_FLASH_EraseUCB + * - Fix XMC_FLASH_VerifyReadProtection and XMC_FLASH_VerifyWriteProtection + * + * @endcond + * + */ + +#include "xmc_flash.h" + +#if UC_FAMILY == XMC4 + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#define XMC_FLASH_PROTECTION_CONFIGURATION_WORDS (8UL) /* Used to upadte the assembly buffer during protection + configuration */ +#define XMC_FLASH_PROT_CONFIRM_OFFSET (512UL) /* Offset address for UCB page */ +#define XMC_FLASH_PROT_CONFIRM_WORDS (4UL) +#define XMC_FLASH_PROT_CONFIRM_CODE (0x8AFE15C3UL) + +/********************************************************************************************************************* + * LOCAL FUNCTIONS + ********************************************************************************************************************/ +void XMC_FLASH_lEnterPageModeCommand(void); +void XMC_FLASH_lLoadPageCommand(uint32_t low_word, uint32_t high_word); +void XMC_FLASH_lWritePageCommand(uint32_t *page_start_address); +void XMC_FLASH_lWriteUCBPageCommand(uint32_t *page_start_address); +void XMC_FLASH_lEraseSectorCommand(uint32_t *sector_start_address); +void XMC_FLASH_lDisableSectorWriteProtectionCommand(uint32_t user, uint32_t password_0, uint32_t password_1); +void XMC_FLASH_lDisableReadProtectionCommand(uint32_t password_0, uint32_t password_1); +void XMC_FLASH_lRepairPhysicalSectorCommand(void); +void XMC_FLASH_lErasePhysicalSectorCommand(uint32_t *sector_start_address); +void XMC_FLASH_lClearStatusCommand(void); + +/* + * Command to program the PFLASH in to page mode, so that assembly buffer is used + */ +void XMC_FLASH_lEnterPageModeCommand(void) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = (uint32_t)0x50U; +} + +/* + * Command to load the data into the page assembly buffer + */ +void XMC_FLASH_lLoadPageCommand(uint32_t low_word, uint32_t high_word) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x55f0U); + *address = low_word; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x55f4U); + *address = high_word; +} + +/* + * Command to start the programming of one page with data from the assembly buffer + */ +void XMC_FLASH_lWritePageCommand(uint32_t *page_start_address) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xa0U; + address = page_start_address; + *address = 0xaaU; +} + +/* + * Command to start the programming of UCB page with data from the assembly buffer + */ +void XMC_FLASH_lWriteUCBPageCommand(uint32_t *page_start_address) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xc0U; + address = page_start_address; + *address = 0xaaU; +} + +/* + * Command to erase sector which is starting with the specified address + */ +void XMC_FLASH_lEraseSectorCommand(uint32_t *sector_start_address) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0x80U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = sector_start_address; + *address = 0x30U; +} + + +/* + * Command to temporarily disables the write protection belonging to the the USER specified, when passwords match with their + * configured values + */ +void XMC_FLASH_lDisableSectorWriteProtectionCommand(uint32_t user, uint32_t password_0, uint32_t password_1) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x553cU); + *address = user; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = password_0; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = password_1; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5558U); + *address = 0x05U; +} + +/* + * Command to temporarily disables the read protection along with write protection, when passwords match with their + * configured values + */ +void XMC_FLASH_lDisableReadProtectionCommand(uint32_t password_0, uint32_t password_1) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x553cU); + *address = 0x00U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = password_0; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = password_1; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5558U); + *address = 0x08U; +} + +/* + * Command to clear FSR.PROG and FSR.ERASE and the error flags in FSR such as PFOPER, SQER, PROER, PFDBER, ORIER, VER + */ +void XMC_FLASH_lClearStatusCommand(void) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xf5U; +} + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + + /* + * This API shall clear Program, erase and error flags(PFOPER, SQER, PROER, PFDBER, ORIER, VER) of FSR register. + */ +void XMC_FLASH_ClearStatus(void) +{ + XMC_FLASH_lClearStatusCommand(); +} + +/* + * This API returns the FSR register value + */ +uint32_t XMC_FLASH_GetStatus(void) +{ + return FLASH0->FSR; +} + +/* + * This API enables the events which required to trigger the ISR + */ +void XMC_FLASH_EnableEvent(const uint32_t event_msk) +{ + FLASH0->FCON |= event_msk; +} + +/* + * This API disables the event generation + */ +void XMC_FLASH_DisableEvent(const uint32_t event_msk) +{ + FLASH0->FCON &= ~event_msk; +} + +/* + * This API write the PFLASH page + */ +void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data) +{ + uint32_t idx; + + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lEnterPageModeCommand(); + + for (idx = 0U; idx < XMC_FLASH_WORDS_PER_PAGE; idx += 2U) + { + XMC_FLASH_lLoadPageCommand(data[idx], data[idx + 1U]); + } + + XMC_FLASH_lWritePageCommand(address); + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * This API erase the logical sector + */ +void XMC_FLASH_EraseSector(uint32_t *address) +{ + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lEraseSectorCommand(address); + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * Command to erase physical sector which is starting with the specified address + */ +void XMC_FLASH_lErasePhysicalSectorCommand(uint32_t *sector_start_address) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0x80U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = sector_start_address; + *address = 0x40U; +} + +/* + * Command to erase physical sector-4 which is starting with the specified address + * This command is only available if PROCON1.PRS = 1. + */ +void XMC_FLASH_lRepairPhysicalSectorCommand(void) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0x80U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = XMC_FLASH_PHY_SECTOR_4; + *address = 0x40U; +} + + /* + * This API erase the physical sector + */ +void XMC_FLASH_ErasePhysicalSector(uint32_t *address) +{ + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lErasePhysicalSectorCommand(address); + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * This API repair the physical sector + */ +void XMC_FLASH_RepairPhysicalSector(void) +{ + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lRepairPhysicalSectorCommand(); +} + +/* + * Command to erase UCB sector which is starting with the specified address + */ +void XMC_FLASH_EraseUCB(uint32_t *ucb_sector_start_address) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0x80U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = ucb_sector_start_address; + *address = 0xc0U; + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * Command to reset the status of the PFLASH + */ +void XMC_FLASH_Reset(void) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xf0U; +} + +/* + * This API install the global read and sector write protection for the specified user + */ +void XMC_FLASH_InstallProtection(uint8_t user, + uint32_t protection_mask, + uint32_t password_0, + uint32_t password_1) +{ + uint32_t idx; + + XMC_ASSERT(" XMC_FLASH_ConfigureProtection: User level out of range", (user < 3U)) + + XMC_FLASH_lEnterPageModeCommand(); + + XMC_FLASH_lLoadPageCommand(protection_mask, 0UL); + XMC_FLASH_lLoadPageCommand(protection_mask, 0UL); + XMC_FLASH_lLoadPageCommand(password_0, password_1); + XMC_FLASH_lLoadPageCommand(password_0, password_1); + + for (idx = 0U; idx < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_PROTECTION_CONFIGURATION_WORDS); idx += 2U) + { + XMC_FLASH_lLoadPageCommand(0UL, 0UL); + } + + XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB0 + (user * XMC_FLASH_BYTES_PER_UCB))); + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * This API confirm the protection. So that This sectors are locked with the specified protection. + */ +void XMC_FLASH_ConfirmProtection(uint8_t user) +{ + uint32_t idx; + + XMC_ASSERT(" XMC_FLASH_ConfirmProtection: User level out of range", (user < 3U)) + + XMC_FLASH_lEnterPageModeCommand(); + + XMC_FLASH_lLoadPageCommand(XMC_FLASH_PROT_CONFIRM_CODE, 0U); + XMC_FLASH_lLoadPageCommand(XMC_FLASH_PROT_CONFIRM_CODE, 0U); + + /* Fill the rest of page buffer with zeros*/ + for (idx = 0UL; idx < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_PROT_CONFIRM_WORDS); idx += 2U) + { + XMC_FLASH_lLoadPageCommand(0UL, 0UL); + } + + XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB0 + + (user * XMC_FLASH_BYTES_PER_UCB) + XMC_FLASH_PROT_CONFIRM_OFFSET)); + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * This API verify read protection configuration. And returns true if passwords are matching. + */ +bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1) +{ + bool status = false; + + /* Check if read protection is installed */ + if ((XMC_FLASH_GetStatus() & (uint32_t)XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED) != 0U) + { + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lDisableReadProtectionCommand(password_0, password_1); + + status = (bool)(XMC_FLASH_GetStatus() & (uint32_t)XMC_FLASH_STATUS_READ_PROTECTION_DISABLED_STATE); + } + + return status; +} + +/* + * This API verify sector write protection configuration. And returns true if passwords are matching for the + * specified user. + */ +bool XMC_FLASH_VerifyWriteProtection(uint32_t user, + uint32_t protection_mask, + uint32_t password_0, + uint32_t password_1) +{ + bool status = false; + uint32_t *flash_procon_ptr = (uint32_t *)(void*)(&(FLASH0->PROCON0) + user); + + XMC_ASSERT(" XMC_FLASH_VerifyWriteProtection: User level out of range", (user < 2U)) + + /* Check if write protection for selected user is installed */ + if ((XMC_FLASH_GetStatus() & (uint32_t)((uint32_t)1U << (uint32_t)((uint32_t)FLASH_FSR_WPROIN0_Pos + user))) != 0U) + { + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lDisableSectorWriteProtectionCommand(user, password_0, password_1); + + status = (bool)((XMC_FLASH_GetStatus() & (uint32_t)((uint32_t)1U << (uint32_t)((uint32_t)FLASH_FSR_WPRODIS0_Pos + user)))) && + (*flash_procon_ptr == (protection_mask & (uint32_t)(~(uint32_t)XMC_FLASH_PROTECTION_READ_GLOBAL))); + } + + return status; +} + +/* + * Command to enables the protection as it was configured + */ +void XMC_FLASH_ResumeProtection(void) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0x5eU; +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_gpio.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_gpio.c new file mode 100644 index 00000000..4c19ab14 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_gpio.c @@ -0,0 +1,105 @@ +/** + * @file xmc4_gpio.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * @endcond + * + */ + +#include "xmc_gpio.h" + +#if UC_FAMILY == XMC4 + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define PORT_PDR_Msk PORT0_PDR0_PD0_Msk +#define PORT_PDR_Size (4U) +#define PORT_HWSEL_Msk PORT0_HWSEL_HW0_Msk + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_GPIO_Init: Invalid port", XMC_GPIO_CHECK_PORT(port)); + XMC_ASSERT("XMC_GPIO_Init: Invalid mode", XMC_GPIO_IsModeValid(config->mode)); + + /* Switch to input */ + port->IOCR[pin >> 2U] &= (uint32_t)~(PORT_IOCR_PC_Msk << (PORT_IOCR_PC_Size * (pin & 0x3U))); + + /* HW port control is disabled */ + port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U)); + + + /* Enable digital input */ + if (XMC_GPIO_CHECK_ANALOG_PORT(port)) + { + port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin); + } + else + { + /* Set output level */ + port->OMR = (uint32_t)config->output_level << pin; + + /* Set output driver strength */ + port->PDR[pin >> 3U] &= (uint32_t)~(PORT_PDR_Msk << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U))); + port->PDR[pin >> 3U] |= (uint32_t)config->output_strength << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U)); + } + + /* Set mode */ + port->IOCR[pin >> 2U] |= (uint32_t)config->mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U)); +} + +void XMC_GPIO_SetOutputStrength(XMC_GPIO_PORT_t *const port, const uint8_t pin, XMC_GPIO_OUTPUT_STRENGTH_t strength) +{ + XMC_ASSERT("XMC_GPIO_Init: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); + XMC_ASSERT("XMC_GPIO_Init: Invalid output strength", XMC_GPIO_CHECK_OUTPUT_STRENGTH(strength)); + + port->PDR[pin >> 3U] &= (uint32_t)~((uint32_t)PORT_PDR_Msk << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U))); + port->PDR[pin >> 3U] |= (uint32_t)strength << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U)); +} + +#endif /* UC_FAMILY == XMC4 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_rtc.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_rtc.c new file mode 100644 index 00000000..a7b03ad4 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_rtc.c @@ -0,0 +1,170 @@ +/** + * @file xmc4_rtc.c + * @date 2016-03-09 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2016-03-09: + * - Optimize write only registers + * + * @endcond + * + */ + +/** + * @brief RTC driver for XMC microcontroller family. + * + */ + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ +#include + +#if UC_FAMILY == XMC4 +#include + +/********************************************************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ + +/* + * Enables RTC peripheral for programming its registers + */ +void XMC_RTC_Enable(void) +{ + XMC_SCU_HIB_EnableHibernateDomain(); +} + +/* + * Disables RTC peripheral for programming its registers + */ +void XMC_RTC_Disable(void) +{ + /* + * Empty because disabling the hibernate + * domain is not done intentionally. + */ +} + +/* + * Checks RTC peripheral is enabled for programming to its registers + */ +bool XMC_RTC_IsEnabled(void) +{ + return XMC_SCU_HIB_IsHibernateDomainEnabled(); +} + +/* + * Initialize the RTC peripheral + */ +XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config) +{ + if (XMC_RTC_IsRunning() == false) + { + if (XMC_SCU_HIB_IsHibernateDomainEnabled() == false) + { + XMC_SCU_HIB_EnableHibernateDomain(); + } + + XMC_RTC_SetPrescaler(config->prescaler); + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM0 = config->time.raw0; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM1 = config->time.raw1; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM0 = config->alarm.raw0; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM1 = config->alarm.raw1; + } + return XMC_RTC_STATUS_OK; +} + +/* + * Enable RTC periodic and alarm event(s) + */ +void XMC_RTC_EnableEvent(const uint32_t event) +{ + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->MSKSR |= event; +} + +/* + * Disable RTC periodic and alarm event(s) + */ +void XMC_RTC_DisableEvent(const uint32_t event) +{ + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->MSKSR &= ~event; +} + +/* + * Clear RTC periodic and alarm event(s) + */ +void XMC_RTC_ClearEvent(const uint32_t event) +{ + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->CLRSR = event; +} + +#endif /* UC_FAMILY == XMC4 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_scu.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_scu.c new file mode 100644 index 00000000..28dfec1d --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc4_scu.c @@ -0,0 +1,1820 @@ +/** + * @file xmc4_scu.c + * @date 2016-06-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - XMC_ASSERT() hanging issues have fixed.
+ * - Line indentation aligned with 120 characters.
+ * + * 2015-06-20: + * - XMC_SCU_INTERRUPT_EnableEvent,XMC_SCU_INTERRUPT_DisableEvent, + * - XMC_SCU_INTERRUPT_TriggerEvent,XMC_SCU_INTERUPT_GetEventStatus, + * - XMC_SCU_INTERRUPT_ClearEventStatus are added + * - Added Weak implementation for OSCHP_GetFrequency() + * + * 2015-11-30: + * - Documentation improved
+ * - Following API functionalities are improved + * XMC_SCU_CLOCK_GatePeripheralClock, XMC_SCU_CLOCK_UngatePeripheralClock, XMC_SCU_CLOCK_IsPeripheralClockGated + * XMC_SCU_RESET_AssertPeripheralReset, XMC_SCU_RESET_DeassertPeripheralReset, XMC_SCU_RESET_IsPeripheralResetAsserted + * + * 2015-12-08: + * - XMC_SCU_GetTemperature renamed to XMC_SCU_GetTemperatureMeasurement + * + * 2016-03-09: + * - Optimize write only registers + * - Added XMC_SCU_HIB_SetPinMode + * - Added XMC_SCU_HIB_GetHibernateControlStatus, + * XMC_SCU_HIB_GetEventStatus, XMC_SCU_HIB_ClearEventStatus, XMC_SCU_HIB_TriggerEvent, + * XMC_SCU_HIB_EnableEvent, XMC_SCU_HIB_DisableEvent + * - Added XMC_SCU_HIB_SetWakeupTriggerInput, XMC_SCU_HIB_SetPinMode, XMC_SCU_HIB_SetOutputPinLevel, + * XMC_SCU_HIB_SetInput0, XMC_SCU_HIB_EnterHibernateState + * + * 2016-04-06: + * - Fixed XMC_SCU_ReadFromRetentionMemory functionality + * + * 2016-05-19: + * - Changed XMC_SCU_CLOCK_StartSystemPll to avoid using floating point calculation which might have an impact on interrupt latency if ISR uses also the FPU + * - Added XMC_SCU_CLOCK_IsLowPowerOscillatorStable() and XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() + * - Added XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus() + * - Added XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus() + * + * 2016-06-15: + * - Added XMC_SCU_HIB_EnterHibernateStateEx() which allows to select between external or internal hibernate mode. This last mode only available in XMC44, XMC42 and XMC41 series. + * - Extended wakeup hibernate events using LPAC wakeup on events. Only available in XMC44, XMC42 and XMC41 series + * - Added LPAC APIs. Only available in XMC44, XMC42 and XMC41 series. + * + * @endcond + * + */ + +/** + * + * @brief SCU low level driver API prototype definition for XMC4 family of microcontrollers. + * + * Detailed description of file:
+ * APIs provided in this file cover the following functional blocks of SCU:
+ * -- GCU (APIs prefixed with XMC_SCU_GEN_)
+ * ------ Temperature Monitoring, Bootmode selection, CCU Start, Comparator configuration etc
+ * -- CCU (APIs prefixed with XMC_SCU_CLOCK_)
+ * ------ Clock sources init, Clock tree init, Clock gating, Sleep Management etc
+ * -- RCU (APIs prefixed with XMC_SCU_RESET_)
+ * ------ Reset Init, Cause, Manual Reset Assert/Deassert
+ * -- INTERRUPT (APIs prefixed with XMC_SCU_INTERRUPT_)
+ * ------ Init, Manual Assert/Deassert, Acknowledge etc
+ * -- PARITY (APIs prefixed with XMC_SCU_PARITY_)
+ * ------ Init, Acknowledge etc
+ * -- HIBERNATION (APIs prefixed with XMC_SCU_HIB_)
+ * ------ Hibernation entry/exit config, entry/wakeup sequences, LPAC configuration etc
+ * -- TRAP (APIs prefixed with XMC_SCU_TRAP_)
+ * ------ Init, Enable/Disable, Acknowledge etc
+ * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +#if UC_FAMILY == XMC4 + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define FOSCREF (2500000UL) /**< Oscillator reference frequency (fOSCREF) monitored by Oscillator watchdog */ +#define FREQ_1MHZ (1000000UL) /**< Used during calculation. */ + +#ifndef OFI_FREQUENCY +#define OFI_FREQUENCY (24000000UL) /**< Fast internal backup clock source. */ +#endif + +#ifndef OSI_FREQUENCY +#define OSI_FREQUENCY (32768UL) /**< Internal slow clock source. */ +#endif + +#ifndef OSCHP_FREQUENCY +#define OSCHP_FREQUENCY (12000000U) /**< External crystal High Precision Oscillator. */ +#endif + +#define XMC_SCU_PLL_PLLSTAT_OSC_USABLE (SCU_PLL_PLLSTAT_PLLHV_Msk | \ + SCU_PLL_PLLSTAT_PLLLV_Msk | \ + SCU_PLL_PLLSTAT_PLLSP_Msk) /**< Used to verify the OSC frequency is + usable or not.*/ + +#define XMC_SCU_ORC_ADC_START_GROUP (0UL) /**< The ADC group whose channel input is compared by Out of Range + Comparator (ORC) to serves the purpose of overvoltage monitoring + for analog input pins of the chip and ORC start measurements from + this group number. */ +#define XMC_SCU_ORC_ADC_END_GROUP (1UL) /**< The ADC group whose channel input is compared by Out of Range + Comparator (ORC) to serves the purpose of overvoltage monitoring + for analog input pins of the chip and ORC end measurements at + this group number. */ +#define XMC_SCU_ORC_START_ADC_CHANNEL (6UL) /**< The ADC channel whose channel input is compared by Out of Range + Comparator (ORC) to serves the purpose of overvoltage monitoring + for analog input pins of the chip and ORC start measurements from + this channel number. */ +#define XMC_SCU_ORC_END_ADC_CHANNEL (7UL) /**< The ADC channel whose channel input is compared by Out of Range + Comparator (ORC) to serves the purpose of overvoltage monitoring + for analog input pins of the chip and ORC ends measurements at + this channel number. */ + +#define XMC_SCU_CHECK_GRPNUM(GROUP_NUM) (((GROUP_NUM) == XMC_SCU_ORC_ADC_START_GROUP) || \ + ((GROUP_NUM) == XMC_SCU_ORC_ADC_END_GROUP) ) /**< Used to verify whether + provided ADC group number lies + within specified ADC start and + end group number or not. */ + +#define XMC_SCU_CHECK_CHNUM(CH_NUM) (((CH_NUM) == XMC_SCU_ORC_START_ADC_CHANNEL) || \ + ((CH_NUM) == XMC_SCU_ORC_END_ADC_CHANNEL) ) /**< Used to verify whether + provided ADC channel number lies + within specified ADC start and + end channel number or not. */ + +#define XMC_SCU_INTERRUPT_EVENT_MAX (32U) /**< Maximum supported SCU events. */ + +#define SCU_HIBERNATE_HDCR_HIBIOSEL_Size (4U) + +#define SCU_HIBERNATE_OSCULCTRL_MODE_OSC_POWER_DOWN (0x2U) + +#define XMC_SCU_POWER_LSB13V (0.0058F) +#define XMC_SCU_POWER_LSB33V (0.0225F) + +/********************************************************************************************************************* + * LOCAL DATA + ********************************************************************************************************************/ +XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler_list[XMC_SCU_INTERRUPT_EVENT_MAX]; /**< For registering callback + functions on SCU event + occurrence. */ + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ + #if defined(UC_ID) +/* This is a non-weak function, which retrieves high precision external oscillator frequency. */ +__WEAK uint32_t OSCHP_GetFrequency(void) +{ + return (OSCHP_FREQUENCY); +} +#endif + +/* This is a local function used to generate the delay until register get updated with new configured value. */ +static void XMC_SCU_lDelay(uint32_t cycles); + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ +/* This is a local function used to generate the delay until register get updated with new configured value. */ +void XMC_SCU_lDelay(uint32_t delay) +{ + uint32_t i; + + SystemCoreClockUpdate(); + delay = delay * (uint32_t)(SystemCoreClock / FREQ_1MHZ); + + for (i = 0U; i < delay; ++i) + { + __NOP(); + } +} + +/* API to enable the SCU event */ +void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event) +{ + SCU_INTERRUPT->SRMSK |= (uint32_t)event; +} + +/* API to disable the SCU event */ +void XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event) +{ + SCU_INTERRUPT->SRMSK &= (uint32_t)~event; +} + +/* API to trigger the SCU event */ +void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event) +{ + SCU_INTERRUPT->SRSET |= (uint32_t)event; +} + +/* API to retrieve the SCU event status */ +XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus(void) +{ + return (SCU_INTERRUPT->SRRAW); +} + +/* API to clear the SCU event status */ +void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event) +{ + SCU_INTERRUPT->SRCLR = (uint32_t)event; +} + + +/* API to retrieve the currently deployed device bootmode */ +uint32_t XMC_SCU_GetBootMode(void) +{ + return (uint32_t)(SCU_GENERAL->STCON & SCU_GENERAL_STCON_SWCON_Msk); +} + +/* API to program a new device bootmode */ +void XMC_SCU_SetBootMode(const XMC_SCU_BOOTMODE_t bootmode) +{ + SCU_GENERAL->STCON = (uint32_t)bootmode; +} + +/* API to read from General purpose register */ +uint32_t XMC_SCU_ReadGPR(const uint32_t index) +{ + return (SCU_GENERAL->GPR[index]); +} + +/* API to write to GPR */ +void XMC_SCU_WriteGPR(const uint32_t index, const uint32_t data) +{ + SCU_GENERAL->GPR[index] = data; +} + +/* API to enable Out of Range Comparator(ORC) for a desired group and a desired channel input */ +void XMC_SCU_EnableOutOfRangeComparator(const uint32_t group, const uint32_t channel) +{ + XMC_ASSERT("XMC_SCU_EnableOutOfangeComparator:Wrong Group Number",XMC_SCU_CHECK_GRPNUM(group)); + XMC_ASSERT("XMC_SCU_EnableOutOfangeComparator:Wrong Channel Number",XMC_SCU_CHECK_CHNUM(channel)); + + SCU_GENERAL->GORCEN[group] |= (uint32_t)(1UL << channel); +} + +/* API to enable Out of Range Comparator(ORC) for a desired group and a desired channel input */ +void XMC_SCU_DisableOutOfRangeComparator(const uint32_t group, const uint32_t channel) +{ + XMC_ASSERT("XMC_SCU_DisableOutOfRangeComparator:Wrong Group Number",XMC_SCU_CHECK_GRPNUM(group)); + XMC_ASSERT("XMC_SCU_DisableOutOfRangeComparator:Wrong Channel Number",XMC_SCU_CHECK_CHNUM(channel)); + + SCU_GENERAL->GORCEN[group] &= (uint32_t)~(1UL << channel); +} + +/* API to calibrate temperature sensor */ +void XMC_SCU_CalibrateTemperatureSensor(uint32_t offset, uint32_t gain) +{ + SCU_GENERAL->DTSCON = ((uint32_t)(offset << SCU_GENERAL_DTSCON_OFFSET_Pos) | + (uint32_t)(gain << SCU_GENERAL_DTSCON_GAIN_Pos) | + (uint32_t)(0x4UL << SCU_GENERAL_DTSCON_REFTRIM_Pos) | + (uint32_t)(0x8UL << SCU_GENERAL_DTSCON_BGTRIM_Pos)); +} +/* API to enable die temperature measurement by powering the DTS module. */ +void XMC_SCU_EnableTemperatureSensor(void) +{ + SCU_GENERAL->DTSCON &= (uint32_t)~(SCU_GENERAL_DTSCON_PWD_Msk); +} + +/* API to disable die temperature measurement by powering the DTS module off. */ +void XMC_SCU_DisableTemperatureSensor(void) +{ + SCU_GENERAL->DTSCON |= (uint32_t)SCU_GENERAL_DTSCON_PWD_Msk; +} + +/* API to provide the die temperature sensor power status. */ +bool XMC_SCU_IsTemperatureSensorEnabled(void) +{ + return ((SCU_GENERAL->DTSCON & SCU_GENERAL_DTSCON_PWD_Msk) == 0U); +} + +/* API to check if the die temperature sensor is ready to start a measurement. */ +bool XMC_SCU_IsTemperatureSensorReady(void) +{ + return ((SCU_GENERAL->DTSSTAT & SCU_GENERAL_DTSSTAT_RDY_Msk) != 0U); +} +/* API to start device temperature measurements */ +XMC_SCU_STATUS_t XMC_SCU_StartTemperatureMeasurement(void) +{ + XMC_SCU_STATUS_t status = XMC_SCU_STATUS_OK; + + if (XMC_SCU_IsTemperatureSensorEnabled() == false) + { + status = XMC_SCU_STATUS_ERROR; + } + + if (XMC_SCU_IsTemperatureSensorBusy() == true) + { + status = XMC_SCU_STATUS_BUSY; + } + + /* And start the measurement */ + SCU_GENERAL->DTSCON |= (uint32_t)SCU_GENERAL_DTSCON_START_Msk; + + return (status); +} + +/* API to retrieve the temperature measured */ +uint32_t XMC_SCU_GetTemperatureMeasurement(void) +{ + uint32_t temperature; + + if (XMC_SCU_IsTemperatureSensorEnabled() == false) + { + temperature = 0x7FFFFFFFUL; + } + else + { + temperature = (uint32_t)((SCU_GENERAL->DTSSTAT & SCU_GENERAL_DTSSTAT_RESULT_Msk) >> SCU_GENERAL_DTSSTAT_RESULT_Pos); + } + + return ((uint32_t)temperature); +} + +/* API to know whether Die temperature sensor is busy */ +bool XMC_SCU_IsTemperatureSensorBusy(void) +{ + return ((SCU_GENERAL->DTSSTAT & SCU_GENERAL_DTSSTAT_BUSY_Msk) != 0U); +} + + +#if defined(SCU_GENERAL_DTEMPLIM_LOWER_Msk) && defined(SCU_GENERAL_DTEMPLIM_UPPER_Msk) +/* API to determine if device temperature has gone past the ceiling */ +bool XMC_SCU_HighTemperature(void) +{ + bool ret_val; + uint32_t dtscon; + uint32_t dtempalarm; + dtscon = SCU_GENERAL->DTSCON; + dtscon = dtscon & SCU_GENERAL_DTSCON_PWD_Msk; + + ret_val = false; + + /* Any audit makes sense only if the DTS were powered up */ + if(dtscon) + { + /* Powered down - return false */ + ret_val = false; + } + else + { + /* Powered up - Read the overflow bit and decide accordingly*/ + dtempalarm = SCU_GENERAL->DTEMPALARM; + dtempalarm = dtempalarm & SCU_GENERAL_DTEMPALARM_OVERFL_Msk; + + if(dtempalarm) + { + ret_val = true; + } + else + { + ret_val = false; + } + } + return (ret_val); +} + +/* API to program raw values of temperature limits into the DTS */ +void XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp) +{ + /* Power up the DTS module */ + SCU_GENERAL->DTSCON &= (uint32_t)~SCU_GENERAL_DTSCON_PWD_Msk; + SCU_GENERAL->DTEMPLIM = 0; + SCU_GENERAL->DTEMPLIM = (lower_temp & SCU_GENERAL_DTEMPLIM_LOWER_Msk); + SCU_GENERAL->DTEMPLIM |= (uint32_t)((upper_temp & SCU_GENERAL_DTEMPLIM_LOWER_Msk) << SCU_GENERAL_DTEMPLIM_UPPER_Pos); +} + +/* API to determine if device temperature has gone below the stipulated limit */ +bool XMC_SCU_LowTemperature(void) +{ + bool ret_val; + uint32_t dtscon; + uint32_t dtempalarm; + dtscon = SCU_GENERAL->DTSCON; + dtscon = dtscon & SCU_GENERAL_DTSCON_PWD_Msk; + + ret_val = false; + + /* Any audit makes sense only if the DTS were powered up */ + if(dtscon) + { + /* Powered down - return false */ + ret_val = false; + } + else + { + /* Powered up - Read the overflow bit and decide accordingly*/ + dtempalarm = SCU_GENERAL->DTEMPALARM; + dtempalarm = dtempalarm & SCU_GENERAL_DTEMPALARM_UNDERFL_Msk; + + if(dtempalarm) + { + ret_val = true; + } + else + { + ret_val = false; + } + } + + return (ret_val); +} +#endif + +/* API to write into Retention memory in hibernate domain */ +void XMC_SCU_WriteToRetentionMemory(uint32_t address, uint32_t data) +{ + uint32_t rmacr; + + /* Get the address right */ + rmacr = (uint32_t)((address << SCU_GENERAL_RMACR_ADDR_Pos) & (uint32_t)SCU_GENERAL_RMACR_ADDR_Msk); + + /* Transfer from RMDATA to Retention memory */ + rmacr |= (uint32_t)(SCU_GENERAL_RMACR_RDWR_Msk); + + /* Write desired data into RMDATA register */ + SCU_GENERAL->RMDATA = data; + + /* Write address & direction of transfer into RMACR register */ + SCU_GENERAL->RMACR = rmacr; + + /* Wait until the update of RMX register in hibernate domain is completed */ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_RMX_Msk) + { + } +} + +/* API to read from Retention memory in hibernate domain */ +uint32_t XMC_SCU_ReadFromRetentionMemory(uint32_t address) +{ + uint32_t rmacr; + + /* Get the address right */ + rmacr = ((uint32_t)(address << SCU_GENERAL_RMACR_ADDR_Pos) & (uint32_t)SCU_GENERAL_RMACR_ADDR_Msk); + + /* Transfer from RMDATA to Retention memory */ + rmacr &= ~((uint32_t)(SCU_GENERAL_RMACR_RDWR_Msk)); + + /* Writing an adress & direction of transfer into RMACR register */ + SCU_GENERAL->RMACR = rmacr; + + /* Wait until the update of RMX register in hibernate domain is completed */ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_RMX_Msk) + { + } + + return (SCU_GENERAL->RMDATA); +} + +/* API to initialize the clock tree */ +void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config) +{ + XMC_ASSERT("", config->fsys_clkdiv != 0); + XMC_ASSERT("", config->fcpu_clkdiv != 0); + XMC_ASSERT("", config->fccu_clkdiv != 0); + XMC_ASSERT("", config->fperipheral_clkdiv != 0); + XMC_ASSERT("", ((config->syspll_config.p_div != 0) && + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL)) || + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR)); + XMC_ASSERT("", ((config->syspll_config.n_div != 0) && + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL)) || + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR)); + XMC_ASSERT("", (config->syspll_config.k_div != 0) && + ((config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL) || + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR))); + XMC_ASSERT("", ((config->fsys_clksrc == XMC_SCU_CLOCK_SYSCLKSRC_PLL) || + (config->fsys_clksrc == XMC_SCU_CLOCK_SYSCLKSRC_OFI)) && + ((config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL) || + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR))); + XMC_ASSERT("", ((config->fstdby_clksrc == XMC_SCU_HIB_STDBYCLKSRC_OSCULP) && (config->enable_osculp == true)) || + (config->fstdby_clksrc != XMC_SCU_HIB_STDBYCLKSRC_OSCULP)); + XMC_ASSERT("", ((config->syspll_config.clksrc == XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP) && + (config->enable_oschp == true)) || (config->syspll_config.clksrc != XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP)); + + XMC_SCU_CLOCK_SetSystemClockSource(XMC_SCU_CLOCK_SYSCLKSRC_OFI); + + XMC_SCU_HIB_EnableHibernateDomain(); + if (config->enable_osculp == true) + { + XMC_SCU_CLOCK_EnableLowPowerOscillator(); + while(XMC_SCU_CLOCK_IsLowPowerOscillatorStable() == false); + } + XMC_SCU_HIB_SetStandbyClockSource(config->fstdby_clksrc); + + XMC_SCU_CLOCK_SetBackupClockCalibrationMode(config->calibration_mode); + + XMC_SCU_CLOCK_SetSystemClockDivider((uint32_t)config->fsys_clkdiv); + XMC_SCU_CLOCK_SetCpuClockDivider((uint32_t)config->fcpu_clkdiv); + XMC_SCU_CLOCK_SetCcuClockDivider((uint32_t)config->fccu_clkdiv); + XMC_SCU_CLOCK_SetPeripheralClockDivider((uint32_t)config->fperipheral_clkdiv); + + if (config->enable_oschp == true) + { + XMC_SCU_CLOCK_EnableHighPerformanceOscillator(); + while(XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() == false); + } + + if (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_DISABLED) + { + XMC_SCU_CLOCK_DisableSystemPll(); + } + else + { + + XMC_SCU_CLOCK_EnableSystemPll(); + XMC_SCU_CLOCK_StartSystemPll(config->syspll_config.clksrc, + config->syspll_config.mode, + (uint32_t)config->syspll_config.p_div, + (uint32_t)config->syspll_config.n_div, + (uint32_t)config->syspll_config.k_div); + } + + /* use SYSPLL? */ + if (config->fsys_clksrc == XMC_SCU_CLOCK_SYSCLKSRC_PLL) + { + XMC_SCU_CLOCK_SetSystemClockSource(XMC_SCU_CLOCK_SYSCLKSRC_PLL); + } + SystemCoreClockUpdate(); +} + +/* API to enable a trap source */ +void XMC_SCU_TRAP_Enable(const uint32_t trap) +{ + SCU_TRAP->TRAPDIS &= (uint32_t)~trap; +} + +/* API to disable a trap source */ +void XMC_SCU_TRAP_Disable(const uint32_t trap) +{ + SCU_TRAP->TRAPDIS |= (uint32_t)trap; +} + +/* API to determine if a trap source has generated event */ +uint32_t XMC_SCU_TRAP_GetStatus(void) +{ + return (SCU_TRAP->TRAPRAW); +} + +/* API to manually trigger a trap event */ +void XMC_SCU_TRAP_Trigger(const uint32_t trap) +{ + SCU_TRAP->TRAPSET = (uint32_t)trap; +} + +/* API to clear a trap event */ +void XMC_SCU_TRAP_ClearStatus(const uint32_t trap) +{ + SCU_TRAP->TRAPCLR = (uint32_t)trap; +} + +/* API to clear parity error event */ +void XMC_SCU_PARITY_ClearStatus(const uint32_t memory) +{ + SCU_PARITY->PEFLAG |= (uint32_t)memory; +} + +/* API to determine if the specified parity error has occured or not */ +uint32_t XMC_SCU_PARITY_GetStatus(void) +{ + return (SCU_PARITY->PEFLAG); +} + +/* API to enable parity error checking for the selected on-chip RAM type */ +void XMC_SCU_PARITY_Enable(const uint32_t memory) +{ + SCU_PARITY->PEEN |= (uint32_t)memory; +} + +/* API to disable parity error checking for the selected on-chip RAM type */ +void XMC_SCU_PARITY_Disable(const uint32_t memory) +{ + SCU_PARITY->PEEN &= (uint32_t)~memory; +} + +/* API to enable trap assertion for the parity error source */ +void XMC_SCU_PARITY_EnableTrapGeneration(const uint32_t memory) +{ + SCU_PARITY->PETE |= (uint32_t)memory; +} + +/* API to disable the assertion of trap for the parity error source */ +void XMC_SCU_PARITY_DisableTrapGeneration(const uint32_t memory) +{ + SCU_PARITY->PETE &= (uint32_t)~memory; +} + +/* Enables a NMI source */ +void XMC_SCU_INTERRUPT_EnableNmiRequest(const uint32_t request) +{ + SCU_INTERRUPT->NMIREQEN |= (uint32_t)request; +} + +/* Disables a NMI source */ +void XMC_SCU_INTERRUPT_DisableNmiRequest(const uint32_t request) +{ + SCU_INTERRUPT->NMIREQEN &= (uint32_t)~request; +} + +/* API to manually assert a reset request */ +void XMC_SCU_RESET_AssertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peripheral) +{ + uint32_t index = (uint32_t)((((uint32_t)peripheral) & 0xf0000000UL) >> 28UL); + uint32_t mask = (((uint32_t)peripheral) & ((uint32_t)~0xf0000000UL)); + + *(uint32_t *)(&(SCU_RESET->PRSET0) + (index * 3U)) = (uint32_t)mask; +} + +/* API to manually de-assert a reset request */ +void XMC_SCU_RESET_DeassertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peripheral) +{ + uint32_t index = (uint32_t)((((uint32_t)peripheral) & 0xf0000000UL) >> 28UL); + uint32_t mask = (((uint32_t)peripheral) & ((uint32_t)~0xf0000000UL)); + + *(uint32_t *)(&(SCU_RESET->PRCLR0) + (index * 3U)) = (uint32_t)mask; +} + +/* Find out if the peripheral reset is asserted */ +bool XMC_SCU_RESET_IsPeripheralResetAsserted(const XMC_SCU_PERIPHERAL_RESET_t peripheral) +{ + uint32_t index = (uint32_t)((((uint32_t)peripheral) & 0xf0000000UL) >> 28UL); + uint32_t mask = (((uint32_t)peripheral) & ((uint32_t)~0xf0000000UL)); + + return ((*(uint32_t *)(&(SCU_RESET->PRSTAT0) + (index * 3U)) & mask) != 0U); +} + +/* + * API to retrieve frequency of System PLL output clock + */ +uint32_t XMC_SCU_CLOCK_GetSystemPllClockFrequency(void) +{ + uint32_t clock_frequency; + uint32_t p_div; + uint32_t n_div; + uint32_t k2_div; + + clock_frequency = XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency(); + if(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) + { + /* Prescalar mode - fOSC is the parent*/ + clock_frequency = (uint32_t)(clock_frequency / + ((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1UL)); + } + else + { + p_div = (uint32_t)((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1UL); + n_div = (uint32_t)((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1UL); + k2_div = (uint32_t)((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1UL); + + clock_frequency = (clock_frequency * n_div) / (p_div * k2_div); + } + + return (clock_frequency); +} + +/** + * API to retrieve frequency of System PLL VCO input clock + */ +uint32_t XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency(void) +{ + uint32_t clock_frequency; + + /* Prescalar mode - fOSC is the parent*/ + if((SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk) == (uint32_t)XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP) + { + clock_frequency = OSCHP_GetFrequency(); + } + else + { + clock_frequency = OFI_FREQUENCY; + } + + return (clock_frequency); +} + +/* + * API to retrieve frequency of USB PLL output clock + */ +uint32_t XMC_SCU_CLOCK_GetUsbPllClockFrequency(void) +{ + uint32_t clock_frequency; + uint32_t n_div; + uint32_t p_div; + + clock_frequency = OSCHP_GetFrequency(); + if((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOBYST_Msk) == 0U) + { + /* Normal mode - fVCO is the parent*/ + n_div = (uint32_t)((((SCU_PLL->USBPLLCON) & SCU_PLL_USBPLLCON_NDIV_Msk) >> SCU_PLL_USBPLLCON_NDIV_Pos) + 1UL); + p_div = (uint32_t)((((SCU_PLL->USBPLLCON) & SCU_PLL_USBPLLCON_PDIV_Msk) >> SCU_PLL_USBPLLCON_PDIV_Pos) + 1UL); + clock_frequency = (uint32_t)((clock_frequency * n_div)/ (uint32_t)(p_div * 2UL)); + } + return (clock_frequency); +} + +/* + * API to retrieve frequency of CCU clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetCcuClockFrequency(void) +{ + uint32_t frequency = 0UL; + frequency = XMC_SCU_CLOCK_GetSystemClockFrequency(); + + return (uint32_t)(frequency >> ((uint32_t)((SCU_CLK->CCUCLKCR & SCU_CLK_CCUCLKCR_CCUDIV_Msk) >> + SCU_CLK_CCUCLKCR_CCUDIV_Pos))); +} + +/* + * API to retrieve USB and SDMMC clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetUsbClockFrequency(void) +{ + uint32_t frequency = 0UL; + XMC_SCU_CLOCK_USBCLKSRC_t clksrc; + + clksrc = XMC_SCU_CLOCK_GetUsbClockSource(); + + if (clksrc == XMC_SCU_CLOCK_USBCLKSRC_SYSPLL) + { + frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); + } + else if (clksrc == XMC_SCU_CLOCK_USBCLKSRC_USBPLL) + { + frequency = XMC_SCU_CLOCK_GetUsbPllClockFrequency(); + } + else + { + } + + return (uint32_t)(frequency / (((SCU_CLK->USBCLKCR & SCU_CLK_USBCLKCR_USBDIV_Msk) >> + SCU_CLK_USBCLKCR_USBDIV_Pos) + 1UL)); +} + +#if defined(EBU) +/* + * API to retrieve EBU clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetEbuClockFrequency(void) +{ + uint32_t frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); + + return (uint32_t)((frequency /(((SCU_CLK->EBUCLKCR & SCU_CLK_EBUCLKCR_EBUDIV_Msk) >> + SCU_CLK_EBUCLKCR_EBUDIV_Pos) + 1UL))); +} +#endif + +#if defined(ECAT0) +/* + * API to retrieve ECAT clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetECATClockFrequency(void) +{ + uint32_t frequency; + + if ((SCU_CLK->ECATCLKCR & SCU_CLK_ECATCLKCR_ECATSEL_Msk) != 0U) + { + frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); + } + else + { + frequency = XMC_SCU_CLOCK_GetUsbPllClockFrequency(); + } + + return (uint32_t)((frequency / (XMC_SCU_CLOCK_GetECATClockDivider() + 1UL))); +} +#endif + +/* + * API to retrieve WDT clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetWdtClockFrequency(void) +{ + uint32_t frequency = 0UL; + XMC_SCU_CLOCK_WDTCLKSRC_t clksrc; + + clksrc = XMC_SCU_CLOCK_GetWdtClockSource(); + + if (clksrc == XMC_SCU_CLOCK_WDTCLKSRC_PLL) + { + frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); + } + else if (clksrc == XMC_SCU_CLOCK_WDTCLKSRC_OFI) + { + frequency = OFI_FREQUENCY; + } + else if (clksrc == XMC_SCU_CLOCK_WDTCLKSRC_STDBY) + { + frequency = OSI_FREQUENCY; + } + else + { + + } + + return (uint32_t)((frequency / (((SCU_CLK->WDTCLKCR & SCU_CLK_WDTCLKCR_WDTDIV_Msk) >> + SCU_CLK_WDTCLKCR_WDTDIV_Pos) + 1UL))); +} + +/** + * @brief API to retrieve EXTERNAL-OUT clock frequency + * @retval Clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetExternalOutputClockFrequency(void) +{ + uint32_t frequency = 0UL; + XMC_SCU_CLOCK_EXTOUTCLKSRC_t clksrc; + + clksrc = XMC_SCU_CLOCK_GetExternalOutputClockSource(); + + if (clksrc == XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL) + { + frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); + + frequency = (uint32_t)((frequency / ((((SCU_CLK->EXTCLKCR) & SCU_CLK_EXTCLKCR_ECKDIV_Msk) >> + SCU_CLK_EXTCLKCR_ECKDIV_Pos)+ 1UL))); + } + else if (clksrc == XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS) + { + frequency = XMC_SCU_CLOCK_GetSystemClockFrequency(); + } + else if (clksrc == XMC_SCU_CLOCK_EXTOUTCLKSRC_USB) + { + frequency = XMC_SCU_CLOCK_GetUsbPllClockFrequency(); + + frequency = (uint32_t)((frequency / ((((SCU_CLK->EXTCLKCR) & SCU_CLK_EXTCLKCR_ECKDIV_Msk) >> + SCU_CLK_EXTCLKCR_ECKDIV_Pos)+ 1UL))); + } + else + { + + } + + return (frequency); +} + +/* + * API to retrieve clock frequency of peripherals on the peripheral bus using a shared functional clock + */ +uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void) +{ + return (uint32_t)(XMC_SCU_CLOCK_GetCpuClockFrequency() >> + ((SCU_CLK->PBCLKCR & SCU_CLK_PBCLKCR_PBDIV_Msk) >> SCU_CLK_PBCLKCR_PBDIV_Pos)); +} + +/* API to select fSYS */ +void XMC_SCU_CLOCK_SetSystemClockSource(const XMC_SCU_CLOCK_SYSCLKSRC_t source) +{ + SCU_CLK->SYSCLKCR = (SCU_CLK->SYSCLKCR & ((uint32_t)~SCU_CLK_SYSCLKCR_SYSSEL_Msk)) | + ((uint32_t)source); +} + +/* API to select fUSB */ +void XMC_SCU_CLOCK_SetUsbClockSource(const XMC_SCU_CLOCK_USBCLKSRC_t source) +{ + SCU_CLK->USBCLKCR = (SCU_CLK->USBCLKCR & ((uint32_t)~SCU_CLK_USBCLKCR_USBSEL_Msk)) | + ((uint32_t)source); +} + +/* API to select fWDT */ +void XMC_SCU_CLOCK_SetWdtClockSource(const XMC_SCU_CLOCK_WDTCLKSRC_t source) +{ + SCU_CLK->WDTCLKCR = (SCU_CLK->WDTCLKCR & ((uint32_t)~SCU_CLK_WDTCLKCR_WDTSEL_Msk)) | + ((uint32_t)source); +} + +/* API to select fEXT */ +void XMC_SCU_CLOCK_SetExternalOutputClockSource(const XMC_SCU_CLOCK_EXTOUTCLKSRC_t source) +{ + SCU_CLK->EXTCLKCR = (SCU_CLK->EXTCLKCR & ((uint32_t)~SCU_CLK_EXTCLKCR_ECKSEL_Msk)) | + ((uint32_t)source); +} + +/* API to select fPLL */ +void XMC_SCU_CLOCK_SetSystemPllClockSource(const XMC_SCU_CLOCK_SYSPLLCLKSRC_t source) +{ + /* Check input clock */ + if (source == XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP) /* Select PLLClockSource */ + { + SCU_PLL->PLLCON2 &= (uint32_t)~(SCU_PLL_PLLCON2_PINSEL_Msk | SCU_PLL_PLLCON2_K1INSEL_Msk); + } + else + { + SCU_PLL->PLLCON2 |= (uint32_t)(SCU_PLL_PLLCON2_PINSEL_Msk | SCU_PLL_PLLCON2_K1INSEL_Msk); + } +} + +/* API to select fRTC */ +void XMC_SCU_HIB_SetRtcClockSource(const XMC_SCU_HIB_RTCCLKSRC_t source) +{ + /* Wait until the update of HDCR register in hibernate domain is completed */ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + } + + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ((uint32_t)~SCU_HIBERNATE_HDCR_RCS_Msk)) | + ((uint32_t)source); +} + +/* API to select fSTDBY */ +void XMC_SCU_HIB_SetStandbyClockSource(const XMC_SCU_HIB_STDBYCLKSRC_t source) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ((uint32_t)~SCU_HIBERNATE_HDCR_STDBYSEL_Msk)) | + ((uint32_t)source); +} + +/* API to program the divider placed between fsys and its parent */ +void XMC_SCU_CLOCK_SetSystemClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetSystemClockDivider:Wrong clock divider value", + (divider <= (SCU_CLK_SYSCLKCR_SYSDIV_Msk + 1UL)) ); + + SCU_CLK->SYSCLKCR = (SCU_CLK->SYSCLKCR & ((uint32_t)~SCU_CLK_SYSCLKCR_SYSDIV_Msk)) | + ((uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_SYSCLKCR_SYSDIV_Pos)); +} + +/* API to program the divider placed between fccu and its parent */ +void XMC_SCU_CLOCK_SetCcuClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetCapcomClockDivider:Wrong clock divider value", (divider <= 2UL) ); + + SCU_CLK->CCUCLKCR = (SCU_CLK->CCUCLKCR & ((uint32_t)~SCU_CLK_CCUCLKCR_CCUDIV_Msk)) | + (uint32_t)((uint32_t)(divider - 1UL) << SCU_CLK_CCUCLKCR_CCUDIV_Pos); +} + +/* API to program the divider placed between fcpu and its parent */ +void XMC_SCU_CLOCK_SetCpuClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetCpuClockDivider:Wrong clock divider value", (divider <= 2UL) ); + + SCU_CLK->CPUCLKCR = (SCU_CLK->CPUCLKCR & ((uint32_t)~SCU_CLK_CPUCLKCR_CPUDIV_Msk)) | + (uint32_t)((uint32_t)(divider - 1UL) << SCU_CLK_CPUCLKCR_CPUDIV_Pos); +} + +/* API to program the divider placed between fperiph and its parent */ +void XMC_SCU_CLOCK_SetPeripheralClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetPeripheralClockDivider:Wrong clock divider value", (divider <= 2UL) ); + + SCU_CLK->PBCLKCR = (SCU_CLK->PBCLKCR & ((uint32_t)~SCU_CLK_PBCLKCR_PBDIV_Msk)) | + ((uint32_t)((uint32_t)(divider - 1UL) << SCU_CLK_PBCLKCR_PBDIV_Pos)); +} + +/* API to program the divider placed between fsdmmc and its parent */ +void XMC_SCU_CLOCK_SetUsbClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetSdmmcClockDivider:Wrong clock divider value", + (divider <= (SCU_CLK_USBCLKCR_USBDIV_Msk + 1UL)) ); + + SCU_CLK->USBCLKCR = (SCU_CLK->USBCLKCR & ((uint32_t)~SCU_CLK_USBCLKCR_USBDIV_Msk)) | + (uint32_t)((uint32_t)(divider - 1UL) << SCU_CLK_USBCLKCR_USBDIV_Pos); +} + +#if defined(EBU) +/* API to program the divider placed between febu and its parent */ +void XMC_SCU_CLOCK_SetEbuClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetEbuClockDivider:Wrong clock divider value", + (divider <= (SCU_CLK_EBUCLKCR_EBUDIV_Msk + 1UL) ) ); + + SCU_CLK->EBUCLKCR = (SCU_CLK->EBUCLKCR & ((uint32_t)~SCU_CLK_EBUCLKCR_EBUDIV_Msk)) | + (uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_EBUCLKCR_EBUDIV_Pos); +} +#endif + +/* API to program the divider placed between fwdt and its parent */ +void XMC_SCU_CLOCK_SetWdtClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetWdtClockDivider:Wrong clock divider value", + (divider <= (SCU_CLK_WDTCLKCR_WDTDIV_Msk + 1UL) ) ); + + SCU_CLK->WDTCLKCR = (SCU_CLK->WDTCLKCR & ((uint32_t)~SCU_CLK_WDTCLKCR_WDTDIV_Msk)) | + (uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_WDTCLKCR_WDTDIV_Pos); +} + +/* API to program the divider placed between fext and its parent */ +void XMC_SCU_CLOCK_SetExternalOutputClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetExternalOutputClockDivider:Wrong clock divider value", + (divider <= (SCU_CLK_EXTCLKCR_ECKDIV_Msk + 1UL) ) ); + + SCU_CLK->EXTCLKCR = (SCU_CLK->EXTCLKCR & ((uint32_t)~SCU_CLK_EXTCLKCR_ECKDIV_Msk)) | + (uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_EXTCLKCR_ECKDIV_Pos); +} + +#if defined(ECAT0) +/* API to configure the ECAT clock by setting the clock divider for the ECAT clock source */ +void XMC_SCU_CLOCK_SetECATClockDivider(const uint32_t divider) +{ + SCU_CLK->ECATCLKCR = (SCU_CLK->ECATCLKCR & ~SCU_CLK_ECATCLKCR_ECADIV_Msk) | + (uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_ECATCLKCR_ECADIV_Pos); +} +#endif + +/* API to enable a given module clock */ +void XMC_SCU_CLOCK_EnableClock(const XMC_SCU_CLOCK_t clock) +{ + SCU_CLK->CLKSET = ((uint32_t)clock); +} + +/* API to disable a given module clock */ +void XMC_SCU_CLOCK_DisableClock(const XMC_SCU_CLOCK_t clock) +{ + SCU_CLK->CLKCLR = ((uint32_t)clock); +} + +/* API to determine if module clock of the given peripheral is enabled */ +bool XMC_SCU_CLOCK_IsClockEnabled(const XMC_SCU_CLOCK_t clock) +{ + return (bool)(SCU_CLK->CLKSTAT & ((uint32_t)clock)); +} + +#if defined(CLOCK_GATING_SUPPORTED) +/* API to gate a given module clock */ +void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral) +{ + uint32_t index = (peripheral & 0xf0000000UL) >> 28UL; + uint32_t mask = (peripheral & (uint32_t)~0xf0000000UL); + + *(uint32_t *)((&(SCU_CLK->CGATSET0)) + (index * 3U)) = (uint32_t)mask; +} + +/* API to ungate a given module clock */ +void XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral) +{ + uint32_t index = (uint32_t)((peripheral & 0xf0000000UL) >> 28UL); + uint32_t mask = (peripheral & (uint32_t)~0xf0000000UL); + + *(uint32_t *)(&(SCU_CLK->CGATCLR0) + (index * 3U)) = (uint32_t)mask; +} + +/* API to ungate a given module clock */ +bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral) +{ + uint32_t index = ((peripheral & 0xf0000000UL) >> 28UL); + uint32_t mask = (peripheral & (uint32_t)~0xf0000000UL); + + return ((*(uint32_t *)(&(SCU_CLK->CGATSTAT0) + (index * 3U)) & mask) != 0U); +} +#endif + +float XMC_SCU_POWER_GetEVR13Voltage(void) +{ + return (SCU_POWER->EVRVADCSTAT & SCU_POWER_EVRVADCSTAT_VADC13V_Msk) * XMC_SCU_POWER_LSB13V; +} + +float XMC_SCU_POWER_GetEVR33Voltage(void) +{ + return ((SCU_POWER->EVRVADCSTAT & SCU_POWER_EVRVADCSTAT_VADC33V_Msk) >> SCU_POWER_EVRVADCSTAT_VADC33V_Pos) * XMC_SCU_POWER_LSB33V; +} + +/* API to enable USB PLL for USB clock */ +void XMC_SCU_CLOCK_EnableUsbPll(void) +{ + SCU_PLL->USBPLLCON &= (uint32_t)~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* API to disable USB PLL for USB clock */ +void XMC_SCU_CLOCK_DisableUsbPll(void) +{ + SCU_PLL->USBPLLCON |= (uint32_t)(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* API to configure USB PLL */ +void XMC_SCU_CLOCK_StartUsbPll(uint32_t pdiv, uint32_t ndiv) +{ + /* Go to bypass the USB PLL */ + SCU_PLL->USBPLLCON |= (uint32_t)SCU_PLL_USBPLLCON_VCOBYP_Msk; + + /* disconnect Oscillator from USB PLL */ + SCU_PLL->USBPLLCON |= (uint32_t)SCU_PLL_USBPLLCON_FINDIS_Msk; + + /* Setup Divider settings for USB PLL */ + SCU_PLL->USBPLLCON = (uint32_t)((uint32_t)((ndiv -1U) << SCU_PLL_USBPLLCON_NDIV_Pos) | + (uint32_t)((pdiv - 1U) << SCU_PLL_USBPLLCON_PDIV_Pos)); + + /* Set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= (uint32_t)SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + + /* connect Oscillator to USB PLL */ + SCU_PLL->USBPLLCON &= (uint32_t)~SCU_PLL_USBPLLCON_FINDIS_Msk; + + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= (uint32_t)SCU_PLL_USBPLLCON_RESLD_Msk; + + while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U) + { + /* wait for PLL Lock */ + } + +} + +/* API to disable USB PLL operation */ +void XMC_SCU_CLOCK_StopUsbPll(void) +{ + SCU_PLL->USBPLLCON = (uint32_t)(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk | + SCU_PLL_USBPLLCON_VCOBYP_Msk); +} + +/* API to onfigure the calibration mode for internal oscillator */ +void XMC_SCU_CLOCK_SetBackupClockCalibrationMode(XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t mode) +{ + /* Enable factory calibration based trimming */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_FOTR_Msk; + + if (mode == XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC) + { + /* Disable factory calibration based trimming */ + SCU_PLL->PLLCON0 &= (uint32_t)~SCU_PLL_PLLCON0_FOTR_Msk; + XMC_SCU_lDelay(100UL); + + /* Enable automatic calibration */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_AOTREN_Msk; + } + + XMC_SCU_lDelay(100UL); +} + + + +/* API to enable USB Phy and comparator */ +void XMC_SCU_POWER_EnableUsb(void) +{ +#if defined(USB_OTG_SUPPORTED) + SCU_POWER->PWRSET = (uint32_t)(SCU_POWER_PWRSET_USBOTGEN_Msk | SCU_POWER_PWRSET_USBPHYPDQ_Msk); +#else + SCU_POWER->PWRSET = (uint32_t)SCU_POWER_PWRSET_USBPHYPDQ_Msk; +#endif +} + +/* API to power down USB Phy and comparator */ +void XMC_SCU_POWER_DisableUsb(void) +{ +#if defined(USB_OTG_SUPPORTED) + SCU_POWER->PWRCLR = (uint32_t)(SCU_POWER_PWRCLR_USBOTGEN_Msk | SCU_POWER_PWRSET_USBPHYPDQ_Msk); +#else + SCU_POWER->PWRCLR = (uint32_t)SCU_POWER_PWRCLR_USBPHYPDQ_Msk; +#endif +} + +/* API to check USB PLL is locked or not */ +bool XMC_SCU_CLOCK_IsUsbPllLocked(void) +{ + return (bool)((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) != 0UL); +} + +/* API to power up the hibernation domain */ +void XMC_SCU_HIB_EnableHibernateDomain(void) +{ + /* Power up HIB domain if and only if it is currently powered down */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0UL) + { + SCU_POWER->PWRSET = (uint32_t)SCU_POWER_PWRSET_HIB_Msk; + + while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0UL) + { + /* wait until HIB domain is enabled */ + } + } + + /* Remove the reset only if HIB domain were in a state of reset */ + if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) + { + SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_HIBRS_Msk; + while((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk) != 0UL) + { + /* wait until HIB domain is enabled */ + } + } +} + +/* API to power down the hibernation domain */ +void XMC_SCU_HIB_DisableHibernateDomain(void) +{ + /* Disable hibernate domain */ + SCU_POWER->PWRCLR = (uint32_t)SCU_POWER_PWRCLR_HIB_Msk; + /* Reset of hibernate domain reset */ + SCU_RESET->RSTSET = (uint32_t)SCU_RESET_RSTSET_HIBRS_Msk; +} + +/* API to check the hibernation domain is enabled or not */ +bool XMC_SCU_HIB_IsHibernateDomainEnabled(void) +{ + return ((bool)(SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) && + !(bool)(SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)); +} + +/* API to enable internal slow clock - fOSI (32.768kHz) in hibernate domain */ +void XMC_SCU_HIB_EnableInternalSlowClock(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk) + { + /* Wait until OSCSICTRL register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->OSCSICTRL &= (uint32_t)~(SCU_HIBERNATE_OSCSICTRL_PWD_Msk); +} + +/* API to disable internal slow clock - fOSI (32.768kHz) in hibernate domain */ +void XMC_SCU_HIB_DisableInternalSlowClock(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk) + { + /* Wait until OSCSICTRL register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->OSCSICTRL |= (uint32_t)SCU_HIBERNATE_OSCSICTRL_PWD_Msk; +} + +void XMC_SCU_HIB_ClearEventStatus(int32_t event) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCLR_Msk) + { + /* Wait until HDCLR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCLR = event; +} + +void XMC_SCU_HIB_TriggerEvent(int32_t event) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDSET_Msk) + { + /* Wait until HDSET register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDSET = event; +} + +void XMC_SCU_HIB_EnableEvent(int32_t event) +{ +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + event = ((event & XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE) << (SCU_HIBERNATE_HDCR_VBATHI_Pos - SCU_HIBERNATE_HDSTAT_VBATPEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE) << (SCU_HIBERNATE_HDCR_VBATLO_Pos - SCU_HIBERNATE_HDSTAT_VBATNEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE); +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO1HI_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO1LO_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE); +#endif +#endif + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR |= event; +} + +void XMC_SCU_HIB_DisableEvent(int32_t event) +{ +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + event = ((event & XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE) << (SCU_HIBERNATE_HDCR_VBATHI_Pos - SCU_HIBERNATE_HDSTAT_VBATPEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE) << (SCU_HIBERNATE_HDCR_VBATLO_Pos - SCU_HIBERNATE_HDSTAT_VBATNEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE); +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO1HI_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO1LO_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE); +#endif +#endif + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR &= ~event; +} + +void XMC_SCU_HIB_EnterHibernateState(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_HIB_Msk; +} + +void XMC_SCU_HIB_EnterHibernateStateEx(XMC_SCU_HIB_HIBERNATE_MODE_t mode) +{ + if (mode == XMC_SCU_HIB_HIBERNATE_MODE_EXTERNAL) + { + XMC_SCU_HIB_EnterHibernateState(); + } +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + if (mode == XMC_SCU_HIB_HIBERNATE_MODE_INTERNAL) + { + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HINTSET_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HINTSET = SCU_HIBERNATE_HINTSET_HIBNINT_Msk; + } +#endif +} + +void XMC_SCU_HIB_SetWakeupTriggerInput(XMC_SCU_HIB_IO_t pin) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + if (pin == XMC_SCU_HIB_IO_0) + { + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_WKUPSEL_Msk; + } + else + { + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_WKUPSEL_Msk; + } +} + +void XMC_SCU_HIB_SetPinMode(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_PIN_MODE_t mode) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ~(SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk << (SCU_HIBERNATE_HDCR_HIBIOSEL_Size * pin))) | + (mode << (SCU_HIBERNATE_HDCR_HIBIOSEL_Size * pin)); +} + +void XMC_SCU_HIB_SetPinOutputLevel(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_IO_OUTPUT_LEVEL_t level) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ~(SCU_HIBERNATE_HDCR_HIBIO0POL_Msk << pin)) | + (level << pin); +} + +void XMC_SCU_HIB_SetInput0(XMC_SCU_HIB_IO_t pin) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + if (pin == XMC_SCU_HIB_IO_0) + { + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_GPI0SEL_Msk; + } + else + { + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_GPI0SEL_Msk; + } +} + +void XMC_SCU_HIB_SetSR0Input(XMC_SCU_HIB_SR0_INPUT_t input) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI0SEL_Msk | SCU_HIBERNATE_HDCR_ADIG0SEL_Msk)) | +#else + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI0SEL_Msk)) | +#endif + input; +} + +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + +#if ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)) +void XMC_SCU_HIB_SetSR1Input(XMC_SCU_HIB_SR1_INPUT_t input) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI0SEL_Msk | SCU_HIBERNATE_HDCR_ADIG0SEL_Msk | SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk)) | + input; +} +#endif + +void XMC_SCU_HIB_LPAC_SetInput(XMC_SCU_HIB_LPAC_INPUT_t input) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->LPACCONF = (SCU_HIBERNATE->LPACCONF & (uint32_t)~SCU_HIBERNATE_LPACCONF_CMPEN_Msk) | + input; +} + +void XMC_SCU_HIB_LPAC_SetTrigger(XMC_SCU_HIB_LPAC_TRIGGER_t trigger) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->LPACCONF = (SCU_HIBERNATE->LPACCONF & (uint32_t)~SCU_HIBERNATE_LPACCONF_TRIGSEL_Msk) | + trigger; +} + +void XMC_SCU_HIB_LPAC_SetTiming(bool enable_delay, uint16_t interval_count, uint8_t settle_count) +{ + uint32_t config = 0; + + if (enable_delay) + { + config = SCU_HIBERNATE_LPACCONF_CONVDEL_Msk; + } + + config |= interval_count << SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos; + config |= settle_count << SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos; + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + SCU_HIBERNATE->LPACCONF = (SCU_HIBERNATE->LPACCONF & (uint32_t)~(SCU_HIBERNATE_LPACCONF_CONVDEL_Msk | + SCU_HIBERNATE_LPACCONF_INTERVCNT_Msk | + SCU_HIBERNATE_LPACCONF_SETTLECNT_Msk)) | + config; + +} + +void XMC_SCU_HIB_LPAC_SetVBATThresholds(uint8_t lower, uint8_t upper) +{ + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH0_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + SCU_HIBERNATE->LPACTH0 = (lower << SCU_HIBERNATE_LPACTH0_VBATLO_Pos) | (upper << SCU_HIBERNATE_LPACTH0_VBATHI_Pos); + + + +} + +void XMC_SCU_HIB_LPAC_SetHIBIO0Thresholds(uint8_t lower, uint8_t upper) +{ + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH1_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + SCU_HIBERNATE->LPACTH1 = (SCU_HIBERNATE->LPACTH1 & (uint32_t)~(SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Msk | SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Msk)) | + (lower << SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Pos) | + (upper << SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Pos); + +} +#if ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)) +void XMC_SCU_HIB_LPAC_SetHIBIO1Thresholds(uint8_t lower, uint8_t upper) +{ + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH1_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + SCU_HIBERNATE->LPACTH1 = (SCU_HIBERNATE->LPACTH1 & (uint32_t)~(SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Msk | SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Msk)) | + (lower << SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Pos) | + (upper << SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Pos); + +} +#endif +int32_t XMC_SCU_HIB_LPAC_GetStatus(void) +{ + return SCU_HIBERNATE->LPACST; +} + +void XMC_SCU_HIB_LPAC_ClearStatus(int32_t status) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCLR_Msk) + { + /* Wait until LPACCLR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->LPACCLR = status;; +} + +void XMC_SCU_HIB_LPAC_TriggerCompare(XMC_SCU_HIB_LPAC_INPUT_t input) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACSET_Msk) + { + /* Wait until LPACSET register in hibernate domain is ready to accept a write */ + } + + SCU_HIBERNATE->LPACSET = input; +} + +#endif + +bool XMC_SCU_CLOCK_IsLowPowerOscillatorStable(void) +{ + return ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) == 0UL); +} + +/* API to configure the 32khz Ultra Low Power oscillator */ +void XMC_SCU_CLOCK_EnableLowPowerOscillator(void) +{ + /* Enable OSC_ULP */ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + { + /* Wait until the update of OSCULCTRL register in hibernate domain is completed */ + } + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; + + /* Enable OSC_ULP Oscillator Watchdog*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCR |= (uint32_t)SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + + /* Enable OSC_ULP Oscillator Watchdog*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDSET_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDSET = (uint32_t)SCU_HIBERNATE_HDSET_ULPWDG_Msk; +} + +/* API to configure the 32khz Ultra Low Power oscillator */ +void XMC_SCU_CLOCK_DisableLowPowerOscillator(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + { + /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->OSCULCTRL |= (uint32_t)SCU_HIBERNATE_OSCULCTRL_MODE_Msk; +} + +void XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + { + /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->OSCULCTRL |= SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk | SCU_HIBERNATE_OSCULCTRL_MODE_Msk; +} + +void XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + { + /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->OSCULCTRL = (SCU_HIBERNATE->OSCULCTRL & ~(uint32_t)(SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk | SCU_HIBERNATE_OSCULCTRL_MODE_Msk)) | + (SCU_HIBERNATE_OSCULCTRL_MODE_OSC_POWER_DOWN << SCU_HIBERNATE_OSCULCTRL_MODE_Pos); +} + +uint32_t XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus(void) +{ + return (SCU_HIBERNATE->OSCULSTAT & SCU_HIBERNATE_OSCULSTAT_X1D_Msk); +} + +/* API to enable High Precision High Speed oscillator */ +void XMC_SCU_CLOCK_EnableHighPerformanceOscillator(void) +{ + SCU_PLL->PLLCON0 &= (uint32_t)~SCU_PLL_PLLCON0_PLLPWD_Msk; + + SCU_OSC->OSCHPCTRL = (uint32_t)((SCU_OSC->OSCHPCTRL & ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk)) | + (((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos)); + + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= (uint32_t)~SCU_PLL_PLLCON0_OSCRES_Msk; +} + +bool XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable(void) +{ + return ((SCU_PLL->PLLSTAT & XMC_SCU_PLL_PLLSTAT_OSC_USABLE) == XMC_SCU_PLL_PLLSTAT_OSC_USABLE); +} + +/* API to disable High Precision High Speed oscillator */ +void XMC_SCU_CLOCK_DisableHighPerformanceOscillator(void) +{ + SCU_OSC->OSCHPCTRL |= (uint32_t)SCU_OSC_OSCHPCTRL_MODE_Msk; +} + +void XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(void) +{ + SCU_OSC->OSCHPCTRL |= SCU_OSC_OSCHPCTRL_X1DEN_Msk; +} + +void XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(void) +{ + SCU_OSC->OSCHPCTRL &= ~SCU_OSC_OSCHPCTRL_X1DEN_Msk; +} + +uint32_t XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus(void) +{ + return (SCU_OSC->OSCHPSTAT & SCU_OSC_OSCHPSTAT_X1D_Msk); +} + +/* API to enable main PLL */ +void XMC_SCU_CLOCK_EnableSystemPll(void) +{ + SCU_PLL->PLLCON0 &= (uint32_t)~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); +} + +/* API to disable main PLL */ +void XMC_SCU_CLOCK_DisableSystemPll(void) +{ + SCU_PLL->PLLCON0 |= (uint32_t)(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); +} + +/* API to configure main PLL */ +void XMC_SCU_CLOCK_StartSystemPll(XMC_SCU_CLOCK_SYSPLLCLKSRC_t source, + XMC_SCU_CLOCK_SYSPLL_MODE_t mode, + uint32_t pdiv, + uint32_t ndiv, + uint32_t kdiv) +{ + + uint32_t vco_frequency; /* Q10.22, max VCO frequency = 520MHz */ + uint32_t kdiv_temp; + + XMC_SCU_CLOCK_SetSystemPllClockSource(source); + + if (mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL) + { + /* Calculate initial step to be close to fOFI */ + if (source == XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP) + { + vco_frequency = (OSCHP_GetFrequency() / 1000000U) << 22; + } + else + { + vco_frequency = (OFI_FREQUENCY / 1000000U) << 22; + } + vco_frequency = ((vco_frequency * ndiv) / pdiv); + kdiv_temp = (vco_frequency / (OFI_FREQUENCY / 1000000U)) >> 22; + + /* Switch to prescaler mode */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_VCOBYP_Msk; + + /* disconnect Oscillator from PLL */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_FINDIS_Msk; + + /* Setup divider settings for main PLL */ + SCU_PLL->PLLCON1 = (uint32_t)((SCU_PLL->PLLCON1 & ~(SCU_PLL_PLLCON1_NDIV_Msk | SCU_PLL_PLLCON1_K2DIV_Msk | + SCU_PLL_PLLCON1_PDIV_Msk)) | ((ndiv - 1UL) << SCU_PLL_PLLCON1_NDIV_Pos) | + ((kdiv_temp - 1UL) << SCU_PLL_PLLCON1_K2DIV_Pos) | + ((pdiv - 1UL)<< SCU_PLL_PLLCON1_PDIV_Pos)); + + /* Set OSCDISCDIS, OSC clock remains connected to the VCO in case of loss of lock */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + /* connect Oscillator to PLL */ + SCU_PLL->PLLCON0 &= (uint32_t)~SCU_PLL_PLLCON0_FINDIS_Msk; + + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_RESLD_Msk; + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U) + { + /* wait for PLL Lock */ + } + + /* Switch to normal mode */ + SCU_PLL->PLLCON0 &= (uint32_t)~SCU_PLL_PLLCON0_VCOBYP_Msk; + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U) + { + /* wait for normal mode */ + } + + /* Ramp up PLL frequency in steps */ + kdiv_temp = (vco_frequency / 60UL) >> 22; + if (kdiv < kdiv_temp) + { + XMC_SCU_CLOCK_StepSystemPllFrequency(kdiv_temp); + } + + kdiv_temp = (vco_frequency / 90UL) >> 22; + if (kdiv < kdiv_temp) + { + XMC_SCU_CLOCK_StepSystemPllFrequency(kdiv_temp); + } + + XMC_SCU_CLOCK_StepSystemPllFrequency(kdiv); + } + else + { + SCU_PLL->PLLCON1 = (uint32_t)((SCU_PLL->PLLCON1 & ~SCU_PLL_PLLCON1_K1DIV_Msk) | + ((kdiv -1UL) << SCU_PLL_PLLCON1_K1DIV_Pos)); + + /* Switch to prescaler mode */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_VCOBYP_Msk; + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) == 0U) + { + /* wait for prescaler mode */ + } + } +} + +/* API to stop main PLL operation */ +void XMC_SCU_CLOCK_StopSystemPll(void) +{ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_PLLPWD_Msk; +} + +/* API to step up/down the main PLL frequency */ +void XMC_SCU_CLOCK_StepSystemPllFrequency(uint32_t kdiv) +{ + SCU_PLL->PLLCON1 = (uint32_t)((SCU_PLL->PLLCON1 & ~SCU_PLL_PLLCON1_K2DIV_Msk) | + ((kdiv - 1UL) << SCU_PLL_PLLCON1_K2DIV_Pos)); + + XMC_SCU_lDelay(50U); +} + +/* API to check main PLL is locked or not */ +bool XMC_SCU_CLOCK_IsSystemPllLocked(void) +{ + return (bool)((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) != 0UL); +} + +/* + * API to assign the event handler function to be executed on occurrence of the selected event. + */ +XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t event, + const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler) +{ + uint32_t index; + XMC_SCU_STATUS_t status; + + index = 0U; + while (((event & ((XMC_SCU_INTERRUPT_EVENT_t)1 << index)) == 0U) && (index < XMC_SCU_INTERRUPT_EVENT_MAX)) + { + index++; + } + + if (index == XMC_SCU_INTERRUPT_EVENT_MAX) + { + status = XMC_SCU_STATUS_ERROR; + } + else + { + event_handler_list[index] = handler; + status = XMC_SCU_STATUS_OK; + } + + return (status); +} + +/* + * API to execute callback functions for multiple events. + */ +void XMC_SCU_IRQHandler(uint32_t sr_num) +{ + uint32_t index; + XMC_SCU_INTERRUPT_EVENT_t event; + XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler; + + XMC_UNUSED_ARG(sr_num); + + index = 0U; + event = XMC_SCU_INTERUPT_GetEventStatus(); + while (index < XMC_SCU_INTERRUPT_EVENT_MAX) + { + if ((event & ((XMC_SCU_INTERRUPT_EVENT_t)1 << index)) != 0U) + { + event_handler = event_handler_list[index]; + if (event_handler != NULL) + { + (event_handler)(); + } + + XMC_SCU_INTERRUPT_ClearEventStatus((uint32_t)(1UL << index)); + + break; + } + index++; + } +} + +#endif /* UC_FAMILY == XMC4 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_can.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_can.c new file mode 100644 index 00000000..547ebc39 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_can.c @@ -0,0 +1,744 @@ +/** + * @file xmc_can.c + * @date 2016-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * + * 2015-05-20: + * - New API added: XMC_CAN_MO_ReceiveData()
+ * - XMC_CAN_MO_Config() signature has changed
+ * - Minor fix in XMC_CAN_TXFIFO_ConfigMOSlaveObject().
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-09-01: + * - Removed fCANB clock support
+ * + * 2015-09-08: + * - Fixed bug in XMC_CAN_Init()
+ * + * 2016-06-07: + * - Changed XMC_CAN_AllocateMOtoNodeList to wait for ready status of list controller + * + * 2015-06-20: + * - Fixed bug in XMC_CAN_MO_Config()
+ * @endcond + * + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#include "xmc_can.h" + +#if defined(CAN) +#include "xmc_scu.h" + +__STATIC_INLINE uint32_t max(uint32_t a, uint32_t b) +{ + return (a > b) ? a : b; +} + +__STATIC_INLINE uint32_t min(uint32_t a, uint32_t b) +{ + return (a < b) ? a : b; +} + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +/* Baudrate Configuration */ +void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const can_bit_time) +{ + uint32_t temp_brp = 12U ; + uint32_t temp_tseg1 = 12U; + uint32_t best_brp = 0U; + uint32_t best_tseg1 = 1U; + uint32_t best_tseg2 = 0U; + uint32_t best_tbaud = 0U; + uint32_t best_error = 10000U; + + XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: rate not supported", (can_bit_time->baudrate < 1000000U) || + (can_bit_time->baudrate >= 100000U)); + XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: fCAN not supported", + can_bit_time->can_frequency <= 120000000U); + XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: fCAN not supported", + can_bit_time->can_frequency > 5000000U); + XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: sample point not supported", + (can_bit_time->sample_point < 10000U) && ((can_bit_time->sample_point > 0U))); + + /* + * Bit timing & sampling + * Tq = (BRP+1)/Fcan if DIV8 = 0 + * Tq = 8*(BRP+1)/Fcan if DIV8 = 1 + * TSync = 1.Tq + * TSeg1 = (TSEG1+1)*Tq >= 3Tq + * TSeg2 = (TSEG2+1)*Tq >= 2Tq + * Bit Time = TSync + TSeg1 + TSeg2 >= 8Tq + * + * Resynchronization: + * + * Tsjw = (SJW + 1)*Tq + * TSeg1 >= Tsjw + Tprop + * TSeg2 >= Tsjw + */ + /* search for best baudrate */ + for (temp_brp = 1U; temp_brp <= 64U; temp_brp++) + { + + uint32_t f_quanta = (uint32_t)((can_bit_time->can_frequency * 10U) / temp_brp); + uint32_t temp_tbaud = (uint32_t)(f_quanta / (can_bit_time->baudrate)); + uint32_t temp_baudrate; + uint32_t error; + + if((temp_tbaud % 10U) > 5U) + { + temp_tbaud = (uint32_t)(temp_tbaud / 10U); + temp_tbaud++; + } + else + { + temp_tbaud = (uint32_t)(temp_tbaud / 10U); + } + + if(temp_tbaud > 0U) + { + temp_baudrate = (uint32_t) (f_quanta / (temp_tbaud * 10U)); + } + else + { + temp_baudrate = f_quanta / 10U; + temp_tbaud = 1; + } + + if(temp_baudrate >= can_bit_time->baudrate) + { + error = temp_baudrate - can_bit_time->baudrate; + } + else + { + error = can_bit_time->baudrate - temp_baudrate; + } + + if ((temp_tbaud <= 20U) && (best_error > error)) + { + best_brp = temp_brp; + best_tbaud = temp_tbaud; + best_error = (error); + + if (error < 1000U) + { + break; + } + } + } + /* search for best sample point */ + best_error = 10000U; + + for (temp_tseg1 = 64U; temp_tseg1 >= 3U; temp_tseg1--) + { + uint32_t tempSamplePoint = ((temp_tseg1 + 1U) * 10000U) / best_tbaud; + uint32_t error; + if (tempSamplePoint >= can_bit_time->sample_point) + { + error = tempSamplePoint - can_bit_time->sample_point; + } + else + { + error = can_bit_time->sample_point - tempSamplePoint; + } + if (best_error > error) + { + best_tseg1 = temp_tseg1; + best_error = error; + } + if (tempSamplePoint < (can_bit_time->sample_point)) + { + break; + } + } + + best_tseg2 = best_tbaud - best_tseg1 - 1U; + + XMC_CAN_NODE_EnableConfigurationChange(can_node); + /* Configure bit timing register */ + can_node->NBTR = (((uint32_t)(best_tseg2 - 1u) << CAN_NODE_NBTR_TSEG2_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG2_Msk) | + ((((uint32_t)((uint32_t)(can_bit_time->sjw)-1U) << CAN_NODE_NBTR_SJW_Pos)) & (uint32_t)CAN_NODE_NBTR_SJW_Msk)| + (((uint32_t)(best_tseg1-1U) << CAN_NODE_NBTR_TSEG1_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG1_Msk)| + (((uint32_t)(best_brp - 1U) << CAN_NODE_NBTR_BRP_Pos) & (uint32_t)CAN_NODE_NBTR_BRP_Msk)| + (((uint32_t)0U << CAN_NODE_NBTR_DIV8_Pos) & (uint32_t)CAN_NODE_NBTR_DIV8_Msk); + XMC_CAN_NODE_DisableConfigurationChange(can_node); +} +/* Function to allocate message object from free list to node list */ +void XMC_CAN_AllocateMOtoNodeList(XMC_CAN_t *const obj, const uint8_t node_num, const uint8_t mo_num) +{ + /* wait while panel operation is in progress. */ + while (XMC_CAN_IsPanelControlReady(obj) == false) + { + /*Do nothing*/ + }; + + /* Panel Command for allocation of MO to node list */ + XMC_CAN_PanelControl(obj, XMC_CAN_PANCMD_STATIC_ALLOCATE,mo_num,(node_num + 1U)); +} + +/* Disable XMC_CAN Peripheral */ +void XMC_CAN_Disable(XMC_CAN_t *const obj) +{ + /* Disable CAN Module */ + obj->CLC = CAN_CLC_DISR_Msk; +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_MCAN); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_MCAN); +#endif +} + +/* Enable XMC_CAN Peripheral */ +void XMC_CAN_Enable(XMC_CAN_t *const obj) +{ +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_MCAN); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_MCAN); +#endif + /* Enable CAN Module */ + obj->CLC &= ~(uint32_t)CAN_CLC_DISR_Msk; + while (obj->CLC & CAN_CLC_DISS_Msk) + { + /*Do nothing*/ + }; +} +#if defined(MULTICAN_PLUS) +uint32_t XMC_CAN_GetBaudrateClockFrequency(XMC_CAN_t *const obj) +{ + uint32_t frequency; + + switch(XMC_CAN_GetBaudrateClockSource(obj)) + { +#if UC_FAMILY == XMC4 + case XMC_CAN_CANCLKSRC_FPERI: + frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + break; +#else + case XMC_CAN_CANCLKSRC_MCLK: + frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + break; +#endif + case XMC_CAN_CANCLKSRC_FOHP: + frequency = OSCHP_GetFrequency(); + break; + + default: + frequency = 0; + break; + } + + return frequency; +} + +void XMC_CAN_Init(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can_frequency) +{ + uint32_t step_n, step_f; + bool normal_divider; + uint32_t freq_n, freq_f; + uint32_t step; + uint32_t can_frequency_khz; + uint32_t peripheral_frequency_khz; + XMC_CAN_DM_t can_divider_mode; + + uint32_t peripheral_frequency; + /*Enabling the module*/ + XMC_CAN_Enable(obj); + + XMC_CAN_SetBaudrateClockSource(obj, clksrc); + + peripheral_frequency = XMC_CAN_GetBaudrateClockFrequency(obj); + + XMC_ASSERT("XMC_CAN_Init: frequency not supported", can_frequency <= peripheral_frequency); + + /* Normal divider mode */ + step_n = (uint32_t)min(max(0U, (1024U - (peripheral_frequency / can_frequency))), 1023U); + freq_n = (uint32_t) (peripheral_frequency / (1024U - step_n)); + + /* Fractional divider mode */ + can_frequency_khz = (uint32_t) (can_frequency >> 6); + peripheral_frequency_khz = (uint32_t)(peripheral_frequency >> 6); + + step_f = (uint32_t)(min( (((1024U * can_frequency_khz) / peripheral_frequency_khz) ), 1023U )); + freq_f = (uint32_t)((peripheral_frequency_khz * step_f) / 1024U); + freq_f = freq_f << 6; + + normal_divider = (uint32_t)(can_frequency - freq_n) <= (can_frequency - freq_f); + + step = (normal_divider != 0U) ? step_n : step_f; + can_divider_mode = (normal_divider != 0U) ? XMC_CAN_DM_NORMAL : XMC_CAN_DM_FRACTIONAL; + + obj->FDR &= (uint32_t) ~(CAN_FDR_DM_Msk | CAN_FDR_STEP_Msk); + obj->FDR |= ((uint32_t)can_divider_mode << CAN_FDR_DM_Pos) | ((uint32_t)step << CAN_FDR_STEP_Pos); + +} + +void XMC_CAN_SetBaudrateClockSource(XMC_CAN_t *const obj,const XMC_CAN_CANCLKSRC_t source) +{ + obj->MCR = (obj->MCR & ~CAN_MCR_CLKSEL_Msk) | source ; +} + +XMC_CAN_CANCLKSRC_t XMC_CAN_GetBaudrateClockSource(XMC_CAN_t *const obj) +{ + return ((XMC_CAN_CANCLKSRC_t)((obj->MCR & CAN_MCR_CLKSEL_Msk) >> CAN_MCR_CLKSEL_Pos)); +} + +#else +/* Initialization of XMC_CAN GLOBAL Object */ +void XMC_CAN_Init(XMC_CAN_t *const obj, uint32_t can_frequency) +{ + uint32_t step_n, step_f; + bool normal_divider; + uint32_t freq_n, freq_f; + uint32_t step; + uint32_t can_frequency_khz; + uint32_t peripheral_frequency_khz; + XMC_CAN_DM_t can_divider_mode; + + uint32_t peripheral_frequency = (XMC_SCU_CLOCK_GetPeripheralClockFrequency()); + + XMC_ASSERT("XMC_CAN_Init: frequency not supported", can_frequency <= peripheral_frequency); + + /*Enabling the module*/ + XMC_CAN_Enable(obj); + + /* Normal divider mode */ + step_n = (uint32_t)min(max(0U, (1024U - (peripheral_frequency / can_frequency))), 1023U); + freq_n = (uint32_t) (peripheral_frequency / (1024U - step_n)); + + /* Fractional divider mode */ + can_frequency_khz = (uint32_t) (can_frequency >> 6); + peripheral_frequency_khz = (uint32_t)(peripheral_frequency >> 6); + + step_f = (uint32_t)(min( (((1024U * can_frequency_khz) / peripheral_frequency_khz) ), 1023U )); + freq_f = (uint32_t)((peripheral_frequency_khz * step_f) / 1024U); + freq_f = freq_f << 6; + + normal_divider = (uint32_t)(can_frequency - freq_n) <= (can_frequency - freq_f); + + step = (normal_divider != 0U) ? step_n : step_f; + can_divider_mode = (normal_divider != 0U) ? XMC_CAN_DM_NORMAL : XMC_CAN_DM_FRACTIONAL; + + obj->FDR &= (uint32_t) ~(CAN_FDR_DM_Msk | CAN_FDR_STEP_Msk); + obj->FDR |= ((uint32_t)can_divider_mode << CAN_FDR_DM_Pos) | ((uint32_t)step << CAN_FDR_STEP_Pos); +} +#endif + +/* Sets the Identifier of the MO */ +void XMC_CAN_MO_SetIdentifier(XMC_CAN_MO_t *const can_mo, const uint32_t can_identifier) +{ + if ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk) + { + can_mo->can_mo_ptr->MOAR = ((can_mo->can_mo_ptr->MOAR) & ~(uint32_t)(CAN_MO_MOAR_ID_Msk)) | + ((can_identifier << XMC_CAN_MO_MOAR_STDID_Pos) & (uint32_t)CAN_MO_MOAR_ID_Msk); + } + else + { + can_mo->can_mo_ptr->MOAR = ((can_mo->can_mo_ptr->MOAR) & ~(uint32_t)(CAN_MO_MOAR_ID_Msk)) | + (can_identifier & (uint32_t)CAN_MO_MOAR_ID_Msk); + } + can_mo->can_identifier = can_identifier; +} + + +/* Gets the Identifier of the MO */ +uint32_t XMC_CAN_MO_GetIdentifier(const XMC_CAN_MO_t *const can_mo) +{ + uint32_t identifier; + if ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk) + { + identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk)) >> XMC_CAN_MO_MOAR_STDID_Pos; + } + else + { + identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk)); + } + return identifier; +} + +/* Gets the acceptance mask for the CAN MO. */ +uint32_t XMC_CAN_MO_GetAcceptanceMask(const XMC_CAN_MO_t *const can_mo) +{ + uint32_t identifier_mask; + if (((can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) != (uint32_t)CAN_MO_MOAMR_MIDE_Msk) + && ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk)) + { + identifier_mask = ((can_mo->can_mo_ptr->MOAMR) & (uint32_t)(CAN_MO_MOAMR_AM_Msk)) >> XMC_CAN_MO_MOAR_STDID_Pos; + } + else + { + identifier_mask = ((can_mo->can_mo_ptr->MOAMR) & (uint32_t)(CAN_MO_MOAMR_AM_Msk)); + } + return identifier_mask; +} + +/* Gets the acceptance mask of the MO */ +void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo,const uint32_t can_id_mask) +{ + if (((can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) != (uint32_t)CAN_MO_MOAMR_MIDE_Msk) + && ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk)) + { + can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) | + (can_id_mask << XMC_CAN_MO_MOAR_STDID_Pos); + } + else + { + can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) | + (can_id_mask & (uint32_t)CAN_MO_MOAMR_AM_Msk); + } + can_mo->can_id_mask = can_id_mask; +} + +/* Initialization of XMC_CAN MO Object */ +void XMC_CAN_MO_Config(const XMC_CAN_MO_t *const can_mo) +{ + uint32_t reg; + + /* Configure MPN */ + uint32_t num = ((uint32_t)(can_mo->can_mo_ptr) - CAN_BASE - 0x1000U)/0x0020U; + uint32_t set = (((uint32_t)(num/32) << (CAN_MO_MOIPR_MPN_Pos + 5U)) | ((uint32_t)(num%32) << CAN_MO_MOIPR_MPN_Pos)); + can_mo->can_mo_ptr->MOIPR &= ~(CAN_MO_MOIPR_MPN_Msk); + can_mo->can_mo_ptr->MOIPR |= set; + + if (((can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_STANDARD_11BITS) && + (can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_EXTENDED_29BITS)) || + ((can_mo->can_mo_type != XMC_CAN_MO_TYPE_RECMSGOBJ) && + (can_mo->can_mo_type != XMC_CAN_MO_TYPE_TRANSMSGOBJ))) + { + ; /*Do nothing*/ + } + else + { + + /* Disable Message object */ + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESMSGVAL_Msk; + if (can_mo->can_id_mode == (uint32_t)XMC_CAN_FRAME_TYPE_STANDARD_11BITS) + { + reg = can_mo->mo_ar; + reg &= (uint32_t) ~(CAN_MO_MOAR_ID_Msk); + reg |= (can_mo->can_identifier << XMC_CAN_MO_MOAR_STDID_Pos); + can_mo->can_mo_ptr->MOAR = reg; + + reg = can_mo->mo_amr; + reg &= (uint32_t) ~(CAN_MO_MOAMR_AM_Msk); + reg |= (can_mo->can_id_mask << XMC_CAN_MO_MOAR_STDID_Pos); + can_mo->can_mo_ptr->MOAMR = reg; + } + else + { + can_mo->can_mo_ptr->MOAR = can_mo->mo_ar; + can_mo->can_mo_ptr->MOAMR = can_mo->mo_amr; + } + /* Check whether message object is transmit message object */ + if (can_mo->can_mo_type == XMC_CAN_MO_TYPE_TRANSMSGOBJ) + { + /* Set MO as Transmit message object */ + XMC_CAN_MO_UpdateData(can_mo); + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_SETDIR_Msk; + } + else + { + /* Set MO as Receive message object and set RXEN bit */ + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESDIR_Msk; + } + + /* Reset RTSEL and Set MSGVAL ,TXEN0 and TXEN1 bits */ + can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk | CAN_MO_MOCTR_SETMSGVAL_Msk | + CAN_MO_MOCTR_SETRXEN_Msk | CAN_MO_MOCTR_RESRTSEL_Msk); + } +} + +/* Update of XMC_CAN Object */ +XMC_CAN_STATUS_t XMC_CAN_MO_UpdateData(const XMC_CAN_MO_t *const can_mo) +{ + XMC_CAN_STATUS_t error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE; + /* Check whether message object is transmit message object */ + if (can_mo->can_mo_type == XMC_CAN_MO_TYPE_TRANSMSGOBJ) + { + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESMSGVAL_Msk; + /* Configure data length */ + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR) & ~(uint32_t)(CAN_MO_MOFCR_DLC_Msk)) | + (((uint32_t) can_mo->can_data_length << CAN_MO_MOFCR_DLC_Pos) & (uint32_t)CAN_MO_MOFCR_DLC_Msk); + /* Configure Data registers*/ + can_mo->can_mo_ptr->MODATAL = can_mo->can_data[0]; + can_mo->can_mo_ptr->MODATAH = can_mo->can_data[1]; + /* Reset RTSEL and Set MSGVAL ,TXEN0 and TXEN1 bits */ + can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETNEWDAT_Msk| CAN_MO_MOCTR_SETMSGVAL_Msk |CAN_MO_MOCTR_RESRTSEL_Msk); + error = XMC_CAN_STATUS_SUCCESS; + } + else + { + error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE; + } + return error; +} + +/* This function is will put a transmit request to transmit message object */ +XMC_CAN_STATUS_t XMC_CAN_MO_Transmit(const XMC_CAN_MO_t *const can_mo) +{ + XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR; + uint32_t mo_type = (uint32_t)(((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_MSGVAL_Msk) >> CAN_MO_MOSTAT_MSGVAL_Pos); + uint32_t mo_transmission_ongoing = (uint32_t) ((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_TXRQ_Msk) >> CAN_MO_MOSTAT_TXRQ_Pos; + /* check if message is disabled */ + if (mo_type == 0U) + { + error = XMC_CAN_STATUS_MO_DISABLED; + } + /* check if transmission is ongoing on message object */ + else if (mo_transmission_ongoing == 1U) + { + error = XMC_CAN_STATUS_BUSY; + } + else + { + /* set TXRQ bit */ + can_mo->can_mo_ptr-> MOCTR = CAN_MO_MOCTR_SETTXRQ_Msk | CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk; + error = XMC_CAN_STATUS_SUCCESS; + } + return error; +} + +/* This function is will read the message object data bytes */ +XMC_CAN_STATUS_t XMC_CAN_MO_ReceiveData (XMC_CAN_MO_t *can_mo) +{ + XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR; + uint8_t rx_pnd = 0U; + uint8_t new_data = 0U; + uint32_t mo_type = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_DIR_Msk) >> CAN_MO_MOSTAT_DIR_Pos; + uint32_t mo_recepcion_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos; + /* check if message object is a receive message object */ + if (mo_type != (uint32_t)XMC_CAN_MO_TYPE_RECMSGOBJ) + { + error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE; + } + /* check if reception is ongoing on message object */ + else if (mo_recepcion_ongoing == 1U) + { + error = XMC_CAN_STATUS_BUSY; + } + else + { + /* read message parameters */ + do + { + can_mo->can_data[0] = can_mo->can_mo_ptr->MODATAL; + can_mo->can_data[1] = can_mo->can_mo_ptr->MODATAH; + + rx_pnd = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos); + new_data = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_NEWDAT_Msk) >> CAN_MO_MOSTAT_NEWDAT_Pos); + } while ((rx_pnd != 0U) && (new_data != 0U)); + + error = XMC_CAN_STATUS_SUCCESS; + } + return error; +} + + +/* This function is will read the message object data bytes */ +XMC_CAN_STATUS_t XMC_CAN_MO_Receive (XMC_CAN_MO_t *can_mo) +{ + XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR; + uint8_t rx_pnd = 0U; + uint8_t new_data = 0U; + uint32_t mo_type = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_DIR_Msk) >> CAN_MO_MOSTAT_DIR_Pos; + uint32_t mo_recepcion_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos; + /* check if message object is a receive message object */ + if (mo_type != (uint32_t)XMC_CAN_MO_TYPE_RECMSGOBJ) + { + error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE; + } + /* check if reception is ongoing on message object */ + else if (mo_recepcion_ongoing == 1U) + { + error = XMC_CAN_STATUS_BUSY; + } + else + { + /* read message parameters */ + do + { + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESNEWDAT_Msk; + if ((((can_mo->can_mo_ptr->MOAR) & CAN_MO_MOAR_IDE_Msk) >> CAN_MO_MOAR_IDE_Pos) == 0U) + { + can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_STANDARD_11BITS; + can_mo->can_identifier = (can_mo->can_mo_ptr->MOAR & XMC_CAN_MO_MOAR_STDID_Msk) >> XMC_CAN_MO_MOAR_STDID_Pos; + can_mo->can_ide_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) >> CAN_MO_MOAMR_MIDE_Pos; + if(can_mo->can_ide_mask == 1U) + { + can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & XMC_CAN_MO_MOAR_STDID_Msk) >> XMC_CAN_MO_MOAR_STDID_Pos; + } + else + { + can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_AM_Msk); + } + } + else + { + can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_EXTENDED_29BITS; + can_mo->can_identifier = (can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_ID_Msk); + can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_AM_Msk); + can_mo->can_ide_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) >> CAN_MO_MOAMR_MIDE_Pos; + } + can_mo->can_data_length = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOFCR) & CAN_MO_MOFCR_DLC_Msk) >> CAN_MO_MOFCR_DLC_Pos); + + can_mo->can_data[0] = can_mo->can_mo_ptr->MODATAL; + can_mo->can_data[1] = can_mo->can_mo_ptr->MODATAH; + + rx_pnd = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos); + new_data = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_NEWDAT_Msk) >> CAN_MO_MOSTAT_NEWDAT_Pos); + } while ((rx_pnd != 0U) && (new_data != 0U)); + + can_mo->can_mo_type = XMC_CAN_MO_TYPE_RECMSGOBJ; + error = XMC_CAN_STATUS_SUCCESS; + } + return error; +} + +/* Function to enable node event */ +void XMC_CAN_NODE_EnableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event) +{ + if(event != XMC_CAN_NODE_EVENT_CFCIE) + { + can_node->NCR |= (uint32_t)event; + } + else + { + can_node->NFCR |= (uint32_t)event; + } +} + +/* Function to disable node event */ +void XMC_CAN_NODE_DisableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event) +{ + if(event != XMC_CAN_NODE_EVENT_CFCIE) + { + can_node->NCR &= ~(uint32_t)event; + } + else + { + can_node->NFCR &= ~(uint32_t)event; + } +} +/* Function to transmit MO from the FIFO */ +XMC_CAN_STATUS_t XMC_CAN_TXFIFO_Transmit(const XMC_CAN_MO_t *const can_mo) +{ + XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR; + uint32_t mo_type = ((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_MSGVAL_Msk) >> CAN_MO_MOSTAT_MSGVAL_Pos); + uint32_t mo_transmission_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_TXRQ_Msk) >> CAN_MO_MOSTAT_TXRQ_Pos; + uint32_t mo_cur = (uint32_t)(can_mo->can_mo_ptr-> MOFGPR & CAN_MO_MOFGPR_CUR_Msk) >> CAN_MO_MOFGPR_CUR_Pos; + CAN_MO_TypeDef* mo = (CAN_MO_TypeDef *)(CAN_BASE + 0x1000UL + (mo_cur * 0x0020UL)); + /* check if message is disabled */ + if (mo_type == 0U) + { + error = XMC_CAN_STATUS_MO_DISABLED; + } + /* check if transmission is ongoing on message object */ + else if (mo_transmission_ongoing == 1U) + { + error = XMC_CAN_STATUS_BUSY; + } + else + { + mo->MOCTR = CAN_MO_MOCTR_SETTXRQ_Msk | CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk; + error = XMC_CAN_STATUS_SUCCESS; + } + return error; +} + +/* Function to initialize the transmit FIFO MO base object */ +void XMC_CAN_TXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo) +{ + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) | + (((uint32_t)0x2U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk); + can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_BOT_Msk | + CAN_MO_MOFGPR_TOP_Msk | + CAN_MO_MOFGPR_CUR_Msk)) | + (((uint32_t)can_fifo.fifo_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) | + (((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t) CAN_MO_MOFGPR_CUR_Msk) | + (((uint32_t)can_fifo.fifo_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t) CAN_MO_MOFGPR_TOP_Msk); +} +/* Function to Initialize the receive FIFO MO base object */ +void XMC_CAN_RXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo) +{ + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) | + (((uint32_t)0x1U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk); + can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~( uint32_t)(CAN_MO_MOFGPR_BOT_Msk | + CAN_MO_MOFGPR_TOP_Msk | + CAN_MO_MOFGPR_CUR_Msk)) | + (((uint32_t)can_fifo.fifo_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) | + (((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk) | + (((uint32_t)can_fifo.fifo_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t)CAN_MO_MOFGPR_TOP_Msk); +} + +/* Function to Initialize the FIFO MO slave object */ +void XMC_CAN_TXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo) +{ + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) | + (((uint32_t)0x3U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk); + can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_CUR_Msk)) | + (((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk); + + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_SETTXEN0_Msk| + CAN_MO_MOCTR_RESTXEN1_Msk; +} + +/* Function to Initialize the Gateway Source Object */ +void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_GATEWAY_CONFIG_t can_gateway) +{ + can_mo->can_mo_ptr->MOFCR = (((uint32_t)0x4U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk) | + ((((uint32_t)can_gateway.gateway_data_frame_send) << CAN_MO_MOFCR_GDFS_Pos) & (uint32_t)CAN_MO_MOFCR_GDFS_Msk) | + ((((uint32_t)can_gateway.gateway_data_length_code_copy) << CAN_MO_MOFCR_DLCC_Pos) & (uint32_t)CAN_MO_MOFCR_DLCC_Msk) | + ((((uint32_t)can_gateway.gateway_identifier_copy) << CAN_MO_MOFCR_IDC_Pos) & (uint32_t)CAN_MO_MOFCR_IDC_Msk) | + ((((uint32_t)can_gateway.gateway_data_copy) << CAN_MO_MOFCR_DATC_Pos) & (uint32_t)CAN_MO_MOFCR_DATC_Msk) ; + can_mo->can_mo_ptr->MOFGPR = (uint32_t)((((uint32_t)can_gateway.gateway_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) | + (((uint32_t)can_gateway.gateway_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk) | + (((uint32_t)can_gateway.gateway_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t)CAN_MO_MOFGPR_TOP_Msk)); +} + +#endif /* XMC_CAN_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ccu4.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ccu4.c new file mode 100644 index 00000000..c0f3868c --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ccu4.c @@ -0,0 +1,1136 @@ +/** + * @file xmc_ccu4.c + * @date 2017-02-25 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API
+ * + * 2015-07-01: + * - In XMC_CCU4_SLICE_StartConfig(), Options in XMC_ASSERT check for start mode is corrected.
+ * + * 2015-07-24: + * - XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
+ * + * 2015-08-17: + * - Start of prescaler XMC_CCU4_StartPrescaler() is invoked in XMC_CCU4_Init() API.
+ * - Bug fix XMC_CCU4_SLICE_ConfigureEvent() during the level setting for XMC14 devices.
+ * - XMC_CCU4_EnableShadowTransfer() definition is removed, since the API is made as inline.
+ * + * 2015-10-07: + * - XMC_CCU4_SLICE_GetEvent() is made as inline. + * - DOC updates for the newly added APIs. + * + * 2017-02-25: + * - XMC_CCU4_lAssertReset(), XMC_CCU4_lDeassertReset(), XMC_CCU4_lGateClock() and XMC_CCU4_lUngateClock() fix compilation warnings. + * + * @endcond + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_ccu4.h" + +#if defined(CCU40) +#include "xmc_scu.h" +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_CCU4_NUM_SLICES_PER_MODULE (4U) +#define XMC_CCU4_SLICE_DITHER_PERIOD_MASK (1U) +#define XMC_CCU4_SLICE_DITHER_DUTYCYCLE_MASK (2U) +#define XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK (3U) +#define XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK (1U) +#define XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK (3U) +#if defined(CCU4V3) /* Defined for XMC1400 devices only */ +#define XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK CCU4_CC4_INS1_EV0IS_Msk +#else +#define XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK CCU4_CC4_INS_EV0IS_Msk +#endif +#define XMC_CCU4_GIDLC_CLOCK_MASK (15U) +#define XMC_CCU4_GCSS_SLICE0_MASK (1U) +#define XMC_CCU4_GCSS_SLICE1_MASK (16U) +#define XMC_CCU4_GCSS_SLICE2_MASK (256U) +#define XMC_CCU4_GCSS_SLICE3_MASK (4096U) + +/** Macro to check if the clock selected enum passed is valid */ +#define XMC_CCU4_SLICE_CHECK_CLOCK(clock) \ + ((clock == XMC_CCU4_CLOCK_SCU) || \ + (clock == XMC_CCU4_CLOCK_EXTERNAL_A) || \ + (clock == XMC_CCU4_CLOCK_EXTERNAL_B) || \ + (clock == XMC_CCU4_CLOCK_EXTERNAL_C)) + +/** Macro used to check if the event ID is valid*/ +#define XMC_CCU4_SLICE_CHECK_EVENT_ID(event_id) \ + ((event_id == XMC_CCU4_SLICE_EVENT_NONE)|| \ + (event_id == XMC_CCU4_SLICE_EVENT_0) || \ + (event_id == XMC_CCU4_SLICE_EVENT_1) || \ + (event_id == XMC_CCU4_SLICE_EVENT_2)) + +/** Macro used to check if the edge sensitivity is valid*/ +#define XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(edge) \ + ((edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE) || \ + (edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE) || \ + (edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE)|| \ + (edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE)) + +/** Macro used to check if the filter clock cycles are valid */ +#define XMC_CCU4_SLICE_CHECK_EVENT_FILTER(cycles) \ + ((cycles == XMC_CCU4_SLICE_EVENT_FILTER_DISABLED) || \ + (cycles == XMC_CCU4_SLICE_EVENT_FILTER_3_CYCLES) || \ + (cycles == XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES) || \ + (cycles == XMC_CCU4_SLICE_EVENT_FILTER_7_CYCLES)) + +/** Macro used to check if the Multi-channel input related action is valid*/ +#define XMC_CCU4_SLICE_CHECK_MCS_ACTION(mcs_action) \ + ((mcs_action == XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR) || \ + (mcs_action == XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP) || \ + (mcs_action == XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT)) + +/** Macro used to check if the SR line is valid*/ +#define XMC_CCU4_SLICE_CHECK_SR_ID(id) \ + ((id == XMC_CCU4_SLICE_SR_ID_0) || \ + (id == XMC_CCU4_SLICE_SR_ID_1) || \ + (id == XMC_CCU4_SLICE_SR_ID_2) || \ + (id == XMC_CCU4_SLICE_SR_ID_3)) + +/** Macro to check if the end mode enum passed is valid */ +#define XMC_CCU4_CHECK_END_MODE(end_mode) \ + ((end_mode == XMC_CCU4_SLICE_END_MODE_TIMER_STOP) || \ + (end_mode == XMC_CCU4_SLICE_END_MODE_TIMER_CLEAR) || \ + (end_mode == XMC_CCU4_SLICE_END_MODE_TIMER_STOP_CLEAR)) + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ +#if defined(PERIPHERAL_RESET_SUPPORTED) +__STATIC_INLINE void XMC_CCU4_lAssertReset(const XMC_CCU4_MODULE_t *const module) +{ + if (module == CCU40) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU40); + } +#if defined(CCU41) + else if (module == CCU41) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU41); + } +#endif +#if defined(CCU42) + else if (module == CCU42) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU42); + } +#endif +#if defined(CCU43) + else if (module == CCU43) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU43); + } +#endif + else + { + XMC_ASSERT("XMC_CCU4_lAssertReset:Invalid Module Pointer", 0); + } +} + +__STATIC_INLINE void XMC_CCU4_lDeassertReset(const XMC_CCU4_MODULE_t *const module) +{ + if (module == CCU40) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU40); + } +#if defined(CCU41) + else if (module == CCU41) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU41); + } +#endif +#if defined(CCU42) + else if (module == CCU42) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU42); + } +#endif +#if defined(CCU43) + else if (module == CCU43) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU43); + } +#endif + else + { + XMC_ASSERT("XMC_CCU4_lDeassertReset:Invalid Module Pointer", 0); + } +} +#endif + +#if defined(CLOCK_GATING_SUPPORTED) +__STATIC_INLINE void XMC_CCU4_lGateClock(const XMC_CCU4_MODULE_t *const module) +{ + + if (module == CCU40) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU40); + } +#if defined(CCU41) + else if (module == CCU41) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU41); + } +#endif +#if defined(CCU42) + else if (module == CCU42) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU42); + } +#endif +#if defined(CCU43) + else if (module == CCU43) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU43); + } +#endif + else + { + XMC_ASSERT("XMC_CCU4_lGateClock:Invalid Module Pointer", 0); + } +} + +__STATIC_INLINE void XMC_CCU4_lUngateClock(const XMC_CCU4_MODULE_t *const module) +{ + if (module == CCU40) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU40); + } +#if defined(CCU41) + else if (module == CCU41) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU41); + } +#endif +#if defined(CCU42) + else if (module == CCU42) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU42); + } +#endif +#if defined(CCU43) + else if (module == CCU43) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU43); + } +#endif + else + { + XMC_ASSERT("XMC_CCU4_lUngateClock:Invalid Module Pointer", 0); + } +} +#endif + +#if defined (XMC_ASSERT_ENABLE) +__STATIC_INLINE bool XMC_CCU4_SLICE_IsInputvalid(XMC_CCU4_SLICE_INPUT_t input) +{ +#if (UC_SERIES == XMC14) + return (input < 48U); +#else + return (input < 16U); +#endif +} +#endif +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +void XMC_CCU4_EnableModule(XMC_CCU4_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU4_EnableModule:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + +#if UC_FAMILY == XMC4 + /* Enable CCU4 module clock */ + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_CCU4_lUngateClock(module); +#endif + +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_CCU4_lDeassertReset(module); +#endif +} + +void XMC_CCU4_DisableModule(XMC_CCU4_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU4_DisableModule:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_CCU4_lAssertReset(module); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_CCU4_lGateClock(module); +#endif +} + +/* API to initialize CCU4 global resources */ +void XMC_CCU4_Init(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_SLICE_MCMS_ACTION_t mcs_action) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU4_Init:Invalid module pointer", XMC_CCU4_IsValidModule(module)); + XMC_ASSERT("XMC_CCU4_Init:Invalid mcs action", XMC_CCU4_SLICE_CHECK_MCS_ACTION(mcs_action)); + + /* Enable CCU4 module */ + XMC_CCU4_EnableModule(module); + /* Start the prescaler */ + XMC_CCU4_StartPrescaler(module); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t) CCU4_GCTRL_MSDE_Msk); + gctrl |= ((uint32_t) mcs_action) << CCU4_GCTRL_MSDE_Pos; + + module->GCTRL = gctrl; +} + +/* API to select CCU4 module clock */ +void XMC_CCU4_SetModuleClock(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_CLOCK_t clock) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU4_SetModuleClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + XMC_ASSERT("XMC_CCU4_SetModuleClock:Invalid Module Clock", XMC_CCU4_SLICE_CHECK_CLOCK(clock)); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t) CCU4_GCTRL_PCIS_Msk); + gctrl |= ((uint32_t) clock) << CCU4_GCTRL_PCIS_Pos; + + module->GCTRL = gctrl; +} + +/* API to configure the multichannel shadow transfer request via SW and via the CCU4x.MCSS input. */ +void XMC_CCU4_SetMultiChannelShadowTransferMode(XMC_CCU4_MODULE_t *const module, const uint32_t slice_mode_msk) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU4_SetMultiChannelShadowTransferMode:Invalid module Pointer", XMC_CCU4_IsValidModule(module)); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t)slice_mode_msk >> 16U); + gctrl |= ((uint32_t)slice_mode_msk & 0xFFFFU); + module->GCTRL = gctrl; +} + +/* API to configure CC4 Slice as Timer */ +void XMC_CCU4_SLICE_CompareInit(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_COMPARE_CONFIG_t *const compare_init) +{ + XMC_ASSERT("XMC_CCU4_SLICE_CompareInit:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_CompareInit:Compare Init Pointer is NULL", + (XMC_CCU4_SLICE_COMPARE_CONFIG_t *) NULL != compare_init); + + /* Program the timer mode */ + slice->TC = compare_init->tc; + /* Enable the timer concatenation */ + slice->CMC = ((uint32_t) compare_init->timer_concatenation << CCU4_CC4_CMC_TCE_Pos); + /* Program initial prescaler divider value */ + slice->PSC = (uint32_t) compare_init->prescaler_initval; + /* Program the dither compare value */ + slice->DITS = (uint32_t) compare_init->dither_limit; + /* Program timer output passive level */ + slice->PSL = (uint32_t) compare_init->passive_level; + /* Program floating prescaler compare value */ + slice->FPCS = (uint32_t) compare_init->float_limit; +} + +/* API to configure CC4 Slice for Capture */ +void XMC_CCU4_SLICE_CaptureInit(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAPTURE_CONFIG_t *const capture_init) +{ + XMC_ASSERT("XMC_CCU4_SLICE_CaptureInit:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_CaptureInit:Capture Init Pointer is NULL", + (XMC_CCU4_SLICE_CAPTURE_CONFIG_t *) NULL != capture_init); + + /* Program the capture mode */ + slice->TC = capture_init->tc; + /* Enable the timer concatenation */ + slice->CMC = ((uint32_t)capture_init->timer_concatenation << CCU4_CC4_CMC_TCE_Pos); + /* Program initial prescaler divider value */ + slice->PSC = (uint32_t) capture_init->prescaler_initval; + /* Program initial floating prescaler compare value */ + slice->FPCS = (uint32_t) capture_init->float_limit; +} + + +/* API to configure the Start trigger function of a slice */ +void XMC_CCU4_SLICE_StartConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_START_MODE_t start_mode) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU4_SLICE_StartConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_StartConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU4_SLICE_StartConfig:Invalid Start Mode", + ((start_mode == XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR) ||\ + (start_mode == XMC_CCU4_SLICE_START_MODE_TIMER_START))); + /* First, Bind the event with the stop function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_STRTS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_STRTS_Pos; + + slice->CMC = cmc; + + tc = slice->TC; + /* Next, Configure the start mode */ + if (start_mode == XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR) + { + tc |= (uint32_t)CCU4_CC4_TC_STRM_Msk; + } + else + { + tc &= ~((uint32_t)CCU4_CC4_TC_STRM_Msk); + } + + slice->TC = tc; +} + +/* API to configure the Stop trigger function of a slice */ +void XMC_CCU4_SLICE_StopConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_END_MODE_t end_mode) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU4_SLICE_StopConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_StopConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU4_SLICE_StopConfig:Invalid Start Mode", XMC_CCU4_CHECK_END_MODE(end_mode)); + + /* First, Bind the event with the stop function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_ENDS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_ENDS_Pos; + + slice->CMC = cmc; + + /* Next, Configure the stop mode */ + tc = slice->TC; + tc &= ~((uint32_t) CCU4_CC4_TC_ENDM_Msk); + tc |= ((uint32_t) end_mode) << CCU4_CC4_TC_ENDM_Pos; + + slice->TC = tc; +} + +/* API to configure the Load trigger function of a slice */ +void XMC_CCU4_SLICE_LoadConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_LoadConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_LoadConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the load function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_LDS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_LDS_Pos; + + slice->CMC = cmc; +} + +/* API to configure the slice modulation function */ +void XMC_CCU4_SLICE_ModulationConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_MODULATION_MODE_t mod_mode, + const bool synch_with_pwm) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU4_SLICE_ModulationConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_ModulationConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU4_SLICE_ModulationConfig:Invalid Modulation Mode", + ((mod_mode == XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT) ||\ + (mod_mode == XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_ST_OUT))); + + tc = slice->TC; + cmc = slice->CMC; + + /* First, Bind the event with the modulation function */ + cmc &= ~((uint32_t) CCU4_CC4_CMC_MOS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_MOS_Pos; + slice->CMC = cmc; + + /* Next, Modulation mode */ + if (mod_mode == XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT) + { + tc |= (uint32_t) CCU4_CC4_TC_EMT_Msk; + } + else + { + tc &= ~((uint32_t) CCU4_CC4_TC_EMT_Msk); + } + + /* Synchronization of modulation effect with PWM cycle */ + if (synch_with_pwm == (bool) true) + { + tc |= (uint32_t) CCU4_CC4_TC_EMS_Msk; + } + else + { + tc &= ~((uint32_t) CCU4_CC4_TC_EMS_Msk); + } + + slice->TC = tc; +} + +/* API to configure the slice count function */ +void XMC_CCU4_SLICE_CountConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_CountConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_CountConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the count function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_CNTS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_CNTS_Pos; + + slice->CMC = cmc; +} + +/* API to configure slice gate function */ +void XMC_CCU4_SLICE_GateConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_GateConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_GateConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the gate function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_GATES_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_GATES_Pos; + + slice->CMC = cmc; +} + +/* API to configure Capture-0 function */ +void XMC_CCU4_SLICE_Capture0Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_Capture0Config:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_Capture0Config:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the gate function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_CAP0S_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_CAP0S_Pos; + + slice->CMC = cmc; +} + +/* API to configure Capture-1 function */ +void XMC_CCU4_SLICE_Capture1Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_Capture1Config:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_Capture1Config:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the gate function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_CAP1S_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_CAP1S_Pos; + + slice->CMC = cmc; +} + +/* API to configure direction function */ +void XMC_CCU4_SLICE_DirectionConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_DirectionConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_DirectionConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the direction function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_UDS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_UDS_Pos; + + slice->CMC = cmc; +} + +/* API to configure slice status bit override function */ +void XMC_CCU4_SLICE_StatusBitOverrideConfig(XMC_CCU4_SLICE_t *const slice) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_StatusBitOverrideConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + + /* Bind the event with the override function */ + cmc = slice->CMC; + /* Map status bit trigger override to Event 1 & + status bit value override to Event 2 */ + cmc &= ~((uint32_t) CCU4_CC4_CMC_OFS_Msk); + cmc |= ((uint32_t) 1) << CCU4_CC4_CMC_OFS_Pos; + + slice->CMC = cmc; +} + +/* API to configure trap function */ +void XMC_CCU4_SLICE_TrapConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_TRAP_EXIT_MODE_t exit_mode, + const bool synch_with_pwm) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU4_SLICE_TrapConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_TrapConfig:Invalid Exit Mode", ((exit_mode == XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC) ||\ + (exit_mode == XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW))); + + /* First, Map trap function to Event 2 */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_TS_Msk); + cmc |= ((uint32_t) 1) << CCU4_CC4_CMC_TS_Pos; + slice->CMC = cmc; + + /* Next, Configure synchronization option */ + tc = slice->TC; + + if (synch_with_pwm == (bool) true) + { + tc |= (uint32_t) CCU4_CC4_TC_TRPSE_Msk; + } + else + { + tc &= ~((uint32_t) CCU4_CC4_TC_TRPSE_Msk); + } + + /* Configure exit mode */ + if (exit_mode == XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW) + { + tc |= (uint32_t) CCU4_CC4_TC_TRPSW_Msk; + } + else + { + tc &= ~((uint32_t) CCU4_CC4_TC_TRPSW_Msk); + } + + slice->TC = tc; +} + +/* API to configure a slice Status Bit Override event */ +void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev2_config) +{ + uint32_t ins; + + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", + XMC_CCU4_SLICE_IsInputvalid(ev1_config->mapped_input)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", + XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(ev1_config->edge)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", + ((ev1_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (ev1_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", + XMC_CCU4_SLICE_CHECK_EVENT_FILTER(ev1_config->duration)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", + XMC_CCU4_SLICE_IsInputvalid(ev2_config->mapped_input)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", + XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(ev2_config->edge)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", + ((ev2_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (ev2_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", + XMC_CCU4_SLICE_CHECK_EVENT_FILTER(ev2_config->duration)); +#if defined(CCU4V3) /* Defined for XMC1400 devices only */ + ins = slice->INS2; + + /* Configure the edge sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS2_EV1EM_Pos); + ins |= ((uint32_t) ev1_config->edge) << CCU4_CC4_INS2_EV1EM_Pos; + + /* Configure the edge sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS2_EV2EM_Pos); + ins |= ((uint32_t) ev2_config->edge) << CCU4_CC4_INS2_EV2EM_Pos; + + /* Configure the level sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS2_EV1LM_Pos); + ins |= ((uint32_t) ev1_config->level) << CCU4_CC4_INS2_EV1LM_Pos; + + /* Configure the level sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS2_EV2LM_Pos); + ins |= ((uint32_t) ev2_config->level) << CCU4_CC4_INS2_EV2LM_Pos; + + /* Configure the debounce filter for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS2_LPF1M_Pos); + ins |= ((uint32_t) ev1_config->duration) << CCU4_CC4_INS2_LPF1M_Pos; + + /* Configure the debounce filter for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS2_LPF2M_Pos); + ins |= ((uint32_t) ev2_config->duration) << CCU4_CC4_INS2_LPF2M_Pos; + + slice->INS2 = ins; + + ins = slice->INS1; + + /* Next, the input for Event1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS1_EV1IS_Pos); + ins |= ((uint32_t) ev1_config->mapped_input) << CCU4_CC4_INS1_EV1IS_Pos; + + /* Finally, the input for Event2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS1_EV2IS_Pos); + ins |= ((uint32_t) ev2_config->mapped_input) << CCU4_CC4_INS1_EV2IS_Pos; + + slice->INS1 = ins; +#else + ins = slice->INS; + + /* Configure the edge sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS_EV1EM_Pos); + ins |= ((uint32_t) ev1_config->edge) << CCU4_CC4_INS_EV1EM_Pos; + + /* Configure the edge sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS_EV2EM_Pos); + ins |= ((uint32_t) ev2_config->edge) << CCU4_CC4_INS_EV2EM_Pos; + + /* Configure the level sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS_EV1LM_Pos); + ins |= ((uint32_t) ev1_config->level) << CCU4_CC4_INS_EV1LM_Pos; + + /* Configure the level sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS_EV2LM_Pos); + ins |= ((uint32_t) ev2_config->level) << CCU4_CC4_INS_EV2LM_Pos; + + /* Configure the debounce filter for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS_LPF1M_Pos); + ins |= ((uint32_t) ev1_config->duration) << CCU4_CC4_INS_LPF1M_Pos; + + /* Configure the debounce filter for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS_LPF2M_Pos); + ins |= ((uint32_t) ev2_config->duration) << CCU4_CC4_INS_LPF2M_Pos; + + /* Next, the input for Event1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS_EV1IS_Pos); + ins |= ((uint32_t) ev1_config->mapped_input) << CCU4_CC4_INS_EV1IS_Pos; + + /* Finally, the input for Event2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS_EV2IS_Pos); + ins |= ((uint32_t) ev2_config->mapped_input) << CCU4_CC4_INS_EV2IS_Pos; + + slice->INS = ins; +#endif +} + +/* API to configure a slice trigger event */ +void XMC_CCU4_SLICE_ConfigureEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const config) +{ + uint32_t ins; + uint8_t pos; + uint8_t offset; + + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Input", XMC_CCU4_SLICE_IsInputvalid(config->mapped_input)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Edge Sensitivity", + XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(config->edge)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Level Sensitivity", + ((config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Debounce Period", + XMC_CCU4_SLICE_CHECK_EVENT_FILTER(config->duration)); + /* Calculate offset with reference to event */ + offset = ((uint8_t) event) - 1U; + +#if defined(CCU4V3) /* Defined for XMC1400 devices only */ + ins = slice->INS2; + + /* First, configure the edge sensitivity */ + pos = ((uint8_t) CCU4_CC4_INS2_EV0EM_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->edge) << pos; + + /* Next, the level */ + pos = ((uint8_t) CCU4_CC4_INS2_EV0LM_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->level) << pos; + + /* Next, the debounce filter */ + pos = ((uint8_t) CCU4_CC4_INS2_LPF0M_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->duration) << pos; + + slice->INS2 = ins; + + ins = slice->INS1; + + /* Finally the input */ + pos = ((uint8_t) CCU4_CC4_INS1_EV0IS_Pos) + (uint8_t)(offset << 3U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->mapped_input) << pos; + + slice->INS1 = ins; + +#else + ins = slice->INS; + + /* First, configure the edge sensitivity */ + pos = ((uint8_t) CCU4_CC4_INS_EV0EM_Pos) + (uint8_t)(offset << 1U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->edge) << pos; + + /* Next, the level */ + pos = ((uint8_t) CCU4_CC4_INS_EV0LM_Pos) + offset; + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->level) << pos; + + /* Next, the debounce filter */ + pos = ((uint8_t) CCU4_CC4_INS_LPF0M_Pos) + (uint8_t)(offset << 1U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->duration) << pos; + + /* Finally the input */ + pos = ((uint8_t) CCU4_CC4_INS_EV0IS_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->mapped_input) << pos; + + slice->INS = ins; +#endif +} + +/* API to bind an input to a slice trigger event */ +void XMC_CCU4_SLICE_SetInput(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_INPUT_t input) +{ + uint32_t ins; + uint8_t pos; + uint8_t offset; + + XMC_ASSERT("XMC_CCU4_SLICE_SetInput:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetInput:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU4_SLICE_SetInput:Invalid Input", XMC_CCU4_SLICE_IsInputvalid(input)); + + /* Calculate offset with reference to event */ + offset = ((uint8_t) event) - 1U; + +#if defined(CCU4V3) /* Defined for XMC1400 devices only */ + pos = ((uint8_t) CCU4_CC4_INS1_EV0IS_Pos) + (uint8_t) (offset << 3U); + + ins = slice->INS1; + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) input) << pos; + + slice->INS1 = ins; +#else + pos = ((uint8_t) CCU4_CC4_INS_EV0IS_Pos) + (uint8_t) (offset << 2U); + + ins = slice->INS; + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) input) << pos; + + slice->INS = ins; +#endif +} + +/* API to program timer repeat mode - Single shot vs repeat */ +void XMC_CCU4_SLICE_SetTimerRepeatMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t mode) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerRepeatMode:Invalid Timer Repeat Mode", + ((mode == XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT) ||\ + (mode == XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE))); + + if (XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT == mode) + { + slice->TC &= ~((uint32_t) CCU4_CC4_TC_TSSM_Msk); + } + else + { + slice->TC |= (uint32_t) CCU4_CC4_TC_TSSM_Msk; + } +} + +/* Programs timer counting mode */ +void XMC_CCU4_SLICE_SetTimerCountingMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_COUNT_MODE_t mode) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerCountingMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerCountingMode:Invalid Timer Count Mode", ((mode == XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA) ||\ + (mode == XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA))); + + if (XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA == mode) + { + slice->TC &= ~((uint32_t) CCU4_CC4_TC_TCM_Msk); + } + else + { + slice->TC |= (uint32_t) CCU4_CC4_TC_TCM_Msk; + } +} + +/* Retrieves desired capture register value */ +uint32_t XMC_CCU4_SLICE_GetCaptureRegisterValue(const XMC_CCU4_SLICE_t *const slice, const uint8_t reg_num) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetCaptureRegisterValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_GetCaptureRegisterValue:Invalid register number", (reg_num < 4U)); + return(slice->CV[reg_num]); +} + +/* @brief Retrieves the latest captured timer value */ +XMC_CCU4_STATUS_t XMC_CCU4_SLICE_GetLastCapturedTimerValue(const XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr) +{ + XMC_CCU4_STATUS_t retval; + uint8_t i; + uint8_t start; + uint8_t end; + + XMC_ASSERT("XMC_CCU4_SLICE_GetLastCapturedTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_GetLastCapturedTimerValue:Invalid Register Set", ((set == XMC_CCU4_SLICE_CAP_REG_SET_LOW) ||\ + (set == XMC_CCU4_SLICE_CAP_REG_SET_HIGH))); + + retval = XMC_CCU4_STATUS_ERROR; + + /* First check if extended capture mode is enabled */ + if ((slice->TC) & CCU4_CC4_TC_ECM_Msk) + { + /* Extended capture mode has been enabled. So start with the lowest capture register and work your way up */ + start = 0U; + end = XMC_CCU4_NUM_SLICES_PER_MODULE; + } + else + { + /* Extended capture mode is not enabled */ + if (set == XMC_CCU4_SLICE_CAP_REG_SET_HIGH) + { + start = ((uint8_t) XMC_CCU4_NUM_SLICES_PER_MODULE) >> 1U; + end = (uint8_t) XMC_CCU4_NUM_SLICES_PER_MODULE; + } + else + { + start = 0U; + end = ((uint8_t) XMC_CCU4_NUM_SLICES_PER_MODULE) >> 1U; + } + } + + for(i=start; i < end; i++) + { + if ( (slice->CV[i]) & CCU4_CC4_CV_FFL_Msk ) + { + *val_ptr = slice->CV[i]; + retval = XMC_CCU4_STATUS_OK; + break; + } + } + + return retval; +} + +/* Retrieves timer capture value from a FIFO made of capture registers */ +#if defined(CCU4V1) /* Defined for XMC4500, XMC400, XMC4200, XMC4100 devices only */ +int32_t XMC_CCU4_GetCapturedValueFromFifo(const XMC_CCU4_MODULE_t *const module, const uint8_t slice_number) +{ + int32_t cap; + uint32_t extracted_slice; + + XMC_ASSERT("XMC_CCU4_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU4_IsValidModule(module)); + + /* First read the global fifo register */ + cap = (int32_t) module->ECRD; + + extracted_slice = (((uint32_t) cap) & ((uint32_t) CCU4_ECRD_SPTR_Msk)) >> CCU4_ECRD_SPTR_Pos; + + /* Return captured result only if it were applicable to this slice */ + if(extracted_slice != ((uint32_t)slice_number)) + { + cap = -1; + } + + return (cap); +} +#else +uint32_t XMC_CCU4_SLICE_GetCapturedValueFromFifo(const XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAP_REG_SET_t set) +{ + uint32_t cap; + + XMC_ASSERT("XMC_CCU4_SLICE_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_GetCapturedValueFromFifo:Invalid Register Set", + ((set == XMC_CCU4_SLICE_CAP_REG_SET_LOW) ||\ + (set == XMC_CCU4_SLICE_CAP_REG_SET_HIGH))); + + if(XMC_CCU4_SLICE_CAP_REG_SET_LOW == set) + { + cap = slice->ECRD0; + } + else + { + cap = slice->ECRD1; + } + + return cap; +} +#endif + +/* Enables PWM dithering feature */ +void XMC_CCU4_SLICE_EnableDithering(XMC_CCU4_SLICE_t *const slice, + const bool period_dither, + const bool duty_dither, + const uint8_t spread) +{ + uint32_t tc; + + XMC_ASSERT("XMC_CCU4_SLICE_EnableDithering:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + + tc = slice->TC; + tc &= ~((uint32_t) CCU4_CC4_TC_DITHE_Msk); + + if ((bool) true == period_dither) + { + tc |= (((uint32_t) XMC_CCU4_SLICE_DITHER_PERIOD_MASK) << CCU4_CC4_TC_DITHE_Pos); + } + if ((bool) true == duty_dither) + { + tc |= (((uint32_t) XMC_CCU4_SLICE_DITHER_DUTYCYCLE_MASK) << CCU4_CC4_TC_DITHE_Pos); + } + + slice->TC = tc; + + XMC_CCU4_SLICE_SetDitherCompareValue((XMC_CCU4_SLICE_t *)slice, (uint8_t)spread); +} + +/* Programs Pre-scalar divider */ +void XMC_CCU4_SLICE_SetPrescaler(XMC_CCU4_SLICE_t *const slice, const uint8_t div_val) +{ + uint32_t fpc; + + XMC_ASSERT("XMC_CCU4_SLICE_SetPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + + fpc = slice->FPC; + fpc &= ~((uint32_t) CCU4_CC4_FPC_PVAL_Msk); + fpc |= ((uint32_t) div_val) << CCU4_CC4_FPC_PVAL_Pos; + slice->FPC = fpc; + /* + * In any case, update the initial value of the divider which is to be loaded once the prescaler increments to the + * compare value. + */ + slice->PSC = (uint32_t) div_val; +} + +/* Binds a capcom event to an NVIC node */ +void XMC_CCU4_SLICE_SetInterruptNode(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_IRQ_ID_t event, + const XMC_CCU4_SLICE_SR_ID_t sr) +{ + uint32_t srs; + uint32_t pos; + uint32_t mask; + + XMC_ASSERT("XMC_CCU4_SLICE_SetInterruptNode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetInterruptNode:Invalid SR ID ", XMC_CCU4_SLICE_CHECK_SR_ID(sr)); + XMC_ASSERT("XMC_CCU4_SLICE_SetInterruptNode:Invalid event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + + srs = slice->SRS; + + switch(event) + { + case XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH: + case XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH: + mask = ((uint32_t) CCU4_CC4_SRS_POSR_Msk); + pos = CCU4_CC4_SRS_POSR_Pos; + break; + + case XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP: + case XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN: + mask = ((uint32_t) CCU4_CC4_SRS_CMSR_Msk); + pos = CCU4_CC4_SRS_CMSR_Pos; + break; + + case XMC_CCU4_SLICE_IRQ_ID_EVENT0: + mask = ((uint32_t) CCU4_CC4_SRS_E0SR_Msk); + pos = CCU4_CC4_SRS_E0SR_Pos; + break; + + case XMC_CCU4_SLICE_IRQ_ID_EVENT1: + mask = ((uint32_t) CCU4_CC4_SRS_E1SR_Msk); + pos = CCU4_CC4_SRS_E1SR_Pos; + break; + + default: + mask = ((uint32_t) CCU4_CC4_SRS_E2SR_Msk); + pos = CCU4_CC4_SRS_E2SR_Pos; + break; + } + + srs &= ~mask; + srs |= (uint32_t)sr << pos; + slice->SRS = srs; +} + +/* Asserts passive level for the slice output */ +void XMC_CCU4_SLICE_SetPassiveLevel(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t level) +{ + uint32_t psl; + + XMC_ASSERT("XMC_CCU4_SLICE_SetPassiveLevel:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetPassiveLevel:Invalid Passive level", ((level == XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW) ||\ + (level == XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH))); + + psl = slice->PSL; + psl &= ~((uint32_t) CCU4_CC4_PSL_PSL_Msk); + psl |= (uint32_t) level; + + /* Program CC4 slice output passive level */ + slice->PSL = psl; +} + +#endif /* CCU40 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ccu8.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ccu8.c new file mode 100644 index 00000000..e5ece680 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ccu8.c @@ -0,0 +1,1320 @@ +/** + * @file xmc_ccu8.c + * @date 2017-02-25 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API
+ * - Added XMC_CCU8_SLICE_LoadSelector() API, to select which compare register value has to be loaded + * during external load event. + * + * 2015-07-24: + * - XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
+ * + * 2015-08-17: + * - XMC_CCU8_SLICE_CHC_CONFIG_MASK is not applicable to XMC14 devices.
+ * - Start of prescaler XMC_CCU8_StartPrescaler() is invoked in XMC_CCU8_Init() API.
+ * - In XMC_CCU8_SLICE_CompareInit(), CHC register is updated according to the device.
+ * - Bug fix XMC_CCU8_SLICE_ConfigureEvent() during the level setting for XMC14 devices.
+ * - XMC_CCU8_EnableShadowTransfer() definition is removed, since the API is made as inline.
+ * + * 2015-10-07: + * - XMC_CCU8_SLICE_GetEvent() is made as inline. + * - DOC updates for the newly added APIs. + * + * 2017-02-25: + * - XMC_CCU8_lAssertReset(), XMC_CCU8_lDeassertReset(), XMC_CCU8_lGateClock() and XMC_CCU8_lUngateClock() fix compilation warnings. + * + * @endcond + */ +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_ccu8.h" + +#if defined(CCU80) +#include "xmc_scu.h" + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_CCU8_NUM_SLICES_PER_MODULE (4U) +#define XMC_CCU8_SLICE_DITHER_PERIOD_MASK (1U) +#define XMC_CCU8_SLICE_DITHER_DUTYCYCLE_MASK (2U) +#define XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK (3U) +#define XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK (1U) +#define XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK (3U) +#if defined(CCU8V3) /* Defined for XMC1400 devices */ +#define XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK CCU8_CC8_INS1_EV0IS_Msk +#else +#define XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK CCU8_CC8_INS_EV0IS_Msk +#endif +#define XMC_CCU8_GIDLC_CLOCK_MASK (15U) +#define XMC_CCU8_GCSS_SLICE0_MASK (1U) +#define XMC_CCU8_GCSS_SLICE1_MASK (16U) +#define XMC_CCU8_GCSS_SLICE2_MASK (256U) +#define XMC_CCU8_GCSS_SLICE3_MASK (4096U) +#define XMC_CCU8_SLICE_DEAD_TIME_CONFIG_MASK (63U) +#if !defined(CCU8V3) /* Defined for all devices except XMC1400 */ +#define XMC_CCU8_SLICE_CHC_CONFIG_MASK (20U) +#endif + +#define XMC_CCU8_SLICE_CHECK_DTC_DIV(div) \ + ((div == XMC_CCU8_SLICE_DTC_DIV_1) || \ + (div == XMC_CCU8_SLICE_DTC_DIV_2) || \ + (div == XMC_CCU8_SLICE_DTC_DIV_4) || \ + (div == XMC_CCU8_SLICE_DTC_DIV_8)) + +#define XMC_CCU8_SLICE_CHECK_CLOCK(clock) \ + ((clock == XMC_CCU8_CLOCK_SCU) || \ + (clock == XMC_CCU8_CLOCK_EXTERNAL_A) || \ + (clock == XMC_CCU8_CLOCK_EXTERNAL_B) || \ + (clock == XMC_CCU8_CLOCK_EXTERNAL_C)) + +#define XMC_CCU8_SLICE_CHECK_OUTPUT(out) \ + ((out == XMC_CCU8_SLICE_OUTPUT_0) || \ + (out == XMC_CCU8_SLICE_OUTPUT_1) || \ + (out == XMC_CCU8_SLICE_OUTPUT_2) || \ + (out == XMC_CCU8_SLICE_OUTPUT_3)) + +#define XMC_CCU8_SLICE_CHECK_END_MODE(end_mode) \ + ((end_mode == XMC_CCU8_SLICE_END_MODE_TIMER_STOP) || \ + (end_mode == XMC_CCU8_SLICE_END_MODE_TIMER_CLEAR) || \ + (end_mode == XMC_CCU8_SLICE_END_MODE_TIMER_STOP_CLEAR)) + +#define XMC_CCU8_SLICE_CHECK_EVENT_ID(event_id) \ + ((event_id == XMC_CCU8_SLICE_EVENT_NONE)|| \ + (event_id == XMC_CCU8_SLICE_EVENT_0) || \ + (event_id == XMC_CCU8_SLICE_EVENT_1) || \ + (event_id == XMC_CCU8_SLICE_EVENT_2)) + +#define XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(edge) \ + ((edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_NONE) || \ + (edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE) || \ + (edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE)|| \ + (edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE)) + +#define XMC_CCU8_SLICE_CHECK_EVENT_FILTER(cycles) \ + ((cycles == XMC_CCU8_SLICE_EVENT_FILTER_DISABLED) || \ + (cycles == XMC_CCU8_SLICE_EVENT_FILTER_3_CYCLES) || \ + (cycles == XMC_CCU8_SLICE_EVENT_FILTER_5_CYCLES) || \ + (cycles == XMC_CCU8_SLICE_EVENT_FILTER_7_CYCLES)) + +#define XMC_CCU8_SLICE_CHECK_CAP_TIMER_CLEAR_MODE(mode) \ + ((mode == XMC_CCU8_SLICE_TIMER_CLEAR_MODE_NEVER) || \ + (mode == XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_HIGH)|| \ + (mode == XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_LOW) || \ + (mode == XMC_CCU8_SLICE_TIMER_CLEAR_MODE_ALWAYS)) + +#define XMC_CCU8_SLICE_CHECK_MCS_ACTION(mcs_action) \ + ((mcs_action == XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR) || \ + (mcs_action == XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP) || \ + (mcs_action == XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT)) + +#define XMC_CCU8_SLICE_CHECK_SR_ID(id) \ + ((id == XMC_CCU8_SLICE_SR_ID_0) || \ + (id == XMC_CCU8_SLICE_SR_ID_1) || \ + (id == XMC_CCU8_SLICE_SR_ID_2) || \ + (id == XMC_CCU8_SLICE_SR_ID_3)) + +#define XMC_CCU8_SLICE_CHECK_MODULATION_CHANNEL(channel) \ + ((channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_NONE) || \ + (channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_1) || \ + (channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_2) || \ + (channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_1_AND_2)) + +#if((UC_SERIES == XMC13) || (UC_SERIES == XMC14)) +#define XMC_CCU8_SLICE_CHECK_SLICE_STATUS(channel) \ + ((channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1) || \ + (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_2) || \ + (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1_AND_2) || \ + (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1_OR_2)) +#else +#define XMC_CCU8_SLICE_CHECK_SLICE_STATUS(channel) \ + ((channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1) || \ + (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_2) || \ + (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1_AND_2)) +#endif + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ +#if defined(PERIPHERAL_RESET_SUPPORTED) +__STATIC_INLINE void XMC_CCU8_lAssertReset(const XMC_CCU8_MODULE_t *const module) +{ + if (module == CCU80) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU80); + } +#if defined(CCU81) + else if (module == CCU81) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU81); + } +#endif + else + { + XMC_ASSERT("XMC_CCU8_lAssertReset:Invalid Module Pointer", 0); + } +} + +__STATIC_INLINE void XMC_CCU8_lDeassertReset(const XMC_CCU8_MODULE_t *const module) +{ + if (module == CCU80) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU80); + } +#if defined(CCU81) + else if (module == CCU81) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU81); + } +#endif + else + { + XMC_ASSERT("XMC_CCU8_lDeassertReset:Invalid Module Pointer", 0); + } +} +#endif + +#if defined(CLOCK_GATING_SUPPORTED) +__STATIC_INLINE void XMC_CCU8_lGateClock(XMC_CCU8_MODULE_t *const module) +{ + if (module == CCU80) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU80); + } +#if defined(CCU81) + else if (module == CCU81) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU81); + } +#endif + else + { + XMC_ASSERT("XMC_CCU8_lGateClock:Invalid Module Pointer", 0); + } +} + +__STATIC_INLINE void XMC_CCU8_lUngateClock(XMC_CCU8_MODULE_t *const module) +{ + if (module == CCU80) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU80); + } +#if defined(CCU81) + else if (module == CCU81) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU81); + } +#endif + else + { + XMC_ASSERT("XMC_CCU8_lUngateClock:Invalid Module Pointer", 0); + } +} +#endif + +#if defined (XMC_ASSERT_ENABLE) +__STATIC_INLINE bool XMC_CCU8_SLICE_IsInputvalid(XMC_CCU8_SLICE_INPUT_t input) +{ +#if (UC_SERIES == XMC14) + return (input < 48U); +#else + return (input < 16U); +#endif +} +#endif +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/* API to set the CCU8 module as active and enable the clock */ +void XMC_CCU8_EnableModule(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_EnableModule:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + +#if (UC_FAMILY == XMC4) + /* Enable CCU8 module clock */ + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_CCU8_lUngateClock(module); +#endif + +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_CCU8_lDeassertReset(module); +#endif +} + +/* API to set the CCU8 module as idle and disable the clock */ +void XMC_CCU8_DisableModule(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_DisableModule:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_CCU8_lAssertReset(module); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_CCU8_lGateClock(module); +#endif +} + +/* API to initialize CCU8 global resources */ +void XMC_CCU8_Init(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_SLICE_MCMS_ACTION_t mcs_action) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU8_Init:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_Init:Invalid mcs action", XMC_CCU8_SLICE_CHECK_MCS_ACTION(mcs_action)); + + /* Enable CCU8 module */ + XMC_CCU8_EnableModule(module); + /* Start the prescaler */ + XMC_CCU8_StartPrescaler(module); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t) CCU8_GCTRL_MSDE_Msk); + gctrl |= (uint32_t)mcs_action << CCU8_GCTRL_MSDE_Pos; + + module->GCTRL = gctrl; +} + +/* API to select CCU8 module clock */ +void XMC_CCU8_SetModuleClock(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_CLOCK_t clock) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU8_SetModuleClock:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_SetModuleClock:Invalid Module Clock", XMC_CCU8_SLICE_CHECK_CLOCK(clock)); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t) CCU8_GCTRL_PCIS_Msk); + gctrl |= ((uint32_t) clock) << CCU8_GCTRL_PCIS_Pos; + + module->GCTRL = gctrl; +} + +/* API to configure CC8 Slice in Compare mode */ +void XMC_CCU8_SLICE_CompareInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CONFIG_t *const compare_init) +{ + XMC_ASSERT("XMC_CCU8_SLICE_CompareInit:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_CompareInit:Timer Init Pointer is NULL", + (XMC_CCU8_SLICE_COMPARE_CONFIG_t *) NULL != compare_init); + /* Stops the timer */ + XMC_CCU8_SLICE_StopTimer(slice); + /* Program the timer mode */ + slice->TC = compare_init->tc; + /* Enable the timer concatenation */ + slice->CMC = (uint32_t)compare_init->timer_concatenation << CCU8_CC8_CMC_TCE_Pos; + /* Program initial prescaler divider value */ + slice->PSC = (uint32_t) compare_init->prescaler_initval; + /* Program floating prescaler compare value */ + slice->FPCS = (uint32_t) compare_init->float_limit; + /* Program the dither compare value */ + slice->DITS = (uint32_t) compare_init->dither_limit; + /* Program timer output passive level */ + slice->PSL = (uint32_t) compare_init->psl; + /* Asymmetric PWM and Slice output routing configuration */ +#if defined(CCU8V3) /* Defined for XMC1400 devices only */ + slice->CHC = (uint32_t) compare_init->chc; +#else + slice->CHC = (uint32_t)((uint32_t)compare_init->chc ^ XMC_CCU8_SLICE_CHC_CONFIG_MASK); +#endif +} + +/* API to configure CC8 Slice in Capture mode */ +void XMC_CCU8_SLICE_CaptureInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_CAPTURE_CONFIG_t *const capture_init) +{ + XMC_ASSERT("XMC_CCU8_SLICE_CaptureInit:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_CaptureInit:Capture Init Pointer is NULL", + (XMC_CCU8_SLICE_CAPTURE_CONFIG_t *) NULL != capture_init); + /* Stops the timer */ + XMC_CCU8_SLICE_StopTimer(slice); + /* Capture mode configuration */ + slice->TC = capture_init->tc; + /* Enable the timer concatenation */ + slice->CMC = (uint32_t)capture_init->timer_concatenation << CCU8_CC8_CMC_TCE_Pos; + /* Program floating prescaler compare value */ + slice->FPCS = (uint32_t) capture_init->float_limit; + /* Program initial prescaler divider value */ + slice->PSC = (uint32_t) capture_init->prescaler_initval; +} + +/* API to configure the each output of the slice with either STx or inverted STx. */ +void XMC_CCU8_SLICE_SetOutPath(XMC_CCU8_SLICE_t *const slice, const uint32_t out_path_msk) +{ + uint32_t chc; + XMC_ASSERT("XMC_CCU8_SLICE_SetOutPath:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + chc = slice->CHC; +#if !defined(CCU8V3) /* Defined for all devices except XMC1400 */ + chc &= ~((uint32_t)out_path_msk >> 16U); + chc |= ((uint32_t)out_path_msk & 0xFFFFU); +#else + chc &= ~((uint32_t)((uint32_t)(out_path_msk & 0xCCCC0U) >> 2U)); + chc |= ((uint32_t)out_path_msk & 0x33330U); +#endif + slice->CHC = chc; +} + +/* API to configure the multichannel shadow transfer request via SW and via the CCU8x.MCSS input. */ +void XMC_CCU8_SetMultiChannelShadowTransferMode(XMC_CCU8_MODULE_t *const module, const uint32_t slice_mode_msk) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU8_SetMultiChannelShadowTransferMode:Invalid module Pointer", XMC_CCU8_IsValidModule(module)); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t)slice_mode_msk >> 16U); + gctrl |= ((uint32_t)slice_mode_msk & 0xFFFFU); + module->GCTRL = gctrl; +} + + +/* API to configure the Start trigger function of a slice*/ +void XMC_CCU8_SLICE_StartConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_START_MODE_t start_mode) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_StartConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_StartConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU8_SLICE_StartConfig:Invalid Start Mode", + ((start_mode == XMC_CCU8_SLICE_START_MODE_TIMER_START) ||\ + (start_mode == XMC_CCU8_SLICE_START_MODE_TIMER_START_CLEAR))); + cmc = slice->CMC; + + cmc &= ~((uint32_t) CCU8_CC8_CMC_STRTS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_STRTS_Pos; + + slice->CMC = cmc; + + tc = slice->TC; + + if(start_mode == XMC_CCU8_SLICE_START_MODE_TIMER_START_CLEAR) + { + tc |= (uint32_t) CCU8_CC8_TC_STRM_Msk; + } + else + { + tc &= ~((uint32_t) CCU8_CC8_TC_STRM_Msk); + } + + slice->TC = tc; +} + +/* API to configure the Stop trigger function of a slice */ +void XMC_CCU8_SLICE_StopConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_END_MODE_t end_mode) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_StopConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_StopConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU8_SLICE_StopConfig:Invalid End Mode", XMC_CCU8_SLICE_CHECK_END_MODE(end_mode)); + + cmc = slice->CMC; + /* First, Bind the event with the stop function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_ENDS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_ENDS_Pos; + + slice->CMC = cmc; + + /* Configure the stop mode */ + tc = slice->TC; + tc &= ~((uint32_t) CCU8_CC8_TC_ENDM_Msk); + tc |= ((uint32_t) end_mode) << CCU8_CC8_TC_ENDM_Pos; + + slice->TC = tc; +} + +/* API to configure the Load trigger function of a slice*/ +void XMC_CCU8_SLICE_LoadConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_LoadConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_LoadConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + cmc = slice->CMC; + + /* First, Bind the event with the load function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_LDS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_LDS_Pos; + + slice->CMC = cmc; +} + +/* API to configure, which compare register value has to be loaded during external load event */ +void XMC_CCU8_SLICE_LoadSelector(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num) +{ + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_LoadSelector:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_LoadSelector:Invalid Channel number", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(ch_num)); + + tc = slice->TC; + + /* First, Bind the event with the load function */ + tc &= ~((uint32_t) CCU8_CC8_TC_TLS_Msk); + tc |= (uint32_t)ch_num << CCU8_CC8_TC_TLS_Pos; + + slice->TC = tc; +} + +/* API to configure the slice modulation function */ +void XMC_CCU8_SLICE_ModulationConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_MODULATION_MODE_t mod_mode, + const XMC_CCU8_SLICE_MODULATION_CHANNEL_t channel, + const bool synch_with_pwm) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid channel for modulation", + XMC_CCU8_SLICE_CHECK_MODULATION_CHANNEL(channel)); + XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid Modulation Mode", + ((mod_mode == XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_ST_OUT) ||\ + (mod_mode == XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_OUT))); + + cmc = slice->CMC; + + /* First, Bind the event with the modulation function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_MOS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_MOS_Pos; + + slice->CMC = cmc; + + tc = slice->TC; + + /* Next, Modulation mode */ + if(mod_mode == XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_OUT) + { + tc |= (uint32_t) CCU8_CC8_TC_EMT_Msk; + } + else + { + tc &= ~((uint32_t) CCU8_CC8_TC_EMT_Msk); + } + + /* Synchronization of modulation effect with PWM cycle */ + if(synch_with_pwm == true) + { + tc |= (uint32_t) CCU8_CC8_TC_EMS_Msk; + } + else + { + tc &= ~((uint32_t) CCU8_CC8_TC_EMS_Msk); + } + + /* Configure on which channel external modulation to be applied */ + tc &= ~((uint32_t) CCU8_CC8_TC_EME_Msk); + tc |= (uint32_t)channel << CCU8_CC8_TC_EME_Pos; + + slice->TC = tc; +} + +/* API to configure the slice count function */ +void XMC_CCU8_SLICE_CountConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_CountConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_CountConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + cmc = slice->CMC; + + /* First, Bind the event with the count function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_CNTS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_CNTS_Pos; + + slice->CMC = cmc; +} + +/* API to configure slice gate function */ +void XMC_CCU8_SLICE_GateConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_GateConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GateConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + cmc = slice->CMC; + + /* First, Bind the event with the gate function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_GATES_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_GATES_Pos; + + slice->CMC = cmc; +} + +/* API to configure Capture-0 function */ +void XMC_CCU8_SLICE_Capture0Config(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_Capture0Config:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_Capture0Config:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + cmc = slice->CMC; + + /* First, Bind the event with the gate function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_CAP0S_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_CAP0S_Pos; + + slice->CMC = cmc; +} + +/* API to configure Capture-1 function */ +void XMC_CCU8_SLICE_Capture1Config(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_Capture1Config:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_Capture1Config:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + + cmc = slice->CMC; + + /* First, Bind the event with the gate function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_CAP1S_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_CAP1S_Pos; + + slice->CMC = cmc; +} + +/* API to configure direction function */ +void XMC_CCU8_SLICE_DirectionConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_DirectionConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_DirectionConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + cmc = slice->CMC; + + /* First, Bind the event with the direction function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_UDS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_UDS_Pos; + + slice->CMC = cmc; +} + +/* API to configure slice status bit override function */ +void XMC_CCU8_SLICE_StatusBitOverrideConfig(XMC_CCU8_SLICE_t *const slice) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_StatusBitOverrideConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + + cmc = slice->CMC; + + /* Map status bit trigger override to Event 1 & + status bit value override to Event 2 */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_OFS_Msk); + cmc |= ((uint32_t) 1) << CCU8_CC8_CMC_OFS_Pos; + + slice->CMC = cmc; +} + +/* API to configure trap function*/ +void XMC_CCU8_SLICE_TrapConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_TRAP_EXIT_MODE_t exit_mode, + const bool synch_with_pwm) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_TrapConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_TrapConfig:Invalid Exit Mode", ((exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_AUTOMATIC) ||\ + (exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW))); + + cmc = slice->CMC; + + /* Map trap function to Event 2 */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_TS_Msk); + cmc |= ((uint32_t) 1) << CCU8_CC8_CMC_TS_Pos; + + slice->CMC = cmc; + + tc = slice->TC; + + /* Configure synchronization option */ + if(synch_with_pwm == true) + { + tc |= (uint32_t) CCU8_CC8_TC_TRPSE_Msk; + } + else + { + tc &= ~((uint32_t) CCU8_CC8_TC_TRPSE_Msk); + } + + /* Configure exit mode */ + if(exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW) + { + tc |= (uint32_t) CCU8_CC8_TC_TRPSW_Msk; + } + else + { + tc &= ~((uint32_t) CCU8_CC8_TC_TRPSW_Msk); + } + + slice->TC = tc; +} + +/* API to configure a slice Status Bit Override event */ +void XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev2_config) +{ + uint32_t ins; + + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", + XMC_CCU8_SLICE_IsInputvalid(ev1_config->mapped_input)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", + XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(ev1_config->edge)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", + ((ev1_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (ev1_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", + XMC_CCU8_SLICE_CHECK_EVENT_FILTER(ev1_config->duration)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", + XMC_CCU8_SLICE_IsInputvalid(ev2_config->mapped_input)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", + XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(ev2_config->edge)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", + ((ev2_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (ev2_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", + XMC_CCU8_SLICE_CHECK_EVENT_FILTER(ev2_config->duration)); + +#if defined(CCU8V3) /* Defined for XMC1400 devices only */ + ins = slice->INS2; + + /* Configure the edge sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU8_CC8_INS2_EV1EM_Pos); + ins |= ((uint32_t) ev1_config->edge) << CCU8_CC8_INS2_EV1EM_Pos; + + /* Configure the edge sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU8_CC8_INS2_EV2EM_Pos); + ins |= ((uint32_t) ev2_config->edge) << CCU8_CC8_INS2_EV2EM_Pos; + + /* Configure the level sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU8_CC8_INS2_EV1LM_Pos); + ins |= ((uint32_t) ev1_config->level) << CCU8_CC8_INS2_EV1LM_Pos; + + /* Configure the level sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU8_CC8_INS2_EV2LM_Pos); + ins |= ((uint32_t) ev2_config->level) << CCU8_CC8_INS2_EV2LM_Pos; + + /* Configure the debounce filter for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU8_CC8_INS2_LPF1M_Pos); + ins |= ((uint32_t) ev1_config->duration) << CCU8_CC8_INS2_LPF1M_Pos; + + /* Configure the debounce filter for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU8_CC8_INS2_LPF2M_Pos); + ins |= ((uint32_t) ev2_config->duration) << CCU8_CC8_INS2_LPF2M_Pos; + + slice->INS2 = ins; + + ins = slice->INS1; + /* Next, the input for Event1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU8_CC8_INS1_EV1IS_Pos); + ins |= ((uint32_t) ev1_config->mapped_input) << CCU8_CC8_INS1_EV1IS_Pos; + + /* Finally, the input for Event2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU8_CC8_INS1_EV2IS_Pos); + ins |= ((uint32_t) ev2_config->mapped_input) << CCU8_CC8_INS1_EV2IS_Pos; + + slice->INS1 = ins; +#else + ins = slice->INS; + + /* Configure the edge sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU8_CC8_INS_EV1EM_Pos); + ins |= ((uint32_t) ev1_config->edge) << CCU8_CC8_INS_EV1EM_Pos; + + /* Configure the edge sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU8_CC8_INS_EV2EM_Pos); + ins |= ((uint32_t) ev2_config->edge) << CCU8_CC8_INS_EV2EM_Pos; + + /* Configure the level sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU8_CC8_INS_EV1LM_Pos); + ins |= ((uint32_t) ev1_config->level) << CCU8_CC8_INS_EV1LM_Pos; + + /* Configure the level sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU8_CC8_INS_EV2LM_Pos); + ins |= ((uint32_t) ev2_config->level) << CCU8_CC8_INS_EV2LM_Pos; + + /* Configure the debounce filter for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU8_CC8_INS_LPF1M_Pos); + ins |= ((uint32_t) ev1_config->duration) << CCU8_CC8_INS_LPF1M_Pos; + + /* Configure the debounce filter for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU8_CC8_INS_LPF2M_Pos); + ins |= ((uint32_t) ev2_config->duration) << CCU8_CC8_INS_LPF2M_Pos; + + /* Next, the input for Event1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU8_CC8_INS_EV1IS_Pos); + ins |= ((uint32_t) ev1_config->mapped_input) << CCU8_CC8_INS_EV1IS_Pos; + + /* Finally, the input for Event2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU8_CC8_INS_EV2IS_Pos); + ins |= ((uint32_t) ev2_config->mapped_input) << CCU8_CC8_INS_EV2IS_Pos; + + slice->INS = ins; +#endif +} + +/* API to configure a slice trigger event */ +void XMC_CCU8_SLICE_ConfigureEvent(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const config) +{ + uint32_t ins; + uint8_t pos; + uint8_t offset; + + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Input", XMC_CCU8_SLICE_IsInputvalid(config->mapped_input)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Edge Sensitivity", + XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(config->edge)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Level Sensitivity", + ((config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Debounce Period", + XMC_CCU8_SLICE_CHECK_EVENT_FILTER(config->duration)); + + /* Calculate offset with reference to event */ + offset = ((uint8_t) event) - 1U; + +#if defined(CCU8V3) /* Defined for XMC1400 devices only */ + ins = slice->INS2; + + /* First, configure the edge sensitivity */ + pos = ((uint8_t) CCU8_CC8_INS2_EV0EM_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->edge) << pos; + + /* Next, the level */ + pos = ((uint8_t) CCU8_CC8_INS2_EV0LM_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << pos); + ins |= ((uint32_t) (config->level)) << pos; + + /* Next, the debounce filter */ + pos = ((uint8_t) CCU8_CC8_INS2_LPF0M_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->duration) << pos; + + slice->INS2 = ins; + + ins = slice->INS1; + + /* Finally the input */ + pos = ((uint8_t) CCU8_CC8_INS1_EV0IS_Pos) + (uint8_t)(offset << 3U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->mapped_input) << pos; + + slice->INS1 = ins; + +#else + ins = slice->INS; + + /* First, configure the edge sensitivity */ + pos = ((uint8_t) CCU8_CC8_INS_EV0EM_Pos) + (uint8_t)(offset << 1U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->edge) << pos; + + /* Next, the level */ + pos = ((uint8_t) CCU8_CC8_INS_EV0LM_Pos) + offset; + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << pos); + ins |= ((uint32_t) (config->level)) << pos; + + /* Next, the debounce filter */ + pos = ((uint8_t) CCU8_CC8_INS_LPF0M_Pos) + (uint8_t)(offset << 1U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->duration) << pos; + + /* Finally the input */ + pos = ((uint8_t) CCU8_CC8_INS_EV0IS_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->mapped_input) << pos; + + slice->INS = ins; +#endif +} + +/* API to bind an input to a slice trigger event */ +void XMC_CCU8_SLICE_SetInput(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_INPUT_t input) +{ + uint32_t ins; + uint8_t pos; + uint8_t offset; + + XMC_ASSERT("XMC_CCU8_SLICE_SetInput:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetInput:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU8_SLICE_SetInput:Invalid Input", XMC_CCU8_SLICE_IsInputvalid(input)); + + /* Calculate offset with reference to event */ + offset = ((uint8_t) event) - 1U; + +#if defined(CCU8V3) /* Defined for XMC1400 devices only */ + pos = ((uint8_t) CCU8_CC8_INS1_EV0IS_Pos) + (uint8_t) (offset << 3U); + ins = slice->INS1; + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) input) << pos; + + slice->INS1 = ins; +#else + + pos = ((uint8_t) CCU8_CC8_INS_EV0IS_Pos) + (uint8_t) (offset << 2U); + ins = slice->INS; + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) input) << pos; + + slice->INS = ins; +#endif +} + +/* API to program timer repeat mode - Single shot vs repeat */ +void XMC_CCU8_SLICE_SetTimerRepeatMode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t mode) +{ + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerRepeatMode:Invalid Timer Repeat Mode", + ((mode == XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT) ||\ + (mode == (mode == XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT)))); + + tc = slice->TC; + + if(XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT == mode) + { + tc &= ~((uint32_t) CCU8_CC8_TC_TSSM_Msk); + } + else + { + tc |= (uint32_t) CCU8_CC8_TC_TSSM_Msk; + } + + slice->TC = tc; +} + +/* Programs timer counting mode */ +void XMC_CCU8_SLICE_SetTimerCountingMode(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_TIMER_COUNT_MODE_t mode) +{ + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCountingMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCountingMode:Invalid Timer Count Mode", + ((mode == XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA) ||\ + (mode == XMC_CCU8_SLICE_TIMER_COUNT_MODE_CA))); + + tc = slice->TC; + + if(XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA == mode) + { + tc &= ~((uint32_t) CCU8_CC8_TC_TCM_Msk); + } + else + { + tc |= (uint32_t) CCU8_CC8_TC_TCM_Msk; + } + + slice->TC = tc; +} + +/* Programs period match value of the timer */ +void XMC_CCU8_SLICE_SetTimerPeriodMatch(XMC_CCU8_SLICE_t *const slice, const uint16_t period_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->PRS = (uint32_t) period_val; +} + +/* Retrieves desired capture register value */ +uint32_t XMC_CCU8_SLICE_GetCaptureRegisterValue(const XMC_CCU8_SLICE_t *const slice, const uint8_t reg_num) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetCaptureRegisterValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GetCaptureRegisterValue:Invalid register number", (reg_num < 4U)); + return(slice->CV[reg_num]); +} + +/* @brief Retrieves the latest captured timer value */ +XMC_CCU8_STATUS_t XMC_CCU8_SLICE_GetLastCapturedTimerValue(const XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr) +{ + + XMC_CCU8_STATUS_t retval; + uint8_t i; + uint8_t start; + uint8_t end; + + XMC_ASSERT("XMC_CCU8_SLICE_GetLastCapturedTimerValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GetLastCapturedTimerValue:Invalid Register Set", + ((set == XMC_CCU8_SLICE_CAP_REG_SET_LOW) ||\ + (set == XMC_CCU8_SLICE_CAP_REG_SET_HIGH))); + + retval = XMC_CCU8_STATUS_ERROR; + + /* First check if extended capture mode is enabled */ + if((slice->TC) & CCU8_CC8_TC_ECM_Msk) + { + /* Extended capture mode has been enabled. So start with the lowest capture register and work your way up */ + start = 0U; + end = XMC_CCU8_NUM_SLICES_PER_MODULE; + } + else + { + /* Extended capture mode is not enabled */ + if(set == XMC_CCU8_SLICE_CAP_REG_SET_HIGH) + { + start = ((uint8_t) XMC_CCU8_NUM_SLICES_PER_MODULE) >> 1U; + end = (uint8_t) XMC_CCU8_NUM_SLICES_PER_MODULE; + } + else + { + start = 0U; + end = ((uint8_t) XMC_CCU8_NUM_SLICES_PER_MODULE) >> 1U; + } + } + + for(i=start; iCV[i]) & CCU8_CC8_CV_FFL_Msk ) + { + *val_ptr = slice->CV[i]; + retval = XMC_CCU8_STATUS_OK; + break; + } + } + + return retval; +} +/* Retrieves timer capture value from a FIFO made of capture registers */ +#if defined(CCU8V1) /* Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only */ +int32_t XMC_CCU8_GetCapturedValueFromFifo(const XMC_CCU8_MODULE_t *const module, const uint8_t slice_number) +{ + int32_t cap; + uint32_t extracted_slice; + + XMC_ASSERT("XMC_CCU8_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU8_IsValidModule(module)); + + /* First read the global fifo register */ + cap = (int32_t) module->ECRD; + + extracted_slice = (((uint32_t) cap) & ((uint32_t) CCU8_ECRD_SPTR_Msk)) >> CCU8_ECRD_SPTR_Pos; + + /* Return captured result only if it were applicable to this slice */ + if(extracted_slice != ((uint32_t)slice_number)) + { + cap = -1; + } + + return (cap); +} +#else +/* Retrieves timer capture value from a FIFO made of capture registers */ +uint32_t XMC_CCU8_SLICE_GetCapturedValueFromFifo(const XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_CAP_REG_SET_t set) +{ + uint32_t cap; + + XMC_ASSERT("XMC_CCU8_SLICE_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GetCapturedValueFromFifo:Invalid Register Set", + ((set == XMC_CCU8_SLICE_CAP_REG_SET_LOW) ||\ + (set == XMC_CCU8_SLICE_CAP_REG_SET_HIGH))); + + if(XMC_CCU8_SLICE_CAP_REG_SET_LOW == set) + { + cap = slice->ECRD0; + } + else + { + cap = slice->ECRD1; + } + + return cap; +} +#endif + +/* Enables PWM dithering feature */ +void XMC_CCU8_SLICE_EnableDithering(XMC_CCU8_SLICE_t *const slice, + const bool period_dither, + const bool duty_dither, + const uint8_t spread) +{ + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_EnableDithering:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + + tc = slice->TC; + tc &= ~((uint32_t) CCU8_CC8_TC_DITHE_Msk); + + if(true == period_dither) + { + tc |= (((uint32_t) XMC_CCU8_SLICE_DITHER_PERIOD_MASK) << CCU8_CC8_TC_DITHE_Pos); + } + if(true == duty_dither) + { + tc |= (((uint32_t) XMC_CCU8_SLICE_DITHER_DUTYCYCLE_MASK) << CCU8_CC8_TC_DITHE_Pos); + } + + slice->TC = tc; + + XMC_CCU8_SLICE_SetDitherCompareValue((XMC_CCU8_SLICE_t *)slice, (uint8_t)spread); +} + +/* Programs Pre-scaler divider */ +void XMC_CCU8_SLICE_SetPrescaler(XMC_CCU8_SLICE_t *const slice, const uint8_t div_val) +{ + uint32_t fpc; + + XMC_ASSERT("XMC_CCU8_SLICE_SetPrescaler:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + + /* If the prescaler is not running, update directly the divider*/ + fpc = slice->FPC; + fpc &= ~((uint32_t) CCU8_CC8_FPC_PVAL_Msk); + fpc |= ((uint32_t) div_val) << CCU8_CC8_FPC_PVAL_Pos; + slice->FPC = fpc; + + /* + * In any case, update the initial value of the divider which is to be loaded once the prescaler increments to the + * compare value. + */ + slice->PSC = (uint32_t) div_val; +} + +/* Programs timer compare match value for channel 1 or 2 */ +void XMC_CCU8_SLICE_SetTimerCompareMatch(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, + const uint16_t compare_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCompareMatch:Invalid channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(channel)); + + if (XMC_CCU8_SLICE_COMPARE_CHANNEL_1 == channel) + { + slice->CR1S = (uint32_t) compare_val; + } + else + { + slice->CR2S = (uint32_t) compare_val; + } +} + +/* Returns the timer compare match value for channel 1 or 2 */ +uint16_t XMC_CCU8_SLICE_GetTimerCompareMatch(const XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel) +{ + uint16_t compare_value; + + XMC_ASSERT("XMC_CCU8_SLICE_GetCompareMatch:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GetCompareMatch:Invalid channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(channel)); + + if (XMC_CCU8_SLICE_COMPARE_CHANNEL_1 == channel) + { + compare_value = (uint16_t) slice->CR1; + } + else + { + compare_value = (uint16_t) slice->CR2; + } + + return(compare_value); +} + +/* Binds a capcom event to an NVIC node */ +void XMC_CCU8_SLICE_SetInterruptNode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_IRQ_ID_t event, + const XMC_CCU8_SLICE_SR_ID_t sr) +{ + uint32_t srs; + uint32_t mask; + uint32_t pos; + + XMC_ASSERT("XMC_CCU8_SLICE_SetInterruptNode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetInterruptNode:Invalid SR ID ", XMC_CCU8_SLICE_CHECK_SR_ID(sr)); + XMC_ASSERT("XMC_CCU8_SLICE_SetInterruptNode:Invalid event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + + srs = slice->SRS; + + switch(event) + { + case XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH: + case XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH: + mask = ((uint32_t) CCU8_CC8_SRS_POSR_Msk); + pos = CCU8_CC8_SRS_POSR_Pos; + break; + + case XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_1: + case XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_1: + mask = ((uint32_t) CCU8_CC8_SRS_CM1SR_Msk); + pos = CCU8_CC8_SRS_CM1SR_Pos; + break; + + case XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_2: + case XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_2: + mask = ((uint32_t) CCU8_CC8_SRS_CM2SR_Msk); + pos = CCU8_CC8_SRS_CM2SR_Pos; + break; + + case XMC_CCU8_SLICE_IRQ_ID_EVENT0: + mask = ((uint32_t) CCU8_CC8_SRS_E0SR_Msk); + pos = CCU8_CC8_SRS_E0SR_Pos; + break; + + case XMC_CCU8_SLICE_IRQ_ID_EVENT1: + mask = ((uint32_t) CCU8_CC8_SRS_E1SR_Msk); + pos = CCU8_CC8_SRS_E1SR_Pos; + break; + + default: + mask = ((uint32_t) CCU8_CC8_SRS_E2SR_Msk); + pos = CCU8_CC8_SRS_E2SR_Pos; + break; + } + + srs &= ~mask; + srs |= (uint32_t)sr << pos; + + slice->SRS = srs; +} + +/* Asserts passive level for the slice output */ +void XMC_CCU8_SLICE_SetPassiveLevel(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_OUTPUT_t out, + const XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t level) +{ + uint32_t psl; + + XMC_ASSERT("XMC_CCU8_SLICE_SetPassiveLevel:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetPassiveLevel:Invalid Slice Output", XMC_CCU8_SLICE_CHECK_OUTPUT(out)); + XMC_ASSERT("XMC_CCU8_SLICE_SetPassiveLevel:Invalid Passive Level", + ((level == XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_LOW) ||\ + (level == XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH))); + + psl = slice->PSL; + + psl &= ~((uint32_t) out); + psl |= (uint32_t) level << ((uint32_t)out >> 1U); + + /* Program CC8 slice output passive level */ + slice->PSL = psl; +} + +/* Initializes Dead time configuration for the slice outputs */ +void XMC_CCU8_SLICE_DeadTimeInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_DEAD_TIME_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureDeadTime:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + + /* Program dead time value for channel 1 */ + slice->DC1R = config->dc1r; + /* Program dead time value for channel 2 */ + slice->DC2R = config->dc2r; + /* Program dead time control configuration */ + slice->DTC = config->dtc; +} + +/* Activates or deactivates dead time for compare channel and ST path */ +void XMC_CCU8_SLICE_ConfigureDeadTime(XMC_CCU8_SLICE_t *const slice, const uint8_t mask) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureDeadTime:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureDeadTime:Invalid Channel", (mask <= XMC_CCU8_SLICE_DEAD_TIME_CONFIG_MASK)); + + slice->DTC &= ~((uint32_t) XMC_CCU8_SLICE_DEAD_TIME_CONFIG_MASK); + slice->DTC |= (uint32_t) mask; +} + +/* Configures rising edge delay and falling edge delay for dead time */ +void XMC_CCU8_SLICE_SetDeadTimeValue(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, + const uint8_t rise_value, + const uint8_t fall_value) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetDeadTimeValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetDeadTimeValue:Invalid channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(channel)); + + if (XMC_CCU8_SLICE_COMPARE_CHANNEL_1 == channel) + { + slice->DC1R = (((uint32_t) fall_value) << CCU8_CC8_DC1R_DT1F_Pos) | ((uint32_t) rise_value); + } + else + { + slice->DC2R = (((uint32_t) fall_value) << CCU8_CC8_DC2R_DT2F_Pos) | ((uint32_t) rise_value); + } +} + +/* Configures clock division factor for dead time */ +void XMC_CCU8_SLICE_SetDeadTimePrescaler(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_DTC_DIV_t div_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetDeadTimePrescaler:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetDeadTimePrescaler:Invalid divider value", XMC_CCU8_SLICE_CHECK_DTC_DIV(div_val)); + + slice->DTC &= ~((uint32_t) CCU8_CC8_DTC_DTCC_Msk); + slice->DTC |= ((uint32_t) div_val) << CCU8_CC8_DTC_DTCC_Pos; +} + +/* Configures status ST1, ST2 mapping to STy */ +void XMC_CCU8_SLICE_ConfigureStatusBitOutput(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_STATUS_t channel) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOutput:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOutput:Invalid Channel", XMC_CCU8_SLICE_CHECK_SLICE_STATUS(channel)); + + slice->TC &= ~((uint32_t) CCU8_CC8_TC_STOS_Msk); + slice->TC |= ((uint32_t) channel) << CCU8_CC8_TC_STOS_Pos; +} + +#endif /* CCU80 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_common.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_common.c new file mode 100644 index 00000000..73101ee4 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_common.c @@ -0,0 +1,219 @@ +/** + * @file xmc_common.c + * @date 2017-02-25 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2017-02-25: + * - Remove the need to define XMC_USER_ASSERT_FUNCTION + * - XMC_AssertHandler fixed compilation warnings + * + * @endcond + * + */ + +#include "xmc_common.h" + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ +struct list +{ + struct list *next; +}; + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ +#if defined(XMC_ASSERT_ENABLE) +__WEAK void XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line) +{ + XMC_UNUSED_ARG(msg); + XMC_UNUSED_ARG(file); + XMC_UNUSED_ARG(line); + + while(1) + { + /* Endless loop */ + } +} +#endif + +void XMC_LIST_Init(XMC_LIST_t *list) +{ + *list = NULL; +} + +void *XMC_LIST_GetHead(XMC_LIST_t *list) +{ + return *list; +} + +void *XMC_LIST_GetTail(XMC_LIST_t *list) +{ + struct list *tail; + + if (*list == NULL) + { + tail = NULL; + } + else + { + for (tail = (struct list *)*list; tail->next != NULL; tail = tail->next) + { + /* Loop through the list */ + } + } + + return tail; +} + +void XMC_LIST_Add(XMC_LIST_t *list, void *item) +{ + struct list *tail; + + ((struct list *)item)->next = NULL; + tail = (struct list *)XMC_LIST_GetTail(list); + + if (tail == NULL) + { + *list = item; + } + else + { + tail->next = (struct list *)item; + } +} + +void XMC_LIST_Remove(XMC_LIST_t *list, void *item) +{ + struct list *right, *left; + + if (*list != NULL) + { + left = NULL; + for(right = (struct list *)*list; right != NULL; right = right->next) + { + if(right == item) + { + if(left == NULL) + { + /* First on list */ + *list = right->next; + } + else + { + /* Not first on list */ + left->next = right->next; + } + right->next = NULL; + break; + } + left = right; + } + } +} + +void XMC_LIST_Insert(XMC_LIST_t *list, void *prev_item, void *new_item) +{ + if (prev_item == NULL) + { + ((struct list *)new_item)->next = (struct list *)*list; + *list = new_item; + } + else + { + ((struct list *)new_item)->next = ((struct list *)prev_item)->next; + ((struct list *)prev_item)->next = (struct list *)new_item; + } +} + +void XMC_PRIOARRAY_Init(XMC_PRIOARRAY_t *prioarray) +{ + XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL); + + /* Initialize head, next points to tail, previous to NULL and the priority is MININT */ + prioarray->items[prioarray->size].next = prioarray->size + 1; + prioarray->items[prioarray->size].previous = -1; + prioarray->items[prioarray->size].priority = INT32_MAX; + + /* Initialize tail, next points to NULL, previous is the head and the priority is MAXINT */ + prioarray->items[prioarray->size + 1].next = -1; + prioarray->items[prioarray->size + 1].previous = prioarray->size; + prioarray->items[prioarray->size + 1].priority = INT32_MIN; + +} + +void XMC_PRIOARRAY_Add(XMC_PRIOARRAY_t *prioarray, int32_t item, int32_t priority) +{ + int32_t next; + int32_t previous; + + XMC_ASSERT("XMC_PRIOARRAY_Add: item out of range", (item >= 0) && (item < prioarray->size)); + + next = XMC_PRIOARRAY_GetHead(prioarray); + while (XMC_PRIOARRAY_GetItemPriority(prioarray, next) > priority) + { + next = XMC_PRIOARRAY_GetItemNext(prioarray, next); + } + + previous = prioarray->items[next].previous; + + prioarray->items[item].next = next; + prioarray->items[item].previous = previous; + prioarray->items[item].priority = priority; + + prioarray->items[previous].next = item; + prioarray->items[next].previous = item; +} + +void XMC_PRIOARRAY_Remove(XMC_PRIOARRAY_t *prioarray, int32_t item) +{ + int32_t next; + int32_t previous; + + XMC_ASSERT("XMC_PRIOARRAY_Add: item out of range", (item >= 0) && (item < prioarray->size)); + + next = prioarray->items[item].next; + previous = prioarray->items[item].previous; + + prioarray->items[previous].next = next; + prioarray->items[next].previous = previous; +} + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_dac.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_dac.c new file mode 100644 index 00000000..20e5291e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_dac.c @@ -0,0 +1,339 @@ +/** + * @file xmc_dac.c + * @date 2015-06-19 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Initial version + * + * 2015-06-19: + * - Removed GetDriverVersion API + * @endcond + * + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include +#include + +/* DAC peripheral is not available on XMC1X devices. */ +#if defined(DAC) + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define XMC_DAC_MIN_FREQ_DIVIDER (16U) +#define XMC_DAC_MAX_FREQ_DIVIDER (1048576U) +#define XMC_DAC_DAC0PATL_PAT_BITSIZE (5U) + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +/* API to enable the DAC module */ +void XMC_DAC_Enable(XMC_DAC_t *const dac) +{ + XMC_UNUSED_ARG(dac); + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DAC); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DAC); +} + +/* API to disable the DAC module */ +void XMC_DAC_Disable(XMC_DAC_t *const dac) +{ + XMC_UNUSED_ARG(dac); + + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DAC); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DAC); +#endif +} + +/* API to check whether DAC is enabled */ +bool XMC_DAC_IsEnabled(const XMC_DAC_t *const dac) +{ + bool status; + + XMC_UNUSED_ARG(dac); + + status = XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DAC); + if(status == true) + { + status = false; + } + else + { + status = true; + } + return (status); +} + +/* API to initialize DAC channel configuration */ +void XMC_DAC_CH_Init(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_CONFIG_t *const config) +{ + XMC_DAC_Enable(dac); + + dac->DACCFG[channel].low = config->cfg0; + dac->DACCFG[channel].high = config->cfg1; + if (channel < XMC_DAC_NO_CHANNELS) + { + XMC_DAC_CH_EnableOutput(dac, channel); + } +} + +/* API to set the waveform frequency except in Ramp and Pattern generation mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetFrequency(XMC_DAC_t *const dac, + const uint8_t channel, + const uint32_t frequency) +{ + uint32_t divider; + XMC_DAC_CH_STATUS_t status; + + XMC_ASSERT("XMC_DAC_CH_SetFrequency: frequency must be greater than zero", frequency > 0U); + + divider = XMC_SCU_CLOCK_GetPeripheralClockFrequency() / frequency; + + if (divider < XMC_DAC_MIN_FREQ_DIVIDER) + { + status = XMC_DAC_CH_STATUS_ERROR_FREQ2HIGH; + } + else if (divider >= XMC_DAC_MAX_FREQ_DIVIDER) + { + status = XMC_DAC_CH_STATUS_ERROR_FREQ2LOW; + } + else { + dac->DACCFG[channel].low = (dac->DACCFG[channel].low & (uint32_t)(~DAC_DAC0CFG0_FREQ_Msk)) | + (divider << DAC_DAC0CFG0_FREQ_Pos); + status = XMC_DAC_CH_STATUS_OK; + } + + return status; +} + +/* API to set the waveform frequency in Ramp Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetRampFrequency(XMC_DAC_t *const dac, + const uint8_t channel, + const uint32_t frequency) +{ + uint32_t stop; + uint32_t start; + + start = dac->DACDATA[channel]; + stop = (dac->DAC01DATA >> (channel * DAC_DAC01DATA_DATA1_Pos)) & (uint32_t)DAC_DAC01DATA_DATA0_Msk; + + return XMC_DAC_CH_SetFrequency(dac, channel, frequency * ((stop - start) + 1U)); +} + +/* API to start the operation in Single Value Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartSingleValueMode(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_StartSingleValueMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_StartSingleValueMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_StartSingleValueMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_SINGLE); + + return XMC_DAC_CH_STATUS_OK; +} + +/* API to start the operation in Data Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartDataMode(XMC_DAC_t *const dac, + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) +{ + XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; + + XMC_ASSERT("XMC_DAC_CH_StartDataMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_StartDataMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_StartDataMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE); + + if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL) + { + status = XMC_DAC_CH_SetFrequency(dac, channel, frequency); + } + + if (status == XMC_DAC_CH_STATUS_OK) + { + XMC_DAC_CH_SetTrigger(dac, channel, trigger); + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_DATA); + } + + return status; +} + +/* API to start the operation in Ramp Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartRampMode(XMC_DAC_t *const dac, + const uint8_t channel, + const uint16_t start, + const uint16_t stop, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) +{ + XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; + + XMC_ASSERT("XMC_DAC_CH_StartRampMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_StartRampMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_StartRampMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE); + + XMC_DAC_CH_SetRampStart(dac, channel, start); + XMC_DAC_CH_SetRampStop(dac, channel, stop); + XMC_DAC_CH_SetTrigger(dac, channel, trigger); + + if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL) + { + status = XMC_DAC_CH_SetRampFrequency(dac, channel, frequency); + } + + if (status == XMC_DAC_CH_STATUS_OK) + { + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_RAMP); + } + + return status; +} + +/* API to start the operation in Pattern Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartPatternMode(XMC_DAC_t *const dac, + const uint8_t channel, + const uint8_t *const pattern, + const XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t sign_output, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) +{ + XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; + + XMC_ASSERT("XMC_DAC_CH_StartPatternMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_StartPatternMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_StartPatternMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE); + + if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL) + { + status = XMC_DAC_CH_SetFrequency(dac, channel, frequency * XMC_DAC_SAMPLES_PER_PERIOD); + } + + if (status == XMC_DAC_CH_STATUS_OK) + { + XMC_DAC_CH_SetPattern(dac, channel, pattern); + if (XMC_DAC_CH_PATTERN_SIGN_OUTPUT_ENABLED == sign_output) + { + XMC_DAC_CH_EnablePatternSignOutput(dac, channel); + } + else + { + XMC_DAC_CH_DisablePatternSignOutput(dac, channel); + } + XMC_DAC_CH_SetTrigger(dac, channel, trigger); + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_PATTERN); + } + + return status; +} + +/* API to start the operation in Noise Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartNoiseMode(XMC_DAC_t *const dac, + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) +{ + XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; + + XMC_ASSERT("XMC_DAC_CH_StartNoiseMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_StartNoiseMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_StartNoiseMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE); + + if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL) + { + status = XMC_DAC_CH_SetFrequency(dac, channel, frequency); + } + + if (status == XMC_DAC_CH_STATUS_OK) + { + XMC_DAC_CH_SetTrigger(dac, channel, trigger); + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_NOISE); + } + + return status; +} + +/* API to write the pattern data table. */ +void XMC_DAC_CH_SetPattern(XMC_DAC_t *const dac, uint8_t channel, const uint8_t *const data) +{ + uint32_t index; + uint32_t temp; + + XMC_ASSERT("XMC_DAC_CH_SetPattern: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetPattern: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_SetPattern: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + temp = data[0U]; + for(index = 1U; index < 6U; ++index) + { + temp |= (uint32_t)data[index] << (index * XMC_DAC_DAC0PATL_PAT_BITSIZE); + } + dac->DACPAT[channel].low = temp; + + temp = data[6U]; + for(index = 1U; index < 6U; ++index) + { + temp |= (uint32_t)data[index + 6U] << (index * XMC_DAC_DAC0PATL_PAT_BITSIZE); + } + dac->DACPAT[channel].high = temp; +} + +#endif /* defined(DAC) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_dma.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_dma.c new file mode 100644 index 00000000..06f2fb96 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_dma.c @@ -0,0 +1,798 @@ + +/** + * @file xmc_dma.c + * @date 2016-04-08 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - Add the declarations for the following APIs:
+ * XMC_DMA_DisableRequestLine, XMC_DMA_ClearRequestLine,
+ * XMC_DMA_CH_ClearSourcePeripheralRequest,
+ * XMC_DMA_CH_ClearDestinationPeripheralRequest
+ * - Remove PRIOARRAY
+ * - Documentation updates
+ * + * 2015-06-20: + * - Removed GetDriverVersion API
+ * - Updated XMC_DMA_CH_Init() to support scatter/gather functionality (only + * on advanced DMA channels)
+ * - Updated XMC_DMA_CH_Disable()
+ * + * 2016-03-09: + * - Optimize write only registers + * + * 2016-04-08: + * - Update XMC_DMA_CH_EnableEvent and XMC_DMA_CH_DisableEvent. + * Write optimization of MASKCHEV + * - Fix XMC_DMA_IRQHandler, clear channel event status before processing the event handler. + * It corrects event losses if the DMA triggered in the event handler finished before returning from handler. + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_dma.h" + +#if defined (GPDMA0) + +#include "xmc_scu.h" + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define DLR_SRSEL_RS_MSK (0xfUL) +#define DLR_SRSEL_RS_BITSIZE (4UL) +#define DMA_EVENT_MAX (5UL) +#define GPDMA_CH_CFGH_DEST_PER_Pos GPDMA0_CH_CFGH_DEST_PER_Pos +#define GPDMA_CH_CFGH_SRC_PER_Pos GPDMA0_CH_CFGH_SRC_PER_Pos +#define GPDMA0_CH_CFGH_PER_Msk (0x7U) +#define GPDMA1_CH_CFGH_PER_Msk (0x3U) +#define GPDMA_CH_CFGH_PER_BITSIZE (4U) +#define GPDMA_CH_CTLL_INT_EN_Msk GPDMA0_CH_CTLL_INT_EN_Msk + +/******************************************************************************* + * LOCAL DATA + *******************************************************************************/ + +#if defined (GPDMA0) +XMC_DMA_CH_EVENT_HANDLER_t dma0_event_handlers[XMC_DMA0_NUM_CHANNELS]; +#endif + +#if defined (GPDMA1) +XMC_DMA_CH_EVENT_HANDLER_t dma1_event_handlers[XMC_DMA1_NUM_CHANNELS]; +#endif + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +/* Initialize GPDMA */ +void XMC_DMA_Init(XMC_DMA_t *const dma) +{ + XMC_DMA_Enable(dma); +} + +/* Enable GPDMA module */ +void XMC_DMA_Enable(XMC_DMA_t *const dma) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA0); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA0); +#if defined(GPDMA1) + } + else + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA1); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA1); + } +#endif + + dma->DMACFGREG = 0x1U; +} + +/* Disable GPDMA module */ +void XMC_DMA_Disable(XMC_DMA_t *const dma) +{ + dma->DMACFGREG = 0x0U; + +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA0); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA0); +#endif +#if defined(GPDMA1) + } + else + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA1); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA1); +#endif + } +#endif +} + +/* Check is the GPDMA peripheral is enabled */ +bool XMC_DMA_IsEnabled(const XMC_DMA_t *const dma) +{ + bool status; + +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + status = !XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_GPDMA0); +#if defined(CLOCK_GATING_SUPPORTED) + status = status && !XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_GPDMA0); +#endif +#if defined(GPDMA1) + } + else + { + status = !XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_GPDMA1); +#if defined(CLOCK_GATING_SUPPORTED) + status = status && !XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_GPDMA1); +#endif + } +#endif + + /* DMA reset is not asserted and peripheral clock is not gated */ + if (status == true) + { + status = status && (dma->DMACFGREG != 0U); + } + + return status; +} + +/* Enable request line */ +void XMC_DMA_EnableRequestLine(XMC_DMA_t *const dma, uint8_t line, uint8_t peripheral) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + DLR->SRSEL0 = ((DLR->SRSEL0 & (uint32_t)~(DLR_SRSEL_RS_MSK << (line * DLR_SRSEL_RS_BITSIZE))) | + ((uint32_t)peripheral << (line * DLR_SRSEL_RS_BITSIZE))); + DLR->LNEN |= (0x1UL << (line & GPDMA0_CH_CFGH_PER_Msk)); +#if defined(GPDMA1) + } + else + { + DLR->SRSEL1 = ((DLR->SRSEL1 & (uint32_t)~(DLR_SRSEL_RS_MSK << (line * DLR_SRSEL_RS_BITSIZE))) | + ((uint32_t)peripheral << (line * DLR_SRSEL_RS_BITSIZE))); + DLR->LNEN |= (0x100UL << line); + } +#endif +} + +void XMC_DMA_DisableRequestLine(XMC_DMA_t *const dma, uint8_t line) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + DLR->LNEN &= ~(0x1UL << line); +#if defined(GPDMA1) + } + else + { + DLR->LNEN &= ~(0x100UL << line); + } +#endif +} + +void XMC_DMA_ClearRequestLine(XMC_DMA_t *const dma, uint8_t line) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + DLR->LNEN &= ~(0x1UL << line); + DLR->LNEN |= 0x1UL << line; +#if defined(GPDMA1) + } + else + { + DLR->LNEN &= ~(0x100UL << line); + DLR->LNEN |= 0x100UL << line; + } +#endif +} + +/* Get DMA DLR overrun status */ +bool XMC_DMA_GetOverrunStatus(XMC_DMA_t *const dma, uint8_t line) +{ + bool status; + +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + status = (bool)(DLR->OVRSTAT & (0x1UL << line)); +#if defined(GPDMA1) + } + else + { + status = (bool)(DLR->OVRSTAT & (0x100UL << line)); + } +#endif + + return status; +} + +/* Clear DMA DLR overrun status */ +void XMC_DMA_ClearOverrunStatus(XMC_DMA_t *const dma, const uint8_t line) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + DLR->OVRCLR = (uint32_t)(0x1UL << line); +#if defined(GPDMA1) + } + else + { + DLR->OVRCLR = (uint32_t)(0x100UL << line); + } +#endif +} + +/* Disable DMA channel */ +void XMC_DMA_CH_Disable(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CHENREG = (uint32_t)(0x100UL << channel); + while((dma->CHENREG & (uint32_t)(0x1UL << channel)) != 0U) + { + /* wait until channel is disabled */ + } +} + +/* Check if a DMA channel is enabled */ +bool XMC_DMA_CH_IsEnabled(XMC_DMA_t *const dma, const uint8_t channel) +{ + return (bool)(dma->CHENREG & ((uint32_t)1U << channel)); +} + +/* Initialize DMA channel */ +XMC_DMA_CH_STATUS_t XMC_DMA_CH_Init(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_CONFIG_t *const config) +{ + XMC_DMA_CH_STATUS_t status; + uint8_t line; + uint8_t peripheral; + + if (XMC_DMA_IsEnabled(dma) == true) + { + if (XMC_DMA_CH_IsEnabled(dma, channel) == false) + { + dma->CH[channel].SAR = config->src_addr; + dma->CH[channel].DAR = config->dst_addr; + dma->CH[channel].LLP = (uint32_t)config->linked_list_pointer; + dma->CH[channel].CTLH = (uint32_t)config->block_size; + dma->CH[channel].CTLL = config->control; + + dma->CH[channel].CFGL = (uint32_t)((uint32_t)config->priority | + (uint32_t)GPDMA0_CH_CFGL_HS_SEL_SRC_Msk | + (uint32_t)GPDMA0_CH_CFGL_HS_SEL_DST_Msk); + + if ((dma == XMC_DMA0) && (channel < (uint8_t)2)) + { + /* Configure scatter and gather */ + dma->CH[channel].SGR = config->src_gather_control; + dma->CH[channel].DSR = config->dst_scatter_control; + } + + if (config->dst_handshaking == XMC_DMA_CH_DST_HANDSHAKING_HARDWARE) + { + /* Hardware handshaking interface configuration */ + if ((config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA) || + (config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA)) + { +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + line = config->dst_peripheral_request & GPDMA0_CH_CFGH_PER_Msk; +#if defined(GPDMA1) + } + else + { + line = config->dst_peripheral_request & GPDMA1_CH_CFGH_PER_Msk; + } +#endif + peripheral = config->dst_peripheral_request >> GPDMA_CH_CFGH_PER_BITSIZE; + + dma->CH[channel].CFGH |= (uint32_t)((uint32_t)line << GPDMA0_CH_CFGH_DEST_PER_Pos); + XMC_DMA_EnableRequestLine(dma, line, peripheral); + dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_HS_SEL_DST_Msk; + } + } + + + if (config->src_handshaking == XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE) + { + if ((config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA) || + (config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA)) + { +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + line = config->src_peripheral_request & GPDMA0_CH_CFGH_PER_Msk; +#if defined(GPDMA1) + } + else + { + line = config->src_peripheral_request & GPDMA1_CH_CFGH_PER_Msk; + } +#endif + peripheral = config->src_peripheral_request >> GPDMA_CH_CFGH_PER_BITSIZE; + + dma->CH[channel].CFGH |= (uint32_t)((uint32_t)line << GPDMA0_CH_CFGH_SRC_PER_Pos); + XMC_DMA_EnableRequestLine(dma, line, peripheral); + dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_HS_SEL_SRC_Msk; + } + } + + XMC_DMA_CH_ClearEventStatus(dma, channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_ERROR)); + + switch (config->transfer_type) + { + case XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK: + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_RELOAD: + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_CONTIGUOUS: + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD: + dma->CH[channel].CFGL |= (uint32_t)((uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk | + (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk); + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_LINKED: + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED: + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk; + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_CONTIGUOUS: + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_RELOAD: + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk; + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED: + dma->CH[channel].CTLL |= (uint32_t)((uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk | + (uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk); + break; + + default: + break; + } + + status = XMC_DMA_CH_STATUS_OK; + + } + else + { + status = XMC_DMA_CH_STATUS_BUSY; + } + } + else + { + status = XMC_DMA_CH_STATUS_ERROR; + } + + return status; +} + +/* Suspend DMA channel transfer */ +void XMC_DMA_CH_Suspend(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_CH_SUSP_Msk; +} + +/* Resume DMA channel transfer */ +void XMC_DMA_CH_Resume(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_CH_SUSP_Msk; +} + +/* Check if a DMA channel is suspended */ +bool XMC_DMA_CH_IsSuspended(XMC_DMA_t *const dma, const uint8_t channel) +{ + return (bool)(dma->CH[channel].CFGL & (uint32_t)GPDMA0_CH_CFGL_CH_SUSP_Msk); +} + +/* Enable GPDMA event */ +void XMC_DMA_CH_EnableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event) +{ + uint32_t event_idx; + + for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + { + if (event & ((uint32_t)0x1UL << event_idx)) + { + dma->MASKCHEV[event_idx * 2UL] = ((uint32_t)0x101UL << channel); + } + } +} + +/* Disable GPDMA event */ +void XMC_DMA_CH_DisableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event) +{ + uint32_t event_idx; + + for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + { + if (event & ((uint32_t)0x1UL << event_idx)) + { + dma->MASKCHEV[event_idx * 2UL] = ((uint32_t)0x100UL << channel); + } + } +} + +/* Clear GPDMA event */ +void XMC_DMA_CH_ClearEventStatus(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event) +{ + uint32_t event_idx; + + for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + { + if (event & (uint32_t)((uint32_t)0x1UL << event_idx)) + { + dma->CLEARCHEV[event_idx * 2UL] = ((uint32_t)0x1UL << channel); + } + } + +} + +/* Get GPDMA event status */ +uint32_t XMC_DMA_CH_GetEventStatus(XMC_DMA_t *const dma, const uint8_t channel) +{ + uint32_t event_idx; + uint32_t status = 0UL; + + for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + { + status |= (uint32_t)((dma->STATUSCHEV[event_idx * 2UL] & (uint32_t)((uint32_t)0x1UL << (uint32_t)channel)) ? + ((uint32_t)0x1UL << event_idx) : (uint32_t)0UL); + } + + return status; +} + +/* Enable source gather */ +void XMC_DMA_CH_EnableSourceGather(XMC_DMA_t *const dma, const uint8_t channel, uint32_t interval, uint16_t count) +{ + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk; + dma->CH[channel].SGR = ((uint32_t)interval << GPDMA0_CH_SGR_SGI_Pos) | ((uint32_t)count << GPDMA0_CH_SGR_SGC_Pos); +} + +/* Disable source gather */ +void XMC_DMA_CH_DisableSourceGather(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CTLL &= (uint32_t)~GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk; +} + +/* Enable destination scatter */ +void XMC_DMA_CH_EnableDestinationScatter(XMC_DMA_t *const dma, const uint8_t channel, uint32_t interval, uint16_t count) +{ + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk; + dma->CH[channel].DSR = ((uint32_t)interval << GPDMA0_CH_DSR_DSI_Pos) | ((uint32_t)count << GPDMA0_CH_DSR_DSC_Pos); +} + +/* Disable destination scatter */ +void XMC_DMA_CH_DisableDestinationScatter(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CTLL &= (uint32_t)~GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk; +} + +/* Trigger source request */ +void XMC_DMA_CH_TriggerSourceRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last) +{ + if ((uint32_t)type == (uint32_t)XMC_DMA_CH_TRANSACTION_TYPE_SINGLE) + { + dma->SGLREQSRCREG = ((uint32_t)0x101UL << channel); + } + + if (last == true) + { + dma->LSTSRCREG = (uint32_t)0x101UL << channel; + } + + dma->REQSRCREG = (uint32_t)0x101UL << channel; +} + +/* Trigger destination request */ +void XMC_DMA_CH_TriggerDestinationRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last) +{ + if(type == XMC_DMA_CH_TRANSACTION_TYPE_SINGLE) + { + dma->SGLREQDSTREG = (uint32_t)0x101UL << channel; + } + + if (last == true) + { + dma->LSTDSTREG = (uint32_t)0x101UL << channel; + } + + dma->REQDSTREG = (uint32_t)0x101UL << channel; +} + +/* Enable source address reload */ +void XMC_DMA_CH_EnableSourceAddressReload(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk; +} + +/* Disable source address reload */ +void XMC_DMA_CH_DisableSourceAddressReload(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_RELOAD_SRC_Msk; +} + +/* Enable destination address reload */ +void XMC_DMA_CH_EnableDestinationAddressReload(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk; +} + +/* Disable destination address reload */ +void XMC_DMA_CH_DisableDestinationAddressReload(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_RELOAD_DST_Msk; +} + +/* Request last multi-block transfer */ +void XMC_DMA_CH_RequestLastMultiblockTransfer(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL &= (uint32_t)~(GPDMA0_CH_CFGL_RELOAD_SRC_Msk | GPDMA0_CH_CFGL_RELOAD_DST_Msk); +} + +/* Set event handler */ +void XMC_DMA_CH_SetEventHandler(XMC_DMA_t *const dma, const uint8_t channel, XMC_DMA_CH_EVENT_HANDLER_t event_handler) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + dma0_event_handlers[channel] = event_handler; +#if defined(GPDMA1) + } + else + { + dma1_event_handlers[channel] = event_handler; + } +#endif +} + +void XMC_DMA_CH_ClearSourcePeripheralRequest(XMC_DMA_t *const dma, uint8_t channel) +{ + uint32_t line; + line = (dma->CH[channel].CFGH & GPDMA0_CH_CFGH_SRC_PER_Msk) >> GPDMA0_CH_CFGH_SRC_PER_Pos; + + XMC_DMA_ClearRequestLine(dma, (uint8_t)line); +} + +void XMC_DMA_CH_ClearDestinationPeripheralRequest(XMC_DMA_t *const dma, uint8_t channel) +{ + uint32_t line; + line = (dma->CH[channel].CFGH & GPDMA0_CH_CFGH_DEST_PER_Msk) >> GPDMA0_CH_CFGH_DEST_PER_Pos; + + XMC_DMA_ClearRequestLine(dma, (uint8_t)line); +} + +/* Default DMA IRQ handler */ +void XMC_DMA_IRQHandler(XMC_DMA_t *const dma) +{ + uint32_t event; + int32_t channel; + uint32_t mask; + XMC_DMA_CH_EVENT_HANDLER_t *dma_event_handlers; + XMC_DMA_CH_EVENT_HANDLER_t event_handler; + +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + dma_event_handlers = dma0_event_handlers; +#if defined(GPDMA1) + } + else + { + dma_event_handlers = dma1_event_handlers; + } +#endif + + event = XMC_DMA_GetEventStatus(dma); + channel = 0; + + if ((event & (uint32_t)XMC_DMA_CH_EVENT_ERROR) != (uint32_t)0UL) + { + event = XMC_DMA_GetChannelsErrorStatus(dma); + while (event != 0) + { + mask = (uint32_t)1U << channel; + if ((event & mask) != 0) + { + XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_ERROR); + + /* Call user callback to handle event */ + event_handler = dma_event_handlers[channel]; + if (event_handler != NULL) + { + event_handler(XMC_DMA_CH_EVENT_ERROR); + } + + break; + } + ++channel; + } + } + else if ((event & (uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE) != (uint32_t)0UL) + { + event = XMC_DMA_GetChannelsTransferCompleteStatus(dma); + while (event != 0) + { + mask = (uint32_t)1U << channel; + if (event & mask) + { + XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE)); + + /* Call user callback to handle event */ + event_handler = dma_event_handlers[channel]; + if (event_handler != NULL) + { + event_handler(XMC_DMA_CH_EVENT_TRANSFER_COMPLETE); + } + + break; + } + ++channel; + } + } + else if ((event & (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE) != (uint32_t)0UL) + { + event = XMC_DMA_GetChannelsBlockCompleteStatus(dma); + while (event != 0) + { + mask = (uint32_t)1U << channel; + if (event & mask) + { + XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE)); + + /* Call user callback to handle event */ + event_handler = dma_event_handlers[channel]; + if (event_handler != NULL) + { + event_handler(XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE); + } + + break; + } + ++channel; + } + } + else if ((event & (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE) != (uint32_t)0UL) + { + event = XMC_DMA_GetChannelsSourceTransactionCompleteStatus(dma); + while (event != 0) + { + mask = (uint32_t)1U << channel; + if (event & mask) + { + XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE); + + /* Call user callback to handle event */ + event_handler = dma_event_handlers[channel]; + if (event_handler != NULL) + { + event_handler(XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE); + } + + break; + } + ++channel; + } + } + else if ((event & (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE) != (uint32_t)0UL) + { + event = XMC_DMA_GetChannelsDestinationTransactionCompleteStatus(dma); + while (event != 0) + { + mask = (uint32_t)1U << channel; + if (event & mask) + { + XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE); + + /* Call user callback to handle event */ + event_handler = dma_event_handlers[channel]; + if (event_handler != NULL) + { + event_handler(XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE); + } + + break; + } + ++channel; + } + } + else + { + /* no active interrupt was found? */ + } + +} + +#endif /* GPDMA0 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_dsd.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_dsd.c new file mode 100644 index 00000000..2c45a23f --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_dsd.c @@ -0,0 +1,369 @@ +/** + * @file xmc_dsd.c + * @date 2015-09-18 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-03-30: + * - Initial version + * + * 2015-06-19: + * - Removed GetDriverVersion API
+ * + * 2015-09-18: + * - Support added for XMC4800 microcontroller family
+ * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_dsd.h" + +#if defined(DSD) + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#define XMC_DSD_MIN_FILTER_START (4U) +#define XMC_DSD_MIN_DECIMATION_FACTOR (4U) +#define XMC_DSD_MAX_DECIMATION_FACTOR (256U) +#define XMC_DSD_MAX_DECIMATION_FACTOR_AUX (32U) + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/*Enable the DSD Module*/ +void XMC_DSD_Enable(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_Enable:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_UNUSED_ARG(dsd); + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DSD); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DSD); +} + +/*Disable the DSD Module*/ +void XMC_DSD_Disable(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_Disable:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_UNUSED_ARG(dsd); + + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DSD); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DSD); +#endif +} + +/* Enable the module clock*/ +void XMC_DSD_EnableClock(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_EnableClock:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + /* Enable the module clock */ + dsd->CLC &= ~(uint32_t)DSD_CLC_DISR_Msk; + /* enable internal module clock */ + dsd ->GLOBCFG |= (uint32_t)0x01; +} + +void XMC_DSD_DisableClock(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_DisableClock:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + + /* disable internal module clock */ + dsd->GLOBCFG &= ~(uint32_t)DSD_GLOBCFG_MCSEL_Msk; + + /* stop the module clock */ + dsd->CLC |= (uint32_t)DSD_CLC_DISR_Msk; + +} + +/* Enable the DSD module and clock */ +void XMC_DSD_Init(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_Init:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_DSD_Enable(dsd); + XMC_DSD_EnableClock(dsd); +} + +bool XMC_DSD_IsEnabled(XMC_DSD_t *const dsd) +{ + bool status; + XMC_ASSERT("XMC_DSD_Disable:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_UNUSED_ARG(dsd); + + #if ((UC_SERIES == XMC44) || (UC_SERIES == XMC48)||(UC_SERIES == XMC47)) + if(XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DSD) == false) + { + if(XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_DSD) == false) + { + status = true; + } + else + { + status = false; + } + } + else + { + status = false; + } + #else + if(XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DSD) == false) + { + status = true; + } + else + { + status = false; + } + #endif + + return (status); +} + +/*Initializes the Waveform Generator*/ +void XMC_DSD_Generator_Init(XMC_DSD_t *const dsd, const XMC_DSD_GENERATOR_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_DSD_GENERATOR_Init:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_ASSERT("XMC_DSD_GENERATOR_Init:NULL Pointer", (config != (XMC_DSD_GENERATOR_CONFIG_t *)NULL) ); + /* Reset Generator */ + dsd ->CGCFG &= ~((uint32_t)DSD_CGCFG_CGMOD_Msk | (uint32_t)DSD_CGCFG_BREV_Msk | (uint32_t)DSD_CGCFG_SIGPOL_Msk | (uint32_t)DSD_CGCFG_DIVCG_Msk); + + /* Generator configuration */ + dsd ->CGCFG = config->generator_conf; +} + +/* Initialize main filter,auxiliary filter,integrator, rectifier and timestamp of DSD*/ +XMC_DSD_STATUS_t XMC_DSD_CH_Init( XMC_DSD_CH_t *const channel, const XMC_DSD_CH_CONFIG_t *const config) +{ + XMC_DSD_STATUS_t status; + + XMC_ASSERT("XMC_DSD_CH_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_CH_Init:NULL Pointer", (config != (XMC_DSD_CH_CONFIG_t *)NULL) ); + + if (config->filter != (XMC_DSD_CH_FILTER_CONFIG_t*)NULL) + { + XMC_DSD_CH_MainFilter_Init(channel, config->filter); + + if (config->aux != (XMC_DSD_CH_AUX_FILTER_CONFIG_t*)NULL) + { + XMC_DSD_CH_AuxFilter_Init(channel, config->aux); + } + if (config->integrator != (XMC_DSD_CH_INTEGRATOR_CONFIG_t*)NULL) + { + XMC_DSD_CH_Integrator_Init(channel, config->integrator); + } + if (config->rectify != (XMC_DSD_CH_RECTIFY_CONFIG_t*)NULL) + { + XMC_DSD_CH_Rectify_Init(channel, config->rectify); + } + if (config->timestamp != (XMC_DSD_CH_TIMESTAMP_CONFIG_t*)NULL) + { + XMC_DSD_CH_Timestamp_Init(channel, config->timestamp); + } + status = XMC_DSD_STATUS_OK; + } + else + { + status = XMC_DSD_STATUS_ERROR; + } + return (status); + +} + +/* Initialize main filter of DSD */ +void XMC_DSD_CH_MainFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_FILTER_CONFIG_t *const config) +{ + uint32_t decimation_factor_temp; + uint32_t filter_start_value_temp; + + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:NULL Pointer", (config != (XMC_DSD_CH_FILTER_CONFIG_t *)NULL) ); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Filter Start Value", (config->filter_start_value >= XMC_DSD_MIN_FILTER_START)); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Filter Start Value", (config->filter_start_value <= config->decimation_factor)); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Decimation Factor", + ((config->decimation_factor >= XMC_DSD_MIN_DECIMATION_FACTOR) && (config->decimation_factor <= XMC_DSD_MAX_DECIMATION_FACTOR))); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid divider",(((uint32_t)config->clock_divider <= XMC_DSD_CH_CLK_DIV_32))); + + /*Set Channel frequency*/ + channel->MODCFG = ((uint32_t)config->clock_divider << DSD_CH_MODCFG_DIVM_Pos) | (uint32_t)DSD_CH_MODCFG_DWC_Msk; + + /* Input Data/Clk */ + channel->DICFG = config->demodulator_conf | (uint32_t)DSD_CH_DICFG_DSWC_Msk | (uint32_t)DSD_CH_DICFG_SCWC_Msk; + + /*The decimation factor of the Main CIC filter is CFMDF + 1.*/ + decimation_factor_temp = config->decimation_factor-1U; + filter_start_value_temp = config->filter_start_value-1U; + + /* Filter setup*/ + channel->FCFGC = (decimation_factor_temp | + (filter_start_value_temp << (uint32_t)DSD_CH_FCFGC_CFMSV_Pos)| + config->main_filter_conf| + (uint32_t)DSD_CH_FCFGC_CFEN_Msk); + + /* Offset */ + channel->OFFM = (uint16_t)config->offset; +} + +/* Initialize timestamp mode of DSD */ +void XMC_DSD_CH_Timestamp_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_TIMESTAMP_CONFIG_t *const config) +{ + uint32_t temp; + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:NULL Pointer", (config != (XMC_DSD_CH_TIMESTAMP_CONFIG_t *)NULL) ); + + temp = (channel->DICFG | (uint32_t)DSD_CH_DICFG_TRWC_Msk); + temp &= ~((uint32_t)DSD_CH_DICFG_TSTRMODE_Msk|(uint32_t)DSD_CH_DICFG_TRSEL_Msk); + temp |= config->timestamp_conf; + channel->DICFG = temp; +} + +/* Initialize auxiliary filter of DSD */ +void XMC_DSD_CH_AuxFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_AUX_FILTER_CONFIG_t *const config) +{ + uint32_t decimation_factor_temp; + + XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:NULL Pointer", (config != (XMC_DSD_CH_AUX_FILTER_CONFIG_t *)NULL) ); + XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:Invalid Decimation Factor", + ((config->decimation_factor >= XMC_DSD_MIN_DECIMATION_FACTOR) && (config->decimation_factor <= XMC_DSD_MAX_DECIMATION_FACTOR_AUX))); + + channel->BOUNDSEL = config->boundary_conf; + /*The decimation factor of the Aux CIC filter is CFMDF + 1.*/ + decimation_factor_temp = config->decimation_factor-1U; + channel->FCFGA = (decimation_factor_temp | config->aux_filter_conf); +} + +/* Integrator initialization of DSD */ +void XMC_DSD_CH_Integrator_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_INTEGRATOR_CONFIG_t *const config) +{ + uint32_t temp; + XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:NULL Pointer", (config != (XMC_DSD_CH_INTEGRATOR_CONFIG_t *)NULL) ); + XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:Invalid integration_loop", (config->integration_loop > 0U )); + XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:Invalid counted_values", (config->counted_values > 0U )); + + channel->IWCTR = ((config->integration_loop - 1U) << DSD_CH_IWCTR_REPVAL_Pos) + | (config->discarded_values << DSD_CH_IWCTR_NVALDIS_Pos) + | (config->stop_condition << DSD_CH_IWCTR_IWS_Pos) + | ((config->counted_values - 1U) << DSD_CH_IWCTR_NVALINT_Pos); + + /*To ensure proper operation, ensure that bit field ITRMODE is zero before selecting any other trigger mode.*/ + temp = (channel->DICFG & ~((uint32_t)DSD_CH_DICFG_ITRMODE_Msk|(uint32_t)DSD_CH_DICFG_TRSEL_Msk)) | (uint32_t)DSD_CH_DICFG_TRWC_Msk; + + channel->DICFG = temp; + + temp |= config->integrator_trigger; + channel->DICFG = temp; +} + +/* Rectifier initialization of DSD */ +void XMC_DSD_CH_Rectify_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_RECTIFY_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_DSD_RECTIFY_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_RECTIFY_Init:NULL Pointer", (config != (XMC_DSD_CH_RECTIFY_CONFIG_t *)NULL)); + XMC_ASSERT("XMC_DSD_RECTIFY_Init:NULL Pointer", (((uint16_t)config->delay + (uint16_t)config->half_cycle) <= 0xFF)); + + channel->RECTCFG = config->rectify_config | (uint32_t)DSD_CH_RECTCFG_RFEN_Msk; + channel->CGSYNC = (((uint32_t) config->delay << (uint32_t)DSD_CH_CGSYNC_SDPOS_Pos) + | (((uint32_t)config->delay + (uint32_t)config->half_cycle) << (uint32_t)DSD_CH_CGSYNC_SDNEG_Pos)); +} + +/* API to get the result of the last conversion */ +void XMC_DSD_CH_GetResult_TS(XMC_DSD_CH_t* const channel, + int16_t* dsd_result, + uint8_t* dsd_filter_count, + uint8_t* dsd_integration_count) +{ + uint32_t timestamp; + uint16_t result; + + timestamp = channel->TSTMP; + result = (uint16_t)((uint32_t)timestamp & DSD_CH_TSTMP_RESULT_Msk); + *dsd_result = (int16_t)(result); + *dsd_filter_count = (uint8_t) ((timestamp & (uint32_t)DSD_CH_TSTMP_CFMDCNT_Msk)>>(uint32_t)DSD_CH_TSTMP_CFMDCNT_Pos); + *dsd_integration_count = (uint8_t) ((timestamp & (uint32_t)DSD_CH_TSTMP_NVALCNT_Msk)>>(uint32_t)DSD_CH_TSTMP_NVALCNT_Pos); +} + +/* API to get the result of the last conversion with the time */ +void XMC_DSD_CH_GetResult_TS_Time(XMC_DSD_CH_t* const channel, int16_t* dsd_Result, uint32_t* time) +{ + uint32_t timestamp; + uint16_t filter_count; + uint16_t integrator_count; + uint16_t decimation; + uint16_t result; + + timestamp = channel->TSTMP; + decimation = (uint16_t)(channel->FCFGC & DSD_CH_FCFGC_CFMDF_Msk); + filter_count = (uint16_t)((timestamp & DSD_CH_TSTMP_CFMDCNT_Msk)>>DSD_CH_TSTMP_CFMDCNT_Pos); + + /* Integration enabled? */ + if ((channel->IWCTR & DSD_CH_IWCTR_INTEN_Msk)) + { + integrator_count = (uint16_t) ((timestamp & DSD_CH_TSTMP_NVALCNT_Msk)>>DSD_CH_TSTMP_NVALCNT_Pos); + + /*See Errata number: xxyy */ + if (filter_count == decimation) + { + integrator_count++; + } + *time = (uint32_t)(((uint32_t) integrator_count * ((uint32_t) decimation + 1U)) + (uint32_t) ((uint32_t)decimation - filter_count)); + } + else + { + *time = (uint32_t) ((uint32_t)decimation - filter_count); + } + result = (uint16_t)((uint32_t)timestamp & DSD_CH_TSTMP_RESULT_Msk); + *dsd_Result = (int16_t)(result); +} + + + +#endif /*DSD*/ + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ebu.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ebu.c new file mode 100644 index 00000000..d04d7d81 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ebu.c @@ -0,0 +1,122 @@ +/** + * @file xmc_ebu.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed GetDriverVersion API + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ + +#include + +#if defined(EBU) + +/********************************************************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ + +/* + * Initialize the EBU peripheral + */ +XMC_EBU_STATUS_t XMC_EBU_Init(XMC_EBU_t *const ebu,const XMC_EBU_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + XMC_ASSERT("XMC_EBU_Init:Null Pointer", (config != (XMC_EBU_CONFIG_t *)NULL)); + + /* Enable EBU */ + XMC_EBU_Enable(ebu); + + /* Clock configuration */ + ebu->CLC = config->ebu_clk_config.raw0; + + /*EBU Mode Configuration */ + ebu->MODCON = config->ebu_mode_config.raw0; + + /* Address Bits available for GPIO function */ + ebu->USERCON = config->ebu_free_pins_to_gpio.raw0; + + return XMC_EBU_STATUS_OK; +} + +/* + * Configures the SDRAM with operating modes and refresh parameters + */ +void XMC_EBU_ConfigureSdram(XMC_EBU_t *const ebu,const XMC_EBU_SDRAM_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + XMC_ASSERT("XMC_EBU_Init:Null Pointer", (config != (XMC_EBU_SDRAM_CONFIG_t *)NULL)); + + /* EBU SDRAM Refresh Configuration Parameters */ + ebu->SDRMREF = config->raw2; + /* EBU SDRAM General Configuration Parameters */ + ebu->SDRMCON = config->raw0; + /* EBU SDRAM Operation Mode Configuration Parameters */ + ebu->SDRMOD = config->raw1; +} + +/* + * Configures the SDRAM region for read and write operation + */ +void XMC_EBU_ConfigureRegion(XMC_EBU_t *const ebu,const XMC_EBU_REGION_t *const region) +{ + + XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + XMC_ASSERT("XMC_EBU_Init:Null Pointer", (region != (XMC_EBU_REGION_t *)NULL)); + + /* Read configuration of the region*/ + ebu->BUS[region->read_config.ebu_region_no].RDCON = region->read_config.ebu_bus_read_config.raw0; + + /* Read parameters of the region*/ + ebu->BUS[region->read_config.ebu_region_no].RDAPR = region->read_config.ebu_bus_read_config.raw1; + + /* Write configuration of the region*/ + ebu->BUS[region->write_config.ebu_region_no].WRCON = region->write_config.ebu_bus_write_config.raw0; + + /* Write parameters of the region*/ + ebu->BUS[region->write_config.ebu_region_no].WRAPR = region->write_config.ebu_bus_write_config.raw1; +} + + +#endif /* defined(EBU) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ecat.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ecat.c new file mode 100644 index 00000000..91ac2773 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ecat.c @@ -0,0 +1,198 @@ + +/** + * @file xmc_ecat.c + * @date 2015-10-21 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-12-27: + * - Add clock gating control in enable/disable APIs + * + * 2015-10-21: + * - Initial Version + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include + +#if defined (ECAT0) + +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ +/* The function defines the access state to the MII management for the PDI interface*/ +__STATIC_INLINE void XMC_ECAT_lRequestPhyAccessToMII(void) +{ + ECAT0->MII_PDI_ACS_STATE |= 0x01; +} + +/* EtherCAT module clock ungating and deassert reset API (Enables ECAT) */ +void XMC_ECAT_Enable(void) +{ + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0); + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0); + + while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == true){} +} + +/* EtherCAT module clock gating and assert reset API (Disables ECAT)*/ +void XMC_ECAT_Disable(void) +{ + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0); + while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == false){} + + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0); +} + +/* EtherCAT initialization function */ +void XMC_ECAT_Init(XMC_ECAT_CONFIG_t *const config) +{ + XMC_ECAT_Enable(); + + /* The process memory is not accessible until the ESC Configuration Area is loaded successfully. */ + + /* words 0x0-0x3 */ + ECAT0->EEP_DATA[0U] = config->dword[0U]; + ECAT0->EEP_DATA[1U] = config->dword[1U]; + ECAT0->EEP_CONT_STAT |= (uint16_t)((uint16_t)0x4U << (uint16_t)ECAT_EEP_CONT_STAT_CMD_REG_Pos); + + /* words 0x4-0x7 */ + ECAT0->EEP_DATA[0U] = config->dword[2U]; + ECAT0->EEP_DATA[1U] = config->dword[3U]; + ECAT0->EEP_CONT_STAT |= (uint16_t)((uint16_t)0x4U << (uint16_t)ECAT_EEP_CONT_STAT_CMD_REG_Pos); + + while (ECAT0->EEP_CONT_STAT & ECAT_EEP_CONT_STAT_L_STAT_Msk) + { + /* Wait until the EEPROM_Loaded signal is active */ + } + +} + +/* EtherCAT application event enable API */ +void XMC_ECAT_EnableEvent(uint32_t event) +{ + ECAT0->AL_EVENT_MASK |= event; +} +/* EtherCAT application event disable API */ +void XMC_ECAT_DisableEvent(uint32_t event) +{ + ECAT0->AL_EVENT_MASK &= ~event; +} + +/* EtherCAT application event status reading API */ +uint32_t XMC_ECAT_GetEventStatus(void) +{ + return (ECAT0->AL_EVENT_REQ); +} + +/* EtherCAT SyncManager channel disable function*/ +void XMC_ECAT_DisableSyncManChannel(const uint8_t channel) +{ + ((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR |= 0x1U; +} + +/* EtherCAT SyncManager channel enable function*/ +void XMC_ECAT_EnableSyncManChannel(const uint8_t channel) +{ + ((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR &= (uint8_t)(~0x1U); +} + + +/* EtherCAT PHY register read function*/ +XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) +{ + XMC_ECAT_STATUS_t status; + + XMC_ECAT_lRequestPhyAccessToMII(); + + ECAT0->MII_PHY_ADR = phy_addr; + ECAT0->MII_PHY_REG_ADR = reg_addr; + + ECAT0->MII_CONT_STAT |= 0x0100U; /* read instruction */ + while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){} + + if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U) + { + ECAT0->MII_CONT_STAT &= ~ECAT_MII_CONT_STAT_CMD_REG_Msk; /* Clear error */ + status = XMC_ECAT_STATUS_ERROR; + } + else + { + *data = (uint16_t)ECAT0->MII_PHY_DATA; + status = XMC_ECAT_STATUS_OK; + } + + return status; +} + +/* EtherCAT PHY register write function*/ +XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t data) +{ + XMC_ECAT_STATUS_t status; + + XMC_ECAT_lRequestPhyAccessToMII(); + + ECAT0->MII_PHY_ADR = phy_addr; + ECAT0->MII_PHY_REG_ADR = reg_addr; + ECAT0->MII_PHY_DATA = data; + + ECAT0->MII_CONT_STAT |= 0x0200U; /* write instruction */ + while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){} + + if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U) + { + ECAT0->MII_CONT_STAT &= ~ECAT_MII_CONT_STAT_CMD_REG_Msk; /* Clear error */ + status = XMC_ECAT_STATUS_ERROR; + } + else + { + status = XMC_ECAT_STATUS_OK; + } + + return status; +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eru.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eru.c new file mode 100644 index 00000000..9141b9b2 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eru.c @@ -0,0 +1,295 @@ +/** + * @file xmc_eru.c + * @date 2016-03-10 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API
+ * + * 2016-03-10: + * - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation.
+ * + * @endcond + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_eru.h" + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#define ERU_EXISEL_BITSIZE (4UL) /* Used to set the input for path A and path B based on the channel */ +#define ERU_EXISEL_INPUT_BITSIZE (2UL) + +#define XMC_ERU_ETL_CHECK_INPUT_A(input) \ + ((input == XMC_ERU_ETL_INPUT_A0) || \ + (input == XMC_ERU_ETL_INPUT_A1) || \ + (input == XMC_ERU_ETL_INPUT_A2) || \ + (input == XMC_ERU_ETL_INPUT_A3)) + +#define XMC_ERU_ETL_CHECK_INPUT_B(input) \ + ((input == XMC_ERU_ETL_INPUT_B0) || \ + (input == XMC_ERU_ETL_INPUT_B1) || \ + (input == XMC_ERU_ETL_INPUT_B2) || \ + (input == XMC_ERU_ETL_INPUT_B3)) + +#define XMC_ERU_ETL_CHECK_STATUS_FLAG_MODE(mode) \ + ((mode == XMC_ERU_ETL_STATUS_FLAG_MODE_SWCTRL) || \ + (mode == XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL)) + +#define XMC_ERU_ETL_CHECK_EVENT_SOURCE(source) \ + ((source == XMC_ERU_ETL_SOURCE_A) || \ + (source == XMC_ERU_ETL_SOURCE_B) || \ + (source == XMC_ERU_ETL_SOURCE_A_OR_B) || \ + (source == XMC_ERU_ETL_SOURCE_A_AND_B) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_A) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_A_OR_B) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_A_AND_B) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_B) || \ + (source == XMC_ERU_ETL_SOURCE_A_OR_NOT_B) || \ + (source == XMC_ERU_ETL_SOURCE_A_AND_NOT_B) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_A_OR_NOT_B) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_A_AND_NOT_B)) + +#define XMC_ERU_ETL_CHECK_TRIGGER_EDGE(edge) \ + ((edge == XMC_ERU_ETL_EDGE_DETECTION_DISABLED) || \ + (edge == XMC_ERU_ETL_EDGE_DETECTION_RISING) || \ + (edge == XMC_ERU_ETL_EDGE_DETECTION_FALLING) || \ + (edge == XMC_ERU_ETL_EDGE_DETECTION_BOTH)) + +#define XMC_ERU_ETL_CHECK_TRIGGER_CHANNEL(channel) \ + ((channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0) || \ + (channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL1) || \ + (channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL2) || \ + (channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL3)) + +#define XMC_ERU_OGU_CHECK_PATTERN_INPUT(input) \ + ((input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT0) || \ + (input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT1) || \ + (input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT2) || \ + (input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT3)) + +#define XMC_ERU_OGU_CHECK_PERIPHERAL_TRIGGER(trigger) \ + ((trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER1) || \ + (trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER2) || \ + (trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER3)) + +#define XMC_ERU_OGU_CHECK_SERIVCE_REQUEST(service) \ + ((service == XMC_ERU_OGU_SERVICE_REQUEST_DISABLED) || \ + (service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER) || \ + (service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH) || \ + (service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH)) + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ +/* Initializes the selected ERU_ETLx channel with the config structure. */ +void XMC_ERU_ETL_Init(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_ERU_ETL_Init:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_Init:Invalid Channel Number", (channel < 4U)); + + XMC_ERU_Enable(eru); + + eru->EXISEL = (eru->EXISEL & + ~((uint32_t)(ERU_EXISEL_EXS0A_Msk | ERU_EXISEL_EXS0B_Msk) << (channel * ERU_EXISEL_BITSIZE))) | + (config->input << (channel * (uint32_t)ERU_EXISEL_BITSIZE)); + + eru->EXICON[channel] = config->raw; +} + +/* Initializes the selected ERU_OGUy channel with the config structure. */ +void XMC_ERU_OGU_Init(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_ERU_OGU_Init:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_Init:Invalid Channel Number", (channel < 4U)); + + XMC_ERU_Enable(eru); + + eru->EXOCON[channel] = config->raw; +} + +/* Configures the event source for path A and path B, with selected input_a and input_b respectively.*/ +void XMC_ERU_ETL_SetInput(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_INPUT_A_t input_a, + const XMC_ERU_ETL_INPUT_B_t input_b) +{ + XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid A", XMC_ERU_ETL_CHECK_INPUT_A(input_a)); + XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid B", XMC_ERU_ETL_CHECK_INPUT_B(input_b)); + + eru->EXISEL = (eru->EXISEL & ~((uint32_t)(ERU_EXISEL_EXS0A_Msk | ERU_EXISEL_EXS0B_Msk) << (channel * ERU_EXISEL_BITSIZE))) | + (((uint32_t)input_a | (uint32_t)(input_b << ERU_EXISEL_INPUT_BITSIZE)) << (channel * ERU_EXISEL_BITSIZE)); +} + +/* Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits of + EXICONx(x = [0 to 3]) register */ +void XMC_ERU_ETL_SetSource(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_SOURCE_t source) +{ + XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Source", XMC_ERU_ETL_CHECK_EVENT_SOURCE(source)); + + eru->EXICON_b[channel].SS = (uint8_t)source; +} + +/* Configure event trigger edge/s by setting (RE, FE) bits of EXICONx(x = [0 to 3]) register.*/ +void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_EDGE_DETECTION_t edge_detection) +{ + XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Trigger Edge", XMC_ERU_ETL_CHECK_TRIGGER_EDGE(edge_detection)); + + eru->EXICON_b[channel].ED = (uint8_t)edge_detection; +} + +/* Returns the configured event trigger edge/s by reading (RE, FE) bits of EXICONx(x = [0 to 3]) register. */ +XMC_ERU_ETL_EDGE_DETECTION_t XMC_ERU_ETL_GetEdgeDetection(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_ETL_GetEdgeDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_GetEdgeDetection:Invalid Channel Number", (channel < 4U)); + return ((XMC_ERU_ETL_EDGE_DETECTION_t)(eru->EXICON_b[channel].ED)); +} + +/* Set the status flag bit(FL) in EXICONx(x = [0 to 3]). */ +void XMC_ERU_ETL_SetStatusFlagMode(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_STATUS_FLAG_MODE_t mode) +{ + XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Status Flag Mode", XMC_ERU_ETL_CHECK_STATUS_FLAG_MODE(mode)); + + eru->EXICON_b[channel].LD = (uint8_t)mode; +} + +/* Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by + * ETLx(Event Trigger Logic, x = [0 to 3]) by setting (OCS and PE) bit fields. */ +void XMC_ERU_ETL_EnableOutputTrigger(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t trigger) +{ + XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Output Channel", XMC_ERU_ETL_CHECK_TRIGGER_CHANNEL(trigger)); + + eru->EXICON_b[channel].OCS = (uint8_t)trigger; + eru->EXICON_b[channel].PE = (uint8_t)true; +} + +/* Disables the trigger pulse generation by clearing the (PE) of the EXICONx(x = [0 to 3]). */ +void XMC_ERU_ETL_DisableOutputTrigger(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_ETL_DisableOutputTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_DisableOutputTrigger:Invalid Channel Number", (channel < 4U)); + + eru->EXICON_b[channel].PE = false; +} + +/* Configures ERU_ETLx(x = [0 to 3]) for pattern match detection by setting IPENx(x = [0 to 3) and GEEN bits. */ +void XMC_ERU_OGU_EnablePatternDetection(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t input) +{ + XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Pattern input", XMC_ERU_OGU_CHECK_PATTERN_INPUT(input)); + + eru->EXOCON_b[channel].IPEN = (uint8_t)input; + eru->EXOCON_b[channel].GEEN = true; +} + +/* Disable the pattern detection by clearing (GEEN) bit. */ +void XMC_ERU_OGU_DisablePatternDetection(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_OGU_DisablePatternDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_DisablePatternDetection:Invalid Channel Number", (channel < 4U)); + + eru->EXOCON_b[channel].GEEN = false; +} + +/* Configures peripheral trigger input, by setting (ISS) bit. */ +void XMC_ERU_OGU_EnablePeripheralTrigger(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger) +{ + XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Peripheral Trigger Input", + XMC_ERU_OGU_CHECK_PERIPHERAL_TRIGGER(peripheral_trigger)); + + eru->EXOCON_b[channel].ISS = (uint8_t)peripheral_trigger; +} + +/* Disables event generation based on peripheral trigger by clearing (ISS) bit. */ +void XMC_ERU_OGU_DisablePeripheralTrigger(XMC_ERU_t *const eru, + const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_OGU_DisablePeripheralTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_DisablePeripheralTrigger:Invalid Channel Number", (channel < 4U)); + + eru->EXOCON_b[channel].ISS = (uint8_t)0; +} + +/* Configures the gating scheme for service request generation by setting (GP) bit. */ +void XMC_ERU_OGU_SetServiceRequestMode(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_SERVICE_REQUEST_t mode) +{ + XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Service Request Mode", XMC_ERU_OGU_CHECK_SERIVCE_REQUEST(mode)); + + eru->EXOCON_b[channel].GP = (uint8_t)mode; + +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_mac.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_mac.c new file mode 100644 index 00000000..f673cd55 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_mac.c @@ -0,0 +1,929 @@ + +/** + * @file xmc_eth_mac.c + * @date 2017-04-17 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * + * 2015-09-01: + * - Add clock gating control in enable/disable APIs + * - Add transmit polling if run out of buffers + * + * 2015-11-30: + * - Fix XMC_ETH_MAC_GetRxFrameSize return value in case of errors + * + * 2016-03-16: + * - Fix XMC_ETH_MAC_DisableEvent + * + * 2016-05-19: + * - Changed XMC_ETH_MAC_ReturnTxDescriptor and XMC_ETH_MAC_ReturnRxDescriptor + * + * 2016-08-30: + * - Changed XMC_ETH_MAC_Init() to disable MMC interrupt events + * + * 2016-11-22: + * - Changed XMC_ETH_MAC_Init() to optimize access to bus + * + * 2017-02-25: + * - XMC_ETH_MAC_Enable() and XMC_ETH_MAC_Disable(), fixed compilation warnings + * + * 2017-03-27: + * - Changed XMC_ETH_MAC_Init() to disable PMT and timestamp interrupt events + * + * 2017-04-02: + * - Added XMC_ETH_MAC_InitPTPEx() + * - Added XMC_ETH_MAC_SetPTPTime() + * - Added XMC_ETH_MAC_UpdateAddend() + * - Fixed XMC_ETH_MAC_InitPTP(), XMC_ETH_MAC_UpdatePTPTime(), XMC_ETH_MAC_SetPTPAlarm() + * - nanoseconds initializazion + * - added polling to wait for setup + * + * 2017-04-04: + * - Changed XMC_ETH_MAC_Init() to disable MMC IPC receive interrupt events + * + * 2017-04-11: + * - Fixed XMC_ETH_MAC_SetPTPAlarm() nanoseconds conversion + * + * 2017-04-17: + * - Changed XMC_ETH_MAC_GetTxTimeStamp() and XMC_ETH_MAC_GetRxTimeStamp() return the timestamp depending on status bit in descriptor + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#include + +#if defined (ETH0) + +#include +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/** + * ETH MAC clock speed + */ +#define XMC_ETH_MAC_CLK_SPEED_35MHZ (35000000U) /**< ETH MAC clock speed 35 MHZ */ +#define XMC_ETH_MAC_CLK_SPEED_60MHZ (60000000U) /**< ETH MAC clock speed 60 MHZ */ +#define XMC_ETH_MAC_CLK_SPEED_100MHZ (100000000U) /**< ETH MAC clock speed 100 MHZ */ +#define XMC_ETH_MAC_CLK_SPEED_150MHZ (150000000U) /**< ETH MAC clock speed 150 MHZ */ +#define XMC_ETH_MAC_CLK_SPEED_200MHZ (200000000U) /**< ETH MAC clock speed 200 MHZ */ +#define XMC_ETH_MAC_CLK_SPEED_250MHZ (250000000U) /**< ETH MAC clock speed 250 MHZ */ + +/** + * ETH MAC MDC divider + */ +#define XMC_ETH_MAC_MDC_DIVIDER_16 (2U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/16 */ +#define XMC_ETH_MAC_MDC_DIVIDER_26 (3U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/26 */ +#define XMC_ETH_MAC_MDC_DIVIDER_42 (0U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/42 */ +#define XMC_ETH_MAC_MDC_DIVIDER_62 (1U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/62 */ +#define XMC_ETH_MAC_MDC_DIVIDER_102 (4U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/102 */ +#define XMC_ETH_MAC_MDC_DIVIDER_124 (5U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/124 */ + + +/** + * RDES1 Descriptor RX Packet Control + */ +#define ETH_MAC_DMA_RDES1_RBS2 (0x1FFF0000U) /**< Receive buffer 2 size */ +#define ETH_MAC_DMA_RDES1_RER (0x00008000U) /**< Receive end of ring */ +#define ETH_MAC_DMA_RDES1_RCH (0x00004000U) /**< Second address chained */ +#define ETH_MAC_DMA_RDES1_RBS1 (0x00001FFFU) /**< Receive buffer 1 size */ + +/** + * Interrupt masking + */ +#define ETH_MAC_DISABLE_MMC_INTERRUPT_MSK (0x03ffffffU) /**< Bit mask to disable MMMC transmit and receive interrupts */ +#define ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK (0x3fff3fffU) /**< Bit mask to disable MMC IPC Receive Checksum Offload Interrupt Mask */ + +/** + * Normal MAC events + */ +#define ETH_MAC_EVENT_NORMAL (XMC_ETH_MAC_EVENT_TRANSMIT |\ + XMC_ETH_MAC_EVENT_TRANSMIT_BUFFER_UNAVAILABLE |\ + XMC_ETH_MAC_EVENT_RECEIVE |\ + XMC_ETH_MAC_EVENT_EARLY_RECEIVE) + +/** + * Abnormal MAC events + */ +#define ETH_MAC_EVENT_ABNORMAL (XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED |\ + XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT |\ + XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW |\ + XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW |\ + XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE |\ + XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED |\ + XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT |\ + XMC_ETH_MAC_EVENT_EARLY_TRANSMIT |\ + XMC_ETH_MAC_EVENT_BUS_ERROR) + +/* Definition needed in case of device header file previous to v1.5.1*/ +#ifndef ETH_BUS_MODE_ATDS_Msk +#define ETH_BUS_MODE_ATDS_Msk (0x00000080UL) +#endif +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +/* Check if the event passed is a normal event */ +__STATIC_INLINE bool XCM_ETH_MAC_IsNormalEvent(uint32_t event) +{ + return (bool)((event & ((uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT | + (uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_BUFFER_UNAVAILABLE | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE | + (uint32_t)XMC_ETH_MAC_EVENT_EARLY_RECEIVE)) != (uint32_t)0); +} + +/* Check if the event passed is an abnormal event */ +__STATIC_INLINE bool XCM_ETH_MAC_IsAbnormalEvent(uint32_t event) +{ + return (bool)((event & ((uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED | + (uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW | + (uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT | + (uint32_t)XMC_ETH_MAC_EVENT_EARLY_TRANSMIT | + (uint32_t)XMC_ETH_MAC_EVENT_BUS_ERROR)) != (uint32_t)0); + } + +#ifdef XMC_ASSERT_ENABLE + +/* Check if the passed argument is a valid ETH module */ +__STATIC_INLINE bool XMC_ETH_MAC_IsValidModule(ETH_GLOBAL_TypeDef *const eth) +{ + return (eth == ETH0); +} + +#endif + +/* ETH MAC initialize */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_Init(XMC_ETH_MAC_t *const eth_mac) +{ + XMC_ETH_MAC_STATUS_t status; + + XMC_ASSERT("XMC_ETH_MAC_Init: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + XMC_ETH_MAC_Enable(eth_mac); + XMC_ETH_MAC_Reset(eth_mac); + + status = XMC_ETH_MAC_SetManagmentClockDivider(eth_mac); + + XMC_ETH_MAC_SetAddress(eth_mac, eth_mac->address); + + /* Initialize MAC configuration */ + eth_mac->regs->MAC_CONFIGURATION = (uint32_t)ETH_MAC_CONFIGURATION_IPC_Msk; + + /* Initialize Filter registers */ + eth_mac->regs->FLOW_CONTROL = ETH_FLOW_CONTROL_DZPQ_Msk; /* Disable Zero Quanta Pause */ + + eth_mac->regs->OPERATION_MODE = (uint32_t)ETH_OPERATION_MODE_RSF_Msk | + (uint32_t)ETH_OPERATION_MODE_TSF_Msk | + (uint32_t)ETH_OPERATION_MODE_OSF_Msk; + + /* Increase enhanced descriptor to 8 WORDS, required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled */ + eth_mac->regs->BUS_MODE = (uint32_t)ETH_BUS_MODE_ATDS_Msk | + (uint32_t)ETH_BUS_MODE_AAL_Msk | /* the AHB interface generates all bursts aligned to the start address LS bits */ + (uint32_t)ETH_BUS_MODE_FB_Msk | /* DMA attempts to execute fixed-length Burst transfers on the AHB Master interface */ + (uint32_t)(0x20 << ETH_BUS_MODE_PBL_Pos); /* maximum Burst length */ + + /* Initialize DMA Descriptors */ + XMC_ETH_MAC_InitRxDescriptors(eth_mac); + XMC_ETH_MAC_InitTxDescriptors(eth_mac); + + /* Clear interrupts */ + eth_mac->regs->STATUS = 0xFFFFFFFFUL; + + /* Disable MMC interrupt events */ + eth_mac->regs->MMC_TRANSMIT_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_INTERRUPT_MSK; + eth_mac->regs->MMC_RECEIVE_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_INTERRUPT_MSK; + eth_mac->regs->MMC_IPC_RECEIVE_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK; + + /* Disable PMT and timestamp interrupt events */ + eth_mac->regs->INTERRUPT_MASK = ETH_INTERRUPT_MASK_PMTIM_Msk | ETH_INTERRUPT_MASK_TSIM_Msk; + + eth_mac->frame_end = NULL; + + return status; +} + +/* Initialize RX descriptors */ +void XMC_ETH_MAC_InitRxDescriptors(XMC_ETH_MAC_t *const eth_mac) +{ + uint32_t i; + uint32_t next; + + XMC_ASSERT("XMC_ETH_MAC_InitRxDescriptors: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + /* + * Chained structure (ETH_MAC_DMA_RDES1_RCH), second address in the descriptor + * (buffer2) is the next descriptor address + */ + for (i = 0U; i < eth_mac->num_rx_buf; ++i) + { + eth_mac->rx_desc[i].status = (uint32_t)ETH_MAC_DMA_RDES0_OWN; + eth_mac->rx_desc[i].length = (uint32_t)ETH_MAC_DMA_RDES1_RCH | (uint32_t)XMC_ETH_MAC_BUF_SIZE; + eth_mac->rx_desc[i].buffer1 = (uint32_t)&(eth_mac->rx_buf[i * XMC_ETH_MAC_BUF_SIZE]); + next = i + 1U; + if (next == eth_mac->num_rx_buf) + { + next = 0U; + } + eth_mac->rx_desc[i].buffer2 = (uint32_t)&(eth_mac->rx_desc[next]); + } + eth_mac->regs->RECEIVE_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&(eth_mac->rx_desc[0]); + eth_mac->rx_index = 0U; +} + +/* Initialize TX descriptors */ +void XMC_ETH_MAC_InitTxDescriptors(XMC_ETH_MAC_t *const eth_mac) +{ + uint32_t i; + uint32_t next; + + XMC_ASSERT("XMC_ETH_MAC_InitTxDescriptors: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + /* Chained structure (ETH_MAC_DMA_TDES0_TCH), second address in the descriptor (buffer2) is the next descriptor address */ + for (i = 0U; i < eth_mac->num_tx_buf; ++i) + { + eth_mac->tx_desc[i].status = ETH_MAC_DMA_TDES0_TCH | ETH_MAC_DMA_TDES0_LS | ETH_MAC_DMA_TDES0_FS; + eth_mac->tx_desc[i].buffer1 = (uint32_t)&(eth_mac->tx_buf[i * XMC_ETH_MAC_BUF_SIZE]); + next = i + 1U; + if (next == eth_mac->num_tx_buf) + { + next = 0U; + } + eth_mac->tx_desc[i].buffer2 = (uint32_t)&(eth_mac->tx_desc[next]); + } + eth_mac->regs->TRANSMIT_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&(eth_mac->tx_desc[0]); + eth_mac->tx_index = 0U; +} + +/* Set address perfect filter */ +void XMC_ETH_MAC_SetAddressPerfectFilter(XMC_ETH_MAC_t *const eth_mac, + uint8_t index, + const uint64_t addr, + uint32_t flags) +{ + __IO uint32_t *reg; + + XMC_ASSERT("XMC_ETH_MAC_SetAddressPerfectFilter: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_SetAddressFilter: index is out of range", ((index > 0) && (index < 4))); + + reg = &(eth_mac->regs->MAC_ADDRESS0_HIGH); + reg[index] = (uint32_t)(addr >> 32U) | flags; + reg[index + 1U] = (uint32_t)addr; +} + +/* Set address hash filter */ +void XMC_ETH_MAC_SetAddressHashFilter(XMC_ETH_MAC_t *const eth_mac, const uint64_t hash) +{ + eth_mac->regs->HASH_TABLE_HIGH = (uint32_t)(hash >> 32); + eth_mac->regs->HASH_TABLE_LOW = (uint32_t)hash; +} + +/* Send frame */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SendFrame(XMC_ETH_MAC_t *const eth_mac, const uint8_t *frame, uint32_t len, uint32_t flags) +{ + XMC_ETH_MAC_STATUS_t status; + uint8_t *dst; + uint32_t ctrl; + + XMC_ASSERT("XMC_ETH_MAC_SendFrame:", eth_mac != NULL); + XMC_ASSERT("XMC_ETH_MAC_SendFrame:", eth_mac->regs == ETH0); + XMC_ASSERT("XMC_ETH_MAC_SendFrame:", (frame != NULL) && (len > 0)); + + dst = eth_mac->frame_end; + + if (eth_mac->tx_desc[eth_mac->tx_index].status & ETH_MAC_DMA_TDES0_OWN) + { + /* Transmitter is busy, wait */ + status = XMC_ETH_MAC_STATUS_BUSY; + if (eth_mac->regs->STATUS & ETH_STATUS_TU_Msk) + { + /* Receive buffer unavailable, resume DMA */ + eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_TU_Msk; + eth_mac->regs->TRANSMIT_POLL_DEMAND = 0U; + } + + } + else + { + if (dst == NULL) + { + /* Start of a new transmit frame */ + dst = (uint8_t *)eth_mac->tx_desc[eth_mac->tx_index].buffer1; + eth_mac->tx_desc[eth_mac->tx_index].length = len; + } + else + { + /* Sending data fragments in progress */ + eth_mac->tx_desc[eth_mac->tx_index].length += len; + } + + memcpy(dst, frame, len); + + if (flags & (uint32_t)XMC_ETH_MAC_TX_FRAME_FRAGMENT) + { + /* More data to come, remember current write position */ + eth_mac->frame_end = dst; + } + else + { + /* Frame is now ready, send it to DMA */ + ctrl = eth_mac->tx_desc[eth_mac->tx_index].status | ETH_MAC_DMA_TDES0_CIC; + ctrl &= ~(ETH_MAC_DMA_TDES0_IC | ETH_MAC_DMA_TDES0_TTSE); + + if (flags & (uint32_t)XMC_ETH_MAC_TX_FRAME_EVENT) + { + ctrl |= ETH_MAC_DMA_TDES0_IC; + } + + if (flags & (uint32_t)XMC_ETH_MAC_TX_FRAME_TIMESTAMP) + { + ctrl |= ETH_MAC_DMA_TDES0_TTSE; + } + eth_mac->tx_ts_index = eth_mac->tx_index; + + eth_mac->tx_desc[eth_mac->tx_index].status = ctrl | ETH_MAC_DMA_TDES0_OWN; + + eth_mac->tx_index++; + if (eth_mac->tx_index == eth_mac->num_tx_buf) + { + eth_mac->tx_index = 0U; + } + eth_mac->frame_end = NULL; + + /* Start frame transmission */ + eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_TPS_Msk; + eth_mac->regs->TRANSMIT_POLL_DEMAND = 0U; + } + status = XMC_ETH_MAC_STATUS_OK; + } + + return status; +} + +/* Read frame */ +uint32_t XMC_ETH_MAC_ReadFrame(XMC_ETH_MAC_t *const eth_mac, uint8_t *frame, uint32_t len) +{ + uint8_t const *src; + + XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", eth_mac != NULL); + XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", eth_mac->regs == ETH0); + XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", (frame != NULL) && (len > 0)); + + /* Fast-copy data to packet buffer */ + src = (uint8_t const *)eth_mac->rx_desc[eth_mac->rx_index].buffer1; + + memcpy(frame, src, len); + + /* Return this block back to DMA */ + eth_mac->rx_desc[eth_mac->rx_index].status = ETH_MAC_DMA_RDES0_OWN; + + eth_mac->rx_index++; + if (eth_mac->rx_index == eth_mac->num_rx_buf) + { + eth_mac->rx_index = 0U; + } + + if (eth_mac->regs->STATUS & ETH_STATUS_RU_Msk) + { + /* Receive buffer unavailable, resume DMA */ + eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_RU_Msk; + eth_mac->regs->RECEIVE_POLL_DEMAND = 0U; + } + + return (len); +} + +/* Get RX frame size */ +uint32_t XMC_ETH_MAC_GetRxFrameSize(XMC_ETH_MAC_t *const eth_mac) +{ + uint32_t status; + uint32_t len = 0U; + + status = eth_mac->rx_desc[eth_mac->rx_index].status; + + if (status & ETH_MAC_DMA_RDES0_OWN) + { + /* Owned by DMA */ + len = 0U; + } + else if (((status & ETH_MAC_DMA_RDES0_ES) != 0U) || + ((status & ETH_MAC_DMA_RDES0_FS) == 0U) || + ((status & ETH_MAC_DMA_RDES0_LS) == 0U)) + { + /* Error, this block is invalid */ + len = 0xFFFFFFFFU; + } + else + { + /* Subtract CRC */ + len = ((status & ETH_MAC_DMA_RDES0_FL) >> 16U) - 4U; + } + + return len; +} + +/* Set management clock divider */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SetManagmentClockDivider(XMC_ETH_MAC_t *const eth_mac) +{ + uint32_t eth_mac_clk; + XMC_ETH_MAC_STATUS_t status; + __IO uint32_t *reg; + + eth_mac_clk = XMC_SCU_CLOCK_GetEthernetClockFrequency(); + status = XMC_ETH_MAC_STATUS_OK; + + reg = &(eth_mac->regs->GMII_ADDRESS); + if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_35MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_16; + } + else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_60MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_26; + } + else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_100MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_42; + } + else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_150MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_62; + } + else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_200MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_102; + } + else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_250MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_124; + } + else + { + status = XMC_ETH_MAC_STATUS_ERROR; + } + + return status; +} + +/* ETH MAC enable */ +void XMC_ETH_MAC_Enable(XMC_ETH_MAC_t *const eth_mac) +{ + XMC_UNUSED_ARG(eth_mac); + + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_ETH); +#if UC_DEVICE != XMC4500 + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ETH0); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ETH0); +} + +/* ETH MAC disable */ +void XMC_ETH_MAC_Disable(XMC_ETH_MAC_t *const eth_mac) +{ + XMC_UNUSED_ARG(eth_mac); + + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ETH0); +#if UC_DEVICE != XMC4500 + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ETH0); +#endif + XMC_SCU_CLOCK_DisableClock(XMC_SCU_CLOCK_ETH); +} + +/* Read physical layer and obtain status */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_ReadPhy(XMC_ETH_MAC_t *eth_mac, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) +{ + uint32_t retries; + + XMC_ASSERT("XMC_ETH_MAC_PhyRead: Parameter error", data != NULL); + + eth_mac->regs->GMII_ADDRESS = (uint32_t)((eth_mac->regs->GMII_ADDRESS & (uint32_t)ETH_GMII_ADDRESS_CR_Msk) | + (uint32_t)ETH_GMII_ADDRESS_MB_Msk | + (uint32_t)((uint32_t)phy_addr << ETH_GMII_ADDRESS_PA_Pos) | + (uint32_t)((uint32_t)reg_addr << ETH_GMII_ADDRESS_MR_Pos)); + + /* Poll busy bit during max PHY_TIMEOUT time */ + retries = 0U; + do + { + if ((eth_mac->regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) == 0U) + { + *data = (uint16_t)(eth_mac->regs->GMII_DATA & ETH_GMII_DATA_MD_Msk); + return XMC_ETH_MAC_STATUS_OK; + } + ++retries; + } while (retries < XMC_ETH_MAC_PHY_MAX_RETRIES); + + return XMC_ETH_MAC_STATUS_ERROR; +} + +/* Write physical layer and return status */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_WritePhy(XMC_ETH_MAC_t *eth_mac, uint8_t phy_addr, uint8_t reg_addr, uint16_t data) +{ + uint32_t retries; + + eth_mac->regs->GMII_DATA = data; + eth_mac->regs->GMII_ADDRESS = (uint32_t)((eth_mac->regs->GMII_ADDRESS & (uint32_t)ETH_GMII_ADDRESS_CR_Msk) | + (uint32_t)ETH_GMII_ADDRESS_MB_Msk | + (uint32_t)ETH_GMII_ADDRESS_MW_Msk | + (uint32_t)((uint32_t)phy_addr << ETH_GMII_ADDRESS_PA_Pos) | + (uint32_t)((uint32_t)reg_addr << ETH_GMII_ADDRESS_MR_Pos)); + + /* Poll busy bit during max PHY_TIMEOUT time */ + retries = 0U; + do + { + if ((eth_mac->regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) == 0U) + { + return XMC_ETH_MAC_STATUS_OK; + } + ++retries; + } while (retries < XMC_ETH_MAC_PHY_MAX_RETRIES); + + return XMC_ETH_MAC_STATUS_ERROR; +} + +/* Flush TX */ +void XMC_ETH_MAC_FlushTx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->OPERATION_MODE &= (uint32_t)~ETH_OPERATION_MODE_ST_Msk; + XMC_ETH_MAC_InitTxDescriptors(eth_mac); + eth_mac->regs->OPERATION_MODE |= (uint32_t)ETH_OPERATION_MODE_ST_Msk; +} + +/* Flush RX */ +void XMC_ETH_MAC_FlushRx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->OPERATION_MODE &= (uint32_t)~ETH_OPERATION_MODE_SR_Msk; + XMC_ETH_MAC_InitRxDescriptors(eth_mac); + eth_mac->regs->OPERATION_MODE |= (uint32_t)ETH_OPERATION_MODE_SR_Msk; +} + +/* Set wakeup frame filter */ +void XMC_ETH_MAC_SetWakeUpFrameFilter(XMC_ETH_MAC_t *const eth_mac, + const uint32_t (*const filter)[XMC_ETH_WAKEUP_REGISTER_LENGTH]) +{ + uint32_t i = 0U; + + /* Fill Remote Wake-up frame filter register with buffer data */ + for (i = 0U; i < XMC_ETH_WAKEUP_REGISTER_LENGTH; i++) + { + /* Write each time to the same register */ + eth_mac->regs->REMOTE_WAKE_UP_FRAME_FILTER = (*filter)[i]; + } +} + +/* Enable event */ +void XMC_ETH_MAC_EnableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event) +{ + XMC_ASSERT("XMC_ETH_MAC_EnableDMAEvent: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + eth_mac->regs->INTERRUPT_MASK &= ~(event >> 16U); + + event &= (uint16_t)0x7fffU; + if (XCM_ETH_MAC_IsNormalEvent(event)) + { + event |= (uint32_t)ETH_INTERRUPT_ENABLE_NIE_Msk; + } + + if (XCM_ETH_MAC_IsAbnormalEvent(event)) + { + event |= (uint32_t)ETH_INTERRUPT_ENABLE_AIE_Msk; + } + + eth_mac->regs->INTERRUPT_ENABLE |= event; +} + +/* Disable event */ +void XMC_ETH_MAC_DisableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event) +{ + XMC_ASSERT("XMC_ETH_MAC_DisableDMAEvent: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + eth_mac->regs->INTERRUPT_MASK |= event >> 16U; + + event &= 0x7fffU; + eth_mac->regs->INTERRUPT_ENABLE &= ~event; +} + +/* Clear event status */ +void XMC_ETH_MAC_ClearEventStatus(XMC_ETH_MAC_t *const eth_mac, uint32_t event) +{ + XMC_ASSERT("XMC_ETH_MAC_ClearEventStatus: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + if ((eth_mac->regs->STATUS & ETH_STATUS_NIS_Msk) != 0U) + { + event |= (uint32_t)ETH_STATUS_NIS_Msk; + } + + if ((eth_mac->regs->STATUS & ETH_STATUS_AIS_Msk) != 0U) + { + event |= (uint32_t)ETH_STATUS_AIS_Msk; + } + + eth_mac->regs->STATUS = event & 0x0001FFFFU; +} + +/* Obtain event status */ +uint32_t XMC_ETH_MAC_GetEventStatus(const XMC_ETH_MAC_t *const eth_mac) +{ + uint32_t temp_status = 0; + XMC_ASSERT("XMC_ETH_MAC_GetEventStatus: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + temp_status = (eth_mac->regs->STATUS & (uint32_t)0x7ffUL); + + return ((uint32_t)((eth_mac->regs->INTERRUPT_STATUS & (ETH_INTERRUPT_MASK_PMTIM_Msk | ETH_INTERRUPT_MASK_TSIM_Msk)) << 16U) | + temp_status); +} + +/* Return RX descriptor */ +void XMC_ETH_MAC_ReturnRxDescriptor(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->rx_desc[eth_mac->rx_index].status |= ETH_MAC_DMA_RDES0_OWN; + eth_mac->rx_index++; + if (eth_mac->rx_index == eth_mac->num_rx_buf) + { + eth_mac->rx_index = 0U; + } +} + +/* Return TX descriptor */ +void XMC_ETH_MAC_ReturnTxDescriptor(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->tx_ts_index = eth_mac->tx_index; + + eth_mac->tx_desc[eth_mac->tx_index].status |= ETH_MAC_DMA_TDES0_CIC |ETH_MAC_DMA_TDES0_OWN; + eth_mac->tx_index++; + if (eth_mac->tx_index == eth_mac->num_tx_buf) + { + eth_mac->tx_index = 0U; + } + + eth_mac->frame_end = NULL; +} + +/* Set VLAN tag */ +void XMC_ETH_MAC_SetVLANTag(XMC_ETH_MAC_t *const eth_mac, uint16_t tag) +{ + XMC_ASSERT("XMC_ETH_MAC_SetVLANTag: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + eth_mac->regs->VLAN_TAG = (uint32_t)tag; +} + +/* Initialize PTP */ +void XMC_ETH_MAC_InitPTP(XMC_ETH_MAC_t *const eth_mac, uint32_t config) +{ + XMC_ASSERT("XMC_ETH_MAC_InitPTP: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + /* Mask the time stamp interrupt */ + eth_mac->regs->INTERRUPT_MASK |= (uint32_t)ETH_INTERRUPT_MASK_TSIM_Msk; + + /* Enable time stamp */ + eth_mac->regs->TIMESTAMP_CONTROL = ETH_TIMESTAMP_CONTROL_TSENA_Msk; + + /* Program sub-second increment register based on PTP clock frequency = fSYS/2 */ + /* the nanoseconds register has a resolution of ~0.465ns. */ + eth_mac->regs->SUB_SECOND_INCREMENT = (uint32_t)((0x80000000U / (float)(XMC_SCU_CLOCK_GetSystemClockFrequency() / 2)) + 0.5F); + + if ((config & (uint32_t)XMC_ETH_MAC_TIMESTAMP_CONFIG_FINE_UPDATE) != 0U) + { + /* Program addend register to obtain fSYS/2 from reference clock (fSYS) */ + eth_mac->regs->TIMESTAMP_ADDEND = (uint32_t)0x80000000U; + /* Addend register update */ + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk; + /* Poll the Timestamp Control register until the bit TSADDREG is cleared */ + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk); + } + + eth_mac->regs->TIMESTAMP_CONTROL |= config | (uint32_t)ETH_TIMESTAMP_CONTROL_TSINIT_Msk; + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk); +} + +/* Initialize PTP using a given time */ +void XMC_ETH_MAC_InitPTPEx(XMC_ETH_MAC_t *const eth_mac, uint32_t config, XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ASSERT("XMC_ETH_MAC_InitPTP: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + /* Mask the time stamp interrupt */ + eth_mac->regs->INTERRUPT_MASK |= (uint32_t)ETH_INTERRUPT_MASK_TSIM_Msk; + + /* Enable time stamp */ + eth_mac->regs->TIMESTAMP_CONTROL = ETH_TIMESTAMP_CONTROL_TSENA_Msk; + + /* Program sub-second increment register based on PTP clock frequency = fSYS/2 */ + /* the nanoseconds register has a resolution of ~0.465ns. */ + eth_mac->regs->SUB_SECOND_INCREMENT = (uint32_t)((0x80000000U / (float)(XMC_SCU_CLOCK_GetSystemClockFrequency() / 2)) + 0.5F); + + if ((config & (uint32_t)XMC_ETH_MAC_TIMESTAMP_CONFIG_FINE_UPDATE) != 0U) + { + /* Program addend register to obtain fSYS/2 from reference clock (fSYS) */ + eth_mac->regs->TIMESTAMP_ADDEND = (uint32_t)0x80000000U; + /* Addend register update */ + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk; + /* Poll the Timestamp Control register until the bit TSADDREG is cleared */ + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk); + } + + /* Initialize the system time */ + eth_mac->regs->SYSTEM_TIME_NANOSECONDS_UPDATE = time->nanoseconds; + eth_mac->regs->SYSTEM_TIME_SECONDS_UPDATE = time->seconds; + + eth_mac->regs->TIMESTAMP_CONTROL |= config | (uint32_t)ETH_TIMESTAMP_CONTROL_TSINIT_Msk; + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk); +} + +/* Get PTP time */ +void XMC_ETH_MAC_GetPTPTime(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ASSERT("XMC_ETH_MAC_GetPTPTime: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + time->nanoseconds = (uint32_t)(eth_mac->regs->SYSTEM_TIME_NANOSECONDS * (1000000000.0F / 0x80000000U)); /* accuracy of 0.46 ns */ + time->seconds = eth_mac->regs->SYSTEM_TIME_SECONDS; +} + +/* Set PTP time */ +void XMC_ETH_MAC_SetPTPTime(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ASSERT("XMC_ETH_MAC_GetPTPTime: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + eth_mac->regs->SYSTEM_TIME_SECONDS_UPDATE = time->seconds; + eth_mac->regs->SYSTEM_TIME_NANOSECONDS_UPDATE = time->nanoseconds; + + /* Initialize precision timer */ + ETH0->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSINIT_Msk; + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk); +} + +/* Update PTP time */ +void XMC_ETH_MAC_UpdatePTPTime(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_TIME_t *const time) +{ + uint32_t temp; + + XMC_ASSERT("XMC_ETH_MAC_UpdatePTPTime: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_UpdatePTPTime: time.time_stamp_nanoseconds not in range", (time->nanoseconds < 1000000000.0F)); + + temp = (uint32_t)(abs(time->nanoseconds) * (0x80000000U / 1000000000.0F)); + if (time->nanoseconds < 0) + { + temp |= (uint32_t)ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk; + } + + eth_mac->regs->SYSTEM_TIME_NANOSECONDS_UPDATE = temp; + eth_mac->regs->SYSTEM_TIME_SECONDS_UPDATE = time->seconds; + + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSUPDT_Msk; +} + +/* Set PTP alarm */ +void XMC_ETH_MAC_SetPTPAlarm(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ASSERT("XMC_ETH_MAC_SetPTPAlarm: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_SetPTPAlarm: time.time_stamp_nanoseconds not in range", (time->nanoseconds < 1000000000.0F)); + + eth_mac->regs->TARGET_TIME_NANOSECONDS = (uint32_t)(time->nanoseconds * (0x80000000U / 1000000000.0F)); + eth_mac->regs->TARGET_TIME_SECONDS = time->seconds; +} + +/* Adjust PTP clock */ +void XMC_ETH_MAC_AdjustPTPClock(XMC_ETH_MAC_t *const eth_mac, uint32_t correction) +{ + XMC_ASSERT("XMC_ETH_MAC_AdjustPTPClock: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + /* Correction factor is Q31 (0x80000000 = 1.000000000) */ + eth_mac->regs->TIMESTAMP_ADDEND = (uint32_t)(((uint64_t)correction * eth_mac->regs->TIMESTAMP_ADDEND) >> 31U); + + /* Update addend register */ + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk; + + /* Poll the Timestamp Control register until the bit TSADDREG is cleared */ + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk); +} + +/* Update Addend */ +void XMC_ETH_MAC_UpdateAddend(XMC_ETH_MAC_t *const eth_mac, uint32_t addend) +{ + XMC_ASSERT("XMC_ETH_MAC_AdjustPTPClock: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + eth_mac->regs->TIMESTAMP_ADDEND = addend; + + /* Update addend register */ + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk; + + /* Poll the Timestamp Control register until the bit TSADDREG is cleared */ + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk); +} + +/* Set PTP status */ +uint32_t XMC_ETH_MAC_GetPTPStatus(const XMC_ETH_MAC_t *const eth_mac) +{ + XMC_ASSERT("XMC_ETH_MAC_GetPTPStatus: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + return (eth_mac->regs->TIMESTAMP_STATUS); +} + +/* Get TX time-stamp */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_GetRxTimeStamp(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ETH_MAC_DMA_DESC_t *rx_desc; + XMC_ETH_MAC_STATUS_t status; + + XMC_ASSERT("XMC_ETH_MAC_GetRxTimeStamp: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_GetRxTimeStamp: time is invalid", time != NULL); + + rx_desc = ð_mac->rx_desc[eth_mac->rx_index]; + if (rx_desc->status & ETH_MAC_DMA_RDES0_OWN) + { + status = XMC_ETH_MAC_STATUS_BUSY; + } + else + { + if ((rx_desc->status & (ETH_MAC_DMA_RDES0_TSA | ETH_MAC_DMA_RDES0_LS)) == (ETH_MAC_DMA_RDES0_TSA | ETH_MAC_DMA_RDES0_LS)) + { + time->nanoseconds = (int32_t)rx_desc->time_stamp_nanoseconds; + time->seconds = rx_desc->time_stamp_seconds; + + status = XMC_ETH_MAC_STATUS_OK; + } + else + { + status = XMC_ETH_MAC_STATUS_ERROR; + } + } + + return status; +} + +/* Get TX time-stamp */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_GetTxTimeStamp(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ETH_MAC_DMA_DESC_t *tx_desc; + XMC_ETH_MAC_STATUS_t status; + + XMC_ASSERT("XMC_ETH_MAC_GetTxTimeStamp: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_GetTxTimeStamp: time is invalid", time != NULL); + + tx_desc = ð_mac->tx_desc[eth_mac->tx_ts_index]; + if (tx_desc->status & ETH_MAC_DMA_TDES0_OWN) + { + status = XMC_ETH_MAC_STATUS_BUSY; + } + else + { + if ((tx_desc->status & (ETH_MAC_DMA_TDES0_TTSS | ETH_MAC_DMA_TDES0_LS)) == (ETH_MAC_DMA_TDES0_TTSS | ETH_MAC_DMA_TDES0_LS)) + { + time->nanoseconds = (int32_t)tx_desc->time_stamp_nanoseconds; + time->seconds = tx_desc->time_stamp_seconds; + + status = XMC_ETH_MAC_STATUS_OK; + } + else + { + status = XMC_ETH_MAC_STATUS_ERROR; + } + } + + return status; +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_phy_dp83848.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_phy_dp83848.c new file mode 100644 index 00000000..12be26c1 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_phy_dp83848.c @@ -0,0 +1,299 @@ +/** + * @file xmc_eth_phy_dp83848.c + * @date 2015-12-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial
+ * + * 2015-12-15: + * - Added Reset and exit power down + * - Reset function called in Init function + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#if defined(XMC_ETH_PHY_DP83848C) +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/* Basic Registers */ +#define REG_BMCR (0x00U) /* Basic Mode Control Register */ +#define REG_BMSR (0x01U) /* Basic Mode Status Register */ +#define REG_PHYIDR1 (0x02U) /* PHY Identifier 1 */ +#define REG_PHYIDR2 (0x03U) /* PHY Identifier 2 */ +#define REG_ANAR (0x04U) /* Auto-Negotiation Advertisement */ +#define REG_ANLPAR (0x05U) /* Auto-Neg. Link Partner Abitily */ +#define REG_ANER (0x06U) /* Auto-Neg. Expansion Register */ +#define REG_ANNPTR (0x07U) /* Auto-Neg. Next Page TX */ +#define REG_RBR (0x17U) /* RMII and Bypass Register */ + +/* Extended Registers */ +#define REG_PHYSTS (0x10U) /* Status Register */ + +/* Basic Mode Control Register */ +#define BMCR_RESET (0x8000U) /* Software Reset */ +#define BMCR_LOOPBACK (0x4000U) /* Loopback mode */ +#define BMCR_SPEED_SEL (0x2000U) /* Speed Select (1=100Mb/s) */ +#define BMCR_ANEG_EN (0x1000U) /* Auto Negotiation Enable */ +#define BMCR_POWER_DOWN (0x0800U) /* Power Down */ +#define BMCR_ISOLATE (0x0400U) /* Isolate Media interface */ +#define BMCR_REST_ANEG (0x0200U) /* Restart Auto Negotiation */ +#define BMCR_DUPLEX (0x0100U) /* Duplex Mode (1=Full duplex) */ +#define BMCR_COL_TEST (0x0080U) /* Collision Test */ + +/* Basic Mode Status Register */ +#define BMSR_100B_T4 (0x8000U) /* 100BASE-T4 Capable */ +#define BMSR_100B_TX_FD (0x4000U) /* 100BASE-TX Full Duplex Capable */ +#define BMSR_100B_TX_HD (0x2000U) /* 100BASE-TX Half Duplex Capable */ +#define BMSR_10B_T_FD (0x1000U) /* 10BASE-T Full Duplex Capable */ +#define BMSR_10B_T_HD (0x0800U) /* 10BASE-T Half Duplex Capable */ +#define BMSR_MF_PRE_SUP (0x0040U) /* Preamble suppression Capable */ +#define BMSR_ANEG_COMPL (0x0020U) /* Auto Negotiation Complete */ +#define BMSR_REM_FAULT (0x0010U) /* Remote Fault */ +#define BMSR_ANEG_ABIL (0x0008U) /* Auto Negotiation Ability */ +#define BMSR_LINK_STAT (0x0004U) /* Link Status (1=established) */ +#define BMSR_JABBER_DET (0x0002U) /* Jaber Detect */ +#define BMSR_EXT_CAPAB (0x0001U) /* Extended Capability */ + +/* RMII and Bypass Register */ +#define RBR_RMII_MODE (0x0020U) /* Reduced MII Mode */ + +/* PHY Identifier Registers */ +#define PHY_ID1 0x2000 /* DP83848C Device Identifier MSB */ +#define PHY_ID2 0x5C90 /* DP83848C Device Identifier LSB */ + +/* PHY Status Register */ +#define PHYSTS_MDI_X 0x4000 /* MDI-X mode enabled by Auto-Negot. */ +#define PHYSTS_REC_ERR 0x2000 /* Receive Error Latch */ +#define PHYSTS_POL_STAT 0x1000 /* Polarity Status */ +#define PHYSTS_FC_SENSE 0x0800 /* False Carrier Sense Latch */ +#define PHYSTS_SIG_DET 0x0400 /* 100Base-TX Signal Detect */ +#define PHYSTS_DES_LOCK 0x0200 /* 100Base-TX Descrambler Lock */ +#define PHYSTS_PAGE_REC 0x0100 /* Link Code Word Page Received */ +#define PHYSTS_MII_INT 0x0080 /* MII Interrupt Pending */ +#define PHYSTS_REM_FAULT 0x0040 /* Remote Fault */ +#define PHYSTS_JABBER_DET 0x0020 /* Jabber Detect */ +#define PHYSTS_ANEG_COMPL 0x0010 /* Auto Negotiation Complete */ +#define PHYSTS_LOOPBACK 0x0008 /* Loopback Status */ +#define PHYSTS_DUPLEX 0x0004 /* Duplex Status (1=Full duplex) */ +#define PHYSTS_SPEED 0x0002 /* Speed10 Status (1=10MBit/s) */ +#define PHYSTS_LINK_STAT 0x0001 /* Link Status (1=established) */ + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + + /* Check if the device identifier is valid */ +static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t phy_id1; + uint16_t phy_id2; + XMC_ETH_PHY_STATUS_t status; + + /* Check Device Identification. */ + if ((XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR1, &phy_id1) == XMC_ETH_MAC_STATUS_OK) && + (XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR2, &phy_id2) == XMC_ETH_MAC_STATUS_OK)) + { + if ((phy_id1 == PHY_ID1) && ((phy_id2 & (uint16_t)0xfff0) == PHY_ID2)) + { + status = XMC_ETH_PHY_STATUS_OK; + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID; + } + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_TIMEOUT; + } + + return (int32_t)status; +} + +/* PHY initialize */ +int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config) +{ + int32_t status; + uint16_t reg_val; + + status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + status = XMC_ETH_PHY_Reset(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_val = 0U; + if (config->speed == XMC_ETH_LINK_SPEED_100M) + { + reg_val |= BMCR_SPEED_SEL; + } + + if (config->duplex == XMC_ETH_LINK_DUPLEX_FULL) + { + reg_val |= BMCR_DUPLEX; + } + + if (config->enable_auto_negotiate == true) + { + reg_val |= BMCR_ANEG_EN; + } + + if (config->enable_loop_back == true) + { + reg_val |= BMCR_LOOPBACK; + } + + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_val); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + /* Configure interface mode */ + switch (config->interface) + { + case XMC_ETH_LINK_INTERFACE_MII: + reg_val = 0x0001; + break; + case XMC_ETH_LINK_INTERFACE_RMII: + reg_val = RBR_RMII_MODE | 0x0001; + break; + } + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_RBR, reg_val); + } + } + } + + return status; +} + +/* Reset */ +int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + /* Reset PHY*/ + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + /* Wait for the reset to complete */ + do + { + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + } while ((reg_bmcr & BMCR_RESET) != 0); + } + + return status; +} + +/* Initiate power down */ +int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr |= BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Exit power down */ +int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr &= ~BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Get link status */ +XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + + return (XMC_ETH_LINK_STATUS_t)((val & BMSR_LINK_STAT) ? XMC_ETH_LINK_STATUS_UP : XMC_ETH_LINK_STATUS_DOWN); +} + +/* Get link speed */ +XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYSTS, &val); + + return (XMC_ETH_LINK_SPEED_t)((val & PHYSTS_SPEED) ? XMC_ETH_LINK_SPEED_10M : XMC_ETH_LINK_SPEED_100M); +} + +/* Get link duplex settings */ +XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYSTS, &val); + + return (XMC_ETH_LINK_DUPLEX_t)((val & PHYSTS_DUPLEX) ? XMC_ETH_LINK_DUPLEX_FULL : XMC_ETH_LINK_DUPLEX_HALF); +} + +bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + return ((val & BMSR_ANEG_COMPL) == BMSR_ANEG_COMPL); +} + +#endif // defined(XMC_ETH_PHY_DP83848C) diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_phy_ksz8031rnl.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_phy_ksz8031rnl.c new file mode 100644 index 00000000..e0c912d3 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_phy_ksz8031rnl.c @@ -0,0 +1,267 @@ +/** + * @file xmc_eth_phy_ksz8031ml.c + * @date 2015-12-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * + * 2015-12-15: + * - Added Reset and exit power down + * - Reset function called in Init function + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#if defined(XMC_ETH_PHY_KSZ8031RNL) +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/* Basic Registers */ +#define REG_BMCR (0x00U) /* Basic Mode Control Register */ +#define REG_BMSR (0x01U) /* Basic Mode Status Register */ +#define REG_PHYIDR1 (0x02U) /* PHY Identifier 1 */ +#define REG_PHYIDR2 (0x03U) /* PHY Identifier 2 */ +#define REG_ANAR (0x04U) /* Auto-Negotiation Advertisement */ +#define REG_ANLPAR (0x05U) /* Auto-Neg. Link Partner Abitily */ +#define REG_ANER (0x06U) /* Auto-Neg. Expansion Register */ +#define REG_ANNPTR (0x07U) /* Auto-Neg. Next Page TX */ + +/* Extended Registers */ +#define REG_PHYCTRL1 (0x1eU) /* PHY control 1 Register */ + +/* Basic Mode Control Register */ +#define BMCR_RESET (0x8000U) /* Software Reset */ +#define BMCR_LOOPBACK (0x4000U) /* Loopback mode */ +#define BMCR_SPEED_SEL (0x2000U) /* Speed Select (1=100Mb/s) */ +#define BMCR_ANEG_EN (0x1000U) /* Auto Negotiation Enable */ +#define BMCR_POWER_DOWN (0x0800U) /* Power Down */ +#define BMCR_ISOLATE (0x0400U) /* Isolate Media interface */ +#define BMCR_REST_ANEG (0x0200U) /* Restart Auto Negotiation */ +#define BMCR_DUPLEX (0x0100U) /* Duplex Mode (1=Full duplex) */ +#define BMCR_COL_TEST (0x0080U) /* Collision Test */ + +/* Basic Mode Status Register */ +#define BMSR_100B_T4 (0x8000U) /* 100BASE-T4 Capable */ +#define BMSR_100B_TX_FD (0x4000U) /* 100BASE-TX Full Duplex Capable */ +#define BMSR_100B_TX_HD (0x2000U) /* 100BASE-TX Half Duplex Capable */ +#define BMSR_10B_T_FD (0x1000U) /* 10BASE-T Full Duplex Capable */ +#define BMSR_10B_T_HD (0x0800U) /* 10BASE-T Half Duplex Capable */ +#define BMSR_MF_PRE_SUP (0x0040U) /* Preamble suppression Capable */ +#define BMSR_ANEG_COMPL (0x0020U) /* Auto Negotiation Complete */ +#define BMSR_REM_FAULT (0x0010U) /* Remote Fault */ +#define BMSR_ANEG_ABIL (0x0008U) /* Auto Negotiation Ability */ +#define BMSR_LINK_STAT (0x0004U) /* Link Status (1=established) */ +#define BMSR_JABBER_DET (0x0002U) /* Jaber Detect */ +#define BMSR_EXT_CAPAB (0x0001U) /* Extended Capability */ + +/* PHY control 1 Register */ +#define PHYCTRL1_OPMODE_SPEED (0x0003U) +#define PHYCTRL1_OPMODE_DUPLEX (0x0004U) + +/* PHY Identifier Registers */ +#define PHY_ID1 (0x0022U) /* KSZ8031 Device Identifier MSB */ +#define PHY_ID2 (0x1550U) /* KSZ8031 Device Identifier LSB */ + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + + /* Check if the device identifier is valid */ +static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t phy_id1; + uint16_t phy_id2; + XMC_ETH_PHY_STATUS_t status; + + /* Check Device Identification. */ + if ((XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR1, &phy_id1) == XMC_ETH_MAC_STATUS_OK) && + (XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR2, &phy_id2) == XMC_ETH_MAC_STATUS_OK)) + { + if ((phy_id1 == PHY_ID1) && ((phy_id2 & (uint16_t)0xfff0) == PHY_ID2)) + { + status = XMC_ETH_PHY_STATUS_OK; + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID; + } + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_TIMEOUT; + } + + return (int32_t)status; +} + +/* PHY initialize */ +int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + status = XMC_ETH_PHY_Reset(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr = 0U; + if (config->speed == XMC_ETH_LINK_SPEED_100M) + { + reg_bmcr |= BMCR_SPEED_SEL; + } + + if (config->duplex == XMC_ETH_LINK_DUPLEX_FULL) + { + reg_bmcr |= BMCR_DUPLEX; + } + + if (config->enable_auto_negotiate == true) + { + reg_bmcr |= BMCR_ANEG_EN; + } + + if (config->enable_loop_back == true) + { + reg_bmcr |= BMCR_LOOPBACK; + } + + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + } + + return status; +} + +/* Reset */ +int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + /* Reset PHY*/ + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + /* Wait for the reset to complete */ + do + { + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + } while ((reg_bmcr & BMCR_RESET) != 0); + } + + return status; +} + +/* Initiate power down */ +int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr |= BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Exit power down */ +int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr &= ~BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Get link status */ +XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + + return (XMC_ETH_LINK_STATUS_t)((val & BMSR_LINK_STAT) ? XMC_ETH_LINK_STATUS_UP : XMC_ETH_LINK_STATUS_DOWN); +} + +/* Get link speed */ +XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val); + + return (XMC_ETH_LINK_SPEED_t)(((val & PHYCTRL1_OPMODE_SPEED) - 1U) ? XMC_ETH_LINK_SPEED_100M : XMC_ETH_LINK_SPEED_10M); +} + +/* Get link duplex settings */ +XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val); + + return (XMC_ETH_LINK_DUPLEX_t)((val & PHYCTRL1_OPMODE_DUPLEX) ? XMC_ETH_LINK_DUPLEX_FULL : XMC_ETH_LINK_DUPLEX_HALF); +} + +bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + return ((val & BMSR_ANEG_COMPL) == BMSR_ANEG_COMPL); +} + +#endif // defined(XMC_ETH_PHY_KSZ8031RNL) diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_phy_ksz8081rnb.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_phy_ksz8081rnb.c new file mode 100644 index 00000000..05c3077c --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_eth_phy_ksz8081rnb.c @@ -0,0 +1,266 @@ +/** + * @file xmc_eth_phy_ksz8081rnb.c + * @date 2015-12-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * + * 2015-12-15: + * - Added Reset and exit power down + * - Reset function called in Init function + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#if defined(XMC_ETH_PHY_KSZ8081RNB) +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/* Basic Registers */ +#define REG_BMCR (0x00U) /* Basic Mode Control Register */ +#define REG_BMSR (0x01U) /* Basic Mode Status Register */ +#define REG_PHYIDR1 (0x02U) /* PHY Identifier 1 */ +#define REG_PHYIDR2 (0x03U) /* PHY Identifier 2 */ +#define REG_ANAR (0x04U) /* Auto-Negotiation Advertisement */ +#define REG_ANLPAR (0x05U) /* Auto-Neg. Link Partner Abitily */ +#define REG_ANER (0x06U) /* Auto-Neg. Expansion Register */ +#define REG_ANNPTR (0x07U) /* Auto-Neg. Next Page TX */ + +/* Extended Registers */ +#define REG_PHYCTRL1 (0x1eU) /* PHY control 1 Register */ + +/* Basic Mode Control Register */ +#define BMCR_RESET (0x8000U) /* Software Reset */ +#define BMCR_LOOPBACK (0x4000U) /* Loopback mode */ +#define BMCR_SPEED_SEL (0x2000U) /* Speed Select (1=100Mb/s) */ +#define BMCR_ANEG_EN (0x1000U) /* Auto Negotiation Enable */ +#define BMCR_POWER_DOWN (0x0800U) /* Power Down */ +#define BMCR_ISOLATE (0x0400U) /* Isolate Media interface */ +#define BMCR_REST_ANEG (0x0200U) /* Restart Auto Negotiation */ +#define BMCR_DUPLEX (0x0100U) /* Duplex Mode (1=Full duplex) */ +#define BMCR_COL_TEST (0x0080U) /* Collision Test */ + +/* Basic Mode Status Register */ +#define BMSR_100B_T4 (0x8000U) /* 100BASE-T4 Capable */ +#define BMSR_100B_TX_FD (0x4000U) /* 100BASE-TX Full Duplex Capable */ +#define BMSR_100B_TX_HD (0x2000U) /* 100BASE-TX Half Duplex Capable */ +#define BMSR_10B_T_FD (0x1000U) /* 10BASE-T Full Duplex Capable */ +#define BMSR_10B_T_HD (0x0800U) /* 10BASE-T Half Duplex Capable */ +#define BMSR_MF_PRE_SUP (0x0040U) /* Preamble suppression Capable */ +#define BMSR_ANEG_COMPL (0x0020U) /* Auto Negotiation Complete */ +#define BMSR_REM_FAULT (0x0010U) /* Remote Fault */ +#define BMSR_ANEG_ABIL (0x0008U) /* Auto Negotiation Ability */ +#define BMSR_LINK_STAT (0x0004U) /* Link Status (1=established) */ +#define BMSR_JABBER_DET (0x0002U) /* Jaber Detect */ +#define BMSR_EXT_CAPAB (0x0001U) /* Extended Capability */ + +/* PHY control 1 Register */ +#define PHYCTRL1_OPMODE_SPEED (0x0003U) +#define PHYCTRL1_OPMODE_DUPLEX (0x0004U) + +/* PHY Identifier Registers */ +#define PHY_ID1 (0x0022U) /* KSZ8031 Device Identifier MSB */ +#define PHY_ID2 (0x1560U) /* KSZ8031 Device Identifier LSB */ + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + + /* Check if the device identifier is valid */ +static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t phy_id1; + uint16_t phy_id2; + XMC_ETH_PHY_STATUS_t status; + + /* Check Device Identification. */ + if ((XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR1, &phy_id1) == XMC_ETH_MAC_STATUS_OK) && + (XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR2, &phy_id2) == XMC_ETH_MAC_STATUS_OK)) + { + if ((phy_id1 == PHY_ID1) && ((phy_id2 & (uint16_t)0xfff0) == PHY_ID2)) + { + status = XMC_ETH_PHY_STATUS_OK; + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID; + } + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_TIMEOUT; + } + + return (int32_t)status; +} + +/* PHY initialize */ +int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + status = XMC_ETH_PHY_Reset(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr = 0U; + if (config->speed == XMC_ETH_LINK_SPEED_100M) + { + reg_bmcr |= BMCR_SPEED_SEL; + } + + if (config->duplex == XMC_ETH_LINK_DUPLEX_FULL) + { + reg_bmcr |= BMCR_DUPLEX; + } + + if (config->enable_auto_negotiate == true) + { + reg_bmcr |= BMCR_ANEG_EN; + } + + if (config->enable_loop_back == true) + { + reg_bmcr |= BMCR_LOOPBACK; + } + + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + } + + return status; +} + +/* Reset */ +int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + /* Reset PHY*/ + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + /* Wait for the reset to complete */ + do + { + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + } while ((reg_bmcr & BMCR_RESET) != 0); + } + + return status; +} + +/* Initiate power down */ +int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr |= BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Exit power down */ +int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr &= ~BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Get link status */ +XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + + return (XMC_ETH_LINK_STATUS_t)((val & BMSR_LINK_STAT) ? XMC_ETH_LINK_STATUS_UP : XMC_ETH_LINK_STATUS_DOWN); +} + +/* Get link speed */ +XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val); + + return (XMC_ETH_LINK_SPEED_t)(((val & PHYCTRL1_OPMODE_SPEED) - 1U) ? XMC_ETH_LINK_SPEED_100M : XMC_ETH_LINK_SPEED_10M); +} + +/* Get link duplex settings */ +XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val); + + return (XMC_ETH_LINK_DUPLEX_t)((val & PHYCTRL1_OPMODE_DUPLEX) ? XMC_ETH_LINK_DUPLEX_FULL : XMC_ETH_LINK_DUPLEX_HALF); +} + +bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + return ((val & BMSR_ANEG_COMPL) == BMSR_ANEG_COMPL); +} +#endif // XMC_ETH_PHY_KSZ8081RNB diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_fce.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_fce.c new file mode 100644 index 00000000..09ac2f13 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_fce.c @@ -0,0 +1,258 @@ +/** + * @file xmc_fce.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed GetDriverVersion API + * @endcond + * + */ + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ +#include + +#if defined (FCE) +#include + +/******************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ + +/* + * Initialize the FCE peripheral: + * Update FCE configuration and initialize seed value + */ +XMC_FCE_STATUS_t XMC_FCE_Init(const XMC_FCE_t *const engine) +{ + engine->kernel_ptr->CFG = engine->fce_cfg_update.regval; + engine->kernel_ptr->CRC = engine->seedvalue; + + return XMC_FCE_STATUS_OK; +} + +/* Disable FCE */ +void XMC_FCE_Disable(void) +{ + FCE->CLC |= (uint32_t)FCE_CLC_DISR_Msk; + + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_FCE); + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_FCE); +#endif + +} + +/* Enable FCE */ +void XMC_FCE_Enable(void) +{ +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_FCE); +#endif + + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_FCE); + + FCE->CLC &= (uint32_t)~FCE_CLC_DISR_Msk; +} + +/* Calculate and return the SAE J1850 CRC8 checksum */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine, + const uint8_t *data, + uint32_t length, + uint8_t *result) +{ + XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK; + + XMC_ASSERT("XMC_FCE_CalculateCRC8: Wrong FCE kernel used", (engine -> kernel_ptr == XMC_FCE_CRC8)); + + if (length == 0UL) + { + status = XMC_FCE_STATUS_ERROR; + } + else + { + while (0UL != length) + { + engine->kernel_ptr->IR = *data; + data++; + length -= 1U; + } + + *result = (uint8_t)engine->kernel_ptr->CRC; + } + + return status; +} + +/* Calculate and return calculated CCITT CRC16 checksum */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine, + const uint16_t *data, + uint32_t length, + uint16_t *result) +{ + XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK; + + XMC_ASSERT("XMC_FCE_CalculateCRC16: Wrong FCE kernel used", (engine -> kernel_ptr == XMC_FCE_CRC16)); + XMC_ASSERT("XMC_FCE_CalculateCRC16: Length field is empty", (length != 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC16: Length is not aligned", ((length & 0x01) == 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC16: Buffer is not aligned", (((uint32_t)data % 2U) == 0)); + + /* Check if data and length are word aligned */ + if (((length & 0x01U) != 0U) || (((uint32_t)length % 2U) != 0U)) + { + status = XMC_FCE_STATUS_ERROR; + } + else + { + while (0UL != length) + { + engine->kernel_ptr->IR = *data; + data++; + length -= 2U; + } + + *result = (uint16_t)engine->kernel_ptr->CRC; + } + + return status; +} + +/* Calculate and return the IEEE 802.3 Ethernet CRC32 checksum */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine, + const uint32_t *data, + uint32_t length, + uint32_t *result) +{ + XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK; + + XMC_ASSERT("XMC_FCE_CalculateCRC32: Wrong FCE kernel used", ((engine->kernel_ptr == XMC_FCE_CRC32_0) || + (engine->kernel_ptr == XMC_FCE_CRC32_1))); + XMC_ASSERT("XMC_FCE_CalculateCRC32: Length field is empty", (length != 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC32: Length is not aligned", ((length & 0x03) == 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC32: Buffer is not aligned", (((uint32_t)data % 4U) == 0)); + + /* Check if data and length are word aligned */ + if (((length & 0x03U) != 0U) || (((uint32_t)length % 4U) != 0U)) + { + status = XMC_FCE_STATUS_ERROR; + } + else + { + while (0UL != length) + { + engine->kernel_ptr->IR = *data; + data++; + length -= 4U; + } + + *result = engine->kernel_ptr->CRC; + } + + return status; +} + +/* Trigger mismatch in the CRC registers */ +void XMC_FCE_TriggerMismatch(const XMC_FCE_t *const engine, XMC_FCE_CTR_TEST_t test) +{ + /* Create a 0 to 1 transition and clear to 0 once it is done */ + engine->kernel_ptr->CTR &= ~((uint32_t)test); + engine->kernel_ptr->CTR |= (uint32_t)test; + engine->kernel_ptr->CTR &= ~((uint32_t)test); +} + +/* Change endianness of 16-bit input buffer */ +void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t length) +{ + uint16_t counter = 0U; + uint16_t bytecounter = 0U; + + if ((length & 0x01U) == 0) + { + for (counter = 0U; counter < (length >> 1); counter++) + { + outbuffer[counter] = 0U; + } + + outbuffer[counter] = 0U; + counter = 0U; + + while (length) + { + outbuffer[counter] = ((uint16_t)((uint16_t)inbuffer[bytecounter] << 8U) | + (inbuffer[bytecounter + 1U])); + counter += 1U; + bytecounter += 2U; + length -= 2U; + } + } +} + +/* Change endianness of 32-bit input buffer */ +void XMC_FCE_LittleEndian32bit(uint8_t* inbuffer, uint32_t* outbuffer, uint16_t length) +{ + uint16_t counter = 0U; + uint16_t bytecounter = 0U; + + if ((length & 0x03U) == 0) + { + for (counter = 0U; counter < (length >> 2U); counter++) + { + outbuffer[counter] = 0U; + } + + outbuffer[counter] = 0U; + counter = 0U; + + while (length) + { + outbuffer[counter] = ((uint32_t)inbuffer[bytecounter] << 24U) | + ((uint32_t)inbuffer[bytecounter + 1U] << 16U) | + ((uint32_t)inbuffer[bytecounter + 2U] << 8U) | + (inbuffer[bytecounter + 3U]); + counter += 1U; + bytecounter += 4U; + length -= 4U; + } + } +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_gpio.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_gpio.c new file mode 100644 index 00000000..208b32dd --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_gpio.c @@ -0,0 +1,81 @@ +/** + * @file xmc_gpio.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * @endcond + * + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define PORT_HWSEL_Msk PORT0_HWSEL_HW0_Msk + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +void XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode) +{ + XMC_ASSERT("XMC_GPIO_SetMode: Invalid port", XMC_GPIO_CHECK_PORT(port)); + XMC_ASSERT("XMC_GPIO_SetMode: Invalid mode", XMC_GPIO_IsModeValid(mode)); + + port->IOCR[(uint32_t)pin >> 2U] &= ~(uint32_t)((uint32_t)PORT_IOCR_PC_Msk << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U))); + port->IOCR[(uint32_t)pin >> 2U] |= (uint32_t)mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U)); +} + +void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl) +{ + XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid port", XMC_GPIO_CHECK_PORT(port)); + XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid hwctrl", XMC_GPIO_CHECK_HWCTRL(hwctrl)); + + port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U)); + port->HWSEL |= (uint32_t)hwctrl << ((uint32_t)pin << 1U); +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_hrpwm.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_hrpwm.c new file mode 100644 index 00000000..e015b879 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_hrpwm.c @@ -0,0 +1,591 @@ + +/** + * @file xmc_hrpwm.c + * @date 2015-07-14 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Variable g_hrpwm_char_data[] defined in startup file is used in place of trim data macro
+ * + * 2015-05-12: + * - XMC_HRPWM_CSG_SelClampingInput() api is added to select the clamping input.
+ * - In XMC_HRPWM_Init() api macros used to check 'ccu_clock' frequency are renamed for readability
+ * - 80MHz HRC operation would need a minimum of 70 Mhz CCU clock.
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * - Updated copyright and change history section.
+ * + * 2015-07-06: + * - CSG trimming data assignment is corrected.
+ * + * 2015-07-14: + * - Redundant code removed in XMC_HRPWM_HRC_ConfigSourceSelect0() and XMC_HRPWM_HRC_ConfigSourceSelect1() API's.
+ * - Enums and masks are type casted to uint32_t type. + * + * @endcond + * + */ + +/** + * + * @brief HRPWM low level driver API prototype definition for XMC family of microcontrollers
+ * + * Detailed description of file
+ * APIs provided in this file cover the following functional blocks of HRPWM:
+ * -- High Resolution Channel (APIs prefixed with XMC_HRPWM_HRC_)
+ * -- Comparator and Slope Generator (APIs prefixed with XMC_HRPWM_CSG_)
+ * + */ + +/*********************************************************************************************************************** + * HEADER FILES + **********************************************************************************************************************/ +#include + +#if defined(HRPWM0) +#include + +/*********************************************************************************************************************** + * MACROS + **********************************************************************************************************************/ +/* 70MHz is considered as the minimum range for 80MHz HRC operation */ +#define XMC_HRPWM_70MHZ_FREQUENCY 70000000U + +/* 100MHz is considered as the maximum range for 80MHz HRC operation */ +#define XMC_HRPWM_100MHZ_FREQUENCY 100000000U + +/* 150MHz is considered as the maximum range for 120MHz HRC operation */ +#define XMC_HRPWM_150MHZ_FREQUENCY 150000000U + +/* 200MHz is considered as the maximum range for 180MHz HRC operation */ +#define XMC_HRPWM_200MHZ_FREQUENCY 200000000U + +#if (UC_SERIES == XMC44) +#define XMC_HRPWM_DELAY_CNT (28800U) /* Provides ~2.8 msec delay @ 220MHz frequency */ + +#elif (UC_SERIES == XMC42) +#define XMC_HRPWM_DELAY_CNT (19200U) /* Provides ~2.8 msec delay @ 150MHz frequency */ + +#else +#define XMC_HRPWM_DELAY_CNT (36000U) /* Provides ~5.3 msec delay @ 150MHz frequency */ +#endif + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ + static void XMC_HRPWM_lDelay(void); + +/*********************************************************************************************************************** + * API IMPLEMENTATION - GENERAL + **********************************************************************************************************************/ + +/* Delay */ +void XMC_HRPWM_lDelay(void) +{ + volatile uint32_t i; + + for (i = 0U; i <= XMC_HRPWM_DELAY_CNT; i++) /* Wait more than 2 microseconds */ + { + __NOP(); + } +} + +/*********************************************************************************************************************** + * API IMPLEMENTATION - HRPWM GLOBAL + **********************************************************************************************************************/ +/* Initializes HRPWM global registers */ +XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm) +{ + uint32_t *csg_memory; + uint32_t ccu_clock; + uint32_t clkc; + XMC_HRPWM_STATUS_t status; + + XMC_ASSERT("XMC_HRPWM_Init:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + status = XMC_HRPWM_STATUS_ERROR; + + /* Apply reset to HRPWM module */ + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0); + + /* Release reset for HRPWM module */ + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0); + + /* Ungate clock */ + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_HRPWM0); + + hrpwm->GLBANA = (uint32_t)0x00004A4E; /* Initialization sequence */ + + hrpwm->HRBSC |= (uint32_t)HRPWM0_HRBSC_HRBE_Msk; /* Enable Bias Generator of HRPWM */ + + /* Update CSG0 memory data */ + csg_memory = (uint32_t *)XMC_HRPWM_CSG0_MEMORY_ADDRESS; + *csg_memory = g_hrpwm_char_data[0]; + /* write csg memory bits[14:11] with 0b1100 */ + *csg_memory &= (uint32_t)(0xFFFF87FF); + *csg_memory |= (uint32_t)(0x00006000); + + /* Update CSG1 trimming data */ + csg_memory = (uint32_t *)XMC_HRPWM_CSG1_MEMORY_ADDRESS; + *csg_memory = g_hrpwm_char_data[1]; + /* write csg memory bits[14:11] with 0b1100 */ + *csg_memory &= (uint32_t)(0xFFFF87FF); + *csg_memory |= (uint32_t)(0x00006000); + + /* Update CSG2 trimming data */ + csg_memory = (uint32_t *)XMC_HRPWM_CSG2_MEMORY_ADDRESS; + *csg_memory = g_hrpwm_char_data[2]; + /* write csg memory bits[14:11] with 0b1100 */ + *csg_memory &= (uint32_t)(0xFFFF87FF); + *csg_memory |= (uint32_t)(0x00006000); + + /* Set CSG units to high speed mode */ + hrpwm->CSGCFG = (uint32_t)(0x0000003F); + + /* Read CCU clock frequency */ + ccu_clock = XMC_SCU_CLOCK_GetCcuClockFrequency(); + + if ((ccu_clock > XMC_HRPWM_70MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_100MHZ_FREQUENCY)) + { + clkc = 3U; /* Clock frequency range 70MHz+ - 100MHz is considered as 80MHz HRC operation */ + } + else if ((ccu_clock > XMC_HRPWM_100MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_150MHZ_FREQUENCY)) + { + clkc = 2U; /* Clock frequency range 100MHz+ - 150MHz is considered as 120MHz HRC operation */ + } + else if ((ccu_clock > XMC_HRPWM_150MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_200MHZ_FREQUENCY)) + { + clkc = 1U; /* Clock frequency range 150MHz+ - 200MHz is considered as 180MHz HRC operation */ + } + else + { + clkc = 0U; /* Invalid frequency for HRC operation: Clock frequency <= 60MHz & Clock frequency > 200MHz */ + } + + if (clkc != 0U) /* Enter the loop only if the clock frequency is valid */ + { + /* Program HRC clock configuration with clock frequency information */ + hrpwm->HRCCFG |= (clkc << HRPWM0_HRCCFG_CLKC_Pos); + + hrpwm->HRCCFG |= (uint32_t)HRPWM0_HRCCFG_HRCPM_Msk; /* Release HR generation from power down mode */ + + XMC_HRPWM_lDelay(); /* As per Initialization sequence */ + + /* Enable global high resolution generation / Force charge pump down */ + hrpwm->GLBANA |= (uint32_t)HRPWM0_GLBANA_GHREN_Msk; + + XMC_HRPWM_lDelay(); + + /* Check High resolution ready bit field */ + if ((hrpwm->HRGHRS & HRPWM0_HRGHRS_HRGR_Msk) == 1U) + { + /* High resolution logic unit is ready */ + status = XMC_HRPWM_STATUS_OK; + } + } + else + { + status = XMC_HRPWM_STATUS_ERROR; /* Clock frequency is invalid */ + } + + return (status); +} + +/* Enable global high resolution generation */ +void XMC_HRPWM_EnableGlobalHR(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_EnableGlobalHR:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + /* Enable global high resolution generation / Force charge pump down */ + hrpwm->GLBANA |= (uint32_t)HRPWM0_GLBANA_GHREN_Msk; + + XMC_HRPWM_lDelay(); /* Elapse startup time */ +} + +/* Disable global high resolution generation */ +void XMC_HRPWM_DisableGlobalHR(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_DisableGlobalHR:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + /* Enable global high resolution generation / Force charge pump down */ + hrpwm->GLBANA &= ~((uint32_t)HRPWM0_GLBANA_GHREN_Msk); +} + +/*********************************************************************************************************************** + * API IMPLEMENTATION - HRPWM HRC GLOBAL + **********************************************************************************************************************/ +/* Checks and returns high resolution generation working status */ +XMC_HRPWM_HR_LOGIC_t XMC_HRPWM_GetHRGenReadyStatus(XMC_HRPWM_t *const hrpwm) +{ + XMC_HRPWM_HR_LOGIC_t status; + + XMC_ASSERT("XMC_HRPWM_GetHRGenReadyStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + if (hrpwm->HRGHRS) + { + status = XMC_HRPWM_HR_LOGIC_WORKING; + } + else + { + status = XMC_HRPWM_HR_LOGIC_NOT_WORKING; + } + return status; +} + +/*********************************************************************************************************************** + * API IMPLEMENTATION - HRPWM HRC CHANNEL + **********************************************************************************************************************/ +/* Initialize HRPWM HRC channel */ +void XMC_HRPWM_HRC_Init(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_HRC_Init:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + + /* Setting of HRCy mode configuration */ + hrc->GC = config->gc; + + /* Passive level configuration */ + hrc->PL = config->psl; +} + +/* Configure Source selector 0 */ +void XMC_HRPWM_HRC_ConfigSourceSelect0(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_HRPWM_HRC_ConfigSourceSelect0:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + + /* HRC mode config for source selector 0 */ + hrc->GC &= ~((uint32_t)HRPWM0_HRC_GC_HRM0_Msk); + hrc->GC |= ((uint32_t)config->high_res_mode) << HRPWM0_HRC_GC_HRM0_Pos; + + /***************************************************************************** + * HRCy global control selection (HRCyGSEL) + ****************************************************************************/ + reg = 0U; + + if(config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) + { + reg = ((uint32_t)config->cmp_set) << HRPWM0_HRC_GSEL_C0SS_Pos; + reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_S0M_Pos; /* comparator output controls the set config */ + } + + if (config->clear_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) + { + reg |= ((uint32_t)config->cmp_clear) << HRPWM0_HRC_GSEL_C0CS_Pos; + reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_C0M_Pos; /* comparator output controls the clear config */ + } + + reg |= ((uint32_t)config->set_edge_config) << HRPWM0_HRC_GSEL_S0ES_Pos; + reg |= ((uint32_t)config->clear_edge_config) << HRPWM0_HRC_GSEL_C0ES_Pos; + hrc->GSEL &= (uint32_t)0xFFFF0000; + hrc->GSEL |= reg; + + /***************************************************************************** + * HRCy timer selection (HRCyTSEL) + ****************************************************************************/ + reg = (uint32_t)config->timer_sel; + reg |= ((uint32_t)config->src_trap_enable) << HRPWM0_HRC_TSEL_TS0E_Pos; + hrc->TSEL &= (uint32_t)0xFFFEFFF8; + hrc->TSEL |= reg; +} + +/* Configure Source selector 1 */ +void XMC_HRPWM_HRC_ConfigSourceSelect1(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_HRPWM_HRC_ConfigSourceSelect1:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + + /* HRC mode config for source selector 1 */ + hrc->GC &= ~((uint32_t)HRPWM0_HRC_GC_HRM1_Msk); + hrc->GC |= ((uint32_t)config->high_res_mode) << HRPWM0_HRC_GC_HRM1_Pos; + + /***************************************************************************** + * HRCy global control selection (HRCyGSEL) + ****************************************************************************/ + reg = 0U; + + if(config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) + { + reg = ((uint32_t)config->cmp_set) << HRPWM0_HRC_GSEL_C1SS_Pos; + reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_S1M_Pos; /* comparator output controls the set config*/ + } + + if (config->clear_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) + { + reg |= ((uint32_t)config->cmp_clear) << HRPWM0_HRC_GSEL_C1CS_Pos; + reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_C1M_Pos; /* comparator output controls the clear config */ + } + + reg |= ((uint32_t)config->set_edge_config) << HRPWM0_HRC_GSEL_S1ES_Pos; + reg |= ((uint32_t)config->clear_edge_config) << HRPWM0_HRC_GSEL_C1ES_Pos; + hrc->GSEL &= (uint32_t)0x0000FFFF; + hrc->GSEL |= reg; + + /***************************************************************************** + * HRCy timer selection (HRCyTSEL) + ****************************************************************************/ + reg = (uint32_t)config->timer_sel; + reg |= ((uint32_t)config->src_trap_enable) << HRPWM0_HRC_TSEL_TS1E_Pos; + hrc->TSEL &= (uint32_t)0xFFFDFFC7; + hrc->TSEL |= reg; +} + +/*********************************************************************************************************************** + * API IMPLEMENTATION - HRPWM CSG GLOBAL + **********************************************************************************************************************/ +/* No api's for CSG GLOBAL in xmc_hrpwm.c file */ + +/*********************************************************************************************************************** + * API IMPLEMENTATION - HRPWM CSG SLICE + **********************************************************************************************************************/ +/* Initialization of CSG slice */ +void XMC_HRPWM_CSG_Init(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CONFIG_t *const config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_HRPWM_CSG_Init:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + /* Passive level configuration */ + csg->PLC = config->cmp_config.plc; + + /* DAC Reference values */ + csg->SDSV1 = config->dac_config.dac_dsv1; + csg->DSV2 = config->dac_config.dac_dsv2; + + /* Pulse Swallow value */ + csg->SPC = config->sgen_config.pulse_swallow_val; + + /* Slope generation control (CSGySC) */ + if(config->sgen_config.ctrl_mode != (uint32_t) XMC_HRPWM_CSG_SLOPE_CTRL_MODE_STATIC) + { + /* Dynamic Slope Generation */ + csg->SC = config->sgen_config.sc; + } + else + { + /* Static Mode */ + csg->SC = ((uint32_t)config->sgen_config.static_mode_ist_enable) << HRPWM0_CSG_SC_IST_Pos; + } + reg = ((uint32_t)config->dac_config.start_mode) << HRPWM0_CSG_SC_SWSM_Pos; + csg->SC |= reg; + + /* Comparator Initialization */ + csg->CC = config->cmp_config.cc; + + /* Blanking value */ + csg->BLV = config->cmp_config.blanking_val; +} + +/* Set either CINA or CINB as inverting input of the comparator */ +void XMC_HRPWM_CSG_SetCMPInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CMP_INPUT_t input) +{ + XMC_ASSERT("XMC_HRPWM_CSG_SetCMPInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + if (input == XMC_HRPWM_CSG_CMP_INPUT_CINA) + { + /* Inverting comparator input connected to CINA */ + csg->CC &= ~((uint32_t)HRPWM0_CSG_CC_IMCS_Msk); + } + else + { + /* Inverting comparator input connected to CINB */ + csg->CC |= (uint32_t)HRPWM0_CSG_CC_IMCS_Msk; + } +} + +/* Configure input selection for Blanking function */ +void XMC_HRPWM_CSG_SelBlankingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_HRPWM_CSG_SelBlankingInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + reg = csg->CC; + + if ((reg & HRPWM0_CSG_CC_EBE_Msk) != 0U) /* external blanking trigger enabled? */ + { + reg &= ~((uint32_t)HRPWM0_CSG_CC_IBS_Msk); + reg |= (uint32_t) config->mapped_input; + } + + reg &= ~((uint32_t)HRPWM0_CSG_CC_BLMC_Msk); + reg |= ((uint32_t) config->edge) << HRPWM0_CSG_CC_BLMC_Pos; + + csg->CC = reg; +} + +/* Configure input selection for Clamping */ +void XMC_HRPWM_CSG_SelClampingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_HRPWM_CSG_SelClampingInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + reg = csg->PLC; + + reg &= ~((uint32_t)HRPWM0_CSG_PLC_IPLS_Msk); + reg |= (uint32_t) config->mapped_input; + + reg &= ~((uint32_t)HRPWM0_CSG_PLC_PLCL_Msk); + reg |= ((uint32_t) config->level) << HRPWM0_CSG_PLC_PLCL_Pos; + + csg->PLC = reg; +} + +/* Configure input selection to start slope generation function */ +void XMC_HRPWM_CSG_StartSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_CSG_StartSlopeGenConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STRIS_Msk); + csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STRIS_Pos; + csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STRES_Msk); + csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STRES_Pos; +} + +/* Configure input selection to stop slope generation function */ +void XMC_HRPWM_CSG_StopSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_CSG_StopSlopeGenConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STPIS_Msk); + csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STPIS_Pos; + csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STPES_Msk); + csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STPES_Pos; +} + +/* Configure input selection for triggering DAC conversion */ +void XMC_HRPWM_CSG_TriggerDACConvConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_CSG_TriggerDACConvConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_TRGIS_Msk); + csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_TRGIS_Pos; + csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_TRGES_Msk); + csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_TRGES_Pos; +} + +/* Configure input selection for triggering shadow transfer */ +void XMC_HRPWM_CSG_TriggerShadowXferConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_CSG_TriggerShadowXferConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STIS_Msk); + csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STIS_Pos; + csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STES_Msk); + csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STES_Pos; +} + +/* Configure input selection to trigger a switch in DAC reference value. This is only applicable to DAC in static mode */ +void XMC_HRPWM_CSG_DACRefValSwitchingConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_CSG_DACRefValSwitchingConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_SVIS_Msk); + csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_SVIS_Pos; + csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_SVLS_Msk); + csg->IES |= ((uint32_t)config->level) << HRPWM0_CSG_IES_SVLS_Pos; +} + +/* Configure input selection for clock selection used in slope generation */ +void XMC_HRPWM_CSG_SelSlopeGenClkInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CLK_INPUT_t input_clk) +{ + XMC_ASSERT("XMC_HRPWM_CSG_SelSlopeGenClkInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_SCS_Msk); + csg->DCI |= ((uint32_t)input_clk) << HRPWM0_CSG0_DCI_SCS_Pos; +} + +/* Set the service request interrupt node */ +void XMC_HRPWM_CSG_SetSRNode(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_IRQ_ID_t event, + const XMC_HRPWM_CSG_IRQ_SR_LINE_t sr) +{ + XMC_ASSERT("XMC_HRPWM_CSG_SetSRNode:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + switch (event) + { + case (XMC_HRPWM_CSG_IRQ_ID_VLS1): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_VLS1S_Msk); + csg->SRS |= (uint32_t)sr; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_VLS2): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_VLS2S_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_VLS2S_Pos; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_TRGS): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_TRLS_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_TRLS_Pos; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_STRS): + case (XMC_HRPWM_CSG_IRQ_ID_STPS): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_SSLS_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_SSLS_Pos; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_STD): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_STLS_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_STLS_Pos; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_CRSE): + case (XMC_HRPWM_CSG_IRQ_ID_CFSE): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_CRFLS_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_CRFLS_Pos; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_CSEE): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_CSLS_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_CSLS_Pos; + break; + + default: + break; + } +} + +#endif /* #if defined(HRPWM0) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_i2c.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_i2c.c new file mode 100644 index 00000000..7d9e3802 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_i2c.c @@ -0,0 +1,402 @@ +/** + * @file xmc_i2c.c + * @date 2015-10-02 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + - Modified XMC_I2C_CH_Stop() API for not setting to IDLE the channel if it is busy
+ * + * 2015-06-20: + * - Removed GetDriverVersion API
+ * + * 2015-08-14: + * - updated the XMC_I2C_CH_SetBaudrate API to support dynamic change from 400K to low frequencies
+ * + * 2015-09-01: + * - Modified XMC_I2C_CH_EnableEvent() and XMC_I2C_CH_DisableEvent() for supporting multiple events configuration
+ * + * 2015-10-02: + * - Fixed 10bit addressing + * + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ +#include + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ +#define XMC_I2C_7BIT_ADDR_Pos (8U) /**< 7-bit address position */ +#define TRANSMISSION_MODE (3U) /**< The shift control signal is considered active + without referring to the actual signal level. Data + frame transfer is possible after each edge of the signal.*/ +#define WORDLENGTH (7U) /**< Word length */ +#define SET_TDV (1U) /**< Transmission data valid */ +#define XMC_I2C_10BIT_ADDR_MASK (0x7C00U) /**< Address mask for 10-bit mode */ + +/********************************************************************************************************************* + * ENUMS + *********************************************************************************************************************/ + +typedef enum XMC_I2C_CH_TDF +{ + XMC_I2C_CH_TDF_MASTER_SEND = 0U, + XMC_I2C_CH_TDF_SLAVE_SEND = (uint32_t)1U << 8U, + XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK = (uint32_t)2U << 8U, + XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK = (uint32_t)3U << 8U, + XMC_I2C_CH_TDF_MASTER_START = (uint32_t)4U << 8U, + XMC_I2C_CH_TDF_MASTER_RESTART = (uint32_t)5U << 8U, + XMC_I2C_CH_TDF_MASTER_STOP = (uint32_t)6U << 8U +} XMC_I2C_CH_TDF_t; + +typedef enum XMC_I2C_CH_MAX_SPEED +{ + XMC_I2C_CH_MAX_SPEED_STANDARD = 100000U, + XMC_I2C_CH_MAX_SPEED_FAST = 400000U +} XMC_I2C_CH_MAX_SPEED_t; + +typedef enum XMC_I2C_CH_CLOCK_OVERSAMPLING +{ + XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD = 10U, + XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST = 25U +} XMC_I2C_CH_CLOCK_OVERSAMPLINGS_t; + +/********************************************************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ +/* Initializes the USIC channel by setting the data format, slave address, baudrate, transfer buffer */ +void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config) +{ + XMC_USIC_CH_Enable(channel); + + /* Data format configuration */ + channel->SCTR = ((uint32_t)TRANSMISSION_MODE << (uint32_t)USIC_CH_SCTR_TRM_Pos) | /* Transmision mode */ + ((uint32_t)WORDLENGTH << (uint32_t)USIC_CH_SCTR_WLE_Pos) | /* 8 data bits */ + USIC_CH_SCTR_FLE_Msk | /* unlimited data flow */ + USIC_CH_SCTR_SDIR_Msk | /* MSB shifted first */ + USIC_CH_SCTR_PDL_Msk; /* Passive Data Level */ + + XMC_I2C_CH_SetSlaveAddress(channel, config->address); + (void)XMC_I2C_CH_SetBaudrate(channel, config->baudrate); + + /* Enable transfer buffer */ + channel->TCSR = ((uint32_t)SET_TDV << (uint32_t)USIC_CH_TCSR_TDEN_Pos) | USIC_CH_TCSR_TDSSM_Msk; + + /* Clear status flags */ + channel->PSCR = 0xFFFFFFFFU; + + /* Disable parity generation */ + channel->CCR = 0x0U; +} +/* Sets the slave address */ +void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t address) +{ + if ((address & XMC_I2C_10BIT_ADDR_MASK) == XMC_I2C_10BIT_ADDR_GROUP) + { + channel->PCR_IICMode = (address & 0xffU) | ((address << 1) & 0xfe00U); + } + else + { + channel->PCR_IICMode = ((uint32_t)address) << XMC_I2C_7BIT_ADDR_Pos; + } +} +/* Read the slave address */ +uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel) +{ + uint32_t address = channel->PCR_IICMode & (uint32_t)USIC_CH_PCR_IICMode_SLAD_Msk; + + if ((address & 0xffU) == 0U) + { + address = address >> XMC_I2C_7BIT_ADDR_Pos; + } + else + { + address = (address & 0xffU) | ((address >> 1) & 0x0300U); + } + + return (uint16_t)address; +} +/* Sets the baudrate and oversampling based on standard speed or fast speed */ +XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate) +{ + XMC_I2C_CH_STATUS_t status; + + status = XMC_I2C_CH_STATUS_ERROR; + + if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_STANDARD) + { + channel->PCR_IICMode &= (uint32_t)~USIC_CH_PCR_IICMode_STIM_Msk; + if (XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD) == XMC_USIC_CH_STATUS_OK) + { + status = XMC_I2C_CH_STATUS_OK; + } + } + else if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_FAST) + { + channel->PCR_IICMode |= (uint32_t)USIC_CH_PCR_IICMode_STIM_Msk; + if (XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST) == XMC_USIC_CH_STATUS_OK) + { + status = XMC_I2C_CH_STATUS_OK; + } + } + else + { + status = XMC_I2C_CH_STATUS_ERROR; + } + + return status; +} +/* Sends master start condition along with read/write command to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command) +{ + uint32_t temp; + + temp = addr | (uint32_t)XMC_I2C_CH_TDF_MASTER_START; + if (command == XMC_I2C_CH_CMD_READ) + { + temp |= 0x1U; + } + + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = temp; + } + else + { + channel->IN[0U] = temp; + } +} +/* Sends master repeated start condition along with read/write command to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterRepeatedStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command) +{ + uint32_t tmp; + tmp = addr | (uint32_t)XMC_I2C_CH_TDF_MASTER_RESTART; + if (command == XMC_I2C_CH_CMD_READ) + { + tmp |= 0x1U; + } + + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = tmp; + } + else + { + channel->IN[0U] = tmp; + } +} + +/* Sends master stop command to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterStop(XMC_USIC_CH_t *const channel) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_STOP; + } + else + { + channel->IN[0U] = (uint32_t)XMC_I2C_CH_TDF_MASTER_STOP; + } +} + +/* Sends master send command along with data to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterTransmit(XMC_USIC_CH_t *const channel, const uint8_t data) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_SEND | data; + } + else + { + channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_SEND | data; + } +} + +/* Sends slave send command along with data to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_SlaveTransmit(XMC_USIC_CH_t *const channel, const uint8_t data) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_SLAVE_SEND | data; + } + else + { + channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_SLAVE_SEND | data; + } +} + +/* Sends master receive ack command to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterReceiveAck(XMC_USIC_CH_t *const channel) +{ +/* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK; + } + else + { + channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK; + } +} + +/* Sends master receive nack command to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterReceiveNack(XMC_USIC_CH_t *const channel) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK; + } + else + { + channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK; + } +} + +/* Reads the data from RBUF if FIFO size is 0 otherwise from OUTR. */ +uint8_t XMC_I2C_CH_GetReceivedData(const XMC_USIC_CH_t *const channel) +{ + uint8_t retval; + + /* Check FIFO size */ + if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U) + { + retval = (uint8_t)channel->RBUF; + } + else + { + retval = (uint8_t)channel->OUTR; + } + + return retval; +} + +/* Sets the operating mode of USIC to IDLE */ +XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel) +{ + XMC_I2C_CH_STATUS_t status = XMC_I2C_CH_STATUS_OK; + + if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) + { + status = XMC_I2C_CH_STATUS_BUSY; + } + else + { + /* USIC channel in IDLE mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE); + } + return status; +} + +void XMC_I2C_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR |= (event&0x1fc00U); + channel->PCR_IICMode |= ((event) & 0x41fc0000U); +} + +void XMC_I2C_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR &= (uint32_t)~(event&0x1fc00U); + channel->PCR_IICMode &= (uint32_t)~((event) & 0x41fc0000U); +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_i2s.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_i2s.c new file mode 100644 index 00000000..332195e3 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_i2s.c @@ -0,0 +1,268 @@ +/** + * @file xmc_i2s.c + * @date 2015-06-30 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-08-21: + * - Initial
+ * + * 2015-09-01: + * - Modified XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent() for supporting multiple events configuration
+ * + * 2015-09-14: + * - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length. + * - Removed parity configuration
+ * + * 2015-09-28: + * - Fixed bugs in the XMC_I2S_CH_Init() and in the ASSERTs
+ * + * 2015-11-04: + * - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_I2S_CH_Transmit() API
+ * + * 2016-06-30: + * - Modified XMC_I2S_CH_Init: + * + change default passive level to 0 + * + Call XMC_I2S_CH_SetSystemWordLength() to set the system frame length equal to the frame length. + * - Modified XMC_I2S_CH_SetBaudrate: + * + Optional Master clock output signal generated with a fixed phase relation to SCLK. + * + * @endcond + * + */ +/** + * + * @brief I2S driver for XMC microcontroller family + * + */ +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include +#include + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +/* To take into account the SCLK divider by 2 and the PPPEN divider (see Divider Mode Counter figure in RM) */ +#define XMC_I2S_CH_OVERSAMPLING (4UL) + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/* Initializes the selected I2S channel with the config structure. */ +void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(config->data_delayed_sclk_periods > 0U) && + (config->data_delayed_sclk_periods < config->frame_length)); + XMC_USIC_CH_Enable(channel); + + if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER) + { + /* Configure baud rate */ + (void)XMC_I2S_CH_SetBaudrate(channel, config->baudrate); + } + /* Configuration of USIC Shift Control */ + /* Transmission Mode (TRM) = 1 */ + channel->SCTR = (uint32_t)(0x3UL << USIC_CH_SCTR_TRM_Pos) | + (uint32_t)((config->frame_length -1U) << USIC_CH_SCTR_FLE_Pos) | + (uint32_t)((config->data_bits - 1U) << USIC_CH_SCTR_WLE_Pos) | + USIC_CH_SCTR_SDIR_Msk; + + /* Configuration of USIC Transmit Control/Status Register */ + /* TBUF Data Enable (TDEN) = 1 */ + /* TBUF Data Single Shot Mode (TDSSM) = 1 */ + /* WA mode enabled(WAMD) = 1 */ + channel->TCSR = (uint32_t)((channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk | + USIC_CH_TCSR_SELMD_Msk | + USIC_CH_TCSR_FLEMD_Msk | + USIC_CH_TCSR_HPCMD_Msk))) | + USIC_CH_TCSR_WAMD_Msk | + (0x01UL << USIC_CH_TCSR_TDEN_Pos) | + USIC_CH_TCSR_TDSSM_Msk); + + if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER) + { + /* Configuration of Protocol Control Register */ + channel->PCR_IISMode = (uint32_t)USIC_CH_PCR_IISMode_WAGEN_Msk; + } + + /* Configuration of Protocol Control Register */ + channel->PCR_IISMode |= (uint32_t)(USIC_CH_PCR_IISMode_DTEN_Msk | + (uint32_t)config->wa_inversion) | + ((uint32_t)((uint32_t)config->data_delayed_sclk_periods - 1U) << USIC_CH_PCR_IISMode_TDEL_Pos); + + XMC_I2S_CH_SetSystemWordLength(channel, config->frame_length); + + /* Clear protocol status */ + channel->PSCR = 0xFFFFFFFFUL; +} + + +XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate) +{ + XMC_I2S_CH_STATUS_t status; + + status = XMC_I2S_CH_STATUS_ERROR; + + if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U)) + { + if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_I2S_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK) + { + channel->BRG = (uint32_t)((channel->BRG & ~(USIC_CH_BRG_CTQSEL_Msk)) | + (0x2UL << USIC_CH_BRG_CTQSEL_Pos)) | + USIC_CH_BRG_PPPEN_Msk; + + status = XMC_I2S_CH_STATUS_OK; + } + + } + return status; +} + +void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length) +{ + uint32_t sclk_cycles_system_word_length_temp; + uint8_t dctq_temp; + uint8_t pctq_temp; + uint8_t dctq = 1U; + uint8_t pctq = 1U; + uint8_t best_error = 64U; + uint8_t error; + XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(sclk_cycles_system_word_length > 0U) && (sclk_cycles_system_word_length < 65U)); + + + for (dctq_temp =1U; dctq_temp < 33U ; dctq_temp++) + { + for (pctq_temp =1U; pctq_temp < 5U ; pctq_temp++) + { + sclk_cycles_system_word_length_temp = ((uint32_t)dctq_temp) * ((uint32_t)pctq_temp); + if(sclk_cycles_system_word_length_temp == sclk_cycles_system_word_length) + { + dctq = dctq_temp; + pctq = pctq_temp; + break; + } + if (sclk_cycles_system_word_length_temp > sclk_cycles_system_word_length) + { + error = (uint8_t)(sclk_cycles_system_word_length_temp - sclk_cycles_system_word_length); + } + else + { + error = (uint8_t)(sclk_cycles_system_word_length - sclk_cycles_system_word_length_temp); + } + + if(error < best_error) + { + best_error = error; + dctq = dctq_temp; + pctq = pctq_temp; + } + } + } + channel->BRG = (uint32_t)((channel->BRG & ~((uint32_t)(USIC_CH_BRG_DCTQ_Msk | + USIC_CH_BRG_PCTQ_Msk))) | + (uint32_t)((uint32_t)((uint32_t)((uint32_t)dctq- 1U) << USIC_CH_BRG_DCTQ_Pos) | + (uint32_t)((uint32_t)((uint32_t)pctq- 1U) << USIC_CH_BRG_PCTQ_Pos))); +} + +/* Puts the data into FIFO if FIFO mode is enabled or else into standard buffers, by setting the proper mode. */ +void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNEL_t channel_number) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) + { + } + + XMC_I2S_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[(uint32_t)channel_number << 4] = data; + } + else + { + channel->IN[(uint32_t)channel_number << 4] = data; + } +} + +/* Reads the data from the buffers based on the FIFO mode selection. */ +uint16_t XMC_I2S_CH_GetReceivedData(XMC_USIC_CH_t *const channel) +{ + uint16_t retval; + + /* Check FIFO size */ + if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U) + { + retval = (uint16_t)channel->RBUF; + } + else + { + retval = (uint16_t)channel->OUTR; + } + + return retval; +} + +XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel) +{ + XMC_I2S_CH_STATUS_t status = XMC_I2S_CH_STATUS_OK; + + if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) + { + status = XMC_I2S_CH_STATUS_BUSY; + } + else + { + /* USIC channel in IDLE mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE); + } + + return status; +} + +void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR |= (event&0x1fc00U); + channel->PCR_IISMode |= ((event >> 2U) & 0x8070U); +} + +void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR &= (uint32_t)~(event&0x1fc00U); + channel->PCR_IISMode &= (uint32_t)~((event >> 2U) & 0x8070U); +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ledts.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ledts.c new file mode 100644 index 00000000..72ac5cd6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_ledts.c @@ -0,0 +1,383 @@ +/** + * @file xmc_ledts.c + * @date 2017-02-25 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * - New API added: XMC_LEDTS_SetActivePADNo()
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2017-02-25: + * - XMC_LEDTS_InitGlobal() fixed compilation warnings + * + * Detailed description of file:
+ * APIs for the functional blocks of LEDTS have been defined:
+ * -- GLOBAL (APIs prefixed with LEDTS_GLOBAL_)
+ * -- Clock configuration, Function/Event configuration, Interrupt configuration + * + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +#if defined(LEDTS0) +#include "xmc_scu.h" + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_LEDTS_CLOCK_NOT_RUNNING 0U + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * GLOBAL DATA + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * LOCAL/UTILITY ROUTINES + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/** + * Initialization of global register + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitGlobal(XMC_LEDTS_t *const ledts, const XMC_LEDTS_GLOBAL_CONFIG_t *config) +{ + XMC_ASSERT("XMC_LEDTS_InitGlobal:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + XMC_ASSERT("XMC_LEDTS_InitGlobal:Null Pointer", (config != (XMC_LEDTS_GLOBAL_CONFIG_t *)NULL)); + + if (ledts == XMC_LEDTS0) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS0); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS0); +#endif + } +#if defined(LEDTS1) + else if (ledts == XMC_LEDTS1) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS1); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS1); +#endif + } +#endif +#if defined(LEDTS2) + else if (ledts == XMC_LEDTS2) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS2); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS2); +#endif + } +#endif + else + { + XMC_ASSERT("XMC_LEDTS_InitGlobal:Invalid Module Pointer", 0); + } + + if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + { + return XMC_LEDTS_STATUS_RUNNING; + } + + ledts->GLOBCTL = config->globctl; + + return XMC_LEDTS_STATUS_SUCCESS; +} + +/** + * Initialization of registers for LED-driving function + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitLED(XMC_LEDTS_t *const ledts, const XMC_LEDTS_LED_CONFIG_t *config) +{ + XMC_ASSERT("XMC_LEDTS_LED_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + XMC_ASSERT("XMC_LEDTS_LED_Init:Null Pointer", (config != (XMC_LEDTS_LED_CONFIG_t *)NULL)); + + if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + { + return XMC_LEDTS_STATUS_RUNNING; + } + + ledts->FNCTL &= ~(LEDTS_FNCTL_COLLEV_Msk | LEDTS_FNCTL_NR_LEDCOL_Msk); + ledts->FNCTL |= (config->fnctl); + + /* Enable LED function */ + ledts->GLOBCTL |= LEDTS_GLOBCTL_LD_EN_Msk; + + return XMC_LEDTS_STATUS_SUCCESS; +} + +/** + * Initialization of registers for basic Touch-Sense control function + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSBasic(XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_BASIC_t *config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_LEDTS_TS_Basic_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + XMC_ASSERT("XMC_LEDTS_TS_Basic_Init:Null Pointer", (config != (XMC_LEDTS_TS_CONFIG_BASIC_t *)NULL)); + + if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + { + return XMC_LEDTS_STATUS_RUNNING; + } + + reg = ~(LEDTS_FNCTL_ACCCNT_Msk | LEDTS_FNCTL_TSCCMP_Msk | LEDTS_FNCTL_TSCTRR_Msk | LEDTS_FNCTL_TSCTRSAT_Msk | + LEDTS_FNCTL_NR_TSIN_Msk); + ledts->FNCTL &= (reg); + ledts->FNCTL |= (config->fnctl); + + /* Enable TS function */ + ledts->GLOBCTL |= LEDTS_GLOBCTL_TS_EN_Msk; + + return XMC_LEDTS_STATUS_SUCCESS; +} + +/** + * Initialization of registers for advanced Touch-Sense control function + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSAdvanced (XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_ADVANCED_t *config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_LEDTS_TS_Advanced_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + XMC_ASSERT("XMC_LEDTS_TS_Advanced_Init:Null Pointer", (config != (XMC_LEDTS_TS_CONFIG_ADVANCED_t *)NULL)); + + if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + { + return XMC_LEDTS_STATUS_RUNNING; + } + + reg = ~(LEDTS_GLOBCTL_MASKVAL_Msk | LEDTS_GLOBCTL_FENVAL_Msk); + ledts->GLOBCTL &= (reg); + ledts->GLOBCTL |= (config->globctl); + + reg = ~(LEDTS_FNCTL_PADT_Msk | LEDTS_FNCTL_PADTSW_Msk | LEDTS_FNCTL_EPULL_Msk | LEDTS_FNCTL_TSOEXT_Msk); + ledts->FNCTL &= (reg); + ledts->FNCTL |= (config->fnctl); + + return XMC_LEDTS_STATUS_SUCCESS; +} + +/** + * Starts LEDTS-counter + */ +void XMC_LEDTS_StartCounter(XMC_LEDTS_t *const ledts, const uint16_t prescaler) +{ + XMC_ASSERT("XMC_LEDTS_Start_Counter:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->GLOBCTL |= prescaler<<16U; +} + +/** + * Stops LEDTS-counter + */ +void XMC_LEDTS_StopCounter(XMC_LEDTS_t *const ledts) +{ + XMC_ASSERT("XMC_LEDTS_Stop_Counter:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->GLOBCTL &= 0x0000FFFF; +} + +/** + * Reads time interrupt flags + */ +uint32_t XMC_LEDTS_ReadInterruptFlag(XMC_LEDTS_t *const ledts) +{ + XMC_ASSERT("XMC_LEDTS_ReadInterruptFlag:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + return (ledts->EVFR & 0xF); +} + +/** + * Set the active pad number + */ +void XMC_LEDTS_SetActivePADNo(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t pad_num) +{ + uint32_t reg; + + XMC_ASSERT("XMC_LEDTS_SetActivePADNo:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + reg = ledts->FNCTL; + reg &= ~(LEDTS_FNCTL_PADT_Msk); + reg |= (uint32_t)pad_num; + ledts->FNCTL = reg; +} + +/** + * Clears interrupt indication flags + */ +void XMC_LEDTS_ClearInterruptFlag(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask) +{ + XMC_ASSERT("XMC_LEDTS_ClearInterruptFlag:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->EVFR = (interrupt_mask << LEDTS_EVFR_CTSF_Pos); +} + +/** + * Programming of registers to output pattern on an LED column in LED matrix + */ +void XMC_LEDTS_SetLEDLinePattern(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t pattern) +{ + uint32_t reg; + uint8_t reg_index = ((uint8_t)column) >> 2; + uint8_t bit_shift_count = ((uint8_t)column & 0x03) * 8; + + XMC_ASSERT("XMC_LEDTS_Set_LED_Line_Pattern:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + reg = ledts->LINE[reg_index]; + reg &= (~(0xff << bit_shift_count)); + reg |= pattern << bit_shift_count; + ledts->LINE[reg_index] = reg; + +} + +/** + * Programming of registers to adjust brightness of an LED column in LED matrix + */ +void XMC_LEDTS_SetColumnBrightness(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t brightness) +{ + uint32_t reg; + uint8_t reg_index = ((uint8_t)column) >> 2; + uint8_t bit_shift_count = ((uint8_t)column & 0x03) * 8; + + XMC_ASSERT("XMC_LEDTS_Set_Column_Brightness:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + reg = ledts->LDCMP[reg_index]; + reg &= (~(0xff << bit_shift_count)); + reg |= brightness << bit_shift_count; + ledts->LDCMP[reg_index] = reg; +} + +/** + * Programming of registers to set common oscillation window size for touch-sense inputs + */ +void XMC_LEDTS_SetCommonOscillationWindow(XMC_LEDTS_t *const ledts, const uint8_t common_size) +{ + uint32_t reg; + + XMC_ASSERT("XMC_LEDTS_Set_Common_Oscillation_Window:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + reg = ledts->LDCMP[1]; + reg &= ~LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk; + reg |= (common_size << LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos); + ledts->LDCMP[1] = reg; +} + +/** + * Checking the previous active function or LED column status + */ +uint32_t XMC_LEDTS_ReadFNCOL(XMC_LEDTS_t *const ledts) +{ + uint32_t fncol_read; + + XMC_ASSERT("XMC_LEDTS_Read_FNCOL:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + fncol_read = ledts->FNCTL & LEDTS_FNCTL_FNCOL_Msk; + fncol_read >>= LEDTS_FNCTL_FNCOL_Pos; + + return fncol_read; +} + +/** + * Set the number of LED column Enabled + */ +void XMC_LEDTS_SetNumOfLEDColumns(XMC_LEDTS_t *const ledts, uint8_t count) +{ + + XMC_ASSERT("XMC_LEDTS_SetNumOfLEDColumns:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->FNCTL &= ~(LEDTS_FNCTL_NR_LEDCOL_Msk); + ledts->FNCTL |= (count << LEDTS_FNCTL_NR_LEDCOL_Pos); +} + +/** + * Reading recorded number of oscillation counts + */ +uint16_t XMC_LEDTS_ReadTSVAL(XMC_LEDTS_t *const ledts) +{ + uint16_t no_of_oscillations; + + XMC_ASSERT("XMC_LEDTS_Read_TSVAL:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + no_of_oscillations = (ledts->TSVAL & 0xFFFF); + + return no_of_oscillations; +} + +/** + * Programming of registers to adjust the size of oscillation window + */ +void XMC_LEDTS_SetOscillationWindow(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t touchpad, const uint8_t size) +{ + uint32_t reg; + uint8_t reg_index = ((uint8_t)touchpad) >> 2; + uint8_t bit_shift_count = ((uint8_t)touchpad & 0x03) * 8; + + XMC_ASSERT("XMC_LEDTS_Set_Oscillation_Window:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + reg = ledts->TSCMP[reg_index]; + reg &= (~(0xff << bit_shift_count)); + reg |= size << bit_shift_count; + ledts->TSCMP[reg_index] = reg; +} + +#endif /* LEDTS0 */ + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_posif.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_posif.c new file mode 100644 index 00000000..a8b50a22 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_posif.c @@ -0,0 +1,275 @@ +/** + * @file xmc_posif.c + * @date 2017-02-25 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Initial version + * + * 2015-02-20: + * - Driver description added
+ * + * 2015-04-30: + * - XMC_POSIF_Enable and XMC_POSIF_Disable APIs updated for POSIF1 peripheral check
+ * + * 2015-06-19: + * - Removed GetDriverVersion API
+ * + * 2017-02-25: + * - XMC_POSIF_Enable() and XMC_POSIF_Disable() fixed compilation warnings + * + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +/* POSIF is not available on XMC1100 and XMC1200 */ +#if defined(POSIF0) +#include + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_POSIF_PCONF_INSEL_Msk (0x3fUL << POSIF_PCONF_INSEL0_Pos) /*< Mask for input pins selection */ +#define XMC_POSIF_INSEL_MAX (4U) /*< Maximum possible input selector */ + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ +#ifdef XMC_ASSERT_ENABLE +__STATIC_INLINE bool XMC_POSIF_IsPeripheralValid(const XMC_POSIF_t *const peripheral) +{ + bool tmp; + + tmp = (peripheral == POSIF0); +#if defined(POSIF1) + tmp |= (peripheral == POSIF1); +#endif + + return tmp; +} +#endif +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/* API to enable the POSIF module */ +void XMC_POSIF_Enable(XMC_POSIF_t *const peripheral) +{ +#if UC_FAMILY == XMC4 + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU); +#endif + + if (peripheral == POSIF0) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0); +#endif + } +#if defined(POSIF1) + else if (peripheral == POSIF1) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1); +#endif + } +#endif + else + { + XMC_ASSERT("XMC_POSIF_Disable:Invalid module pointer", 0); + } +} + +/* API to disable the POSIF module */ +void XMC_POSIF_Disable(XMC_POSIF_t *const peripheral) +{ + if (peripheral == POSIF0) + { +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0); +#endif + } +#if defined(POSIF1) + else if (peripheral == POSIF1) + { +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1); +#endif + } +#endif + else + { + XMC_ASSERT("XMC_POSIF_Disable:Invalid module pointer", 0); + } +} + +/* API to initialize POSIF global resources */ +void XMC_POSIF_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_POSIF_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_Init:NULL Pointer", (config != (XMC_POSIF_CONFIG_t *)NULL) ); + + /* Enable the POSIF module */ + XMC_POSIF_Enable(peripheral); + + /* Stop POSIF */ + XMC_POSIF_Stop(peripheral); + + /* Program the operational mode, input selectors and debounce filter */ + peripheral->PCONF = config->pconf; +} + +/* API to initialize hall sensor interface */ +XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_HSC_CONFIG_t * const config) +{ + XMC_POSIF_STATUS_t retval; + + XMC_ASSERT("XMC_POSIF_HSC_Init:Invalid module pointer\n", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_HSC_Init:NULL Pointer\n", (config != (XMC_POSIF_HSC_CONFIG_t *)NULL) ); + + if (XMC_POSIF_MODE_HALL_SENSOR == (XMC_POSIF_MODE_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk) ) + { + peripheral->PCONF |= config->hall_config; + retval = XMC_POSIF_STATUS_OK; + } + else + { + retval = XMC_POSIF_STATUS_ERROR; + } + return retval; +} + +/* API to initialize quadrature decoder interface */ +XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_QD_CONFIG_t * const config) +{ + uint8_t reg; + XMC_POSIF_STATUS_t retval; + + XMC_ASSERT("XMC_POSIF_QD_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_QD_Init:NULL Pointer", (config != (XMC_POSIF_QD_CONFIG_t *)NULL) ); + + reg = (uint8_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk); + if (((uint32_t)XMC_POSIF_MODE_QD == reg) || ((uint32_t)XMC_POSIF_MODE_MCM_QD == reg)) + { + /* Program the quadrature mode */ + peripheral->PCONF |= (uint32_t)(config->mode) << POSIF_PCONF_QDCM_Pos; + peripheral->QDC = config->qdc; + retval = XMC_POSIF_STATUS_OK; + } + else + { + retval = XMC_POSIF_STATUS_ERROR; + } + + return retval; +} + +/* API to initialize multi-channel mode. + * This is used in Hall mode, standalone multi-channel mode and quadrature with multi-channel mode + */ +XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_MCM_CONFIG_t * const config) +{ + XMC_POSIF_STATUS_t retval; + + XMC_ASSERT("XMC_POSIF_MCM_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_MCM_Init:NULL Pointer", (config != (XMC_POSIF_MCM_CONFIG_t *)NULL) ); + + if ((XMC_POSIF_MODE_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk) != XMC_POSIF_MODE_QD) + { + peripheral->PCONF |= config->mcm_config; + retval = XMC_POSIF_STATUS_OK; + } + else + { + retval = XMC_POSIF_STATUS_ERROR; + } + return retval; +} + +/* API to configure input source */ +void XMC_POSIF_SelectInputSource (XMC_POSIF_t *const peripheral, const XMC_POSIF_INPUT_PORT_t input0, + const XMC_POSIF_INPUT_PORT_t input1, const XMC_POSIF_INPUT_PORT_t input2) +{ + uint32_t reg; + XMC_ASSERT("XMC_POSIF_SelectInputSource:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input0", (input0 < XMC_POSIF_INSEL_MAX)); + XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input1", (input1 < XMC_POSIF_INSEL_MAX)); + XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input2", (input2 < XMC_POSIF_INSEL_MAX)); + + reg = (uint32_t)((((uint32_t)input0 << POSIF_PCONF_INSEL0_Pos) & (uint32_t)POSIF_PCONF_INSEL0_Msk) | + (((uint32_t)input1 << POSIF_PCONF_INSEL1_Pos) & (uint32_t)POSIF_PCONF_INSEL1_Msk) | + (((uint32_t)input2 << POSIF_PCONF_INSEL2_Pos) & (uint32_t)POSIF_PCONF_INSEL2_Msk)); + peripheral->PCONF = ((peripheral->PCONF & ~(uint32_t)XMC_POSIF_PCONF_INSEL_Msk) | reg); +} + +/* API to select an interrupt node */ +void XMC_POSIF_SetInterruptNode(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event, const XMC_POSIF_SR_ID_t sr) +{ + uint32_t reg; + + XMC_ASSERT("XMC_POSIF_SetInterruptNode:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_SetInterruptNode:Wrong IRQ event", (event <= XMC_POSIF_IRQ_EVENT_PCLK) ); + XMC_ASSERT("XMC_POSIF_SetInterruptNode:Wrong SR ID", (sr <= XMC_POSIF_SR_ID_1) ); + + reg = peripheral->PFLGE; + reg &= ~((uint32_t)1 << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos)); + reg |= (uint32_t)sr << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos); + peripheral->PFLGE = reg; +} +#endif /* #if defined(POSIF0) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_rtc.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_rtc.c new file mode 100644 index 00000000..6a115952 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_rtc.c @@ -0,0 +1,298 @@ +/** + * @file xmc_rtc.c + * @date 2015-05-19 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed GetDriverVersion API + * + * 2016-05-19: + * - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat() + * + * @endcond + * + */ + +/** + * + * @brief RTC driver for XMC microcontroller family. + * + */ + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_scu.h" +#include "xmc_rtc.h" + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ + +#define XMC_RTC_MAXSECONDS (59U) /**< RTC time : Maximum seconds */ +#define XMC_RTC_MAXMINUTES (59U) /**< RTC time : Maximum minutes */ +#define XMC_RTC_MAXHOURS (23U) /**< RTC time : Maximum hours */ +#define XMC_RTC_MAXDAYS (31U) /**< RTC time : Maximum days */ +#define XMC_RTC_MAXDAYSOFWEEK (7U) /**< RTC time : Maximum days of week */ +#define XMC_RTC_MAXMONTH (12U) /**< RTC time : Maximum month */ +#define XMC_RTC_MAXYEAR (0xFFFFU) /**< RTC time : Maximum year */ +#define XMC_RTC_MAXPRESCALER (0xFFFFU) /**< RTC time : Maximum prescaler */ +#define XMC_RTC_YEAR_OFFSET (1900U) /**< RTC year offset : Year offset */ + +#if (UC_FAMILY == XMC4) +#define XMC_RTC_INIT_SEQUENCE (1U) +#endif +#if (UC_FAMILY == XMC1) +#define XMC_RTC_INIT_SEQUENCE (0U) +#endif + +/********************************************************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ + +/* + * Enables RTC peripheral to start counting time + */ +void XMC_RTC_Start(void) +{ + while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->CTR |= (uint32_t)RTC_CTR_ENB_Msk; +} + +/* + * Disables RTC peripheral to start counting time + */ +void XMC_RTC_Stop(void) +{ + while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->CTR &= ~(uint32_t)RTC_CTR_ENB_Msk; +} + +/* + * Sets the RTC module prescaler value + */ +void XMC_RTC_SetPrescaler(uint16_t prescaler) +{ + XMC_ASSERT("XMC_RTC_SetPrescaler:Wrong prescaler value", (prescaler < XMC_RTC_MAXPRESCALER)); + + while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->CTR = (RTC->CTR & ~(uint32_t)RTC_CTR_DIV_Msk) | + ((uint32_t)prescaler << (uint32_t)RTC_CTR_DIV_Pos); +} + +/* + * Sets the RTC_TIM0, RTC_TIM1 registers with time values + */ +void XMC_RTC_SetTime(const XMC_RTC_TIME_t *const time) +{ + XMC_ASSERT("XMC_RTC_SetTime:Wrong seconds value", ((uint32_t)time->seconds < XMC_RTC_MAXSECONDS)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong minutes value", ((uint32_t)time->minutes < XMC_RTC_MAXMINUTES)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong hours value", ((uint32_t)time->hours < XMC_RTC_MAXHOURS)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong month day value", ((uint32_t)time->days < XMC_RTC_MAXDAYS)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong week day value", ((uint32_t)time->daysofweek < XMC_RTC_MAXDAYSOFWEEK)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong month value", ((uint32_t)time->month < XMC_RTC_MAXMONTH)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong year value", ((uint32_t)time->year < XMC_RTC_MAXYEAR)); + + #if (XMC_RTC_INIT_SEQUENCE == 1U) + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM0 = time->raw0; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM1 = time->raw1; + #endif + #if (XMC_RTC_INIT_SEQUENCE == 0U) + while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk)) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM0 = time->raw0; + RTC->TIM1 = time->raw1; ; + #endif +} + +/* + * Gets the RTC module time value + */ +void XMC_RTC_GetTime(XMC_RTC_TIME_t *const time) +{ + time->raw0 = RTC->TIM0; + time->raw1 = RTC->TIM1; +} + +/* + * Sets the RTC module time values in standard format + */ +void XMC_RTC_SetTimeStdFormat(const struct tm *const stdtime) +{ + + XMC_RTC_TIME_t time; + + time.seconds = stdtime->tm_sec; + time.minutes = stdtime->tm_min; + time.hours = stdtime->tm_hour; + time.days = stdtime->tm_mday - 1; + time.month = stdtime->tm_mon; + time.year = stdtime->tm_year + XMC_RTC_YEAR_OFFSET; + time.daysofweek = stdtime->tm_wday; + + XMC_RTC_SetTime(&time); +} + +/* + * Gets the RTC module time values in standard format + */ +void XMC_RTC_GetTimeStdFormat(struct tm *const stdtime) +{ + XMC_RTC_TIME_t time; + time.raw0 = RTC->TIM0; + time.raw1 = RTC->TIM1; + + stdtime->tm_sec = (int8_t)time.seconds; + stdtime->tm_min = (int8_t)time.minutes; + stdtime->tm_hour = (int8_t)time.hours; + stdtime->tm_mday = ((int8_t)time.days + (int8_t)1); + stdtime->tm_mon = (int8_t)time.month; + stdtime->tm_year = (int32_t)time.year - (int32_t)XMC_RTC_YEAR_OFFSET; + stdtime->tm_wday = (int8_t)time.daysofweek; +} + +/* + * Sets the RTC module alarm time value + */ +void XMC_RTC_SetAlarm(const XMC_RTC_ALARM_t *const alarm) +{ + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong seconds value", ((uint32_t)alarm->seconds < XMC_RTC_MAXSECONDS)); + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong minutes value", ((uint32_t)alarm->minutes < XMC_RTC_MAXMINUTES)); + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong hours value", ((uint32_t)alarm->hours < XMC_RTC_MAXHOURS)); + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong days value", ((uint32_t)alarm->days < XMC_RTC_MAXDAYS)); + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong month value", ((uint32_t)alarm->month < XMC_RTC_MAXMONTH)); + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong year value", ((uint32_t)alarm->year < XMC_RTC_MAXYEAR)); + + #if (XMC_RTC_INIT_SEQUENCE == 1U) + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM0 = alarm->raw0; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM1 = alarm->raw1; + #endif + #if (XMC_RTC_INIT_SEQUENCE == 0U) + while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk)) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM0 = alarm->raw0; + RTC->ATIM1 = alarm->raw1; + #endif +} + +/* + * Gets the RTC module alarm time value + */ +void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm) +{ + alarm->raw0 = RTC->ATIM0; + alarm->raw1 = RTC->ATIM1; +} + + +/* + * Sets the RTC module alarm time value in standard format + */ +void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime) +{ + XMC_RTC_ALARM_t alarm; + + + alarm.seconds = stdtime->tm_sec; + alarm.minutes = stdtime->tm_min; + alarm.hours = stdtime->tm_hour; + alarm.days = stdtime->tm_mday - 1; + alarm.month = stdtime->tm_mon; + alarm.year = stdtime->tm_year + XMC_RTC_YEAR_OFFSET; + + XMC_RTC_SetAlarm(&alarm); +} + +/* + * Gets the RTC module alarm time value in standard format + */ +void XMC_RTC_GetAlarmStdFormat(struct tm *const stdtime) +{ + XMC_RTC_ALARM_t alarm; + + alarm.raw0 = RTC->ATIM0; + alarm.raw1 = RTC->ATIM1; + + stdtime->tm_sec = (int8_t)alarm.seconds; + stdtime->tm_min = (int8_t)alarm.minutes; + stdtime->tm_hour = (int8_t)alarm.hours; + stdtime->tm_mday = ((int8_t)alarm.days + (int8_t)1); + stdtime->tm_mon = (int8_t)alarm.month; + stdtime->tm_year = (int32_t)alarm.year - (int32_t)XMC_RTC_YEAR_OFFSET; +} + +/* + * Gets the RTC periodic and alarm event(s) status + */ +uint32_t XMC_RTC_GetEventStatus(void) +{ + return RTC->STSSR; +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_sdmmc.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_sdmmc.c new file mode 100644 index 00000000..db99fdd7 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_sdmmc.c @@ -0,0 +1,350 @@ + +/** + * @file xmc_sdmmc.c + * @date 2016-07-11 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Removed GetDriverVersion API
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API
+ * + * 2016-03-14: + * - Values are directly assigned to the int status registers
+ * + * 2016-07-11: + * - XMC_SDMMC_SetDataTransferMode() shall not invoke SetDateLineTimeout()
+ * + * @endcond + */ + +/** + * @addtogroup XMClib + * @{ + */ + +/** + * @addtogroup SDMMC + * @brief SDMMC driver + * @{ + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_sdmmc.h" + +/* + * The SDMMC peripheral is only available on the + * XMC4500. The SDMMC definition can be found in + * the XMC4500.h (device header file). + */ +#if defined (SDMMC) +#include "xmc_scu.h" + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/* + * Check for valid SDMMC error events
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_ERROR_EVENT(e)\ + ((e == XMC_SDMMC_CMD_TIMEOUT_ERR) ||\ + (e == XMC_SDMMC_CMD_CRC_ERR) ||\ + (e == XMC_SDMMC_CMD_END_BIT_ERR) ||\ + (e == XMC_SDMMC_CMD_IND_ERR) ||\ + (e == XMC_SDMMC_DATA_TIMEOUT_ERR) ||\ + (e == XMC_SDMMC_DATA_CRC_ERR) ||\ + (e == XMC_SDMMC_DATA_END_BIT_ERR) ||\ + (e == XMC_SDMMC_CURRENT_LIMIT_ERR) ||\ + (e == XMC_SDMMC_ACMD_ERR) ||\ + (e == XMC_SDMMC_TARGET_RESP_ERR)) + +/* + * Check for valid SDMMC normal events
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_NORMAL_EVENT(e)\ + ((e == XMC_SDMMC_CMD_COMPLETE) ||\ + (e == XMC_SDMMC_TX_COMPLETE) ||\ + (e == XMC_SDMMC_BLOCK_GAP_EVENT) ||\ + (e == XMC_SDMMC_BUFFER_WRITE_READY) ||\ + (e == XMC_SDMMC_BUFFER_READ_READY) ||\ + (e == XMC_SDMMC_CARD_INS) ||\ + (e == XMC_SDMMC_CARD_REMOVAL) ||\ + (e == XMC_SDMMC_CARD_INT)) + +/* + * Check for both normal and error events
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_EVENT(e)\ + ((XMC_SDMMC_CHECK_NORMAL_EVENT(e)) ||\ + (XMC_SDMMC_CHECK_ERROR_EVENT(e))) + +/* + * Check for valid SDMMC wakeup events
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_WAKEUP_EVENT(w)\ + ((w == XMC_SDMMC_WAKEUP_EN_CARD_INT) ||\ + (w == XMC_SDMMC_WAKEUP_EN_CARD_INS) ||\ + (w == XMC_SDMMC_WAKEUP_EN_CARD_REM)) + +/* + * Check for valid SDMMC software reset modes
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_SW_RESET_MODE(m)\ + ((m == XMC_SDMMC_SW_RESET_ALL) ||\ + (m == XMC_SDMMC_SW_RST_CMD_LINE) ||\ + (m == XMC_SDMMC_SW_RST_DAT_LINE)) + +/* + * Check for valid SDMMC transfer modes
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_TRANSFER_MODE(m)\ + ((m == XMC_SDMMC_TRANSFER_MODE_TYPE_SINGLE) ||\ + (m == XMC_SDMMC_TRANSFER_MODE_TYPE_INFINITE) ||\ + (m == XMC_SDMMC_TRANSFER_MODE_TYPE_MULTIPLE) ||\ + (m == XMC_SDMMC_TRANSFER_MODE_TYPE_STOP_MULTIPLE)) + + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +/* Get power status of the SDMMC peripheral */ +bool XMC_SDMMC_GetPowerStatus(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetPowerStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (bool)(sdmmc->POWER_CTRL & SDMMC_POWER_CTRL_SD_BUS_POWER_Msk); +} + +/* + * De-assert the peripheral reset. The SDMMC peripheral + * needs to be initialized + */ +void XMC_SDMMC_Enable(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_Enable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_SDMMC); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_SDMMC); +#endif +} + +/* Assert the peripheral reset */ +void XMC_SDMMC_Disable(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_Disable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_SDMMC); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_SDMMC); +#endif +} + +/* Initialize SDMMC peripheral */ +XMC_SDMMC_STATUS_t XMC_SDMMC_Init(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_CONFIG_t *config) +{ + XMC_ASSERT("XMC_SDMMC_Init: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_Init: Invalid clock divider value", XMC_SDMMC_CHECK_SDCLK_FREQ(config->clock_divider)); + XMC_ASSERT("XMC_SDMMC_Init: Invalid bus width", XMC_SDMMC_CHECK_DATA_LINES(config->bus_width)); + + /* Enable SDMMC peripheral */ + XMC_SDMMC_Enable(sdmmc); + + /* Write internal clock divider register */ + sdmmc->CLOCK_CTRL |= (uint16_t)((uint32_t)config->clock_divider << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos); + + /* Set bus width */ + sdmmc->HOST_CTRL = (uint8_t)((sdmmc->HOST_CTRL & (uint8_t)~SDMMC_HOST_CTRL_DATA_TX_WIDTH_Msk) | + ((uint8_t)config->bus_width << SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos)); + + return XMC_SDMMC_STATUS_SUCCESS; +} + +/* Enable event status */ +void XMC_SDMMC_EnableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_EnableEventStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + /* Set INT status enable register */ + sdmmc->EN_INT_STATUS_NORM |= (uint16_t)event; + sdmmc->EN_INT_STATUS_ERR |= (uint16_t)(event >> 16U); +} + +/* Disable event status */ +void XMC_SDMMC_DisableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_DisableEventStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + /* Clear INT status enable register */ + sdmmc->EN_INT_STATUS_NORM &= (uint16_t)~event; + sdmmc->EN_INT_STATUS_ERR &= (uint16_t)~(event >> 16U); +} + +/* Enable SDMMC event */ +void XMC_SDMMC_EnableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_EnableEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + XMC_SDMMC_EnableEventStatus(sdmmc, event); + + sdmmc->EN_INT_SIGNAL_NORM |= (uint16_t)event; + sdmmc->EN_INT_SIGNAL_ERR |= (uint16_t)(event >> 16U); +} + +/* Disable SDMMC event without disabling event status */ +void XMC_SDMMC_DisableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_DisableEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + /* Clear INT signal enable register */ + sdmmc->EN_INT_SIGNAL_NORM &= (uint16_t)~event; + sdmmc->EN_INT_SIGNAL_ERR &= (uint16_t)~(event >> 16U); +} + +/* Clear SDMMC event(s) */ +void XMC_SDMMC_ClearEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_ClearEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_ClearEvent: Invalid bit-field", !(event & XMC_SDMMC_TARGET_RESP_ERR)); + + sdmmc->INT_STATUS_NORM = (uint16_t)event; + sdmmc->INT_STATUS_ERR = (uint16_t)(event >> 16U); +} + +/* Get the status of an SDMMC event */ +bool XMC_SDMMC_GetEvent(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_EVENT_t event) +{ + bool status; + + XMC_ASSERT("XMC_SDMMC_GetEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_GetEvent: Invalid SDMMC event", XMC_SDMMC_CHECK_EVENT(event)); + + if (event < XMC_SDMMC_CMD_TIMEOUT_ERR) + { + status = (bool)(sdmmc->INT_STATUS_NORM & (uint16_t)event); + } + else + { + status = (bool)(sdmmc->INT_STATUS_ERR & (uint16_t)((uint32_t)event >> 16U)); + } + + return status; +} + +/* Read R2 response (CID, CSD register) */ +void XMC_SDMMC_GetR2Response(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_RESPONSE_t *const response) +{ + XMC_ASSERT("XMC_SDMMC_GetR2Response: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + response->response_0 = sdmmc->RESPONSE[0]; + response->response_2 = sdmmc->RESPONSE[1]; + response->response_4 = sdmmc->RESPONSE[2]; + response->response_6 = sdmmc->RESPONSE[3]; +} + +/* Send SDMMC command */ +XMC_SDMMC_STATUS_t XMC_SDMMC_SendCommand(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_COMMAND_t *cmd, uint32_t arg) +{ + XMC_ASSERT("XMC_SDMMC_SendCommand: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->ARGUMENT1 = arg; + sdmmc->COMMAND = (uint16_t)(*(uint16_t *)cmd); + + return XMC_SDMMC_STATUS_SUCCESS; +} + +/* Set data transfer mode */ +void XMC_SDMMC_SetDataTransferMode(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_TRANSFER_MODE_t *const response) +{ + XMC_ASSERT("XMC_SDMMC_SetDataTransferMode: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetDataTransferMode: Invalid transfer type", XMC_SDMMC_CHECK_TRANSFER_MODE(response->type)); + + /* Block size */ + sdmmc->BLOCK_SIZE = (uint16_t)(response->block_size); + + /* Number of blocks */ + sdmmc->BLOCK_COUNT = (uint16_t)(response->num_blocks); + + /* Type of data transfer: single, infinite, multiple or stop multiple */ + sdmmc->TRANSFER_MODE = (uint16_t)((sdmmc->TRANSFER_MODE & (uint16_t)~SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Msk) | + ((uint16_t)response->type)); + + /* + * Clear block count enable bit; that's only valid for + * a multi-block transfer + */ + if (response->type == XMC_SDMMC_TRANSFER_MODE_TYPE_SINGLE) + { + sdmmc->TRANSFER_MODE &= (uint16_t)~SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Msk; + } + + /* Auto CMD configuration */ + sdmmc->TRANSFER_MODE = (uint16_t)((sdmmc->TRANSFER_MODE & (uint16_t)~SDMMC_TRANSFER_MODE_ACMD_EN_Msk) | + ((uint16_t)response->auto_cmd << SDMMC_TRANSFER_MODE_ACMD_EN_Pos)); +} + +#endif /* #if defined (SDMMC) */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_spi.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_spi.c new file mode 100644 index 00000000..8d324a32 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_spi.c @@ -0,0 +1,279 @@ +/** + * @file xmc_spi.c + * @date 2015-11-04 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - Modified XMC_SPI_CH_Stop() API for not setting to IDLE the channel if it is busy + * - Modified XMC_SPI_CH_SetInterwordDelay() implementation in order to gain accuracy
+ * + * 2015-06-20: + * - Removed GetDriverVersion API
+ * + * 2015-09-01: + * - Modified XMC_SPI_CH_EnableEvent() and XMC_SPI_CH_DisableEvent() for supporting multiple events configuration
+ * + * 2015-11-04: + * - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_SPI_CH_Transmit() flag
+ * @endcond + * + */ +/** + * + * @brief SPI driver for XMC microcontroller family + * + */ +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include +#include + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_SPI_CH_OVERSAMPLING (2UL) + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/* Initializes the selected SPI channel with the config structure. */ +void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config) +{ + XMC_USIC_CH_Enable(channel); + + if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER) + { + /* Configure baud rate */ + (void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, XMC_SPI_CH_OVERSAMPLING); + } + + /* Configuration of USIC Shift Control */ + /* Transmission Mode (TRM) = 1 */ + /* Passive Data Level (PDL) = 1 */ + channel->SCTR = USIC_CH_SCTR_PDL_Msk | + (0x1UL << USIC_CH_SCTR_TRM_Pos) | + (0x3fUL << USIC_CH_SCTR_FLE_Pos)| + (0x7UL << USIC_CH_SCTR_WLE_Pos); + + /* Configuration of USIC Transmit Control/Status Register */ + /* TBUF Data Enable (TDEN) = 1 */ + /* TBUF Data Single Shot Mode (TDSSM) = 1 */ + channel->TCSR = (uint32_t)(USIC_CH_TCSR_HPCMD_Msk | + (0x01UL << USIC_CH_TCSR_TDEN_Pos) | + USIC_CH_TCSR_TDSSM_Msk); + + if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER) + { + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode = (uint32_t)(USIC_CH_PCR_SSCMode_MSLSEN_Msk | + USIC_CH_PCR_SSCMode_SELCTR_Msk | + (uint32_t)config->selo_inversion | + USIC_CH_PCR_SSCMode_FEM_Msk); + } + + /* Clear protocol status */ + channel->PSCR = 0xFFFFFFFFUL; + + /* Set parity settings */ + channel->CCR = (uint32_t)config->parity_mode; +} + +XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate) +{ + XMC_SPI_CH_STATUS_t status; + + status = XMC_SPI_CH_STATUS_ERROR; + + if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U)) + { + if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_SPI_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK) + { + status = XMC_SPI_CH_STATUS_OK; + } + } + return status; +} + +/* Enable the selected slave signal by setting (SELO) bits in PCR register. */ +void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SELECT_t slave) +{ + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SELO_Msk; + channel->PCR_SSCMode |= (uint32_t)slave; +} + +/* Disable the slave signals by clearing (SELO) bits in PCR register. */ +void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel) +{ + XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_MSLS); + + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SELO_Msk; +} + +/* Puts the data into FIFO if FIFO mode is enabled or else into standard buffers, by setting the proper mode. */ +void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_SPI_CH_MODE_t mode) +{ + + channel->CCR = (channel->CCR & (uint32_t)(~USIC_CH_CCR_HPCEN_Msk)) | + (((uint32_t) mode << USIC_CH_CCR_HPCEN_Pos) & (uint32_t)USIC_CH_CCR_HPCEN_Msk); + + + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) + { + } + + XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[mode] = data; + } + else + { + channel->IN[mode] = data; + } +} + +/* Reads the data from the buffers based on the FIFO mode selection. */ +uint16_t XMC_SPI_CH_GetReceivedData(XMC_USIC_CH_t *const channel) +{ + uint16_t retval; + + /* Check FIFO size */ + if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U) + { + retval = (uint16_t)channel->RBUF; + } + else + { + retval = (uint16_t)channel->OUTR; + } + + return retval; +} + +/* Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields. */ +void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterword_delay_us) +{ + uint32_t peripheral_clock; + uint32_t pdiv; + uint32_t step; + uint32_t fFD; + uint32_t fpdiv; + uint32_t divider_factor1 = 0U; + uint32_t divider_factor2 = 32U; + uint32_t divider_factor1_int = 0U; + uint32_t divider_factor1_int_min = 4U; + uint32_t divider_factor1_frac_min =100U; + uint32_t divider_factor1_frac = 0U; + uint32_t divider_factor2_temp = 0U; + peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + pdiv = (uint32_t)(channel->BRG & USIC_CH_BRG_PDIV_Msk) >> USIC_CH_BRG_PDIV_Pos; + step = (uint32_t)(channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos; + fFD = (uint32_t)((peripheral_clock >> 10U) * step); + fpdiv= fFD/(1U+pdiv); + + if(tinterword_delay_us < (128000000/fpdiv)) + { + for(divider_factor2_temp = 32U; divider_factor2_temp > 0U; --divider_factor2_temp) + { + + divider_factor1 = (tinterword_delay_us*fpdiv)/(divider_factor2_temp*10000); + divider_factor1_frac = divider_factor1%100U; + + if(divider_factor1_frac > 50) + { + divider_factor1_int = (divider_factor1/100U)+1; + divider_factor1_frac = (divider_factor1_int*100)-divider_factor1; + } + else + { + divider_factor1_int = (divider_factor1/100U); + } + + if ((divider_factor1_int < 5U) && (divider_factor1_int > 0) && (divider_factor1_frac < divider_factor1_frac_min)) + { + divider_factor1_frac_min = divider_factor1_frac; + divider_factor1_int_min = divider_factor1_int; + divider_factor2= divider_factor2_temp; + } + } + } + + channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode) & (~(USIC_CH_PCR_SSCMode_DCTQ1_Msk | + USIC_CH_PCR_SSCMode_PCTQ1_Msk | + USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) | + (((divider_factor1_int_min - 1) << USIC_CH_PCR_SSCMode_PCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_PCTQ1_Msk) | + (((divider_factor2 - 1 ) << USIC_CH_PCR_SSCMode_DCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_DCTQ1_Msk); +} + +XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel) +{ + XMC_SPI_CH_STATUS_t status = XMC_SPI_CH_STATUS_OK; + + if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) + { + status = XMC_SPI_CH_STATUS_BUSY; + } + else + { + + /* USIC channel in IDLE mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE); + } + + return status; +} + +void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR |= (event&0x1fc00U); + channel->PCR_SSCMode |= ((event << 13U) & 0xe000U); +} + +void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR &= (uint32_t)~(event&0x1fc00U); + channel->PCR_SSCMode &= (uint32_t)~((event << 13U) & 0xe000U); +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_uart.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_uart.c new file mode 100644 index 00000000..3641315a --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_uart.c @@ -0,0 +1,216 @@ +/** + * @file xmc_uart.c + * @date 2016-07-22 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - xmc_uart_ch_stop API implementation corrected. + * - Modified XMC_UART_CH_Stop() API for not setting to IDLE the channel if it is busy
+ * + * 2015-06-20: + * - Removed GetDriverVersion API
+ * + * 2015-09-01: + * - Modified XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent() for supporting multiple events configuration
+ * + * 2016-07-22: + * - Modified XMC_UART_CH_Init() to enable transfer status BUSY + * - Modified XMC_UART_CH_Stop() to check for transfer status + * + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ + +#include +#include + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ + +#define XMC_UART_CH_OVERSAMPLING (16UL) +#define XMC_UART_CH_OVERSAMPLING_MIN_VAL (4UL) + +/********************************************************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ + +void XMC_UART_CH_Init(XMC_USIC_CH_t *channel, const XMC_UART_CH_CONFIG_t *const config) +{ + uint32_t oversampling = XMC_UART_CH_OVERSAMPLING; + + /* USIC channel switched on*/ + XMC_USIC_CH_Enable(channel); + + if(config->oversampling != 0U) + { + oversampling = (uint32_t)config->oversampling; + } + + /* Configure baud rate */ + (void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, oversampling); + + /* Configure frame format + * Configure the number of stop bits + * Pulse length is set to 0 to have standard UART signaling, + * i.e. the 0 level is signaled during the complete bit time + * Sampling point set equal to the half of the oversampling period + * Enable Sample Majority Decision + * Enable Transfer Status BUSY + */ + channel->PCR_ASCMode = (uint32_t)(((config->stop_bits - 1UL) << USIC_CH_PCR_ASCMode_STPB_Pos) | + (((oversampling >> 1UL) + 1UL) << USIC_CH_PCR_ASCMode_SP_Pos) | + USIC_CH_PCR_ASCMode_SMD_Msk | + USIC_CH_PCR_ASCMode_RSTEN_Msk | USIC_CH_PCR_ASCMode_TSTEN_Msk); + + /* Set passive data level, high + Set word length. Data bits - 1 + If frame length is > 0, frame_lemgth-1; else, FLE = WLE (Data bits - 1) + Transmission Mode: The shift control signal is considered active if it + is at 1-level. This is the setting to be programmed to allow data transfers */ + channel->SCTR = (uint32_t)((((uint32_t)config->data_bits - 1UL) << USIC_CH_SCTR_WLE_Pos) | + ((0x1UL << USIC_CH_SCTR_TRM_Pos) | USIC_CH_SCTR_PDL_Msk)); + + if (config->frame_length != 0U) + { + channel->SCTR |= (uint32_t)(((uint32_t)config->frame_length - 1UL) << USIC_CH_SCTR_FLE_Pos); + } + else + { + channel->SCTR |= (uint32_t)(((uint32_t)config->data_bits - 1UL) << USIC_CH_SCTR_FLE_Pos); + } + + /* Enable transfer buffer */ + channel->TCSR = (0x1UL << USIC_CH_TCSR_TDEN_Pos) | + USIC_CH_TCSR_TDSSM_Msk; + + /* Clear protocol status */ + channel->PSCR = 0xFFFFFFFFUL; + + /* Set parity settings */ + channel->CCR = (uint32_t)config->parity_mode; +} + +XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling) +{ + XMC_UART_CH_STATUS_t status; + + status = XMC_UART_CH_STATUS_ERROR; + + if ((rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 2U)) && (oversampling >= XMC_UART_CH_OVERSAMPLING_MIN_VAL)) + { + if (XMC_USIC_CH_SetBaudrate(channel, rate, oversampling) == XMC_USIC_CH_STATUS_OK) + { + status = XMC_UART_CH_STATUS_OK; + } + } + return status; +} + +void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0UL) + { + /* Wait till the Transmit Buffer is free for transmission */ + while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + } + + /* Clear the Transmit Buffer indication flag */ + XMC_UART_CH_ClearStatusFlag(channel, (uint32_t)XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + /*Transmit data */ + channel->TBUF[0U] = data; + } + else + { + channel->IN[0U] = data; + } +} + +uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel) +{ + uint16_t retval; + + /* Check FIFO size */ + if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U) + { + retval = (uint16_t)channel->RBUF; + } + else + { + retval = (uint16_t)channel->OUTR; + } + + return retval; +} + +XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel) +{ + XMC_UART_CH_STATUS_t status = XMC_UART_CH_STATUS_OK; + + if (((XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t) XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) || + ((XMC_UART_CH_GetStatusFlag(channel) & XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY) != 0)) + { + status = XMC_UART_CH_STATUS_BUSY; + } + else + { + /* USIC channel in IDLE mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE); + } + return status; +} + +void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR |= (event&0x1fc00U); + channel->PCR_ASCMode |= (event&0xf8U); +} + +void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR &= (uint32_t)~(event&0x1fc00U); + channel->PCR_ASCMode &= (uint32_t)~(event&0xf8U); +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_usbd.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_usbd.c new file mode 100644 index 00000000..e2e977db --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_usbd.c @@ -0,0 +1,1627 @@ +/** + * @file xmc_usbd.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-16: + * - Initial Version.
+ * 2015-03-18: + * - Updated the XMC_USBD_EndpointStall() to fix issue on USB clear stall.
+ * - Updated the XMC_USBD_EndpointConfigure() to fix issue in EP0 configuration.
+ * - Updated the XMC_USBD_IRQHandler()(Removed the DAVE_CE check on SOF event).
+ * 2015-06-20: + * - Removed GetDriverVersion API.
+ * - Updated the XMC_USBD_IsEnumDone() API.
+ * - Updated the copy right in the file header.
+ * - Updated the XMC_USBD_Disable() API to gate the clock after programming the SCU registers.
+ * + * @endcond + * + */ + + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#include + +#if defined(USB0) + +/**< macro to check the maximum number of endpoints used*/ +#define XMC_USBD_CHECK_INPUT_MAX_NUM_EPS(usbd_max_num_eps) \ + ((usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_1 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_2 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_3 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_4 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_5 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_6 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_7 )) + +/******************************************************************************* + *GLOBAL DATA + *******************************************************************************/ +/* + * Endpoint Out Fifo Size + */ +uint32_t XMC_USBD_EP_OUT_BUFFERSIZE[7] = {0U,0U,0U,0U,0U,0U,0U}; +/* + * Endpoint In Fifo Size + */ +uint32_t XMC_USBD_EP_IN_BUFFERSIZE[7] = {0U,0U,0U,0U,0U,0U,0U}; +/* + * Device definition + */ + XMC_USBD_DEVICE_t xmc_device; +#ifdef __GNUC__ /*GCC*/ +/* + * Endpoint Out Fifo + */ +static __attribute__((aligned(4))) uint8_t XMC_USBD_EP_OUT_BUFFER[7][256] __attribute__((section("USB_RAM"))); +/* + * Endpoint In Fifo + */ +static __attribute__((aligned(4))) uint8_t XMC_USBD_EP_IN_BUFFER[7][256] __attribute__((section("USB_RAM"))); +#endif +#if defined(__ICCARM__) +#pragma data_alignment=4 +/* + * Endpoint Out Fifo + */ +static uint8_t XMC_USBD_EP_OUT_BUFFER[7][256] @ ".dram"; +/* + * Endpoint In Fifo + */ +#pragma data_alignment=4 +static uint8_t XMC_USBD_EP_IN_BUFFER[7][256] @ ".dram"; +#endif +#if defined(__CC_ARM) +/* + * Endpoint Out Fifo + */ +static __attribute__((aligned(4))) uint8_t XMC_USBD_EP_OUT_BUFFER[7][256] __attribute__((section ("RW_IRAM1"))); +/* + * Endpoint In Fifo + */ +static __attribute__((aligned(4))) uint8_t XMC_USBD_EP_IN_BUFFER[7][256] __attribute__((section ("RW_IRAM1"))); +#endif +XMC_USBD_t *usbd_init; + +/******************************************************************************* + *LOCAL ROUTINES + *******************************************************************************/ +/*Local routines prototypes*/ +uint8_t XMC_USBD_lDeviceActive(const XMC_USBD_t *const obj); +static void XMC_USBD_lReadFifo(const uint32_t ep_num,const uint32_t byte_count); +static uint32_t XMC_USBD_lWriteFifo(XMC_USBD_EP_t *ep); +static void XMC_USBD_lFlushTXFifo(const uint8_t fifo_num); +static void XMC_USBD_lFlushRXFifo(void); +static uint8_t XMC_USBD_lAssignTXFifo(void); +static void XMC_USBD_lStartReadXfer(XMC_USBD_EP_t *const ep); +static void XMC_USBD_lStartWriteXfer(XMC_USBD_EP_t *const ep); +static void XMC_USBD_lHandleEnumDone(void); +static void XMC_USBD_lHandleOEPInt(const XMC_USBD_t *const obj); +static void XMC_USBD_lHandleRxFLvl(void); +static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj); +static void XMC_USBD_lUnassignFifo(const uint8_t fifo_nr); +static void XMC_USBD_lHandleUSBReset(const XMC_USBD_t *const obj); +static void XMC_USBD_lHandleOTGInt(void); +static void XMC_USBD_lClearEventOTG(uint32_t event); + +/** + * The device driver + */ +const XMC_USBD_DRIVER_t Driver_USBD0 = +{ + .GetCapabilities = XMC_USBD_GetCapabilities, + .Initialize = XMC_USBD_Init, + .Uninitialize = XMC_USBD_Uninitialize, + .DeviceConnect = XMC_USBD_DeviceConnect, + .DeviceDisconnect = XMC_USBD_DeviceDisconnect, + .DeviceGetState = XMC_USBD_DeviceGetState, + .DeviceSetAddress = XMC_USBD_DeviceSetAddress, + .EndpointConfigure = XMC_USBD_EndpointConfigure, + .EndpointUnconfigure = XMC_USBD_EndpointUnconfigure, + .EndpointStall = XMC_USBD_EndpointStall, + .EndpointReadStart = XMC_USBD_EndpointReadStart, + .EndpointRead = XMC_USBD_EndpointRead, + .EndpointWrite = XMC_USBD_EndpointWrite, + .EndpointAbort = XMC_USBD_EndpointAbort, + .GetFrameNumber = XMC_USBD_GetFrameNumber, + .IsEnumDone = XMC_USBD_IsEnumDone +}; + +/** + * @brief Checks if device is active + * + * Therefore the endpoint inInUse flag are checked and if one endpoint is in use, 1 is returned, + * else 0 is returned. + * @return 1 if an endpoint is active else 0 + */ +uint8_t XMC_USBD_lDeviceActive(const XMC_USBD_t *const obj) +{ + uint8_t i; + uint8_t result = 0U; + for (i = 0U; i < (uint8_t)obj->usbd_max_num_eps; i++) + { + if (xmc_device.ep[i].inInUse || xmc_device.ep[i].outInUse) + { + result = 1U; + } + } + return result; +} + + +/** + * @brief Read data from the rx fifo + * + * The data from the fifo is copied in to the buffer specified by @ref xfer_buffer and + * the transfer values get updated. If the endpoint is disabled or the buffer not existent + * the function exits. + * + * @arg ep_num the endpoint to read for + * @arg byte_count the byte count to read + */ +static void XMC_USBD_lReadFifo(const uint32_t ep_num,const uint32_t byte_count) +{ + XMC_USBD_EP_t * ep = &xmc_device.ep[ep_num]; + uint32_t word_count; + uint32_t temp_data; + uint32_t temp_word_count; + volatile uint32_t *fifo = xmc_device.fifo[0U]; + uint32_t i; + depctl_data_t data; + data.d32 = xmc_device.endpoint_out_register[ep_num]->doepctl; + word_count = (byte_count >> 2U ); + temp_word_count = (word_count << 2U); + /* Check if ep is enabled and has buffer */ + if (!data.b.usbactep) + { + /*Do Nothing*/ + } + else if (ep->xferBuffer == NULL) + { + /*Do Nothing*/ + } + else + { + /* store the data */ + for (i = 0U;i < word_count; i++) + { + *(((uint32_t*)ep->xferBuffer)+i) = *fifo; + } + /* space is not devidable by 4 */ + if (byte_count!=temp_word_count) + { + temp_data = *fifo; + for (i = 0U;(temp_word_count + i) < byte_count;i++) + { + ep->xferBuffer[(word_count << 2)+i] = (uint8_t)((temp_data & ((uint32_t)0xFFU << (i * 8U))) >> (i * 8U)); + } + } + + /* save the amount of data */ + ep->xferCount += byte_count; + ep->xferBuffer += byte_count; + } +} + +/** + * @brief Write data to an endpoint fifo + * + * The data from the @ref xfer_buffer gets copied in to the tx fifo of the endpoint until the buffer has been read + *completely or the tx fifo is full. The transfer values are not updated. + * + * @arg[in] ep the endpoint to use + * @return the number of bytes written to the fifo + */ +static uint32_t XMC_USBD_lWriteFifo(XMC_USBD_EP_t *const ep) +{ + dtxfsts_data_t freeSpace; + volatile uint32_t *fifo; + uint32_t byte_count; + uint32_t word_count; + uint32_t result; + uint32_t i; + fifo = xmc_device.fifo[ep->address_u.address_st.number]; /* fifo */ + freeSpace.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->dtxfsts; + /* calculate the length and the amount of dwords to copy based on the fifo status */ + byte_count = ep->xferLength - ep->xferCount; + if (!byte_count) + { + result = 0U; + } + else + { + /* add the unaligned bytes to the word count to compare with the fifo space */ + word_count = ((uint32_t)byte_count + 3U) >> 2U; + if (word_count > (uint32_t)freeSpace.b.txfspcavail ) + { + word_count = (uint32_t)freeSpace.b.txfspcavail; + byte_count = (uint32_t)word_count << (uint32_t)2U; + } + + /* copy data dword wise */ + for (i = 0U; i < word_count;ep->xferBuffer+= 4U) + { + *fifo = *(uint32_t*)ep->xferBuffer; + i++; + } + result=byte_count; + } + return result; +} + +/** + * @brief Flush a tx fifo + * + * @param[in] fifo_num Fifo number to flush + * + * @note Use 0x10 as parameter to flush all tx fifos. + */ +static void XMC_USBD_lFlushTXFifo(const uint8_t fifo_num) +{ + volatile grstctl_t data; + uint32_t count; + data.d32 = 0U; + /*flush fifo */ + data.b.txfflsh = 1U; + data.b.txfnum = fifo_num; + xmc_device.global_register->grstctl = data.d32; + for (count = 0U;count < 1000U; count++){} + do + { + data.d32 = xmc_device.global_register->grstctl; + } while (data.b.txfflsh); + count = 0U; + while (count++ < 1000U) + { + /* wait 3 phy clocks */ + } +} + +/** + * @brief Flush the rx fifo + */ +static void XMC_USBD_lFlushRXFifo(void) +{ + volatile grstctl_t data; + uint32_t count; + + data.d32 = 0U; + data.b.rxfflsh = 1U; + /* flush FIFO */ + xmc_device.global_register->grstctl = data.d32; + do + { + for (count = 0U; count < 1000U; count++){} + data.d32 = xmc_device.global_register->grstctl; + } while (data.b.rxfflsh); + count = 0U; + while (count++ < 1000U) + { + /* wait 3 phy clocks */ + } +} + +/* + * Support Functions + */ + +/** + * @brief Assign a free tx fifo + * + * A free tx fifo will be searched and the number will be returned. + * + * @return Fifo number for a free fifo + */ +static uint8_t XMC_USBD_lAssignTXFifo(void) +{ + uint16_t mask = 1U; + uint8_t i = 0U; + uint8_t result = 0U; + while( (i < (uint8_t)XMC_USBD_NUM_TX_FIFOS)&&((xmc_device.txfifomsk & mask) != 0U)) + { + mask = (uint16_t)(mask << 1U); + i++; + } + if ((xmc_device.txfifomsk & mask) == 0U) + { + xmc_device.txfifomsk |= mask; + result=i; + } + return result; +} + +/** + * @brief Free a tx fifo + * + * Mark an used tx fifo as free. + * @param[in] fifo_nr Fifo number to free + */ +static void XMC_USBD_lUnassignFifo(const uint8_t fifo_nr) +{ + xmc_device.txfifomsk = (uint16_t)((uint32_t)xmc_device.txfifomsk & (uint32_t)(~((uint32_t)((uint32_t)1U << fifo_nr)))); +} + +/** + * @brief Start a transfer for an out endpoint + * + * Based on the transfer values of the endpoint, the out endpoint registers will be programmed + * to start a new out transfer. + * + * @note No checking of the transfer values are done in this function. Be sure, + * that the transfer values are reasonable (e.g. buffer size is not exceeded). + * + * @param[in] ep Endpoint to start the transfer + */ +static void XMC_USBD_lStartReadXfer(XMC_USBD_EP_t *const ep) +{ + deptsiz_data_t data; + depctl_data_t epctl; + + data.d32 = 0U; + if ((ep->xferTotal - ep->xferLength) > ep->maxTransferSize) + { + ep->xferLength += ep->maxTransferSize; + } + else + { + ep->xferLength = ep->xferTotal; + } + if (ep->address_u.address_st.number == 0U) + { + /* Setup the endpoint to receive 3 setup packages and one normal package.*/ + /* Cast the data pointer to use only one variable */ + deptsiz0_data_t *ep0_data = (deptsiz0_data_t*)&data; + ep0_data->b.pktcnt = 0x1U; + ep0_data->b.supcnt = 0x3U; + ep0_data->b.xfersize = (uint8_t)ep->xferTotal; + } + else + { + /* If requested length is zero, just receive one zero length packet */ + if (ep->xferLength == 0U) + { + data.b.xfersize = 0U; + data.b.pktcnt = 1U; + } + else + { + /* setup endpoint to recive a amount of packages by given size */ + data.b.pktcnt = (uint16_t)(((ep->xferLength - ep->xferCount) + (ep->maxPacketSize -(uint32_t)1U))/ep->maxPacketSize); + data.b.xfersize =(uint32_t)(ep->xferLength - ep->xferCount); + } + } + if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + /* Programm dma address if needed */ + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepdma = (uint32_t)(ep->xferBuffer); + } + /* setup endpoint size and enable endpoint */ + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doeptsiz = data.d32; + + epctl.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; + epctl.b.cnak = 1U; + epctl.b.epena = 1U; + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = epctl.d32; +} + +/** + * @brief Start a new in transfer + * + * Based on the transfer values of the endpoint the in endpoint registers will be programmed + * to start a new in transfer + * + * @param[in] ep Endpoint to start the transfer + */ +static void XMC_USBD_lStartWriteXfer(XMC_USBD_EP_t *const ep) +{ + deptsiz_data_t size; + depctl_data_t ctl; + + size.d32 = 0U; + ctl.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; + + if ((ep->xferTotal - ep->xferLength) < ep->maxTransferSize) + { + ep->xferLength = ep->xferTotal; + } + else + { + ep->xferLength += ep->maxTransferSize; + } + if (ep->xferLength == 0U) + { + size.b.xfersize = 0U; + size.b.pktcnt = 1U; + } + else + { + if (ep->address_u.address_st.number == 0U) + { + size.b.pktcnt = 1U; + /* ep->maxXferSize equals maxPacketSize */ + size.b.xfersize = (uint32_t)(ep->xferLength - ep->xferCount); + } + else + { + size.b.xfersize =(uint32_t)(ep->xferLength - ep->xferCount); + size.b.pktcnt = (uint16_t)(((uint16_t)(ep->xferLength - ep->xferCount) + (uint16_t)((uint16_t)ep->maxPacketSize - 1U))/ + ep->maxPacketSize); + } + if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + /* Program dma*/ + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepdma = (uint32_t)ep->xferBuffer; + } + if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + /* enable fifo empty interrupt */ + xmc_device.device_register->dtknqr4_fifoemptymsk |= (uint32_t)((uint32_t)1U << (uint8_t)ep->address_u.address_st.number); + } + } + + /* Program size of transfer and enable endpoint */ + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->dieptsiz = size.d32; + ctl.b.epena = 1U; + ctl.b.cnak = 1U; + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = ctl.d32; +} + + +/** + * @brief Handles the USBD reset interrupt + * + * When ever the host sets the bus into reset condition the usb otg_core generates + * an interrupt, which is handled by this function. It resets the complete otg_core + * into the default state. + */ +static void XMC_USBD_lHandleUSBReset(const XMC_USBD_t *const obj) +{ + uint32_t i; + depctl_data_t epctl; + dctl_data_t dctl; + fifosize_data_t gnptxfsiz; + daint_data_t daint; + dcfg_data_t dcfg; + + /* Clear the Remote Wakeup Signaling */ + dctl.d32 = xmc_device.device_register->dctl; + dctl.b.rmtwkupsig = 1U; + xmc_device.device_register->dctl = dctl.d32; + + /* enable naks for all eps */ + for (i = 0U;i < (uint8_t)XMC_USBD_NUM_EPS;i++) + { + epctl.d32 = xmc_device.endpoint_out_register[i]->doepctl; + epctl.b.snak = 1U; + epctl.b.stall = 0U; + xmc_device.endpoint_out_register[i]->doepctl = epctl.d32; + } + + /* Configure fifos */ + /* Calculate the size of the rx fifo */ + xmc_device.global_register->grxfsiz = 64U; + /* Calculate the size of the tx fifo for ep 0 */ + gnptxfsiz.d32 = 0U; + gnptxfsiz.b.depth = 16U; + gnptxfsiz.b.startaddr = 64U; + xmc_device.global_register->gnptxfsiz = gnptxfsiz.d32; + /* calculate the size for the rest */ + for (i = 1U;i < (uint8_t)XMC_USBD_NUM_TX_FIFOS;i++) + { + xmc_device.global_register->dtxfsiz[i- 1U] = (uint32_t)(((256U + (i*(64U)))/4U) | ((uint32_t)16U << 16U)); + } + + /* flush the fifos for proper operation */ + XMC_USBD_lFlushTXFifo(0x10U); /* 0x10 == all fifos, see doc */ + XMC_USBD_lFlushTXFifo(0x0U); + XMC_USBD_lFlushRXFifo(); + /* Flush learning queue not needed due to fifo config */ + /* enable ep0 interrupts */ + daint.d32 = 0U; + daint.b.inep0 = 1U; + daint.b.outep0 = 1U; + xmc_device.device_register->daintmsk = daint.d32; + + /* enable endpoint interrupts */ + /* out ep interrupts */ + XMC_USBD_EnableEventOUTEP(((uint32_t)XMC_USBD_EVENT_OUT_EP_TX_COMPLET | (uint32_t)XMC_USBD_EVENT_OUT_EP_DISABLED | + (uint32_t)XMC_USBD_EVENT_OUT_EP_SETUP | (uint32_t)XMC_USBD_EVENT_OUT_EP_AHB_ERROR)); + + /*in ep interrupts */ + XMC_USBD_EnableEventINEP(((uint32_t)XMC_USBD_EVENT_IN_EP_TX_COMPLET | (uint32_t)XMC_USBD_EVENT_IN_EP_DISABLED | + (uint32_t)XMC_USBD_EVENT_IN_EP_AHB_ERROR | (uint32_t)XMC_USBD_EVENT_IN_EP_TIMEOUT)); + + + /* Clear device Address */ + dcfg.d32 = xmc_device.device_register->dcfg; + dcfg.b.devaddr = 0U; + xmc_device.device_register->dcfg = dcfg.d32; + + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + /* Clear Empty interrupt */ + xmc_device.device_register->dtknqr4_fifoemptymsk = 0U; + } + + xmc_device.ep[0U].outInUse = 0U; + xmc_device.ep[0U].inInUse = 0U; + + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_RESET); + + /* clear reset intr */ + XMC_USBD_ClearEvent(XMC_USBD_EVENT_RESET); +} + +/** +* @brief Handle OTG Interrupt +* +* It detects especially connect and disconnect events. +*/ +static void XMC_USBD_lHandleOTGInt(void) +{ + gotgint_data_t data; + data.d32 = xmc_device.global_register->gotgint; + if (data.b.sesenddet) + { + xmc_device.IsPowered = 0U; + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_POWER_OFF); + } + XMC_USBD_lClearEventOTG(data.d32); + +} + +/** + * @brief Interrupt handler for device enumeration done. + * + * Handles the enumeration done from dwc_otg, when the host has enumerated the device. + */ +static void XMC_USBD_lHandleEnumDone(void) +{ + /* Normaly we need to check dctl + * We are always fullspeed, so max it up. */ + depctl_data_t epctl; + gusbcfg_data_t gusbcfg; + + epctl.d32=xmc_device.endpoint_in_register[0U]->diepctl; + epctl.b.mps = 0x00U; /* 64 Byte, this is also automatically set for out ep */ + xmc_device.endpoint_in_register[0U]->diepctl = epctl.d32; + + /* update device connected flag */ + xmc_device.IsConnected = 1U; + xmc_device.IsPowered = 1U; + + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_CONNECT); + + /* Set Trim */ + gusbcfg.d32 = xmc_device.global_register->gusbcfg; + gusbcfg.b.usbtrdtim = 9U; /* default value for LS/FS */ + xmc_device.global_register->gusbcfg = gusbcfg.d32; + + /* clear interrupt */ + XMC_USBD_ClearEvent(XMC_USBD_EVENT_ENUMDONE); +} + + +/** + * @brief Handles all interrupts for all out endpoints + * + * The interrupt handler first checks, which endpoint has caused the interrupt and then + * determines, which interrupt should be handled. + */ +static void XMC_USBD_lHandleOEPInt(const XMC_USBD_t *const obj) +{ + daint_data_t daint; + daint_data_t daintmsk; + doepmsk_data_t doepmsk; + doepint_data_t doepint; + deptsiz_data_t doeptsiz; + XMC_USBD_EP_t *ep; + uint16_t temp; + uint16_t temp1; + uint16_t mask; + uint8_t ep_num; + + daint.d32 = xmc_device.device_register->daint; + + daintmsk.d32 = xmc_device.device_register->daintmsk; + + doepmsk.d32 = xmc_device.device_register->doepmsk; + + mask = daint.ep.out & daintmsk.ep.out; + ep_num = 0U; + doeptsiz.d32 = 0U; + + while ((uint16_t)mask >> ep_num) + { + temp1 = (mask >> (uint16_t)ep_num); + temp = temp1 & 0x1U; + if (temp) + { + /* load register data for endpoint */ + ep = &xmc_device.ep[ep_num]; + doepint.d32 = xmc_device.endpoint_out_register[ep_num]->doepint & doepmsk.d32; + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + doeptsiz.d32 = xmc_device.endpoint_out_register[ep_num]->doeptsiz; + } + /* Setup Phase Complete */ + if (doepint.b.setup) + { + /* ep0 not stalled any more */ + ep->isStalled = 0U; + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + /* calculate size for setup packet */ + ep->outBytesAvailable = (uint32_t)(((uint32_t)XMC_USBD_SETUP_COUNT - + (uint32_t)((deptsiz0_data_t*)&doeptsiz)->b.supcnt)*(uint32_t)XMC_USBD_SETUP_SIZE); + } + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + ep->outBytesAvailable += ep->xferCount; + } + ep->outInUse = 0U; + xmc_device.EndpointEvent_cb(0U,XMC_USBD_EP_EVENT_SETUP); /* signal endpoint event */ + /* clear the interrupt */ + XMC_USBD_ClearEventOUTEP((uint32_t)XMC_USBD_EVENT_OUT_EP_SETUP,ep_num); + } + if (doepint.b.xfercompl) + { + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + uint32_t bytes = (ep->xferLength - ep->xferCount) - doeptsiz.b.xfersize; + ep->xferCount += bytes; + ep->xferBuffer += bytes; + } + if (ep->xferTotal == ep->xferLength) + { + ep->outBytesAvailable = ep->xferCount; + ep->outInUse = 0U; + xmc_device.EndpointEvent_cb(ep_num,XMC_USBD_EP_EVENT_OUT); + } + else + { + XMC_USBD_lStartReadXfer(ep); + } + + } + + XMC_USBD_ClearEventOUTEP(doepint.d32,ep_num); + } + ep_num++; + } + + /* clear interrupt */ + XMC_USBD_ClearEvent(XMC_USBD_EVENT_OUTEP); +} + +/** + * @brief Handles all interrupts for all in endpoints + * + * The interrupt handler first checks, which endpoint has caused the interrupt and then + * determines, which interrupt should be handled. + */ +static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj) +{ + XMC_USBD_EP_t *ep; + daint_data_t daint; + diepmsk_data_t diepmsk; + diepint_data_t diepint; + deptsiz_data_t dieptsiz; + uint16_t temp; + uint16_t temp1; + uint16_t mask; + uint8_t ep_num; + uint32_t inepint; + + daint.d32 = xmc_device.device_register->daint; + + diepmsk.d32 = xmc_device.device_register->diepmsk; + + dieptsiz.d32 = 0U; + mask = daint.ep.in; + ep_num = 0U; + + while ((uint16_t)mask >> ep_num) + { + temp1 = ((uint16_t)mask >> (uint16_t)ep_num); + temp = (uint16_t)temp1 & (uint16_t)0x1U; + if ((uint16_t)temp) + { + ep = &xmc_device.ep[ep_num]; + inepint = (uint32_t)xmc_device.endpoint_in_register[ep_num]->diepint; + diepint.d32 = inepint & + ((((uint32_t)((uint32_t)xmc_device.device_register->dtknqr4_fifoemptymsk >> ep->address_u.address_st.number) & + 0x1U) << 7U) | (uint32_t)diepmsk.d32); + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + dieptsiz.d32 = xmc_device.endpoint_in_register[ep_num]->dieptsiz; + } + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + if (diepint.b.emptyintr) + { + uint32_t bytes; + bytes = XMC_USBD_lWriteFifo(ep); + ep->xferCount += bytes; + ep->xferBuffer += bytes; + } + } + if (diepint.b.xfercompl) + { + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + /* update xfer values */ + if ((dieptsiz.b.pktcnt == 0U) && (dieptsiz.b.xfersize == 0U)) + { + uint32_t Bytes = ep->xferLength - ep->xferCount; + ep->xferCount += Bytes; + ep->xferBuffer += Bytes; + } + } + if (ep->xferTotal==ep->xferLength) + { + ep->inInUse = 0U; + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + /* mask fifo empty interrupt */ + xmc_device.device_register->dtknqr4_fifoemptymsk = + (uint32_t)(xmc_device.device_register->dtknqr4_fifoemptymsk & ~(((uint32_t)1U << ep_num))); + } + xmc_device.EndpointEvent_cb(0x80U | ep_num,XMC_USBD_EP_EVENT_IN); + } + else + { + /* start next step of transfer */ + XMC_USBD_lStartWriteXfer(ep); + } + + } + + XMC_USBD_ClearEventINEP((uint32_t)diepint.d32,ep_num); + } + ep_num++; + } + XMC_USBD_ClearEvent(XMC_USBD_EVENT_INEP); +} + +/** + * @brief RX Fifo interrupt handler + * + * This function handles the interrupt, when the rx fifo is not empty anymore. + */ +static void XMC_USBD_lHandleRxFLvl(void) +{ + device_grxsts_data_t data; + data.d32 = xmc_device.global_register->grxstsp; + + switch (data.b.pktsts) + { + case XMC_USBD_GRXSTS_PKTSTS_GOUTNAK: + break; + case XMC_USBD_GRXSTS_PKTSTS_OUTCMPL: + break; + case XMC_USBD_GRXSTS_PKTSTS_OUTDATA: + XMC_USBD_lReadFifo((uint32_t)data.b.epnum,(uint32_t)data.b.bcnt); + break; + case XMC_USBD_GRXSTS_PKTSTS_SETUP: + XMC_USBD_lReadFifo((uint32_t)data.b.epnum,(uint32_t)data.b.bcnt); + break; + case XMC_USBD_GRXSTS_PKTSTS_SETUPCMPL: + break; + default: + break; + } + /* no need to clear */ +} + +/** + * @brief Global interrupt handler + * + * The handler first checks, which global interrupt has caused the interrupt + * and then dispatches interrupt to the corresponding sub-handler. + */ +void XMC_USBD_IRQHandler(const XMC_USBD_t *const obj) +{ + gintmsk_data_t gintmsk; + gintsts_data_t data; + + gintmsk.d32 = xmc_device.global_register->gintmsk; + data.d32 = xmc_device.global_register->gintsts & gintmsk.d32; + + if (data.b.sofintr) + { + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_SOF); + XMC_USBD_ClearEvent(XMC_USBD_EVENT_SOF); + } + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + if (data.b.rxstsqlvl) + { + /* Masked that interrupt so its only done once */ + gintmsk.b.rxstsqlvl = 0U; + xmc_device.global_register->gintmsk = gintmsk.d32; + XMC_USBD_lHandleRxFLvl(); /* handle the interrupt */ + gintmsk.b.rxstsqlvl = 1U; + xmc_device.global_register->gintmsk = gintmsk.d32; + } + } + if (data.b.erlysuspend) + { + XMC_USBD_ClearEvent(XMC_USBD_EVENT_EARLYSUSPEND); + } + if (data.b.usbsuspend) + { + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_SUSPEND); + XMC_USBD_ClearEvent(XMC_USBD_EVENT_SUSPEND); + } + if (data.b.wkupintr) + { + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_REMOTE_WAKEUP); + XMC_USBD_ClearEvent(XMC_USBD_EVENT_REMOTE_WAKEUP); + } + if (data.b.sessreqintr) + { + xmc_device.IsPowered = 1U; + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_POWER_ON); + XMC_USBD_ClearEvent(XMC_USBD_EVENT_POWER_ON); + } + if (data.b.usbreset) + { + XMC_USBD_lHandleUSBReset(obj); + } + if (data.b.enumdone) + { + XMC_USBD_lHandleEnumDone(); + } + if (data.b.inepint) + { + XMC_USBD_lHandleIEPInt(obj); + } + if (data.b.outepintr) + { + XMC_USBD_lHandleOEPInt(obj); + } + if (data.b.otgintr) + { + XMC_USBD_lHandleOTGInt(); + } + +} + + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ +/** + * Enables the USB0 module + **/ +void XMC_USBD_Enable(void) +{ +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); +#endif + /* Reset and power up */ + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0); + XMC_SCU_POWER_EnableUsb(); +} + +/** + * Disables the USB0 module + **/ +void XMC_USBD_Disable(void) +{ + /* Clear Reset and power up */ + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); +#endif + XMC_SCU_POWER_DisableUsb(); +} + +/** + * Clear the USB device event + **/ +void XMC_USBD_ClearEvent(const XMC_USBD_EVENT_t event) +{ + gintsts_data_t clear; + clear.d32 = 0U; + switch(event) + { + case (XMC_USBD_EVENT_POWER_ON): + clear.b.sessreqintr = 1U; + break; + case (XMC_USBD_EVENT_RESET): + clear.b.usbreset = 1U; + break; + case (XMC_USBD_EVENT_SUSPEND): + clear.b.usbsuspend = 1U; + break; + case (XMC_USBD_EVENT_RESUME): + clear.b.wkupintr = 1U; + break; + case (XMC_USBD_EVENT_REMOTE_WAKEUP): + clear.b.wkupintr = 1U; + break; + case (XMC_USBD_EVENT_SOF): + clear.b.sofintr = 1U; + break; + case (XMC_USBD_EVENT_EARLYSUSPEND): + clear.b.erlysuspend = 1U; + break; + case (XMC_USBD_EVENT_ENUMDONE): + clear.b.enumdone = 1U; + break; + case (XMC_USBD_EVENT_OUTEP): + clear.b.outepintr = 1U; + break; + default: + break; + } + xmc_device.global_register->gintsts = clear.d32; +} + +/** + * Clear the USB OTG events + **/ +static void XMC_USBD_lClearEventOTG(uint32_t event) +{ + gotgint_data_t clear = { .d32 = 0U}; + clear.d32 = event; + xmc_device.global_register->gotgint = clear.d32; +} + +/** + * Clear the USB IN EP events + **/ +void XMC_USBD_ClearEventINEP(uint32_t event,const uint8_t ep_num) +{ + diepint_data_t clear; + clear.d32 = event; + xmc_device.endpoint_in_register[ep_num]->diepint = clear.d32; +} + +/** + * Clear the USB OUT EP events + **/ +void XMC_USBD_ClearEventOUTEP(uint32_t event,const uint8_t ep_num) +{ + doepint_data_t clear; + clear.d32 = event; + xmc_device.endpoint_out_register[ep_num]->doepint = clear.d32; +} + +/** + * Enable the USB OUT EP events + **/ +void XMC_USBD_EnableEventOUTEP(uint32_t event) +{ + doepint_data_t doepint; + doepint.d32 = event; + xmc_device.device_register->doepmsk |= doepint.d32; +} + +/** + * Enable the USB IN EP events + **/ +void XMC_USBD_EnableEventINEP(uint32_t event) +{ + diepint_data_t diepint; + diepint.d32 = event; + xmc_device.device_register->diepmsk |= diepint.d32; +} + +/** + * Gets the USB device capabilities + **/ +XMC_USBD_CAPABILITIES_t XMC_USBD_GetCapabilities() +{ + XMC_USBD_CAPABILITIES_t cap={0U}; + cap.event_connect = 1U; + cap.event_disconnect = 1U; +#if UC_SERIES == 45 + cap.event_power_off = 1U; + cap.event_power_on = 1U; +#else + cap.event_power_off = 0U; + cap.event_power_on = 0U; +#endif + cap.event_high_speed = 0U; + cap.event_remote_wakeup = 1U; + cap.event_reset = 1U; + cap.event_resume = 1U; + cap.event_suspend = 1U; + cap.reserved = 0U; + return cap; +} + +/** + * Initializes the USB device + **/ +XMC_USBD_STATUS_t XMC_USBD_Init(XMC_USBD_t *obj) +{ + uint8_t *XMC_USBD_BASE_ADDRESS; + uint32_t i; + gahbcfg_data_t gahbcfg; + gusbcfg_data_t gusbcfg; + dcfg_data_t dcfg; + dctl_data_t dctl; + gintmsk_data_t gintmsk; + + XMC_ASSERT("XMC_USBD_Init: obj.usbd_max_num_eps not of type XMC_USBD_MAX_NUM_EPS_t", + XMC_USBD_CHECK_INPUT_MAX_NUM_EPS(obj->usbd_max_num_eps)) + + XMC_USBD_Enable(); + + usbd_init = obj; + + /* Filling out buffer size */ + for(i = 0U;i < (uint32_t)XMC_USBD_NUM_EPS;i++) + { + XMC_USBD_EP_OUT_BUFFERSIZE[i] = XMC_USBD_EP0_BUFFER_SIZE; + XMC_USBD_EP_IN_BUFFERSIZE[i] = XMC_USBD_EP0_BUFFER_SIZE; + } + + /* clear device status */ + memset((void*)&xmc_device,0x0U,sizeof(XMC_USBD_DEVICE_t)); + + /* assign callbacks */ + xmc_device.DeviceEvent_cb = obj->cb_xmc_device_event; + xmc_device.EndpointEvent_cb = obj->cb_endpoint_event; + XMC_USBD_BASE_ADDRESS = (uint8_t *)(obj->usbd); + /* assign register address */ + xmc_device.global_register = (dwc_otg_core_global_regs_t*)(obj->usbd); + xmc_device.device_register = ((dwc_otg_device_global_regs_t*)(XMC_USBD_BASE_ADDRESS + DWC_DEV_GLOBAL_REG_OFFSET)); + for (i = 0U;i < (uint32_t)XMC_USBD_NUM_EPS;i++) + { + xmc_device.endpoint_in_register[i] = (dwc_otg_dev_in_ep_regs_t*)(XMC_USBD_BASE_ADDRESS + DWC_DEV_IN_EP_REG_OFFSET + + ((uint32_t)DWC_EP_REG_OFFSET*i)); + } + for (i = 0U;i < (uint32_t)XMC_USBD_NUM_EPS;i++) + { + xmc_device.endpoint_out_register[i] = (dwc_otg_dev_out_ep_regs_t*)(XMC_USBD_BASE_ADDRESS + + DWC_DEV_OUT_EP_REG_OFFSET + + ((uint32_t)DWC_EP_REG_OFFSET*i)); + } + for (i = 0U;i < (uint32_t)XMC_USBD_NUM_TX_FIFOS;i++) + { + xmc_device.fifo[i] = (uint32_t*)(XMC_USBD_BASE_ADDRESS + + XMC_USBD_TX_FIFO_REG_OFFSET + + (i * XMC_USBD_TX_FIFO_OFFSET)); + } + /* obj data structure for endpoint 0 */ + /* Done by driver core */ + /* configure ahb details */ + gahbcfg.d32 = xmc_device.global_register->gahbcfg; + gahbcfg.b.glblintrmsk = 1U; /* enable interrupts ( global mask ) */ + gahbcfg.b.nptxfemplvl_txfemplvl = 1U; + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + /* Enable dma if needed */ + gahbcfg.b.dmaenable = 1U; /* enable dma if needed */ + } + else + { + gahbcfg.b.dmaenable = 0U; + } + xmc_device.global_register->gahbcfg = gahbcfg.d32; + /* configure usb details */ + gusbcfg.d32= xmc_device.global_register->gusbcfg; + gusbcfg.b.force_dev_mode = 1U; /* force us into device mode */ + gusbcfg.b.srpcap = 1U; /* enable session request protocoll */ + xmc_device.global_register->gusbcfg = gusbcfg.d32; + + /* Device init */ + /* configure device speed */ + dcfg.d32 = xmc_device.device_register->dcfg; + dcfg.b.devspd = XMC_USBD_DCFG_DEVSPD_FS; + dcfg.b.descdma = 0U; + xmc_device.device_register->dcfg = dcfg.d32; + /* configure device functions */ + dctl.d32 = xmc_device.device_register->dctl; + dctl.b.sftdiscon = 1U; /* disconnect the device until its connected by the user */ + /* all other config is done by default register value */ + xmc_device.device_register->dctl = dctl.d32; + /* flush the fifos for proper operation */ + XMC_USBD_lFlushTXFifo((uint8_t)0x10U); /* 0x10 == all fifos, see doc */ + XMC_USBD_lFlushRXFifo(); + /* Enable Global Interrupts */ + /* clear interrupt status bits prior to unmasking */ + xmc_device.global_register->gintmsk = 0U; /* disable all interrupts */ + xmc_device.global_register->gintsts = 0xFFFFFFFFU; /* clear all interrupts */ + + gintmsk.d32 = 0U; + /* enable common interrupts */ + gintmsk.b.modemismatch = 1U; + gintmsk.b.otgintr = 1U; + gintmsk.b.sessreqintr = 1U; + /* enable device interrupts */ + gintmsk.b.usbreset = 1U; + gintmsk.b.enumdone = 1U; + gintmsk.b.erlysuspend = 1U; + gintmsk.b.usbsuspend = 1U; + gintmsk.b.wkupintr = 1U; + gintmsk.b.sofintr = 1U; + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + gintmsk.b.rxstsqlvl = 1U; + } + gintmsk.b.outepintr = 1U; + gintmsk.b.inepintr = 1U; + xmc_device.global_register->gintmsk = gintmsk.d32; + return XMC_USBD_STATUS_OK; +} + +/** + * Uninitializes the USB device + **/ +XMC_USBD_STATUS_t XMC_USBD_Uninitialize() +{ + /* Disconnect the device */ + dctl_data_t dctl; + dctl.d32 = xmc_device.device_register->dctl; + dctl.b.sftdiscon = 1U; + xmc_device.device_register->dctl = dctl.d32; + /* clean up */ + memset((void*)&xmc_device,0U,sizeof(xmc_device)); + return XMC_USBD_STATUS_OK; +} + +/** + * Connects the USB device to host + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceConnect() +{ + /* Just disable softdisconnect */ + dctl_data_t dctl; + dctl.d32 = xmc_device.device_register->dctl; + dctl.b.sftdiscon = 0U; + xmc_device.device_register->dctl = dctl.d32; + return XMC_USBD_STATUS_OK; +} + +/** + * Disconnects the USB device from host + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceDisconnect() +{ + dctl_data_t dctl; + dctl.d32 = xmc_device.device_register->dctl; + dctl.b.sftdiscon = 1U; + xmc_device.device_register->dctl = dctl.d32; + return XMC_USBD_STATUS_OK; +} + +/** + * Gets the USB device state. + **/ +XMC_USBD_STATE_t XMC_USBD_DeviceGetState(const XMC_USBD_t *const obj) +{ + XMC_USBD_STATE_t state={0U}; + state.speed = XMC_USBD_SPEED_FULL; + state.connected = xmc_device.IsConnected; + state.active = XMC_USBD_lDeviceActive(obj); + state.powered = xmc_device.IsPowered; + return state; +} + +/** + * Prepares the endpoint to read next OUT packet + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointReadStart(const uint8_t ep_addr, uint32_t size) +{ + XMC_USBD_EP_t *ep = &xmc_device.ep[ep_addr & (uint8_t)XMC_USBD_EP_NUM_MASK]; + XMC_USBD_STATUS_t result; + + if (ep->outInUse || !ep->isConfigured) + { + result = XMC_USBD_STATUS_ERROR; + } + else + { + /* short the length to buffer size if needed */ + if (size > ep->outBufferSize) + { + size = ep->outBufferSize; + } + /* set ep values */ + ep->xferTotal = size; + ep->xferCount = 0U; + ep->xferLength = 0U; + ep->xferBuffer = ep->outBuffer; + ep->outBytesAvailable = 0U; + XMC_USBD_lStartReadXfer(ep); + result= XMC_USBD_STATUS_OK; + } + return result; +} + +/** + * Reads the number of bytes from the USB OUT endpoint + **/ +int32_t XMC_USBD_EndpointRead(const uint8_t ep_num,uint8_t * buffer,uint32_t length) +{ + XMC_USBD_EP_t *ep = &xmc_device.ep[ep_num]; + if (length > ep->outBytesAvailable) + { + length = ep->outBytesAvailable; + } + memcpy(buffer,&ep->outBuffer[ep->outOffset],length); + ep->outBytesAvailable -= length; + if (ep->outBytesAvailable) + { + ep->outOffset += length; + } + else + { + ep->outOffset = 0U; + } + return (int32_t)length; +} + +/** + * Writes number of bytes in to the USB IN endpoint. + **/ +int32_t XMC_USBD_EndpointWrite(const uint8_t ep_num,const uint8_t * buffer,uint32_t length) +{ + XMC_USBD_EP_t * ep = &xmc_device.ep[ep_num & (uint8_t)XMC_USBD_EP_NUM_MASK]; + int32_t result; + if (!ep->isConfigured) + { + result = (int32_t)XMC_USBD_STATUS_ERROR; + } + else if (ep->inInUse == 1U) + { + result=(int32_t)0; + } + else + { + if (length > ep->inBufferSize) + { + length = ep->inBufferSize; + } + /* copy data into input buffer for DMA and FIFO mode */ + memcpy(ep->inBuffer,(const void *)buffer,length); + ep->xferBuffer = ep->inBuffer; + ep->xferTotal = length; + /* set transfer values */ + ep->xferLength = 0U; + ep->xferCount = 0U; + ep->inInUse = 1U; + /* start the transfer */ + XMC_USBD_lStartWriteXfer(ep); + result=(int32_t)ep->xferTotal; + } + return result; +} + +/** + * Sets the USB device address. + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceSetAddress(const uint8_t address,const XMC_USBD_SET_ADDRESS_STAGE_t stage) +{ + dcfg_data_t data; + data.d32 = xmc_device.device_register->dcfg; + if (stage == XMC_USBD_SET_ADDRESS_STAGE_SETUP) + { + data.b.devaddr = address; + xmc_device.device_register->dcfg = data.d32; + } + return XMC_USBD_STATUS_OK; +} + +/** + * Set/clear stall on the selected endpoint. + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointStall(const uint8_t ep_addr, const bool stall) +{ + depctl_data_t data; + XMC_USBD_EP_t *ep = &xmc_device.ep[(ep_addr & (uint8_t)XMC_USBD_EP_NUM_MASK)]; + if (stall) + { + if (ep_addr & (uint8_t)XMC_USBD_ENDPOINT_DIRECTION_MASK) + { + /*set stall bit */ + data.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; + data.b.stall = 1U; + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; + } + else + { + /*set stall bit */ + data.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; + data.b.stall = 1U; + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; + } + ep->isStalled = 1U; + } + else + { + /* just clear stall bit */ + if (ep_addr & (uint8_t)XMC_USBD_ENDPOINT_DIRECTION_MASK) + { + data.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; + data.b.stall = 0U; + data.b.setd0pid = 1U; /* reset pid to 0 */ + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; + } + else + { + data.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; + data.b.stall = 0U; + data.b.setd0pid = 1U; /* reset pid to 0 */ + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; + } + ep->isStalled = 0U; + } + return XMC_USBD_STATUS_OK; +} + +/** + * Aborts the data transfer on the selected endpoint + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointAbort(const uint8_t ep_addr) { + XMC_USBD_EP_t *ep = &xmc_device.ep[ep_addr & (uint8_t)XMC_USBD_ENDPOINT_NUMBER_MASK]; + if (ep->address_u.address_st.direction) + { + ep->inInUse = 0U; + } + if (!ep->address_u.address_st.direction) + { + ep->outInUse = 0U; + } + ep->isStalled = 0U; + ep->outBytesAvailable = 0U; + ep->outOffset = 0U; + ep->xferLength = 0U; + ep->xferCount = 0U; + ep->xferTotal = 0U; + + return XMC_USBD_STATUS_OK; +} + +/** + * Configures the given endpoint + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointConfigure(const uint8_t ep_addr, + const XMC_USBD_ENDPOINT_TYPE_t ep_type, + const uint16_t ep_max_packet_size) +{ + daint_data_t daintmsk; + XMC_USBD_EP_t *ep; + daintmsk.d32 = xmc_device.device_register->daintmsk; + ep =&xmc_device.ep[ep_addr & (uint32_t)XMC_USBD_ENDPOINT_NUMBER_MASK]; + memset((void*)ep,0x0U,sizeof(XMC_USBD_EP_t)); /* clear endpoint structure */ + /* do ep configuration */ + ep->address_u.address = ep_addr; + ep->isConfigured = 1U; + ep->maxPacketSize = (uint8_t)ep_max_packet_size; + if (ep->address_u.address != 0U) + { + ep->maxTransferSize = (uint32_t)XMC_USBD_MAX_TRANSFER_SIZE; + } + else + { + ep->maxTransferSize = (uint32_t)XMC_USBD_MAX_TRANSFER_SIZE_EP0; + } + /* transfer buffer */ + ep->inBuffer = XMC_USBD_EP_IN_BUFFER[ep->address_u.address_st.number]; + ep->outBuffer = XMC_USBD_EP_OUT_BUFFER[ep->address_u.address_st.number]; + /* buffer size*/ + ep->inBufferSize = XMC_USBD_EP_IN_BUFFERSIZE[ep->address_u.address_st.number]; + ep->outBufferSize = XMC_USBD_EP_OUT_BUFFERSIZE[ep->address_u.address_st.number]; + /* is in */ + if ((ep->address_u.address_st.direction == 1U) || (ep_type == XMC_USBD_ENDPOINT_TYPE_CONTROL)) + { + depctl_data_t data; + data.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; + /*enable endpoint */ + data.b.usbactep = 1U; + /* set ep type */ + data.b.eptype = (uint8_t)ep_type; + /* set mps */ + if (ep_type == XMC_USBD_ENDPOINT_TYPE_CONTROL) + { + switch(ep_max_packet_size) + { + case (64U): + data.b.mps = 0x0U; + break; + case (32U): + data.b.mps = 0x1U; + break; + case (16U): + data.b.mps = 0x2U; + break; + case (8U): + data.b.mps = 0x3U; + break; + default: + break; + } + } + else + { + data.b.mps = ep_max_packet_size; + } + /* set first data0 pid */ + data.b.setd0pid = 1U; + /* clear stall */ + data.b.stall = 0U; + /* set tx fifo */ + ep->txFifoNum = XMC_USBD_lAssignTXFifo(); /* get tx fifo */ + data.b.txfnum = ep->txFifoNum; + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; /* configure endpoint */ + daintmsk.ep.in |= (uint16_t)((uint16_t)1U << (uint8_t)ep->address_u.address_st.number); /* enable interrupts for endpoint */ + } + if ((ep->address_u.address_st.direction == 0U) || (ep_type == XMC_USBD_ENDPOINT_TYPE_CONTROL)) + { + /* is out */ + depctl_data_t data; + data.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; + /*enable endpoint */ + data.b.usbactep = 1U; + /* set ep type */ + data.b.eptype = (uint8_t)ep_type; + /* set mps */ + if (ep_type == XMC_USBD_ENDPOINT_TYPE_CONTROL) + { + switch(ep_max_packet_size) + { + case (64U): + data.b.mps = 0x0U; + break; + case (32U): + data.b.mps = 0x1U; + break; + case (16U): + data.b.mps = 0x2U; + break; + case (8U): + data.b.mps = 0x3U; + break; + default: + break; + } + } + else + { + data.b.mps = ep_max_packet_size; + } + /* set first data0 pid */ + data.b.setd0pid = 1U; + /* clear stall */ + data.b.stall =(uint8_t) 0U; + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; /* configure endpoint */ + daintmsk.ep.out |=(uint16_t) ((uint16_t)1U << (uint8_t)ep->address_u.address_st.number); /* enable interrupts */ + } + xmc_device.device_register->daintmsk = daintmsk.d32; + return XMC_USBD_STATUS_OK; +} + +/** + * Unconfigure the selected endpoint. + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointUnconfigure(const uint8_t ep_addr) +{ + XMC_USBD_EP_t *ep = &xmc_device.ep[ep_addr & (uint8_t)XMC_USBD_ENDPOINT_NUMBER_MASK]; + depctl_data_t data; + daint_data_t daintmsk; + XMC_USBD_STATUS_t result; + uint32_t number_temp; + data.d32 = 0U; + daintmsk.d32 = xmc_device.device_register->daintmsk; + number_temp = (uint32_t)((uint32_t)1U << (uint8_t)ep->address_u.address_st.number); + /* if not configured return an error */ + if (!ep->isConfigured) + { + result = XMC_USBD_STATUS_ERROR; + } + else + { + /* disable the endpoint, deactivate it and only send naks */ + data.b.usbactep = 0U; + data.b.epdis = 1U; + data.b.snak = 1U; + data.b.stall = 0U; + ep->isConfigured = 0U; + ep->isStalled = 0U; + ep->outInUse = 0U; + ep->inInUse = 0U; + /* chose register based on the direction. Control Endpoint need both */ + if ((ep->address_u.address_st.direction == 1U) || (ep->type == (uint8_t)XMC_USBD_ENDPOINT_TYPE_CONTROL)) + { + /* disable endpoint configuration */ + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; + /* disable interrupts */ + daintmsk.ep.in = (uint16_t)((uint32_t)daintmsk.ep.in & (~(uint32_t)number_temp)); + } + if ((ep->address_u.address_st.direction == 0U) || (ep->type == (uint8_t)XMC_USBD_ENDPOINT_TYPE_CONTROL)) + { + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; + daintmsk.ep.out = (uint16_t)((uint32_t)daintmsk.ep.out & (~(uint32_t)number_temp)); + if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + xmc_device.device_register->dtknqr4_fifoemptymsk &= ~number_temp; + } + } + xmc_device.device_register->daintmsk = daintmsk.d32; + XMC_USBD_lUnassignFifo(ep->txFifoNum); /* free fifo */ + result = XMC_USBD_STATUS_OK; + } + return result; +} + +/** + * Gets the current USB frame number + **/ +uint16_t XMC_USBD_GetFrameNumber(void) +{ + uint16_t result; + dsts_data_t dsts; + dsts.d32 = xmc_device.device_register->dsts; + result = (uint16_t)dsts.b.soffn; + return result; +} + +/** + * Gets the USB speed enumeration completion status. + * This should not be used for the actual USB enumeration completion status. For the actual USB enumeration status, + * the application layer should check for the completion of USB standard request Set configuration. + **/ +uint32_t XMC_USBD_IsEnumDone(void) +{ + return (uint32_t)((uint8_t)xmc_device.IsConnected && (uint8_t)xmc_device.IsPowered); +} + +/*** + * MISRA C 2004 Deviations + * + * 1. cast from pointer to pointer [MISRA 2004 Rule 11.4] + * 2. cast from pointer to unsigned int [Encompasses MISRA 2004 Rule 11.1], [MISRA 2004 Rule 11.3] + * 3. call to function 'memset()' not made in the presence of a prototype [MISRA 2004 Rule 8.1] + * 4. No explicit type for symbol '_Bool', int assumed + */ +#endif /* defined(USB0) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_usbh.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_usbh.c new file mode 100644 index 00000000..f3e5aeb6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_usbh.c @@ -0,0 +1,1487 @@ +/** + * @file xmc_usbh.c + * @date 2016-06-30 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * (To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + * + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2016-06-30: + * - Initial
+ * 2016-09-01: + * - Removed Keil specific exclusion
+ * + * @endcond + * + */ + +#include +#include + +#include "xmc_usbh.h" + +#if((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC43) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48)) + +/*Function provides transfer result*/ +static uint32_t XMC_USBH_PipeTransferGetResult (XMC_USBH_PIPE_HANDLE pipe_hndl); +/*Updates the power state of the driver*/ +static int32_t XMC_USBH_PowerControl (XMC_USBH_POWER_STATE_t state); + +/*********************************************************** USBH Driver ***************************************************************** */ + +/*Macro to represent USB host driver version*/ +#define XMC_USBH_DRV_VERSION ((uint16_t)((uint16_t)XMC_LIB_MINOR_VERSION << 8U)|XMC_LIB_PATCH_VERSION) +/*Macro used to gate PHY clock and AHB clock*/ +#define XMC_USBH_PHY_CLK_STOP (0x03U) +/*Macro used to ungate PHY clock and AHB clock*/ +#define XMC_USBH_PHY_CLK_UNGATE (0x100U) + +/* Driver Version */ +static const XMC_USBH_DRIVER_VERSION_t xmc_usbh_driver_version = { XMC_USBH_API_VERSION, XMC_USBH_DRV_VERSION }; + +/*Variables to hold selected VBUS port pin*/ +XMC_GPIO_PORT_t * VBUS_port = XMC_GPIO_PORT3; +uint32_t VBUS_pin = 2U; + +/*Array to track nack events on each pipe*/ +bool is_nack[USBH0_MAX_PIPE_NUM]; + +/* Driver Capabilities */ +static const XMC_USBH_CAPABILITIES_t xmc_usbh_driver_capabilities = { + 0x0001U, /* Root HUB available Ports Mask */ + 0U, /* Automatic SPLIT packet handling */ + 1U, /* Signal Connect event */ + 1U, /* Signal Disconnect event */ + 0U /* Signal Overcurrent event */ +}; +/* Driver state and registers */ +static XMC_USBH0_DEVICE_t XMC_USBH0_device/* __attribute__((section ("RW_IRAM1")))*/ = { + (USB0_GLOBAL_TypeDef *)(USB0_BASE), /** Global register interface */ + ((USB0_CH_TypeDef *)(USB0_CH0_BASE)), /** Host channel interface */ + 0, /** Port event callback; set during init */ + 0, /** Pipe event callback; set during init */ + false, /** init status */ + XMC_USBH_POWER_OFF, /** USB Power status */ + false /** Port reset state */ +}; + +/*USB host pipe information. The array stores information related to packet id, data toggle, + * pending data transfer information, periodic transfer interval, received data size etc for each + * pipe.*/ +volatile XMC_USBH0_pipe_t pipe[USBH0_MAX_PIPE_NUM]; + +/* FIFO sizes in bytes (total available memory for FIFOs is 1.25 kB) */ +#define RX_FIFO_SIZE (1128U) /* RxFIFO size */ +#define TX_FIFO_SIZE_NON_PERI (64U) /* Non-periodic Tx FIFO size */ +#define TX_FIFO_SIZE_PERI (1024U) /* Periodic Tx FIFO size */ + +/*Stores data FIFO pointer for each pipe*/ +static uint32_t *XMC_USBH0_dfifo_ptr[USBH0_MAX_PIPE_NUM]; + +/* Local functions */ +/** + * @param enable Enable (XMC_USBH_CLOCK_GATING_ENABLE) or disable(XMC_USBH_CLOCK_GATING_DISABLE) clock gating + * @return None + * \parDescription:
+ * Enable/disable clock gating depending if feature is supported. +*/ +__INLINE static void XMC_lClockGating(uint8_t enable) +{ +#if defined(CLOCK_GATING_SUPPORTED) +if (enable == XMC_USBH_CLOCK_GATING_ENABLE) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); + if (enable == XMC_USBH_CLOCK_GATING_DISABLE) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); +#endif + return; +} + +/** + * @param ptr_ch Pointer to Channel + * @return None + * \parDescription:
+ * Triggers halt of a channel. +*/ +__INLINE static void XMC_lTriggerHaltChannel(USB0_CH_TypeDef *ptr_ch) +{ + ptr_ch->HCINTMSK = USB_CH_HCINT_ChHltd_Msk; /* Enable halt interrupt */ + ptr_ch->HCCHAR |= (uint32_t)(USB_CH_HCCHAR_ChEna_Msk | USB_CH_HCCHAR_ChDis_Msk); + return; +} + +/** + * @param ptr_pipe Pointer to Pipe + * @param ptr_ch Pointer to Channel + * @return bool \n + * true = success,\n + * false = fail + * \parDescription:
+ * Start transfer on Pipe. The function uses transfer complete interrupts to transfer data more than maximum + * packet size. It takes care of updating data toggle information in subsequent packets related to the same data transfer. +*/ +static bool XMC_lStartTransfer (XMC_USBH0_pipe_t *ptr_pipe, USB0_CH_TypeDef *ptr_ch) { + uint32_t hcchar; + uint32_t hctsiz; + uint32_t hcintmsk; + uint32_t num_remaining_transfer; + uint32_t num_remaining_fifo; + uint32_t num_remaining_queue; + uint32_t txsts = 0U; + uint32_t pckt_num; + uint32_t max_pckt_size; + uint8_t *ptr_src = ptr_pipe->data; + uint32_t *ptr_dest = NULL; + uint16_t cnt; + uint32_t loc_index; + bool status; + + if (!(XMC_USBH0_device.global_register->HPRT & USB_HPRT_PrtConnSts_Msk)) + { + status = false; + } + else + { + /* Save channel characteristic register to local variable */ + hcchar = ptr_ch->HCCHAR; + /* Save transfer size register to local variable */ + hctsiz = ptr_ch->HCTSIZ_BUFFERMODE; + hcintmsk = 0U; + cnt = 0U; + + /* Prepare transfer */ + /* Reset EPDir (transfer direction = output) and enable channel */ + hcchar &= (uint32_t)(~(uint32_t)(USB_CH_HCCHAR_EPDir_Msk | USB_CH_HCCHAR_ChDis_Msk)); + hcchar |= (uint32_t)USB_CH_HCCHAR_ChEna_Msk; + + /* Enable default interrupts needed for all transfers */ + hcintmsk = (USB_CH_HCINTMSK_XactErrMsk_Msk | + USB_CH_HCINTMSK_XferComplMsk_Msk | + USB_CH_HCINTMSK_NakMsk_Msk | + USB_CH_HCINTMSK_StallMsk_Msk) ; + /* Keep PID */ + hctsiz &= (uint32_t)USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk; + + /* Packet specific setup */ + switch (ptr_pipe->packet & XMC_USBH_PACKET_TOKEN_Msk) { + case XMC_USBH_PACKET_IN: + /* set transfer direction to input */ + hcchar |= (uint32_t)USB_CH_HCCHAR_EPDir_Msk; + /* Enable IN transfer specific interrupts */ + hcintmsk |= (uint32_t)( USB_CH_HCINTMSK_DataTglErrMsk_Msk | + USB_CH_HCINTMSK_BblErrMsk_Msk | + USB_CH_HCINTMSK_AckMsk_Msk | + USB_CH_HCINTMSK_NakMsk_Msk ) ; + break; + case XMC_USBH_PACKET_OUT: + break; + case XMC_USBH_PACKET_SETUP: + hctsiz &= (uint32_t)~USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk ; + hctsiz |= (uint32_t)USB_CH_HCTSIZx_DPID_MDATA; + break; + default: + break; + } + /* Prepare PID */ + switch (ptr_pipe->packet & XMC_USBH_PACKET_DATA_Msk) { + case XMC_USBH_PACKET_DATA0: + hctsiz &= (uint32_t)~USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk; + hctsiz |= (uint32_t)USB_CH_HCTSIZx_DPID_DATA0; + break; + case XMC_USBH_PACKET_DATA1: + hctsiz &= (uint32_t)~USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk; + hctsiz |= (uint32_t)USB_CH_HCTSIZx_DPID_DATA1; + break; + default: + break; + } + + /* Prepare odd/even frame */ + if ((XMC_USBH0_device.global_register->HFNUM & 1U) != 0U) { + hcchar &= (uint32_t)~USB_CH_HCCHAR_OddFrm_Msk; + } else { + hcchar |= (uint32_t)USB_CH_HCCHAR_OddFrm_Msk; + } + + /* Get transfer type specific status */ + switch (ptr_pipe->ep_type) { + case XMC_USBH_ENDPOINT_CONTROL: + case XMC_USBH_ENDPOINT_BULK: + if (!(hcchar & USB_CH_HCCHAR_EPDir_Msk)) { + txsts = XMC_USBH0_device.global_register->GNPTXSTS; + } + break; + case XMC_USBH_ENDPOINT_ISOCHRONOUS: + case XMC_USBH_ENDPOINT_INTERRUPT: + if (!(hcchar & USB_CH_HCCHAR_EPDir_Msk)) { + txsts = XMC_USBH0_device.global_register->HPTXSTS; + } + break; + default: + break; + } + + /* Calculate remaining transfer size */ + num_remaining_transfer = ptr_pipe->num - ptr_pipe->num_transferred_total; + /* Limit transfer to available space inside fifo/queue if OUT transaction */ + if ((uint32_t)(hcchar & USB_CH_HCCHAR_EPDir_Msk) == 0U) { + max_pckt_size = ptr_pipe->ep_max_packet_size; + num_remaining_fifo = (uint32_t)((uint32_t)(txsts & 0x0000FFFFU) << 2); + num_remaining_queue = (uint32_t)((uint32_t)(txsts & 0x00FF0000U) >> 16); + if (num_remaining_transfer > num_remaining_fifo) { + num_remaining_transfer = num_remaining_fifo; + } + pckt_num = (uint32_t)((num_remaining_transfer + (max_pckt_size - 1U)) / max_pckt_size); + if (pckt_num > num_remaining_queue) { + pckt_num = num_remaining_queue; + } + if (num_remaining_transfer > (pckt_num * max_pckt_size)) { + num_remaining_transfer = pckt_num * max_pckt_size; + } + cnt = (uint16_t)((num_remaining_transfer + 3U) / 4U); + ptr_src = ptr_pipe->data + ptr_pipe->num_transferred_total; + loc_index = ((USB0_CH_TypeDef *)ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers)); + ptr_dest = (uint32_t *)XMC_USBH0_dfifo_ptr[loc_index]; + /* For OUT/SETUP transfer num_transferring represents num of bytes to be sent */ + ptr_pipe->num_transferring = num_remaining_transfer; + } + else { + /* For IN transfer num_transferring is zero */ + ptr_pipe->num_transferring = 0U; + } + /* Set packet count and transfer size */ + if (num_remaining_transfer != 0U) { + hctsiz |= (((num_remaining_transfer + ptr_pipe->ep_max_packet_size) - 1U) / ptr_pipe->ep_max_packet_size) << 19U; + hctsiz |= num_remaining_transfer; + } else { /* Zero length packet */ + hctsiz |= ((uint32_t)1U << USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos); /* Packet count = 1 */ + hctsiz |= 0U; /* Transfer size = 0 */ + } + NVIC_DisableIRQ (USB0_0_IRQn); + ptr_ch->HCINTMSK = hcintmsk; /* Enable channel interrupts */ + ptr_ch->HCTSIZ_BUFFERMODE = hctsiz; /* Write ch transfer size */ + ptr_ch->HCCHAR = hcchar; /* Write ch characteristics */ + while (cnt != 0U) { /* Load data */ +#if defined __TASKING__/*tasking*/ + *ptr_dest = *((__unaligned uint32_t *)ptr_src); +#else/* defined (__GNUC__) || defined (__CC_ARM) || defined (__ICCARM__)*/ + *ptr_dest = *((__packed uint32_t *)ptr_src); +#endif + ptr_src += 4U; + cnt--; + } + NVIC_EnableIRQ (USB0_0_IRQn); /* Enable OTG interrupt */ + status = true; + } + return status; +} + +/* USB driver API functions */ +/** + * @return \ref XMC_USBH_DRIVER_VERSION_t + * \parDescription:
+ * Get driver version. +*/ +static XMC_USBH_DRIVER_VERSION_t XMC_USBH_GetVersion (void) { return xmc_usbh_driver_version; } + +/** + * @return \ref XMC_USBH_CAPABILITIES_t + * \parDescription:
+ * Get driver capabilities. +*/ +static XMC_USBH_CAPABILITIES_t XMC_USBH_GetCapabilities (void) { return xmc_usbh_driver_capabilities; } + +/** + * @param cb_port_event Pointer to port event callback function \ref ARM_USBH_SignalPortEvent + * @param cb_pipe_event Pointer to pipe event callback function \ref ARM_USBH_SignalPipeEvent + * @return int32_t \ref Execution_status. 0 if execution is successful. + * + * \parDescription:
+ * Initialize USB Host Interface. Registers callback functions to be executed on port event and pipe event. + * Initializes FIFO address for each pipe. Configures P3.2 as the VBUS charge pump enable pin.\n + * + * \parRelated APIs:
+ * XMC_USBH_Select_VBUS(), XMC_USBH_Uninitialize() \n +*/ +static int32_t XMC_USBH_Initialize (XMC_USBH_SignalPortEvent_t cb_port_event, + XMC_USBH_SignalPipeEvent_t cb_pipe_event) { + + uint32_t channel; + int32_t status = XMC_USBH_DRIVER_OK; + if (XMC_USBH0_device.init_done == true) + { + /*return ok since initialized*/ + } + else + { + /* assign callbacks */ + XMC_USBH0_device.SignalPortEvent_cb = cb_port_event; + XMC_USBH0_device.SignalPipeEvent_cb = cb_pipe_event; + + /* assign fifo start addresses */ + for (channel = 0U; channel < USBH0_MAX_PIPE_NUM; channel++) { + XMC_USBH0_dfifo_ptr[channel] = (uint32_t *)((uint32_t)USB0_BASE + ((channel + 1U) * 0x01000U)); + } + + XMC_GPIO_SetMode(VBUS_port, (uint8_t)VBUS_pin, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1); + + XMC_USBH0_device.init_done = true; + } + return status; +} + +/** + * @return int32_t \ref Execution_status. Returns 0 to indicate success. + * \parDescription:
+ * De-initialize USB Host Interface. Sets the driver power state as powered off. Disables VBUS.\n + * + * \parRelated APIs:
+ * XMC_USBH_Select_VBUS(), XMC_USBH_Initialize(), XMC_USBH_PortVbusOnOff() \n +*/ +static int32_t XMC_USBH_Uninitialize (void) { + XMC_USBH0_device.init_done = false; + (void)XMC_USBH_PowerControl(XMC_USBH_POWER_OFF); + return XMC_USBH_DRIVER_OK; +} + +/** + * @param state Power state. \ref XMC_USBH_POWER_STATE_t + * @return int32_t \ref Execution_status. Returns 0 if successful. + * \parDescription:
+ * Control USB Host Interface Power. If power state is set to \ref XMC_USBH_POWER_FULL, + * it initializes the peripheral and enables VBUS. If power state is set to \ref XMC_USBH_POWER_OFF, + * disables the peripheral and the VBUS.\n + * + * \parRelated APIs:
+ * XMC_USBH_Select_VBUS(), XMC_USBH_Initialize(), XMC_USBH_PortVbusOnOff(), XMC_USBH_Uninitialize() \n +*/ +static int32_t XMC_USBH_PowerControl (XMC_USBH_POWER_STATE_t state) { + int32_t status = XMC_USBH_DRIVER_OK; + uint32_t loc_value; + switch (state) { + case XMC_USBH_POWER_LOW: + status = XMC_USBH_DRIVER_ERROR_UNSUPPORTED; + break; + case XMC_USBH_POWER_OFF: + NVIC_DisableIRQ (USB0_0_IRQn); + NVIC_ClearPendingIRQ (USB0_0_IRQn); /* Clear pending interrupt */ + XMC_USBH0_device.power_state = state; /* Clear powered flag */ + XMC_USBH0_device.global_register->GAHBCFG &= (uint32_t)(~USB_GAHBCFG_GlblIntrMsk_Msk); /* Disable USB interrupts */ + XMC_lClockGating((uint8_t)XMC_USBH_CLOCK_GATING_ENABLE); /* Enable Clock Gating */ + XMC_USBH0_device.global_register->PCGCCTL |= (uint32_t)USB_PCGCCTL_StopPclk_Msk; /* Stop PHY clock */ + XMC_SCU_POWER_DisableUsb(); /* Disable Power USB */ + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0); /* reset USB */ + XMC_USBH0_device.port_reset_active = false; /* Reset variables */ + memset((void *)(pipe), 0, (USBH0_MAX_PIPE_NUM * sizeof(XMC_USBH0_pipe_t))); + break; + case XMC_USBH_POWER_FULL: + if (XMC_USBH0_device.init_done == false) + { + status = XMC_USBH_DRIVER_ERROR; + break; + } /* not initialized */ + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_FULL) + { + status = XMC_USBH_DRIVER_OK; + break; + } /* already powered */ + XMC_lClockGating((uint8_t)XMC_USBH_CLOCK_GATING_DISABLE); /* disable clock gating */ + (void)XMC_USBH_osDelay(2U); + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0); /* deassert reset USB */ + (void)XMC_USBH_osDelay(2U); + (void)XMC_USBH_osDelay(100U); + XMC_SCU_POWER_EnableUsb(); /* Enable Power USB */ + + /* On-chip Full-speed PHY */ + XMC_USBH0_device.global_register->PCGCCTL &= (uint32_t)~USB_PCGCCTL_StopPclk_Msk; /* Start PHY clock */ + XMC_USBH0_device.global_register->GUSBCFG |= (uint32_t)USB_GUSBCFG_PHYSel_Msk; /* Full-speed transceiver */ + + while ((XMC_USBH0_device.global_register->GRSTCTL & USB_GRSTCTL_AHBIdle_Msk) == 0U) /* wait until AHB master state machine is idle */ + { + /*Wait*/ + } + + XMC_USBH0_device.global_register->GRSTCTL |= (uint32_t)USB_GRSTCTL_CSftRst_Msk; /* Core soft reset */ + + while ((XMC_USBH0_device.global_register->GRSTCTL & USB_GRSTCTL_CSftRst_Msk) != 0U) /* wait soft reset confirmation */ + { + /*Wait*/ + } + (void)XMC_USBH_osDelay(100U); + + XMC_USBH0_device.port_reset_active = false; /* Reset variables */ + memset((void *)(pipe), 0, (USBH0_MAX_PIPE_NUM * sizeof(XMC_USBH0_pipe_t))); + + /*Created local copy of GUSBCFG to avoid side effects*/ + loc_value = XMC_USBH0_device.global_register->GUSBCFG; + if (((loc_value & USB_GUSBCFG_ForceHstMode_Msk) == 0U) || \ + ((loc_value & USB_GUSBCFG_ForceDevMode_Msk) != 0U)) + { + XMC_USBH0_device.global_register->GUSBCFG &= (uint32_t)~USB_GUSBCFG_ForceDevMode_Msk; /* Clear force device mode */ + XMC_USBH0_device.global_register->GUSBCFG |= (uint32_t)USB_GUSBCFG_ForceHstMode_Msk; /* Force host mode */ + (void)XMC_USBH_osDelay(100U); + } + + /* FS only, even if HS is supported */ + XMC_USBH0_device.global_register->HCFG |= (uint32_t)(0x200U | USB_CH_HCFG_FSLSSUP(1)); + + /* Rx FIFO setting */ + XMC_USBH0_device.global_register->GRXFSIZ = (RX_FIFO_SIZE/4U); + /* Non-periodic Tx FIFO setting */ + XMC_USBH0_device.global_register->GNPTXFSIZ_HOSTMODE = (((uint32_t)(TX_FIFO_SIZE_NON_PERI/4U) << 16) | (RX_FIFO_SIZE / 4U)); + /* Periodic Tx FIFO setting */ + XMC_USBH0_device.global_register->HPTXFSIZ = ((uint32_t)(TX_FIFO_SIZE_PERI / 4U) << 16U) | ((RX_FIFO_SIZE + TX_FIFO_SIZE_NON_PERI) / 4U); + /* Enable channel interrupts */ + XMC_USBH0_device.global_register->HAINTMSK = ((uint32_t)1U << USBH0_MAX_PIPE_NUM) - 1U; + /* Unmask interrupts */ + XMC_USBH0_device.global_register->GINTMSK_HOSTMODE = ( + USB_GINTSTS_HOSTMODE_DisconnInt_Msk | + USB_GINTMSK_HOSTMODE_HChIntMsk_Msk | + USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk | + USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk | + USB_GINTMSK_HOSTMODE_SofMsk_Msk | + USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk + ) ; + /* Set powered state */ + XMC_USBH0_device.power_state = state; + /* Enable interrupts */ + XMC_USBH0_device.global_register->GAHBCFG |= (uint32_t)USB_GAHBCFG_GlblIntrMsk_Msk; + /* Set highest interrupt priority */ + NVIC_SetPriority (USB0_0_IRQn, 0U); + NVIC_EnableIRQ (USB0_0_IRQn); + break; + default: + status = XMC_USBH_DRIVER_ERROR_UNSUPPORTED; + } + return status; +} + +/** + * @param port Root HUB Port Number. Only one port(0) is supported. + * @param vbus VBUS state - \n + * - \b false VBUS off + * - \b true VBUS on + * @return int32_t \ref Execution_status. Returns 0 if successful. + * + * \parDescription:
+ * Set USB port VBUS on/off. +*/ +static int32_t XMC_USBH_PortVbusOnOff (uint8_t port, bool vbus) { + int32_t status = XMC_USBH_DRIVER_OK; + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (port != 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + if (vbus != 0U) { + /* Port power on */ + XMC_USBH0_device.global_register->HPRT |= (uint32_t)USB_HPRT_PrtPwr_Msk; + XMC_GPIO_SetMode(VBUS_port, (uint8_t)VBUS_pin, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1); + } else { + /* Port power off */ + XMC_USBH0_device.global_register->HPRT &= (uint32_t)~USB_HPRT_PrtPwr_Msk; + XMC_GPIO_SetMode(VBUS_port, (uint8_t)VBUS_pin, XMC_GPIO_MODE_INPUT_TRISTATE); + } + } + } + return status; +} + +/** + * @param port Root HUB Port Number. Only one port(0) is supported. + * @return int32_t Execution status. \ref Execution_status + * \parDescription:
+ * Do USB port reset. Port reset should honor the requirement of 50ms delay before enabling. + * The function depends on implementation of XMC_USBH_osDelay() for 1ms delay to achieve required delay. + * +*/ +static int32_t XMC_USBH_PortReset (uint8_t port) { + uint32_t hprt; + int32_t status = XMC_USBH_DRIVER_OK; + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (port != 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + + XMC_USBH0_device.port_reset_active = true; + hprt = XMC_USBH0_device.global_register->HPRT; + hprt &= (uint32_t)~USB_HPRT_PrtEna_Msk; /* Disable port */ + hprt |= (uint32_t)USB_HPRT_PrtRst_Msk; /* Port reset */ + XMC_USBH0_device.global_register->HPRT = hprt; + (void)XMC_USBH_osDelay(50U); /* wait at least 50ms */ + hprt &= (uint32_t)~USB_HPRT_PrtRst_Msk; /* Clear port reset */ + XMC_USBH0_device.global_register->HPRT = hprt; + (void)XMC_USBH_osDelay(50U); /* wait for ISR */ + + /*Wait for the port to be enabled*/ + while ((XMC_USBH0_device.global_register->HPRT & USB_HPRT_PrtEna_Msk) == 0U) + { + /*wait*/ + } + + if (XMC_USBH0_device.port_reset_active == true) + { + XMC_USBH0_device.port_reset_active = false; + status = XMC_USBH_DRIVER_ERROR; /* reset not confirmed inside ISR */ + } + } + + return status; +} + +/** + * @param port USB port number. Only one port(0) is supported. + * @return \ref Execution_status + * \parDescription:
+ * Suspend USB Port (stop generating SOFs).\n + * + * \parRelated APIs:
+ * XMC_USBH_PortResume() \n +*/ +static int32_t XMC_USBH_PortSuspend (uint8_t port) +{ + int32_t status = XMC_USBH_DRIVER_OK; + uint32_t hprt; + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (port != 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + hprt = XMC_USBH0_device.global_register->HPRT; + hprt &= (uint32_t)~(USB_HPRT_PrtEna_Msk); + hprt |= (uint32_t)USB_HPRT_PrtSusp_Msk; + XMC_USBH0_device.global_register->HPRT = hprt; + /* Stop PHY clock after suspending the bus*/ + XMC_USBH0_device.global_register->PCGCCTL |= XMC_USBH_PHY_CLK_STOP; + + } + } + return status; +} + +/** + * @param port USB port number. Only one port(0) is supported. + * @return \ref Execution_status + * \parDescription:
+ * Resume suspended USB port (start generating SOFs).\n + * + * \parRelated APIs:
+ * XMC_USBH_PortSuspend() \n +*/ +static int32_t XMC_USBH_PortResume (uint8_t port) +{ + int32_t status = XMC_USBH_DRIVER_OK; + uint32_t hprt; + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (port != 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + /*Ungate PHY clock*/ + XMC_USBH0_device.global_register->PCGCCTL = XMC_USBH_PHY_CLK_UNGATE; + /*Set resume bit*/ + hprt = XMC_USBH0_device.global_register->HPRT; + hprt &= (uint32_t)~(USB_HPRT_PrtEna_Msk); + hprt |= (uint32_t)USB_HPRT_PrtRes_Msk; + XMC_USBH0_device.global_register->HPRT = hprt; + + (void)XMC_USBH_osDelay(20U); + + hprt = XMC_USBH0_device.global_register->HPRT; + hprt &= (uint32_t)~(USB_HPRT_PrtEna_Msk); + hprt &= (uint32_t)~((uint32_t)USB_HPRT_PrtRes_Msk); + XMC_USBH0_device.global_register->HPRT = hprt; + } + } + + return status; +} + +/** + * @param port USB port number. Only one port(0) is supported. + * @return XMC_USBH_PORT_STATE_t Port State + * + * \parDescription:
+ * Get current USB port state. The state indicates if the port is connected, port speed + * and port overcurrent status. +*/ +static XMC_USBH_PORT_STATE_t XMC_USBH_PortGetState (uint8_t port) +{ + XMC_USBH_PORT_STATE_t port_state = { 0U, 0U, 0U }; + uint32_t hprt; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + /*Do not update the port state*/ + } + else + { + if (port != 0U) + { + /*Do not update the port state*/ + } + else + { + hprt = XMC_USBH0_device.global_register->HPRT; + if(((hprt & USB_HPRT_PrtConnSts_Msk) != 0U)) + { + port_state.connected = 1U; + } + else + { + port_state.connected = 0U; + } + port_state.overcurrent = 0U; + + switch ((uint32_t)((uint32_t)(hprt & USB_HPRT_PrtSpd_Msk) >> USB_HPRT_PrtSpd_Pos)) { + case 1U: /* Full speed */ + port_state.speed = XMC_USBH_SPEED_FULL; + break; + default: + break; + } + } + } + return port_state; +} + +/** + * @param dev_addr Device address + * @param dev_speed Device speed + * @param hub_addr Hub address. This value should be 0 since hub is not supported. + * @param hub_port USB port number. Only one port(0) is supported. + * @param ep_addr Device endpoint address \n + * - ep_addr.0..3: Address \n + * - ep_addr.7: Direction\n + * @param ep_type Endpoint type (ARM_USB_ENDPOINT_xxx) + * @param ep_max_packet_size Endpoint maximum packet size + * @param ep_interval Endpoint polling interval + * @return XMC_USBH_PIPE_HANDLE Pipe handle is a pointer to pipe hardware base address. + * + * \parDescription:
+ * Create/allocate a pipe configured with input parameters. The function looks for an unused pipe and configures with input parameters. + * + * \parRelated APIs:
+ * XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeReset(), XMC_USBH_PipeTransfer() \n +*/ +static XMC_USBH_PIPE_HANDLE XMC_USBH_PipeCreate (uint8_t dev_addr, uint8_t dev_speed, uint8_t hub_addr, uint8_t hub_port, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_max_packet_size, uint8_t ep_interval) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + uint32_t i; + uint32_t loc_val; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + ptr_ch = (USB0_CH_TypeDef *)NULL; + } + else + { + /* get first free pipe available */ + ptr_ch = (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers); + + for (i = 0U; i < USBH0_MAX_PIPE_NUM; i++) { + if ((ptr_ch->HCCHAR & 0x3FFFFFFFU) == 0U) + { + break; + } + ptr_ch++; + } + + /* free pipe found? */ + if (i == USBH0_MAX_PIPE_NUM) + { + ptr_ch = (USB0_CH_TypeDef *)NULL; + } + else + { + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + + memset((void *)ptr_pipe, 0, sizeof(XMC_USBH0_pipe_t)); /* Initialize pipe structure */ + + /* Fill in all fields of Endpoint Descriptor */ + /*Get the end point direction from the MSB of address*/ + loc_val = 0U; + if (((ep_addr >> 7U) & 0x1U) == 0U) + { + loc_val = 1U; + } + ptr_ch->HCCHAR = ((uint32_t)(USB_CH_HCCHARx_MPS(ep_max_packet_size))| + USB_CH_HCCHARx_EPNUM(ep_addr)) | + (uint32_t)(USB_CH_HCCHAR_EPDir_Msk * loc_val) | + (USB_CH_HCCHARx_EPTYPE (ep_type) ) | + (USB_CH_HCCHARx_DEVADDR (dev_addr) ) ; + /* Store Pipe settings */ + ptr_pipe->ep_max_packet_size = ep_max_packet_size; + ptr_pipe->ep_type = ep_type; + switch (ep_type) { + case XMC_USBH_ENDPOINT_CONTROL: + case XMC_USBH_ENDPOINT_BULK: + break; + case XMC_USBH_ENDPOINT_ISOCHRONOUS: + case XMC_USBH_ENDPOINT_INTERRUPT: + if (ep_interval > 0U) { + ptr_pipe->interval_reload = ep_interval; + } + ptr_pipe->interval = ptr_pipe->interval_reload; + loc_val = ((((uint32_t)ep_max_packet_size >> 11U) + 1U) & 3U); + ptr_ch->HCCHAR |= (uint32_t)USB_CH_HCCHARx_MCEC(loc_val); + break; + default: + break; + } + } + } + return ((XMC_USBH_EP_HANDLE)ptr_ch); +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @param dev_addr Device address to be configured for the pipe. + * @param dev_speed Device speed class. + * @param hub_addr Hub address. It should be 0 since hub is not supported. + * @param hub_port USB port number. Only one port(0) is supported. + * @param ep_max_packet_size Endpoint maximum packet size + * @return Execution_status + * + * \parDescription:
+ * Modify an existing pipe with input parameters. It can be used to configure the pipe after receiving configuration details from the device. + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeDelete(), XMC_USBH_PipeReset(), XMC_USBH_PipeTransfer() \n +*/ +static int32_t XMC_USBH_PipeModify (XMC_USBH_PIPE_HANDLE pipe_hndl, uint8_t dev_addr, uint8_t dev_speed, uint8_t hub_addr, uint8_t hub_port, uint16_t ep_max_packet_size) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + uint32_t hcchar; + int32_t status = XMC_USBH_DRIVER_OK; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (pipe_hndl == 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + ptr_ch = (USB0_CH_TypeDef *)(pipe_hndl); + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + if (ptr_pipe->in_use != 0U) + { + status = XMC_USBH_DRIVER_ERROR_BUSY; + } + else + { + /* Fill in all fields of channel */ + hcchar = ptr_ch->HCCHAR; + /* Clear fields */ + hcchar &= (uint32_t)~(USB_CH_HCCHAR_MPS_Msk | USB_CH_HCCHAR_DevAddr_Msk) ; + /* Set fields */ + hcchar |= (uint32_t)(USB_CH_HCCHARx_MPS(ep_max_packet_size) | (USB_CH_HCCHARx_DEVADDR(dev_addr))); + ptr_ch->HCCHAR = hcchar; + + ptr_pipe->ep_max_packet_size = ep_max_packet_size; + } + } + } + + return status; +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @return Execution_status + * + * \parDescription:
+ * Delete pipe from active pipes list. After it is deleted, it can be assigned to new pipe request. + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeReset(), XMC_USBH_PipeTransfer() \n +*/ +static int32_t XMC_USBH_PipeDelete (XMC_USBH_PIPE_HANDLE pipe_hndl) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + int32_t status = XMC_USBH_DRIVER_OK; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (pipe_hndl == 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + ptr_ch = (USB0_CH_TypeDef *)(pipe_hndl); + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + if (ptr_pipe->in_use != 0U) + { + status = XMC_USBH_DRIVER_ERROR_BUSY; + } + else + { + ptr_ch->HCCHAR = 0U; + ptr_ch->HCINT = 0U; + ptr_ch->HCINTMSK = 0U; + ptr_ch->HCTSIZ_BUFFERMODE = 0U; + + memset((void *)ptr_pipe, 0, sizeof(XMC_USBH0_pipe_t)); + } + } + } + + return status; +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @return Execution_status + * \parDescription:
+ * Reset pipe by clearing the interrupt mask and resetting the transfer control register.\n + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeTransfer() \n +*/ +static int32_t XMC_USBH_PipeReset (XMC_USBH_PIPE_HANDLE pipe_hndl) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + int32_t status = XMC_USBH_DRIVER_OK; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (pipe_hndl == 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + ptr_ch = (USB0_CH_TypeDef *)(pipe_hndl); + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + if (ptr_pipe->in_use != 0U) + { + status = XMC_USBH_DRIVER_ERROR_BUSY; + } + else + { + ptr_ch->HCINT = 0U; + ptr_ch->HCINTMSK = 0U; + ptr_ch->HCTSIZ_BUFFERMODE = 0U; + } + } + } + return status; +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @param packet Packet information with bit masks to represent packet data toggle information and packet type.\n + * \ref XMC_USBH_PACKET_DATA0 / \ref XMC_USBH_PACKET_DATA1, \ref XMC_USBH_PACKET_SETUP / + * \ref XMC_USBH_PACKET_OUT / \ref XMC_USBH_PACKET_IN + * @param data Pointer to buffer with data to send or for received data to be stored. + * @param num Number of data bytes to transfer + * @return Execution_status + * + * \parDescription:
+ * Transfer packets through USB Pipe. Handles transfer of multiple packets using the pipe transfer complete event. + * The pipe event callback function will be called when the transfer is completed.\n + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeReset() \n +*/ +static int32_t XMC_USBH_PipeTransfer (XMC_USBH_PIPE_HANDLE pipe_hndl, uint32_t packet, uint8_t *data, uint32_t num) { + XMC_USBH0_pipe_t *ptr_pipe; + int32_t status = XMC_USBH_DRIVER_OK; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + + if(!(((((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_OUT) || + ((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_IN))) || + ((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_SETUP ))) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + if (pipe_hndl == 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + if ((XMC_USBH0_device.global_register->HPRT & USB_HPRT_PrtConnSts_Msk) == 0U) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[((USB0_CH_TypeDef *)pipe_hndl - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + if (ptr_pipe->in_use != 0U) + { + status = XMC_USBH_DRIVER_ERROR_BUSY; + } + else + { + /* Prepare transfer information */ + ptr_pipe->packet = packet; + ptr_pipe->data = data; + ptr_pipe->num = num; + ptr_pipe->num_transferred_total = 0U; + ptr_pipe->num_transferring = 0U; + ptr_pipe->in_use = 0U; + ptr_pipe->transfer_active = 0U; + ptr_pipe->interrupt_triggered = 0U; + ptr_pipe->event = 0U; + + if ((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) && (ptr_pipe->interval != 0U)) { + ptr_pipe->in_use = 1U; /* transfer will be started inside interrupt (SOF) */ + } else { + ptr_pipe->transfer_active = 1U; + ptr_pipe->in_use = 1U; + if(XMC_lStartTransfer (ptr_pipe, (USB0_CH_TypeDef *)pipe_hndl) == false) + { + status = XMC_USBH_DRIVER_ERROR; + } + } + } + } + } + } + } + return status; +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @return uint32_t Number of successfully transferred data bytes + * + * \parDescription:
+ * Get result of USB Pipe transfer. + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeTransfer() \n +*/ +static uint32_t XMC_USBH_PipeTransferGetResult (XMC_USBH_PIPE_HANDLE pipe_hndl) { + uint32_t status; + if (pipe_hndl == 0U) + { + status = 0U; + } + else + { + status = (pipe[((USB0_CH_TypeDef *)pipe_hndl - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))].num_transferred_total); + } + return status; +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @return Execution_status + * + * \parDescription:
+ * Abort current USB Pipe transfer.\n + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeTransfer() \n +*/ +static int32_t XMC_USBH_PipeTransferAbort (XMC_USBH_PIPE_HANDLE pipe_hndl) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + uint32_t timeout; + int32_t status = XMC_USBH_DRIVER_ERROR; + + ptr_ch = (USB0_CH_TypeDef *) pipe_hndl; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + /*Error in power state*/ + } + else + { + if (pipe_hndl == 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + + if (ptr_pipe->in_use != 0U) { + ptr_pipe->in_use = 0U; + /* Disable channel if not yet halted */ + if ((ptr_ch->HCINT & USB_CH_HCINT_ChHltd_Msk) == 0U) + { + if (ptr_ch->HCCHAR & USB_CH_HCCHAR_ChEna_Msk) + { + ptr_ch->HCINTMSK = 0U; + (void)XMC_USBH_osDelay(1U); + if (ptr_ch->HCINT & USB_CH_HCINT_NAK_Msk) { + ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* Clear all interrupts */ + status = XMC_USBH_DRIVER_OK; + } + else + { + ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* Clear all interrupts */ + ptr_ch->HCCHAR = (uint32_t)(ptr_ch->HCCHAR | USB_CH_HCCHAR_ChEna_Msk | USB_CH_HCCHAR_ChDis_Msk); + + /* wait until channel is halted */ + for (timeout = 0U; timeout < 5000U; timeout++) { + if (ptr_ch->HCINT & USB_CH_HCINT_ChHltd_Msk) { + ptr_ch->HCINT = USB_CH_HCINTx_ALL; + status = XMC_USBH_DRIVER_OK; + } + } + } + } + } + } + } + } + + return status; +} + +/** + * @return Frame number. + * + * \parDescription:
+ * Get current USB Frame Number. +*/ +static uint16_t XMC_USBH_GetFrameNumber (void) +{ + uint16_t status; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = 0U; + } + else + { + status = (uint16_t)((XMC_USBH0_device.global_register->HFNUM) & 0xFFFU); + } + return status; +} + +/** + * @param gintsts USB port interrupt status flag. + * + * \parDescription:
+ * USB host interrupt handler. It updates port and pipe state information based on different events + * generated by the peripheral. It propagates the port events to the callback function registered by the user + * during initialization. When a pipe transfer complete event is detected, it checks if any further data is available + * to be transmitted on the same pipe and continues transmission until data is available. A pipe event is also propagated + * to the user provided pipe event callback function. A transfer complete event will be propagated only when all the data + * is transmitted for an OUT transaction. + * +*/ +void XMC_USBH_HandleIrq (uint32_t gintsts) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + uint32_t hprt, haint, hcint, pktcnt, mpsiz; + uint32_t ch; + uint8_t *ptr_data; + uint32_t *dfifo; + uint32_t grxsts, bcnt, dat, len, len_rest; + + /* Host port interrupt */ + if ((gintsts & USB_GINTSTS_HOSTMODE_PrtInt_Msk) != 0U) { + hprt = XMC_USBH0_device.global_register->HPRT; + /* Clear port enable */ + XMC_USBH0_device.global_register->HPRT = hprt & (uint32_t)(~USB_HPRT_PrtEna_Msk); + if ((hprt & USB_HPRT_PrtConnDet_Msk) != 0U) { + XMC_USBH0_device.global_register->HCFG = (0x200U | (USB_CH_HCFG_FSLSPCS(1) | + USB_CH_HCFG_FSLSSUP(1))); + /* Ignore connect under reset */ + if (XMC_USBH0_device.port_reset_active == false) { + XMC_USBH0_device.SignalPortEvent_cb(0U, XMC_USBH_EVENT_CONNECT); + } + } + if ((hprt & USB_HPRT_PrtEnChng_Msk) != 0U) { /* If port enable changed */ + if ((hprt & USB_HPRT_PrtEna_Msk) != 0U) { /* If device connected */ + if (XMC_USBH0_device.port_reset_active == true) { + XMC_USBH0_device.port_reset_active = false; + XMC_USBH0_device.SignalPortEvent_cb(0U, XMC_USBH_EVENT_RESET); + } + } + } + } + + /* Disconnect interrupt */ + if ((gintsts & USB_GINTSTS_HOSTMODE_DisconnInt_Msk) != 0U) { + XMC_USBH0_device.global_register->GINTSTS_HOSTMODE = USB_GINTSTS_HOSTMODE_DisconnInt_Msk; /* Clear disconnect interrupt */ + /* Ignore disconnect under reset */ + if ( XMC_USBH0_device.port_reset_active == false) { + ptr_ch = (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers); + ptr_pipe = (XMC_USBH0_pipe_t *)(pipe); + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { + if (ptr_pipe->in_use != 0U) { + ptr_pipe->in_use = 0U; + ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* Clear all interrupts */ + ptr_ch->HCINTMSK = USB_CH_HCINT_ChHltd_Msk; /* Enable halt interrupt */ + ptr_ch->HCCHAR |= (uint32_t)(USB_CH_HCCHAR_ChEna_Msk | USB_CH_HCCHAR_ChDis_Msk); /* Activate Halt */ + XMC_USBH0_device.SignalPipeEvent_cb((XMC_USBH_EP_HANDLE)ptr_ch, XMC_USBH_EVENT_BUS_ERROR); + } + ptr_ch++; + ptr_pipe++; + } + XMC_USBH0_device.SignalPortEvent_cb(0U, XMC_USBH_EVENT_DISCONNECT); + } + } + /* Handle receive fifo not-empty interrupt */ + if ((gintsts & USB_GINTSTS_HOSTMODE_RxFLvl_Msk) != 0U) { + XMC_USBH0_device.global_register->GINTMSK_HOSTMODE &= (uint32_t)~USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk; + grxsts = (XMC_USBH0_device.global_register->GRXSTSP_HOSTMODE); + /* IN Data Packet received ? */ + if ((uint32_t)((grxsts >> 17U) & 0x0FU) == (uint32_t)USB_GRXSTSR_HOSTMODE_PktSts_IN_DATA_PKT) { + ch = (uint32_t)(grxsts & USB_GRXSTSR_DEVICEMODE_EPNum_Msk); + bcnt = ((uint32_t)(grxsts & USB_GRXSTSR_DEVICEMODE_BCnt_Msk) >> USB_GRXSTSR_DEVICEMODE_BCnt_Pos); + dfifo = (uint32_t *)XMC_USBH0_dfifo_ptr[ch]; + ptr_data = pipe[ch].data + pipe[ch].num_transferred_total; + len = bcnt / 4U; /* Received number of 32-bit data */ + len_rest = bcnt & 3U; /* Number of bytes left */ + /* Read data from fifo */ + /* Read 32 bit sized data */ + while (len != 0U) { +#if defined __TASKING__/*tasking*/ + *((__unaligned uint32_t *)ptr_data) = *dfifo; +#else /* defined (__GNUC__) || defined (__CC_ARM) || defined (__ICCARM__)*/ + *((__packed uint32_t *)ptr_data) = *dfifo; +#endif + + ptr_data += 4U; + len--; + } + /* Read 8 bit sized data */ + if (len_rest != 0U) { +#if defined __TASKING__/*tasking*/ + dat = *((__unaligned uint32_t *)dfifo); +#else /* defined (__GNUC__) || defined (__CC_ARM) || defined (__ICCARM__)*/ + dat = *((__packed uint32_t *)dfifo); +#endif + while (len_rest != 0U) { + *ptr_data = (uint8_t)dat; + ptr_data++; + dat >>= 8; + len_rest--; + } + } + pipe[ch].num_transferring += bcnt; + pipe[ch].num_transferred_total += bcnt; + } + XMC_USBH0_device.global_register->GINTMSK_HOSTMODE |= (uint32_t)USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk; + } + + /* Handle sof interrupt */ + if ((gintsts & USB_GINTSTS_HOSTMODE_Sof_Msk) != 0U) { /* If start of frame interrupt */ + XMC_USBH0_device.global_register->GINTSTS_HOSTMODE = USB_GINTSTS_HOSTMODE_Sof_Msk; /* Clear SOF interrupt */ + ptr_pipe = (XMC_USBH0_pipe_t *)(pipe); + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { + /* If interrupt transfer is active handle period (interval) */ + if ((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) && (ptr_pipe->in_use == 1U)) { + if (ptr_pipe->interval != 0U) + { + ptr_pipe->interval--; + if (ptr_pipe->interval == 0U) + { + ptr_pipe->interval = ptr_pipe->interval_reload; + ptr_pipe->interrupt_triggered = 1U; + } + } + } + ptr_pipe++; + } + } + + /* Handle host ctrl interrupt */ + if ((gintsts & USB_GINTSTS_HOSTMODE_HChInt_Msk) != 0U) { + haint = XMC_USBH0_device.global_register->HAINT; + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { + /* Check for interrupt of all channels */ + if ((haint & (uint32_t)((uint32_t)1U << ch)) != 0U) { + haint &= (uint32_t)~((uint32_t)1U << ch); + ptr_ch = (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers) + ch; + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[ch]); + /*Local variable for HCINT*/ + dat = ptr_ch->HCINT; + hcint = (uint32_t)(dat & ptr_ch->HCINTMSK); + if ((hcint & USB_CH_HCINT_ChHltd_Msk) != 0U) { /* channel halted ? */ + ptr_ch->HCINTMSK = 0U; /* disable all channel interrupts */ + ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* clear all interrupts */ + ptr_pipe->transfer_active = 0U; /* set status transfer not active */ + hcint = 0U; + } + if ((hcint & USB_CH_HCINT_XferCompl_Msk) != 0U) { /* data transfer finished ? */ + ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* clear all interrupts */ + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) == 0U) { /* endpoint OUT ? */ + ptr_ch->HCINTMSK = 0U; /* disable all channel interrupts */ + ptr_pipe->transfer_active = 0U; /* transfer not in progress */ + ptr_pipe->num_transferred_total += ptr_pipe->num_transferring; /* admin OUT transfer status */ + ptr_pipe->num_transferring = 0U; /* admin OUT transfer status */ + if (ptr_pipe->num_transferred_total == ptr_pipe->num) { /* all bytes transferred ? */ + ptr_pipe->in_use = 0U; /* release pipe */ + ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_TRANSFER_COMPLETE; /* prepare event notification */ + } + hcint = 0U; + } + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) { /* endpoint IN ? */ + ptr_pipe->in_use = 0U; /* release pipe */ + ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_TRANSFER_COMPLETE; /* prepare event notification */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + } + } + if ((hcint & USB_CH_HCINTMSK_AckMsk_Msk) != 0U) { /* ACK received ? */ + ptr_ch->HCINT = USB_CH_HCINTMSK_AckMsk_Msk; /* clear ACK interrupt */ + is_nack[ch] = false; + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) { /* endpoint IN ? */ + if ((ptr_pipe->num != ptr_pipe->num_transferred_total) && /* if all data was not transferred */ + (ptr_pipe->num_transferring != 0U) && /* if zero-length packet was not received */ + ((ptr_pipe->num_transferred_total%ptr_pipe->ep_max_packet_size) == 0U)){ /* if short packet was not received */ + ptr_ch->HCCHAR |= (uint32_t)USB_CH_HCCHAR_ChEna_Msk; /* trigger next transfer */ + } + } else { /* endpoint OUT */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + } + hcint = 0U; + } + /*local variable for HCCHAR*/ + dat = ptr_ch->HCCHAR; + if (((hcint & (USB_CH_HCINTMSK_StallMsk_Msk | /* STALL */ + USB_CH_HCINTMSK_NakMsk_Msk | /* or NAK */ + USB_CH_HCINTx_ERRORS )) != 0U) && /* or transaction error */ + ((dat & USB_CH_HCCHAR_EPDir_Msk) == 0U)) + { /* and endpoint OUT */ + + pktcnt = (uint32_t)((ptr_ch->HCTSIZ_BUFFERMODE & USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk) /* administrate OUT transfer status */ + >> USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos); + mpsiz = (ptr_ch->HCCHAR ) & 0x000007FFU; + if ((ptr_pipe->num_transferring >= mpsiz) && (pktcnt > 0U)) { + ptr_pipe->num_transferred_total += (uint32_t)(ptr_pipe->num_transferring - (mpsiz * pktcnt)); + } + ptr_pipe->num_transferring = 0U; + } + + if ((hcint & USB_CH_HCINTMSK_NakMsk_Msk)!=0U) { /* if NAK */ + is_nack[ch] = true; + ptr_pipe->event |= (uint8_t)XMC_USBH_EVENT_HANDSHAKE_NAK; + ptr_ch->HCINT = USB_CH_HCINTMSK_NakMsk_Msk; /* clear NAK interrupt */ + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) { /* endpoint IN ? */ + if (ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) { /* is endpoint of type interrupt ? */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt (after halted will be restarted in next sof) */ + } else { /* is endpoint not of type interrupt ?*/ + ptr_ch->HCCHAR |= (uint32_t)USB_CH_HCCHAR_ChEna_Msk; /* trigger next transfer */ + } + } else { /* If endpoint OUT */ /* endpoint OUT ? */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + } + hcint = 0U; + } + + if ((hcint & USB_CH_HCINTMSK_StallMsk_Msk) != 0U) { /* if STALL */ + /*Reset the packet data toggle*/ + ptr_ch->HCINT = USB_CH_HCINTMSK_StallMsk_Msk; /* clear STALL interrupt */ + ptr_pipe->in_use = 0U; /* release pipe */ + ptr_pipe->packet &= (uint32_t)(~XMC_USBH_PACKET_DATA_Msk); + ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA0; + ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_HANDSHAKE_STALL; /* prepare event notification */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + hcint = 0U; + } + if ((hcint & USB_CH_HCINTx_ERRORS) != 0U) { /* if transaction error */ + ptr_ch->HCINT = USB_CH_HCINTx_ERRORS; /* clear all error interrupt */ + ptr_pipe->in_use = 0U; /* release pipe */ + ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_BUS_ERROR; /* prepare event notification */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + hcint = 0U; + } + if ((ptr_pipe->transfer_active == 0U) && (ptr_pipe->in_use == 0U) && (ptr_pipe->event != 0U)) { + XMC_USBH0_device.SignalPipeEvent_cb((XMC_USBH_EP_HANDLE)ptr_ch, (uint32_t)ptr_pipe->event); + ptr_pipe->event = 0U; + } + } + } + } + /*Check if remote wakeup event detected*/ + if ((gintsts & USB_GINTSTS_HOSTMODE_WkUpInt_Msk) != 0U) + { + XMC_USBH0_device.global_register->GINTSTS_HOSTMODE = USB_GINTSTS_HOSTMODE_WkUpInt_Msk; /* Clear wakeup interrupt */ + /*Recover PHY clock*/ + XMC_USBH0_device.global_register->PCGCCTL = XMC_USBH_PHY_CLK_UNGATE; + /*Callback function execution*/ + XMC_USBH0_device.SignalPortEvent_cb(0U, XMC_USBH_EVENT_REMOTE_WAKEUP); + } + + /* Handle restarts of unfinished transfers (due to NAK or ACK) */ + ptr_pipe = (XMC_USBH0_pipe_t *)(pipe); + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { + if ((ptr_pipe->in_use == 1U) && (ptr_pipe->transfer_active == 0U)) { + /* Restart periodic transfer if not in progress and interval expired */ + if (ptr_pipe->ep_type != (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) + { + /*Data toggle if NACK not received*/ + if (!is_nack[ch]) + { + switch (ptr_pipe->packet & (uint32_t)XMC_USBH_PACKET_DATA_Msk) + { + case XMC_USBH_PACKET_DATA0: + ptr_pipe->packet &= (uint32_t)~XMC_USBH_PACKET_DATA_Msk; + ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA1; + break; + case XMC_USBH_PACKET_DATA1: + ptr_pipe->packet &= (uint32_t)~XMC_USBH_PACKET_DATA_Msk; + ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA0; + break; + default: + break; + } + } + else + { + is_nack[ch] = false; + } + } + if (((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT)&&(ptr_pipe->interrupt_triggered == 1U))|| + (ptr_pipe->ep_type != (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT)) + { + ptr_pipe->interrupt_triggered = 0U; + ptr_pipe->transfer_active = 1U; + (void)XMC_lStartTransfer (ptr_pipe, (((USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers)) + ch)); + } + } + ptr_pipe++; + } +} + +/*Function provides host mode interrupt status*/ +uint32_t XMC_USBH_GetInterruptStatus(void) +{ + return XMC_USBH0_device.global_register->GINTSTS_HOSTMODE; +} + +/*Function selects the port pin used as DRIVEVBUS*/ +void XMC_USBH_Select_VBUS(XMC_GPIO_PORT_t* port, uint32_t pin) +{ + VBUS_port = port; + VBUS_pin = pin; + + /*Configure the port pin alternate function*/ + XMC_GPIO_SetMode(VBUS_port, (uint8_t)VBUS_pin, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1); +} + +/*Function asserts the remote wakeup request by device by clearing the resume bit*/ +void XMC_USBH_TurnOffResumeBit(void) +{ + uint32_t hprt; + /*Clear resume bit*/ + hprt = XMC_USBH0_device.global_register->HPRT; + hprt &= (uint32_t)~(USB_HPRT_PrtEna_Msk); + hprt &= (uint32_t)~((uint32_t)USB_HPRT_PrtRes_Msk); + XMC_USBH0_device.global_register->HPRT = hprt; +} + + + +/*USB host driver assembling all the implementation into a single CMSIS compliant structure type*/ +XMC_USBH_DRIVER_t Driver_USBH0 = { + XMC_USBH_GetVersion, + XMC_USBH_GetCapabilities, + XMC_USBH_Initialize, + XMC_USBH_Uninitialize, + XMC_USBH_PowerControl, + XMC_USBH_PortVbusOnOff, + XMC_USBH_PortReset, + XMC_USBH_PortSuspend, + XMC_USBH_PortResume, + XMC_USBH_PortGetState, + XMC_USBH_PipeCreate, + XMC_USBH_PipeModify, + XMC_USBH_PipeDelete, + XMC_USBH_PipeReset, + XMC_USBH_PipeTransfer, + XMC_USBH_PipeTransferGetResult, + XMC_USBH_PipeTransferAbort, + XMC_USBH_GetFrameNumber +}; + + +/*Weak definition of delay function*/ +__WEAK uint8_t XMC_USBH_osDelay(uint32_t MS) +{ + /*A precise time delay implementation for this function has to be provided*/ + while (1) + { + /*Wait*/ + } +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_usic.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_usic.c new file mode 100644 index 00000000..d6f3b0c7 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_usic.c @@ -0,0 +1,373 @@ +/** + * @file xmc_usic.c + * @date 2015-09-01 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * - Documentation improved
+ * + * 2015-05-08: + * - Clearing bit fields PDIV, PCTQ, PPPEN in XMC_USIC_CH_SetBaudrate() API
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-08-27: + * - Added APIs for external input for BRG configuration:XMC_USIC_CH_ConfigExternalInputSignalToBRG()
+ * + * 2015-08-28: + * - Added asserts to XMC_USIC_CH_ConfigExternalInputSignalToBRG()
+ * + * 2015-09-01: + * - Fixed warning in the asserts
+ * + * @endcond + * + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_usic.h" +#include "xmc_scu.h" + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define USIC_CH_INPR_Msk (0x7UL) + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel) +{ + XMC_ASSERT("XMC_USIC_CH_Enable: channel not valid", XMC_USIC_IsChannelValid(channel)); + + if ((channel == XMC_USIC0_CH0) || (channel == XMC_USIC0_CH1)) + { + XMC_USIC_Enable(XMC_USIC0); + } +#if defined(USIC1) + else if((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1)) + { + XMC_USIC_Enable(XMC_USIC1); + } +#endif +#if defined(USIC2) + else if((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1)) + { + XMC_USIC_Enable(XMC_USIC2); + } +#endif + else + { + XMC_ASSERT("USIC module not available", 0U/*Always*/); + } + + /* USIC channel switched on*/ + channel->KSCFG = (USIC_CH_KSCFG_MODEN_Msk | USIC_CH_KSCFG_BPMODEN_Msk); + while ((channel->KSCFG & USIC_CH_KSCFG_MODEN_Msk) == 0U) + { + /* Wait till the channel is enabled */ + } + + /* Set USIC channel in IDLE mode */ + channel->CCR &= (uint32_t)~USIC_CH_CCR_MODE_Msk; +} + +void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel) +{ + channel->KSCFG = (uint32_t)((channel->KSCFG & (~USIC_CH_KSCFG_MODEN_Msk)) | USIC_CH_KSCFG_BPMODEN_Msk); +} + +XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling) +{ + XMC_USIC_CH_STATUS_t status; + + uint32_t peripheral_clock; + + uint32_t clock_divider; + uint32_t clock_divider_min; + + uint32_t pdiv; + uint32_t pdiv_int; + uint32_t pdiv_int_min; + + uint32_t pdiv_frac; + uint32_t pdiv_frac_min; + + /* The rate and peripheral clock are divided by 100 to be able to use only 32bit arithmetic */ + if ((rate >= 100U) && (oversampling != 0U)) + { + peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency() / 100U; + rate = rate / 100U; + + clock_divider_min = 1U; + pdiv_int_min = 1U; + pdiv_frac_min = 0x3ffU; + + for(clock_divider = 1023U; clock_divider > 0U; --clock_divider) + { + pdiv = ((peripheral_clock * clock_divider) / (rate * oversampling)); + pdiv_int = pdiv >> 10U; + pdiv_frac = pdiv & 0x3ffU; + + if ((pdiv_int < 1024U) && (pdiv_frac < pdiv_frac_min)) + { + pdiv_frac_min = pdiv_frac; + pdiv_int_min = pdiv_int; + clock_divider_min = clock_divider; + } + } + + channel->FDR = XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL | + (clock_divider_min << USIC_CH_FDR_STEP_Pos); + + channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk | + USIC_CH_BRG_PDIV_Msk | + USIC_CH_BRG_PCTQ_Msk | + USIC_CH_BRG_PPPEN_Msk)) | + ((oversampling - 1U) << USIC_CH_BRG_DCTQ_Pos) | + ((pdiv_int_min - 1U) << USIC_CH_BRG_PDIV_Pos); + + status = XMC_USIC_CH_STATUS_OK; + } + else + { + status = XMC_USIC_CH_STATUS_ERROR; + } + + return status; +} + +void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, + const uint16_t pdiv, + const uint32_t oversampling, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) +{ + XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Divider out of range", ((1U < pdiv) || (pdiv < 1024U))); + XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Oversampling out of range", ((1U < oversampling) || (oversampling < 32U))); + + /* Setting the external input frequency source through DX1 */ + XMC_USIC_CH_SetBRGInputClockSource(channel, XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T); + + /* Setting the trigger combination mode */ + XMC_USIC_CH_SetInputTriggerCombinationMode(channel,XMC_USIC_CH_INPUT_DX1,combination_mode); + + /* Configuring the dividers and oversampling */ + channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk | + USIC_CH_BRG_PDIV_Msk | + USIC_CH_BRG_PCTQ_Msk | + USIC_CH_BRG_PPPEN_Msk)) | + (((oversampling) - 1U) << USIC_CH_BRG_DCTQ_Pos) | + (((pdiv) - 1U) << USIC_CH_BRG_PDIV_Pos); +} + +void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel, + const uint32_t data_pointer, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit) +{ + /* Disable FIFO */ + channel->TBCTR &= (uint32_t)~USIC_CH_TBCTR_SIZE_Msk; + + /* LOF = 0, A standard transmit buffer event occurs when the filling level equals the limit value and gets + * lower due to transmission of a data word + * STBTEN = 0, the trigger of the standard transmit buffer event is based on the transition of the fill level + * from equal to below the limit, not the fact being below + */ + channel->TBCTR = (uint32_t)(channel->TBCTR & (uint32_t)~(USIC_CH_TBCTR_LIMIT_Msk | + USIC_CH_TBCTR_DPTR_Msk | + USIC_CH_TBCTR_SIZE_Msk)) | + (uint32_t)((limit << USIC_CH_TBCTR_LIMIT_Pos) | + (data_pointer << USIC_CH_TBCTR_DPTR_Pos) | + ((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos)); +} + + +void XMC_USIC_CH_RXFIFO_Configure(XMC_USIC_CH_t *const channel, + const uint32_t data_pointer, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit) +{ + /* Disable FIFO */ + channel->RBCTR &= (uint32_t)~USIC_CH_RBCTR_SIZE_Msk; + + /* LOF = 1, A standard receive buffer event occurs when the filling level equals the limit value and gets bigger + * due to the reception of a new data word + */ + channel->RBCTR = (uint32_t)((channel->RBCTR & (uint32_t)~(USIC_CH_RBCTR_LIMIT_Msk | + USIC_CH_RBCTR_DPTR_Msk | + USIC_CH_RBCTR_LOF_Msk)) | + ((limit << USIC_CH_RBCTR_LIMIT_Pos) | + (data_pointer << USIC_CH_RBCTR_DPTR_Pos) | + ((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos) | + (uint32_t)USIC_CH_RBCTR_LOF_Msk)); +} + +void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit) +{ + /* Disable FIFO */ + channel->TBCTR &= (uint32_t)~USIC_CH_TBCTR_SIZE_Msk; + + /* STBTEN = 0, the trigger of the standard transmit buffer event is based on the transition of the fill level + * from equal to below the limit, not the fact being below + */ + channel->TBCTR = (uint32_t)((uint32_t)(channel->TBCTR & (uint32_t)~USIC_CH_TBCTR_LIMIT_Msk) | + (limit << USIC_CH_TBCTR_LIMIT_Pos) | + ((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos)); +} + +void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit) +{ + /* Disable FIFO */ + channel->RBCTR &= (uint32_t)~USIC_CH_RBCTR_SIZE_Msk; + + channel->RBCTR = (uint32_t)((uint32_t)(channel->RBCTR & (uint32_t)~USIC_CH_RBCTR_LIMIT_Msk) | + (limit << USIC_CH_RBCTR_LIMIT_Pos) | + ((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos)); +} + +void XMC_USIC_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + channel->INPR = (uint32_t)((channel->INPR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) | + (service_request << (uint32_t)interrupt_node)); +} + +void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + channel->TBCTR = (uint32_t)((channel->TBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) | + (service_request << (uint32_t)interrupt_node)); +} + +void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + channel->RBCTR = (uint32_t)((channel->RBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) | + (service_request << (uint32_t)interrupt_node)); +} + +void XMC_USIC_Enable(XMC_USIC_t *const usic) +{ + if (usic == USIC0) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0); +#endif + } +#if defined(USIC1) + else if (usic == USIC1) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1); +#endif + } +#endif +#if defined(USIC2) + else if (usic == USIC2) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2); +#endif + } +#endif + else + { + XMC_ASSERT("USIC module not available", 0/*Always*/); + } +} + +void XMC_USIC_Disable(XMC_USIC_t *const usic) +{ + if (usic == (XMC_USIC_t *)USIC0) + { +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0); +#endif + } +#if defined(USIC1) + else if (usic == (XMC_USIC_t *)USIC1) + { +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1); +#endif + } +#endif +#if defined(USIC2) + else if (usic == (XMC_USIC_t *)USIC2) + { +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2); +#endif + } +#endif + else + { + XMC_ASSERT("USIC module not available", 0/*Always*/); + } + +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_vadc.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_vadc.c new file mode 100644 index 00000000..30298969 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_vadc.c @@ -0,0 +1,2121 @@ +/** + * @file xmc_vadc.c + * @date 2016-06-17 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-15: + * - Initial
+ * + * 2015-02-20: + * - Revised for XMC1201 device.
+ * + * 2015-04-27: + * - Added new APIs for SHS.
+ * - Added New APIs for trigger edge selection.
+ * - Added new APIs for Queue flush entries, boundary selection, Boundary node pointer.
+ * - Revised GatingMode APIs and EMUX Control Init API.
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-06-25: + * - BFL configuration in channel initialization fixed. + * + * 2015-07-28: + * - CLOCK_GATING_SUPPORTED and PERIPHERAL_RESET_SUPPORTED macros used + * - Clubbed the macro definitions for XMC13 XMC12 and XMC14 + * - Clubbed the macro definitions for XMC44 XMC47 and XMC48 + * - New APIs Created. + * - XMC_VADC_GLOBAL_SetIndividualBoundary + * - XMC_VADC_GROUP_SetIndividualBoundary + * - XMC_VADC_GROUP_GetAlias + * - XMC_VADC_GROUP_GetInputClass + * - XMC_VADC_GROUP_ChannelSetIclass + * - XMC_VADC_GROUP_ChannelGetResultAlignment + * - XMC_VADC_GROUP_ChannelGetInputClass + * - XMC_VADC_GROUP_SetResultSubtractionValue + * + * 2015-12-01: + * - Fixed the analog calibration voltage for XMC1100 to external reference upper supply range. + * - Fixed the XMC_VADC_GLOBAL_StartupCalibration() for XMC1100. + * + * 2016-06-17: + * - New macros added XMC_VADC_SHS_FULL_SET_REG, XMC_VADC_RESULT_PRIORITY_AVAILABLE + * and XMC_VADC_SYNCTR_START_LOCATION + * - New Enum added XMC_VADC_SHS_GAIN_LEVEL_t and XMC_VADC_SYNCTR_EVAL_t + * - Fixed the EVAL configuration in API XMC_VADC_GROUP_CheckSlaveReadiness and XMC_VADC_GROUP_IgnoreSlaveReadiness + * - New APIs added are: + * - XMC_VADC_GROUP_SetSyncSlaveReadySignal + * - XMC_VADC_GROUP_ChannelGetAssertedEvents + * - XMC_VADC_GROUP_GetAssertedResultEvents + * - XMC_VADC_GROUP_SetResultRegPriority + * - XMC_VADC_GROUP_SetSyncReadySignal + * - XMC_VADC_GROUP_GetSyncReadySignal + * - XMC_VADC_GROUP_GetResultRegPriority + * + * 2017-01-11: + * - Fix assertion in XMC_VADC_GROUP_CheckSlaveReadiness() and XMC_VADC_GROUP_IgnoreSlaveReadiness() checking the slave_group parameter + * + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_VADC_MAX_ICLASS_SET (2U) /**< Defines the maximum number of conversion parameter sets */ +#define XMC_VADC_NUM_EMUX_INTERFACES (2U) /**< Defines the maximum number of external multiplexer interfaces */ + +#define XMC_VADC_RESULT_LEFT_ALIGN_10BIT (2U) /**< Defines the 10 bit converted result register left align mask. It \ + is used in the XMC_VADC_GLOBAL_SetCompareValue() API */ + +#define XMC_VADC_SYNCTR_START_LOCATION (3U) /**< Defines the location in SYNCTR needed for calculations*/ +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * GLOBAL DATA + ********************************************************************************************************************/ + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) + +#if (XMC_VADC_MAXIMUM_NUM_GROUPS == 4U) +static VADC_G_TypeDef *const g_xmc_vadc_group_array[XMC_VADC_MAXIMUM_NUM_GROUPS] = {(VADC_G_TypeDef*)(void*)VADC_G0, + (VADC_G_TypeDef*)(void*)VADC_G1, + (VADC_G_TypeDef*)(void*)VADC_G2, + (VADC_G_TypeDef*)(void*)VADC_G3 }; +#else +static VADC_G_TypeDef *const g_xmc_vadc_group_array[XMC_VADC_MAXIMUM_NUM_GROUPS] = {(VADC_G_TypeDef* )(void *) VADC_G0, + (VADC_G_TypeDef* )(void *)VADC_G1 }; +#endif + +#endif + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/*API to enable the VADC Module*/ +void XMC_VADC_GLOBAL_EnableModule(void) +{ + /* + * Enable Out of Range Comparator for ADC channels pins P2.2to P2.9. This hack is applicable only for XMC1xxx devices + * and in particular the G11 step. + * + * Please refer to the XMC1000 Errata sheet V1.4 released 2014-06 Errata ID : ADC_AI.003 Additonal bit to enable ADC + * function + */ + +#if defined (COMPARATOR) + COMPARATOR->ORCCTRL = (uint32_t)0xFF; +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_VADC); +#endif + +#if defined(PERIPHERAL_RESET_SUPPORTED) + /* Reset the Hardware */ + XMC_SCU_RESET_DeassertPeripheralReset((XMC_SCU_PERIPHERAL_RESET_t)XMC_SCU_PERIPHERAL_RESET_VADC ); +#endif +} + +/*API to Disable the VADC Module*/ +void XMC_VADC_GLOBAL_DisableModule(void) +{ +#if defined(PERIPHERAL_RESET_SUPPORTED) + /* Reset the Hardware */ + XMC_SCU_RESET_AssertPeripheralReset((XMC_SCU_PERIPHERAL_RESET_t)XMC_SCU_PERIPHERAL_RESET_VADC ); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_VADC); +#endif + +} + + +/* API to initialize global resources */ +void XMC_VADC_GLOBAL_Init(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CONFIG_t *config) +{ +#if (XMC_VADC_GROUP_AVAILABLE == 0U) + uint32_t reg; +#endif + XMC_ASSERT("XMC_VADC_GLOBAL_Init:Wrong Module Pointer", (global_ptr == VADC)) + + /* Enable the VADC module*/ + XMC_VADC_GLOBAL_EnableModule(); + + global_ptr->CLC = (uint32_t)(config->clc); + + /* Clock configuration */ + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) + global_ptr->GLOBCFG = (uint32_t)(config->clock_config.globcfg | (uint32_t)(VADC_GLOBCFG_DIVWC_Msk)); +#endif + + /* ICLASS-0 configuration */ + global_ptr->GLOBICLASS[0] = (uint32_t)(config->class0.globiclass); + + /* ICLASS-1 configuration */ + global_ptr->GLOBICLASS[1] = (uint32_t)(config->class1.globiclass); + + + /*Result generation related configuration */ + global_ptr->GLOBRCR = (uint32_t)(config->globrcr); + +#if (XMC_VADC_BOUNDARY_AVAILABLE == 1U) + + /* Boundaries */ + global_ptr->GLOBBOUND = (uint32_t)(config->globbound); + +#endif + + /* Configure the SHS register that are needed for XMC11xx devices*/ +#if (XMC_VADC_GROUP_AVAILABLE == 0U) + + /* Enabling the Analog part of the converter*/ + reg = SHS0->SHSCFG | SHS_SHSCFG_SCWC_Msk; + reg &= ~(SHS_SHSCFG_ANOFF_Msk); + SHS0->SHSCFG = reg; + + /* From the Errata sheet of XMC1100 V1.7*/ + XMC_VADC_CONV_ENABLE_FOR_XMC11 = 1U; +#endif + +} + +/* API to Set the Global IClass registers*/ +void XMC_VADC_GLOBAL_InputClassInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CLASS_t config, + const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num) +{ + + XMC_ASSERT("XMC_VADC_GLOBAL_InputClassInit:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_InputClassInit:Wrong Conversion Type", ((conv_type) <= XMC_VADC_GROUP_CONV_EMUX)) + XMC_ASSERT("XMC_VADC_GLOBAL_InputClassInit:Wrong ICLASS set number", (set_num < XMC_VADC_MAX_ICLASS_SET)) + +#if(XMC_VADC_EMUX_AVAILABLE == 1U) + if (conv_type == XMC_VADC_GROUP_CONV_STD ) + { +#endif + global_ptr->GLOBICLASS[set_num] = config.globiclass & + (uint32_t)(VADC_GLOBICLASS_CMS_Msk | VADC_GLOBICLASS_STCS_Msk); +#if(XMC_VADC_EMUX_AVAILABLE == 1U) + } + else + { + global_ptr->GLOBICLASS[set_num] = config.globiclass & (uint32_t)(VADC_GLOBICLASS_CME_Msk | VADC_GLOBICLASS_STCE_Msk); + } +#endif +} + +/* API to enable startup calibration feature */ +void XMC_VADC_GLOBAL_StartupCalibration(XMC_VADC_GLOBAL_t *const global_ptr) +{ +#if (XMC_VADC_GROUP_AVAILABLE == 1U) + uint8_t i; + VADC_G_TypeDef *group_ptr; +#endif + + XMC_ASSERT("XMC_VADC_GLOBAL_StartupCalibration:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->GLOBCFG |= (uint32_t)VADC_GLOBCFG_SUCAL_Msk; + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) + /* Loop until all active groups finish calibration */ + for(i=0U; iARBCFG) & (uint32_t)VADC_G_ARBCFG_ANONS_Msk) + { + /* This group is active. Loop until it finishes calibration */ + while((group_ptr->ARBCFG) & (uint32_t)VADC_G_ARBCFG_CAL_Msk) + { + /* NOP */ + } + } + } +#else + /* Loop until it finishes calibration */ + while ((((SHS0->SHSCFG) & (uint32_t)SHS_SHSCFG_STATE_Msk) >> (uint32_t)SHS_SHSCFG_STATE_Pos) == + XMC_VADC_SHS_START_UP_CAL_ACTIVE ) + { + /* NOP */ + } +#endif +} + +/* API to set boudaries for result of conversion. Should the boundaries be violated, interrupts are generated */ +#if (XMC_VADC_BOUNDARY_AVAILABLE == 1U) +void XMC_VADC_GLOBAL_SetBoundaries(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t boundary0, + const uint32_t boundary1) +{ + uint32_t globbound; + + XMC_ASSERT("XMC_VADC_GLOBAL_SetBoundaries:Wrong Module Pointer", (global_ptr == VADC)) + + globbound = 0U; + globbound |= (uint32_t) (boundary0 << VADC_GLOBBOUND_BOUNDARY0_Pos); + globbound |= (uint32_t) (boundary1 << VADC_GLOBBOUND_BOUNDARY1_Pos); + + global_ptr->GLOBBOUND = globbound; +} + +/* API to set an individual boundary for conversion results */ +void XMC_VADC_GLOBAL_SetIndividualBoundary(XMC_VADC_GLOBAL_t *const global_ptr, + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value) +{ + + uint32_t globbound; + + XMC_ASSERT("XMC_VADC_GLOBAL_SetBoundaries:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_SetBoundaries:Wrong Boundary Selection", + ((XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND0 == selection) || + (XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND1 == selection))) + + /* Program the Boundary registers */ + globbound = global_ptr->GLOBBOUND; + + if (XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND0 == selection) + { + globbound &= ~((uint32_t) VADC_GLOBBOUND_BOUNDARY0_Msk); + globbound |= (uint32_t) ((uint32_t) boundary_value << VADC_GLOBBOUND_BOUNDARY0_Pos); + } + else if (XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND1 == selection) + { + globbound &= ~((uint32_t) VADC_GLOBBOUND_BOUNDARY1_Msk); + globbound |= (uint32_t) ((uint32_t) boundary_value << VADC_GLOBBOUND_BOUNDARY1_Pos); + } + else + { + /* For MISRA*/ + } + global_ptr->GLOBBOUND = globbound; + +} + +#endif + +/* API to set compare value for the result register. Result of conversion is compared against this compare value */ +void XMC_VADC_GLOBAL_SetCompareValue(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_RESULT_SIZE_t compare_val) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SetCompareValue:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->GLOBRES &= ~((uint32_t)VADC_GLOBRES_RESULT_Msk); + global_ptr->GLOBRES |= (uint32_t)((uint32_t)compare_val << XMC_VADC_RESULT_LEFT_ALIGN_10BIT); +} + +/* API to retrieve the result of comparison */ +XMC_VADC_FAST_COMPARE_t XMC_VADC_GLOBAL_GetCompareResult(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_VADC_FAST_COMPARE_t result; + uint32_t res; + + XMC_ASSERT("XMC_VADC_GLOBAL_GetCompareResult:Wrong Module Pointer", (global_ptr == VADC)) + + res = global_ptr->GLOBRES; + + if (res & (uint32_t)VADC_GLOBRES_VF_Msk) + { + result = (XMC_VADC_FAST_COMPARE_t)((uint32_t)(res >> (uint32_t)VADC_GLOBRES_FCR_Pos) & (uint32_t)1); + } + else + { + result = XMC_VADC_FAST_COMPARE_UNKNOWN; + } + + return result; +} + +/* Bind one of the four groups to one of the two EMUX interfaces */ +#if (XMC_VADC_EMUX_AVAILABLE == 1U) +void XMC_VADC_GLOBAL_BindGroupToEMux(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t emuxif, const uint32_t group) +{ + uint32_t mask; + uint32_t pos; + + XMC_ASSERT("XMC_VADC_GLOBAL_BindGroupToEMux:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BindGroupToEMux:Wrong EMUX Group", (emuxif < XMC_VADC_NUM_EMUX_INTERFACES)) + XMC_ASSERT("XMC_VADC_GLOBAL_BindGroupToEMux:Wrong VADC Group", (group < XMC_VADC_MAXIMUM_NUM_GROUPS)) + + if (0U == emuxif) + { + pos = (uint32_t)VADC_EMUXSEL_EMUXGRP0_Pos; + mask = (uint32_t)VADC_EMUXSEL_EMUXGRP0_Msk; + } + else + { + pos = (uint32_t)VADC_EMUXSEL_EMUXGRP1_Pos; + mask = (uint32_t)VADC_EMUXSEL_EMUXGRP1_Msk; + } + + global_ptr->EMUXSEL &= ~(mask); + global_ptr->EMUXSEL |= (uint32_t) (group << pos); + +} +#endif + +/* API to bind result event with a service request line */ +void XMC_VADC_GLOBAL_SetResultEventInterruptNode(XMC_VADC_GLOBAL_t *const global_ptr, XMC_VADC_SR_t sr) +{ + uint32_t node; + + XMC_ASSERT("XMC_VADC_GLOBAL_SetResultEventInterruptNode:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_SetResultEventInterruptNode:Wrong SR Number", (sr <= XMC_VADC_SR_SHARED_SR3)) + + if (sr >= XMC_VADC_SR_SHARED_SR0) + { + node = (uint32_t)sr - (uint32_t)XMC_VADC_SR_SHARED_SR0; + } + else + { + node = (uint32_t)sr; + } + + global_ptr->GLOBEVNP &= ~((uint32_t)VADC_GLOBEVNP_REV0NP_Msk); + global_ptr->GLOBEVNP |= (uint32_t)(node << VADC_GLOBEVNP_REV0NP_Pos); +} + +/* API to bind request source event with a service request line */ +void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *const global_ptr, XMC_VADC_SR_t sr) +{ + uint32_t node; + + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode:Wrong Module Pointer", (global_ptr == VADC)) + + if (sr >= XMC_VADC_SR_SHARED_SR0) + { + node = (uint32_t)sr - (uint32_t)XMC_VADC_SR_SHARED_SR0; + } + else + { + node = (uint32_t)sr; + } + + global_ptr->GLOBEVNP &= ~((uint32_t)VADC_GLOBEVNP_SEV0NP_Msk); + global_ptr->GLOBEVNP |= (uint32_t) (node << VADC_GLOBEVNP_SEV0NP_Pos); +} + +/* API to initialize an instance of group of VADC hardware */ +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +void XMC_VADC_GROUP_Init( XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_CONFIG_t *config) +{ + XMC_ASSERT("XMC_VADC_GROUP_Init:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Program the input classes */ + XMC_VADC_GROUP_InputClassInit(group_ptr, config->class0, XMC_VADC_GROUP_CONV_STD, 0U); + XMC_VADC_GROUP_InputClassInit(group_ptr, config->class0, XMC_VADC_GROUP_CONV_EMUX, 0U); + XMC_VADC_GROUP_InputClassInit(group_ptr, config->class1, XMC_VADC_GROUP_CONV_STD, 1U); + XMC_VADC_GROUP_InputClassInit(group_ptr, config->class1, XMC_VADC_GROUP_CONV_EMUX, 1U); + + group_ptr->ARBCFG = config->g_arbcfg; + + group_ptr->BOUND = config->g_bound; + + /* External mux configuration */ + XMC_VADC_GROUP_ExternalMuxControlInit(group_ptr,config->emux_config); + +} + +/* API to program conversion characteristics */ +void XMC_VADC_GROUP_InputClassInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_CLASS_t config, + const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num) +{ + uint32_t conv_class; + uint32_t conv_mode_pos; + uint32_t sample_time_pos; + uint32_t conv_mode_mask; + uint32_t sample_time_mask; + uint32_t sample_time; + XMC_VADC_CONVMODE_t conv_mode; + + XMC_ASSERT("XMC_VADC_GROUP_InputClassInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_InputClassInit:Wrong Conversion Type", ((conv_type) <= XMC_VADC_GROUP_CONV_EMUX)) + XMC_ASSERT("XMC_VADC_GROUP_InputClassInit:Wrong ICLASS set number", (set_num < XMC_VADC_MAX_ICLASS_SET)) + + /* + * Obtain the mask and position macros of the parameters based on what is being requested - Standard channels vs + * external mux channels. + */ + if (XMC_VADC_GROUP_CONV_STD == conv_type) + { + conv_mode_pos = (uint32_t) VADC_G_ICLASS_CMS_Pos; + conv_mode_mask = (uint32_t) VADC_G_ICLASS_CMS_Msk; + sample_time_pos = (uint32_t) VADC_G_ICLASS_STCS_Pos; + sample_time_mask = (uint32_t) VADC_G_ICLASS_STCS_Msk; + sample_time = (uint32_t) config.sample_time_std_conv; + conv_mode = (XMC_VADC_CONVMODE_t)config.conversion_mode_standard; + } + else + { + conv_mode_pos = (uint32_t) VADC_G_ICLASS_CME_Pos; + conv_mode_mask = (uint32_t) VADC_G_ICLASS_CME_Msk; + sample_time_pos = (uint32_t) VADC_G_ICLASS_STCE_Pos; + sample_time_mask = (uint32_t) VADC_G_ICLASS_STCE_Msk; + sample_time = (uint32_t) config.sampling_phase_emux_channel; + conv_mode = (XMC_VADC_CONVMODE_t)config.conversion_mode_emux; + } + + /* Determine the class */ + conv_class = group_ptr->ICLASS[set_num]; + + /* Program the class register */ + conv_class &= ~(conv_mode_mask); + conv_class |= (uint32_t)((uint32_t) conv_mode << conv_mode_pos); + conv_class &= ~(sample_time_mask); + conv_class |= (uint32_t)(sample_time << sample_time_pos); + group_ptr->ICLASS[set_num] = conv_class; +} + +/* API which sets the power mode of analog converter of a VADC group */ +void XMC_VADC_GROUP_SetPowerMode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_POWERMODE_t power_mode) +{ + uint32_t arbcfg; + + XMC_ASSERT("XMC_VADC_GROUP_SetPowerMode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetPowerMode:Wrong Power Mode", (power_mode <= XMC_VADC_GROUP_POWERMODE_NORMAL)) + + arbcfg = group_ptr->ARBCFG; + + arbcfg &= ~((uint32_t)VADC_G_ARBCFG_ANONC_Msk); + arbcfg |= (uint32_t)power_mode; + + group_ptr->ARBCFG = arbcfg; +} + +/* API which programs a group as a slave group during sync conversions */ +void XMC_VADC_GROUP_SetSyncSlave(XMC_VADC_GROUP_t *const group_ptr, uint32_t master_grp, uint32_t slave_grp) +{ + uint32_t synctr; + #if (XMC_VADC_MULTIPLE_SLAVEGROUPS == 1U ) + #endif + XMC_ASSERT("XMC_VADC_GROUP_SetSyncSlave:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + #if (XMC_VADC_MULTIPLE_SLAVEGROUPS == 1U ) + + /* Determine the coding of SYNCTR */ + if (slave_grp > master_grp) + { + master_grp = master_grp + 1U; + } + #endif + + /* Program SYNCTR */ + synctr = group_ptr->SYNCTR; + synctr &= ~((uint32_t)VADC_G_SYNCTR_STSEL_Msk); + synctr |= master_grp; + group_ptr->SYNCTR = synctr; +} + +/* API which programs a group as a master group during sync conversions */ +void XMC_VADC_GROUP_SetSyncMaster(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t synctr; + + XMC_ASSERT("XMC_VADC_GROUP_SetSyncMaster:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + synctr = group_ptr->SYNCTR; + synctr &= ~((uint32_t)VADC_G_SYNCTR_STSEL_Msk); + group_ptr->SYNCTR = synctr; +} + +/* API to enable checking of readiness of slaves before a synchronous conversion request is issued */ +void XMC_VADC_GROUP_CheckSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group) +{ + uint32_t i,master_grp_num; + XMC_ASSERT("XMC_VADC_GROUP_CheckSlaveReadiness:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_CheckSlaveReadiness:Wrong Slave group", ((slave_group >= 0) && (slave_group <= (XMC_VADC_MAXIMUM_NUM_GROUPS - 1)))) + + master_grp_num =0; + for(i=0; iSYNCTR |= (1U << (slave_group + XMC_VADC_SYNCTR_START_LOCATION)); +} + +/* API to disable checking of readiness of slaves during synchronous conversions */ +void XMC_VADC_GROUP_IgnoreSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group) +{ + uint32_t i,master_grp_num; + XMC_ASSERT("XMC_VADC_GROUP_IgnoreSlaveReadiness:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_IgnoreSlaveReadiness:Wrong Slave group", ((slave_group >= 0) && (slave_group <= (XMC_VADC_MAXIMUM_NUM_GROUPS - 1)))) + + master_grp_num =0; + for(i=0; iSYNCTR &= ~(1U << (slave_group + XMC_VADC_SYNCTR_START_LOCATION)); +} + +/* API to configure EVAL bit in the slave groups*/ +void XMC_VADC_GROUP_SetSyncSlaveReadySignal(XMC_VADC_GROUP_t *const group_ptr, + uint32_t eval_waiting_group, + uint32_t eval_origin_group) +{ + XMC_ASSERT("XMC_VADC_GROUP_SetSyncSlaveReadySignal:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetSyncSlaveReadySignal:Wrong Group numbers", (eval_waiting_group == eval_origin_group )) + + if(eval_origin_group < eval_waiting_group) + { + eval_origin_group++; + } + group_ptr->SYNCTR |= (1U << (eval_origin_group + XMC_VADC_SYNCTR_START_LOCATION)); +} + + +/* API to enable the synchronous conversion feature - Applicable only to kernel configured as master */ +void XMC_VADC_GROUP_EnableChannelSyncRequest(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + uint32_t synctr; + + XMC_ASSERT("XMC_VADC_GROUP_EnableChannelSyncRequest:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_EnableChannelSyncRequest:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + synctr = group_ptr->SYNCTR; + + if (!(synctr & (uint32_t)VADC_G_SYNCTR_STSEL_Msk)) + { + group_ptr->CHCTR[ch_num] |= (uint32_t)((uint32_t)1 << VADC_G_CHCTR_SYNC_Pos); + } +} + +/* API to disable synchronous conversion feature */ +void XMC_VADC_GROUP_DisableChannelSyncRequest(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + uint32_t synctr; + + XMC_ASSERT("XMC_VADC_GROUP_DisableChannelSyncRequest:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_DisableChannelSyncRequest:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + synctr = group_ptr->SYNCTR; + + if (synctr & (uint32_t)VADC_G_SYNCTR_STSEL_Msk) + { + group_ptr->CHCTR[ch_num] &= ~((uint32_t)VADC_G_CHCTR_SYNC_Msk); + } +} + +/* API to retrieve the converter state - Idle vs Busy */ +XMC_VADC_GROUP_STATE_t XMC_VADC_GROUP_IsConverterBusy(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t arbcfg; + + XMC_ASSERT("XMC_VADC_GROUP_IsConverterBusy:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + arbcfg = group_ptr->ARBCFG; + arbcfg &= (uint32_t)VADC_G_ARBCFG_BUSY_Msk; + arbcfg = arbcfg >> VADC_G_ARBCFG_BUSY_Pos; + + return( (XMC_VADC_GROUP_STATE_t)arbcfg); +} + +/* API to set boundaries for conversion results */ +void XMC_VADC_GROUP_SetBoundaries(XMC_VADC_GROUP_t *const group_ptr, const uint32_t boundary0, const uint32_t boundary1) +{ + uint32_t bound; + + XMC_ASSERT("XMC_VADC_GROUP_SetBoundaries:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Program the Boundary registers */ + bound = group_ptr->BOUND; + bound &= ~((uint32_t) VADC_G_BOUND_BOUNDARY0_Msk); + bound &= ~((uint32_t) VADC_G_BOUND_BOUNDARY1_Msk); + bound |= (uint32_t) ((uint32_t) boundary0 << VADC_G_BOUND_BOUNDARY0_Pos); + bound |= (uint32_t) ((uint32_t) boundary1 << VADC_G_BOUND_BOUNDARY1_Pos); + group_ptr->BOUND = bound; +} + +/* API to set an individual boundary for conversion results */ +void XMC_VADC_GROUP_SetIndividualBoundary(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value) +{ + + uint32_t bound; + + XMC_ASSERT("XMC_VADC_GROUP_SetIndividualBoundary:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetIndividualBoundary:Wrong Boundary Selection", + ((XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0 == selection) || + (XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND1 == selection))) + + /* Program the Boundary registers */ + bound = group_ptr->BOUND; + if (XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0 == selection) + { + bound &= ~((uint32_t) VADC_G_BOUND_BOUNDARY0_Msk); + bound |= (uint32_t) ((uint32_t) boundary_value << VADC_G_BOUND_BOUNDARY0_Pos); + } + else if (XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND1 == selection) + { + bound &= ~((uint32_t) VADC_G_BOUND_BOUNDARY1_Msk); + bound |= (uint32_t) ((uint32_t) boundary_value << VADC_G_BOUND_BOUNDARY1_Pos); + } + else + { + /* For MISRA*/ + } + group_ptr->BOUND = bound; + +} + +/* Manually assert service request (Interrupt) to NVIC */ +void XMC_VADC_GROUP_TriggerServiceRequest(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t sr_num, + const XMC_VADC_GROUP_IRQ_t type) +{ + uint32_t sract; + + XMC_ASSERT("XMC_VADC_GROUP_TriggerServiceRequest:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_TriggerServiceRequest:Wrong SR number", (sr_num <= XMC_VADC_SR_SHARED_SR3)) + XMC_ASSERT("XMC_VADC_GROUP_TriggerServiceRequest:Wrong SR type", ((type)<= XMC_VADC_GROUP_IRQ_SHARED)) + + sract = group_ptr->SRACT; + + if (XMC_VADC_GROUP_IRQ_KERNEL == type) + { + sract |= (uint32_t)((uint32_t)1 << sr_num); + } + else + { + sract |= (uint32_t)((uint32_t)1 << (sr_num + (uint32_t)8)); + } + + group_ptr->SRACT = sract; +} + +#if XMC_VADC_BOUNDARY_FLAG_SELECT == 1U + +/* API to set the SR line for the Boundary flag node pointer*/ +void XMC_VADC_GROUP_SetBoundaryEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint8_t boundary_flag_num, + const XMC_VADC_BOUNDARY_NODE_t sr) +{ + uint32_t flag_pos; + XMC_ASSERT("XMC_VADC_GROUP_SetBoundaryEventInterruptNode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Program the GxBFLNP */ + flag_pos = (uint32_t)boundary_flag_num << (uint32_t)2; + group_ptr->BFLNP &= ~((uint32_t)VADC_G_BFLNP_BFL0NP_Msk << flag_pos); + group_ptr->BFLNP |= (uint32_t)sr << flag_pos; +} + +#endif + +#endif + +#if(XMC_VADC_SHS_AVAILABLE == 1U) + +/* API to Initialize the Sample and hold features*/ +void XMC_VADC_GLOBAL_SHS_Init(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, const XMC_VADC_GLOBAL_SHS_CONFIG_t *config) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_Init:Wrong SHS Pointer", (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_Init:Wrong Index number",(config == (XMC_VADC_GLOBAL_SHS_CONFIG_t*)NULL)) + + /* Initialize the SHS Configuration register*/ + shs_ptr->SHSCFG = (uint32_t)((uint32_t)config->shscfg | (uint32_t)SHS_SHSCFG_SCWC_Msk); + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) + /* Select the Calibration order*/ + shs_ptr->CALCTR &= ~((uint32_t)SHS_CALCTR_CALORD_Msk); + shs_ptr->CALCTR |= (uint32_t) ((uint32_t)config->calibration_order << SHS_CALCTR_CALORD_Pos); +#endif +} + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/* API to enable the accelerated mode of conversion */ +void XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, XMC_VADC_GROUP_INDEX_t group_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) + + /* Set the converted to Accelerated mode from compatible mode*/ + if (group_num == XMC_VADC_GROUP_INDEX_0 ) + { + shs_ptr->TIMCFG0 |= (uint32_t)SHS_TIMCFG0_AT_Msk; + } + else if (group_num == XMC_VADC_GROUP_INDEX_1 ) + { + shs_ptr->TIMCFG1 |= (uint32_t)SHS_TIMCFG1_AT_Msk; + } + else + { + /* for MISRA*/ + } +} + +/* API to disable the accelerated mode of conversion */ +void XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, XMC_VADC_GROUP_INDEX_t group_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) + + /* Set the converted to Accelerated mode from compatible mode*/ + if (group_num == XMC_VADC_GROUP_INDEX_0 ) + { + shs_ptr->TIMCFG0 &= ~(uint32_t)SHS_TIMCFG0_AT_Msk; + } + else if (group_num == XMC_VADC_GROUP_INDEX_1 ) + { + shs_ptr->TIMCFG1 &= ~(uint32_t)SHS_TIMCFG1_AT_Msk; + } + else + { + /* for MISRA*/ + } +} + +/* API to set the Short sample time of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_SetShortSampleTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + uint8_t sst_value) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetShortSampleTime:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetShortSampleTime:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetShortSampleTime:Wrong SST value",(sst_value < 64U)) + + /* Set the short sample time for the Accelerated mode of operation*/ + if (group_num == XMC_VADC_GROUP_INDEX_0 ) + { + shs_ptr->TIMCFG0 &= ~((uint32_t)SHS_TIMCFG0_SST_Msk); + shs_ptr->TIMCFG0 |= (uint32_t)((uint32_t)sst_value << SHS_TIMCFG0_SST_Pos ); + } + else if (group_num == XMC_VADC_GROUP_INDEX_1 ) + { + shs_ptr->TIMCFG1 &= ~((uint32_t)SHS_TIMCFG1_SST_Msk); + shs_ptr->TIMCFG1 |= (uint32_t)((uint32_t)sst_value << SHS_TIMCFG1_SST_Pos ); + } + else + { + /* for MISRA*/ + } +} +#endif + +/* API to set the gain factor of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_SetGainFactor(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + uint8_t gain_value, + XMC_VADC_GROUP_INDEX_t group_num, + uint8_t ch_num) +{ + uint32_t ch_mask; + + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetGainFactor:Wrong SHS Pointer", (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetGainFactor:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) + + /*Calculate location of channel bit-field*/ + ch_mask = ((uint32_t)ch_num << (uint32_t)2); + if (group_num == XMC_VADC_GROUP_INDEX_0 ) + { + shs_ptr->GNCTR00 &= ~((uint32_t)SHS_GNCTR00_GAIN0_Msk << ch_mask) ; + shs_ptr->GNCTR00 |= ((uint32_t)gain_value << ch_mask); + } + else if (group_num == XMC_VADC_GROUP_INDEX_1 ) + { + shs_ptr->GNCTR10 &= ~((uint32_t)SHS_GNCTR10_GAIN0_Msk << ch_mask); + shs_ptr->GNCTR10 |= ((uint32_t)gain_value << ch_mask); + } + else + { + /* for MISRA*/ + } +} + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/* API to enable the gain and offset calibration of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations:Wrong group selected", + (group_num <= (uint32_t)XMC_VADC_GROUP_INDEX_1)) + + /* Enable gain and offset calibration*/ + if ( XMC_VADC_GROUP_INDEX_0 == group_num) + { + shs_ptr->CALOC0 &= ~((uint32_t)SHS_CALOC0_DISCAL_Msk); + } + else if ( XMC_VADC_GROUP_INDEX_1 == group_num) + { + shs_ptr->CALOC1 &= ~((uint32_t)SHS_CALOC1_DISCAL_Msk); + } + else + { + /* for MISRA */ + } +} + +/* API to enable the gain and offset calibration of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations:Wrong group selected", + (group_num <= (uint32_t)XMC_VADC_GROUP_INDEX_1)) + + if ( XMC_VADC_GROUP_INDEX_0 == group_num) + { + shs_ptr->CALOC0 |= (uint32_t)SHS_CALOC0_DISCAL_Msk; + } + else if ( XMC_VADC_GROUP_INDEX_1 == group_num) + { + shs_ptr->CALOC1 |= (uint32_t)SHS_CALOC1_DISCAL_Msk; + } + else + { + /* for MISRA */ + } +} + +/* API to get the offset calibration value of the Sample and hold module*/ +uint8_t XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level) +{ + uint32_t calibration_value; + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue:Wrong Group number selected", + (group_num == XMC_VADC_GROUP_INDEX_0)||(group_num == XMC_VADC_GROUP_INDEX_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue:Wrong gain level selected", + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_0)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_1)|| + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_2)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_3)) + + calibration_value = 0U; + if ( XMC_VADC_GROUP_INDEX_0 == group_num) + { + calibration_value = (shs_ptr->CALOC0 >> (uint32_t)gain_level) & (uint32_t)SHS_CALOC0_CALOFFVAL0_Msk; + } + else if ( XMC_VADC_GROUP_INDEX_1 == group_num) + { + calibration_value = (shs_ptr->CALOC1 >> (uint32_t)gain_level) & (uint32_t)SHS_CALOC1_CALOFFVAL0_Msk; + } + else + { + /* for MISRA */ + } + return ((uint8_t)calibration_value); +} + +/* API to set the offset calibration value of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level, + uint8_t offset_calibration_value) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue:Wrong Group number selected", + (group_num == XMC_VADC_GROUP_INDEX_0)||(group_num == XMC_VADC_GROUP_INDEX_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue:Wrong gain level selected", + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_0)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_1)|| + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_2)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_3)) + + if ( XMC_VADC_GROUP_INDEX_0 == group_num) + { + shs_ptr->CALOC0 = (shs_ptr->CALOC0 & ~((uint32_t)SHS_CALOC0_CALOFFVAL0_Msk << (uint32_t)gain_level)) | + (uint32_t)SHS_CALOC0_OFFWC_Msk; + shs_ptr->CALOC0 |= ((uint32_t)offset_calibration_value << (uint32_t)gain_level) | (uint32_t)SHS_CALOC0_OFFWC_Msk; + } + else if ( XMC_VADC_GROUP_INDEX_1 == group_num) + { + shs_ptr->CALOC1 = (shs_ptr->CALOC1 & ~((uint32_t)SHS_CALOC1_CALOFFVAL0_Msk << (uint32_t)gain_level)) | + (uint32_t)SHS_CALOC1_OFFWC_Msk; + shs_ptr->CALOC1 |= ((uint32_t)offset_calibration_value << (uint32_t)gain_level) | (uint32_t)SHS_CALOC1_OFFWC_Msk; + } + else + { + /* for MISRA */ + } +} +#endif + +/* API to set the values of sigma delta loop of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_LOOP_CH_t loop_select, + uint8_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong Group number selected", + (group_num == XMC_VADC_GROUP_INDEX_0)||(group_num == XMC_VADC_GROUP_INDEX_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong Delta sigma loop selected", + (loop_select == XMC_VADC_SHS_LOOP_CH_0)||(loop_select == XMC_VADC_SHS_LOOP_CH_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + shs_ptr->LOOP &= ~(((uint32_t)SHS_LOOP_LPCH0_Msk | (uint32_t)SHS_LOOP_LPSH0_Msk | (uint32_t)SHS_LOOP_LPEN0_Msk) + << (uint32_t)loop_select); + shs_ptr->LOOP |= ((uint32_t)ch_num | ((uint32_t)group_num << (uint32_t)SHS_LOOP_LPSH0_Pos)) << (uint32_t)loop_select; + +} + +#endif + +#if (XMC_VADC_GSCAN_AVAILABLE == 1U) +/* API to initialize the group scan hardware of a kernel */ +void XMC_VADC_GROUP_ScanInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SCAN_CONFIG_t *config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_VADC_GROUP_ScanInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* All configurations have to be performed with the arbitration slot disabled */ + XMC_VADC_GROUP_ScanDisableArbitrationSlot(group_ptr); + + /* Read in the existing contents of arbitration priority register */ + reg = group_ptr->ARBPR; + + /* Program the priority of the request source */ + reg &= ~(uint32_t)VADC_G_ARBPR_PRIO1_Msk; + reg |= (uint32_t)((uint32_t)config->req_src_priority << VADC_G_ARBPR_PRIO1_Pos); + + /* Program the start mode */ + if (XMC_VADC_STARTMODE_WFS != (XMC_VADC_STARTMODE_t)(config->conv_start_mode)) + { + reg |= (uint32_t)(VADC_G_ARBPR_CSM1_Msk); + } + + group_ptr->ARBPR = reg; + + group_ptr->ASCTRL = (uint32_t)(config->asctrl |(VADC_G_ASCTRL_XTWC_Msk) |(VADC_G_ASCTRL_GTWC_Msk) | + (VADC_G_ASCTRL_TMWC_Msk)); + + group_ptr->ASMR = (uint32_t)((config->asmr)| (uint32_t)((uint32_t)XMC_VADC_GATEMODE_IGNORE << VADC_G_ASMR_ENGT_Pos)); + + if (XMC_VADC_STARTMODE_CNR == (XMC_VADC_STARTMODE_t)(config->conv_start_mode)) + { + group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_RPTDIS_Msk; + } + + /* Enable arbitration slot now */ + XMC_VADC_GROUP_ScanEnableArbitrationSlot(group_ptr); + +} + +/* API to select one of the 16 inputs as a trigger input for Group Scan request source */ +void XMC_VADC_GROUP_ScanSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_TRIGGER_INPUT_SELECT_t trigger_input) +{ + uint32_t scanctrl; + + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTrigger:Wrong Trigger Port", ((trigger_input)< XMC_VADC_NUM_PORTS)) + + scanctrl = group_ptr->ASCTRL; + scanctrl |= (uint32_t) VADC_G_ASCTRL_XTWC_Msk; + scanctrl &= ~((uint32_t)VADC_G_ASCTRL_XTSEL_Msk); + scanctrl |= (uint32_t)((uint32_t)trigger_input << VADC_G_ASCTRL_XTSEL_Pos); + group_ptr->ASCTRL = scanctrl; +} + +/* Select a trigger edge*/ +void XMC_VADC_GROUP_ScanSelectTriggerEdge(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_TRIGGER_EDGE_t trigger_edge) +{ + uint32_t scanctrl; + + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTriggerEdge:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTriggerEdge:Wrong Trigger Port", ((trigger_edge)<= XMC_VADC_TRIGGER_EDGE_ANY)) + + scanctrl = group_ptr->ASCTRL; + scanctrl |= (uint32_t) VADC_G_ASCTRL_XTWC_Msk; + scanctrl &= ~((uint32_t)VADC_G_ASCTRL_XTMODE_Msk); + scanctrl |= (uint32_t)((uint32_t)trigger_edge << VADC_G_ASCTRL_XTMODE_Pos); + group_ptr->ASCTRL = scanctrl; +} + +/* API to select one of the 16 inputs as a trigger gating input for Group Scan request source */ +void XMC_VADC_GROUP_ScanSelectGating(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_GATE_INPUT_SELECT_t gating_input) +{ + uint32_t scanctrl; + + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectGating:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectGating:Wrong Gating Port", ((gating_input)< XMC_VADC_NUM_PORTS)) + + scanctrl = group_ptr->ASCTRL; + scanctrl |= (uint32_t)VADC_G_ASCTRL_GTWC_Msk; + scanctrl &= ~((uint32_t)VADC_G_ASCTRL_GTSEL_Msk); + scanctrl |= (uint32_t)((uint32_t)gating_input << VADC_G_ASCTRL_GTSEL_Pos); + group_ptr->ASCTRL = scanctrl; +} + +/* API to stop an ongoing conversion of a sequence */ +void XMC_VADC_GROUP_ScanSequenceAbort(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t asctrl; + bool arbitration_status; + + XMC_ASSERT("XMC_VADC_GROUP_ScanSequenceAbort:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* To disable trigger and gating before abort*/ + asctrl = group_ptr->ASCTRL; + + group_ptr->ASCTRL =(0U | (uint32_t)VADC_G_ASCTRL_XTWC_Msk | + (uint32_t)VADC_G_ASCTRL_GTWC_Msk | (uint32_t)VADC_G_ASCTRL_TMWC_Msk ); + + /* To disable Arbitration before abort*/ + arbitration_status = (bool)((uint32_t)(group_ptr->ARBPR >> VADC_G_ARBPR_ASEN1_Pos) & 1U); + XMC_VADC_GROUP_ScanDisableArbitrationSlot(group_ptr); + + group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_ENGT_Msk); + group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_CLRPND_Msk; + + /* Enable the arbitration slot 1*/ + group_ptr->ARBPR |= (uint32_t)((uint32_t)arbitration_status << VADC_G_ARBPR_ASEN1_Pos); + + /* Enable any disabled gating*/ + group_ptr->ASCTRL =(asctrl | (uint32_t)VADC_G_ASCTRL_XTWC_Msk | + (uint32_t)VADC_G_ASCTRL_GTWC_Msk | (uint32_t)VADC_G_ASCTRL_TMWC_Msk ); +} + +/* API to find out number of channels awaiting conversion */ +uint32_t XMC_VADC_GROUP_ScanGetNumChannelsPending(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t reg; + uint32_t i; + uint32_t count; + + XMC_ASSERT("XMC_VADC_GROUP_ScanGetNumChannelsPending:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + + count = 0U; + + if (group_ptr->ASPND) + { + reg = group_ptr->ASPND; + + for(i=0U;i> (uint32_t)1); + } + } + + return count; +} + +/* API to select a service request line (NVIC Node) for request source event */ +void XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SR_t sr) +{ + uint32_t sevnp; + sevnp = group_ptr->SEVNP; + + XMC_ASSERT("XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode:Wrong Service Request", ((sr) <= XMC_VADC_SR_SHARED_SR3)) + + sevnp &= ~((uint32_t)VADC_G_SEVNP_SEV1NP_Msk); + sevnp |= (uint32_t)((uint32_t)sr << VADC_G_SEVNP_SEV1NP_Pos); + + group_ptr->SEVNP = sevnp; +} + +/* Removes the selected channel from conversion*/ +void XMC_VADC_GROUP_ScanRemoveChannel(XMC_VADC_GROUP_t *const group_ptr, const uint32_t channel_num) +{ + uint32_t assel; + + XMC_ASSERT("XMC_VADC_GROUP_ScanRemoveChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanRemoveChannel:Wrong channel number", ((channel_num)< XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + assel = group_ptr->ASSEL; + assel &= (~( 1 << channel_num)); + group_ptr->ASSEL = assel; +} +#endif + +/* API to initialize background scan request source hardware */ +void XMC_VADC_GLOBAL_BackgroundInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_BACKGROUND_CONFIG_t *config) +{ + #if (XMC_VADC_GROUP_AVAILABLE ==1U) + uint8_t i; + uint32_t reg; + uint32_t conv_start_mask; + #endif + + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundInit:Wrong Module Pointer", (global_ptr == VADC)) + + #if (XMC_VADC_GROUP_AVAILABLE ==1U) + for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + XMC_VADC_GROUP_BackgroundDisableArbitrationSlot((XMC_VADC_GROUP_t *)g_xmc_vadc_group_array[i]); + } + + conv_start_mask = (uint32_t) 0; + if (XMC_VADC_STARTMODE_WFS != (XMC_VADC_STARTMODE_t)config->conv_start_mode) + { + conv_start_mask = (uint32_t)VADC_G_ARBPR_CSM2_Msk; + } + + for(i=0U; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + reg = g_xmc_vadc_group_array[i]->ARBPR; + + reg &= ~(uint32_t)(VADC_G_ARBPR_PRIO2_Msk); + + /* Program the priority of the request source */ + reg |= (uint32_t)((uint32_t)config->req_src_priority << VADC_G_ARBPR_PRIO2_Pos); + + /* Program the start mode */ + reg |= conv_start_mask; + + g_xmc_vadc_group_array[i]->ARBPR = reg; + + } + #endif + + /* program BRSCTRL register */ + global_ptr->BRSCTRL = (uint32_t)(config->asctrl | (uint32_t)VADC_BRSCTRL_XTWC_Msk | (uint32_t)VADC_BRSCTRL_GTWC_Msk); + + /* program BRSMR register */ + global_ptr->BRSMR = (uint32_t)((config->asmr)| (uint32_t)((uint32_t)XMC_VADC_GATEMODE_IGNORE << VADC_BRSMR_ENGT_Pos)); + +#if (XMC_VADC_GROUP_AVAILABLE ==1U) + if (XMC_VADC_STARTMODE_CNR == (XMC_VADC_STARTMODE_t)(config->conv_start_mode)) + { + global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_RPTDIS_Msk; + } +#endif + + #if (XMC_VADC_GROUP_AVAILABLE ==1U) + for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + XMC_VADC_GROUP_BackgroundEnableArbitrationSlot((XMC_VADC_GROUP_t *)g_xmc_vadc_group_array[i]); + } + #endif + +} + +/* API to select one of the 16 inputs as a trigger for background scan request source */ +void XMC_VADC_GLOBAL_BackgroundSelectTrigger(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t input_num) +{ + uint32_t scanctrl; + + XMC_ASSERT("VADC_BCKGND_SelectTriggerInput:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectTrigger:Wrong Trigger Port", ((input_num)< XMC_VADC_NUM_PORTS)) + + + scanctrl = global_ptr->BRSCTRL; + scanctrl |= (uint32_t)VADC_BRSCTRL_XTWC_Msk; + scanctrl &= ~((uint32_t)VADC_BRSCTRL_XTSEL_Msk); + scanctrl |= (uint32_t)(input_num << VADC_BRSCTRL_XTSEL_Pos); + global_ptr->BRSCTRL = scanctrl; +} + +/* Select a trigger edge*/ +void XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge(XMC_VADC_GLOBAL_t *const global_ptr, + const XMC_VADC_TRIGGER_EDGE_t trigger_edge) +{ + uint32_t scanctrl; + + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge:Wrong Global Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge:Wrong Trigger Port", + ((trigger_edge)<= XMC_VADC_TRIGGER_EDGE_ANY)) + + scanctrl = global_ptr->BRSCTRL; + scanctrl |= (uint32_t) VADC_BRSCTRL_XTWC_Msk; + scanctrl &= ~((uint32_t)VADC_BRSCTRL_XTMODE_Msk); + scanctrl |= (uint32_t)((uint32_t)trigger_edge << VADC_BRSCTRL_XTMODE_Pos); + global_ptr->BRSCTRL = scanctrl; +} + + +/* API to select one of the 16 inputs as a trigger gate for background scan request source */ +void XMC_VADC_GLOBAL_BackgroundSelectGating(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t input_num) +{ + uint32_t scanctrl; + + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectGating:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectGating:Wrong Gating Port", ((input_num)< XMC_VADC_NUM_PORTS)) + + scanctrl = global_ptr->BRSCTRL; + scanctrl |= (uint32_t)VADC_BRSCTRL_GTWC_Msk; + scanctrl &= ~((uint32_t)VADC_BRSCTRL_GTSEL_Msk); + scanctrl |= (uint32_t)(input_num << VADC_BRSCTRL_GTSEL_Pos); + global_ptr->BRSCTRL = scanctrl; +} + +/* API to abort ongoing conversion of a sequence */ +void XMC_VADC_GLOBAL_BackgroundAbortSequence(XMC_VADC_GLOBAL_t *const global_ptr) +{ + uint32_t brsctrl; +#if (XMC_VADC_GROUP_AVAILABLE ==1U) + uint32_t i; + uint8_t grp_asen2_flag[XMC_VADC_MAXIMUM_NUM_GROUPS]; +#endif + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAbortSequence:Wrong Module Pointer", (global_ptr == VADC)) + + /* To disable trigger and gating before abort*/ + brsctrl = global_ptr->BRSCTRL; + + global_ptr->BRSCTRL =(0U | (uint32_t)VADC_BRSCTRL_XTWC_Msk | (uint32_t)VADC_BRSCTRL_GTWC_Msk); + + /* Disable Background Request source */ + +#if (XMC_VADC_GROUP_AVAILABLE ==1U) + for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + grp_asen2_flag[i] = (uint8_t)(g_xmc_vadc_group_array[i]->ARBPR >> VADC_G_ARBPR_ASEN2_Pos); + XMC_VADC_GROUP_BackgroundDisableArbitrationSlot((XMC_VADC_GROUP_t *)g_xmc_vadc_group_array[i]); + } +#endif + + /* Abort the ongoing sequence */ + global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_CLRPND_Msk; + +#if (XMC_VADC_GROUP_AVAILABLE ==1U) + /* Enable Background Request source */ + for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + if ((uint8_t)1 == grp_asen2_flag[i]) + { + XMC_VADC_GROUP_BackgroundEnableArbitrationSlot((XMC_VADC_GROUP_t*)g_xmc_vadc_group_array[i]); + } + } +#endif + + /* Re-enable any disabled trigger and gating*/ + global_ptr->BRSCTRL =(brsctrl | (uint32_t)VADC_BRSCTRL_XTWC_Msk | (uint32_t)VADC_BRSCTRL_GTWC_Msk); +} + +/* API to determine how many channels are awaiting conversion */ +uint32_t XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending(XMC_VADC_GLOBAL_t *const global_ptr) +{ + uint32_t reg; + uint32_t i; + uint32_t j; + uint32_t count; + + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending:Wrong Module Pointer", (global_ptr == VADC)) + + count = 0U; + + /* Loop through all groups and find out who is awaiting conversion */ + for(i = 0U; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + if (global_ptr->BRSSEL[i]) + { + reg = global_ptr->BRSPND[i]; + + for(j=0U;j> 1U; + } + } + } + + return count; +} + +#if (XMC_VADC_QUEUE_AVAILABLE == 1U) +/* API to initialize queue request source */ +void XMC_VADC_GROUP_QueueInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_QUEUE_CONFIG_t *config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_VADC_GROUP_QueueInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Disable arbitration slot of the queue request source */ + XMC_VADC_GROUP_QueueDisableArbitrationSlot(group_ptr); + + reg = group_ptr->ARBPR; + + /* Request Source priority */ + reg &= ~((uint32_t)VADC_G_ARBPR_PRIO0_Msk); + reg |= (uint32_t) ((uint32_t)config->req_src_priority << VADC_G_ARBPR_PRIO0_Pos); + + /* Conversion Start mode */ + if (XMC_VADC_STARTMODE_WFS != (XMC_VADC_STARTMODE_t)config->conv_start_mode) + { + reg |= (uint32_t)(VADC_G_ARBPR_CSM0_Msk); + } + + group_ptr->ARBPR = reg; + + + group_ptr->QCTRL0 = (uint32_t)((config->qctrl0)|(uint32_t)(VADC_G_QCTRL0_XTWC_Msk)| + (uint32_t)(VADC_G_QCTRL0_TMWC_Msk)| + (uint32_t)(VADC_G_QCTRL0_GTWC_Msk)); + + /* Gating mode */ + group_ptr->QMR0 = ((uint32_t)(config->qmr0) | (uint32_t)((uint32_t)XMC_VADC_GATEMODE_IGNORE << VADC_G_QMR0_ENGT_Pos)); + + if (XMC_VADC_STARTMODE_CNR == (XMC_VADC_STARTMODE_t)(config->conv_start_mode) ) + { + group_ptr->QMR0 |= (uint32_t)((uint32_t)1 << VADC_G_QMR0_RPTDIS_Pos); + } + /* Enable arbitration slot for the queue request source */ + XMC_VADC_GROUP_QueueEnableArbitrationSlot(group_ptr); + +} + +/* API to select one of the 16 possible triggers as a conversion trigger for queue request source */ +void XMC_VADC_GROUP_QueueSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_TRIGGER_INPUT_SELECT_t input_num) +{ + uint32_t qctrl; + + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTrigger:Wrong Trigger Port", ((input_num)< XMC_VADC_NUM_PORTS)) + + + /* Now select the conversion trigger */ + qctrl = group_ptr->QCTRL0; + qctrl |= (uint32_t)VADC_G_QCTRL0_XTWC_Msk; + qctrl &= ~((uint32_t)VADC_G_QCTRL0_XTSEL_Msk); + qctrl |= (uint32_t)((uint32_t)input_num << VADC_G_QCTRL0_XTSEL_Pos); + group_ptr->QCTRL0 = qctrl; +} + +/* Select a trigger edge*/ +void XMC_VADC_GROUP_QueueSelectTriggerEdge(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_TRIGGER_EDGE_t trigger_edge) +{ + uint32_t qctrl; + + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTriggerEdge:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTriggerEdge:Wrong Gating Port", ((trigger_edge)<= XMC_VADC_TRIGGER_EDGE_ANY)) + + /* Now select the gating input */ + qctrl = group_ptr->QCTRL0; + qctrl |= (uint32_t)VADC_G_QCTRL0_XTWC_Msk; + qctrl &= ~((uint32_t)VADC_G_QCTRL0_XTMODE_Msk); + qctrl |= (uint32_t)((uint32_t)trigger_edge << VADC_G_QCTRL0_XTMODE_Pos); + group_ptr->QCTRL0 = qctrl; +} + +/* API to select one of the 16 possible trigger gates as a trigger gating signal for queue request source */ +void XMC_VADC_GROUP_QueueSelectGating(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GATE_INPUT_SELECT_t input_num) +{ + uint32_t qctrl; + + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectGating:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectGating:Wrong Gating Port", ((input_num)< XMC_VADC_NUM_PORTS)) + + /* Now select the gating input */ + qctrl = group_ptr->QCTRL0; + qctrl |= (uint32_t)VADC_G_QCTRL0_GTWC_Msk; + qctrl &= ~((uint32_t)VADC_G_QCTRL0_GTSEL_Msk); + qctrl |= (uint32_t)((uint32_t)input_num << VADC_G_QCTRL0_GTSEL_Pos); + group_ptr->QCTRL0 = qctrl; +} + +/* API to determine the number of channels in the queue (length includes the valid channel in the Backup register)*/ +uint32_t XMC_VADC_GROUP_QueueGetLength(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t qsr; + uint32_t qbur0; + uint32_t length; + + XMC_ASSERT("XMC_VADC_GROUP_QueueGetLength:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + qsr = group_ptr->QSR0; + qbur0 = group_ptr->QBUR0; + + if (qsr & (uint32_t)VADC_G_QSR0_EMPTY_Msk) + { + length = 0U; + } + else + { + length = (qsr & (uint32_t)VADC_G_QSR0_FILL_Msk) + 1U; + } + + if (qbur0 & (uint32_t)VADC_G_QBUR0_V_Msk ) + { + length++; + } + + return length; +} + +/* API to abort ongoing conversion of a channel sequence */ +void XMC_VADC_GROUP_QueueAbortSequence(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t qctrl0; + bool arbitration_status; + + XMC_ASSERT("XMC_VADC_GROUP_QueueAbortSequence:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Disable any gating if present*/ + qctrl0 = group_ptr->QCTRL0; + + group_ptr->QCTRL0 =(0U | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); + + /* Disable the Arbitration 0 in the group before abort*/ + arbitration_status = (bool)((uint32_t)(group_ptr->ARBPR >> VADC_G_ARBPR_ASEN0_Pos) & 1U); + XMC_VADC_GROUP_QueueDisableArbitrationSlot(group_ptr); + + /* Flush the Entries from queue*/ + XMC_VADC_GROUP_QueueFlushEntries(group_ptr); + + /* Enable the arbitration slot 0*/ + group_ptr->ARBPR |= (uint32_t)((uint32_t)arbitration_status << VADC_G_ARBPR_ASEN0_Pos); + + /* Enable any disabled gating*/ + group_ptr->QCTRL0 = (qctrl0 | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); +} + +/* API to abort conversion of the channel queued up next */ +void XMC_VADC_GROUP_QueueRemoveChannel(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t length_before_abort; + uint32_t length_after_abort; + uint32_t qctrl0; + bool arbitration_status; + + XMC_ASSERT("XMC_VADC_GROUP_QueueRemoveChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Disable any gating if present*/ + qctrl0= group_ptr->QCTRL0; + + group_ptr->QCTRL0 =(0U | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); + + /* Disable the Arbitration 0 in the group before abort*/ + arbitration_status = (bool)((uint32_t)(group_ptr->ARBPR >> VADC_G_ARBPR_ASEN0_Pos) & 1U); + XMC_VADC_GROUP_QueueDisableArbitrationSlot(group_ptr); + + length_before_abort = XMC_VADC_GROUP_QueueGetLength(group_ptr); + + if (length_before_abort) + { + /* Remove the first entry of the queue */ + group_ptr->QMR0 |= (uint32_t)VADC_G_QMR0_CLRV_Msk; + + length_after_abort = XMC_VADC_GROUP_QueueGetLength(group_ptr); + + /* Loop until a reduction in queue length is assessed */ + while(length_after_abort == length_before_abort) + { + length_after_abort = XMC_VADC_GROUP_QueueGetLength(group_ptr); + } + } + /* Enable the arbitration slot 0*/ + group_ptr->ARBPR |= (uint32_t)((uint32_t)arbitration_status << VADC_G_ARBPR_ASEN0_Pos); + + /* Enable any disabled gating*/ + group_ptr->QCTRL0 = (qctrl0 | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); +} + +/* Get details of channel meant to be converted right after the ongoing conversion */ +int32_t XMC_VADC_GROUP_QueueGetNextChannel(XMC_VADC_GROUP_t *const group_ptr) +{ + int32_t ch_num; + + XMC_ASSERT("XMC_VADC_GROUP_QueueGetNextChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* + * Check if there is something in the backup stage. If not, read queue-0 + * entry. + */ + if ( (group_ptr->QBUR0) & (uint32_t)VADC_G_QBUR0_V_Msk) + { + ch_num = (int32_t)(group_ptr->QBUR0 & (uint32_t)VADC_G_QBUR0_REQCHNR_Msk); + } + else if ( (group_ptr->Q0R0) & (uint32_t)VADC_G_Q0R0_V_Msk) + { + ch_num = (int32_t)(group_ptr->Q0R0 & (uint32_t)VADC_G_Q0R0_REQCHNR_Msk); + } + else + { + /* Nothing is pending */ + ch_num = -1; + } + + return ch_num; +} + +/* Get the channel number of the channel whose conversion had been interrupted */ +int32_t XMC_VADC_GROUP_QueueGetInterruptedChannel(XMC_VADC_GROUP_t *const group_ptr) +{ + int32_t ch_num; + + XMC_ASSERT("XMC_VADC_GROUP_QueueGetInterruptedChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + if ((group_ptr->QBUR0) & (uint32_t)VADC_G_QBUR0_V_Msk) + { + ch_num = (int32_t)(group_ptr->QBUR0 & (uint32_t)VADC_G_QBUR0_REQCHNR_Msk); + } + else + { + /* No such channel */ + ch_num = -1; + } + + return ch_num; +} + +/* Select a Service Request line for the request source event */ +void XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SR_t sr) +{ + uint32_t sevnp; + + XMC_ASSERT("XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode:Wrong Service Request", ((sr) <= XMC_VADC_SR_SHARED_SR3)) + + sevnp = group_ptr->SEVNP; + + sevnp &= ~((uint32_t)VADC_G_SEVNP_SEV0NP_Msk); + sevnp |= (uint32_t)((uint32_t)sr << VADC_G_SEVNP_SEV0NP_Pos); + + group_ptr->SEVNP = sevnp; + +} +#endif + +#if (XMC_VADC_GROUP_AVAILABLE ==1U) +/* API to initialize a channel unit */ +void XMC_VADC_GROUP_ChannelInit(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num, + const XMC_VADC_CHANNEL_CONFIG_t *config) +{ + uint32_t prio; + uint32_t ch_assign; + uint32_t mask; + + + XMC_ASSERT("XMC_VADC_GROUP_ChannelInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelInit:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + prio = (uint32_t)config->channel_priority; + + /* Priority channel */ + ch_assign = group_ptr->CHASS; + ch_assign &= ~((uint32_t)((uint32_t)1 << ch_num)); + ch_assign |= (uint32_t)(prio << ch_num); + group_ptr->CHASS = ch_assign; + + /* Alias channel */ + if (config->alias_channel >= (int32_t)0) + { + mask = (uint32_t)0; + if ((uint32_t)1 == ch_num) + { + mask = VADC_G_ALIAS_ALIAS1_Pos; + group_ptr->ALIAS &= ~(uint32_t)(VADC_G_ALIAS_ALIAS1_Msk); + } + else if ((uint32_t)0 == ch_num) + { + mask = VADC_G_ALIAS_ALIAS0_Pos; + group_ptr->ALIAS &= ~(uint32_t)(VADC_G_ALIAS_ALIAS0_Msk); + } + + group_ptr->ALIAS |= (uint32_t)(config->alias_channel << mask); + } + + group_ptr->BFL |= config->bfl; + +#if (XMC_VADC_BOUNDARY_FLAG_SELECT == 1U) + group_ptr->BFLC |= config->bflc; +#endif + /* Program the CHCTR register */ + group_ptr->CHCTR[ch_num] = config->chctr; + +} + +/* API to set an alias channel for channels numbered 2 through 7 */ +void XMC_VADC_GROUP_SetChannelAlias(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t src_ch_num, + const uint32_t alias_ch_num) +{ + uint32_t alias; + uint32_t mask; + uint32_t pos; + + XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Alias Channel", ((alias_ch_num == 0)|| (alias_ch_num == 1U))) + XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Aliased Channel", ((src_ch_num < 8U))) + + alias = group_ptr->ALIAS; + + if (0U == alias_ch_num) + { + mask = (uint32_t) VADC_G_ALIAS_ALIAS0_Msk; + pos = (uint32_t) VADC_G_ALIAS_ALIAS0_Pos; + } + else + { + mask = (uint32_t) VADC_G_ALIAS_ALIAS1_Msk; + pos = (uint32_t) VADC_G_ALIAS_ALIAS1_Pos; + } + alias &= ~mask; + alias |= (uint32_t)(src_ch_num << pos); + + group_ptr->ALIAS = alias; +} + +/* API to determine whether input to a channel has violated boundary conditions */ +bool XMC_VADC_GROUP_ChannelIsResultOutOfBounds(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + bool retval; + uint32_t chctr; + uint32_t ceflag; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelIsResultOutOfBounds:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelIsResultOutOfBounds:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + retval = (bool)false; + /* + Check if the Channel event is configured to be generated in the event of + boundary violation and if affirmative, check if the channel event is set. + */ + /* Extract CHEVMODE for requested channel */ + chctr = group_ptr->CHCTR[ch_num]; + chctr = (uint32_t)(chctr >> (uint32_t)VADC_G_CHCTR_CHEVMODE_Pos)& (uint32_t)0x3; + + /* Extract CEFLAG for the requested channel */ + ceflag = group_ptr->CEFLAG; + ceflag = ceflag & ((uint32_t)((uint32_t)1 << ch_num) ); + + /* Check what was the channel event generation criteria */ + if ( (( (uint32_t)XMC_VADC_CHANNEL_EVGEN_INBOUND == chctr) \ + || ((uint32_t) XMC_VADC_CHANNEL_EVGEN_OUTBOUND == chctr)) && (ceflag) ) + { + retval = (bool)true; + } + + return retval; +} + +/* Set a reference voltage for conversion */ +void XMC_VADC_GROUP_ChannelSetInputReference(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_CHANNEL_REF_t ref) +{ + uint32_t chctr; + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetInputReference:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetInputReference:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetInputReference:Wrong Voltage Reference", ((ref)<= XMC_VADC_CHANNEL_REF_ALT_CH0)) + + chctr = group_ptr->CHCTR[ch_num]; + chctr &= ~((uint32_t)VADC_G_CHCTR_REFSEL_Msk); + chctr |= (uint32_t)((uint32_t)ref << VADC_G_CHCTR_REFSEL_Pos); + + group_ptr->CHCTR[ch_num] = chctr; +} + +/* API to select one of the available 16 registers for storing the channel result */ +void XMC_VADC_GROUP_ChannelSetResultRegister(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const uint32_t result_reg_num) +{ + uint32_t chctr; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetResultRegister:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetResultRegister:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetResultRegister:Wrong Result Register", + ((result_reg_num) < XMC_VADC_NUM_RESULT_REGISTERS)) + + chctr = group_ptr->CHCTR[ch_num]; + chctr &= ~((uint32_t)VADC_G_CHCTR_RESREG_Msk); + chctr |= (uint32_t)(result_reg_num << VADC_G_CHCTR_RESREG_Pos); + + group_ptr->CHCTR[ch_num] = chctr; +} + +/* API to select one of the available 4 class conversion */ +void XMC_VADC_GROUP_ChannelSetIclass(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_CHANNEL_CONV_t conversion_class) +{ + + uint32_t chctr; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetIclass:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetIclass:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetIclass:Wrong input class ", + (XMC_VADC_CHANNEL_CONV_GLOBAL_CLASS1 >= conversion_class)) + + chctr = group_ptr->CHCTR[ch_num]; + chctr &= ~((uint32_t)VADC_G_CHCTR_ICLSEL_Msk); + chctr |= (uint32_t)((uint32_t)conversion_class << (uint32_t)VADC_G_CHCTR_ICLSEL_Pos); + + group_ptr->CHCTR[ch_num] = chctr; + +} + +/* API to retrieve the result register bound with specified channel */ +uint8_t XMC_VADC_GROUP_ChannelGetResultRegister(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + uint8_t resreg; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetResultRegister:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetResultRegister:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + resreg = (uint8_t)((group_ptr->CHCTR[ch_num] & (uint32_t)VADC_G_CHCTR_RESREG_Msk) >> VADC_G_CHCTR_RESREG_Pos) ; + + return resreg; +} + +/* API to manually assert channel event */ +void XMC_VADC_GROUP_ChannelTriggerEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + uint32_t ceflag; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelTriggerEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelTriggerEvent:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + ceflag = group_ptr->CEFLAG; + ceflag |= (uint32_t)((uint32_t)1 << ch_num); + group_ptr->CEFLAG = ceflag; +} + +/* API to bind channel event with a service request (NVIC Node) */ +void XMC_VADC_GROUP_ChannelSetEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_SR_t sr) +{ + uint32_t route_mask; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetEventInterruptNode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetEventInterruptNode:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetEventInterruptNode:Wrong Service Request", ((sr) <= XMC_VADC_SR_SHARED_SR3)) + + route_mask = group_ptr->CEVNP0; + route_mask &= ~((uint32_t)15 << (ch_num * (uint32_t)4)); + route_mask |= (uint32_t)( (uint32_t)sr << (ch_num * (uint32_t)4)); + group_ptr->CEVNP0 = route_mask; +} + +/* API to configure conditions for generation of channel event */ +void XMC_VADC_GROUP_ChannelTriggerEventGenCriteria( XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_CHANNEL_EVGEN_t criteria) +{ + uint32_t chctr; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelTriggerEventGenCriteria:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelTriggerEventGenCriteria:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelTriggerEventGenCriteria:Wrong Event Generation Criteria", + ((criteria) <= XMC_VADC_CHANNEL_EVGEN_ALWAYS)) + + chctr = group_ptr->CHCTR[ch_num]; + chctr &= ~((uint32_t)VADC_G_CHCTR_CHEVMODE_Msk); + chctr |= (uint32_t)((uint32_t)criteria << VADC_G_CHCTR_CHEVMODE_Pos); + group_ptr->CHCTR[ch_num] = chctr; +} + +/* API to configure the boundary selection */ +void XMC_VADC_GROUP_ChannelSetBoundarySelection(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + XMC_VADC_BOUNDARY_SELECT_t boundary_sel, + XMC_VADC_CHANNEL_BOUNDARY_t selection) +{ + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetBoundarySelection:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetBoundarySelection:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + group_ptr->CHCTR[ch_num] &= ~((uint32_t)VADC_G_CHCTR_BNDSELL_Msk << boundary_sel); + group_ptr->CHCTR[ch_num] |= (selection<< ((uint32_t)VADC_G_CHCTR_BNDSELL_Pos + (uint32_t)boundary_sel)); +} + +/* Make the specified result register part of Result FIFO */ +void XMC_VADC_GROUP_AddResultToFifo(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + uint32_t fen; + + XMC_ASSERT("XMC_VADC_GROUP_AddResultToFifo:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_AddResultToFifo:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + /* Extract and clear the FIFO enable field */ + fen = group_ptr->RCR[res_reg]; + fen &= ~((uint32_t)VADC_G_RCR_FEN_Msk); + /* Set this register up as a FIFO member */ + fen |= (uint32_t)((uint32_t)1 << VADC_G_RCR_FEN_Pos); + group_ptr->RCR[res_reg] = fen; +} + + +/* Applicable to fast compare mode, this API sets up the value which is to be compared against conversion result */ +void XMC_VADC_GROUP_SetResultFastCompareValue(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg, + const XMC_VADC_RESULT_SIZE_t compare_val) +{ + uint32_t res = group_ptr->RES[res_reg]; + + XMC_ASSERT("XMC_VADC_GROUP_SetResultFastCompareValue:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetResultFastCompareValue:Wrong Result Register", + ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + res &= ~((uint32_t)VADC_G_RES_RESULT_Msk); + res |= (uint32_t)((uint32_t)compare_val << XMC_VADC_RESULT_LEFT_ALIGN_10BIT); + group_ptr->RES[res_reg] = res; +} + +/* API to retrieve the result of fast mode comparison */ +XMC_VADC_FAST_COMPARE_t XMC_VADC_GROUP_GetFastCompareResult(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + XMC_VADC_FAST_COMPARE_t result; + uint32_t res; + + XMC_ASSERT("XMC_VADC_GROUP_GetFastCompareResult:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetFastCompareResult:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + res = group_ptr->RES[res_reg]; + + if (res & (uint32_t)VADC_G_RES_VF_Msk) + { + result = (XMC_VADC_FAST_COMPARE_t)((uint32_t)(res >> (uint32_t)VADC_G_RES_FCR_Pos) & (uint32_t)1); + } + else + { + result = XMC_VADC_FAST_COMPARE_UNKNOWN; + } + + return result; +} + +/* Applicable to fast compare mode, this API sets up the value which is to be compared against conversion result */ +void XMC_VADC_GROUP_SetResultSubtractionValue(XMC_VADC_GROUP_t *const group_ptr, + const uint16_t subtraction_val) +{ + uint32_t res; + + XMC_ASSERT("XMC_VADC_GROUP_SetResultSubtractionValue:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + res = group_ptr->RES[0]; + res &= ~((uint32_t)VADC_G_RES_RESULT_Msk); + res |= (uint32_t)subtraction_val; + group_ptr->RES[0] = res; +} + + +/* API to select a service request line (NVIC Node) for result event of specified unit of result hardware */ +void XMC_VADC_GROUP_SetResultInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg, + const XMC_VADC_SR_t sr) +{ + uint32_t route_mask; + + XMC_ASSERT("XMC_VADC_GROUP_SetResultInterruptNode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetResultInterruptNode:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + XMC_ASSERT("XMC_VADC_GROUP_SetResultInterruptNode:Wrong Service Request", ((sr) <= XMC_VADC_SR_SHARED_SR3)) + + if (res_reg <= 7U) + { + route_mask = group_ptr->REVNP0; + route_mask &= ~((uint32_t)((uint32_t)15 << (res_reg * (uint32_t)4) )); + route_mask |= (uint32_t)((uint32_t)sr << (res_reg * (uint32_t)4)); + group_ptr->REVNP0 = route_mask; + } + else + { + route_mask = group_ptr->REVNP1; + route_mask &= ~((uint32_t)((uint32_t)15 << (( res_reg - (uint32_t)8) * (uint32_t)4) )); + route_mask |= (uint32_t)((uint32_t)sr << ((res_reg - (uint32_t)8) * (uint32_t)4)); + group_ptr->REVNP1 = route_mask; + } +} + +/* API to retrieve the tail of the fifo which the specified result register is a part of */ +uint32_t XMC_VADC_GROUP_GetResultFifoTail(XMC_VADC_GROUP_t *const group_ptr, uint32_t res_reg) +{ + uint32_t tail; + uint32_t rcr; + int32_t i; + bool exit_flag; + + XMC_ASSERT("XMC_VADC_GROUP_GetResultFifoTail:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetResultFifoTail:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + tail = 0U; + exit_flag= (bool)false; + + if ((bool)true == XMC_VADC_GROUP_IsResultRegisterFifoHead(group_ptr, res_reg)) + { + res_reg = res_reg - 1U; + } + + /* Border condition */ + if (0U == res_reg) + { + tail = 0U; + } + else + { + /* Stop either at a node that does not have FEN set or at Node-0 */ + for(i = (int32_t)res_reg; i >= (int32_t)0; i--) + { + rcr = group_ptr->RCR[i]; + rcr &= (uint32_t)VADC_G_RCR_FEN_Msk; + + if (rcr) + { + if ((int32_t)0 == i) + { + /* No more nodes. Stop here */ + tail = (uint32_t)0; + exit_flag = (bool)true; + } + } + else + { + /* The preceding register forms the tail of the FIFO */ + tail = (uint32_t)i + (uint32_t)1; + exit_flag = (bool)true; + } + if (exit_flag) + { + break; + } + } + } + return tail; +} + +/* API to retrieve the head of the fifo which the specified result register is a part of */ +uint32_t XMC_VADC_GROUP_GetResultFifoHead(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + uint32_t head; + uint32_t rcr; + uint32_t i; + + XMC_ASSERT("XMC_VADC_GROUP_GetResultFifoHead:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetResultFifoHead:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + if ((bool)true == XMC_VADC_GROUP_IsResultRegisterFifoHead(group_ptr, res_reg)) + { + head = res_reg; + } + else + { + head = XMC_VADC_NUM_RESULT_REGISTERS - (uint32_t)1; + + for(i = res_reg; i < XMC_VADC_NUM_RESULT_REGISTERS ; i++) + { + rcr = group_ptr->RCR[i]; + rcr &= (uint32_t)VADC_G_RCR_FEN_Msk; + + if (!rcr) + { + /* This node forms the head of the FIFO */ + head = i ; + break; + } + } + } + return head; +} + +/* API to determine if the specified result register is the head of a result fifo */ +bool XMC_VADC_GROUP_IsResultRegisterFifoHead(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + bool ret_val; + uint32_t rcr_head; + uint32_t rcr_next; + + XMC_ASSERT("XMC_VADC_GROUP_IsResultRegisterFifoHead:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_IsResultRegisterFifoHead:Wrong Result Register", + ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + rcr_head = group_ptr->RCR[res_reg]; + rcr_head &= (uint32_t)VADC_G_RCR_FEN_Msk; + rcr_next = group_ptr->RCR[res_reg - (uint32_t)1]; + rcr_next &= (uint32_t)VADC_G_RCR_FEN_Msk; + + if (rcr_head) + { + ret_val = (bool)false; + } + else if (rcr_next) + { + ret_val = (bool)true; + } + else + { + ret_val = (bool)false; + } + + return ret_val; +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_wdt.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_wdt.c new file mode 100644 index 00000000..43018b1d --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_wdt.c @@ -0,0 +1,94 @@ +/** + * @file xmc_wdt.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API
+ * + * @endcond + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_wdt.h" +#include "xmc_scu.h" + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/* Enables watchdog clock and releases watchdog reset. */ +void XMC_WDT_Enable(void) +{ +#if UC_FAMILY == XMC4 + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_WDT); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_WDT); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_WDT); +#endif +} + +/* Disables watchdog clock and resets watchdog. */ +void XMC_WDT_Disable(void) +{ +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_WDT); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_WDT); +#endif + +#if UC_FAMILY == XMC4 + XMC_SCU_CLOCK_DisableClock(XMC_SCU_CLOCK_WDT); +#endif +} +/* Initializes and configures watchdog with configuration data pointed by \a config. */ +void XMC_WDT_Init(const XMC_WDT_CONFIG_t *const config) +{ + XMC_WDT_Enable(); + WDT->CTR = config->wdt_ctr; + WDT->WLB = config->window_lower_bound; + WDT->WUB = config->window_upper_bound; +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Startup/startup_XMC4700.S b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Startup/startup_XMC4700.S new file mode 100644 index 00000000..49ff0fb1 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Startup/startup_XMC4700.S @@ -0,0 +1,431 @@ +/********************************************************************************************************************* + * @file startup_XMC4700.S + * @brief CMSIS Core Device Startup File for Infineon XMC4700 Device Series + * @version V1.1 + * @date 05 Jan 2016 + * + * @cond + ********************************************************************************************************************* + * Copyright (c) 2015-2016, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + **************************** Change history ******************************** + * V1.0,Sep, 03, 2015 JFT:Initial version + * V1.1,Jan, 05, 2016 JFT:Fix .reset section attributes + * + * @endcond + */ + +/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ + +.macro Entry Handler + .long \Handler +.endm + +.macro Insert_ExceptionHandler Handler_Func + .weak \Handler_Func + .thumb_set \Handler_Func, Default_Handler +.endm + +/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */ + +/* ================== START OF VECTOR TABLE DEFINITION ====================== */ +/* Vector Table - This gets programed into VTOR register by onchip BootROM */ + .syntax unified + + .section .reset, "a", %progbits + + .align 2 + .globl __Vectors + .type __Vectors, %object +__Vectors: + .long __initial_sp /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + + Entry NMI_Handler /* NMI Handler */ + Entry HardFault_Handler /* Hard Fault Handler */ + Entry MemManage_Handler /* MPU Fault Handler */ + Entry BusFault_Handler /* Bus Fault Handler */ + Entry UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + Entry SVC_Handler /* SVCall Handler */ + Entry DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + Entry PendSV_Handler /* PendSV Handler */ + Entry SysTick_Handler /* SysTick Handler */ + + /* Interrupt Handlers for Service Requests (SR) from XMC4700 Peripherals */ + Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */ + Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */ + Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */ + Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */ + Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */ + Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */ + Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */ + Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */ + Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */ + .long 0 /* Not Available */ + Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */ + Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */ + Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */ + Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */ + Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */ + Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */ + Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */ + Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */ + Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */ + Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */ + Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */ + Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */ + Entry VADC0_G2_0_IRQHandler /* Handler name for SR VADC0_G2_0 */ + Entry VADC0_G2_1_IRQHandler /* Handler name for SR VADC0_G2_1 */ + Entry VADC0_G2_2_IRQHandler /* Handler name for SR VADC0_G2_2 */ + Entry VADC0_G2_3_IRQHandler /* Handler name for SR VADC0_G2_3 */ + Entry VADC0_G3_0_IRQHandler /* Handler name for SR VADC0_G3_0 */ + Entry VADC0_G3_1_IRQHandler /* Handler name for SR VADC0_G3_1 */ + Entry VADC0_G3_2_IRQHandler /* Handler name for SR VADC0_G3_2 */ + Entry VADC0_G3_3_IRQHandler /* Handler name for SR VADC0_G3_3 */ + Entry DSD0_0_IRQHandler /* Handler name for SR DSD0_0 */ + Entry DSD0_1_IRQHandler /* Handler name for SR DSD0_1 */ + Entry DSD0_2_IRQHandler /* Handler name for SR DSD0_2 */ + Entry DSD0_3_IRQHandler /* Handler name for SR DSD0_3 */ + Entry DSD0_4_IRQHandler /* Handler name for SR DSD0_4 */ + Entry DSD0_5_IRQHandler /* Handler name for SR DSD0_5 */ + Entry DSD0_6_IRQHandler /* Handler name for SR DSD0_6 */ + Entry DSD0_7_IRQHandler /* Handler name for SR DSD0_7 */ + Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */ + Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_0 */ + Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */ + Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */ + Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */ + Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */ + Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */ + Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */ + Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */ + Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */ + Entry CCU42_0_IRQHandler /* Handler name for SR CCU42_0 */ + Entry CCU42_1_IRQHandler /* Handler name for SR CCU42_1 */ + Entry CCU42_2_IRQHandler /* Handler name for SR CCU42_2 */ + Entry CCU42_3_IRQHandler /* Handler name for SR CCU42_3 */ + Entry CCU43_0_IRQHandler /* Handler name for SR CCU43_0 */ + Entry CCU43_1_IRQHandler /* Handler name for SR CCU43_1 */ + Entry CCU43_2_IRQHandler /* Handler name for SR CCU43_2 */ + Entry CCU43_3_IRQHandler /* Handler name for SR CCU43_3 */ + Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */ + Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */ + Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */ + Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */ + Entry CCU81_0_IRQHandler /* Handler name for SR CCU81_0 */ + Entry CCU81_1_IRQHandler /* Handler name for SR CCU81_1 */ + Entry CCU81_2_IRQHandler /* Handler name for SR CCU81_2 */ + Entry CCU81_3_IRQHandler /* Handler name for SR CCU81_3 */ + Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */ + Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */ + Entry POSIF1_0_IRQHandler /* Handler name for SR POSIF1_0 */ + Entry POSIF1_1_IRQHandler /* Handler name for SR POSIF1_1 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */ + Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */ + Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */ + Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */ + Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */ + Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */ + Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */ + Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */ + Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */ + Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */ + Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */ + Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */ + Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */ + Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */ + Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */ + Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */ + Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */ + Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */ + Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */ + Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */ + Entry USIC2_0_IRQHandler /* Handler name for SR USIC2_0 */ + Entry USIC2_1_IRQHandler /* Handler name for SR USIC2_1 */ + Entry USIC2_2_IRQHandler /* Handler name for SR USIC2_2 */ + Entry USIC2_3_IRQHandler /* Handler name for SR USIC2_3 */ + Entry USIC2_4_IRQHandler /* Handler name for SR USIC2_4 */ + Entry USIC2_5_IRQHandler /* Handler name for SR USIC2_5 */ + Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */ + .long 0 /* Not Available */ + Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */ + Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */ + Entry SDMMC0_0_IRQHandler /* Handler name for SR SDMMC0_0 */ + Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */ + Entry ETH0_0_IRQHandler /* Handler name for SR ETH0_0 */ + .long 0 /* Not Available */ + Entry GPDMA1_0_IRQHandler /* Handler name for SR GPDMA1_0 */ + .long 0 /* Not Available */ + + .size __Vectors, . - __Vectors +/* ================== END OF VECTOR TABLE DEFINITION ======================= */ + +/* ================== START OF VECTOR ROUTINES ============================= */ + + .align 1 + .thumb + +/* Reset Handler */ + .thumb_func + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp,=__initial_sp + +#ifndef __SKIP_SYSTEM_INIT + ldr r0, =SystemInit + blx r0 +#endif + +/* Initialize data + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: + +/* Zero initialized data + * Between symbol address __zero_table_start__ and __zero_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + * + * Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup. + */ +#ifndef __SKIP_BSS_CLEAR + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#endif /* __SKIP_BSS_CLEAR */ + +#ifndef __SKIP_LIBC_INIT_ARRAY + ldr r0, =__libc_init_array + blx r0 +#endif + + ldr r0, =main + blx r0 + +.align 2 +__copy_table_start__: + .long __data_load, __data_start, __data_size + .long __ram_code_load, __ram_code_start, __ram_code_size +__copy_table_end__: + +__zero_table_start__: + .long __bss_start, __bss_size + .long USB_RAM_start, USB_RAM_size + .long ETH_RAM_start, ETH_RAM_size +__zero_table_end__: + + .pool + .size Reset_Handler,.-Reset_Handler + +/* ======================================================================== */ +/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ + +/* Default exception Handlers - Users may override this default functionality by + defining handlers of the same name in their C code */ + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + Insert_ExceptionHandler NMI_Handler + Insert_ExceptionHandler HardFault_Handler + Insert_ExceptionHandler MemManage_Handler + Insert_ExceptionHandler BusFault_Handler + Insert_ExceptionHandler UsageFault_Handler + Insert_ExceptionHandler SVC_Handler + Insert_ExceptionHandler DebugMon_Handler + Insert_ExceptionHandler PendSV_Handler + Insert_ExceptionHandler SysTick_Handler + + Insert_ExceptionHandler SCU_0_IRQHandler + Insert_ExceptionHandler ERU0_0_IRQHandler + Insert_ExceptionHandler ERU0_1_IRQHandler + Insert_ExceptionHandler ERU0_2_IRQHandler + Insert_ExceptionHandler ERU0_3_IRQHandler + Insert_ExceptionHandler ERU1_0_IRQHandler + Insert_ExceptionHandler ERU1_1_IRQHandler + Insert_ExceptionHandler ERU1_2_IRQHandler + Insert_ExceptionHandler ERU1_3_IRQHandler + Insert_ExceptionHandler PMU0_0_IRQHandler + Insert_ExceptionHandler VADC0_C0_0_IRQHandler + Insert_ExceptionHandler VADC0_C0_1_IRQHandler + Insert_ExceptionHandler VADC0_C0_2_IRQHandler + Insert_ExceptionHandler VADC0_C0_3_IRQHandler + Insert_ExceptionHandler VADC0_G0_0_IRQHandler + Insert_ExceptionHandler VADC0_G0_1_IRQHandler + Insert_ExceptionHandler VADC0_G0_2_IRQHandler + Insert_ExceptionHandler VADC0_G0_3_IRQHandler + Insert_ExceptionHandler VADC0_G1_0_IRQHandler + Insert_ExceptionHandler VADC0_G1_1_IRQHandler + Insert_ExceptionHandler VADC0_G1_2_IRQHandler + Insert_ExceptionHandler VADC0_G1_3_IRQHandler + Insert_ExceptionHandler VADC0_G2_0_IRQHandler + Insert_ExceptionHandler VADC0_G2_1_IRQHandler + Insert_ExceptionHandler VADC0_G2_2_IRQHandler + Insert_ExceptionHandler VADC0_G2_3_IRQHandler + Insert_ExceptionHandler VADC0_G3_0_IRQHandler + Insert_ExceptionHandler VADC0_G3_1_IRQHandler + Insert_ExceptionHandler VADC0_G3_2_IRQHandler + Insert_ExceptionHandler VADC0_G3_3_IRQHandler + Insert_ExceptionHandler DSD0_0_IRQHandler + Insert_ExceptionHandler DSD0_1_IRQHandler + Insert_ExceptionHandler DSD0_2_IRQHandler + Insert_ExceptionHandler DSD0_3_IRQHandler + Insert_ExceptionHandler DSD0_4_IRQHandler + Insert_ExceptionHandler DSD0_5_IRQHandler + Insert_ExceptionHandler DSD0_6_IRQHandler + Insert_ExceptionHandler DSD0_7_IRQHandler + Insert_ExceptionHandler DAC0_0_IRQHandler + Insert_ExceptionHandler DAC0_1_IRQHandler + Insert_ExceptionHandler CCU40_0_IRQHandler + Insert_ExceptionHandler CCU40_1_IRQHandler + Insert_ExceptionHandler CCU40_2_IRQHandler + Insert_ExceptionHandler CCU40_3_IRQHandler + Insert_ExceptionHandler CCU41_0_IRQHandler + Insert_ExceptionHandler CCU41_1_IRQHandler + Insert_ExceptionHandler CCU41_2_IRQHandler + Insert_ExceptionHandler CCU41_3_IRQHandler + Insert_ExceptionHandler CCU42_0_IRQHandler + Insert_ExceptionHandler CCU42_1_IRQHandler + Insert_ExceptionHandler CCU42_2_IRQHandler + Insert_ExceptionHandler CCU42_3_IRQHandler + Insert_ExceptionHandler CCU43_0_IRQHandler + Insert_ExceptionHandler CCU43_1_IRQHandler + Insert_ExceptionHandler CCU43_2_IRQHandler + Insert_ExceptionHandler CCU43_3_IRQHandler + Insert_ExceptionHandler CCU80_0_IRQHandler + Insert_ExceptionHandler CCU80_1_IRQHandler + Insert_ExceptionHandler CCU80_2_IRQHandler + Insert_ExceptionHandler CCU80_3_IRQHandler + Insert_ExceptionHandler CCU81_0_IRQHandler + Insert_ExceptionHandler CCU81_1_IRQHandler + Insert_ExceptionHandler CCU81_2_IRQHandler + Insert_ExceptionHandler CCU81_3_IRQHandler + Insert_ExceptionHandler POSIF0_0_IRQHandler + Insert_ExceptionHandler POSIF0_1_IRQHandler + Insert_ExceptionHandler POSIF1_0_IRQHandler + Insert_ExceptionHandler POSIF1_1_IRQHandler + Insert_ExceptionHandler CAN0_0_IRQHandler + Insert_ExceptionHandler CAN0_1_IRQHandler + Insert_ExceptionHandler CAN0_2_IRQHandler + Insert_ExceptionHandler CAN0_3_IRQHandler + Insert_ExceptionHandler CAN0_4_IRQHandler + Insert_ExceptionHandler CAN0_5_IRQHandler + Insert_ExceptionHandler CAN0_6_IRQHandler + Insert_ExceptionHandler CAN0_7_IRQHandler + Insert_ExceptionHandler USIC0_0_IRQHandler + Insert_ExceptionHandler USIC0_1_IRQHandler + Insert_ExceptionHandler USIC0_2_IRQHandler + Insert_ExceptionHandler USIC0_3_IRQHandler + Insert_ExceptionHandler USIC0_4_IRQHandler + Insert_ExceptionHandler USIC0_5_IRQHandler + Insert_ExceptionHandler USIC1_0_IRQHandler + Insert_ExceptionHandler USIC1_1_IRQHandler + Insert_ExceptionHandler USIC1_2_IRQHandler + Insert_ExceptionHandler USIC1_3_IRQHandler + Insert_ExceptionHandler USIC1_4_IRQHandler + Insert_ExceptionHandler USIC1_5_IRQHandler + Insert_ExceptionHandler USIC2_0_IRQHandler + Insert_ExceptionHandler USIC2_1_IRQHandler + Insert_ExceptionHandler USIC2_2_IRQHandler + Insert_ExceptionHandler USIC2_3_IRQHandler + Insert_ExceptionHandler USIC2_4_IRQHandler + Insert_ExceptionHandler USIC2_5_IRQHandler + Insert_ExceptionHandler LEDTS0_0_IRQHandler + Insert_ExceptionHandler FCE0_0_IRQHandler + Insert_ExceptionHandler GPDMA0_0_IRQHandler + Insert_ExceptionHandler SDMMC0_0_IRQHandler + Insert_ExceptionHandler USB0_0_IRQHandler + Insert_ExceptionHandler ETH0_0_IRQHandler + Insert_ExceptionHandler GPDMA1_0_IRQHandler + +/* ============= END OF INTERRUPT HANDLER DEFINITION ====================== */ + + .end diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Startup/system_XMC4700.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Startup/system_XMC4700.c new file mode 100644 index 00000000..a95e951b --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Startup/system_XMC4700.c @@ -0,0 +1,734 @@ +/********************************************************************************************************************* + * @file system_XMC4700.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the Infineon XMC4700 Device Series + * @version V1.0.3 + * @date 09. Feb 2017 + * + * @cond + ********************************************************************************************************************* + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + ********************** Version History *************************************** + * V1.0.0, 03. Sep 2015, Initial version + * V1.0.1, 26. Jan 2016, Disable trap generation from clock unit + * V1.0.2, 01. Jun 2016, Fix masking of OSCHPCTRL value + * V1.0.3, 09. Feb 2017, Fix activation of USBPLL when SDMMC clock is enabled + ****************************************************************************** + * @endcond + */ + +/******************************************************************************* + * Default clock initialization + * fPLL = 288MHz => fSYS = 144MHz => fCPU = 144MHz + * => fPB = 144MHz + * => fCCU = 144MHz + * => fETH = 72MHz + * => fUSB = 48MHz + * => fEBU = 72MHz + * + * fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected + * + * fOFI = 24MHz => fWDT = 24MHz + *******************************************************************************/ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#include + +#include +#include "system_XMC4700.h" + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define CHIPID_LOC ((uint8_t *)0x20000000UL) + +/* Define WEAK attribute */ +#if !defined(__WEAK) +#if defined ( __CC_ARM ) +#define __WEAK __attribute__ ((weak)) +#elif defined ( __ICCARM__ ) +#define __WEAK __weak +#elif defined ( __GNUC__ ) +#define __WEAK __attribute__ ((weak)) +#elif defined ( __TASKING__ ) +#define __WEAK __attribute__ ((weak)) +#endif +#endif + +#define PMU_FLASH_WS (0x4U) + +#define FOSCREF (2500000U) + +#define DELAY_CNT_50US_50MHZ (2500UL) +#define DELAY_CNT_150US_50MHZ (7500UL) +#define DELAY_CNT_50US_48MHZ (2400UL) +#define DELAY_CNT_50US_72MHZ (3600UL) +#define DELAY_CNT_50US_96MHZ (4800UL) +#define DELAY_CNT_50US_120MHZ (6000UL) +#define DELAY_CNT_50US_144MHZ (7200UL) + +#define SCU_PLL_PLLSTAT_OSC_USABLE (SCU_PLL_PLLSTAT_PLLHV_Msk | \ + SCU_PLL_PLLSTAT_PLLLV_Msk | \ + SCU_PLL_PLLSTAT_PLLSP_Msk) + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/* +// Clock configuration +*/ + +/* +// External crystal frequency [Hz] +// <8000000=> 8MHz +// <12000000=> 12MHz +// <16000000=> 16MHz +// Defines external crystal frequency +// Default: 8MHz +*/ +#define OSCHP_FREQUENCY (12000000U) + +/* USB PLL settings, fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz */ +/* Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and fUSBPLLVCO <= 520 MHz*/ +#if OSCHP_FREQUENCY == 8000000U +#define USB_PDIV (1U) +#define USB_NDIV (95U) + +#elif OSCHP_FREQUENCY == 12000000U +#define USB_PDIV (1U) +#define USB_NDIV (63U) + +#elif OSCHP_FREQUENCY == 16000000U +#define USB_PDIV (1U) +#define USB_NDIV (47U) + +#else +#error "External crystal frequency not supported" + +#endif + +/* +// Backup clock calibration mode +// <0=> Factory calibration +// <1=> Automatic calibration +// Default: Automatic calibration +*/ +#define FOFI_CALIBRATION_MODE 1 +#define FOFI_CALIBRATION_MODE_FACTORY 0 +#define FOFI_CALIBRATION_MODE_AUTOMATIC 1 + +/* +// Standby clock (fSTDBY) source selection +// <0=> Internal slow oscillator (32768Hz) +// <1=> External crystal (32768Hz) +// Default: Internal slow oscillator (32768Hz) +*/ +#define STDBY_CLOCK_SRC 0 +#define STDBY_CLOCK_SRC_OSI 0 +#define STDBY_CLOCK_SRC_OSCULP 1 + +/* +// PLL clock source selection +// <0=> External crystal +// <1=> Internal fast oscillator +// Default: External crystal +*/ +#define PLL_CLOCK_SRC 0 +#define PLL_CLOCK_SRC_EXT_XTAL 0 +#define PLL_CLOCK_SRC_OFI 1 + +/* PLL settings, fPLL = 288MHz */ +#if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL +#if OSCHP_FREQUENCY == 8000000U +#define PLL_PDIV (1U) +#define PLL_NDIV (71U) +#define PLL_K2DIV (0U) + +#elif OSCHP_FREQUENCY == 12000000U +#define PLL_PDIV (1U) +#define PLL_NDIV (47U) +#define PLL_K2DIV (0U) + +#elif OSCHP_FREQUENCY == 16000000U +#define PLL_PDIV (1U) +#define PLL_NDIV (35U) +#define PLL_K2DIV (0U) + +#else +#error "External crystal frequency not supported" + +#endif + +#define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL)) + +#else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */ +#define PLL_PDIV (1U) +#define PLL_NDIV (23U) +#define PLL_K2DIV (0U) + +#define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL)) + +#endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */ + +#define PLL_K2DIV_24MHZ ((VCO / OFI_FREQUENCY) - 1UL) +#define PLL_K2DIV_48MHZ ((VCO / 48000000U) - 1UL) +#define PLL_K2DIV_72MHZ ((VCO / 72000000U) - 1UL) +#define PLL_K2DIV_96MHZ ((VCO / 96000000U) - 1UL) +#define PLL_K2DIV_120MHZ ((VCO / 120000000U) - 1UL) + +#define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_MMCCLK SCU_CLK_CLKCLR_MMCCDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_ETHCLK SCU_CLK_CLKCLR_ETH0CDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_EBUCLK SCU_CLK_CLKCLR_EBUCDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk + +#define SCU_CLK_SYSCLKCR_SYSSEL_OFI (0U << SCU_CLK_SYSCLKCR_SYSSEL_Pos) +#define SCU_CLK_SYSCLKCR_SYSSEL_PLL (1U << SCU_CLK_SYSCLKCR_SYSSEL_Pos) + +#define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos) +#define SCU_CLK_USBCLKCR_USBSEL_PLL (1U << SCU_CLK_USBCLKCR_USBSEL_Pos) + +#define SCU_CLK_WDTCLKCR_WDTSEL_OFI (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) +#define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) +#define SCU_CLK_WDTCLKCR_WDTSEL_PLL (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) + +#define SCU_CLK_EXTCLKCR_ECKSEL_SYS (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) +#define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) +#define SCU_CLK_EXTCLKCR_ECKSEL_PLL (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) + +#define EXTCLK_PIN_P0_8 (1) +#define EXTCLK_PIN_P1_15 (2) + +/* +// Clock tree +// System clock source selection +// <0=> fOFI +// <1=> fPLL +// Default: fPLL +// System clock divider <1-256><#-1> +// Default: 2 +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Default: fCPU = fSYS +// Peripheral clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// Default: fPB = fCPU +// CCU clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// Default: fCCU = fCPU +// Enable WDT clock +// WDT clock source <0=> fOFI +// <1=> fSTDBY +// <2=> fPLL +// Default: fOFI +// WDT clock divider <1-256><#-1> +// Default: 1 +// +// Enable EBU clock +// EBU clock divider <1-64><#-1> +// Default: 4 +// +// Enable ETH clock +// +// Enable MMC clock +// +// Enable USB clock +// USB clock source <0=> fUSBPLL +// <1=> fPLL +// Default: fPLL +// +// Enable external clock +// External Clock Source Selection +// <0=> fSYS +// <2=> fUSB +// <3=> fPLL +// Default: fPLL +// External Clock divider <1-512><#-1> +// Default: 288 +// Only valid for USB PLL and PLL clocks +// External Clock Pin Selection +// <0=> Disabled +// <1=> P0.8 +// <2=> P1.15 +// Default: Disabled +// +// +*/ +#define __CLKSET (0x00000000UL) +#define __SYSCLKCR (0x00010001UL) +#define __CPUCLKCR (0x00000000UL) +#define __PBCLKCR (0x00000000UL) +#define __CCUCLKCR (0x00000000UL) +#define __WDTCLKCR (0x00000000UL) +#define __EBUCLKCR (0x00000003UL) +#define __USBCLKCR (0x00010000UL) + +#define __EXTCLKCR (0x01200003UL) +#define __EXTCLKPIN (0U) + +/* +// +*/ + +/* +//-------- <<< end of configuration section >>> ------------------ +*/ + +#define ENABLE_PLL \ + (((__SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) == SCU_CLK_SYSCLKCR_SYSSEL_PLL) || \ + ((__CLKSET & SCU_CLK_CLKSET_EBUCEN_Msk) != 0) || \ + (((__CLKSET & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \ + (((__CLKSET & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && ((__WDTCLKCR & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL))) + +#define ENABLE_USBPLL \ + ((((__CLKSET & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL)) || \ + (((__CLKSET & SCU_CLK_CLKSET_MMCCEN_Msk) != 0) && ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL))) + +#if ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL) +#define USB_DIV (3U) +#else +#define USB_DIV (5U) +#endif + +/******************************************************************************* + * GLOBAL VARIABLES + *******************************************************************************/ +#if defined ( __CC_ARM ) +#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) +uint32_t SystemCoreClock __attribute__((at(0x2003FFC0))); +uint8_t g_chipid[16] __attribute__((at(0x2003FFC4))); +#elif defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536) +uint32_t SystemCoreClock __attribute__((at(0x2002CFC0))); +uint8_t g_chipid[16] __attribute__((at(0x2002CFC4))); +#else +#error "system_XMC4700.c: device not supported" +#endif +#elif defined ( __ICCARM__ ) +#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) || \ + defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536) +__no_init uint32_t SystemCoreClock; +__no_init uint8_t g_chipid[16]; +#else +#error "system_XMC4700.c: device not supported" +#endif +#elif defined ( __GNUC__ ) +#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) || \ + defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536) +uint32_t SystemCoreClock __attribute__((section(".no_init"))); +uint8_t g_chipid[16] __attribute__((section(".no_init"))); +#else +#error "system_XMC4700.c: device not supported" +#endif +#elif defined ( __TASKING__ ) +#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) +uint32_t SystemCoreClock __at( 0x2003FFC0 ); +uint8_t g_chipid[16] __at( 0x2003FFC4 ); +#elif defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536) +uint32_t SystemCoreClock __at( 0x2002CFC0 ); +uint8_t g_chipid[16] __at( 0x2002CFC4 ); +#else +#error "system_XMC4700.c: device not supported" +#endif +#else +#error "system_XMC4700.c: compiler not supported" +#endif + +extern uint32_t __Vectors; + +/******************************************************************************* + * LOCAL FUNCTIONS + *******************************************************************************/ +static void delay(uint32_t cycles) +{ + volatile uint32_t i; + + for(i = 0UL; i < cycles ;++i) + { + __NOP(); + } +} + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +__WEAK void SystemInit(void) +{ + memcpy(g_chipid, CHIPID_LOC, 16); + + SystemCoreSetup(); + SystemCoreClockSetup(); +} + +__WEAK void SystemCoreSetup(void) +{ + uint32_t temp; + + /* relocate vector table */ + __disable_irq(); + SCB->VTOR = (uint32_t)(&__Vectors); + __DSB(); + __enable_irq(); + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + + /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ + SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + + temp = FLASH0->FCON; + temp &= ~FLASH_FCON_WSPFLASH_Msk; + temp |= PMU_FLASH_WS; + FLASH0->FCON = temp; +} + +__WEAK void SystemCoreClockSetup(void) +{ +#if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY + /* Enable factory calibration */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk; +#else + /* Automatic calibration uses the fSTDBY */ + + /* Enable HIB domain */ + /* Power up HIB domain if and only if it is currently powered down */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + { + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; + + while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + { + /* wait until HIB domain is enabled */ + } + } + + /* Remove the reset only if HIB domain were in a state of reset */ + if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) + { + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; + delay(DELAY_CNT_150US_50MHZ); + } + +#if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP + /* Enable OSC_ULP */ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL) + { + /*enable OSC_ULP*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; + + /* Check if the clock is OK using OSCULP Oscillator Watchdog*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + + /* wait till clock is stable */ + do + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + + delay(DELAY_CNT_50US_50MHZ); + + } while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL); + + } + + /* now OSC_ULP is running and can be used*/ + /* Select OSC_ULP as the clock source for RTC and STDBY*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk; +#endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */ + + /* Enable automatic calibration of internal fast oscillator */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; +#endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */ + + delay(DELAY_CNT_50US_50MHZ); + +#if ENABLE_PLL + + /* enable PLL */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +#if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI + /* enable OSC_HP */ + if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U) + { + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk); + SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos; + + /* select OSC_HP clock as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE) + { + /* wait till OSC_HP output frequency is usable */ + } + } +#else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */ + + /* select backup clock as PLL input */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; +#endif + + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + + /* disconnect Oscillator from PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + + /* Setup divider settings for main PLL */ + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_24MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + /* Set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + /* connect Oscillator to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U) + { + /* wait for PLL Lock at 24MHz*/ + } + + /* Disable bypass- put PLL clock back */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U) + { + /* wait for normal mode */ + } +#endif /* ENABLE_PLL */ + + /* Before scaling to final frequency we need to setup the clock dividers */ + SCU_CLK->SYSCLKCR = __SYSCLKCR; + SCU_CLK->PBCLKCR = __PBCLKCR; + SCU_CLK->CPUCLKCR = __CPUCLKCR; + SCU_CLK->CCUCLKCR = __CCUCLKCR; + SCU_CLK->WDTCLKCR = __WDTCLKCR; + SCU_CLK->EBUCLKCR = __EBUCLKCR; + SCU_CLK->USBCLKCR = __USBCLKCR | USB_DIV; + SCU_CLK->EXTCLKCR = __EXTCLKCR; + +#if ENABLE_PLL + /* PLL frequency stepping...*/ + /* Reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_48MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + delay(DELAY_CNT_50US_48MHZ); + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_72MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + delay(DELAY_CNT_50US_72MHZ); + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_96MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + delay(DELAY_CNT_50US_96MHZ); + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_120MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + delay(DELAY_CNT_50US_120MHZ); + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + delay(DELAY_CNT_50US_144MHZ); + +#endif /* ENABLE_PLL */ + +#if ENABLE_USBPLL + /* enable USB PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); + + /* USB PLL uses as clock input the OSC_HP */ + /* check and if not already running enable OSC_HP */ + if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U) + { + /* check if Main PLL is switched on for OSC WDG*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL) + { + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk); + SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos; + + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE) + { + /* wait till OSC_HP output frequency is usable */ + } + } + + + /* Setup USB PLL */ + /* Go to bypass the USB PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + + /* disconnect Oscillator from USB PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + + /* Setup Divider settings for USB PLL */ + SCU_PLL->USBPLLCON = ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) | + (USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos)); + + /* Set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + + /* connect Oscillator to USB PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + + while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U) + { + /* wait for PLL Lock */ + } +#endif + + + /* Enable selected clocks */ + SCU_CLK->CLKSET = __CLKSET; + +#if __EXTCLKPIN != 0 +#if __EXTCLKPIN == EXTCLK_PIN_P1_15 + /* P1.15 */ + PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk; + PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT0_IOCR12_PC15_Msk) | (0x11U << PORT0_IOCR12_PC15_Pos); +#else + /* P0.8 */ + PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk; + PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk; + PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos); +#endif +#endif /* ENABLE_EXTCLK == 1 */ + + SystemCoreClockUpdate(); +} + +__WEAK void SystemCoreClockUpdate(void) +{ + uint32_t pdiv; + uint32_t ndiv; + uint32_t kdiv; + uint32_t temp; + + if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) + { + /* fPLL is clock source for fSYS */ + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk) + { + /* PLL input clock is the backup clock (fOFI) */ + temp = OFI_FREQUENCY; + } + else + { + /* PLL input clock is the high performance osicllator (fOSCHP) */ + temp = OSCHP_GetFrequency(); + } + + /* check if PLL is locked */ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* PLL normal mode */ + /* read back divider settings */ + pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1; + ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1; + kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1; + + temp = (temp / (pdiv * kdiv)) * ndiv; + } + else + { + /* PLL prescalar mode */ + /* read back divider settings */ + kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1; + + temp = (temp / kdiv); + } + } + else + { + /* fOFI is clock source for fSYS */ + temp = OFI_FREQUENCY; + } + + temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1); + temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1); + + SystemCoreClock = temp; +} + +__WEAK uint32_t OSCHP_GetFrequency(void) +{ + return OSCHP_FREQUENCY; +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/blt_conf.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/blt_conf.h new file mode 100644 index 00000000..05323cc6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/blt_conf.h @@ -0,0 +1,175 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Boot\blt_conf.h +* \brief Bootloader configuration header file. +* \ingroup Boot_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef BLT_CONF_H +#define BLT_CONF_H + +/**************************************************************************************** +* C P U D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* To properly initialize the baudrate clocks of the communication interface, typically + * the speed of the crystal oscillator and/or the speed at which the system runs is + * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and + * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is + * not dependent on the targets architecture, the byte ordering needs to be known. + * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects + * little endian mode. + * + * Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be + * called the moment the user program is about to be started. This could be used to + * de-initialize application specific parts, for example to stop blinking an LED, etc. + */ +/** \brief Frequency of the external crystal oscillator. */ +#define BOOT_CPU_XTAL_SPEED_KHZ (12000) +/** \brief Desired system speed. */ +#define BOOT_CPU_SYSTEM_SPEED_KHZ (144000) +/** \brief Motorola or Intel style byte ordering. */ +#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0) +/** \brief Enable/disable hook function call right before user program start. */ +#define BOOT_CPU_USER_PROGRAM_START_HOOK (1) + + +/**************************************************************************************** +* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N +****************************************************************************************/ +/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE + * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed + * in bits/second. Two CAN messages are reserved for communication with the host. The + * message identifier for sending data from the target to the host is configured with + * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with + * BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data + * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and + * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more + * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the + * CAN controller channel. + * + */ +/** \brief Enable/disable CAN transport layer. */ +#define BOOT_COM_CAN_ENABLE (1) +/** \brief Configure the desired CAN baudrate. */ +#define BOOT_COM_CAN_BAUDRATE (500000) +/** \brief Configure CAN message ID target->host. */ +#define BOOT_COM_CAN_TX_MSG_ID (0x7E1) +/** \brief Configure number of bytes in the target->host CAN message. */ +#define BOOT_COM_CAN_TX_MAX_DATA (8) +/** \brief Configure CAN message ID host->target. */ +#define BOOT_COM_CAN_RX_MSG_ID (0x667) +/** \brief Configure number of bytes in the host->target CAN message. */ +#define BOOT_COM_CAN_RX_MAX_DATA (8) +/** \brief Select the desired CAN peripheral as a zero based index. */ +#define BOOT_COM_CAN_CHANNEL_INDEX (1) + +/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE + * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed + * in bits/second. The maximum amount of data bytes in a message for data transmission + * and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA, + * respectively. It is common for a microcontroller to have more than 1 UART interface + * on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface. + * + */ +/** \brief Enable/disable UART transport layer. */ +#define BOOT_COM_UART_ENABLE (1) +/** \brief Configure the desired communication speed. */ +#define BOOT_COM_UART_BAUDRATE (57600) +/** \brief Configure number of bytes in the target->host data packet. */ +#define BOOT_COM_UART_TX_MAX_DATA (64) +/** \brief Configure number of bytes in the host->target data packet. */ +#define BOOT_COM_UART_RX_MAX_DATA (64) +/** \brief Select the desired UART peripheral as a zero based index. */ +#define BOOT_COM_UART_CHANNEL_INDEX (0) + + +/**************************************************************************************** +* B A C K D O O R E N T R Y C O N F I G U R A T I O N +****************************************************************************************/ +/* It is possible to implement an application specific method to force the bootloader to + * stay active after a reset. Such a backdoor entry into the bootloader is desired in + * situations where the user program does not run properly and therefore cannot + * reactivate the bootloader. By enabling these hook functions, the application can + * implement the backdoor, which overrides the default backdoor entry that is programmed + * into the bootloader. When desired for security purposes, these hook functions can + * also be implemented in a way that disables the backdoor entry altogether. + */ +/** \brief Enable/disable the backdoor override hook functions. */ +#define BOOT_BACKDOOR_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The NVM driver typically supports erase and program operations of the internal memory + * present on the microcontroller. Through these hook functions the NVM driver can be + * extended to support additional memory types such as external flash memory and serial + * eeproms. The size of the internal memory in kilobytes is specified with configurable + * BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can + * be overridden with a application specific method by enabling configuration switch + * BOOT_NVM_CHECKSUM_HOOKS_ENABLE. + */ +/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */ +#define BOOT_NVM_HOOKS_ENABLE (0) +/** \brief Configure the size of the default memory device (typically flash EEPROM). */ +#define BOOT_NVM_SIZE_KB (2048) +/** \brief Enable/disable hooks functions to override the user program checksum handling. */ +#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* W A T C H D O G D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The COP driver cannot be configured internally in the bootloader, because its use + * and configuration is application specific. The bootloader does need to service the + * watchdog in case it is used. When the application requires the use of a watchdog, + * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through + * hook functions. + */ +/** \brief Enable/disable the hook functions for controlling the watchdog. */ +#define BOOT_COP_HOOKS_ENABLE (1) + + +/**************************************************************************************** +* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N +****************************************************************************************/ +/* A security mechanism can be enabled in the bootloader's XCP module by setting configu- + * rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming + * operations can be performed, access to this resource need to be unlocked. + * In the Microboot settings on tab "XCP Protection" you need to specify a DLL that + * implements the unlocking algorithm. The demo programs are configured for the (simple) + * algorithm in "FeaserKey.dll". The source code for this DLL is available so it can be + * customized to your needs. + * During the unlock sequence, Microboot requests a seed from the bootloader, which is in + * the format of a byte array. Using this seed the unlock algorithm in the DLL computes + * a key, which is also a byte array, and sends this back to the bootloader. The + * bootloader then verifies this key to determine if programming and erase operations are + * permitted. + * After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook() + * are called by the bootloader to obtain the seed and to verify the key, respectively. + */ +#define BOOT_XCP_SEED_KEY_ENABLE (0) + + +#endif /* BLT_CONF_H */ +/*********************************** end of blt_conf.h *********************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/boot.dox b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/boot.dox new file mode 100644 index 00000000..ac8729dd --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/boot.dox @@ -0,0 +1,7 @@ +/** +\defgroup Boot_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC Bootloader +\brief Bootloader. +\ingroup ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +*/ + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/hooks.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/hooks.c new file mode 100644 index 00000000..a5437b2e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/hooks.c @@ -0,0 +1,307 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Boot\hooks.c +* \brief Bootloader callback source file. +* \ingroup Boot_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "led.h" /* LED driver header */ +#include "xmc_gpio.h" /* GPIO module */ + + +/**************************************************************************************** +* B A C K D O O R E N T R Y H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Initializes the backdoor entry option. +** \return none. +** +****************************************************************************************/ +void BackDoorInitHook(void) +{ +} /*** end of BackDoorInitHook ***/ + + +/************************************************************************************//** +** \brief Checks if a backdoor entry is requested. +** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool BackDoorEntryHook(void) +{ + /* default implementation always activates the bootloader after a reset */ + return BLT_TRUE; +} /*** end of BackDoorEntryHook ***/ +#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* C P U D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0) +/************************************************************************************//** +** \brief Callback that gets called when the bootloader is about to exit and +** hand over control to the user program. This is the last moment that +** some final checking can be performed and if necessary prevent the +** bootloader from activiting the user program. +** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep +** keep the bootloader active. +** +****************************************************************************************/ +blt_bool CpuUserProgramStartHook(void) +{ + /* clean up the LED driver */ + LedBlinkExit(); + + /* additional and optional backdoor entry through BUTTON1 on the board. to + * force the bootloader to stay active after reset, keep it pressed during reset. + */ + if (XMC_GPIO_GetInput(P15_13) == 0) + { + /* pushbutton pressed, so do not start the user program and keep the + * bootloader active instead. + */ + return BLT_FALSE; + } + + /* okay to start the user program.*/ + return BLT_TRUE; +} /*** end of CpuUserProgramStartHook ***/ +#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */ + + +/**************************************************************************************** +* W A T C H D O G D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_COP_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** initialization routine. It can be used to configure and enable the +** watchdog. +** \return none. +** +****************************************************************************************/ +void CopInitHook(void) +{ + /* this function is called upon initialization. might as well use it to initialize + * the LED driver. It is kind of a visual watchdog anyways. + */ + LedBlinkInit(100); +} /*** end of CopInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** service routine. This gets called upon initialization and during +** potential long lasting loops and routine. It can be used to service +** the watchdog to prevent a watchdog reset. +** \return none. +** +****************************************************************************************/ +void CopServiceHook(void) +{ + /* run the LED blink task. this is a better place to do it than in the main() program + * loop. certain operations such as flash erase can take a long time, which would cause + * a blink interval to be skipped. this function is also called during such operations, + * so no blink intervals will be skipped when calling the LED blink task here. + */ + LedBlinkTask(); +} /*** end of CopServiceHook ***/ +#endif /* BOOT_COP_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_NVM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the start of the internal NVM driver +** initialization routine. +** \return none. +** +****************************************************************************************/ +void NvmInitHook(void) +{ +} /*** end of NvmInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of a firmware update to reinitialize +** the NVM driver. +** \return none. +** +****************************************************************************************/ +void NvmReinitHook(void) +{ +} /*** end of NvmReinitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver write +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't +** been written yet. +** \param addr Start address. +** \param len Length in bytes. +** \param data Pointer to the data buffer. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the write +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmWriteHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver erase +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory +** hasn't been erased yet. +** \param addr Start address. +** \param len Length in bytes. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the erase +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmEraseHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the NVM programming session. +** \return BLT_TRUE is successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmDoneHook(void) +{ + return BLT_TRUE; +} /*** end of NvmDoneHook ***/ +#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */ + + +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Verifies the checksum, which indicates that a valid user program is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmVerifyChecksumHook(void) +{ + return BLT_TRUE; +} /*** end of NvmVerifyChecksum ***/ + + +/************************************************************************************//** +** \brief Writes a checksum of the user program to non-volatile memory. This is +** performed once the entire user program has been programmed. Through +** the checksum, the bootloader can check if a valid user programming is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmWriteChecksumHook(void) +{ + return BLT_TRUE; +} +#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_XCP_SEED_KEY_ENABLE > 0) +/************************************************************************************//** +** \brief Provides a seed to the XCP master that will be used for the key +** generation when the master attempts to unlock the specified resource. +** Called by the GET_SEED command. +** \param resource Resource that the seed if requested for (XCP_RES_XXX). +** \param seed Pointer to byte buffer wher the seed will be stored. +** \return Length of the seed in bytes. +** +****************************************************************************************/ +blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed) +{ + /* request seed for unlocking ProGraMming resource */ + if ((resource & XCP_RES_PGM) != 0) + { + seed[0] = 0x55; + } + + /* return seed length */ + return 1; +} /*** end of XcpGetSeedHook ***/ + + +/************************************************************************************//** +** \brief Called by the UNLOCK command and checks if the key to unlock the +** specified resource was correct. If so, then the resource protection +** will be removed. +** \param resource resource to unlock (XCP_RES_XXX). +** \param key pointer to the byte buffer holding the key. +** \param len length of the key in bytes. +** \return 1 if the key was correct, 0 otherwise. +** +****************************************************************************************/ +blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len) +{ + /* suppress compiler warning for unused parameter */ + len = len; + + /* the example key algorithm in "FeaserKey.dll" works as follows: + * - PGM will be unlocked if key = seed - 1 + */ + + /* check key for unlocking ProGraMming resource */ + if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1))) + { + /* correct key received for unlocking PGM resource */ + return 1; + } + + /* still here so key incorrect */ + return 0; +} /*** end of XcpVerifyKeyHook ***/ +#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */ + + +/*********************************** end of hooks.c ************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/led.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/led.c new file mode 100644 index 00000000..c214044f --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/led.c @@ -0,0 +1,102 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Boot\led.c +* \brief LED driver source file. +* \ingroup Boot_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "led.h" /* module header */ +#include "xmc_gpio.h" /* GPIO module */ + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Holds the desired LED blink interval time. */ +static blt_int16u ledBlinkIntervalMs; + + +/************************************************************************************//** +** \brief Initializes the LED blink driver. +** \param interval_ms Specifies the desired LED blink interval time in milliseconds. +** \return none. +** +****************************************************************************************/ +void LedBlinkInit(blt_int16u interval_ms) +{ + /* store the interval time between LED toggles */ + ledBlinkIntervalMs = interval_ms; +} /*** end of LedBlinkInit ***/ + + +/************************************************************************************//** +** \brief Task function for blinking the LED as a fixed timer interval. +** \return none. +** +****************************************************************************************/ +void LedBlinkTask(void) +{ + static blt_bool ledOn = BLT_FALSE; + static blt_int32u nextBlinkEvent = 0; + + /* check for blink event */ + if (TimerGet() >= nextBlinkEvent) + { + /* toggle the LED state */ + if (ledOn == BLT_FALSE) + { + /* turn the LED on */ + ledOn = BLT_TRUE; + XMC_GPIO_SetOutputLevel(P5_9, XMC_GPIO_OUTPUT_LEVEL_HIGH); + } + else + { + /* turn the LED off */ + ledOn = BLT_FALSE; + XMC_GPIO_SetOutputLevel(P5_9, XMC_GPIO_OUTPUT_LEVEL_LOW); + } + /* schedule the next blink event */ + nextBlinkEvent = TimerGet() + ledBlinkIntervalMs; + } +} /*** end of LedBlinkTask ***/ + + +/************************************************************************************//** +** \brief Cleans up the LED blink driver. This is intended to be used upon program +** exit. +** \return none. +** +****************************************************************************************/ +void LedBlinkExit(void) +{ + /* turn the LED off */ + XMC_GPIO_SetOutputLevel(P5_9, XMC_GPIO_OUTPUT_LEVEL_LOW); +} /*** end of LedBlinkExit ***/ + + +/*********************************** end of led.c **************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/led.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/led.h new file mode 100644 index 00000000..3a7c6bba --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/led.h @@ -0,0 +1,40 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Boot\led.h +* \brief LED driver header file. +* \ingroup Boot_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef LED_H +#define LED_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void LedBlinkInit(blt_int16u interval_ms); +void LedBlinkTask(void); +void LedBlinkExit(void); + + +#endif /* LED_H */ +/*********************************** end of led.h **************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/main.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/main.c new file mode 100644 index 00000000..980b634f --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/main.c @@ -0,0 +1,138 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Boot\main.c +* \brief Bootloader application source file. +* \ingroup Boot_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "xmc_gpio.h" /* GPIO module */ +#include "xmc_uart.h" /* UART driver header */ +#include "xmc_can.h" /* CAN driver header */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static void Init(void); +static void PostInit(void); + + +/************************************************************************************//** +** \brief This is the entry point for the bootloader application and is called +** by the reset interrupt vector after the C-startup routines executed. +** \return Program return code. +** +****************************************************************************************/ +int main(void) +{ + /* initialize the microcontroller */ + Init(); + /* initialize the bootloader */ + BootInit(); + /* post initialization of the microcontroller */ + PostInit(); + + /* start the infinite program loop */ + while (1) + { + /* run the bootloader task */ + BootTask(); + } + + /* program should never get here */ + return 0; +} /*** end of main ***/ + + +/************************************************************************************//** +** \brief Initializes the microcontroller. +** \return none. +** +****************************************************************************************/ +static void Init(void) +{ + /* initialize LED1 on P5.9 as digital output */ + XMC_GPIO_SetMode(P5_9, XMC_GPIO_MODE_OUTPUT_PUSH_PULL); + /* initialize BUTTON1 as digital input. */ + XMC_GPIO_SetMode(P15_13, XMC_GPIO_MODE_INPUT_TRISTATE); + XMC_GPIO_EnableDigitalInput(P15_13); +} /*** end of Init ***/ + + +/************************************************************************************//** +** \brief Post initialization of the microcontroller. Contains all initialization +** code that should run after the bootloader's core was initialized. +** \return none. +** +****************************************************************************************/ +static void PostInit(void) +{ +#if (BOOT_COM_UART_ENABLE > 0) + XMC_GPIO_CONFIG_t rx_uart_config; + XMC_GPIO_CONFIG_t tx_uart_config; +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + XMC_GPIO_CONFIG_t rx_can_config; + XMC_GPIO_CONFIG_t tx_can_config; +#endif + +#if (BOOT_COM_UART_ENABLE > 0) + /* initialize UART Rx pin */ + rx_uart_config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; + rx_uart_config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; + rx_uart_config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE; + XMC_GPIO_Init(P1_4, &rx_uart_config); + /* initialize UART Tx pin */ + tx_uart_config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2; + tx_uart_config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; + tx_uart_config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE; + XMC_GPIO_Init(P1_5, &tx_uart_config); + /* set input source path to DXnB to connect P1_4 to ASC Receive. note that this + * function must be called after XMC_UART_CH_Init(), which is called when initializing + * the bootloader core with BootInit(). + */ + XMC_USIC_CH_SetInputSource(XMC_UART0_CH0, XMC_USIC_CH_INPUT_DX0, 1U); +#endif + +#if (BOOT_COM_CAN_ENABLE > 0) + /* configure CAN receive pin */ + rx_can_config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; + XMC_GPIO_Init(P1_13, &rx_can_config); + /* configure CAN transmit pin */ + tx_can_config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2; + tx_can_config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; + tx_can_config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE; + XMC_GPIO_Init(P1_12, &tx_can_config); + /* select CAN Receive Input C (N1_RXDC) to map P1_13 to CAN_NODE1 */ + XMC_CAN_NODE_EnableConfigurationChange(CAN_NODE1); + XMC_CAN_NODE_SetReceiveInput(CAN_NODE1, XMC_CAN_NODE_RECEIVE_INPUT_RXDCC); + XMC_CAN_NODE_DisableConfigurationChange(CAN_NODE1); +#endif +} /*** end of PostInit ***/ + +/*********************************** end of main.c *************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/openblt_xmc4700.launch b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/openblt_xmc4700.launch new file mode 100644 index 00000000..45d78bcb --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/openblt_xmc4700.launch @@ -0,0 +1,85 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.cproject b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.cproject new file mode 100644 index 00000000..cf555532 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.cproject @@ -0,0 +1,207 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.project b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.project new file mode 100644 index 00000000..f79044ca --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.project @@ -0,0 +1,28 @@ + + + Prog + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.ifx.xmc4000.xmc4000Nature + com.dave.common.daveBenchNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.settings/com.dave.mbs.xc800.prefs b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.settings/com.dave.mbs.xc800.prefs new file mode 100644 index 00000000..6b077dca --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.settings/com.dave.mbs.xc800.prefs @@ -0,0 +1,14 @@ +ACTIVE_CONFIG_NAME=Debug +AppCompatibilitySet=1 +DEVICE_DESC=Package\= LQFP144 \nROM\= 2 MB Flash \nRAM\= 352 KB RAM \nInOut\= 91 digital I/O \nADC\= 32 ADC Channels, 12-bit, Delta Sigma Demodulator \nDAC\= 2 DAC Channels, 12 bit \nTimed_InOut\= 26 Timer, 48 CAPCOM channels, 2 POSIF \nSerial\= 6 USIC channels, ETH, USB, CAN \nDMA\= 12 DMA channels, ETH DMA, USB DMA \nTouch\= Touch and LED matrix control \nEBU\= MUX, DEMUX, Burst, SDRAM \n +DEVICE_NAME=XMC4700-F144x2048 +DEVICE_PACKAGE=LQFP144 +DEVICE_PACK_VERSION=2.1.20 +DEVICE_PATH=/DeviceRoot/Microcontrollers/XMC4000/XMC4700 Series/XMC4700-F144x2048 +FLASH_SIZE=2048 +MBS_PROVIDER_ID_KEY=com.dave.mbs.xmc4000.xmc4000MbsFactory +SOFTWARE_ID=XMC4.7.00.F144.ALL +TEMPLATE_KEY=com.ifx.xmc4000.appEmptyMainTemplate +USED_DAVE_VERSIONS=4.3.2 +eclipse.preferences.version=1 +minDaveVersion=4.3.2 diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.settings/language.settings.xml b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.settings/language.settings.xml new file mode 100644 index 00000000..705af776 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.settings/language.settings.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.settings/org.eclipse.cdt.core.prefs b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 00000000..d4995d0c --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,163 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.core.formatter.alignment_for_arguments_in_method_invocation=16 +org.eclipse.cdt.core.formatter.alignment_for_assignment=16 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+
+
+
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cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.1 + * @date 30. January 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * ARM Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #include + + #ifndef __NO_RETURN + #define __NO_RETURN __noreturn + #endif + #ifndef __USED + #define __USED __root + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + __packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED __packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct + #endif + + +/* + * TI ARM Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/CMSIS/Include/cmsis_gcc.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 00000000..a4ad21a0 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1899 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.1 + * @date 02. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; +#pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +//{ +// __ASM volatile ("nop"); +//} +#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +//{ +// __ASM volatile ("wfi"); +//} +#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +//{ +// __ASM volatile ("wfe"); +//} +#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +//{ +// __ASM volatile ("sev"); +//} +#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/CMSIS/Include/core_cm4.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 00000000..38aee9de --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,2103 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 30. January 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/CMSIS/Infineon/XMC4700_series/Include/XMC4700.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/CMSIS/Infineon/XMC4700_series/Include/XMC4700.h new file mode 100644 index 00000000..d901cb6e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/CMSIS/Infineon/XMC4700_series/Include/XMC4700.h @@ -0,0 +1,17688 @@ +/********************************************************************************************************************* + * Copyright (c) 2015-2016, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + *********************************************************************************************************************/ + + +/****************************************************************************************************//** + * @file XMC4700.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * XMC4700 from Infineon. + * + * @version V1.3.0 (Reference Manual v1.3) + * @date 30. August 2016 + * + * @note Generated with SVDConv V2.87l + * from CMSIS SVD File 'XMC4700_Processed_SVD.xml' Version 1.3.0 (Reference Manual v1.3), + *******************************************************************************************************/ + + + +/** @addtogroup Infineon + * @{ + */ + +/** @addtogroup XMC4700 + * @{ + */ + +#ifndef XMC4700_H +#define XMC4700_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* --------------------- XMC4700 Specific Interrupt Numbers --------------------- */ + SCU_0_IRQn = 0, /*!< 0 System Control */ + ERU0_0_IRQn = 1, /*!< 1 External Request Unit 0 */ + ERU0_1_IRQn = 2, /*!< 2 External Request Unit 0 */ + ERU0_2_IRQn = 3, /*!< 3 External Request Unit 0 */ + ERU0_3_IRQn = 4, /*!< 4 External Request Unit 0 */ + ERU1_0_IRQn = 5, /*!< 5 External Request Unit 1 */ + ERU1_1_IRQn = 6, /*!< 6 External Request Unit 1 */ + ERU1_2_IRQn = 7, /*!< 7 External Request Unit 1 */ + ERU1_3_IRQn = 8, /*!< 8 External Request Unit 1 */ + PMU0_0_IRQn = 12, /*!< 12 Program Management Unit */ + VADC0_C0_0_IRQn = 14, /*!< 14 Analog to Digital Converter Common Block 0 */ + VADC0_C0_1_IRQn = 15, /*!< 15 Analog to Digital Converter Common Block 0 */ + VADC0_C0_2_IRQn = 16, /*!< 16 Analog to Digital Converter Common Block 0 */ + VADC0_C0_3_IRQn = 17, /*!< 17 Analog to Digital Converter Common Block 0 */ + VADC0_G0_0_IRQn = 18, /*!< 18 Analog to Digital Converter Group 0 */ + VADC0_G0_1_IRQn = 19, /*!< 19 Analog to Digital Converter Group 0 */ + VADC0_G0_2_IRQn = 20, /*!< 20 Analog to Digital Converter Group 0 */ + VADC0_G0_3_IRQn = 21, /*!< 21 Analog to Digital Converter Group 0 */ + VADC0_G1_0_IRQn = 22, /*!< 22 Analog to Digital Converter Group 1 */ + VADC0_G1_1_IRQn = 23, /*!< 23 Analog to Digital Converter Group 1 */ + VADC0_G1_2_IRQn = 24, /*!< 24 Analog to Digital Converter Group 1 */ + VADC0_G1_3_IRQn = 25, /*!< 25 Analog to Digital Converter Group 1 */ + VADC0_G2_0_IRQn = 26, /*!< 26 Analog to Digital Converter Group 2 */ + VADC0_G2_1_IRQn = 27, /*!< 27 Analog to Digital Converter Group 2 */ + VADC0_G2_2_IRQn = 28, /*!< 28 Analog to Digital Converter Group 2 */ + VADC0_G2_3_IRQn = 29, /*!< 29 Analog to Digital Converter Group 2 */ + VADC0_G3_0_IRQn = 30, /*!< 30 Analog to Digital Converter Group 3 */ + VADC0_G3_1_IRQn = 31, /*!< 31 Analog to Digital Converter Group 3 */ + VADC0_G3_2_IRQn = 32, /*!< 32 Analog to Digital Converter Group 3 */ + VADC0_G3_3_IRQn = 33, /*!< 33 Analog to Digital Converter Group 3 */ + DSD0_M_0_IRQn = 34, /*!< 34 Delta Sigma Demodulator Main */ + DSD0_M_1_IRQn = 35, /*!< 35 Delta Sigma Demodulator Main */ + DSD0_M_2_IRQn = 36, /*!< 36 Delta Sigma Demodulator Main */ + DSD0_M_3_IRQn = 37, /*!< 37 Delta Sigma Demodulator Main */ + DSD0_A_4_IRQn = 38, /*!< 38 Delta Sigma Demodulator Auxiliary */ + DSD0_A_5_IRQn = 39, /*!< 39 Delta Sigma Demodulator Auxiliary */ + DSD0_A_6_IRQn = 40, /*!< 40 Delta Sigma Demodulator Auxiliary */ + DSD0_A_7_IRQn = 41, /*!< 41 Delta Sigma Demodulator Auxiliary */ + DAC0_0_IRQn = 42, /*!< 42 Digital to Analog Converter */ + DAC0_1_IRQn = 43, /*!< 43 Digital to Analog Converter */ + CCU40_0_IRQn = 44, /*!< 44 Capture Compare Unit 4 (Module 0) */ + CCU40_1_IRQn = 45, /*!< 45 Capture Compare Unit 4 (Module 0) */ + CCU40_2_IRQn = 46, /*!< 46 Capture Compare Unit 4 (Module 0) */ + CCU40_3_IRQn = 47, /*!< 47 Capture Compare Unit 4 (Module 0) */ + CCU41_0_IRQn = 48, /*!< 48 Capture Compare Unit 4 (Module 1) */ + CCU41_1_IRQn = 49, /*!< 49 Capture Compare Unit 4 (Module 1) */ + CCU41_2_IRQn = 50, /*!< 50 Capture Compare Unit 4 (Module 1) */ + CCU41_3_IRQn = 51, /*!< 51 Capture Compare Unit 4 (Module 1) */ + CCU42_0_IRQn = 52, /*!< 52 Capture Compare Unit 4 (Module 2) */ + CCU42_1_IRQn = 53, /*!< 53 Capture Compare Unit 4 (Module 2) */ + CCU42_2_IRQn = 54, /*!< 54 Capture Compare Unit 4 (Module 2) */ + CCU42_3_IRQn = 55, /*!< 55 Capture Compare Unit 4 (Module 2) */ + CCU43_0_IRQn = 56, /*!< 56 Capture Compare Unit 4 (Module 3) */ + CCU43_1_IRQn = 57, /*!< 57 Capture Compare Unit 4 (Module 3) */ + CCU43_2_IRQn = 58, /*!< 58 Capture Compare Unit 4 (Module 3) */ + CCU43_3_IRQn = 59, /*!< 59 Capture Compare Unit 4 (Module 3) */ + CCU80_0_IRQn = 60, /*!< 60 Capture Compare Unit 8 (Module 0) */ + CCU80_1_IRQn = 61, /*!< 61 Capture Compare Unit 8 (Module 0) */ + CCU80_2_IRQn = 62, /*!< 62 Capture Compare Unit 8 (Module 0) */ + CCU80_3_IRQn = 63, /*!< 63 Capture Compare Unit 8 (Module 0) */ + CCU81_0_IRQn = 64, /*!< 64 Capture Compare Unit 8 (Module 1) */ + CCU81_1_IRQn = 65, /*!< 65 Capture Compare Unit 8 (Module 1) */ + CCU81_2_IRQn = 66, /*!< 66 Capture Compare Unit 8 (Module 1) */ + CCU81_3_IRQn = 67, /*!< 67 Capture Compare Unit 8 (Module 1) */ + POSIF0_0_IRQn = 68, /*!< 68 Position Interface (Module 0) */ + POSIF0_1_IRQn = 69, /*!< 69 Position Interface (Module 0) */ + POSIF1_0_IRQn = 70, /*!< 70 Position Interface (Module 1) */ + POSIF1_1_IRQn = 71, /*!< 71 Position Interface (Module 1) */ + CAN0_0_IRQn = 76, /*!< 76 MultiCAN */ + CAN0_1_IRQn = 77, /*!< 77 MultiCAN */ + CAN0_2_IRQn = 78, /*!< 78 MultiCAN */ + CAN0_3_IRQn = 79, /*!< 79 MultiCAN */ + CAN0_4_IRQn = 80, /*!< 80 MultiCAN */ + CAN0_5_IRQn = 81, /*!< 81 MultiCAN */ + CAN0_6_IRQn = 82, /*!< 82 MultiCAN */ + CAN0_7_IRQn = 83, /*!< 83 MultiCAN */ + USIC0_0_IRQn = 84, /*!< 84 Universal Serial Interface Channel (Module 0) */ + USIC0_1_IRQn = 85, /*!< 85 Universal Serial Interface Channel (Module 0) */ + USIC0_2_IRQn = 86, /*!< 86 Universal Serial Interface Channel (Module 0) */ + USIC0_3_IRQn = 87, /*!< 87 Universal Serial Interface Channel (Module 0) */ + USIC0_4_IRQn = 88, /*!< 88 Universal Serial Interface Channel (Module 0) */ + USIC0_5_IRQn = 89, /*!< 89 Universal Serial Interface Channel (Module 0) */ + USIC1_0_IRQn = 90, /*!< 90 Universal Serial Interface Channel (Module 1) */ + USIC1_1_IRQn = 91, /*!< 91 Universal Serial Interface Channel (Module 1) */ + USIC1_2_IRQn = 92, /*!< 92 Universal Serial Interface Channel (Module 1) */ + USIC1_3_IRQn = 93, /*!< 93 Universal Serial Interface Channel (Module 1) */ + USIC1_4_IRQn = 94, /*!< 94 Universal Serial Interface Channel (Module 1) */ + USIC1_5_IRQn = 95, /*!< 95 Universal Serial Interface Channel (Module 1) */ + USIC2_0_IRQn = 96, /*!< 96 Universal Serial Interface Channel (Module 2) */ + USIC2_1_IRQn = 97, /*!< 97 Universal Serial Interface Channel (Module 2) */ + USIC2_2_IRQn = 98, /*!< 98 Universal Serial Interface Channel (Module 2) */ + USIC2_3_IRQn = 99, /*!< 99 Universal Serial Interface Channel (Module 2) */ + USIC2_4_IRQn = 100, /*!< 100 Universal Serial Interface Channel (Module 2) */ + USIC2_5_IRQn = 101, /*!< 101 Universal Serial Interface Channel (Module 2) */ + LEDTS0_0_IRQn = 102, /*!< 102 LED and Touch Sense Control Unit (Module 0) */ + FCE0_0_IRQn = 104, /*!< 104 Flexible CRC Engine */ + GPDMA0_0_IRQn = 105, /*!< 105 General Purpose DMA Unit 0 */ + SDMMC0_0_IRQn = 106, /*!< 106 Multi Media Card Interface */ + USB0_0_IRQn = 107, /*!< 107 Universal Serial Bus (Module 0) */ + ETH0_0_IRQn = 108, /*!< 108 Ethernet (Module 0) */ + GPDMA1_0_IRQn = 110 /*!< 110 General Purpose DMA Unit 1 */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4700.h" /*!< XMC4700 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define OFI_FREQUENCY (24000000UL) /**< 24MHz Backup Clock (fOFI) frequency. */ +#define OSI_FREQUENCY (32768UL) /**< 32KHz Internal Slow Clock source (fOSI) frequency. */ + +/******************************************************************************* + * GLOBAL VARIABLES + *******************************************************************************/ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint8_t g_chipid[16]; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize the system + * + */ +void SystemInit(void); + +/** + * @brief Initialize CPU settings + * + */ +void SystemCoreSetup(void); + +/** + * @brief Initialize clock + * + */ +void SystemCoreClockSetup(void); + +/** + * @brief Update SystemCoreClock variable + * + */ +void SystemCoreClockUpdate(void); + +/** + * @brief Returns frequency of the high performace oscillator + * User needs to overload this function to return the correct oscillator frequency + */ +uint32_t OSCHP_GetFrequency(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/Newlib/syscalls.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/Newlib/syscalls.c new file mode 100644 index 00000000..0ce488cf --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/Newlib/syscalls.c @@ -0,0 +1,100 @@ +/********************************************************************************************************************* + * @file syscalls.c + * @brief Newlib stubs + * @version V1.6 + * @date 20 Apr 2017 + * + * @cond + ********************************************************************************************************************* + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * *************************** Change history ******************************** + * V0.1 : Initial version + * V0.2 : Label updates + * V1.0 : Made _sbrk device agnostic + * V1.1 : C++ support + * V1.2 : Restored compatibility with old project files + * V1.3 Jan 2014, PKB : Encapsulating everything in this file for use only with GCC + * V1.4 11 Dec 2015, JFT : Fix heap overflow + * V1.5 09 Mar 2016, JFT : Add dso_handle to support destructors call at exit + * V1.6 20 Apr 2017, JFT : Foward declaration of __sbrk to fix link time optimization (-flto) compilation errors + * @endcond + */ + +/* + * This file contains stubs for standard C library functionality that must + * typically be provided for the underlying platform. + * + */ +#if defined ( __GNUC__ ) + +#include +#include +#include + +/* Forward prototypes. */ +caddr_t _sbrk(int nbytes) __attribute__((externally_visible)); +void _init(void) __attribute__((externally_visible)); + +/* c++ destructor dynamic shared object needed if -fuse-cxa-atexit is used*/ +void *__dso_handle __attribute__ ((weak)); + +// defined in linker script +extern caddr_t Heap_Bank1_Start; +extern caddr_t Heap_Bank1_End; +caddr_t _sbrk(int nbytes) +{ + static caddr_t heap_ptr = NULL; + caddr_t base; + + if (heap_ptr == NULL) { + heap_ptr = (caddr_t)&Heap_Bank1_Start; + } + + base = heap_ptr; + + /* heap word alignment */ + nbytes = (nbytes + 3) & ~0x3U; + if ((caddr_t)&Heap_Bank1_End > (heap_ptr + nbytes)) + { + heap_ptr += nbytes; + return (base); + } + else + { + /* Heap overflow */ + errno = ENOMEM; + return ((caddr_t)-1); + } +} + +/* Init */ +void _init(void) +{} + +#endif /* __GNUC__ */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_ccu4_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_ccu4_map.h new file mode 100644 index 00000000..6dd7295f --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_ccu4_map.h @@ -0,0 +1,4976 @@ +/** + * @file xmc4_ccu4_map.h + * @date 2015-12-07 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-08-25: + * - Initial version + * + * 2015-12-07: + * - Add XMC4300 support + * + * @endcond + */ + +#ifndef XMC4_CCU4_MAP_H +#define XMC4_CCU4_MAP_H + +#define XMC_CCU4_SLICE_INPUT_A (0U) +#define XMC_CCU4_SLICE_INPUT_B (1U) +#define XMC_CCU4_SLICE_INPUT_C (2U) +#define XMC_CCU4_SLICE_INPUT_D (3U) +#define XMC_CCU4_SLICE_INPUT_E (4U) +#define XMC_CCU4_SLICE_INPUT_F (5U) +#define XMC_CCU4_SLICE_INPUT_G (6U) +#define XMC_CCU4_SLICE_INPUT_H (7U) +#define XMC_CCU4_SLICE_INPUT_I (8U) +#define XMC_CCU4_SLICE_INPUT_J (9U) +#define XMC_CCU4_SLICE_INPUT_K (10U) +#define XMC_CCU4_SLICE_INPUT_L (11U) +#define XMC_CCU4_SLICE_INPUT_M (12U) +#define XMC_CCU4_SLICE_INPUT_N (13U) +#define XMC_CCU4_SLICE_INPUT_O (14U) +#define XMC_CCU4_SLICE_INPUT_P (15U) + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#endif + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_HRPWM0_QOUT3 7 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_HRPWM0_QOUT1 7 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_HRPWM0_QOUT2 7 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_HRPWM0_QOUT3 7 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_HRPWM0_QOUT1 7 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_HRPWM0_QOUT2 7 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_HRPWM0_QOUT3 7 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_HRPWM0_QOUT1 7 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_HRPWM0_QOUT2 7 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_HRPWM0_QOUT3 7 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_HRPWM0_QOUT1 7 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_HRPWM0_QOUT2 7 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define CCU40_IN0_CAN0_SR7 7 +#define CCU40_IN0_CCU40_ST0 12 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_ERU1_PDOUT0 9 +#define CCU40_IN0_ERU1_PDOUT1 3 +#define CCU40_IN0_P1_3 0 +#define CCU40_IN0_P2_1 2 +#define CCU40_IN0_P2_8 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ERU1_IOUT0 10 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_CCU40_ST0 12 +#define CCU40_IN1_CCU40_ST1 13 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU1_PDOUT0 3 +#define CCU40_IN1_ERU1_PDOUT1 9 +#define CCU40_IN1_P1_2 0 +#define CCU40_IN1_P2_0 2 +#define CCU40_IN1_P2_8 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT2 11 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ERU1_IOUT1 10 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN2_CCU40_ST0 12 +#define CCU40_IN2_CCU40_ST1 13 +#define CCU40_IN2_CCU40_ST2 14 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU1_PDOUT0 3 +#define CCU40_IN2_ERU1_PDOUT2 9 +#define CCU40_IN2_P1_1 0 +#define CCU40_IN2_P2_7 2 +#define CCU40_IN2_P2_8 1 +#define CCU40_IN2_POSIF0_OUT0 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ERU1_IOUT2 10 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN2_U0C1_DX2INS 11 +#define CCU40_IN3_CCU40_ST0 12 +#define CCU40_IN3_CCU40_ST1 13 +#define CCU40_IN3_CCU40_ST2 14 +#define CCU40_IN3_CCU40_ST3 15 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU1_PDOUT0 3 +#define CCU40_IN3_ERU1_PDOUT3 9 +#define CCU40_IN3_P1_0 0 +#define CCU40_IN3_P2_6 2 +#define CCU40_IN3_P2_8 1 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ERU1_IOUT3 10 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_U1C0_DX2INS 11 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_CAN0_SR7 7 +#define CCU41_IN0_CCU41_ST0 12 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_ERU1_PDOUT0 9 +#define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_P1_4 2 +#define CCU41_IN0_P2_5 0 +#define CCU41_IN0_P2_9 1 +#define CCU41_IN0_POSIF1_OUT0 4 +#define CCU41_IN0_POSIF1_OUT1 5 +#define CCU41_IN0_POSIF1_OUT3 6 +#define CCU41_IN0_SCU_ERU1_IOUT0 10 +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_VADC0_G0BFL0 11 +#define CCU41_IN1_CCU41_ST0 12 +#define CCU41_IN1_CCU41_ST1 13 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU1_PDOUT0 3 +#define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_P1_5 2 +#define CCU41_IN1_P2_4 0 +#define CCU41_IN1_P2_9 1 +#define CCU41_IN1_POSIF1_OUT0 4 +#define CCU41_IN1_POSIF1_OUT1 5 +#define CCU41_IN1_POSIF1_OUT2 11 +#define CCU41_IN1_POSIF1_OUT3 6 +#define CCU41_IN1_POSIF1_OUT4 7 +#define CCU41_IN1_SCU_ERU1_IOUT1 10 +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN2_CCU41_ST0 12 +#define CCU41_IN2_CCU41_ST1 13 +#define CCU41_IN2_CCU41_ST2 14 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU1_PDOUT0 3 +#define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_P1_10 2 +#define CCU41_IN2_P2_3 0 +#define CCU41_IN2_P2_9 1 +#define CCU41_IN2_POSIF1_OUT0 4 +#define CCU41_IN2_POSIF1_OUT2 5 +#define CCU41_IN2_POSIF1_OUT3 6 +#define CCU41_IN2_POSIF1_OUT4 7 +#define CCU41_IN2_SCU_ERU1_IOUT2 10 +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN2_VADC0_G0BFL1 11 +#define CCU41_IN3_CCU41_ST0 12 +#define CCU41_IN3_CCU41_ST1 13 +#define CCU41_IN3_CCU41_ST2 14 +#define CCU41_IN3_CCU41_ST3 15 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU1_PDOUT0 3 +#define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_P1_11 2 +#define CCU41_IN3_P2_2 0 +#define CCU41_IN3_P2_9 1 +#define CCU41_IN3_POSIF1_OUT3 4 +#define CCU41_IN3_POSIF1_OUT5 5 +#define CCU41_IN3_SCU_ERU1_IOUT3 10 +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0BFL2 11 +#define CCU41_IN3_VADC0_G1ARBCNT 6 +#define CCU42_IN0_CCU42_ST0 12 +#define CCU42_IN0_CCU42_ST1 13 +#define CCU42_IN0_CCU42_ST2 14 +#define CCU42_IN0_CCU42_ST3 15 +#define CCU42_IN0_CCU80_IGBTO 7 +#define CCU42_IN0_ERU1_PDOUT0 9 +#define CCU42_IN0_ERU1_PDOUT1 3 +#define CCU42_IN0_P2_15 1 +#define CCU42_IN0_P3_15 2 +#define CCU42_IN0_P3_6 0 +#define CCU42_IN0_POSIF0_OUT2 4 +#define CCU42_IN0_POSIF0_OUT5 5 +#define CCU42_IN0_SCU_ERU1_IOUT0 10 +#define CCU42_IN0_SCU_GSC42 8 +#define CCU42_IN0_U0C0_DX2INS 11 +#define CCU42_IN1_CCU42_ST0 12 +#define CCU42_IN1_CCU42_ST1 13 +#define CCU42_IN1_CCU42_ST2 14 +#define CCU42_IN1_CCU42_ST3 15 +#define CCU42_IN1_ERU1_PDOUT0 3 +#define CCU42_IN1_ERU1_PDOUT1 9 +#define CCU42_IN1_P2_15 1 +#define CCU42_IN1_P3_14 2 +#define CCU42_IN1_P3_5 0 +#define CCU42_IN1_POSIF0_OUT2 4 +#define CCU42_IN1_POSIF0_OUT5 5 +#define CCU42_IN1_SCU_ERU1_IOUT1 10 +#define CCU42_IN1_SCU_GSC42 8 +#define CCU42_IN1_U0C1_DX2INS 11 +#define CCU42_IN2_CAN0_SR7 6 +#define CCU42_IN2_CCU42_ST0 12 +#define CCU42_IN2_CCU42_ST1 13 +#define CCU42_IN2_CCU42_ST2 14 +#define CCU42_IN2_CCU42_ST3 15 +#define CCU42_IN2_ERU1_PDOUT0 3 +#define CCU42_IN2_ERU1_PDOUT2 9 +#define CCU42_IN2_P0_15 2 +#define CCU42_IN2_P2_15 1 +#define CCU42_IN2_P3_4 0 +#define CCU42_IN2_POSIF0_OUT2 4 +#define CCU42_IN2_POSIF0_OUT5 5 +#define CCU42_IN2_SCU_ERU1_IOUT2 10 +#define CCU42_IN2_SCU_GSC42 8 +#define CCU42_IN2_U1C0_DX2INS 11 +#define CCU42_IN3_CCU42_ST0 12 +#define CCU42_IN3_CCU42_ST1 13 +#define CCU42_IN3_CCU42_ST2 14 +#define CCU42_IN3_CCU42_ST3 15 +#define CCU42_IN3_ERU1_PDOUT0 3 +#define CCU42_IN3_ERU1_PDOUT3 9 +#define CCU42_IN3_P0_14 2 +#define CCU42_IN3_P2_15 1 +#define CCU42_IN3_P3_3 0 +#define CCU42_IN3_POSIF0_OUT2 4 +#define CCU42_IN3_POSIF0_OUT5 5 +#define CCU42_IN3_SCU_ERU1_IOUT3 10 +#define CCU42_IN3_SCU_GSC42 8 +#define CCU42_IN3_U1C1_DX2INS 11 +#define CCU42_IN3_VADC0_G2ARBCNT 6 +#define CCU43_IN0_CCU43_ST0 12 +#define CCU43_IN0_CCU43_ST1 13 +#define CCU43_IN0_CCU43_ST2 14 +#define CCU43_IN0_CCU43_ST3 15 +#define CCU43_IN0_CCU81_IGBTO 6 +#define CCU43_IN0_ERU1_PDOUT0 9 +#define CCU43_IN0_ERU1_PDOUT1 3 +#define CCU43_IN0_P2_14 1 +#define CCU43_IN0_P4_6 0 +#define CCU43_IN0_P4_7 2 +#define CCU43_IN0_POSIF1_OUT2 4 +#define CCU43_IN0_POSIF1_OUT5 5 +#define CCU43_IN0_SCU_ERU1_IOUT0 10 +#define CCU43_IN0_SCU_GSC43 8 +#define CCU43_IN0_U0C0_DX2INS 11 +#define CCU43_IN0_VADC0_G0BFL0 7 +#define CCU43_IN1_CAN0_SR7 6 +#define CCU43_IN1_CCU43_ST0 12 +#define CCU43_IN1_CCU43_ST1 13 +#define CCU43_IN1_CCU43_ST2 14 +#define CCU43_IN1_CCU43_ST3 15 +#define CCU43_IN1_ERU1_PDOUT0 3 +#define CCU43_IN1_ERU1_PDOUT1 9 +#define CCU43_IN1_P2_14 1 +#define CCU43_IN1_P4_2 2 +#define CCU43_IN1_P4_5 0 +#define CCU43_IN1_POSIF1_OUT2 4 +#define CCU43_IN1_POSIF1_OUT5 5 +#define CCU43_IN1_SCU_ERU1_IOUT1 10 +#define CCU43_IN1_SCU_GSC43 8 +#define CCU43_IN1_U0C1_DX2INS 11 +#define CCU43_IN1_VADC0_G1BFL0 7 +#define CCU43_IN2_CCU43_ST0 12 +#define CCU43_IN2_CCU43_ST1 13 +#define CCU43_IN2_CCU43_ST2 14 +#define CCU43_IN2_CCU43_ST3 15 +#define CCU43_IN2_ERU1_PDOUT0 3 +#define CCU43_IN2_ERU1_PDOUT2 9 +#define CCU43_IN2_P2_13 2 +#define CCU43_IN2_P2_14 1 +#define CCU43_IN2_P4_4 0 +#define CCU43_IN2_POSIF1_OUT2 4 +#define CCU43_IN2_POSIF1_OUT5 5 +#define CCU43_IN2_SCU_ERU1_IOUT2 10 +#define CCU43_IN2_SCU_GSC43 8 +#define CCU43_IN2_U1C0_DX2INS 11 +#define CCU43_IN2_VADC0_G2BFL0 7 +#define CCU43_IN3_CCU43_ST0 12 +#define CCU43_IN3_CCU43_ST1 13 +#define CCU43_IN3_CCU43_ST2 14 +#define CCU43_IN3_CCU43_ST3 15 +#define CCU43_IN3_ERU1_PDOUT0 3 +#define CCU43_IN3_ERU1_PDOUT3 9 +#define CCU43_IN3_P2_12 2 +#define CCU43_IN3_P2_14 1 +#define CCU43_IN3_P4_3 0 +#define CCU43_IN3_POSIF1_OUT2 4 +#define CCU43_IN3_POSIF1_OUT5 5 +#define CCU43_IN3_SCU_ERU1_IOUT3 10 +#define CCU43_IN3_SCU_GSC43 8 +#define CCU43_IN3_U1C1_DX2INS 11 +#define CCU43_IN3_VADC0_G3ARBCNT 6 +#define CCU43_IN3_VADC0_G3BFL0 7 +#endif + +#endif /* XMC4_CCU4_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_ccu8_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_ccu8_map.h new file mode 100644 index 00000000..33c53684 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_ccu8_map.h @@ -0,0 +1,2596 @@ +/** + * @file xmc4_ccu8_map.h + * @date 2015-12-07 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-08-25: + * - Initial version + * + * 2015-12-07: + * - Add XMC4300 support + * + * @endcond + */ + +#ifndef XMC4_CCU8_MAP_H +#define XMC4_CCU8_MAP_H + +#define XMC_CCU8_SLICE_INPUT_A (0U) +#define XMC_CCU8_SLICE_INPUT_B (1U) +#define XMC_CCU8_SLICE_INPUT_C (2U) +#define XMC_CCU8_SLICE_INPUT_D (3U) +#define XMC_CCU8_SLICE_INPUT_E (4U) +#define XMC_CCU8_SLICE_INPUT_F (5U) +#define XMC_CCU8_SLICE_INPUT_G (6U) +#define XMC_CCU8_SLICE_INPUT_H (7U) +#define XMC_CCU8_SLICE_INPUT_I (8U) +#define XMC_CCU8_SLICE_INPUT_J (9U) +#define XMC_CCU8_SLICE_INPUT_K (10U) +#define XMC_CCU8_SLICE_INPUT_L (11U) +#define XMC_CCU8_SLICE_INPUT_M (12U) +#define XMC_CCU8_SLICE_INPUT_N (13U) +#define XMC_CCU8_SLICE_INPUT_O (14U) +#define XMC_CCU8_SLICE_INPUT_P (15U) + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#endif + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_HRPWM0_C0O 12 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_HRPWM0_C1O 13 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_HRPWM0_C2O 14 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_HRPWM0_C0O 15 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define CCU80_IN0_CCU40_SR3 10 +#define CCU80_IN0_CCU80_ST0 12 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU81_SR3 11 +#define CCU80_IN0_ERU1_PDOUT0 9 +#define CCU80_IN0_P0_7 0 +#define CCU80_IN0_P3_2 2 +#define CCU80_IN0_P3_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ERU1_IOUT0 6 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN0_VADC0_G0BFL0 8 +#define CCU80_IN0_VADC0_G0SR3 5 +#define CCU80_IN1_CCU41_SR3 10 +#define CCU80_IN1_CCU80_ST0 12 +#define CCU80_IN1_CCU80_ST1 13 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU81_SR3 11 +#define CCU80_IN1_ERU1_PDOUT0 9 +#define CCU80_IN1_ERU1_PDOUT1 5 +#define CCU80_IN1_P0_7 0 +#define CCU80_IN1_P0_8 1 +#define CCU80_IN1_P3_1 2 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ERU1_IOUT1 6 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN1_VADC0_G0BFL1 8 +#define CCU80_IN2_CCU42_SR3 10 +#define CCU80_IN2_CCU80_ST0 12 +#define CCU80_IN2_CCU80_ST1 13 +#define CCU80_IN2_CCU80_ST2 14 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU81_SR3 11 +#define CCU80_IN2_ERU1_PDOUT0 9 +#define CCU80_IN2_ERU1_PDOUT2 5 +#define CCU80_IN2_P0_6 1 +#define CCU80_IN2_P0_7 0 +#define CCU80_IN2_P3_0 2 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ERU1_IOUT2 6 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN2_VADC0_G0BFL2 8 +#define CCU80_IN3_CCU43_SR3 10 +#define CCU80_IN3_CCU80_ST0 12 +#define CCU80_IN3_CCU80_ST1 13 +#define CCU80_IN3_CCU80_ST2 14 +#define CCU80_IN3_CCU80_ST3 15 +#define CCU80_IN3_CCU81_SR3 11 +#define CCU80_IN3_ERU1_PDOUT0 9 +#define CCU80_IN3_ERU1_PDOUT3 5 +#define CCU80_IN3_P0_7 0 +#define CCU80_IN3_P3_13 2 +#define CCU80_IN3_P3_3 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ERU1_IOUT3 6 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU80_IN3_VADC0_G0BFL3 8 +#define CCU81_IN0_CCU40_SR3 10 +#define CCU81_IN0_CCU80_SR3 11 +#define CCU81_IN0_CCU81_ST0 12 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_ERU1_PDOUT0 5 +#define CCU81_IN0_ERU1_PDOUT1 8 +#define CCU81_IN0_P3_0 2 +#define CCU81_IN0_P5_0 0 +#define CCU81_IN0_P5_1 1 +#define CCU81_IN0_POSIF1_OUT2 3 +#define CCU81_IN0_POSIF1_OUT5 4 +#define CCU81_IN0_SCU_ERU1_IOUT0 6 +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN0_VADC0_G0SR3 9 +#define CCU81_IN1_CCU41_SR3 10 +#define CCU81_IN1_CCU80_SR3 11 +#define CCU81_IN1_CCU81_ST0 12 +#define CCU81_IN1_CCU81_ST1 13 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_ERU1_PDOUT0 8 +#define CCU81_IN1_P3_13 2 +#define CCU81_IN1_P5_0 0 +#define CCU81_IN1_P5_2 1 +#define CCU81_IN1_POSIF1_OUT2 3 +#define CCU81_IN1_POSIF1_OUT5 4 +#define CCU81_IN1_SCU_ERU1_IOUT1 6 +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN1_VADC0_G1SR3 9 +#define CCU81_IN2_CCU42_SR3 10 +#define CCU81_IN2_CCU80_SR3 11 +#define CCU81_IN2_CCU81_ST0 12 +#define CCU81_IN2_CCU81_ST1 13 +#define CCU81_IN2_CCU81_ST2 14 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_ERU1_PDOUT1 8 +#define CCU81_IN2_ERU1_PDOUT2 5 +#define CCU81_IN2_P3_12 2 +#define CCU81_IN2_P5_0 0 +#define CCU81_IN2_P5_3 1 +#define CCU81_IN2_POSIF1_OUT2 3 +#define CCU81_IN2_POSIF1_OUT5 4 +#define CCU81_IN2_SCU_ERU1_IOUT2 6 +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN2_VADC0_G2SR3 9 +#define CCU81_IN3_CCU43_SR3 10 +#define CCU81_IN3_CCU80_SR3 11 +#define CCU81_IN3_CCU81_ST0 12 +#define CCU81_IN3_CCU81_ST1 13 +#define CCU81_IN3_CCU81_ST2 14 +#define CCU81_IN3_CCU81_ST3 15 +#define CCU81_IN3_ERU1_PDOUT1 8 +#define CCU81_IN3_ERU1_PDOUT3 5 +#define CCU81_IN3_P3_11 2 +#define CCU81_IN3_P5_0 0 +#define CCU81_IN3_P5_4 1 +#define CCU81_IN3_POSIF1_OUT2 3 +#define CCU81_IN3_POSIF1_OUT5 4 +#define CCU81_IN3_SCU_ERU1_IOUT3 6 +#define CCU81_IN3_SCU_GSC81 7 +#define CCU81_IN3_VADC0_G3SR3 9 +#endif + +#endif /* XMC4_CCU8_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_eru_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_eru_map.h new file mode 100644 index 00000000..1959469e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_eru_map.h @@ -0,0 +1,2134 @@ +/** + * @file xmc4_eru_map.h + * @date 2016-10-27 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial version + * + * 2015-12-07: + * - Add XMC4300 support + * + * 2016-10-27: + * - Fixed: Remove incorrect ERU0_ETL1_INPUTB_P0_1 and replace it by ERU0_ETL1_INPUTB_SCU_HIB_SR1 + * + * @endcond + */ + +#ifndef XMC4_ERU_MAP_H +#define XMC4_ERU_MAP_H + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ +#define ERU0_ETL0 XMC_ERU0, 0 +#define ERU0_ETL1 XMC_ERU0, 1 +#define ERU0_ETL2 XMC_ERU0, 2 +#define ERU0_ETL3 XMC_ERU0, 3 + +#define ERU0_OGU0 XMC_ERU0, 0 +#define ERU0_OGU1 XMC_ERU0, 1 +#define ERU0_OGU2 XMC_ERU0, 2 +#define ERU0_OGU3 XMC_ERU0, 3 + +#define ERU1_ETL0 XMC_ERU1, 0 +#define ERU1_ETL1 XMC_ERU1, 1 +#define ERU1_ETL2 XMC_ERU1, 2 +#define ERU1_ETL3 XMC_ERU1, 3 + +#define ERU1_OGU0 XMC_ERU1, 0 +#define ERU1_OGU1 XMC_ERU1, 1 +#define ERU1_OGU2 XMC_ERU1, 2 +#define ERU1_OGU3 XMC_ERU1, 3 + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2 +#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3 +#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 +#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#endif + +#endif /* XMC4_ERU_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_flash.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_flash.h new file mode 100644 index 00000000..3a9cd61e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_flash.h @@ -0,0 +1,705 @@ +/** + * @file xmc4_flash.h + * @date 2016-03-22 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2014-12-10: + * - Initial
+ * 2015-02-20: + * - Updated for Documentation related changes
+ * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * 2015-08-17: + * - Added the below API's to the public interface. + * 1. XMC_FLASH_Reset + * 2. XMC_FLASH_ErasePhysicalSector + * 3. XMC_FLASH_EraseUCB + * 4. XMC_FLASH_ResumeProtection + * 5. XMC_FLASH_RepairPhysicalSector + * - Added support for XMC4800/4700 devices + * 2015-12-07: + * - Fix XMC_FLASH_READ_ACCESS_TIME for XMC43, 47 and 48 devices + * 2016-03-18: + * - Fix implementation of XMC_PREFETCH_EnableInstructionBuffer and XMC_PREFETCH_DisableInstructionBuffer + * 2016-03-22: + * - Fix implementation of XMC_PREFETCH_InvalidateInstructionBuffer + * @endcond + * + */ + +#ifndef XMC4_FLASH_H +#define XMC4_FLASH_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_common.h" + +#if UC_FAMILY == XMC4 + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup FLASH + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_FLASH_UNCACHED_BASE (0x0C000000U) /**< Non cached flash starting address of for + XMC4 family of microcontrollers */ +#define XMC_FLASH_WORDS_PER_PAGE (64UL) /**< Number of words in a page (256 bytes / 4 bytes = 64 words)*/ +#define XMC_FLASH_BYTES_PER_PAGE (256UL) /**< Number of bytes in a page*/ + +#define XMC_FLASH_UCB0 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0000UL) /**< Starting address of User + Configurable Block 0*/ +#define XMC_FLASH_UCB1 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0400UL) /**< Starting address of User + Configurable Block 1*/ +#define XMC_FLASH_UCB2 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0800UL) /**< Starting address of User + Configurable Block 2*/ +#define XMC_FLASH_BYTES_PER_UCB (1024UL) /**< Number of bytes in a user configurable block*/ + +/**< Note : Total number of Sectors depends on the flash size of the controller. So while using these macros for flash + * operations ensure that sector is available, other may lead to flash error. + */ +#define XMC_FLASH_SECTOR_0 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x00000UL) /** + * + */ +typedef enum XMC_FLASH_PROTECTION +{ + XMC_FLASH_PROTECTION_WRITE_SECTOR_0 = 0x0001UL, /**< Sector 0 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_1 = 0x0002UL, /**< Sector 1 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_2 = 0x0004UL, /**< Sector 3 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_3 = 0x0008UL, /**< Sector 3 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_4 = 0x0010UL, /**< Sector 4 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_5 = 0x0020UL, /**< Sector 5 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_6 = 0x0040UL, /**< Sector 6 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_7 = 0x0080UL, /**< Sector 7 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_8 = 0x0100UL, /**< Sector 8 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTOR_9 = 0x0200UL, /**< Sector 9 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTORS_10_11 = 0x0400UL, /**< Sector 10 and 11 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTORS_12_13 = 0x0800UL, /**< Sector 12 and 13 write protection */ + XMC_FLASH_PROTECTION_WRITE_SECTORS_14_15 = 0x1000UL, /**< Sector 14 and 15 write protection */ + XMC_FLASH_PROTECTION_READ_GLOBAL = 0x8000UL /**< Global read protection (Applicable for UserLevel0 alone)*/ +} XMC_FLASH_PROTECTION_t; + +/********************************************************************************************************************* + * API PROTOTYPES + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Enables the wait state for error correction.process, It enables one additional wait state for ECC by setting WSECPF + * bit of FCON register.\n + * + * \parRelated APIs:
+ * XMC_FLASH_DisableWaitStateForECC()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_EnableWaitStateForECC(void) +{ + FLASH0->FCON |= FLASH_FCON_WSECPF_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Disables the wait state for error correction.\n\n Removes additional wait state for ECC by resetting WSECPF bit of + * FCON register.\n + * + * \parRelated APIs:
+ * XMC_FLASH_EnableWaitStateForECC()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_DisableWaitStateForECC(void) +{ + FLASH0->FCON &= (uint32_t)~FLASH_FCON_WSECPF_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Enables dynamic idle mode feature to save power.\n\n It switches off the PFLASH read path when no read access is + * pending. Hence power is saved marginally. This slightly reduces the flash read performance because static + * pre-fetching is disabled.It sets the FCON register IDLE bit to enable this feature. + * + * \parRelated APIs:
+ * XMC_FLASH_DisableDynamicIdle()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_EnableDynamicIdle(void) +{ + FLASH0->FCON |= FLASH_FCON_IDLE_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Disables dynamic idle mode feature.\n\n It resets the FCON register IDLE bit to disable this feature. Hence normal + * flash read operation is selected. + * + * \parRelated APIs:
+ * XMC_FLASH_EnableDynamicIdle()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_DisableDynamicIdle(void) +{ + FLASH0->FCON &= (uint32_t)~FLASH_FCON_IDLE_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Enables sleep mode of the PFLASH.\n\n Sleep mode is enabled by setting the bit FCON.SLEEP. + * + * \parNote:
+ * fCPU must be equal or above 1 MHz when wake-up request is triggered. + * + * \parRelated APIs:
+ * XMC_FLASH_DisableSleepRequest()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_EnableSleepRequest(void) +{ + FLASH0->FCON |= (uint32_t)FLASH_FCON_SLEEP_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Wake-up the PFLASH from sleep.\n\n Wakes-up from sleep is done by clearing the bit FCON.SLEEP, if selected via this + * bit, or wake-up is initiated by releasing the external sleep signal from SCU. + * + * \parNote:
+ * fCPU must be equal or above 1 MHz when wake-up request is triggered. + * + * \parRelated APIs:
+ * XMC_FLASH_EnableSleepRequest()\n\n\n + * + */ +__STATIC_INLINE void XMC_FLASH_DisableSleepRequest(void) +{ + FLASH0->FCON &= (uint32_t)~FLASH_FCON_SLEEP_Msk; +} + +/** + * + * @param margin PFLASH margin selection. Use type @ref XMC_FLASH_MARGIN_t. + * + * @return None + * + * \parDescription:
+ * Sets the read margin levels for checking the healthiness of flash data.\n\n Configures the margin field of MARP + * MARP register with the specified \a margin level. It changes the margin levels for read operations to find + * problematic array bits. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_FLASH_SetMargin(const XMC_FLASH_MARGIN_t margin) +{ + FLASH0->MARP = (FLASH0->MARP & (uint32_t)~FLASH_MARP_MARGIN_Msk) | margin; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Enables double bit error trap.\n\n. It enables by setting MARP register bit TRAPDIS. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_FLASH_EnableDoubleBitErrorTrap(void) +{ + FLASH0->MARP &= (uint32_t)~FLASH_MARP_TRAPDIS_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Disables the trap generation for double bit error by clearing MARP register bit TRAPDIS.\n\n The double-bit error + * trap can be disabled for margin checks and also redirected to an error interrupt. Any time during the execution the + * double bit error trap can be enabled back by calling XMC_FLASH_EnableDoubleBitErrorTrap() API. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_FLASH_DisableDoubleBitErrorTrap(void) +{ + FLASH0->MARP |= FLASH_MARP_TRAPDIS_Msk; +} + +/** + * + * @param num_wait_states number of wait states for initial read access
Range: [0 to 15] + * + * @return None + * + * \parDescription:
+ * Configures the number of wait states for initial flash read access.\n\n Depending on the configured \a + * num_wait_states value into FCON resister \a WSPFLASH field, the read performance gets optimized . The wait cycles + * for the flash read access must be configured based on the CPU frequency (fCPU), in relation to the flash access + * time (\a ta) defined. The access time formula (\a WSPFLASH x (\a \a \a 1 / fCPU) \a >= \a ta) applies only for + * the values \a \a \a num_wait_states >0. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_FLASH_SetWaitStates(uint32_t num_wait_states) +{ + FLASH0->FCON = (FLASH0->FCON & (uint32_t)~FLASH_FCON_WSPFLASH_Msk) | + (num_wait_states << FLASH_FCON_WSPFLASH_Pos); +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Configures the cacheable accesses to use the instruction buffer by resetting the register bit PREF_PCON.IBYP. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_PREFETCH_EnableInstructionBuffer(void) +{ + PREF->PCON &= (uint32_t)~PREF_PCON_IBYP_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Bypasses the instruction buffer for cacheable accesses, by setting the register bit PREF_PCON.IBYP. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_PREFETCH_DisableInstructionBuffer(void) +{ + PREF->PCON |= PREF_PCON_IBYP_Msk; +} + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Invalidates the instruction buffer by setting PREF_PCON register bit IINV.\n\n After system reset, the instruction + * buffer is automatically invalidated. + * + * \parNote:
+ * The complete invalidation operation is performed in a single cycle. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_PREFETCH_InvalidateInstructionBuffer(void) +{ + PREF->PCON |= PREF_PCON_IINV_Msk; + __DSB(); + __ISB(); + + PREF->PCON &= ~PREF_PCON_IINV_Msk; + __DSB(); + __ISB(); + +} + +/** + * + * @param user ID number of the user configuration block (UCB).
Range: [0 to 2] + * + * @param protection_mask ORed values of @ref XMC_FLASH_PROTECTION_t enum type, for which sectors the protection + * has to be enabled. + * @param password_0 First password for protection.
Range: [0 to 4294967295] + * @param password_1 Second password for protection.
Range: [0 to 4294967295] + * + * @return None + * + * \parDescription:
+ * Installs the global read and sector write protection.\n\n The installation starts by issuing the page mode entry + * command followed by the load page command. The load page command mode loads the required sectors intended for + * protection specified in \a protection_mask. It also loads the specified passwords \a password0 and \a password1 + * respectively. Finally, it issues the write page command for the specified \a user configuration block. Calling + * XMC_FLASH_ConfirmProtection() after this API completes the protection process by freezing the sectors forever. + * + * + * \parRelated APIs:
+ * XMC_FLASH_ConfirmProtection()
+ * XMC_FLASH_VerifyReadProtection()
+ */ +void XMC_FLASH_InstallProtection(uint8_t user, + uint32_t protection_mask, + uint32_t password_0, + uint32_t password_1); + +/** + * + * @param user ID number of the user configuration block (UCB).
Range: [0 to 2] + * + * @return None + * + * \parDescription:
+ * Confirms the protection, so that sectors specified under \a user configurable block are locked forever.\n\n The + * protection shall be installed by calling XMC_FLASH_InstallProtection() before calling this API. + * The confirmation starts by issuing the page mode entry command followed by the load page command. The load page + * command issues the confirmation protection command for the sectors on which the protection installation was done. + * It also loads the specified passwords \a password0 and \a password1 respectively. Finally, it issues the confirm + * protection command for the specified \a user configuration block so that the sectors will be protected forever. + * + * \parRelated APIs:
+ * XMC_FLASH_InstallProtection()
+ * + */ +void XMC_FLASH_ConfirmProtection(uint8_t user); + +/** + * + * @param password_0 First password used for protection.
Range: [0 to 4294967295] + * @param password_1 Second password used for protection.
Range: [0 to 4294967295] + * + * @return true if read protection installed properly else returns \a false. + * + * \parDescription:
+ * Verifies sector read protection is properly installed or not.\n\n Before entering into verify read protection + * process, it clears the error status bits inside status register. It temporarily disables the protection with + * passwords \a password0 and \a password1 respectively. It reads the FSR register and verifies the protection state. + * Resumption of read protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset. + * + * \parRelated APIs:
+ * XMC_FLASH_InstallProtection()
+ * XMC_FLASH_VerifyWriteProtection()
+ * XMC_FLASH_ResumeProtection()
+ */ +bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1); + +/** + * + * @param user ID number of the user configuration block (UCB).
Range: [0 to 2] + * + * @param protection_mask ORed values of @ref XMC_FLASH_PROTECTION_t enum type, for which sectors the protection + * has to be verified. + * @param password_0 First password used for protection.
Range: [0 to 4294967295] + * @param password_1 Second password used for protection.
Range: [0 to 4294967295] + * + * @return true if write protection installed properly else returns \a false. + * + * \parDescription:
+ * Verifies sector read protection is properly installed or not.\n\n Before entering into verify read protection + * process, it clears the error status bits inside status register. It temporarily disables the protection with + * passwords \a password0 and \a password1 respectively for the intended sectors specified in \a protection_mask. + * It reads the FSR register and verifies the write protection state. + * Resumption of write protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset. + * + * \parRelated APIs:
+ * XMC_FLASH_InstallProtection()
+ * XMC_FLASH_VerifyReadProtection()
+ * XMC_FLASH_ResumeProtection()
+ */ +bool XMC_FLASH_VerifyWriteProtection(uint32_t user, + uint32_t protection_mask, + uint32_t password_0, + uint32_t password_1); + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Resumes flash protection as it was configured before.\n\n + * It clears all the disable proection status flags FSR.WPRODISx and FSR.RPRODIS. But FSR.WPRODISx is not + * cleared when corresponding UCBx is not in the “confirmed” state. + * + * \parRelated APIs:
+ * None + */ +void XMC_FLASH_ResumeProtection(void); + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Repairs the physical sector "PS4".\n\n + * For selected devices, Erase Physical Sector can also be used for Sector Soft Repair, depending on the configuration + * of PROCON1.PSR. This command sequence is required to run an EEPROM emulation algorithm that cycles the logical + * sectors S4..S7 of PS4. This command sequence repairs the corrupted logical sectors inside the physical sector due to + * interrupted erase operation. + * + * \parRelated APIs:
+ * None + */ +void XMC_FLASH_RepairPhysicalSector(void); +/** + * + * @param sector_start_address Pointer to the starting address of physical sector. Use XMC_FLASH_SECTOR_x MACRO defined + * in xmc4_flash.h file. + * + * @return None + * + * \parDescription:
+ * Erases the physical sector "PSA".\n\n If "PSA" does not point to base address of a correct sector or an unavailable + * sector, it returns SQER. + * + * + * \parRelated APIs:
+ * None + */ +void XMC_FLASH_ErasePhysicalSector(uint32_t *sector_start_address); + +/** + * + * @param ucb_sector_start_address Pointer to the starting address of physical sector. Use XMC_FLASH_UCBx MACRO + * defined in xmc4_flash.h file. + * + * @return None + * + * \parDescription:
+ * The addressed user configuration block “UCB” is erased.\n\n + * Erases UCB whose startting address specified in the input parameter \a ucb_sector_start_address. When the UCB has + * an active write protection or the Flash module has an active global read protection the execution fails and + * PROER is set. The command fails with SQER when \a ucb_sector_start_address is not the start address of a valid UCB. + * Call \ref XMC_FLASH_GetStatus API after this API to verify the erase was proper ot not. + * + * \parRelated APIs:
+ * None + */ +void XMC_FLASH_EraseUCB(uint32_t *ucb_sector_start_address); + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * Resets the command interpreter to its initial state.\n\n + * Reset to Read can cancel every command sequence before its last command cycle has been received. All error flags + * gets cleared by calling this API. + * \parNote:
+ * todo + * + * \parRelated APIs:
+ * None + */ +void XMC_FLASH_Reset(void); + + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif + +#endif + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_gpio.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_gpio.h new file mode 100644 index 00000000..3234782d --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_gpio.h @@ -0,0 +1,345 @@ +/** + * @file xmc4_gpio.h + * @date 2015-10-09 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-10-09: + * - Added PORT MACRO checks and definitions for XMC4800/4700 devices + * @endcond + * + */ + +#ifndef XMC4_GPIO_H +#define XMC4_GPIO_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_common.h" + +#if UC_FAMILY == XMC4 + +#include "xmc4_gpio_map.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup GPIO + * @{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +#if defined(PORT0) +#define XMC_GPIO_PORT0 ((XMC_GPIO_PORT_t *) PORT0_BASE) +#define XMC_GPIO_CHECK_PORT0(port) (port == XMC_GPIO_PORT0) +#else +#define XMC_GPIO_CHECK_PORT0(port) 0 +#endif + +#if defined(PORT1) +#define XMC_GPIO_PORT1 ((XMC_GPIO_PORT_t *) PORT1_BASE) +#define XMC_GPIO_CHECK_PORT1(port) (port == XMC_GPIO_PORT1) +#else +#define XMC_GPIO_CHECK_PORT1(port) 0 +#endif + +#if defined(PORT2) +#define XMC_GPIO_PORT2 ((XMC_GPIO_PORT_t *) PORT2_BASE) +#define XMC_GPIO_CHECK_PORT2(port) (port == XMC_GPIO_PORT2) +#else +#define XMC_GPIO_CHECK_PORT2(port) 0 +#endif + +#if defined(PORT3) +#define XMC_GPIO_PORT3 ((XMC_GPIO_PORT_t *) PORT3_BASE) +#define XMC_GPIO_CHECK_PORT3(port) (port == XMC_GPIO_PORT3) +#else +#define XMC_GPIO_CHECK_PORT3(port) 0 +#endif + +#if defined(PORT4) +#define XMC_GPIO_PORT4 ((XMC_GPIO_PORT_t *) PORT4_BASE) +#define XMC_GPIO_CHECK_PORT4(port) (port == XMC_GPIO_PORT4) +#else +#define XMC_GPIO_CHECK_PORT4(port) 0 +#endif + +#if defined(PORT5) +#define XMC_GPIO_PORT5 ((XMC_GPIO_PORT_t *) PORT5_BASE) +#define XMC_GPIO_CHECK_PORT5(port) (port == XMC_GPIO_PORT5) +#else +#define XMC_GPIO_CHECK_PORT5(port) 0 +#endif + +#if defined(PORT6) +#define XMC_GPIO_PORT6 ((XMC_GPIO_PORT_t *) PORT6_BASE) +#define XMC_GPIO_CHECK_PORT6(port) (port == XMC_GPIO_PORT6) +#else +#define XMC_GPIO_CHECK_PORT6(port) 0 +#endif + +#if defined(PORT7) +#define XMC_GPIO_PORT7 ((XMC_GPIO_PORT_t *) PORT7_BASE) +#define XMC_GPIO_CHECK_PORT7(port) (port == XMC_GPIO_PORT7) +#else +#define XMC_GPIO_CHECK_PORT7(port) 0 +#endif + +#if defined(PORT8) +#define XMC_GPIO_PORT8 ((XMC_GPIO_PORT_t *) PORT8_BASE) +#define XMC_GPIO_CHECK_PORT8(port) (port == XMC_GPIO_PORT8) +#else +#define XMC_GPIO_CHECK_PORT8(port) 0 +#endif + +#if defined(PORT9) +#define XMC_GPIO_PORT9 ((XMC_GPIO_PORT_t *) PORT9_BASE) +#define XMC_GPIO_CHECK_PORT9(port) (port == XMC_GPIO_PORT9) +#else +#define XMC_GPIO_CHECK_PORT9(port) 0 +#endif + +#if defined(PORT14) +#define XMC_GPIO_PORT14 ((XMC_GPIO_PORT_t *) PORT14_BASE) +#define XMC_GPIO_CHECK_PORT14(port) (port == XMC_GPIO_PORT14) +#else +#define XMC_GPIO_CHECK_PORT14(port) 0 +#endif + +#if defined(PORT15) +#define XMC_GPIO_PORT15 ((XMC_GPIO_PORT_t *) PORT15_BASE) +#define XMC_GPIO_CHECK_PORT15(port) (port == XMC_GPIO_PORT15) +#else +#define XMC_GPIO_CHECK_PORT15(port) 0 +#endif + +#define XMC_GPIO_CHECK_PORT(port) (XMC_GPIO_CHECK_PORT0(port) || \ + XMC_GPIO_CHECK_PORT1(port) || \ + XMC_GPIO_CHECK_PORT2(port) || \ + XMC_GPIO_CHECK_PORT3(port) || \ + XMC_GPIO_CHECK_PORT4(port) || \ + XMC_GPIO_CHECK_PORT5(port) || \ + XMC_GPIO_CHECK_PORT6(port) || \ + XMC_GPIO_CHECK_PORT7(port) || \ + XMC_GPIO_CHECK_PORT8(port) || \ + XMC_GPIO_CHECK_PORT9(port) || \ + XMC_GPIO_CHECK_PORT14(port) || \ + XMC_GPIO_CHECK_PORT15(port)) + +#define XMC_GPIO_CHECK_OUTPUT_PORT(port) (XMC_GPIO_CHECK_PORT0(port) || \ + XMC_GPIO_CHECK_PORT1(port) || \ + XMC_GPIO_CHECK_PORT2(port) || \ + XMC_GPIO_CHECK_PORT3(port) || \ + XMC_GPIO_CHECK_PORT4(port) || \ + XMC_GPIO_CHECK_PORT5(port) || \ + XMC_GPIO_CHECK_PORT6(port) || \ + XMC_GPIO_CHECK_PORT7(port) || \ + XMC_GPIO_CHECK_PORT8(port) || \ + XMC_GPIO_CHECK_PORT9(port)) + +#define XMC_GPIO_CHECK_ANALOG_PORT(port) (XMC_GPIO_CHECK_PORT14(port) || \ + XMC_GPIO_CHECK_PORT15(port)) + +#define XMC_GPIO_CHECK_OUTPUT_STRENGTH(strength) ((strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE) ||\ + (strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE) ||\ + (strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE) ||\ + (strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE) ||\ + (strength == XMC_GPIO_OUTPUT_STRENGTH_MEDIUM) ||\ + (strength == XMC_GPIO_OUTPUT_STRENGTH_WEAK)) + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + +/** + * Defines the direction and characteristics of a pin. Use type \a XMC_GPIO_MODE_t for this enum. For the operation + * with alternate functions, the port pins are directly connected to input or output functions of the on-chip periphery. + */ + +typedef enum XMC_GPIO_MODE +{ + XMC_GPIO_MODE_INPUT_TRISTATE = 0x0UL << PORT0_IOCR0_PC0_Pos, /**< No internal pull device active */ + XMC_GPIO_MODE_INPUT_PULL_DOWN = 0x1UL << PORT0_IOCR0_PC0_Pos, /**< Internal pull-down device active */ + XMC_GPIO_MODE_INPUT_PULL_UP = 0x2UL << PORT0_IOCR0_PC0_Pos, /**< Internal pull-up device active */ + XMC_GPIO_MODE_INPUT_SAMPLING = 0x3UL << PORT0_IOCR0_PC0_Pos, /**< No internal pull device active;Pn_OUTx continuously samples the input value */ + XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE = 0x4UL << PORT0_IOCR0_PC0_Pos, /**< Inverted no internal pull device active */ + XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN = 0x5UL << PORT0_IOCR0_PC0_Pos, /**< Inverted internal pull-down device active */ + XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP = 0x6UL << PORT0_IOCR0_PC0_Pos, /**< Inverted internal pull-up device active */ + XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING = 0x7UL << PORT0_IOCR0_PC0_Pos, /**< Inverted no internal pull device active; Pn_OUTx continuously samples the input value */ + XMC_GPIO_MODE_OUTPUT_PUSH_PULL = 0x80UL, /**< Push-pull general-purpose output */ + XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN = 0xc0UL, /**< Open-drain general-purpose output */ + XMC_GPIO_MODE_OUTPUT_ALT1 = 0x1UL << PORT0_IOCR0_PC0_Pos, + XMC_GPIO_MODE_OUTPUT_ALT2 = 0x2UL << PORT0_IOCR0_PC0_Pos, + XMC_GPIO_MODE_OUTPUT_ALT3 = 0x3UL << PORT0_IOCR0_PC0_Pos, + XMC_GPIO_MODE_OUTPUT_ALT4 = 0x4UL << PORT0_IOCR0_PC0_Pos, + XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT1, /**< Push-pull alternate output function 1 */ + XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT2, /**< Push-pull alternate output function 2 */ + XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT3, /**< Push-pull alternate output function 3 */ + XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT4, /**< Push-pull alternate output function 4 */ + XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT1, /**< Open drain alternate output function 1 */ + XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT2, /**< Open drain alternate output function 2 */ + XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT3, /**< Open drain alternate output function 3 */ + XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT4, /**< Open drain alternate output function 4 */ +} XMC_GPIO_MODE_t; + +/** + * Defines output strength and slew rate of a pin. Use type \a XMC_GPIO_OUTPUT_STRENGTH_t for this enum. + * + */ +typedef enum XMC_GPIO_OUTPUT_STRENGTH +{ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE = 0x0U, /**< Defines pad driver mode, for high speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE = 0x1U, /**< Defines pad driver mode, for high speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE = 0x2U, /**< Defines pad driver mode, medium speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE = 0x3U, /**< Defines pad driver mode, medium speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_MEDIUM = 0x4U, /**< Defines pad driver mode, for low speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_WEAK = 0x7U /**< Defines pad driver mode, low speed 3.3V LVTTL outputs */ +} XMC_GPIO_OUTPUT_STRENGTH_t; + + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ +/** + * Structure points port hardware registers. Use type XMC_GPIO_PORT_t for this structure. + */ + +typedef struct XMC_GPIO_PORT { + __IO uint32_t OUT; /**< The port output register determines the value of a GPIO pin when it is selected by + Pn_IOCRx as output */ + __O uint32_t OMR; /**< The port output modification register contains control bits that make it possible + to individually set, reset, or toggle the logic state of a single port line*/ + __I uint32_t RESERVED0[2]; + __IO uint32_t IOCR[4]; /**< The port input/output control registers select the digital output and input driver + functionality and characteristics of a GPIO port pin */ + __I uint32_t RESERVED1; + __I uint32_t IN; /**< The logic level of a GPIO pin can be read via the read-only port input register + Pn_IN */ + __I uint32_t RESERVED2[6]; + __IO uint32_t PDR[2]; /**< Pad Driver Mode Registers */ + + __I uint32_t RESERVED3[6]; + __IO uint32_t PDISC; /**< Pin Function Decision Control Register is to disable/enable the digital pad + structure in shared analog and digital ports*/ + __I uint32_t RESERVED4[3]; + __IO uint32_t PPS; /**< Pin Power Save Register */ + __IO uint32_t HWSEL; /**< Pin Hardware Select Register */ +} XMC_GPIO_PORT_t; + +/** + * Structure initializes port pin. Use type XMC_GPIO_CONFIG_t for this structure. + */ +typedef struct XMC_GPIO_CONFIG +{ + XMC_GPIO_MODE_t mode; /**< Defines the direction and characteristics of a pin */ + XMC_GPIO_OUTPUT_LEVEL_t output_level; /**< Defines output level of a pin */ + XMC_GPIO_OUTPUT_STRENGTH_t output_strength; /**< Defines pad driver mode of a pin */ +} XMC_GPIO_CONFIG_t; + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +__STATIC_INLINE bool XMC_GPIO_IsModeValid(XMC_GPIO_MODE_t mode) +{ + return ((mode == XMC_GPIO_MODE_INPUT_TRISTATE) || + (mode == XMC_GPIO_MODE_INPUT_PULL_DOWN) || + (mode == XMC_GPIO_MODE_INPUT_PULL_UP) || + (mode == XMC_GPIO_MODE_INPUT_SAMPLING) || + (mode == XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE) || + (mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN) || + (mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP) || + (mode == XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING) || + (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL) || + (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1) || + (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2) || + (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3) || + (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4) || + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN) || + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1) || + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2) || + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3) || + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4)); +} + +/** + * + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDR. + * @param pin Port pin number. + * @param strength Output driver mode selection. Refer data structure @ref XMC_GPIO_OUTPUT_STRENGTH_t for details. + * + * @return None + * + * \parDescription:
+ * Sets port pin output strength and slew rate. It configures hardware registers Pn_PDR. \a strength is initially + * configured during initialization in XMC_GPIO_Init(). Call this API to alter output driver mode as needed later in + * the program. + * + * \parRelated APIs:
+ * None + * + * \parNote:
+ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). + * + */ + +void XMC_GPIO_SetOutputStrength(XMC_GPIO_PORT_t *const port, const uint8_t pin, XMC_GPIO_OUTPUT_STRENGTH_t strength); + +/** + * @} (end addtogroup GPIO) + */ + +/** + * @} (end addtogroup XMClib) + */ + +#endif /* UC_FAMILY == XMC4 */ + +#endif /* XMC4_GPIO_H */ + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_gpio_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_gpio_map.h new file mode 100644 index 00000000..7397a381 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_gpio_map.h @@ -0,0 +1,7535 @@ +/** + * @file xmc4_gpio_map.h + * @date 2016-08-22 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * + * 2015-06-20: + * - Updated copyright information + * + * 2015-11-12: + * - Added XMC4800 + * + * 2015-06-20: + * - Missing CAN_N0_TXD connectivity + * - VADC_EMUXn_IN replaced by VADC_EMUX0xy + * - DSD_MCLKOUT replaced by DSD_MCLKx + * - Missing connectivity for XMC48/47 + * + * 2015-12-07: + * - Add XMC4300 support + * + * 2016-03-09: + * - Fixed SDMMC signals names + * - Added P2_0_AF_CAN_N0_TXD for XMC44xx + * - Added P1_9_AF_U0C0_SCLKOUT, P4_7_AF_U2C1_DOUT0, P6_6_AF_U2C0_DOUT0 for XMC47/48 BGA196 + * + * 2016-03-22: + * - Fixed EBU CS signal names + * + * 2016-08-22: + * - Added P2_0_AF_CAN_N0_TXD for XMC4300 + * + * @endcond + * + * @brief XMC pin mapping definitions + */ + +#ifndef XMC4_GPIO_MAP_H +#define XMC4_GPIO_MAP_H + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX22 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX22 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX22 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX22 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_6_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_11_AF_ECAT0_LED_STATE_RUN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_10_AF_ECAT0_SYNC1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_1_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_12_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_15_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_15_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_15_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_14 XMC_GPIO_PORT14, 14 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_HRPWM0_OUT01 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_HRPWM0_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_HRPWM0_OUT21 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_HRPWM0_OUT00 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_HRPWM0_OUT30 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_HRPWM0_OUT11 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_HRPWM0_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_HRPWM0_OUT31 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_15_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P7_0 XMC_GPIO_PORT7, 0 +#define P7_1 XMC_GPIO_PORT7, 1 +#define P7_2 XMC_GPIO_PORT7, 2 +#define P7_3 XMC_GPIO_PORT7, 3 +#define P7_4 XMC_GPIO_PORT7, 4 +#define P7_5 XMC_GPIO_PORT7, 5 +#define P7_6 XMC_GPIO_PORT7, 6 +#define P7_7 XMC_GPIO_PORT7, 7 +#define P7_8 XMC_GPIO_PORT7, 8 +#define P7_9 XMC_GPIO_PORT7, 9 +#define P7_10 XMC_GPIO_PORT7, 10 +#define P7_11 XMC_GPIO_PORT7, 11 +#define P8_0 XMC_GPIO_PORT8, 0 +#define P8_1 XMC_GPIO_PORT8, 1 +#define P8_2 XMC_GPIO_PORT8, 2 +#define P8_3 XMC_GPIO_PORT8, 3 +#define P8_4 XMC_GPIO_PORT8, 4 +#define P8_5 XMC_GPIO_PORT8, 5 +#define P8_6 XMC_GPIO_PORT8, 6 +#define P8_7 XMC_GPIO_PORT8, 7 +#define P8_8 XMC_GPIO_PORT8, 8 +#define P8_9 XMC_GPIO_PORT8, 9 +#define P8_10 XMC_GPIO_PORT8, 10 +#define P8_11 XMC_GPIO_PORT8, 11 +#define P9_0 XMC_GPIO_PORT9, 0 +#define P9_1 XMC_GPIO_PORT9, 1 +#define P9_2 XMC_GPIO_PORT9, 2 +#define P9_3 XMC_GPIO_PORT9, 3 +#define P9_4 XMC_GPIO_PORT9, 4 +#define P9_5 XMC_GPIO_PORT9, 5 +#define P9_6 XMC_GPIO_PORT9, 6 +#define P9_7 XMC_GPIO_PORT9, 7 +#define P9_8 XMC_GPIO_PORT9, 8 +#define P9_9 XMC_GPIO_PORT9, 9 +#define P9_10 XMC_GPIO_PORT9, 10 +#define P9_11 XMC_GPIO_PORT9, 11 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_8_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_11_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_2_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_4_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_6_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_7_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_8_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_10_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_11_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_4_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_5_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_6_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_8_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P9_0_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_1_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_2_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_3_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_7_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_10_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_11_AF_U2C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P7_0_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_1_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_2_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_3_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_8_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_0_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_1_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_3_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_8_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_11_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P7_0 XMC_GPIO_PORT7, 0 +#define P7_1 XMC_GPIO_PORT7, 1 +#define P7_2 XMC_GPIO_PORT7, 2 +#define P7_3 XMC_GPIO_PORT7, 3 +#define P7_4 XMC_GPIO_PORT7, 4 +#define P7_5 XMC_GPIO_PORT7, 5 +#define P7_6 XMC_GPIO_PORT7, 6 +#define P7_7 XMC_GPIO_PORT7, 7 +#define P7_8 XMC_GPIO_PORT7, 8 +#define P7_9 XMC_GPIO_PORT7, 9 +#define P7_10 XMC_GPIO_PORT7, 10 +#define P7_11 XMC_GPIO_PORT7, 11 +#define P8_0 XMC_GPIO_PORT8, 0 +#define P8_1 XMC_GPIO_PORT8, 1 +#define P8_2 XMC_GPIO_PORT8, 2 +#define P8_3 XMC_GPIO_PORT8, 3 +#define P8_4 XMC_GPIO_PORT8, 4 +#define P8_5 XMC_GPIO_PORT8, 5 +#define P8_6 XMC_GPIO_PORT8, 6 +#define P8_7 XMC_GPIO_PORT8, 7 +#define P8_8 XMC_GPIO_PORT8, 8 +#define P8_9 XMC_GPIO_PORT8, 9 +#define P8_10 XMC_GPIO_PORT8, 10 +#define P8_11 XMC_GPIO_PORT8, 11 +#define P9_0 XMC_GPIO_PORT9, 0 +#define P9_1 XMC_GPIO_PORT9, 1 +#define P9_2 XMC_GPIO_PORT9, 2 +#define P9_3 XMC_GPIO_PORT9, 3 +#define P9_4 XMC_GPIO_PORT9, 4 +#define P9_5 XMC_GPIO_PORT9, 5 +#define P9_6 XMC_GPIO_PORT9, 6 +#define P9_7 XMC_GPIO_PORT9, 7 +#define P9_8 XMC_GPIO_PORT9, 8 +#define P9_9 XMC_GPIO_PORT9, 9 +#define P9_10 XMC_GPIO_PORT9, 10 +#define P9_11 XMC_GPIO_PORT9, 11 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_11_AF_ECAT0_LED_STATE_RUN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_10_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_10_AF_ECAT0_SYNC1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_0_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_1_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_8_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_11_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_5_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_6_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_0_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_1_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_2_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_2_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_3_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_4_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_6_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_7_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_8_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P7_8_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P7_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_10_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P7_11_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_0_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P8_1_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P8_2_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P8_3_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P8_4_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_5_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_6_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P8_8_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P8_9_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P8_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P9_0_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_0_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_1_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_1_AF_ECAT0_SYNC1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_2_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_2_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_3_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_3_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_4_AF_ECAT0_LED_STATE_RUN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P9_4_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_5_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_6_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_7_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_8_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_9_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P9_10_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P9_11_AF_U2C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_2_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P7_0_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_1_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_2_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_3_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P7_8_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_0_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_1_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P8_3_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P9_7_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 + + +/* Alternate Output Function */ +#define P0_0_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_11_AF_ECAT0_LED_STATE_RUN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_10_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_10_AF_ECAT0_SYNC1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_0_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_1_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P1_7 XMC_GPIO_PORT1, 7 +#define P1_8 XMC_GPIO_PORT1, 8 +#define P1_9 XMC_GPIO_PORT1, 9 +#define P1_10 XMC_GPIO_PORT1, 10 +#define P1_11 XMC_GPIO_PORT1, 11 +#define P1_12 XMC_GPIO_PORT1, 12 +#define P1_13 XMC_GPIO_PORT1, 13 +#define P1_14 XMC_GPIO_PORT1, 14 +#define P1_15 XMC_GPIO_PORT1, 15 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 +#define P2_12 XMC_GPIO_PORT2, 12 +#define P2_13 XMC_GPIO_PORT2, 13 +#define P2_14 XMC_GPIO_PORT2, 14 +#define P2_15 XMC_GPIO_PORT2, 15 +#define P3_0 XMC_GPIO_PORT3, 0 +#define P3_1 XMC_GPIO_PORT3, 1 +#define P3_2 XMC_GPIO_PORT3, 2 +#define P3_3 XMC_GPIO_PORT3, 3 +#define P3_4 XMC_GPIO_PORT3, 4 +#define P3_5 XMC_GPIO_PORT3, 5 +#define P3_6 XMC_GPIO_PORT3, 6 +#define P3_7 XMC_GPIO_PORT3, 7 +#define P3_8 XMC_GPIO_PORT3, 8 +#define P3_9 XMC_GPIO_PORT3, 9 +#define P3_10 XMC_GPIO_PORT3, 10 +#define P3_11 XMC_GPIO_PORT3, 11 +#define P3_12 XMC_GPIO_PORT3, 12 +#define P3_13 XMC_GPIO_PORT3, 13 +#define P3_14 XMC_GPIO_PORT3, 14 +#define P3_15 XMC_GPIO_PORT3, 15 +#define P4_0 XMC_GPIO_PORT4, 0 +#define P4_1 XMC_GPIO_PORT4, 1 +#define P4_2 XMC_GPIO_PORT4, 2 +#define P4_3 XMC_GPIO_PORT4, 3 +#define P4_4 XMC_GPIO_PORT4, 4 +#define P4_5 XMC_GPIO_PORT4, 5 +#define P4_6 XMC_GPIO_PORT4, 6 +#define P4_7 XMC_GPIO_PORT4, 7 +#define P5_0 XMC_GPIO_PORT5, 0 +#define P5_1 XMC_GPIO_PORT5, 1 +#define P5_2 XMC_GPIO_PORT5, 2 +#define P5_3 XMC_GPIO_PORT5, 3 +#define P5_4 XMC_GPIO_PORT5, 4 +#define P5_5 XMC_GPIO_PORT5, 5 +#define P5_6 XMC_GPIO_PORT5, 6 +#define P5_7 XMC_GPIO_PORT5, 7 +#define P5_8 XMC_GPIO_PORT5, 8 +#define P5_9 XMC_GPIO_PORT5, 9 +#define P5_10 XMC_GPIO_PORT5, 10 +#define P5_11 XMC_GPIO_PORT5, 11 +#define P6_0 XMC_GPIO_PORT6, 0 +#define P6_1 XMC_GPIO_PORT6, 1 +#define P6_2 XMC_GPIO_PORT6, 2 +#define P6_3 XMC_GPIO_PORT6, 3 +#define P6_4 XMC_GPIO_PORT6, 4 +#define P6_5 XMC_GPIO_PORT6, 5 +#define P6_6 XMC_GPIO_PORT6, 6 +#define P14_0 XMC_GPIO_PORT14, 0 +#define P14_1 XMC_GPIO_PORT14, 1 +#define P14_2 XMC_GPIO_PORT14, 2 +#define P14_3 XMC_GPIO_PORT14, 3 +#define P14_4 XMC_GPIO_PORT14, 4 +#define P14_5 XMC_GPIO_PORT14, 5 +#define P14_6 XMC_GPIO_PORT14, 6 +#define P14_7 XMC_GPIO_PORT14, 7 +#define P14_8 XMC_GPIO_PORT14, 8 +#define P14_9 XMC_GPIO_PORT14, 9 +#define P14_12 XMC_GPIO_PORT14, 12 +#define P14_13 XMC_GPIO_PORT14, 13 +#define P14_14 XMC_GPIO_PORT14, 14 +#define P14_15 XMC_GPIO_PORT14, 15 +#define P15_2 XMC_GPIO_PORT15, 2 +#define P15_3 XMC_GPIO_PORT15, 3 +#define P15_4 XMC_GPIO_PORT15, 4 +#define P15_5 XMC_GPIO_PORT15, 5 +#define P15_6 XMC_GPIO_PORT15, 6 +#define P15_7 XMC_GPIO_PORT15, 7 +#define P15_8 XMC_GPIO_PORT15, 8 +#define P15_9 XMC_GPIO_PORT15, 9 +#define P15_12 XMC_GPIO_PORT15, 12 +#define P15_13 XMC_GPIO_PORT15, 13 +#define P15_14 XMC_GPIO_PORT15, 14 +#define P15_15 XMC_GPIO_PORT15, 15 + + +/* Alternate Output Function */ +#define P0_0_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_0_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_1_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_2_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_2_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_3_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_4_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_5_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_5_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_6_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_6_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_7_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_7_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_8_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_8_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_9_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_9_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_10_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_10_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_11_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_12_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_12_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_13_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_13_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_14_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_14_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_15_AF_U1C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P0_15_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_0_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_1_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_2_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_2_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_2_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_3_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_3_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_3_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_5_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_8_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_9_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_10_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_10_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_11_AF_ECAT0_LED_STATE_RUN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_11_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_11_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_11_AF_ECAT0_LED_RUN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_12_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_12_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_12_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_12_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_13_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_13_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_13_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_13_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_14_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_14_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_14_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_DSD_MCLK2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_15_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_1_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_2_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_2_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_2_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_2_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_3_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_3_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_3_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_4_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_4_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_4_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_5_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_U2C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_7_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_10_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_10_AF_ECAT0_SYNC1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_11_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_12_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_12_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_12_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_13_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_13_AF_ECAT0_P1_TXD2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_13_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_14_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_14_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_14_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_14_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_15_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_15_AF_ECAT0_P1_TXD3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_15_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_15_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_0_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_0_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_0_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_0_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_1_AF_ECAT0_P1_TXD0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_USB_DRIVEVBUS XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_2_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_2_AF_ECAT0_P1_TXD1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_2_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_3_AF_U1C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_3_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_4_AF_U2C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_4_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_4_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_4_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_5_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_5_AF_U1C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_5_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_6_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_6_AF_CCU42_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_7_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_7_AF_LEDTS0_LINE0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_8_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_8_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_8_AF_LEDTS0_LINE1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_9_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_9_AF_CAN_N1_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_9_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_9_AF_LEDTS0_LINE2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_10_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_10_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_10_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_10_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_11_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_11_AF_CCU42_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_11_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_12_AF_ECAT0_P1_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_12_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_12_AF_CCU42_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_12_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_13_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P3_13_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_13_AF_CCU42_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P3_13_AF_LEDTS0_LINE6 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P3_14_AF_U1C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P3_15_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_DSD_MCLK1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_1_AF_U2C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_1_AF_DSD_MCLK0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_2_AF_U2C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_2_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_2_AF_U2C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_3_AF_U2C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_3_AF_U0C0_SELO5 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_3_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_3_AF_ECAT0_MCLK XMC_GPIO_MODE_OUTPUT_ALT4 +#define P4_4_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_4_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_5_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_5_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_6_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P4_7_AF_U2C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P4_7_AF_CAN_N2_TXD XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_0_AF_DSD_CGPWMN XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_0_AF_CCU81_OUT33 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_DSD_CGPWMP XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_1_AF_CCU81_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_2_AF_U2C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_2_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_2_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_3_AF_U2C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_3_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_3_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_4_AF_U2C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_4_AF_CCU81_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_5_AF_U2C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_5_AF_CCU81_OUT12 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_6_AF_U2C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_6_AF_CCU81_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_7_AF_CCU81_OUT02 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_8_AF_ECAT0_P1_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_8_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_8_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_8_AF_CAN_N4_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_9_AF_U1C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_9_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_9_AF_ETH0_TX_EN XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_10_AF_U1C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_10_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_10_AF_LEDTS0_LINE7 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_11_AF_U1C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_11_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P5_11_AF_CAN_N5_TXD XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_0_AF_ETH0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_0_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_0_AF_CCU81_OUT31 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_1_AF_ETH0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_1_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_1_AF_ECAT0_P0_TX_ENA XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_2_AF_ETH0_TXER XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_2_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_2_AF_CCU43_OUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_2_AF_ECAT0_P0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_3_AF_CCU43_OUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_3_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_4_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_4_AF_CCU43_OUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_4_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_5_AF_CAN_N3_TXD XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_5_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P6_5_AF_CCU43_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_5_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P6_6_AF_U2C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P6_6_AF_DSD_MCLK3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P6_6_AF_ECAT0_P0_TXD3 XMC_GPIO_MODE_OUTPUT_ALT4 + +/* HW control options */ +#define P0_2_HWCTRL_U1C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_2_HWCTRL_EBU_AD0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_3_HWCTRL_U1C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_3_HWCTRL_EBU_AD1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_4_HWCTRL_U1C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_4_HWCTRL_EBU_AD2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_5_HWCTRL_U1C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_5_HWCTRL_EBU_AD3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_6_HWCTRL_EBU_ADV XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_7_HWCTRL_EBU_AD6 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_8_HWCTRL_EBU_AD7 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_9_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_9_HWCTRL_EBU_CS1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_11_HWCTRL_SDMMC_RESET XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_11_HWCTRL_EBU_BREQ XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_12_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_12_HWCTRL_EBU_HLDA_OUT XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P0_14_HWCTRL_U1C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P0_15_HWCTRL_U1C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_2_HWCTRL_EBU_AD14 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_3_HWCTRL_EBU_AD15 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_4_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_5_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_SDMMC_DATA_OUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_6_HWCTRL_EBU_AD10 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_7_HWCTRL_SDMMC_DATA_OUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_7_HWCTRL_EBU_AD11 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_8_HWCTRL_SDMMC_DATA_OUT4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_8_HWCTRL_EBU_AD12 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_9_HWCTRL_SDMMC_DATA_OUT5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_9_HWCTRL_EBU_AD13 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_11_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_SDMMC_DATA_OUT6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_12_HWCTRL_EBU_AD16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_13_HWCTRL_SDMMC_DATA_OUT7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P1_13_HWCTRL_EBU_AD17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_14_HWCTRL_EBU_AD18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_15_HWCTRL_EBU_AD19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_0_HWCTRL_ETH0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_0_HWCTRL_EBU_AD20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_1_HWCTRL_DB_TDO_TRACESWO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_1_HWCTRL_EBU_AD21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_2_HWCTRL_LEDTS0_TSIN0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_2_HWCTRL_EBU_AD22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_3_HWCTRL_LEDTS0_TSIN1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_3_HWCTRL_EBU_AD23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_4_HWCTRL_LEDTS0_TSIN2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_4_HWCTRL_EBU_AD24 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_5_HWCTRL_LEDTS0_TSIN3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_5_HWCTRL_EBU_AD25 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_6_HWCTRL_U2C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_LEDTS0_TSIN4 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_8_HWCTRL_EBU_AD26 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_9_HWCTRL_LEDTS0_TSIN5 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_9_HWCTRL_EBU_AD27 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_10_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_10_HWCTRL_EBU_AD28 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_11_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_11_HWCTRL_EBU_AD29 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_12_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_12_HWCTRL_EBU_AD30 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_13_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_13_HWCTRL_EBU_AD31 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_14_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_14_HWCTRL_EBU_BC0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P2_15_HWCTRL_LEDTS0_TSIN6 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P2_15_HWCTRL_EBU_BC1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_0_HWCTRL_EBU_RD XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_1_HWCTRL_EBU_RD_NWR XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_2_HWCTRL_EBU_CS0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_3_HWCTRL_SDMMC_LED XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_4_HWCTRL_SDMMC_BUS_POWER XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_SDMMC_CMD_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_5_HWCTRL_EBU_AD4 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_6_HWCTRL_SDMMC_CLK_OUT XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_6_HWCTRL_EBU_AD5 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P3_10_HWCTRL_U0C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_11_HWCTRL_U0C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_12_HWCTRL_U0C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_13_HWCTRL_U0C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_14_HWCTRL_U1C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P3_15_HWCTRL_U1C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_SDMMC_DATA_OUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_0_HWCTRL_EBU_AD8 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_1_HWCTRL_SDMMC_DATA_OUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_1_HWCTRL_EBU_AD9 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P4_2_HWCTRL_ECAT0_MDO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_4_HWCTRL_U2C1_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_5_HWCTRL_U2C1_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_6_HWCTRL_U2C1_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P4_7_HWCTRL_U2C1_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_0_HWCTRL_U2C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_1_HWCTRL_U2C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_CKE XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_3_HWCTRL_EBU_A20 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_4_HWCTRL_EBU_RAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_4_HWCTRL_EBU_A21 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_5_HWCTRL_EBU_CAS XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_5_HWCTRL_EBU_A22 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_6_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_6_HWCTRL_EBU_A23 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_7_HWCTRL_U2C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_8_HWCTRL_EBU_CS2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_9_HWCTRL_EBU_BFCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P5_9_HWCTRL_EBU_CS3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P5_10_HWCTRL_LEDTS0_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_DB_ETM_TRACECLK XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_0_HWCTRL_EBU_A16 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_1_HWCTRL_DB_ETM_TRACEDATA3 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_1_HWCTRL_EBU_A17 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_2_HWCTRL_DB_ETM_TRACEDATA2 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_2_HWCTRL_EBU_A18 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_4_HWCTRL_EBU_SDCLKO XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_4_HWCTRL_EBU_A19 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_5_HWCTRL_DB_ETM_TRACEDATA1 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_5_HWCTRL_EBU_BC2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P6_6_HWCTRL_DB_ETM_TRACEDATA0 XMC_GPIO_HWCTRL_PERIPHERAL1 +#define P6_6_HWCTRL_EBU_BC3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#endif + +#endif /* XMC4_GPIO_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_rtc.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_rtc.h new file mode 100644 index 00000000..dd5f223a --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_rtc.h @@ -0,0 +1,142 @@ +/** + * @file xmc4_rtc.h + * @date 2015-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial + * + * 2015-05-20: + * - Documentation updates
+ * + * @endcond + * + */ + +#ifndef XMC4_RTC_H +#define XMC4_RTC_H + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup RTC + * @{ + */ + +/********************************************************************************************************************* + * ENUMS + *********************************************************************************************************************/ + +/** + * Wakeup events for RTC from hibernate domain + */ +typedef enum XMC_RTC_WAKEUP_EVENT +{ + XMC_RTC_WAKEUP_EVENT_ON_ALARM = RTC_CTR_TAE_Msk, /**< Wakeup from alarm event */ + XMC_RTC_WAKEUP_EVENT_ON_SECONDS = RTC_CTR_ESEC_Msk, /**< Wakeup from seconds event */ + XMC_RTC_WAKEUP_EVENT_ON_MINUTES = RTC_CTR_EMIC_Msk, /**< Wakeup from minutes event */ + XMC_RTC_WAKEUP_EVENT_ON_HOURS = RTC_CTR_EHOC_Msk, /**< Wakeup from hours event */ + XMC_RTC_WAKEUP_EVENT_ON_DAYS = RTC_CTR_EDAC_Msk, /**< Wakeup from days event */ + XMC_RTC_WAKEUP_EVENT_ON_MONTHS = RTC_CTR_EMOC_Msk, /**< Wakeup from months event */ + XMC_RTC_WAKEUP_EVENT_ON_YEARS = RTC_CTR_EYEC_Msk /**< Wakeup from years event */ +} XMC_RTC_WAKEUP_EVENT_t; + +/********************************************************************************************************************* + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param event A valid RTC Wakeup event (::XMC_RTC_WAKEUP_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Enable Wakeup from hibernate mode
+ * + * \par + * The function sets the bitfields of CTR register to enable wakeup from hibernate mode. + * Setting the masking value for the RTC wakeup events containing in the ::XMC_RTC_WAKEUP_EVENT_t + * leads to a wakeup from hibernate mode. + * + * \parRelated APIs:
+ * XMC_RTC_DisableHibernationWakeUp() + */ +__STATIC_INLINE void XMC_RTC_EnableHibernationWakeUp(const uint32_t event) +{ + RTC->CTR |= event; +} + +/** + * @param event A valid RTC Wakeup event (::XMC_RTC_WAKEUP_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Disable Wakeup from hibernate mode
+ * + * \par + * The function resets the bitfields of CTR register to disable wakeup from hibernate mode. + * Resetting the masking value for the RTC wakeup events containing in the ::XMC_RTC_WAKEUP_EVENT_t + * disables wakeup from hibernate mode. + * + * \parRelated APIs:
+ * XMC_RTC_EnableHibernationWakeUp() + */ +__STATIC_INLINE void XMC_RTC_DisableHibernationWakeUp(const uint32_t event) +{ + RTC->CTR &= ~event; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XMC4_RTC_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_scu.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_scu.h new file mode 100644 index 00000000..8ddaf6b0 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_scu.h @@ -0,0 +1,3418 @@ +/** + * @file xmc4_scu.h + * @date 2016-06-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial version + * - Documentation improved + * + * 2015-11-30: + * - Documentation improved + * + * 2016-03-09: + * - Added XMC_SCU_POWER_EnableMonitor/XMC_SCU_POWER_DisableMonitor + * XMC_SCU_POWER_GetEVRStatus, XMC_SCU_POWER_GetEVR13Voltage, XMC_SCU_POWER_GetEVR33Voltage + * - Added XMC_SCU_HIB_GetHibernateControlStatus, + * XMC_SCU_HIB_GetEventStatus, XMC_SCU_HIB_ClearEventStatus, XMC_SCU_HIB_TriggerEvent, + * XMC_SCU_HIB_EnableEvent, XMC_SCU_HIB_DisableEvent + * - Added XMC_SCU_HIB_SetWakeupTriggerInput, XMC_SCU_HIB_SetPinMode, XMC_SCU_HIB_SetOutputPinLevel, + * XMC_SCU_HIB_SetInput0, XMC_SCU_HIB_EnterHibernateState + * + * 2016-04-15: + * - Fixed naming of XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG peripheral clock. + * Added enable and disable for peripheral clocks + * + * 2016-05-19: + * - Added XMC_SCU_CLOCK_IsLowPowerOscillatorStable() and XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() + * - Added XMC_SCU_POWER_WaitForInterrupt() and XMC_SCU_POWER_WaitForEvent() + * - Added XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus() + * - Added XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus() + * - Removed XMC_SCU_INTERRUPT_EVENT_OSCULSTAT_UPDATED, XMC_SCU_INTERRUPT_EVENT_HDSTAT_UPDATED + * + * 2016-06-14: + * - Added XMC_SCU_HIB_IsWakeupEventDetected() and XMC_SCU_HIB_ClearWakeupEventDetectionStatus() + * + * 2016-06-15: + * - Added XMC_SCU_HIB_EnterHibernateStateEx() which allows to select between external or internal hibernate mode. This last mode only available in XMC44, XMC42 and XMC41 series. + * - Extended wakeup hibernate events using LPAC wakeup on events. Only available in XMC44, XMC42 and XMC41 series. + * - Added LPAC APIs. Only available in XMC44, XMC42 and XMC41 series. + * + * @endcond + * + */ + +#ifndef XMC4_SCU_H +#define XMC4_SCU_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_common.h" + +#if UC_FAMILY == XMC4 + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup SCU + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define PLL_PDIV_XTAL_8MHZ (1U) /* PDIV value for main PLL settings, fPLL = 120MHz with fOSC = 8MHz */ +#define PLL_NDIV_XTAL_8MHZ (89U) /* NDIV value for main PLL settings, fPLL = 120MHz with fOSC = 8MHz */ +#define PLL_K2DIV_XTAL_8MHZ (2U) /* K2DIV value for main PLL settings, fPLL = 120MHz with fOSC = 8MHz */ + +#define PLL_PDIV_XTAL_12MHZ (1U) /* PDIV value for main PLL settings, fPLL = 120MHz with fOSC = 12MHz */ +#define PLL_NDIV_XTAL_12MHZ (79U) /* NDIV value for main PLL settings, fPLL = 120MHz with fOSC = 12MHz */ +#define PLL_K2DIV_XTAL_12MHZ (3U) /* K2DIV value for main PLL settings, fPLL = 120MHz with fOSC = 12MHz */ + +#define PLL_PDIV_XTAL_16MHZ (1U) /* PDIV value for main PLL settings, fPLL = 120MHz with fOSC = 16MHz */ +#define PLL_NDIV_XTAL_16MHZ (59U) /* NDIV value for main PLL settings, fPLL = 120MHz with fOSC = 16MHz */ +#define PLL_K2DIV_XTAL_16MHZ (3U) /* K2DIV value for main PLL settings, fPLL = 120MHz with fOSC = 16MHz */ + +#define XMC_SCU_INTERRUPT_EVENT_WDT_WARN SCU_INTERRUPT_SRSTAT_PRWARN_Msk /**< Watchdog prewarning event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC SCU_INTERRUPT_SRSTAT_PI_Msk /**< RTC periodic interrupt. */ +#define XMC_SCU_INTERRUPT_EVENT_RTC_ALARM SCU_INTERRUPT_SRSTAT_AI_Msk /**< RTC alarm event. */ +#define XMC_SCU_INTERRUPT_EVENT_DLR_OVERRUN SCU_INTERRUPT_SRSTAT_DLROVR_Msk /**< DLR overrun event. */ +#if defined(SCU_INTERRUPT_SRSTAT_LPACCR_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACCR_UPDATED SCU_INTERRUPT_SRSTAT_LPACCR_Msk /**< LPAC Control register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_LPACTH0_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACTH0_UPDATED SCU_INTERRUPT_SRSTAT_LPACTH0_Msk /**< LPAC Threshold-0 register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_LPACTH1_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACTH1_UPDATED SCU_INTERRUPT_SRSTAT_LPACTH1_Msk /**< LPAC Threshold-1 register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_LPACST_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACST_UPDATED SCU_INTERRUPT_SRSTAT_LPACST_Msk /**< LPAC Status register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_LPACCLR_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACCLR_UPDATED SCU_INTERRUPT_SRSTAT_LPACCLR_Msk /**< LPAC event clear register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_LPACSET_Msk) +#define XMC_SCU_INTERRUPT_EVENT_LPACSET_UPDATED SCU_INTERRUPT_SRSTAT_LPACSET_Msk /**< LPAC event set register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_HINTST_Msk) +#define XMC_SCU_INTERRUPT_EVENT_HINTST_UPDATED SCU_INTERRUPT_SRSTAT_HINTST_Msk /**< HIB HINTST register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_HINTCLR_Msk) +#define XMC_SCU_INTERRUPT_EVENT_HINTCLR_UPDATED SCU_INTERRUPT_SRSTAT_HINTCLR_Msk /**< HIB HINTCLR register update event. */ +#endif +#if defined(SCU_INTERRUPT_SRSTAT_HINTSET_Msk) +#define XMC_SCU_INTERRUPT_EVENT_HINTSET_UPDATED SCU_INTERRUPT_SRSTAT_HINTSET_Msk /**< HIB HINTSET register update event. */ +#endif +#define XMC_SCU_INTERRUPT_EVENT_HDCLR_UPDATED SCU_INTERRUPT_SRSTAT_HDCLR_Msk /**< HIB HDCLR register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_HDSET_UPDATED SCU_INTERRUPT_SRSTAT_HDSET_Msk /**< HIB HDSET register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_HDCR_UPDATED SCU_INTERRUPT_SRSTAT_HDCR_Msk /**< HIB HDCR register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_OSCSICTRL_UPDATED SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk /**< HIB OSCSICTRL register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_OSCULCTRL_UPDATED SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk /**< HIB OSCULCTRL register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk /**< HIB RTCCTR register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk /**< HIB RTCATIM0 register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk /**< HIB RTCATIM1 register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk /**< HIB TIM0 register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk /**< HIB TIM1 register update event. */ +#define XMC_SCU_INTERRUPT_EVENT_RMX_UPDATED SCU_INTERRUPT_SRSTAT_RMX_Msk /**< HIB RMX register update event. */ + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +/** + * Defines Capture/Compare unit timer slice trigger, that enables synchronous start function available on the \a SCU, + * CCUCON register. Use type \a XMC_SCU_CCU_TRIGGER_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CCU_TRIGGER +{ +#if defined(CCU40) + XMC_SCU_CCU_TRIGGER_CCU40 = SCU_GENERAL_CCUCON_GSC40_Msk, /**< Trigger mask used for Global Start Control of + CCU40 peripheral. */ +#endif +#if defined(CCU41) + XMC_SCU_CCU_TRIGGER_CCU41 = SCU_GENERAL_CCUCON_GSC41_Msk, /**< Trigger mask used for Global Start Control of + CCU41 peripheral. */ +#endif +#if defined(CCU42) + XMC_SCU_CCU_TRIGGER_CCU42 = SCU_GENERAL_CCUCON_GSC42_Msk, /**< Trigger mask used for Global Start Control of + CCU42 peripheral. */ +#endif +#if defined(CCU43) + XMC_SCU_CCU_TRIGGER_CCU43 = SCU_GENERAL_CCUCON_GSC43_Msk, /**< Trigger mask used for Global Start Control of + CCU43 peripheral. */ +#endif +#if defined(CCU80) + XMC_SCU_CCU_TRIGGER_CCU80 = SCU_GENERAL_CCUCON_GSC80_Msk, /**< Trigger mask used for Global Start Control of + CCU80 peripheral. */ +#endif +#if defined(CCU81) + XMC_SCU_CCU_TRIGGER_CCU81 = SCU_GENERAL_CCUCON_GSC81_Msk /**< Trigger mask used for Global Start Control of + CCU81 peripheral. */ +#endif +} XMC_SCU_CCU_TRIGGER_t; + +/** + * Defines enumerations representing the status of trap cause. The cause of the trap gets automatically stored in + * the \a TRAPSTAT register and can be checked by user software to determine the state of the system and for debug + * purpose. + * Use type \a XMC_SCU_TRAP_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_TRAP +{ + XMC_SCU_TRAP_OSC_WDG = SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk, /**< OSC_HP Oscillator Watchdog trap. */ + XMC_SCU_TRAP_VCO_LOCK = SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk, /**< PLL loss of lock trap. */ + XMC_SCU_TRAP_USB_VCO_LOCK = SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk, /**< USB PLL loss of lock trap. */ + XMC_SCU_TRAP_PARITY_ERROR = SCU_TRAP_TRAPSTAT_PET_Msk, /**< Memory Parity error trap. */ + XMC_SCU_TRAP_BROWNOUT = SCU_TRAP_TRAPSTAT_BRWNT_Msk, /**< Brownout trap. */ + XMC_SCU_TRAP_ULP_WDG = SCU_TRAP_TRAPSTAT_ULPWDGT_Msk, /**< Unstable 32KHz clock trap. */ + XMC_SCU_TRAP_PER_BRIDGE0 = SCU_TRAP_TRAPSTAT_BWERR0T_Msk, /**< Bad memory access of peripherals on Bridge-0. */ + XMC_SCU_TRAP_PER_BRIDGE1 = SCU_TRAP_TRAPSTAT_BWERR1T_Msk, /**< Bad memory access of peripherals on Bridge-1. */ +#if defined(SCU_TRAP_TRAPSTAT_TEMPHIT_Msk) + XMC_SCU_TRAP_DIETEMP_HIGH = SCU_TRAP_TRAPSTAT_TEMPHIT_Msk, /**< Die temperature higher than expected. */ +#endif +#if defined(SCU_TRAP_TRAPSTAT_TEMPLOT_Msk) + XMC_SCU_TRAP_DIETEMP_LOW = SCU_TRAP_TRAPSTAT_TEMPLOT_Msk, /**< Die temperature lower than expected. */ +#endif +#if defined(ECAT0) + XMC_SCU_TRAP_ECAT_RESET = SCU_TRAP_TRAPSTAT_ECAT0RST_Msk, /**< EtherCat Reset */ +#endif +} XMC_SCU_TRAP_t; + +/** + * Defines enumerations for different parity event generating modules that in turn generate a trap. + * Parity can be enabled with \a PETE register in order to get the trap flag reflected in \a TRAPRAW register. These enums are used to + * configure parity error trap generation mechanism bits of \a PETE register. + * All the enum items are tabulated as per bits present in \a PETE register. + * Use type \a XMC_SCU_PARITY_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_PARITY +{ + XMC_SCU_PARITY_PSRAM_MEM = SCU_PARITY_PEEN_PEENPS_Msk, /**< Program SRAM parity error trap. */ + XMC_SCU_PARITY_DSRAM1_MEM = SCU_PARITY_PEEN_PEENDS1_Msk, /**< Data SRAM-1 parity error trap. */ +#if defined(XMC_SCU_PARITY_DSRAM2_MEM) + XMC_SCU_PARITY_DSRAM2_MEM = SCU_PARITY_PEEN_PEENDS2_Msk, /**< Data SRAM-2 parity error trap. */ +#endif + XMC_SCU_PARITY_USIC0_MEM = SCU_PARITY_PEEN_PEENU0_Msk, /**< USIC0 memory parity error trap. */ +#if defined(XMC_SCU_PARITY_USIC1_MEM) + XMC_SCU_PARITY_USIC1_MEM = SCU_PARITY_PEEN_PEENU1_Msk, /**< USIC1 memory parity error trap. */ +#endif +#if defined(XMC_SCU_PARITY_USIC2_MEM) + XMC_SCU_PARITY_USIC2_MEM = SCU_PARITY_PEEN_PEENU2_Msk, /**< USIC2 memory parity error trap. */ +#endif + XMC_SCU_PARITY_MCAN_MEM = SCU_PARITY_PEEN_PEENMC_Msk, /**< CAN memory parity error trap. */ + XMC_SCU_PARITY_PMU_MEM = SCU_PARITY_PEEN_PEENPPRF_Msk, /**< PMU Prefetch memory parity error trap. */ + XMC_SCU_PARITY_USB_MEM = SCU_PARITY_PEEN_PEENUSB_Msk, /**< USB memory parity error trap. */ +#if defined(SCU_PARITY_PEEN_PEENETH0TX_Msk) + XMC_SCU_PARITY_ETH_TXMEM = SCU_PARITY_PEEN_PEENETH0TX_Msk, /**< Ethernet transmit memory parity error trap. */ +#endif +#if defined(SCU_PARITY_PEEN_PEENETH0RX_Msk) + XMC_SCU_PARITY_ETH_RXMEM = SCU_PARITY_PEEN_PEENETH0RX_Msk, /**< Ethernet receive memory parity error trap. */ +#endif +#if defined(SCU_PARITY_PEEN_PEENSD0_Msk) + XMC_SCU_PARITY_SDMMC_MEM0 = SCU_PARITY_PEEN_PEENSD0_Msk, /**< SDMMC Memory-0 parity error trap. */ +#endif +#if defined(SCU_PARITY_PEEN_PEENSD1_Msk) + XMC_SCU_PARITY_SDMMC_MEM1 = SCU_PARITY_PEEN_PEENSD1_Msk, /**< SDMMC Memory-1 parity error trap. */ +#endif +} XMC_SCU_PARITY_t; + +/** + * Defines the different causes for last reset. The cause of the last reset gets automatically stored in + * the \a SCU_RSTSTAT register and can be checked by user software to determine the state of the system and for debuggging + * purpose. All the enum items are tabulated as per bits present in \a SCU_RSTSTAT register. + * Use type \a XMC_SCU_RESET_REASON_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_RESET_REASON +{ + XMC_SCU_RESET_REASON_PORST = (1UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Power on reset. */ + XMC_SCU_RESET_REASON_SWD = (2UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Supply Watchdog reset. */ + XMC_SCU_RESET_REASON_PV = (4UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Power Validation reset. */ + XMC_SCU_RESET_REASON_SW = (8UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Software reset. */ + XMC_SCU_RESET_REASON_LOCKUP = (16UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to reset due to CPU lockup. */ + XMC_SCU_RESET_REASON_WATCHDOG = (32UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Watchdog timer initiated reset. */ + XMC_SCU_RESET_REASON_PARITY_ERROR = (128UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to reset due to memory parity error. */ +} XMC_SCU_RESET_REASON_t; + +/** + * Defines enumerations for events which can lead to interrupt. These enumeration values represent the + * status of one of the bits in \a SRSTAT register. + * Use type \a XMC_SCU_INTERRUPT_EVENT_t for accessing these enum parameters. + */ +typedef uint32_t XMC_SCU_INTERRUPT_EVENT_t; + + +/** + * Defines enumeration for the events that can generate non maskable interrupt(NMI). + * The NMI generation can be enabled with \a NMIREQEN register. The event will be reflected in \a SRSTAT or will be + * mirrored in the TRAPSTAT register. These enums can be used to configure NMI request generation bits of \a + * NMIREQEN register. Once configured, these events can generate non maskable interrupt. + * All the enum items are tabulated as per bits present in \a NMIREQEN register. + * Use type \a XMC_SCU_NMIREQ_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_NMIREQ +{ + XMC_SCU_NMIREQ_WDT_WARN = SCU_INTERRUPT_NMIREQEN_PRWARN_Msk, /**< Watchdog timer Pre-Warning event */ + XMC_SCU_NMIREQ_RTC_PI = SCU_INTERRUPT_NMIREQEN_PI_Msk, /**< RTC Periodic event */ + XMC_SCU_NMIREQ_RTC_AI = SCU_INTERRUPT_NMIREQEN_AI_Msk, /**< RTC Alarm event */ + XMC_SCU_NMIREQ_ERU0_0 = SCU_INTERRUPT_NMIREQEN_ERU00_Msk, /**< Channel 0 event of ERU0 */ + XMC_SCU_NMIREQ_ERU0_1 = SCU_INTERRUPT_NMIREQEN_ERU01_Msk, /**< Channel 1 event of ERU0 */ + XMC_SCU_NMIREQ_ERU0_2 = SCU_INTERRUPT_NMIREQEN_ERU02_Msk, /**< Channel 2 event of ERU0 */ + XMC_SCU_NMIREQ_ERU0_3 = SCU_INTERRUPT_NMIREQEN_ERU03_Msk /**< Channel 3 event of ERU0 */ +} XMC_SCU_NMIREQ_t; + + +/** + * Defines enumeration representing different peripheral reset bits in the \a PRSTAT registers. + * All the enum items are tabulated as per bits present in \a PRSTAT0, \a PRSTAT1, \a PRSTAT2, + * \a PRSTAT3 registers. Use type \a XMC_SCU_PERIPHERAL_RESET_t for accessing these enum parameters. + * Note: Release of reset should be prevented when the peripheral clock is gated in cases where kernel + * clock and bus interface clocks are shared, in order to avoid system hang-up. + */ +typedef enum XMC_SCU_PERIPHERAL_RESET +{ + XMC_SCU_PERIPHERAL_RESET_VADC = SCU_RESET_PRSTAT0_VADCRS_Msk, /**< VADC reset. */ +#if defined(DSD) + XMC_SCU_PERIPHERAL_RESET_DSD = SCU_RESET_PRSTAT0_DSDRS_Msk, /**< DSD reset. */ +#endif + XMC_SCU_PERIPHERAL_RESET_CCU40 = SCU_RESET_PRSTAT0_CCU40RS_Msk, /**< CCU40 reset. */ +#if defined(CCU41) + XMC_SCU_PERIPHERAL_RESET_CCU41 = SCU_RESET_PRSTAT0_CCU41RS_Msk, /**< CCU41 reset. */ +#endif +#if defined(CCU42) + XMC_SCU_PERIPHERAL_RESET_CCU42 = SCU_RESET_PRSTAT0_CCU42RS_Msk, /**< CCU42 reset. */ +#endif +#if defined(CCU80) + XMC_SCU_PERIPHERAL_RESET_CCU80 = SCU_RESET_PRSTAT0_CCU80RS_Msk, /**< CCU80 reset. */ +#endif +#if defined(CCU81) + XMC_SCU_PERIPHERAL_RESET_CCU81 = SCU_RESET_PRSTAT0_CCU81RS_Msk, /**< CCU81 reset. */ +#endif +#if defined(POSIF0) + XMC_SCU_PERIPHERAL_RESET_POSIF0 = SCU_RESET_PRSTAT0_POSIF0RS_Msk, /**< POSIF0 reset. */ +#endif +#if defined(POSIF1) + XMC_SCU_PERIPHERAL_RESET_POSIF1 = SCU_RESET_PRSTAT0_POSIF1RS_Msk, /**< POSIF1 reset.*/ +#endif + XMC_SCU_PERIPHERAL_RESET_USIC0 = SCU_RESET_PRSTAT0_USIC0RS_Msk, /**< USIC0 reset. */ + XMC_SCU_PERIPHERAL_RESET_ERU1 = SCU_RESET_PRSTAT0_ERU1RS_Msk, /**< ERU1 reset. */ +#if defined(HRPWM0) + XMC_SCU_PERIPHERAL_RESET_HRPWM0 = SCU_RESET_PRSTAT0_HRPWM0RS_Msk, /**< HRPWM0 reset. */ +#endif +#if defined(CCU43) + XMC_SCU_PERIPHERAL_RESET_CCU43 = (SCU_RESET_PRSTAT1_CCU43RS_Msk | 0x10000000UL), /**< CCU43 reset. */ +#endif +#if defined(LEDTS0) + XMC_SCU_PERIPHERAL_RESET_LEDTS0 = (SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk | 0x10000000UL), /**< LEDTS0 reset. */ +#endif +#if defined(CAN) + XMC_SCU_PERIPHERAL_RESET_MCAN = (SCU_RESET_PRSTAT1_MCAN0RS_Msk | 0x10000000UL), /**< MCAN reset. */ +#endif +#if defined(DAC) + XMC_SCU_PERIPHERAL_RESET_DAC = (SCU_RESET_PRSTAT1_DACRS_Msk | 0x10000000UL), /**< DAC reset. */ +#endif +#if defined(SDMMC) + XMC_SCU_PERIPHERAL_RESET_SDMMC = (SCU_RESET_PRSTAT1_MMCIRS_Msk | 0x10000000UL), /**< SDMMC reset. */ +#endif +#if defined(USIC1) + XMC_SCU_PERIPHERAL_RESET_USIC1 = (SCU_RESET_PRSTAT1_USIC1RS_Msk | 0x10000000UL), /**< USIC1 reset. */ +#endif +#if defined(USIC2) + XMC_SCU_PERIPHERAL_RESET_USIC2 = (SCU_RESET_PRSTAT1_USIC2RS_Msk | 0x10000000UL), /**< USIC2 reset. */ +#endif + XMC_SCU_PERIPHERAL_RESET_PORTS = (SCU_RESET_PRSTAT1_PPORTSRS_Msk | 0x10000000UL), /**< PORTS reset. */ + XMC_SCU_PERIPHERAL_RESET_WDT = (SCU_RESET_PRSTAT2_WDTRS_Msk | 0x20000000UL), /**< WDT reset. */ +#if defined(ETH0) + XMC_SCU_PERIPHERAL_RESET_ETH0 = (SCU_RESET_PRSTAT2_ETH0RS_Msk | 0x20000000UL), /**< ETH0 reset. */ +#endif + XMC_SCU_PERIPHERAL_RESET_GPDMA0 = (SCU_RESET_PRSTAT2_DMA0RS_Msk | 0x20000000UL), /**< DMA0 reset. */ +#if defined(GPDMA1) + XMC_SCU_PERIPHERAL_RESET_GPDMA1 = (SCU_RESET_PRSTAT2_DMA1RS_Msk | 0x20000000UL), /**< DMA1 reset. */ +#endif +#if defined(FCE) + XMC_SCU_PERIPHERAL_RESET_FCE = (SCU_RESET_PRSTAT2_FCERS_Msk | 0x20000000UL), /**< FCE reset. */ +#endif +#if defined(USB0) + XMC_SCU_PERIPHERAL_RESET_USB0 = (SCU_RESET_PRSTAT2_USBRS_Msk | 0x20000000UL), /**< USB0 reset. */ +#endif +#if defined(ECAT0) + XMC_SCU_PERIPHERAL_RESET_ECAT0 = (SCU_RESET_PRSTAT2_ECAT0RS_Msk | 0x20000000UL), /**< ECAT0 reset. */ +#endif +#if defined(EBU) + XMC_SCU_PERIPHERAL_RESET_EBU = (SCU_RESET_PRSTAT3_EBURS_Msk | 0x30000000UL) /**< EBU reset. */ +#endif +} XMC_SCU_PERIPHERAL_RESET_t; + +/** + * Defines enumerations for disabling the clocks sources of peripherals. Disabling of the peripheral + * clock is configured via the \a CLKCLR registers. + * Use type \a XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK +{ + XMC_SCU_CLOCK_USB = SCU_CLK_CLKCLR_USBCDI_Msk, /**< USB module clock. */ +#if defined(SDMMC) + XMC_SCU_CLOCK_MMC = SCU_CLK_CLKCLR_MMCCDI_Msk, /**< MMC module clock. */ +#endif +#if defined(ETH0) + XMC_SCU_CLOCK_ETH = SCU_CLK_CLKCLR_ETH0CDI_Msk, /**< Ethernet module clock. */ +#endif +#if defined(EBU) + XMC_SCU_CLOCK_EBU = SCU_CLK_CLKCLR_EBUCDI_Msk, /**< EBU module clock. */ +#endif + XMC_SCU_CLOCK_CCU = SCU_CLK_CLKCLR_CCUCDI_Msk, /**< CCU module clock. */ + XMC_SCU_CLOCK_WDT = SCU_CLK_CLKCLR_WDTCDI_Msk /**< WDT module clock. */ +} XMC_SCU_CLOCK_t; + +#if(UC_SERIES != XMC45) +/** + * Defines enumeration for peripherals that support clock gating. + * The enumerations can be used for gating or ungating the peripheral clocks. + * All the enum items are tabulated as per bits present in \a CGATSTAT0 register. + * Use type \a XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_PERIPHERAL_CLOCK +{ + XMC_SCU_PERIPHERAL_CLOCK_VADC = SCU_CLK_CGATSTAT0_VADC_Msk, /**< VADC peripheral gating. */ +#if defined(DSD) + XMC_SCU_PERIPHERAL_CLOCK_DSD = SCU_CLK_CGATSTAT0_DSD_Msk, /**< DSD peripheral gating. */ +#endif + XMC_SCU_PERIPHERAL_CLOCK_CCU40 = SCU_CLK_CGATSTAT0_CCU40_Msk, /**< CCU40 peripheral gating. */ +#if defined(CCU41) + XMC_SCU_PERIPHERAL_CLOCK_CCU41 = SCU_CLK_CGATSTAT0_CCU41_Msk, /**< CCU41 peripheral gating. */ +#endif +#if defined(CCU42) + XMC_SCU_PERIPHERAL_CLOCK_CCU42 = SCU_CLK_CGATSTAT0_CCU42_Msk, /**< CCU42 peripheral gating. */ +#endif +#if defined(CCU80) + XMC_SCU_PERIPHERAL_CLOCK_CCU80 = SCU_CLK_CGATSTAT0_CCU80_Msk, /**< CCU80 peripheral gating. */ +#endif +#if defined(CCU81) + XMC_SCU_PERIPHERAL_CLOCK_CCU81 = SCU_CLK_CGATSTAT0_CCU81_Msk, /**< CCU81 peripheral gating. */ +#endif +#if defined(POSIF0) + XMC_SCU_PERIPHERAL_CLOCK_POSIF0 = SCU_CLK_CGATSTAT0_POSIF0_Msk, /**< POSIF0 peripheral gating. */ +#endif +#if defined(POSIF1) + XMC_SCU_PERIPHERAL_CLOCK_POSIF1 = SCU_CLK_CGATSTAT0_POSIF1_Msk, /**< POSIF1 peripheral gating. */ +#endif + XMC_SCU_PERIPHERAL_CLOCK_USIC0 = SCU_CLK_CGATSTAT0_USIC0_Msk, /**< USIC0 peripheral gating. */ + XMC_SCU_PERIPHERAL_CLOCK_ERU1 = SCU_CLK_CGATSTAT0_ERU1_Msk, /**< ERU1 peripheral gating. */ +#if defined(HRPWM0) + XMC_SCU_PERIPHERAL_CLOCK_HRPWM0 = SCU_CLK_CGATSTAT0_HRPWM0_Msk, /**< HRPWM0 peripheral gating. */ +#endif +#if defined(CCU43) + XMC_SCU_PERIPHERAL_CLOCK_CCU43 = (SCU_CLK_CGATSTAT1_CCU43_Msk | 0x10000000UL), /**< CCU43 peripheral gating. */ +#endif +#if defined(LEDTS0) + XMC_SCU_PERIPHERAL_CLOCK_LEDTS0 = (SCU_CLK_CGATSTAT1_LEDTSCU0_Msk | 0x10000000UL), /**< LEDTS0 peripheral gating. */ +#endif +#if defined(CAN) + XMC_SCU_PERIPHERAL_CLOCK_MCAN = (SCU_CLK_CGATSTAT1_MCAN0_Msk | 0x10000000UL), /**< MCAN peripheral gating. */ +#endif +#if defined(DAC) + XMC_SCU_PERIPHERAL_CLOCK_DAC = (SCU_CLK_CGATSTAT1_DAC_Msk | 0x10000000UL), /**< DAC peripheral gating. */ +#endif +#if defined(SDMMC) + XMC_SCU_PERIPHERAL_CLOCK_SDMMC = (SCU_CLK_CGATSTAT1_MMCI_Msk | 0x10000000UL), /**< SDMMC peripheral gating. */ +#endif +#if defined(USIC1) + XMC_SCU_PERIPHERAL_CLOCK_USIC1 = (SCU_CLK_CGATSTAT1_USIC1_Msk | 0x10000000UL), /**< USIC1 peripheral gating. */ +#endif +#if defined(USIC2) + XMC_SCU_PERIPHERAL_CLOCK_USIC2 = (SCU_CLK_CGATSTAT1_USIC2_Msk | 0x10000000UL), /**< USIC2 peripheral gating. */ +#endif + XMC_SCU_PERIPHERAL_CLOCK_PORTS = (SCU_CLK_CGATSTAT1_PPORTS_Msk | 0x10000000UL), /**< PORTS peripheral gating. */ + XMC_SCU_PERIPHERAL_CLOCK_WDT = (SCU_CLK_CGATSTAT2_WDT_Msk | 0x20000000UL), /**< WDT peripheral gating. */ +#if defined(ETH0) + XMC_SCU_PERIPHERAL_CLOCK_ETH0 = (SCU_CLK_CGATSTAT2_ETH0_Msk | 0x20000000UL), /**< ETH0 peripheral gating. */ +#endif + XMC_SCU_PERIPHERAL_CLOCK_GPDMA0 = (SCU_CLK_CGATSTAT2_DMA0_Msk | 0x20000000UL), /**< DMA0 peripheral gating. */ +#if defined(GPDMA1) + XMC_SCU_PERIPHERAL_CLOCK_GPDMA1 = (SCU_CLK_CGATSTAT2_DMA1_Msk | 0x20000000UL), /**< DMA1 peripheral gating. */ +#endif +#if defined(FCE) + XMC_SCU_PERIPHERAL_CLOCK_FCE = (SCU_CLK_CGATSTAT2_FCE_Msk | 0x20000000UL), /**< FCE peripheral gating. */ +#endif +#if defined(USB0) + XMC_SCU_PERIPHERAL_CLOCK_USB0 = (SCU_CLK_CGATSTAT2_USB_Msk | 0x20000000UL), /**< USB0 peripheral gating. */ +#endif +#if defined(ECAT0) + XMC_SCU_PERIPHERAL_CLOCK_ECAT0 = (SCU_CLK_CGATSTAT2_ECAT0_Msk | 0x20000000UL), /**< ECAT0 peripheral gating. */ +#endif +#if defined(EBU) + XMC_SCU_PERIPHERAL_CLOCK_EBU = (SCU_CLK_CGATSTAT3_EBU_Msk | 0x30000000UL) /**< EBU peripheral gating. */ +#endif +} XMC_SCU_PERIPHERAL_CLOCK_t; +#endif + +/** + * Defines options for system clock (fSYS) source. These enums are used to configure \a SYSSEL bits of \a SYSCLKCR + * Clock Control Register. + * Use type \a XMC_SCU_CLOCK_SYSCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_SYSCLKSRC +{ + XMC_SCU_CLOCK_SYSCLKSRC_OFI = (0UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos), /**< Internal Fast Clock (fOFI) as a + source for system clock (fSYS). */ + XMC_SCU_CLOCK_SYSCLKSRC_PLL = (1UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos) /**< PLL output (fPLL) as a + source for system clock (fSYS). */ +} XMC_SCU_CLOCK_SYSCLKSRC_t; + +/** + * Defines options for selecting the P-Divider input frequency. These enums are used to configure \a PINSEL bits of \a PLLCON2 + * register. + * Use type \a XMC_SCU_CLOCK_OSCCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_SYSPLLCLKSRC +{ + XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP = 0UL, /**< External crystal oscillator + (fOHP) as the source for P-Divider. */ + XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI = SCU_PLL_PLLCON2_PINSEL_Msk | SCU_PLL_PLLCON2_K1INSEL_Msk /**< Backup clock(fOFI) + as the source for P-Divider. */ +} XMC_SCU_CLOCK_SYSPLLCLKSRC_t; + +/** + * Defines options for selecting the USB clock source(fUSB/fSDMMC). + * These enums are used to configure \a USBSEL bits of \a USBCLKCR + * register. User can choose either fPLL or fUSBPLL clock as a source for USB clock. + * Use type \a XMC_SCU_CLOCK_USBCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_USBCLKSRC +{ + XMC_SCU_CLOCK_USBCLKSRC_USBPLL = (0UL << SCU_CLK_USBCLKCR_USBSEL_Pos), /**< USB PLL(fUSB PLL) as a + source for USB clock (fUSB/fSDMMC). */ + XMC_SCU_CLOCK_USBCLKSRC_SYSPLL = (1UL << SCU_CLK_USBCLKCR_USBSEL_Pos) /**< Main PLL output (fPLL) as a + source for USB clock (fUSB/fSDMMC). */ +} XMC_SCU_CLOCK_USBCLKSRC_t; + +#if defined(ECAT0) +/** + * Defines options for selecting the ECAT clock source. + */ +typedef enum XMC_SCU_CLOCK_ECATCLKSRC +{ + XMC_SCU_CLOCK_ECATCLKSRC_USBPLL = (0UL << SCU_CLK_ECATCLKCR_ECATSEL_Pos), /**< USB PLL (fUSBPLL) as a source for ECAT clock. */ + XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL = (1UL << SCU_CLK_ECATCLKCR_ECATSEL_Pos) /**< Main PLL output (fPLL) as a source for ECAT clock. */ +} XMC_SCU_CLOCK_ECATCLKSRC_t; +#endif + +/** + * Defines options for selecting the source of WDT clock(fWDT). These enums are used to configure \a WDTSEL bits of \a WDTCLKCR + * register. User can choose either fOFI or fPLL or fSTDBY clock as a source for WDT clock. + * Use type \a XMC_SCU_CLOCK_USBCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_WDTCLKSRC +{ + XMC_SCU_CLOCK_WDTCLKSRC_OFI = (0UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos), /**< Internal Fast Clock + (fOFI) as the source for WDT clock (fWDT). */ + XMC_SCU_CLOCK_WDTCLKSRC_STDBY = (1UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos), /**< Standby clock + (fSTDBY) as the source for WDT clock (fWDT). */ + XMC_SCU_CLOCK_WDTCLKSRC_PLL = (2UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos) /**< PLL output (fPLL) as the + source for WDT clock (fWDT). */ +} XMC_SCU_CLOCK_WDTCLKSRC_t; + +/** + * Defines options for selecting the source of external clock out (fEXT). These enums are used to configure \a ECKSEL bits of \a EXTCLKCR + * register. User can choose either fSYS or fPLL or fUSBPLL clock as a source for external clock out (fEXT). + * Use type \a XMC_SCU_CLOCK_EXTOUTCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_EXTOUTCLKSRC +{ + XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS = (0UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< System clock (fSYS) as + the source for external clock out (fEXT). */ + XMC_SCU_CLOCK_EXTOUTCLKSRC_USB = (2UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< USB PLL output(fUSB PLL) as the + source for external clock out (fEXT). */ + XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL = (3UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< Main PLL output(fPLL) as the + source for external clock out (fEXT). */ +#if ((UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY = (4UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< Standby clock(fSTDBY) as the + source for external clock out (fEXT). */ +#endif +} XMC_SCU_CLOCK_EXTOUTCLKSRC_t; + +/** + * Defines options for selecting the source of RTC Clock (fRTC). These enums are used to configure \a RCS bit of \a HDCR register. + * User can choose either fOSI or fULP clock as a source for RTC Clock (fRTC). + * Use type \a XMC_SCU_HIB_RTCCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_HIB_RTCCLKSRC +{ + XMC_SCU_HIB_RTCCLKSRC_OSI = (0UL << SCU_HIBERNATE_HDCR_RCS_Pos), /**< Internal Slow Clock + (fOSI) as the source for RTC Clock (fRTC). */ + XMC_SCU_HIB_RTCCLKSRC_ULP = (1UL << SCU_HIBERNATE_HDCR_RCS_Pos) /**< Ultra Low Power Clock (fULP) + as the source for RTC Clock (fRTC). */ +} XMC_SCU_HIB_RTCCLKSRC_t; + +/** + * Defines options for selecting the source of Standby Clock (fSTDBY). These enums are used to configure \a STDBYSEL bit of \a HDCR + * register. User can choose either fOSI or fULP clock as a source for Standby Clock (fSTDBY). + * Use type \a XMC_SCU_HIB_STDBYCLKSRC_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_HIB_STDBYCLKSRC +{ + XMC_SCU_HIB_STDBYCLKSRC_OSI = (0UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos), /**< Internal Slow Clock + (fOSI) as the source for Standby Clock + (fSTDBY). */ + XMC_SCU_HIB_STDBYCLKSRC_OSCULP = (1UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos) /**< Ultra Low Power Clock + (fULP) as the source for Standby Clock + (fSTDBY). */ +} XMC_SCU_HIB_STDBYCLKSRC_t; + +/** + * Defines options for backup clock trimming. These enums are used to configure \a AOTREN \a FOTR bits of \a + * PLLCON0 register. Use type \a XMC_SCU_CLOCK_BACKUP_TRIM_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE +{ + XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY = 0UL, /**< Factory Oscillator Calibration: + Force adjustment of the internal oscillator with the firmware defined values.*/ + XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC = 1UL /**< Automatic Oscillator Calibration adjustment of the fOFI clock with fSTDBY clock. */ +} XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t; + + +/** + * Defines options for selecting device boot mode. These enums are used to configure \a SWCON bits of \a STCON register. + * User can choose among various boot modes by configuring SWCON bits. + * Use type \a XMC_SCU_BOOTMODE_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_BOOTMODE +{ + XMC_SCU_BOOTMODE_NORMAL = (0UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from start of flash. */ + XMC_SCU_BOOTMODE_ASC_BSL = (1UL << SCU_GENERAL_STCON_SWCON_Pos), /**< UART bootstrap. */ + XMC_SCU_BOOTMODE_BMI = (2UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot Mode Index - Customized boot + sequence. */ + XMC_SCU_BOOTMODE_CAN_BSL = (3UL << SCU_GENERAL_STCON_SWCON_Pos), /**< CAN bootstrap. */ + XMC_SCU_BOOTMODE_PSRAM_BOOT = (4UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from PSRAM. */ + XMC_SCU_BOOTMODE_ABM0 = (8UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from flash - fixed alternative + address 0. */ + XMC_SCU_BOOTMODE_ABM1 = (12UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from flash - fixed alternative + address 1. */ + XMC_SCU_BOOTMODE_FABM = (14UL << SCU_GENERAL_STCON_SWCON_Pos), /**< fallback Alternate Boot Mode (ABM) - + Try ABM-0 then try ABM-1. */ +} XMC_SCU_BOOTMODE_t; + + +/** + * Defines various PLL modes of operation. These enums are used to configure \a VCOBYP bit of \a PLLCON0 register. + * User can choose either normal or prescalar mode by configuring VCOBYP bit. + * Use type \a XMC_SCU_PLL_MODE_t for accessing these enum parameters. + */ +typedef enum XMC_SCU_CLOCK_SYSPLL_MODE +{ + XMC_SCU_CLOCK_SYSPLL_MODE_DISABLED, /**< fPLL derived from fOSC and PLL operating in prescalar mode(i.e.VCO bypassed). */ + XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL, /**< fPLL derived from fVCO and PLL operating in normal mode. */ + XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR /**< fPLL derived from fOSC and PLL operating in prescalar mode(i.e.VCO bypassed). */ +} XMC_SCU_CLOCK_SYSPLL_MODE_t; + +/** + * Defines the source of the system clock and peripherals clock gating in SLEEP state. + * Use this enum as parameter of XMC_SCU_CLOCK_SetSleepConfig before going to SLEEP state. + * + * The SLEEP state of the system corresponds to the SLEEP state of the CPU. The state is + * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is + * stopped. Peripherals are only clocked when configured to stay enabled. + * + * Peripherals can continue to operate unaffected and eventually generate an event to + * wake-up the CPU. Any interrupt to the NVIC will bring the CPU back to operation. The + * clock tree upon exit from SLEEP state is restored to what it was before entry into SLEEP + * state. + * + */ +typedef enum XMC_SCU_CLOCK_SLEEP_MODE_CONFIG +{ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI = 0, /**< fOFI used as system clock source in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FPLL = SCU_CLK_SLEEPCR_SYSSEL_Msk, /**< fPLL used as system clock source in SLEEP state */ +#if defined(USB0) + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_USB = 0, /**< USB clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_USB = SCU_CLK_SLEEPCR_USBCR_Msk, /**< USB clock enabled in SLEEP state */ +#endif +#if defined(SDMMC) + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_SDMMC = 0,/**< SDMMC clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_SDMMC = SCU_CLK_SLEEPCR_MMCCR_Msk,/**< SDMMC clock enabled in SLEEP state */ +#endif +#if defined(ETH0) + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_ETH = 0, /**< ETH clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_ETH = SCU_CLK_SLEEPCR_ETH0CR_Msk, /**< ETH clock enabled in SLEEP state */ +#endif +#if defined(EBU) + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_EBU = 0, /**< EBU clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_EBU = SCU_CLK_SLEEPCR_EBUCR_Msk, /**< EBU clock enabled in SLEEP state */ +#endif + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_CCU = 0, /**< CCU clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_CCU = SCU_CLK_SLEEPCR_CCUCR_Msk, /**< CCU clock enabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_WDT = 0, /**< WDT clock disabled in SLEEP state */ + XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_WDT = SCU_CLK_SLEEPCR_WDTCR_Msk, /**< WDT clock enabled in SLEEP state */ +} XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_t; + +/** + * Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state. + * In addition the state of FLASH, PLL and PLLVCO during DEEPSLEEP state. + * Use this enum as parameter of XMC_SCU_CLOCK_SetDeepSleepConfig before going to DEEPSLEEP state. + * + * The DEEPSLEEP state of the system corresponds to the DEEPSLEEP state of the CPU. The state is + * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is + * stopped. + * + * In Deep Sleep state the OSC_HP and the PLL may be switched off. The wake-up logic in the NVIC is still clocked + * by a free-running clock. Peripherals are only clocked when configured to stay enabled. + * Configuration of peripherals and any SRAM content is preserved. + * The Flash module can be put into low-power mode to achieve a further power reduction. + * On wake-up Flash module will be restarted again before instructions or data access is possible. + * Any interrupt will bring the system back to operation via the NVIC.The clock setup before + * entering Deep Sleep state is restored upon wake-up. + */ +typedef enum XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG +{ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FOFI = 0, /**< fOFI used as system clock source in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FPLL = SCU_CLK_DSLEEPCR_SYSSEL_Msk, /**< fPLL used as system clock source in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_FLASH_POWERDOWN = SCU_CLK_DSLEEPCR_FPDN_Msk,/**< Flash power down in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN = SCU_CLK_DSLEEPCR_PLLPDN_Msk, /**< Switch off main PLL in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_VCO_POWERDOWN = SCU_CLK_DSLEEPCR_VCOPDN_Msk, /**< Switch off VCO of main PLL in DEEPSLEEP state */ +#if defined(USB0) + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_USB = 0, /**< USB clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_USB = SCU_CLK_DSLEEPCR_USBCR_Msk, /**< USB clock enabled in DEEPSLEEP state */ +#endif +#if defined(SDMMC) + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_SDMMC = 0,/**< SDMMC clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_SDMMC = SCU_CLK_DSLEEPCR_MMCCR_Msk,/**< SDMMC clock enabled in DEEPSLEEP state */ +#endif +#if defined(ETH0) + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_ETH = 0, /**< ETH clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_ETH = SCU_CLK_DSLEEPCR_ETH0CR_Msk, /**< ETH clock enabled in DEEPSLEEP state */ +#endif +#if defined(EBU) + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_EBU = 0, /**< EBU clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_EBU = SCU_CLK_DSLEEPCR_EBUCR_Msk, /**< EBU clock enabled in DEEPSLEEP state */ +#endif + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_CCU = 0, /**< CCU clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_CCU = SCU_CLK_DSLEEPCR_CCUCR_Msk, /**< CCU clock enabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_WDT = 0, /**< WDT clock disabled in DEEPSLEEP state */ + XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_WDT = SCU_CLK_DSLEEPCR_WDTCR_Msk, /**< WDT clock enabled in DEEPSLEEP state */ +} XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_t; + +/** + * Defines status of EVR13 regulator + */ +typedef enum XMC_SCU_POWER_EVR_STATUS +{ + XMC_SCU_POWER_EVR_STATUS_OK = 0, /**< EVR13 regulator No overvoltage condition */ + XMC_SCU_POWER_EVR_STATUS_EVR13_OVERVOLTAGE = SCU_POWER_EVRSTAT_OV13_Msk /**< EVR13 regulator is in overvoltage */ +} XMC_SCU_POWER_EVR_STATUS_t; + +/** + * Define status of external hibernate control + */ +typedef enum XMC_SCU_HIB_CTRL_STATUS +{ + XMC_SCU_HIB_CTRL_STATUS_NO_ACTIVE = 0, /**< Hibernate not driven active to pads */ + XMC_SCU_HIB_CTRL_STATUS_ACTIVE = SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk, /**< Hibernate driven active to pads */ +} XMC_SCU_HIB_CTRL_STATUS_t; + +/** + * Hibernate domain event status + */ +typedef enum XMC_SCU_HIB_EVENT +{ + XMC_SCU_HIB_EVENT_WAKEUP_ON_POS_EDGE = SCU_HIBERNATE_HDCR_WKPEP_Msk, /**< Wake-up on positive edge pin event */ + XMC_SCU_HIB_EVENT_WAKEUP_ON_NEG_EDGE = SCU_HIBERNATE_HDCR_WKPEN_Msk, /**< Wake-up on negative edge pin event */ + XMC_SCU_HIB_EVENT_WAKEUP_ON_RTC = SCU_HIBERNATE_HDCR_RTCE_Msk, /**< Wake-up on RTC event */ + XMC_SCU_HIB_EVENT_ULPWDG = SCU_HIBERNATE_HDCR_ULPWDGEN_Msk, /**< ULP watchdog alarm status */ +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE = SCU_HIBERNATE_HDSTAT_VBATPEV_Msk, /**< Wake-up on LPAC positive edge of VBAT threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */ + XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE = SCU_HIBERNATE_HDSTAT_VBATNEV_Msk, /**< Wake-up on LPAC negative edge of VBAT threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */ + XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Msk, /**< Wake-up on LPAC positive edge of HIB_IO_0 threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */ + XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Msk, /**< Wake-up on LPAC negative edge of HIB_IO_0 threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */ +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Msk, /**< Wake-up on LPAC positive edge of HIB_IO_1 threshold crossing. @note Only available in XMC44 series and LQFP100. */ + XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Msk, /**< Wake-up on LPAC negative edge of HIB_IO_1 threshold crossing. @note Only available in XMC44 series and LQFP100. */ +#endif +#endif +} XMC_SCU_HIB_EVENT_t; + +/** + * Hibernate domain dedicated pins + */ +typedef enum XMC_SCU_HIB_IO +{ + XMC_SCU_HIB_IO_0 = 0, /**< HIB_IO_0 pin. + At the first power-up and with every reset of the hibernate domain this pin is configured as opendrain output and drives "0". As output the medium driver mode is active. */ +#if (defined(DOXYGEN) || (UC_PACKAGE == BGA196) || (UC_PACKAGE == BGA144) || (UC_PACKAGE == LQFP144) || (UC_PACKAGE == LQFP100)) + XMC_SCU_HIB_IO_1 = 1 /**< HIB_IO_1 pin. + At the first power-up and with every reset of the hibernate domain this pin is configured as input with no pull device active. As output the medium driver mode is active. + @note : Only available in certain packages*/ +#endif +} XMC_SCU_HIB_IO_t; + +/** + * HIB_IOx pin I/O control + */ +typedef enum XMC_SCU_HIB_PIN_MODE +{ + XMC_SCU_HIB_PIN_MODE_INPUT_PULL_NONE = 0 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Direct input, no input pull device connected */ + XMC_SCU_HIB_PIN_MODE_INPUT_PULL_DOWN = 1 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Direct input, input pull down device connected */ + XMC_SCU_HIB_PIN_MODE_INPUT_PULL_UP = 2 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Direct input, input pull up device connected */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_HIBCTRL = 8 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Push-pull HIB control output */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_WDTSRV = 9 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Push-pull WDT service output */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_GPIO = 10 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Push-pull GPIO output */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_HIBCTRL = 12 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain HIB control output */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_WDTSRV = 13 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain WDT service output */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_GPIO = 14 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain GPIO output */ +} XMC_SCU_HIB_PIN_MODE_t; + +/** + * Selects the output polarity of the HIB_IOx + */ +typedef enum XMC_SCU_HIB_IO_OUTPUT_LEVEL +{ + XMC_SCU_HIB_IO_OUTPUT_LEVEL_LOW = 0 << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos, /**< Direct value */ + XMC_SCU_HIB_IO_OUTPUT_LEVEL_HIGH = 1 << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos /**< Inverted value */ +} XMC_SCU_HIB_IO_OUTPUT_LEVEL_t; + +/** + * Selects hibernate mode + */ +typedef enum XMC_SCU_HIB_HIBERNATE_MODE +{ + XMC_SCU_HIB_HIBERNATE_MODE_EXTERNAL = 0, /**< Request external hibernate mode */ +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + XMC_SCU_HIB_HIBERNATE_MODE_INTERNAL = 1, /**< Request internal hibernate mode. @note Only available in XMC44, XMC42 and XMC41 series */ +#endif +} XMC_SCU_HIB_HIBERNATE_MODE_t; + +/** + * Selects input signal HIB_SR0 of ERU0 + */ +typedef enum XMC_SCU_HIB_SR0_INPUT +{ + XMC_SCU_HIB_SR0_INPUT_HIB_IO_0 = SCU_HIBERNATE_HDCR_GPI0SEL_Msk, /**< Set HIB_SR0 to HIB_IO_0 digital input */ +#if (defined(DOXYGEN) || (UC_PACKAGE == BGA196) || (UC_PACKAGE == BGA144) || (UC_PACKAGE == LQFP144) || (UC_PACKAGE == LQFP100)) + XMC_SCU_HIB_SR0_INPUT_HIB_IO_1 = 0, /**< Set HIB_SR0 to HIB_IO_1 digital input. @note Only available in certain packages. */ +#endif +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + XMC_SCU_HIB_SR0_INPUT_ACMP0 = SCU_HIBERNATE_HDCR_ADIG0SEL_Msk, /**< Set HIB_SR0 to LPAC CMP0. @note Only available in XMC44, XMC42 and XMC41 series. */ +#endif +} XMC_SCU_HIB_SR0_INPUT_t; + +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + +#if ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)) +/** + * Selects input signal HIB_SR1 of ERU0. @note Only available in XMC44 in certain packages. + */ +typedef enum XMC_SCU_HIB_SR1_INPUT +{ + XMC_SCU_HIB_SR1_INPUT_HIB_IO_0 = SCU_HIBERNATE_HDCR_GPI1SEL_Msk, /**< Set HIB_SR1 to HIB_IO_0 digital input */ + XMC_SCU_HIB_SR1_INPUT_HIB_IO_1 = 0, /**< Set HIB_SR1 to HIB_IO_1 digital input. */ + XMC_SCU_HIB_SR1_INPUT_ACMP1 = SCU_HIBERNATE_HDCR_ADIG1SEL_Msk, /**< Set HIB_SR0 to LPAC CMP1. */ + XMC_SCU_HIB_SR1_INPUT_XTAL_GPI = SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk, /**< Set HIB_SR0 to RTC_XTAL_1 digital input */ +} XMC_SCU_HIB_SR1_INPUT_t; +#endif + +/** + * HIB LPAC input selection + */ +typedef enum XMC_SCU_HIB_LPAC_INPUT +{ + XMC_SCU_HIB_LPAC_INPUT_DISABLED = 0 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator permanently in power down */ + XMC_SCU_HIB_LPAC_INPUT_VBAT = 0x1 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for VBAT input */ + XMC_SCU_HIB_LPAC_INPUT_HIB_IO_0 = 0x2 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for HIB_IO_0 input */ +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + XMC_SCU_HIB_LPAC_INPUT_HIB_IO_1 = 0x4 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for HIB_IO_1 input. @note Only available in XMC44 series and LQFP100 package. */ +#endif +} XMC_SCU_HIB_LPAC_INPUT_t; + +/** + * HIB LPAC start trigger selection for selected inputs + */ +typedef enum XMC_SCU_HIB_LPAC_TRIGGER +{ + XMC_SCU_HIB_LPAC_TRIGGER_SUBSECOND_INTERVAL_COUNTER = 0 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< Sub-second interval counter */ + XMC_SCU_HIB_LPAC_TRIGGER_RTC_ALARM_EVENT = 0x1 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< RTC alarm event */ + XMC_SCU_HIB_LPAC_TRIGGER_RTC_PERIODIC_EVENT = 0x2 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< RTC periodic event */ + XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_POSITIVE_EDGE_EVENT = 0x3 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< On digital wakeup input positive edge event */ + XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_NEGATIVE_EDGE_EVENT = 0x5 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< On digital wakeup input negative edge event */ + XMC_SCU_HIB_LPAC_TRIGGER_CONTINOUS = 0x6 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< Continuous measurement */ + XMC_SCU_HIB_LPAC_TRIGGER_SINGLE_SHOT = 0x7 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< Single shot on software request */ +} XMC_SCU_HIB_LPAC_TRIGGER_t; + +/** + * HIB LPAC status + */ +typedef enum XMC_SCU_HIB_LPAC_STATUS +{ + XMC_SCU_HIB_LPAC_STATUS_VBAT_COMPARE_DONE = SCU_HIBERNATE_LPACST_VBATSCMP_Msk, /**< VBAT compare operation completed */ + XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_COMPARE_DONE = SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Msk, /**< HBI_IO_0 compare operation completed */ +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_COMPARE_DONE = SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Msk, /**< HBI_IO_1 compare operation completed. @note Only available in XMC44 series and LQFP100 package. */ +#endif + XMC_SCU_HIB_LPAC_STATUS_VBAT_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_VBATVAL_Msk, /**< VBAT comparison result above programmed threshold */ + XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_AHIBIO0VAL_Msk, /**< HBI_IO_0 comparison result above programmed threshold */ +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_AHIBIO1VAL_Msk, /**< HBI_IO_1 comparison result above programmed threshold. @note Only available in XMC44 series and LQFP100 package. */ +#endif +} XMC_SCU_HIB_LPAC_STATUS_t; + +#endif /* (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) */ + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/** + * Defines a data structure for initializing the PLL functional block. + * Structure holds divider values for N-DIV, P-DIV, K1-DIV, K2-DIV in order to generate desired + * frequency using VCO. It holds the PLL mode of operation either normal or prescaler (VCO bypassed). + * Use type \a XMC_SCU_CLOCK_PLL_CONFIG_t for accessing these structure parameters. + */ +typedef struct XMC_SCU_CLOCK_SYSPLL_CONFIG +{ + uint8_t n_div; /**< PLL N-Divider value. */ + uint8_t p_div; /**< PLL P-Divider value. */ + uint8_t k_div; /**< K1-Divider(Prescalar mode) or K2-Divider (Normal mode). */ + XMC_SCU_CLOCK_SYSPLL_MODE_t mode; /**< PLL mode of operation. */ + XMC_SCU_CLOCK_SYSPLLCLKSRC_t clksrc; /**< PLL divider input frequency. */ +} XMC_SCU_CLOCK_SYSPLL_CONFIG_t; + +/** + * Defines a data structure used for initializing the clock functional block. + * Clock functional block configures clock source needed for various peripheral and its divider values. + * Use type \a XMC_SCU_CLOCK_CONFIG_t for accessing these structure parameters. + */ +typedef struct XMC_SCU_CLOCK_CONFIG +{ + XMC_SCU_CLOCK_SYSPLL_CONFIG_t syspll_config; /**< PLL configuration */ + bool enable_oschp; /**< Enable external high precision oscillator. + Should be enabled when fOHP has to be source of system clock. */ + bool enable_osculp; /**< Enable external ultra low power oscillator. + Should be enabled when fULP has to be source of standby clock(fSTDBY). */ + XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t calibration_mode; /**< Backup clock trimming mode. */ + XMC_SCU_HIB_STDBYCLKSRC_t fstdby_clksrc; /**< Standby clock source. */ + XMC_SCU_CLOCK_SYSCLKSRC_t fsys_clksrc; /**< Choice of system clock. */ + uint8_t fsys_clkdiv; /**< Ratio of fPLL to fSYS. */ + uint8_t fcpu_clkdiv; /**< Ratio of fSys to fCPU. */ + uint8_t fccu_clkdiv; /**< Ratio of fSys to fCCU. */ + uint8_t fperipheral_clkdiv; /**< Ratio of fSYS to fPERI. */ +} const XMC_SCU_CLOCK_CONFIG_t; + +/** + * Low power modes + */ +typedef enum XMC_SCU_POWER_MODE_t +{ + XMC_SCU_POWER_MODE_SLEEP = 0, /**< sleep mode stops the processor clock */ + XMC_SCU_POWER_MODE_DEEPSLEEP = SCB_SCR_SLEEPDEEP_Msk /**< deep sleep mode stops the system clock and switches off the PLL and flash memory. */ +} XMC_SCU_POWER_MODE_t; + +/********************************************************************************************************************* + * API PROTOTYPES + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + * @param group ADC Group to which the channel being monitored belongs to.\n + * \b Range: 0 or 1. + * @param channel The channel whose voltage range has to be monitored.\n + * \b Range: 6 or 7. Value identifies the channel in the selected ADC group. + * + * @return None + * + * \parDescription
+ * Enables out of range comparator for the selected ADC group and channel. \n\n + * The ADC channel input is compared by Out of Range Comparator (ORC) for overvoltage monitoring + * or for detection of out of range analog inputs. ORC must be turned on explicitly + * to leverage the auditing feature. ORC is enabled by setting the enable bit in the GORCEN register. + * \parRelated APIs:
+ * XMC_SCU_DisableOutOfRangeComparator()\n\n\n + */ +void XMC_SCU_EnableOutOfRangeComparator(const uint32_t group, const uint32_t channel); + +/** + * + * @param group ADC Group to which the channel being monitored belongs to.\n + * \b Range: 0 or 1. + * @param channel The channel whose voltage range has to be monitored.\n + * \b Range: 6 or 7. Value identifies the channel in the selected ADC group. + * + * @return None + * + * \parDescription
+ * Disables the out of range comparator for the selected ADC group and the channel. \n\n + * Out of range comparator is disabled by clearing the enable bit in the GORCEN register. + * \parRelated APIs:
+ * XMC_SCU_EnableOutOfRangeComparator()\n\n\n + */ +void XMC_SCU_DisableOutOfRangeComparator(const uint32_t group, const uint32_t channel); + +/** + * @return None + * + * \parDescription
+ * Enables die temperature measurement by powering the DTS module.\n\n + * Die temperature sensor is enabled by setting the PWD bit of DTSCON register. + * \parRelated APIs:
+ * XMC_SCU_DisableTemperatureSensor(), XMC_SCU_IsTemperatureSensorEnabled(), XMC_SCU_CalibrateTemperatureSensor(), + * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +void XMC_SCU_EnableTemperatureSensor(void); + +/** + * @return None + * + * \parDescription
+ * Disables die temperature measurement by powering the DTS module off.\n\n + * Die temperature sensor is disabled by clearing the PWD bit of DTSCON register. + * \parRelated APIs:
+ * XMC_SCU_EnableTemperatureSensor(), XMC_SCU_IsTemperatureSensorEnabled(), XMC_SCU_CalibrateTemperatureSensor(), + * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +void XMC_SCU_DisableTemperatureSensor(void); + +/** + * @return Status of die temperature sensor. \n + * \b Range: true - if temperature sensor is enabled.\n + * false - if temperature sensor is disabled. + * + * \parDescription
+ * Provides the die temperature sensor power status.\n\n + * The status is obtained by reading the PWD bit of DTSCON register. + * \parRelated APIs:
+ * XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor(), + * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +bool XMC_SCU_IsTemperatureSensorEnabled(void); + +/** + * + * @param offset Offset value for calibrating the DTS result.\n + * \b Range: 0 to 127. + * @param gain Gain value for calibrating the DTS conversion result.\n + * \b Range: 0 to 63. + * + * @return None + * + * \parDescription
+ * Calibrates the measurement of temperature by configuring the values of offset and gain of \a DTSCON register. \n\n + * Allows to improve the accuracy of the temperature measurement with the adjustment of \a OFFSET and \a GAIN bit fields + * in the \a DTSCON register. + * Offset adjustment is defined as a shift of the conversion result. The range of the offset adjustment is 7 bits with a + * resolution that corresponds to +/- 12.5�C. The offset value gets added to the measure result. + * Offset is considered as a signed value. + * Gain adjustment helps in minimizing gain error. When the \a gain value is 0, result is generated with maximum gain. + * When the \a gain value is 63, result is generated with least gain, i.e, \a RESULT - 63 at the highest measured temperature.\n + * It is recommended to use following steps:\n + * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\n + * - Call \a XMC_SCU_CalibrateTempMonitor with desired offset and gain calibration values to the DTS.\n + * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.\n + * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n + * - Check whether Die Temperature Sensor (DTS) is busy in conversion by calling \a XMC_SCU_IsTemperatureSensorBusy() and wait till + * conversion complete.\n + * - Read the die temperature value using \a XMC_SCU_GetTemperatureMeasurement API. + * \parRelated APIs:
+ * XMC_SCU_EnableTemperatureSensor(), + * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +void XMC_SCU_CalibrateTemperatureSensor(uint32_t offset, uint32_t gain); + +/** + * @return XMC_SCU_STATUS_t Result of starting the temperature measurement.\n + * \b Range: \n + * XMC_SCU_STATUS_OK if the measurement is started successfully.\n + * XMC_SCU_STATUS_ERROR if temperature sensor is not enabled.\n + * XMC_SCU_STATUS_BUSY if temperature sensor is busy measuring the temperature.\n + * + * + * \parDescription
+ * Starts die temperature measurement using internal temperature sensor.\n\n + * The API checks if the temperature sensor is enabled and is not busy in measurement.\n + * It is recommended to use following steps:\n + * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\n + * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.\n + * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n + * - Check whether Die Temperature Sensor (DTS) is busy in conversion by calling \a XMC_SCU_IsTemperatureSensorBusy() and wait till + * conversion complete.\n + * - Read the die temperature value using \a XMC_SCU_GetTemperatureMeasurement API. + * \parRelated APIs:
+ * XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor(), + * XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +XMC_SCU_STATUS_t XMC_SCU_StartTemperatureMeasurement(void); + + +/** + * + * @return uint32_t Measured temperature value.\n + * \b Range: Valid temperature range is 0 to 1023. \n + * If sensor is not enabled, 0x7FFFFFFFH is returned. + * + * \parDescription
+ * Reads the measured value of die temperature.\n\n + * Temperature measurement result is read from \a RESULT bit field of \a DTSSTAT register. + * The temperature measured in �C is given by (RESULT - 605) / 2.05 [�C] + * \parRelated APIs:
+ * XMC_SCU_IsTemperatureSensorBusy() \n\n\n + */ +uint32_t XMC_SCU_GetTemperatureMeasurement(void); + +/** + * @return bool Indicates if the die temperature sensor is busy.\n + * \b Range: \a true if sensor is busy in temperature measurement. + * \a false if sensor is free and can accept a new request for measurement. + * + * \parDescription
+ * Checks whether Die Temperature Sensor (DTS) is busy in temperature measurement.\n\n + * The status is read from the \a BUSY bit field of the \a DTSSTAT register. + * \parRelated APIs:
+ * XMC_SCU_GetTemperatureMeasurement() \n\n\n + */ +bool XMC_SCU_IsTemperatureSensorBusy(void); + +/** + * @return bool Status of die temperature sensor whether it is ready to start measurement. \n + * \b Range: \n \a true if temperature sensor is ready to start measurement. \n + * \a false if temperature sensor is not ready to start measurement. + * + * \parDescription
+ * Checks if the die temperature sensor is ready to start a measurement\n\n + * The status is obtained by reading \a RDY bit of \a DTSSTAT register. It is recommended + * to check the ready status of die temperature sensor before starting it. + * \parRelated APIs:
+ * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_IsTemperatureSensorBusy() \n\n\n + */ +bool XMC_SCU_IsTemperatureSensorReady(void); + +#if (UC_SERIES != XMC45) +/** + * @return bool Indicates if the measured die temperature value has exceeded the configured upper limit.\n + * \b Range: \a true if the temperature value has exceeded the configured upper limit. \a false + * if the temperature value is less than the configured upper limit. + * + * \parDescription
+ * Checks if the measured temperature has exceeded the configured upper limit of temperature.\n\n + * The API checks \a OVERFL bit (Upper Limit Overflow Status bit) of \a DTEMPALARM register. + * The \a OVERFL bit will be set if the measured temperature has exceeded the limit configured in + * the bitfield \a UPPER in the \a DTEMPLIM register. + * \parRelated APIs:
+ * XMC_SCU_SetRawTempLimits(),XMC_SCU_LowTemperature() \n\n\n + */ +bool XMC_SCU_HighTemperature(void); + +/** + * + * @param lower_temp Lower threshold of die temperature. If measured temperature falls below this value, + * alarm bit will be set in \a UNDERFL bit field of \a DTEMPALARM register. + * @param upper_temp Upper threshold of die temperature. If measured temperature exceeds this value, + * alarm bit will be set in \a OVERFL bit field of \a DTEMPALARM register. + * + * @return None + * + * \parDescription
+ * Configures the lower and upper threshold of die temperature.\n\n + * API configures \a DTEMPLIM register for upper and lower die temperature threshold limits. + * When the measured temperature is outside the range defined by the limits, alarm bits \a UNDERFL or \a OVERFL + * will be set in the register \a DTEMPALARM.\n + * It is recommended to use following steps:\n + * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\n + * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values.\n + * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n + * - Use \a XMC_SCU_HighTemperature() and XMC_SCU_LowTemperature() to monitor the temperature.\n + * \parRelated APIs:
+ * XMC_SCU_HighTemperature(), XMC_SCU_LowTemperature() \n\n\n + */ +void XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp); + +/** + * @return bool Indicates if the measured die temperature value has dropped below the configured lower limit.\n + * \b Range: \a true if the temperature value has dropped below the configured lower limit. \a false + * if the temperature value is higher than the configured lower limit. + * + * \parDescription
+ * Checks if the measured temperature has dropped below the configured lower limit of temperature.\n\n + * The API checks \a UNDERFL bit (Lower LimitUnderflow Status bit) of \a DTEMPALARM register. + * The \a UNDERFL bit will be set if the measured temperature has dropped below the limit configured in + * the bitfield \a LOWER in the \a DTEMPLIM register. + * \parRelated APIs:
+ * XMC_SCU_SetRawTempLimits(),XMC_SCU_HighTemperature() \n\n\n + */ +bool XMC_SCU_LowTemperature(void); +#endif + +/** + * @return uint32_t Configured boot mode for the device.\n + * \b Range: Use type @ref XMC_SCU_BOOTMODE_t for enumeration of different boot modes. + * + * \parDescription
+ * Provides the boot mode configured for the device.\n\n + * The boot mode is read from the \a STCON register bit field \a SWCON. + * + * \parRelated APIs:
+ * XMC_SCU_SetBootMode() \n\n\n + */ +uint32_t XMC_SCU_GetBootMode(void); + +/** + * + * @param mode Boot mode to be configured for the device.\n + * \b Range: Use type @ref XMC_SCU_BOOTMODE_t for selecting the boot mode. + * + * @return None + * + * \parDescription
+ * Configures the desired boot mode for the device.\n\n + * The XMC4 series devices support multiple boot modes. A running application can set a desired bootmode and + * launch it by means of software reset. Switching of boot modes should be handled carefully. User should ensure that + * the initial boot sequence is executed. A stable execution environment should be maintained when program control is + * eventually handed over to the application program.\n + * It is recommended to use following steps to launch requested bootmode:\n + * - Call \a XMC_SCU_SetBootMode() with desired boot mode value.\n + * - Trigger a software reset using system reset request by enabling a bit \a SYSRESETREQ of AIRCR register + * (PPB->AIRCR |= PPB_AIRCR_SYSRESETREQ_Msk).\n + * \parRelated APIs:
+ * XMC_SCU_GetBootMode() \n\n\n + */ +void XMC_SCU_SetBootMode(const XMC_SCU_BOOTMODE_t mode); + +/** + * + * @param index The SCU general purpose register to be read.\n + * \b Range: 0 and 1 corresponding to GPR0 and GPR1. + * + * @return uint32_t Data read from the selected general purpose register. + * + * \parDescription
+ * Provides stored data from general purpose SCU register.\n\n + * SCU consists of 2 general purpose registers. These registers can be used for storing + * data. The API reads from either GPR0 or GPR1 based on the \a index value. + * \parRelated APIs:
+ * XMC_SCU_WriteGPR()\n\n\n + */ +uint32_t XMC_SCU_ReadGPR(const uint32_t index); + +/** + * + * @param index The SCU general purpose register to be written.\n + * \b Range: 0 and 1 corresponding to GPR0 and GPR1. + * @param data Data to be written to the selected general purpose register. + * + * @return None + * + * \parDescription
+ * Stores data in the selected general purpose SCU register.\n\n + * SCU consists of 2 general purpose registers. These registers can be used for storing + * data. The API writes data to either GPR0 or GPR1 based on the \a index value. + * \parRelated APIs:
+ * XMC_SCU_ReadGPR()\n\n\n + */ +void XMC_SCU_WriteGPR(const uint32_t index, const uint32_t data); + +/** + * + * @param address Location in the retention memory to be written.\n + * \b Range: 4 bit address space is provided for selecting 16 words of 32 bits. + * equivalent to 64 bytes of data. \a address value should be from + * 0 to 15. + * @param data 32 bit data to be written into retention memory. The API writes + * one word(4 bytes) of data to the address specified.\n + * \b Range: 32 bit data. + * + * @return None + * + * \parDescription
+ * Writes input data to the selected address of Retention memory in hibernate domain.\n\n + * The retention memory is located in hibernate domain. + * It is used for the purpose of store/restore of context information. + * Access to the retention memory space is served over shared serial interface. + * Retention memory content is retained even in hibernate mode. + * \parRelated APIs:
+ * XMC_SCU_ReadFromRetentionMemory() \n\n\n + */ +void XMC_SCU_WriteToRetentionMemory(uint32_t address, uint32_t data); + +/** + * + * @param address Location in the retention memory to be read.\n + * \b Range: 4 bit address space is provided for selecting 16 words of 32 bits. + * equivalent to 64 bytes of data. \a address value should be from + * 0 to 15. + * + * @return uint32_t 32 bit data read from retention memory. The API reads + * one word(4 bytes) of data from the address specified.\n + * \b Range: 32 bit data. + * + * \parDescription
+ * Reads data from selected address of retention memory in hibernate domain.\n\n + * The retention memory is located in hibernate domain. + * It is used for the purpose of store/restore of context information. + * Access to the retention memory space is served over shared serial interface. + * Retention memory content is retained even in hibernate mode. + * \parRelated APIs:
+ * XMC_SCU_WriteToRetentionMemory() \n\n\n + */ +uint32_t XMC_SCU_ReadFromRetentionMemory(uint32_t address); + +/** + * + * @param request Non-maskable interrupt (NMI) request source to be enabled.\n + * \b Range: Use type @ref XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple + * sources can be combined using \a OR operation. + * + * @return None + * + * \parDescription
+ * Selectively enables interrupt sources to generate non maskable interrupt(NMI).\n\n + * NMI assertion can be individually enabled by setting corresponding bit of an interrupt in the + * \a NMIREQEN register. + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_DisableNmiRequest() \n\n\n + */ +void XMC_SCU_INTERRUPT_EnableNmiRequest(const uint32_t request); + +/** + * + * @param request Non-maskable interrupt (NMI) request source to be disabled.\n + * \b Range: Use type @ref XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple + * sources can be combined using \a OR operation. + * + * @return None + * + * \parDescription
+ * Selectively disables interrupt sources from generating non maskable interrupt(NMI).\n\n + * NMI assertion can be individually disabled by clearing corresponding bits in the \a NMIREQEN register. + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_EnableNmiRequest() \n\n\n + */ +void XMC_SCU_INTERRUPT_DisableNmiRequest(const uint32_t request); + +/** + * + * @param trap The event for which, trap generation has to be enabled.\n + * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. + * + * @return None + * + * \parDescription
+ * Enables assertion of trap for the selected trap event.\n\n + * Trap assertion can be individually enabled by clearing respective bit of the + * event in \a TRAPDIS register in order to get an exception. + * \parRelated APIs:
+ * XMC_SCU_TRAP_Disable(), XMC_SCU_TRAP_ClearStatus(), XMC_SCU_TRAP_GetStatus() \n\n\n + */ +void XMC_SCU_TRAP_Enable(const uint32_t trap); + +/** + * + * @param trap The event for which, trap generation has to be disabled.\n + * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. + * + * @return None + * + * \parDescription
+ * Disables assertion of trap for the selected trap event.\n\n + * Trap assertion can be individually disabled by setting the respective event bit + * in the \a TRAPDIS register in order to suppress trap generation. + * \parRelated APIs:
+ * XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_ClearStatus(), XMC_SCU_TRAP_GetStatus() \n\n\n + */ +void XMC_SCU_TRAP_Disable(const uint32_t trap); + +/** + * + * @param trap The event for which, trap status bit has to be cleared.\n + * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. + * + * @return None + * + * \parDescription
+ * Clears the trap status of input event.\n\n + * Once a trap event is detected, it will have to be acknowledged and later serviced. + * The trap status bit should be cleared to detect the occurence of trap next time. + * This is useful while polling for TRAPSTAT without enabling the NMI for trap. + * Trap status can be cleared by setting the event bit in the \a TRAPCLR register. + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_GetStatus() \n\n\n + */ +void XMC_SCU_TRAP_ClearStatus(const uint32_t trap); + +/** + * @return uint32_t Status of trap generating events.\n + * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. The returned + * value indicates the status of multiple events at their respective bit positions. + * User should mask the bits of the events of interest using the type specified. + * + * \parDescription
+ * Provides the status of trap generating events. \n\n + * The status is read from \a TRAPRAW register. Status of the specific events can be checked + * using their respective bits in the \a TRAPRAW register. The bit masks can be obtained from + * the enumeration type @ref XMC_SCU_TRAP_t. Multiple events can be combined using \a OR operation. + * A trap event is considered to be asserted if the respective bit of the event is set to 1. + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_ClearStatus() \n\n\n + */ +uint32_t XMC_SCU_TRAP_GetStatus(void); + +/** + * + * @param trap The event for which, trap has to be triggered.\n + * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. + * + * @return None + * + * \parDescription
+ * Triggers trap generation for the event specified. \n\n + * The trap source has to be enabled before invocation of this API. + * Trap event can be triggered by setting its respective bit in the \a TRAPSET register. + * Trap event can be configured to generate a non maskable interrupt by using the API XMC_SCU_INTERRUPT_EnableNmiRequest().\n + * It is recommended to use following steps to manually assert a trap event:\n + * - Call \a XMC_SCU_TRAP_EnableEvent with desired trap request source ID.\n + * - Call \a XMC_SCU_TRAP_SetEvent with same trap request source ID to manually assert a trap event.\n + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_GetStatus() \n\n\n + */ +void XMC_SCU_TRAP_Trigger(const uint32_t trap); + +/** + * + * @param peripheral The peripheral to be reset.\n + * \b Range: Type @ref XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals that can be reset. + * + * @return None + * + * \parDescription
+ * Puts the specified peripheral in to reset state. \n\n + * The API achieves reset of peripherals by setting the respective bit in the \a PRSET0, \a PRSET1 or \a PRSET2 + * register. Status of reset assertion automatically stored in the \a PRSTATn register and can be checked by + * user software to determine the state of the system and for debug purpose.\n + * It is recommended to use following steps to assert a peripheral reset:\n + * - Call \a XMC_SCU_RESET_AssertPeripheralReset() with desired peripheral identifier.\n + * - Call \a XMC_SCU_RESET_IsPeripheralResetAsserted with same peripheral identifier to verify whether peripheral + * is in reset state.\n + * \parRelated APIs:
+ * XMC_SCU_RESET_IsPeripheralResetAsserted() \n\n\n + */ +void XMC_SCU_RESET_AssertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peripheral); + +/** + * + * @param peripheral The peripheral to be moved out of reset state.\n + * \b Range: Type @ref XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals that can be reset. + * + * @return None + * + * \parDescription
+ * Enables the specified peripheral by moving it out of reset state. \n\n + * Any peripheral should be moved out of reset state for executing its functionality. + * The API enables the peripheral by setting its respective bit in the \a PRCLR0, \a PRCLR1 or \a PRCLR2 + * register. Status of reset deassertion is automatically stored in the \a PRSTATn register and can be checked by + * the user software to determine the state of the system and for debug purpose.\n + * It is recommended to use following steps to deassert a peripheral reset:\n + * - Call \a XMC_SCU_RESET_DeassertPeripheralReset() with desired peripheral identifier.\n + * - Call \a XMC_SCU_RESET_IsPeripheralResetAsserted() with desired peripheral identifier to verify whether peripheral + * has been enabled.\n + * \parRelated APIs:
+ * XMC_SCU_RESET_AssertPeripheralReset() \n\n\n + */ +void XMC_SCU_RESET_DeassertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peripheral); + +/** + * + * @param peripheral The peripheral, whose reset status has to be checked.\n + * \b Range: Type @ref XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals. + * + * @return bool Status of peripheral reset. \n + * \b Range: \a true if peripheral is in reset state. \a false if peripheral is enabled and out of reset state. + * + * \parDescription
+ * Checks the reset status of the selected peripheral.\n\n + * The API reads the reset status from \a PRSTATn register. Returns true if the peripheral is in + * reset state. On power up of the device, all the peripherals will be in reset state. + * If the peripheral is enabled, \a false will be returned as the status. + * \parRelated APIs:
+ * XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset() \n\n\n + */ +bool XMC_SCU_RESET_IsPeripheralResetAsserted(const XMC_SCU_PERIPHERAL_RESET_t peripheral); + +/** + * + * @param memory The on-chip RAM type, for which the parity error status has to be cleared.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * memory status bits can be cleared by using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Clears the parity error status bit. \n\n + * When a memory parity error is detected using the status bits in \a PEFLAG register. It has to + * be cleared by software to detect the parity error from the same memory next time. + * The API clears the parity error status bit of the selected peripheral by setting the + * respective bit in the \a PEFLAG register. Status of multiple memory parity errors + * can be cleared by combining the enum values using \a OR operation. + * \parRelated APIs:
+ * XMC_SCU_PARITY_GetStatus(), XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_EnableTrapGeneration() \n\n\n + */ +void XMC_SCU_PARITY_ClearStatus(const uint32_t memory); + +/** + * + * @param memory The on-chip RAM type, for which the parity error checking has to be enabled.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * memory types can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Enables parity error checking for the selected on-chip RAM type.\n\n + * Parity error checking can be enabled by setting respective bits in the \a PEEN register. + * Additionally parity error can be configured to generate trap when the error is detected, + * using the API XMC_SCU_PARITY_EnableTrapGeneration(). Such a trap can be further configured + * to generate non maskable interrupt(NMI) using the API XMC_SCU_INTERRUPT_EnableNmiRequest(). + * \parRelated APIs:
+ * XMC_SCU_PARITY_EnableTrapGeneration(), XMC_SCU_INTERRUPT_EnableNmiRequest() \n\n\n + */ +void XMC_SCU_PARITY_Enable(const uint32_t memory); + +/** + * + * @param memory The on-chip RAM type, for which the parity error checking has to be disabled.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * memory types can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Disables parity error checking for the selected on-chip RAM type.\n\n + * Parity error detection can be disabled by clearing the respective bit in the \a PEEN register. + * \parRelated APIs:
+ * XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_DisableTrapGeneration() \n\n\n + */ +void XMC_SCU_PARITY_Disable(const uint32_t memory); + +/** + * + * @param memory The on-chip RAM type, for which the parity error trap generation has to be enabled.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * memory types can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Enables trap assertion for the parity error source.\n\n + * Parity error detection for different types of on-chip RAM can generate trap. + * Trap assertion for parity error can be individually enabled by setting the respective bits + * in the \a PETE register. The generated trap can be additionally configured to generate + * non maskable interrupt(NMI) using the API XMC_SCU_INTERRUPT_EnableNmiRequest(). + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_PARITY_DisableTrapGeneration() \n\n\n + */ +void XMC_SCU_PARITY_EnableTrapGeneration(const uint32_t memory); + +/** + * + * @param memory The on-chip RAM type, for which the parity error trap generation has to be disabled.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * memory types can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Disables the assertion of trap for the parity error source.\n\n + * Trap assertion can be disabled by clearing the respective bit of the RAM type in the \a PETE register. + * + * \parRelated APIs:
+ * XMC_SCU_PARITY_EnableTrapGeneration() \n\n\n + */ +void XMC_SCU_PARITY_DisableTrapGeneration(const uint32_t memory); + +/** + * + * @return uint32_t Status of parity error detection for the on-chip RAM modules.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to get the bit mask of each RAM module type. + * + * \parDescription
+ * Provides the status of parity error detection for the on-chip RAM modules.\n\n + * Parity error status information is obtained from the \a PEFLAG register. + * If a particular RAM module has parity error, its respective bit field will be set to 1 in the + * returned value. A check for the status of a particular RAM module can be done by + * masking the returned value with the RAM module identifier from the type @ref XMC_SCU_PARITY_t. + * \parRelated APIs:
+ * XMC_SCU_PARITY_ClearStatus() \n\n\n + */ +uint32_t XMC_SCU_PARITY_GetStatus(void); + +/** + * + * @param clock Peripheral for which the clock has to be enabled. \n + * \b Range: Use type @ref XMC_SCU_CLOCK_t to select the peripheral. + * + * @return None + * + * \parDescription
+ * Enables the source clock for selected peripheral.\n\n + * The various outputs of Clock Generation Unit (CGU) can be individually enabled by setting the peripheral + * specific bit in the \a CLKSET register.\n + * It is recommended to use following steps to verify whether a source clock of peripheral is enabled/disabled:\n + * - Call \a XMC_SCU_CLOCK_EnableClock() with desired peripheral identifier.\n + * - Call \a XMC_SCU_CLOCK_IsClockEnabled() with same peripheral identifier to verify whether the clock is enabled.\n + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableClock(), XMC_SCU_RESET_DeassertPeripheralReset() \n\n\n + */ +void XMC_SCU_CLOCK_EnableClock(const XMC_SCU_CLOCK_t clock); + +/** + * + * @param clock Peripheral for which the clock has to be disabled. \n + * \b Range: Use type @ref XMC_SCU_CLOCK_t to select the peripheral. + * + * @return None + * + * \parDescription
+ * Disables source clock for the peripheral selected.\n\n + * The various outputs of Clock Generation Unit (CGU) can be individually disabled by setting the peripheral + * specific bits in the \a CLKCLR register.\n + * It is recommended to use following steps to verify whether clock source of the peripheral is enabled/disabled:\n + * - Call \a XMC_SCU_CLOCK_DisableClock with desired peripheral identifier.\n + * - Call \a XMC_SCU_CLOCK_IsClockEnabled with same peripheral identifier to verify whether peripheral is enabled/disabled.\n + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableClock(), XMC_SCU_RESET_AssertPeripheralReset() \n\n\n + */ +void XMC_SCU_CLOCK_DisableClock(const XMC_SCU_CLOCK_t clock); + +/** + * + * @param clock Peripheral for which the clock status has to be checked. \n + * \b Range: Use type @ref XMC_SCU_CLOCK_t to select the peripheral. + * + * @return bool Status of peripheral clock.\n + * \b Range: \a true if peripheral clock is enabled. \a false if peripheral clock is disabled. + * + * \parDescription
+ * Checks the status of peripheral source clock.\n\n + * The status of peripheral source clock is read from the \a CLKSTATn register. + * Returns \a true if clock is enabled and returns \a false otherwise. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableClock(), XMC_SCU_CLOCK_DisableClock() \n\n\n + */ +bool XMC_SCU_CLOCK_IsClockEnabled(const XMC_SCU_CLOCK_t clock); + +/** + * + * @param source Source of clock for fSYS.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSCLKSRC_t to select the source of clock.\n + * XMC_SCU_CLOCK_SYSCLKSRC_OFI for selecting internal fast clock as fSYS.\n + * XMC_SCU_CLOCK_SYSCLKSRC_PLL for selecting the output of PLL fPLL as fSYS. + * + * @return None + * + * \parDescription
+ * Selects the source for system clock (fSYS).\n\n + * System clock is selected by setting \a SYSSEL bits in the \a SYSCLKCR register. + * If \a XMC_SCU_CLOCK_SYSCLKSRC_PLL is selected, then the dividers of the PLL have to be + * additionally configured to achieve the required system clock frequency. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StartSystemPll(), XMC_SCU_CLOCK_EnableHighPerformanceOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_SetSystemClockSource(const XMC_SCU_CLOCK_SYSCLKSRC_t source); + +/** + * @return XMC_SCU_CLOCK_SYSCLKSRC_t Source of clock for fSYS.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSCLKSRC_t to select the source of clock.\n + * XMC_SCU_CLOCK_SYSCLKSRC_OFI - internal fast clock selected as fSYS.\n + * XMC_SCU_CLOCK_SYSCLKSRC_PLL - output of PLL fPLL selected as fSYS. + * + * \parDescription
+ * Provides the selected source of system clock (fSYS). \n\n + * Selected source of fSYS is obtained by reading \a SYSSEL bits of \a SYSCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSystemClockSource(), XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency() \n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_SYSCLKSRC_t XMC_SCU_CLOCK_GetSystemClockSource(void) +{ + return (XMC_SCU_CLOCK_SYSCLKSRC_t)(SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk); +} + +/** + * + * @param source Source of clock for USB and SDMMC(fUSB/SDMMC).\n + * \b Range: Use type @ref XMC_SCU_CLOCK_USBCLKSRC_t to select the source of clock.\n + * XMC_SCU_CLOCK_USBCLKSRC_USBPLL - output of USB PLL as source of USB clock(fUSB/SDMMC).\n + * XMC_SCU_CLOCK_USBCLKSRC_SYSPLL - output of PLL fPLL as source of USB clock(fUSB/SDMMC). + * + * @return None + * + * \parDescription
+ * Selects the source of USB/SDMMC clock (fUSB/SDMMC).\n\n + * USB and SDMMC use a common clock source. They can either use fUSB PLL or fPLL as the source of clock. + * The selection is done by configuring the \a USBSEL bits of \a USBCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbPllClockFrequency() \n\n\n + */ +void XMC_SCU_CLOCK_SetUsbClockSource(const XMC_SCU_CLOCK_USBCLKSRC_t source); + +/** + * @return XMC_SCU_CLOCK_USBCLKSRC_t Source of clock for USB and SDMMC(fUSB/SDMMC).\n + * \b Range: Use type @ref XMC_SCU_CLOCK_USBCLKSRC_t to identify the source of clock.\n + * XMC_SCU_CLOCK_USBCLKSRC_USBPLL - output of USB PLL is selected as source of USB clock(fUSB/SDMMC).\n + * XMC_SCU_CLOCK_USBCLKSRC_SYSPLL - output of PLL fPLL is selected as source of USB clock(fUSB/SDMMC). + * + * \parDescription
+ * Provides the selected source of USB and SDMMC clock frequency.\n\n + * The clock source is read from from the \a USBSEL bits of \a USBCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbPllClockFrequency() \n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_USBCLKSRC_t XMC_SCU_CLOCK_GetUsbClockSource(void) +{ + return (XMC_SCU_CLOCK_USBCLKSRC_t)(SCU_CLK->USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk); +} + +/** + * + * @param source Clock source for watchdog timer.\n + * \b Range: Use type XMC_SCU_CLOCK_WDTCLKSRC_t to identify the clock source.\n + * XMC_SCU_CLOCK_WDTCLKSRC_OFI - internal fast oscillator (fOFI)\n + * XMC_SCU_CLOCK_WDTCLKSRC_STDBY - backup standby clock (fSTDBY)\n + * XMC_SCU_CLOCK_WDTCLKSRC_PLL - PLL output clock (fPLL) + * + * @return None + * + * \parDescription
+ * Selects the source of WDT clock (fWDT).\n\n + * The selected value is configured to the \a WDTSEL bits of \a WDTCLKCR register. + * The watchdog timer counts at the frequency selected using this API. So the time for + * timeout or pre-warning of watchdog has to be calculated based on this selection. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_GetWdtClockFrequency() \n\n\n + */ +void XMC_SCU_CLOCK_SetWdtClockSource(const XMC_SCU_CLOCK_WDTCLKSRC_t source); + +/** + * @return XMC_SCU_CLOCK_WDTCLKSRC_t Clock source configured for watchdog timer.\n + * \b Range: Use type XMC_SCU_CLOCK_WDTCLKSRC_t to identify the clock source.\n + * XMC_SCU_CLOCK_WDTCLKSRC_OFI - internal fast oscillator (fOFI)\n + * XMC_SCU_CLOCK_WDTCLKSRC_STDBY - backup standby clock (fSTDBY)\n + * XMC_SCU_CLOCK_WDTCLKSRC_PLL - PLL output clock (fPLL) + * + * \parDescription
+ * Provides the source of clock used for watchdog timer.\n\n + * The value is obtained by reading \a WDTSEL bits of \a WDTCLKCR register. + * The time for timeout or pre-warning of watchdog has to be calculated based on + * the clock source selected. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetWdtClockSource() \n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_WDTCLKSRC_t XMC_SCU_CLOCK_GetWdtClockSource(void) +{ + return (XMC_SCU_CLOCK_WDTCLKSRC_t)(SCU_CLK->WDTCLKCR & SCU_CLK_WDTCLKCR_WDTSEL_Msk); +} + +/** + * + * @param source Source for standby clock.\n + * \b Range: Use type @ref XMC_SCU_HIB_STDBYCLKSRC_t to identify the clock source.\n + * XMC_SCU_HIB_STDBYCLKSRC_OSI - internal slow oscillator (fOSI) \n + * XMC_SCU_HIB_STDBYCLKSRC_OSCULP - ultra low power osciallator (fULP) \n + * + * @return None + * + * \parDescription
+ * Selects the source of Standby clock (fSTDBY).\n\n + * Clock source is configured by setting the \a STDBYSEL bits of \a HDCR register. + * Hibernate domain should be enabled explicitly before using the API. + * \parRelated APIs:
+ * XMC_SCU_HIB_GetStdbyClockSource(), XMC_SCU_HIB_EnableHibernateDomain() \n\n\n + */ +void XMC_SCU_HIB_SetStandbyClockSource(const XMC_SCU_HIB_STDBYCLKSRC_t source); + +/** + * @return XMC_SCU_HIB_RTCCLKSRC_t Source clock of standby clock(fSTDBY).\n + * \b Range: Use type @ref XMC_SCU_HIB_STDBYCLKSRC_t to identify the clock source.\n + * XMC_SCU_HIB_STDBYCLKSRC_OSI - internal slow oscillator (fOSI) \n + * XMC_SCU_HIB_STDBYCLKSRC_OSCULP - ultra low power osciallator (fULP) \n + * + * \parDescription
+ * Provides the source of standby clock (fSTDBY).\n\n + * The value is obtained by reading \a STDBYSEL bits of \a HDCR register.\n + * \parRelated APIs:
+ * XMC_SCU_HIB_SetStandbyClockSource(), XMC_SCU_HIB_EnableHibernateDomain() \n\n\n + */ +__STATIC_INLINE XMC_SCU_HIB_RTCCLKSRC_t XMC_SCU_HIB_GetStdbyClockSource(void) +{ + return (XMC_SCU_HIB_RTCCLKSRC_t)(SCU_HIBERNATE->HDCR & SCU_HIBERNATE_HDCR_STDBYSEL_Msk); +} + +/** + * + * @param source Source of RTC clock.\n + * \b Range: Use type @ref XMC_SCU_HIB_RTCCLKSRC_t to identify the clock source.\n + * XMC_SCU_HIB_RTCCLKSRC_OSI - internal slow oscillator(fOSI). \n + * XMC_SCU_HIB_RTCCLKSRC_ULP - ultra low power oscillator(fULP). \n + * + * @return None + * + * \parDescription
+ * Selects the source of RTC clock (fRTC).\n\n + * The value is configured to \a RCS bit of \a HDCR register. + * fULP needs external input powered by VBAT or VDDP. fOSI is internal clock. + * The frequency of the clock will be 32.768 kHz. + * \parRelated APIs:
+ * XMC_SCU_HIB_GetRtcClockSource() \n\n\n + */ +void XMC_SCU_HIB_SetRtcClockSource(const XMC_SCU_HIB_RTCCLKSRC_t source); + +/** + * @return XMC_SCU_HIB_RTCCLKSRC_t Source of RTC clock.\n + * \b Range: Use type @ref XMC_SCU_HIB_RTCCLKSRC_t to identify the clock source.\n + * XMC_SCU_HIB_RTCCLKSRC_OSI - internal slow oscillator(fOSI). \n + * XMC_SCU_HIB_RTCCLKSRC_ULP - ultra low power oscillator(fULP). \n + * + * \parDescription
+ * Provides the source of RTC clock (fRTC). + * The value is obtained by reading \a RCS bit of \a HDCR register. + * The frequency of the clock will be 32.768 kHz. + * \parRelated APIs:
+ * XMC_SCU_HIB_SetRtcClockSource() \n\n\n + */ +__STATIC_INLINE XMC_SCU_HIB_RTCCLKSRC_t XMC_SCU_HIB_GetRtcClockSource(void) +{ + return (XMC_SCU_HIB_RTCCLKSRC_t)(SCU_HIBERNATE->HDCR & SCU_HIBERNATE_HDCR_RCS_Msk); +} + +/** + * + * @param clock Source of external clock output(fEXT).\n + * \b Range: Use type @ref XMC_SCU_CLOCK_EXTOUTCLKSRC_t to identify the clock.\n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS - system clock fSYS. \n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_USB - USB clock fUSB. \n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL - PLL output fPLL. \n + * \if XMC42 + * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n + * + * \endif + * \if XMC41 + * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n + * \endif + * + * @return None + * + * \parDescription
+ * Selects the source of external clock out (fEXT).\n\n + * The value will be configured to \a ECKSEL bits of \a EXTCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetExternalOutputClockSource(const XMC_SCU_CLOCK_EXTOUTCLKSRC_t clock); + +/** + * @return XMC_SCU_CLOCK_EXTOUTCLKSRC_t Source of external clock output(fEXT).\n + * \b Range: Use type @ref XMC_SCU_CLOCK_EXTOUTCLKSRC_t to identify the clock.\n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS - system clock fSYS. \n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_USB - USB clock fUSB. \n + * XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL - PLL output fPLL. \n + * \if XMC42 + * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n + * \endif + * \if XMC41 + * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n + * \endif + * + * \parDescription
+ * Provides the source of external clock output(fEXT).\n\n + * The value is obtained by reading \a ECKSEL bits of \a EXTCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider() \n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_EXTOUTCLKSRC_t XMC_SCU_CLOCK_GetExternalOutputClockSource(void) +{ + return (XMC_SCU_CLOCK_EXTOUTCLKSRC_t)(SCU_CLK->EXTCLKCR & SCU_CLK_EXTCLKCR_ECKSEL_Msk); +} + +/** + * + * @param source Source of clock for system PLL.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLLCLKSRC_t for identifying the clock source.\n + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP - External High performance oscillator(fOHP).\n + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI - Internal fast clock (fOFI). + * + * @return None + * + * \parDescription
+ * Selects the source of system PLL.\n\n + * The value is configured to \a VCOBYP bit of \a PLLCON0 register. + * If \a XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP is selected, ensure that the high performance oscillator is + * enabled by using the API XMC_SCU_CLOCK_EnableHighPerformanceOscillator(). + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillator()\n\n\n + */ +void XMC_SCU_CLOCK_SetSystemPllClockSource(const XMC_SCU_CLOCK_SYSPLLCLKSRC_t source); + +/** + * @return XMC_SCU_CLOCK_OSCCLKSRC_t Source of clock for system PLL.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLLCLKSRC_t for identifying the clock source.\n + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP - External High performance oscillator(fOHP).\n + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI - Internal fast clock (fOFI). + * + * \parDescription
+ * Provides the source of system PLL clock (fPLL). \n\n + * The value is obtained by reading \a VCOBYP bit of \a PLLCON0 register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_SetSystemPllClockSource()\n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_SYSPLLCLKSRC_t XMC_SCU_CLOCK_GetSystemPllClockSource(void) +{ + return (XMC_SCU_CLOCK_SYSPLLCLKSRC_t)(SCU_PLL->PLLCON0 & SCU_PLL_PLLCON0_VCOBYP_Msk); +} + +#if defined(ECAT0) +/** + * + * @param source Source of ECAT clock.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_ECATCLKSRC_t to identify the clock source.\n + * XMC_SCU_CLOCK_ECATCLKSRC_USBPLL - USB PLL (fUSBPLL) as a source for ECAT clock. \n + * XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL - Main PLL output (fPLL) as a source for ECAT clock. \n + * + * @return None + * + * \parDescription
+ * Selects the source of ECAT clock (fECAT).\n\n + * The value is configured to \a ECATSEL bit of \a ECATCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetECATClockSource() \n\n\n + */ +__STATIC_INLINE void XMC_SCU_CLOCK_SetECATClockSource(const XMC_SCU_CLOCK_ECATCLKSRC_t source) +{ + SCU_CLK->ECATCLKCR = (SCU_CLK->ECATCLKCR & ((uint32_t)~SCU_CLK_ECATCLKCR_ECATSEL_Msk)) | + ((uint32_t)source); +} + +/** + * @return XMC_SCU_CLOCK_ECATCLKSRC_t Source of ECAT clock.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_ECATCLKSRC_t to identify the clock source.\n + * XMC_SCU_CLOCK_ECATCLKSRC_USBPLL - USB PLL (fUSBPLL) as a source for ECAT clock. \n + * XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL - Main PLL output (fPLL) as a source for ECAT clock. \n + * + * \parDescription
+ * Provides the source of ECAT clock (fECAT). + * The value is obtained by reading \a ECATSEL bit of \a ECATCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_HIB_SetRtcClockSource() \n\n\n + */ +__STATIC_INLINE XMC_SCU_CLOCK_ECATCLKSRC_t XMC_SCU_CLOCK_GetECATClockSource(void) +{ + return (XMC_SCU_CLOCK_ECATCLKSRC_t)((SCU_CLK->ECATCLKCR & SCU_CLK_ECATCLKCR_ECATSEL_Msk) >> SCU_CLK_ECATCLKCR_ECATSEL_Pos); +} +#endif + +/** + * + * @param divider Ratio of fSYS clock source to the value of fSYS. + * \b Range: 1 to 256. + * + * @return None + * + * \parDescription
+ * Configures the ratio of system clock source to the value of system clock frequency.\n\n + * The value is configured as \a SYSDIV bits of \a SYSCLKCR register. The divider value is + * decremented by 1 before configuring. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemClockDivider(), XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n + */ +void XMC_SCU_CLOCK_SetSystemClockDivider(const uint32_t divider); + +/** + * @return uint32_t Ratio of fSYS clock source to the value of fSYS. + * \b Range: 0 to 255. + * + * \parDescription
+ * Provides the value of ratio between the source of system clock to the the value of system clock frequency. \n\n + * The value is obtained by reading \a SYSDIV bits of \a SYSCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSystemClockDivider(), XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetSystemClockDivider(void) +{ + return (uint32_t)((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) >> SCU_CLK_SYSCLKCR_SYSDIV_Pos); +} + +/** + * + * @param ratio Ratio of fCCU clock source to the value of fCCU. + * \b Range: 1 or 2.\n + * 1-> fCCU= fSYS \n + * 2-> fCCU= fSYS/2. + * + * @return None + * + * \parDescription
+ * Configures the divider for CCU clock source. \n\n + * Capture compare unit(CCU) can take either fSYS or fSYS/2 as the source of clock. + * The configuration is set to \a CCUDIV bit of \a CCUCLKCR register. The CCUDIV bit is 1 bit wide. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetCcuClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetCcuClockDivider(const uint32_t ratio); + +/** + * @return uint32_t Ratio of fCCU clock source to the value of fCCU. + * \b Range: 0 or 1.\n + * 0-> fCCU= fSYS \n + * 1-> fCCU= fSYS/2. + * + * \parDescription
+ * Provides the ratio of CCU clock(fCCU) to system clock(fSYS).\n\n + * The value is obtained by reading \a CCUDIV bit of \a CCUCLKCR register. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetCcuClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCcuClockDivider(void) +{ + return (uint32_t)((SCU_CLK->CCUCLKCR & SCU_CLK_CCUCLKCR_CCUDIV_Msk) >> SCU_CLK_CCUCLKCR_CCUDIV_Pos); +} + +/** + * + * @param ratio Ratio between system clock(fSYS) and CPU clock(fCPU). + * \b Range: 1 or 2.\n + * 1-> fCPU= fSYS. \n + * 2-> fCPU= fSYS/2. + * + * @return None + * + * \parDescription
+ * Configures the CPU clock by setting the divider value for the system clock. \n\n + * The value is set to the \a CPUDIV bit of \a CPUCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetCpuClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetCpuClockDivider(const uint32_t ratio); + +/** + * @return uint32_t Ratio between system clock(fSYS) and CPU clock(fCPU). + * \b Range: 0 or 1.\n + * 0-> fCPU= fSYS. \n + * 1-> fCPU= fSYS/2. + * + * \parDescription
+ * Provides the ratio between system clock(fSYS) and CPU clock(fCPU). \n\n + * The value is obtained by reading \a CPUDIV bit of \a CPUCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetCpuClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockDivider(void) +{ + return (uint32_t)((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) >> SCU_CLK_CPUCLKCR_CPUDIV_Pos); +} + +/** + * + * @param ratio Ratio of peripheral clock source to the value of peripheral clock.\n + * \b Range: 1 or 2.\n + * 1-> fPERIPH= fCPU.\n + * 2-> fPERIPH= fCPU/2. + * + * @return None + * + * \parDescription
+ * Configures the peripheral clock by setting the divider for CPU clock(fCPU).\n\n + * The peripheral clock can be equal to either fCPU or fCPU/2. The value is configured to \a PBDIV bit of \a PBCLKCR register. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetPeripheralClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetPeripheralClockDivider(const uint32_t ratio); + +/** + * @return uint32_t Ratio of peripheral clock source to the value of peripheral clock.\n + * \b Range: 0 or 1.\n + * 0-> fPERIPH= fCPU.\n + * 1-> fPERIPH= fCPU/2. + * + * \parDescription
+ * Provides the ratio of CPU clock(fCPU) to peripheral clock(fPERIPH).\n\n + * The value is obtained by reading \a PBDIV bit of \a PBCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetPeripheralClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetPeripheralClockDivider(void) +{ + return (uint32_t)((SCU_CLK->PBCLKCR & SCU_CLK_PBCLKCR_PBDIV_Msk) >> SCU_CLK_PBCLKCR_PBDIV_Pos); +} + +/** + * + * @param ratio Ratio of PLL output clock(fPLL) to USB clock(fUSB). + * \b Range: 1 to 8. + * + * @return None + * + * \parDescription
+ * Configures the USB clock(fUSB) by setting the USB clock divider. \n\n + * The value is decremented by 1 before setting it to \a USBDIV bits of \a USBCLKCR register. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetUsbClockDivider(), XMC_SCU_CLOCK_SetUsbClockSource() \n\n\n + */ +void XMC_SCU_CLOCK_SetUsbClockDivider(const uint32_t ratio); + +/** + * + * @return uint32_t Ratio of PLL output clock(fPLL) to USB clock(fUSB). + * \b Range: 0 to 7. + * + * \parDescription
+ * Provides the ratio between PLL output frequency(fPLL) and USB clock(fUSB).\n\n + * The value is obtained by reading \a USBDIV bit of \a USBCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbClockSource() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetUsbClockDivider(void) +{ + return (uint32_t)((SCU_CLK->USBCLKCR & SCU_CLK_USBCLKCR_USBDIV_Msk) >> SCU_CLK_USBCLKCR_USBDIV_Pos); +} + + + +#if defined(EBU) +/** + * + * @param ratio Ratio of PLL clock(fPLL) to EBU clock(fEBU).\n + * \b Range: 1 to 64. + * + * @return None + * + * \parDescription
+ * Configures the EBU clock(fEBU) by setting the divider value.\n\n + * The clock divider is configured to the \a EBUDIV bits of \a EBUCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetEbuClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetEbuClockDivider(const uint32_t ratio); + +/** + * + * @return uint32_t Ratio of PLL clock(fPLL) to EBU clock(fEBU).\n + * \b Range: 0 to 63. + * + * \parDescription
+ * Provides the ratio between PLL clock(fPLL) and EBU clock(fEBU).\n\n + * The value is obtained by reading \a EBUDIV bits of \a EBUCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetEbuClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetEbuClockDivider(void) +{ + return (uint32_t)((SCU_CLK->EBUCLKCR & SCU_CLK_EBUCLKCR_EBUDIV_Msk) >> SCU_CLK_EBUCLKCR_EBUDIV_Pos); +} +#endif + +/** + * + * @param ratio Ratio between the source of WDT clock and the WDT clock.\n + * \b Range: 1 to 256. + * + * @return None + * + * \parDescription
+ * Configures the WDT clock by setting the clock divider for the WDT clock source.\n\n + * The value is configured to \a WDTDIV bits of \a WDTCLKCR register. The value of divider + * is decremented by 1 before configuring. Check the selected clock source for the WDT clock + * before configuring the divider using the API XMC_SCU_CLOCK_SetWdtClockSource(). + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetWdtClockSource(), XMC_SCU_CLOCK_GetWdtClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetWdtClockDivider(const uint32_t ratio); + +/** + * + * @return uint32_t Ratio between the source of WDT clock and the WDT clock.\n + * \b Range: 0 to 255. + * + * \parDescription
+ * Provides the ratio between the WDT parent clock and the WDT clock. \n\n + * The value is obtained by reading \a WDTDIV bits of \a WDTCLKCR register. + * Ensure that the WDT parent clock is considered before using the value of + * the divider value. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetWdtClockSource(), XMC_SCU_CLOCK_SetWdtClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetWdtClockDivider(void) +{ + return (uint32_t)((SCU_CLK->WDTCLKCR & SCU_CLK_WDTCLKCR_WDTDIV_Msk) >> SCU_CLK_WDTCLKCR_WDTDIV_Pos); +} + +/** + * + * @param ratio Ratio between the external output parent clock selected and the output clock.\n + * \b Range: 1 to 512. + * + * @return None + * + * \parDescription
+ * Configures the external output clock by setting the divider value for the parent clock. \n\n + * The value will be configured to \a ECKDIV bits of \a EXTCLKCR register. + * The divider value is decremented by 1 before storing it to the bit fields. + * Ensure that the source of external output clock is configured appropriately using the API + * XMC_SCU_CLOCK_SetExternalOutputClockSource(). + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetExternalOutputClockSource(), XMC_SCU_CLOCK_GetExternalOutputClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetExternalOutputClockDivider(const uint32_t ratio); + +/** + * + * @return uint32_t Ratio between the external output parent clock selected and the output clock.\n + * \b Range: 0 to 511. + * + * \parDescription
+ * Provides the divider value applied on parent clock before the generation of external output clock. \n\n + * The value is obtained by reading \a EXTDIV bit of \a EXTCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetExternalOutputClockDivider(void) +{ + return (uint32_t)((SCU_CLK->EXTCLKCR & SCU_CLK_EXTCLKCR_ECKDIV_Msk) >> SCU_CLK_EXTCLKCR_ECKDIV_Pos); +} + +#if defined(ECAT0) +/** + * + * @param ratio Ratio between the source of ECAT clock and the ECAT clock.\n + * \b Range: 1 to 4. + * + * @return None + * + * \parDescription
+ * Configures the ECAT clock by setting the clock divider for the ECAT clock source.\n\n + * The value is configured to \a ECADIV bits of \a ECATCLKCR register. The value of divider + * is decremented by 1 before configuring. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetECATClockSource(), XMC_SCU_CLOCK_GetECATClockDivider() \n\n\n + */ +void XMC_SCU_CLOCK_SetECATClockDivider(const uint32_t divider); + +/** + * + * @return uint32_t Ratio between the source of ECAT clock and the ECAT clock.\n + * \b Range: 0 to 3. + * + * \parDescription
+ * Provides the ratio between the ECAT parent clock and the ECAT clock. \n\n + * The value is obtained by reading \a ECADIV bits of \a ECATCLKCR register. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetECATClockSource(), XMC_SCU_CLOCK_SetECATClockDivider() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetECATClockDivider(void) +{ + return (uint32_t)((SCU_CLK->ECATCLKCR & SCU_CLK_ECATCLKCR_ECADIV_Msk) >> SCU_CLK_ECATCLKCR_ECADIV_Pos); +} +#endif + +/** + * + * @return None + * + * \parDescription
+ * Enables the high precision oscillator by configuring external crystal mode.\n\n + * The API configures \a MODE bits of \a OSCHPCTRL register to 0, there by configuring the + * external clock input. + * The System Oscillator Watchdog is enabled. The user should check the status + * of the oscillator using XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableHighPerformanceOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_EnableHighPerformanceOscillator(void); + +/** + * @return None + * + * \parDescription
+ * Disables the high precision oscillator by disabling the external oscillator.\n\n + * The API configures \a MODE bits of \a OSCHPCTRL register to 1, there by disabling the + * external oscillator. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_DisableHighPerformanceOscillator(void); + +/** + * + * @return Status of high performance oscillator + * + * \parDescription
+ * Checks if the OSC_HP oscillator is stable and usable + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillator() \n\n\n + */ +bool XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable(void); + +/** + * + * @return None + * + * \parDescription
+ * Enables XTAL1 input of OSC_ULP as general purpose input. + * Use XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus to monitor the status of OSC_HP XTAL1 pin. + * @Note OSC_ULP should be disabled previously using XMC_SCU_CLOCK_DisableHighPerformanceOscillator(). + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableHighPerformanceOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(void); + +/** + * + * @return None + * + * \parDescription
+ * Disables XTAL1 input of OSC_ULP as general purpose input. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput() \n\n\n + */ +void XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(void); + +/** + * + * @return Status OSC_HP XTAL1 pin + * + * \parDescription
+ * Monitor the status of OSC_HP XTAL1 pin. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus(void); + +/** + * + * @return None + * + * \parDescription
+ * Enables ultra low power oscillator(ULP). \n\n + * It enables the hibernate domain, configures the ultra low power oscillator + * uisng the \a MODE bits of the \a OSCULCTRL register. The \a Mode bits will be + * reset to 0 to enable the low power oscillator. Mirror register update delays + * are handled internally. + * The OSC_ULP Oscillator Watchdog is enabled. The user should check the status + * of the oscillator using XMC_SCU_CLOCK_IsLowPowerOscillatorStable() + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableLowPowerOscillator() + * XMC_SCU_CLOCK_IsLowPowerOscillatorStable() \n\n\n + */ +void XMC_SCU_CLOCK_EnableLowPowerOscillator(void); + +/** + * + * @return None + * + * \parDescription
+ * Disables ultra low power oscillator.\n\n + * It is disabled by setting the \a MODE bits of \a OSCULCTRL register to value 2. + * By default on power up, the ultra low power osciallator is disabled. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableLowPowerOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_DisableLowPowerOscillator(void); + +/** + * + * @return Status of low power oscillator + * + * \parDescription
+ * Checks if the OSC_ULP oscillator is stable and usable + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableLowPowerOscillator() \n\n\n + */ +bool XMC_SCU_CLOCK_IsLowPowerOscillatorStable(void); + +/** + * + * @return None + * + * \parDescription
+ * Enables XTAL1 input of OSC_ULP as general purpose input. + * Use XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus to monitor the status of OSC_ULP XTAL1 pin. + * @Note OSC_ULP should be disabled previously using XMC_SCU_CLOCK_DisableLowPowerOscillator(). + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableLowPowerOscillator() \n\n\n + */ +void XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(void); + +/** + * + * @return None + * + * \parDescription
+ * Disables XTAL1 input of OSC_ULP as general purpose input. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput() \n\n\n + */ +void XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(void); + +/** + * + * @return Status OSC_ULP XTAL1 pin + * + * \parDescription
+ * Monitor the status of OSC_ULP XTAL1 pin. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus(void); + +/** + * + * @return uint32_t System frequency in Hertz.\n + * \b Range: clock frequency in Hertz. Range of the value depends on the source clock frequency + * and the configured values of dividers. + * + * \parDescription
+ * Provides the value of system PLL output clock frequency(fPLL).\n\n + * The API uses \a N-DIV, \a P-DIV, \a K1-DIV, \a K2-DIV bits information from \a PLLCON1 register and + * VCOBYP bit information from \a PLLCON0 register. It calculates frequency of system pll clock using following formula: + * If normal Mode : fPLL = (fOSC * N)/(P * K2). + * If prescaler mode: fPLL = fOSC/ K1. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetSystemPllClockFrequency(void); + +/** + * + * @return uint32_t Source clock used for deriving system clock.\n + * \b Range: fOHP frequency if external high precision frequency is used. \n + * fOFI fast internal clock frequency. + * + * \parDescription
+ * Provides the value of the input clock frequency for deriving the system clock. + * The API retrieves frequency of system PLL input clock (fPLLin). + * Based on \a PINSEL bits information from \a PLLCON2 register, the parent clock source is obtained. + * This bit field specifies if fOHP or fOFI is used for deriving system clock. + * System clock frequency is obtained by dividing the source clock frequency with different divider values. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemPllClockFrequency() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency(void); + +/** + * + * @return uint32_t USB PLL output clock frequency. + * + * \parDescription
+ * Provides the frequency of USB PLL output clock (fUSBPLL).\n\n + * It obtains the \a VCOBYP bits information from \a USBPLLCON register and decides if USB PLL mode is used. + * If USB PLL mode is used, the USB clock frequency is obtained by dividing the source clock by USB PLL dividers.\n + * The frequency is obtained using following formula:\n + * If Normal Mode : fUSBPLL = (fOSC * N)/(P * 2).\n + * If Prescaler mode: fPLL = fOSC. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetUsbPllClockFrequency(void); + +/** + * + * @return uint32_t System clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of system clock (fSYS).\n\n + * The value obtained by dividing \a CPUDIV bits information of \a CPUCLKCR register with SystemCoreClock (fCPU) value.\n + * Based on these values, fSYS clock frequency is derived using the following formula:\n + * fSYS = fCPU << CPUDIV. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetUsbPllClockFrequency() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetSystemClockFrequency(void) +{ + return SystemCoreClock << ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) >> SCU_CLK_CPUCLKCR_CPUDIV_Pos); +} + + +/** + * + * @return uint32_t CCU clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of clock(fCPU) used for CCU4, CCU8, POSIF and HRPWM.\n\n + * The value is obtained from \a CCUDIV bits of \a CCUCLKCR register and system clock (fSYS) frequency. + * Based on these values, fCCU clock frequency is calculated using following formula:\n + * fCCU = fSYS >> CCUDIV.\n + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetCcuClockDivider(), XMC_SCU_CLOCK_GetSystemClockFrequency() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetCcuClockFrequency(void); + +/** + * @return uint32_t USB clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of USB and SDMMC clock(fUSB/fSDMMC).\n\n + * The value is obtained from \a USBDIV bits of \a USBCLKCR register and USB clock source. + * Based on these values fUSB/fSDMMC clock frequency is calculated using following formula:\n + * if USB clock source = USBPLL: fUSB/fSDMMC = fUSBPLL/(USBDIV + 1).\n + * if USB clock source = PLL: fUSB/fSDMMC = fPLL/(USBDIV + 1).\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetUsbClockSource(), XMC_SCU_CLOCK_GetUsbClockDivider() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetUsbClockFrequency(void); + +/** + * @return uint32_t Ethernet clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of Ethernet clock(fETH).\n\n + * The value is derived from system clock frequency(fSYS). It is calculated using + * the following formula:\n + * fETH = fSYS >> 1; + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemClockFrequency() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetEthernetClockFrequency(void) +{ + return XMC_SCU_CLOCK_GetSystemClockFrequency() >> 1U; +} + +#if defined(EBU) +/** + * @return uint32_t EBU clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of EBU clock(fEBU).\n\n + * The value is derived from system PLL clock frequency(fPLL) by applying the EBU divider. + * It is calculated using the following formula:\n + * fETH = fPLL /(EBUDIV+1) + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetEbuClockDivider(), XMC_SCU_CLOCK_GetSystemPllClockFrequency() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetEbuClockFrequency(void); +#endif + +/** + * @return uint32_t WDT clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of WDT clock(fWDT).\n\n + * The value is derived using \a WDTDIV bits of \a WDTCLKCR register and WDT clock source. + * Based on these values it is calculated using the following formula:\n + * if WDT clock source = PLL: fWDT = fUSBPLL/(WDTDIV + 1).\n + * if WDT clock source = OFI: fWDT = fOFI/(WDTDIV + 1).\n + * if WDT clock source = Standby: fWDT = fSTDBY/(WDTDIV + 1).\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetWdtClockSource(), XMC_SCU_CLOCK_GetWdtClockDivider() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetWdtClockFrequency(void); + +/** + * + * @return uint32_t External clock out frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of external output clock(fEXT).\n\n + * The value is derived using \a ECKDIV bits of \a EXCLKCR register and external clock out source. + * Based on these values, it is calculated using the following formula:\n + * if external clock out source = System clock: fEXT = fSYS.\n + * if external clock out source = PLL: fEXT = fPLL/(ECKDIV + 1).\n + * if external clock out source = USBPLL: fEXT = fUSBPLL/(ECKDIV + 1).\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetExternalOutputClockDivider(), XMC_SCU_CLOCK_GetExternalOutputClockSource() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetExternalOutputClockFrequency(void); + +#if defined(ECAT) +/** + * @return uint32_t ECAT clock frequency in Hertz. + * + * \parDescription
+ * Provides the frequency of ECAT clock(fECAT).\n\n + * The value is derived using \a ECADIV bits of \a ECATCLKCR register and ECAT clock source. + * Based on these values it is calculated using the following formula:\n + * if ECAT clock source = PLL: fECAT = fPLL/(ECADIV + 1).\n + * if ECAT clock source = USBPLL: fECAT = fUSBPLL/(ECADIV + 1).\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetECATClockSource(), XMC_SCU_CLOCK_GetECATClockDivider() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetECATClockFrequency(void); +#endif + +/** + * @return None + * + * \parDescription
+ * Enables main PLL for system clock. \n\n + * System PLL is enabled by clearing the \a PLLPWD and \a VCOPWD bits of \a PLLCON0 register. + * By default the system PLL is in power saving mode. The API enables the PLL and the voltage + * controlled oscillator associated with it. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableSystemPll(), XMC_SCU_CLOCK_StartSystemPll() \n\n\n + */ +void XMC_SCU_CLOCK_EnableSystemPll(void); + + /** + * @return None + * + * \parDescription
+ * Disables main PLL for system clock. \n\n + * System PLL is disabled by setting the \a PLLPWD and \a VCOPWD bits of \a PLLCON0 register. + * By default the system PLL is in power saving mode. If the system PLL is explicitly enabled, + * the API disables the PLL and the voltage controlled oscillator(VCO) associated with it. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableSystemPll(), XMC_SCU_CLOCK_StopSystemPll() \n\n\n + */ + void XMC_SCU_CLOCK_DisableSystemPll(void); + +/** + * @param source PLL clock source. \n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLLCLKSRC_t to identify the clock source.\n + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP- External high precision oscillator input. + * XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI- Internal fast clock input. + * @param mode Mode of PLL operation.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLL_MODE_t to identify the PLL mode. \n + * XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL- PLL frequency obtained from output of VCO(fVCO).\n + * XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR- VCO is bypassed. Frequency obtained from fOSC.\n + * @param pdiv Input divider. Represents (PDIV+1) applied to external reference frequency. \n + * \b Range: 1 to 16.\n + * @param ndiv Feedback divider. Represents(NDIV+1) \n + * \b Range: 1 to 128. \n + * @param kdiv Output divider. Represents (K2DIV+1) in normal PLL mode or (K1DIV+1) in prescaler mode.\n + * \b Range: 1 to 128. \n + * @return None + * + * \parDescription
+ * Enables system PLL.\n\n + * Based on the selected source of clock, either external frequency fOHP or internal clock fOFI will be used. + * Based on the selected PLL mode, either voltage controlled oscillator(VCO) output(fVCO) or direct input frequency + * is used for the output dividers.\n + * The API implements the following sequence:\n + * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n + * - Clear all PLL related traps.\n + * - If external fOHP is selected as source, wait for the external oscillator to stabilize.\n + * - If PLL normal mode is selected, calculate the value of K2DIV and configure the PDIV, NDIV and K2DIV values.\n + * - Ramp up the PLL frequency in steps. \n + * - If prescaler mode is selected, configure the value of K1DIV.\n + * - Wait for LOCK.\n + * - Restore the trap configuration from stored temporary variable.\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemPllClockFrequency(), XMC_SCU_CLOCK_StopSystemPll() \n\n\n + */ +void XMC_SCU_CLOCK_StartSystemPll(XMC_SCU_CLOCK_SYSPLLCLKSRC_t source, + XMC_SCU_CLOCK_SYSPLL_MODE_t mode, + uint32_t pdiv, + uint32_t ndiv, + uint32_t kdiv); + +/** + * + * @return None + * + * \parDescription
+ * Disables the system PLL. + * PLL is placed in power saving mode. It disables the PLL by setting the \a PLLPWD bit of \a PLLCON0 register. + * If the PLL is put to power saving mode, it can no longer be used. + * It is recommended to ensure following steps before using \a XMC_SCU_CLOCK_StopSystemPll API:\n + * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n + * - Clear all PLL related traps.\n + * - Ramp down frequency until fPLL reaches backup clock frequency (fOFI).\n + * - Disable PLL.\n + * - Restore the trap configuration from stored temporary variable.\n + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetSystemPllClockFrequency(), XMC_SCU_CLOCK_StartSystemPll() \n\n\n + */ +void XMC_SCU_CLOCK_StopSystemPll(void); + +/** + * @param kdiv PLL output divider K2DIV. \n + * \b Range: 1 to 128. Represents (K2DIV+1). + * @return None + * + * \parDescription
+ * Ramps up or ramps down the PLL output frequency in provided step. \n\n + * The PLL output frequency is divided by the \a kdiv value. This generates a step of ramp + * for the PLL output frequency. The API waits for the clock to stabilize before the completing its + * execution. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StartSystemPll() \n\n\n + */ +void XMC_SCU_CLOCK_StepSystemPllFrequency(uint32_t kdiv); + +/** + * @param None + * @return Boolean value indicating if System PLL is locked + * + * \parDescription
+ * Return status of System PLL VCO. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StartSystemPll() \n\n\n + */ +bool XMC_SCU_CLOCK_IsSystemPllLocked(void); + +/** + * @return None + * + * \parDescription
+ * Enables USB PLL for USB clock. \n\n + * USB PLL is enabled by clearing the \a PLLPWD and \a VCOPWD bits of \a USBPLLCON register. + * By default the USB PLL is in power saving mode. The API enables the PLL and the voltage + * controlled oscillator associated with it. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_DisableUsbPll(), XMC_SCU_CLOCK_StartUsbPll() \n\n\n + */ + void XMC_SCU_CLOCK_EnableUsbPll(void); + + /** + * @return None + * + * \parDescription
+ * Disables USB PLL for USB clock. \n\n + * USB PLL is disabled by setting the \a PLLPWD and \a VCOPWD bits of \a USBPLLCON register. + * By default the USB PLL is in power saving mode. If the USB PLL is explicitly enabled, + * the API disables the PLL and the voltage controlled oscillator(VCO) associated with it. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_EnableUsbPll(), XMC_SCU_CLOCK_StopUsbPll() \n\n\n + */ +void XMC_SCU_CLOCK_DisableUsbPll(void); + +/** + * + * @param pdiv Input divider value. Represents (PDIV+1) divider for the USB PLL.\n + * \b Range: 1 to 16. + * @param ndiv VCO feedback divider for USB PLL. Represents (NDIV+1) feedback divider.\n + * \b Range: 1 to 128. + * + * @return None + * + * \parDescription
+ * Configures USB PLL dividers and enables the PLL.\n\n + * The API follows the required sequence for safely configuring the divider values of USB PLL. + * Checks for PLL stabilization before enabling the same. After the configuring the dividers, + * it waits till the VCO lock is achieved. + * The sequence followed is as follows:\n + * - Enable the USB PLL and configure VCO to be bypassed.\n + * - Set up the HP oscillator clock input.\n + * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n + * - Clear all USBPLL related traps.\n + * - Disconnect the oscillator from USB PLL and configure the dividers PDIV and NDIV. \n + * - Connect the oscillator to USB PLL and enable VCO.\n + * - Wait for LOCK.\n + * - Restore the trap configuration from stored temporary variable.\n + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StopUsbPll() \n\n\n + */ +void XMC_SCU_CLOCK_StartUsbPll(uint32_t pdiv, uint32_t ndiv); + +/** + * + * @return None + * + * \parDescription
+ * Disables USB PLL operation.\n\n + * USB PLL is disabled by placing the USB PLL in power saving mode. The VCO and USB PLL are put in power saving mode + * by setting the \a PLLPWD bit and \a VCOPWD bit of \a USBLLCON register to 1. VCO bypass mode is enabled by setting the + * \a VCOBYP bit of \a USBLLCON register to 1. + * It is recommended to ensure following steps before using \a XMC_SCU_CLOCK_StopUsbPll API:\n + * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n + * - Clear all USBPLL related traps.\n + * - Ramp down frequency.\n + * - Disable PLL.\n + * - Restore the trap configuration from stored temporary variable.\n + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StartUsbPll() \n\n\n + */ +void XMC_SCU_CLOCK_StopUsbPll(void); + +/** + * @param None + * @return Boolean value indicating if USB PLL is locked + * + * \parDescription
+ * Return status of USB PLL VCO. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_StartUsbPll() \n\n\n + */ +bool XMC_SCU_CLOCK_IsUsbPllLocked(void); + +/** + * @param mode Backup clock calibration mode.\n + * \b Range: Use type @ref XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t to identify the calibration mode.\n + * XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY- Force trimming of internal oscillator with firmware configured values.\n + * XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC- Calibrate internal oscillator automatically using standby clock(fSTDBY).\n + * + * @return None + * + * \parDescription
+ * Configures the calibration mode of internal oscillator.\n\n + * Based on the calibration mode selected, the internal oscillator calibration will be configured. + * The calibration is useful while using fast internal clock(fOFI). When factory mode calibration is used, + * the internal oscillator is trimmed using the firmware configured values. If automatic calibration is + * selected, the internal oscillator will be monitored using the backup clock. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n + */ +void XMC_SCU_CLOCK_SetBackupClockCalibrationMode(XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t mode); + +/** + * @param mode Low power mode\n + * @param sleep_on_exit Enter sleep, or deep sleep, on return from an ISR + * + * @return None + * + * \parDescription
+ * Enter selected low power mode and wait for interrupt + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSleepConfig(), XMC_SCU_CLOCK_SetDeepSleepConfig() \n\n\n + */ +__STATIC_INLINE void XMC_SCU_POWER_WaitForInterrupt(XMC_SCU_POWER_MODE_t mode, bool sleep_on_exit) +{ + SCB->SCR = mode | (sleep_on_exit ? SCB_SCR_SLEEPONEXIT_Msk : 0); + + __WFI(); +} + +/** + * @param mode Low power mode\n + * + * @return None + * + * \parDescription
+ * Enter selected low power mode and wait for event + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_SetSleepConfig(), XMC_SCU_CLOCK_SetDeepSleepConfig() \n\n\n + */ +__STATIC_INLINE void XMC_SCU_POWER_WaitForEvent(XMC_SCU_POWER_MODE_t mode) +{ + SCB->SCR = mode | SCB_SCR_SEVONPEND_Msk; + + __WFE(); +} + +/** + * @param threshold Threshold value for comparison to VDDP for brownout detection. LSB33V is 22.5mV + * @param interval Interval value for comparison to VDDP expressed in cycles of system clock + * @return None + * + * Enable power monitoring control register for brown-out detection. + * Brown Out Trap need to be enabled using XMC_SCU_TRAP_Enable() and event handling done in NMI_Handler. + * + * \parRelated APIs:
+ * XMC_SCU_TRAP_Enable() \n\n\n + * + */ +__STATIC_INLINE void XMC_SCU_POWER_EnableMonitor(uint8_t threshold, uint8_t interval) +{ + SCU_POWER->PWRMON = SCU_POWER_PWRMON_ENB_Msk | + ((uint32_t)threshold << SCU_POWER_PWRMON_THRS_Pos) | + ((uint32_t)interval << SCU_POWER_PWRMON_INTV_Pos); +} + +/** + * @return None + * + * Disable power monitoring control register for brown-out detection. + * + */ +__STATIC_INLINE void XMC_SCU_POWER_DisableMonitor(void) +{ + SCU_POWER->PWRMON &= ~SCU_POWER_PWRMON_ENB_Msk; +} + +/** + * @return ::XMC_SCU_POWER_EVR_STATUS_t + * + * \parDescription
+ * Returns status of the EVR13. + * + */ +__STATIC_INLINE int32_t XMC_SCU_POWER_GetEVRStatus(void) +{ + return SCU_POWER->EVRSTAT; +} + +/** + * @return EVR13 voltage in volts + * + * \parDescription
+ * Returns EVR13 voltage in volts. + * + */ +float XMC_SCU_POWER_GetEVR13Voltage(void); + +/** + * @return EVR33 voltage in volts + * + * \parDescription
+ * Returns EVR33 voltage in volts + * + */ +float XMC_SCU_POWER_GetEVR33Voltage(void); + +/** + * @return None + * + * \parDescription
+ * Enables the USB PHY and also OTG comparator if available.\n\n + * Configures the \a USBPHYPDQ bit of \a PWRSET register to move the USB PHY from power down state. + * If USB OTG is available in the device, the \a USBOTGEN bit of \a PWRSET register is set to 1. This + * enables the USB on the go comparators. + * + * \parRelated APIs:
+ * XMC_SCU_POWER_DisableUsb(), XMC_SCU_CLOCK_SetUsbClockSource() \n\n\n + */ +void XMC_SCU_POWER_EnableUsb(void); + +/** + * @return None + * + * \parDescription
+ * Disables the USB PHY and also OTG comparator if available.\n\n + * Configures the \a USBPHYPDQ bit of \a PWRSET register to move the USB PHY to power down state. + * If USB OTG is available in the device, the \a USBOTGEN bit of \a PWRSET register is set to 0. This + * disables the USB on the go comparators. + * + * \parRelated APIs:
+ * XMC_SCU_POWER_EnableUsb(), XMC_SCU_CLOCK_SetUsbClockSource() \n\n\n + */ +void XMC_SCU_POWER_DisableUsb(void); + +/** + * @return None + * + * \parDescription
+ * Powers up the hibernation domain.\n\n + * Hibernate domain should be enabled before using any peripheral from the hibernate domain. + * It enables the power to the hibernate domain and moves it out of reset state. + * Power to hibernate domain is enabled by setting the \a HIB bit of \a PWRSET register only if it is currently powered down. + * The API will wait until HIB domain is enabled. If hibernate domain is in a state of reset, + * \a HIBRS bit of \a RSTCLR register is set to move it out of reset state.\n + * It is recommended to use following steps to verify whether a hibernation domain is enabled/disabled:\n + * - Call \a XMC_SCU_HIB_EnableHibernateDomain . + * - Call \a XMC_SCU_HIB_IsHibernateDomainEnabled and check the return value. If return value is true, it indicates + * that the hibernation domain is enabled otherwise disabled.\n + * \parRelated APIs:
+ * XMC_SCU_HIB_DisableHibernateDomain(), XMC_SCU_HIB_IsHibernateDomainEnabled() \n\n\n + */ +void XMC_SCU_HIB_EnableHibernateDomain(void); + +/** + * + * @return None + * + * \parDescription
+ * Powers down the hibernation domain.\n\n + * After disabling the hibernate domain, none of the peripherals from the hibernte domain can be used. + * Hibernate domain is disabled by setting the \a HIB bit of \a PWRCLR register and \ HIBRS bit of \a RSTSET register.\n + * It is recommended to use following steps to verify whether a hibernation domain is enabled/disabled:\n + * - Call \a XMC_SCU_HIB_DisableHibernateDomain . + * - Call \a XMC_SCU_HIB_IsHibernateDomainEnabled and check return value. If return value is true, it indicates + * that the hibernation domain is enabled otherwise disabled.\n + * \parRelated APIs:
+ * XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_IsHibernateDomainEnabled() \n\n\n + */ +void XMC_SCU_HIB_DisableHibernateDomain(void); + +/** + * + * @return bool Power status of hibernate domain.\n + * \b Range: Boolean state value.\n + * \a true if hibernate domain is enabled.\n + * \a false if hibernate domain is disabled.\n + * + * + * \parDescription
+ * Checks whether hibernation domain is enabled/disabled.\n\n + * The API can be used before using the peripherals from hibernation domain to ensure that the + * power is supplied to the peripherals and also that the hibernation domain is not in reset state. + * The status is obtained using the \a HIBEN bit of \a PWRSTAT register and \a HIBRS bit of \a RSTSET register. + * \parRelated APIs:
+ * XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain() \n\n\n + */ +bool XMC_SCU_HIB_IsHibernateDomainEnabled(void); + +/** + * @return ::XMC_SCU_HIB_CTRL_STATUS_t + * + * \parDescription
+ * Returns status of the external hibernate control. + * + */ +__STATIC_INLINE int32_t XMC_SCU_HIB_GetHibernateControlStatus(void) +{ + return (SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk); +} + +/** + * @return ::XMC_SCU_HIB_EVENT_t + * + * \parDescription
+ * Returns status of hibernate wakeup events. + * + */ +__STATIC_INLINE int32_t XMC_SCU_HIB_GetEventStatus(void) +{ + return SCU_HIBERNATE->HDSTAT; +} + +/** + * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t + * @return None + * + * \parDescription
+ * Clear hibernate wakeup event status + * + */ +void XMC_SCU_HIB_ClearEventStatus(int32_t event); + +/** + * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t + * @return None + * + * \parDescription
+ * Trigger hibernate wakeup event + * + */ +void XMC_SCU_HIB_TriggerEvent(int32_t event); + +/** + * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t + * @return None + * + * \parDescription
+ * Enable hibernate wakeup event source + * + */ +void XMC_SCU_HIB_EnableEvent(int32_t event); + +/** + * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t + * @return None + * + * \parDescription
+ * Disable hibernate wakeup event source + * + */ +void XMC_SCU_HIB_DisableEvent(int32_t event); + +/** + * @return None + * + * \parDescription
+ * Request enter external hibernate state + * + */ +void XMC_SCU_HIB_EnterHibernateState(void); + +/** + * @param mode hibernate mode ::XMC_SCU_HIB_HIBERNATE_MODE_t + * @return None + * + * \parDescription
+ * Request enter external hibernate state + * + */ +void XMC_SCU_HIB_EnterHibernateStateEx(XMC_SCU_HIB_HIBERNATE_MODE_t mode); + +/** + * @return Detection of a wakeup from hibernate mode + * + * \parDescription
+ * Detection of a wakeup from hibernate mode + */ +__STATIC_INLINE bool XMC_SCU_HIB_IsWakeupEventDetected(void) +{ + return ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBWK_Msk) != 0U); +} + +/** + * @return None + * + * \parDescription
+ * Clear detection status of wakeup from hibernate mode + */ +__STATIC_INLINE void XMC_SCU_HIB_ClearWakeupEventDetectionStatus(void) +{ + SCU_RESET->RSTCLR = SCU_RESET_RSTCLR_HIBWK_Msk; +} + +/** + * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t + * @return None + * + * \parDescription
+ * Selects input for Wake-Up from Hibernate + * + */ +void XMC_SCU_HIB_SetWakeupTriggerInput(XMC_SCU_HIB_IO_t pin); + +/** + * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t + * @param mode Hibernate domain dedicated pin mode ::XMC_SCU_HIB_PIN_MODE_t + * @return None + * + * \parDescription
+ * Selects mode of hibernate domain dedicated pins HIB_IOx + * + */ +void XMC_SCU_HIB_SetPinMode(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_PIN_MODE_t mode); + +/** + * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t + * @param level Output polarity of the hibernate domain dedicated pins HIB_IOx ::XMC_SCU_HIB_IO_OUTPUT_LEVEL_t + * @return None + * + * \parDescription
+ * Selects the output polarity of the hibernate domain dedicated pins HIB_IOx + * + */ +void XMC_SCU_HIB_SetPinOutputLevel(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_IO_OUTPUT_LEVEL_t level); + +/** + * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t + * @return None + * + * \parDescription
+ * Selects input to ERU0 module (HIB_SR0) that optionally can be used with software as a general purpose input. + * + * \parRelated APIs:
+ * XMC_SCU_HIB_SetSR0Input() + * + */ +void XMC_SCU_HIB_SetInput0(XMC_SCU_HIB_IO_t pin); + +/** + * @param input input signal HIB_SR0 of ERU0 + * @return None + * + * \parDescription
+ * Selects input to ERU0 module (HIB_SR0). + * + * \parRelated APIs:
+ * XMC_SCU_HIB_SetInput0() + * + */ +void XMC_SCU_HIB_SetSR0Input(XMC_SCU_HIB_SR0_INPUT_t input); + +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + +#if ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)) +/** + * @param input input signal HIB_SR1 of ERU0 + * @return None + * + * \parDescription
+ * Configures HIB_SR1 input to ERU0 module. + * @note Only available in XMC44 series and LQFP100 package + * + */ +void XMC_SCU_HIB_SetSR1Input(XMC_SCU_HIB_SR1_INPUT_t input); +#endif + +/** + * @param input LPAC compare input. Values from ::XMC_SCU_HIB_LPAC_INPUT_t can be ORed. + * @return None + * + * \parDescription
+ * Selects inputs to the LPAC comparator. Several inputs can be selected (time multiplexing). + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_SetInput(XMC_SCU_HIB_LPAC_INPUT_t input); + +/** + * @param trigger LPAC compare trigger + * @return None + * + * \parDescription
+ * Selects trigger mechanism to start a comparison. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_SetTrigger(XMC_SCU_HIB_LPAC_TRIGGER_t trigger); + +/** + * @param enable_delay Enable conversion delay + * @param interval_count compare interval (interval_count + 16) * 1/32768 (s) + * @param settle_count settleing time of LPAC after powered up (triggered) before measurement start (settle_count + 1) * 1/32768 (s) + * @return None + * + * \parDescription
+ * Configures timing behavior of comparator. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_SetTiming(bool enable_delay, uint16_t interval_count, uint8_t settle_count); + +/** + * @param low VBAT low threshold + * @param high VBAT high threshold + * @return None + * + * \parDescription
+ * Select compare thresholds for VBAT. + * After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards. + * Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements + * until it has been crossed downwards and the threshold values gets swapped again. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_SetVBATThresholds(uint8_t lower, uint8_t upper); + +/** + * @param low HIB_IO_0 low threshold + * @param high HIB_IO_0 high threshold + * @return None + * + * \parDescription
+ * Select compare thresholds for HIB_IO_0. + * After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards. + * Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements + * until it has been crossed downwards and the threshold values gets swapped again. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_SetHIBIO0Thresholds(uint8_t lower, uint8_t upper); + +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)) +/** + * @param low HIB_IO_1 low threshold + * @param high HIB_IO_1 high threshold + * @return None + * + * \parDescription
+ * Select compare thresholds for HIB_IO_1. + * After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards. + * Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements + * until it has been crossed downwards and the threshold values gets swapped again. + * @note Only available in XMC44 series and LQFP100 package + * + */ +void XMC_SCU_HIB_LPAC_SetHIBIO1Thresholds(uint8_t lower, uint8_t upper); +#endif + +/** + * @return HIB LPAC status ::XMC_SCU_HIB_LPAC_STATUS_t + * + * \parDescription
+ * Return status of HIB LPAC. + * @note Only available in XMC44, XMC42 and XMC41 series and in certain packages + * + */ +int32_t XMC_SCU_HIB_LPAC_GetStatus(void); + +/** + * @param status HIB LPAC status. Values from ::XMC_SCU_HIB_LPAC_STATUS_t can be ORed. + * @return None + * + * \parDescription
+ * Clear status of HIB LPAC. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_ClearStatus(int32_t status); + +/** + * @param input LPAC compare input. Values from ::XMC_SCU_HIB_LPAC_INPUT_t can be ORed. + * @return None + * + * \parDescription
+ * Trigger comparasion on the selected inputs. + * @note Only available in XMC44, XMC42 and XMC41 series + * + */ +void XMC_SCU_HIB_LPAC_TriggerCompare(XMC_SCU_HIB_LPAC_INPUT_t input); + +#endif + +/** + * + * @return None + * + * \parDescription
+ * Enables slow internal oscillator(fOSI).\n\n + * By default on device power up, the slow internall oscillator is enabled. + * It can be disabled only if the external oscillator(fULP) is enabled and toggling. + * It is recommended to enable fOSI to prevent deadlock if fULP fails. + * fOSI is enabled by clearing the \a PWD bit of \a OSCSICTRL register. + * The API waits for the mirror register update of the configured register. + * The slow internal oscillator registers are in hibernate domain. + * Ensure that the hibernate domain is enabled before changing the configuration. + * \parRelated APIs:
+ * XMC_SCU_HIB_DisableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(), + * XMC_SCU_HIB_EnableHibernateDomain() \n\n\n + */ +void XMC_SCU_HIB_EnableInternalSlowClock(void); + +/** + * + * @return None + * + * \parDescription
+ * Disables slow internal oscillator(fOSI).\n\n + * By default on device power up, the slow internall oscillator is enabled. + * It can be disabled only if the external oscillator(fULP) is enabled and toggling. + * It is recommended to enable fOSI to prevent deadlock if fULP fails. + * fOSI is disabled by setting the \a PWD bit of \a OSCSICTRL register. + * The API waits for the mirror register update of the configured register. + * The slow internal oscillator registers are in hibernate domain. + * Ensure that the hibernate domain is enabled before changing the configuration. + * \parRelated APIs:
+ * XMC_SCU_HIB_EnableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(), + * XMC_SCU_HIB_EnableHibernateDomain() \n\n\n + */ +void XMC_SCU_HIB_DisableInternalSlowClock(void); + +/** + * @param config Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state. ::XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_t + * @return None + * + * \parDescription
+ * Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state. + * In addition the state of FLASH, PLL and PLLVCO during DEEPSLEEP state. + * Use this enum as parameter of XMC_SCU_CLOCK_SetDeepSleepConfig before going to DEEPSLEEP state. + * + * The DEEPSLEEP state of the system corresponds to the DEEPSLEEP state of the CPU. The state is + * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is + * stopped. + * + * In Deep Sleep state the OSC_HP and the PLL may be switched off. The wake-up logic in the NVIC is still clocked + * by a free-running clock. Peripherals are only clocked when configured to stay enabled. + * Configuration of peripherals and any SRAM content is preserved. + * The Flash module can be put into low-power mode to achieve a further power reduction. + * On wake-up Flash module will be restarted again before instructions or data access is possible. + * Any interrupt will bring the system back to operation via the NVIC.The clock setup before + * entering Deep Sleep state is restored upon wake-up. + * + * @usage + * @code + * // Configure system during SLEEP state + * XMC_SCU_CLOCK_SetDeepSleepConfig(XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI | + * XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_FLASH_POWERDOWN | + * XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN); + * + * // Make sure that SLEEPDEEP bit is set + * SCB->SCR |= SCB_SCR_DEEPSLEEP_Msk; + * + * // Return to SLEEP mode after handling the wakeup event + * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; + * + * // Put system in DEEPSLEEP state + * __WFI(); + * + * @endcode + * + *\parRelated APIs:
+ * XMC_SCU_CLOCK_Init() \n\n\n + * + */ +__STATIC_INLINE void XMC_SCU_CLOCK_SetDeepSleepConfig(int32_t config) +{ + SCU_CLK->DSLEEPCR = config; +} + +/** + * @param config Defines the source of the system clock and peripherals clock gating in SLEEP state. ::XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_t + * @return None + * + * \parDescription
+ * Defines the source of the system clock and peripherals clock gating in SLEEP state. + * + * The SLEEP state of the system corresponds to the SLEEP state of the CPU. The state is + * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is + * stopped. Peripherals are only clocked when configured to stay enabled. + * + * Peripherals can continue to operate unaffected and eventually generate an event to + * wake-up the CPU. Any interrupt to the NVIC will bring the CPU back to operation. The + * clock tree upon exit from SLEEP state is restored to what it was before entry into SLEEP + * state. + * + * @usage + * @code + * // Configure system during SLEEP state + * XMC_SCU_CLOCK_SetSleepConfig(XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI); + * + * // Make sure that SLEEPDEEP bit is cleared + * SCB->SCR &= ~ SCB_SCR_DEEPSLEEP_Msk; + * + * // Return to SLEEP mode after handling the wakeup event + * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; + * + * // Put system in SLEEP state + * __WFI(); + * + * @endcode + * + *\parRelated APIs:
+ * XMC_SCU_CLOCK_Init() \n\n\n + * + */ +__STATIC_INLINE void XMC_SCU_CLOCK_SetSleepConfig(int32_t config) +{ + SCU_CLK->SLEEPCR = config; +} + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* UC_FAMILY == XMC4 */ + +#endif /* XMC4_SCU_H */ + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_usic_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_usic_map.h new file mode 100644 index 00000000..93dc69be --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc4_usic_map.h @@ -0,0 +1,2021 @@ +/** + * @file xmc4_usic_map.h + * @date 2016-07-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial version + * + * 2015-08-25: + * - Added XMC4800 + * + * 2015-12-07: + * - Add XMC4300 support + * + * 2016-07-20: + * - Add missing USIC2_C1_DX0_P4_6,USIC1_C0_DX0_P1_14, USIC2_C0_DX0_P6_5, USIC2_C0_DX0_P9_4, USIC2_C1_DX1_P9_9, USIC2_C1_DX2_P9_8 for XMC47/48 BGA196 + * - Add missing USIC2_C1_DX0_P4_6, USIC1_C0_DX0_P1_14 for XMC47/48 LQFP100 + * - Add missing USIC2_C1_DX0_P4_6, USIC1_C0_DX0_P1_14, USIC2_C0_DX0_P6_5 for XMC47/48 LQFP144 + * + * @endcond + * + */ + +#ifndef XMC4_USIC_MAP_H +#define XMC4_USIC_MAP_H + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define USIC_INPUT_ALWAYS_1 7 + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX0_P8_8 4 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_P8_3 2 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_P8_1 2 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX0_P6_5 3 +#define USIC2_C0_DX0_P9_4 4 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_P9_1 2 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_P9_0 2 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX0_P4_6 4 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_P9_9 2 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_P9_8 2 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX0_P6_5 3 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX0_P4_6 4 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX0_P8_8 4 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_P8_3 2 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_P8_1 2 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX0_P6_5 3 +#define USIC2_C0_DX0_P9_4 4 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_P9_1 2 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_P9_0 2 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX0_P4_6 4 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_P9_9 2 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_P9_8 2 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define USIC0_C0_DX0_DOUT0 6 +#define USIC0_C0_DX0_P1_4 1 +#define USIC0_C0_DX0_P1_5 0 +#define USIC0_C0_DX0_P4_7 2 +#define USIC0_C0_DX0_P5_0 3 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 0 +#define USIC0_C0_DX1_SCLKOUT 6 +#define USIC0_C0_DX2_CCU40_SR1 4 +#define USIC0_C0_DX2_CCU80_SR1 5 +#define USIC0_C0_DX2_P0_7 1 +#define USIC0_C0_DX2_P1_0 0 +#define USIC0_C0_DX2_SELO0 6 +#define USIC0_C0_DX3_DOUT1 6 +#define USIC0_C0_DX4_DOUT2 6 +#define USIC0_C0_DX5_DOUT3 6 +#define USIC0_C1_DX0_DOUT0 6 +#define USIC0_C1_DX0_P2_2 0 +#define USIC0_C1_DX0_P2_5 1 +#define USIC0_C1_DX0_P3_13 3 +#define USIC0_C1_DX0_P4_0 4 +#define USIC0_C1_DX0_P6_3 2 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_P2_4 0 +#define USIC0_C1_DX1_P3_0 1 +#define USIC0_C1_DX1_P6_2 2 +#define USIC0_C1_DX1_SCLKOUT 6 +#define USIC0_C1_DX2_CCU42_SR1 4 +#define USIC0_C1_DX2_CCU80_SR1 5 +#define USIC0_C1_DX2_P2_3 0 +#define USIC0_C1_DX2_P3_1 1 +#define USIC0_C1_DX2_P6_1 2 +#define USIC0_C1_DX2_SELO0 6 +#define USIC0_C1_DX3_DOUT1 6 +#define USIC0_C1_DX4_DOUT2 6 +#define USIC0_C1_DX5_DOUT3 6 +#define USIC1_C0_DX0_DOUT0 6 +#define USIC1_C0_DX0_P0_4 0 +#define USIC1_C0_DX0_P0_5 1 +#define USIC1_C0_DX0_P1_14 4 +#define USIC1_C0_DX0_P2_14 3 +#define USIC1_C0_DX0_P2_15 2 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_P0_11 0 +#define USIC1_C0_DX1_P5_8 1 +#define USIC1_C0_DX1_SCLKOUT 6 +#define USIC1_C0_DX2_CCU41_SR1 4 +#define USIC1_C0_DX2_CCU81_SR1 5 +#define USIC1_C0_DX2_P0_6 0 +#define USIC1_C0_DX2_P5_9 1 +#define USIC1_C0_DX2_SELO0 6 +#define USIC1_C0_DX3_DOUT1 6 +#define USIC1_C0_DX4_DOUT2 6 +#define USIC1_C0_DX5_DOUT3 6 +#define USIC1_C1_DX0_DOUT0 6 +#define USIC1_C1_DX0_P0_0 3 +#define USIC1_C1_DX0_P3_14 1 +#define USIC1_C1_DX0_P3_15 0 +#define USIC1_C1_DX0_P4_2 2 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_P0_10 0 +#define USIC1_C1_DX1_P0_13 1 +#define USIC1_C1_DX1_P4_0 2 +#define USIC1_C1_DX1_SCLKOUT 6 +#define USIC1_C1_DX2_CCU43_SR1 4 +#define USIC1_C1_DX2_CCU81_SR1 5 +#define USIC1_C1_DX2_P0_12 1 +#define USIC1_C1_DX2_P0_9 0 +#define USIC1_C1_DX2_SELO0 6 +#define USIC1_C1_DX3_DOUT1 6 +#define USIC1_C1_DX4_DOUT2 6 +#define USIC1_C1_DX5_DOUT3 6 +#define USIC2_C0_DX0_DOUT0 6 +#define USIC2_C0_DX0_P3_7 2 +#define USIC2_C0_DX0_P5_0 1 +#define USIC2_C0_DX0_P5_1 0 +#define USIC2_C0_DX0_P6_5 3 +#define USIC2_C0_DX1_DX0INS 5 +#define USIC2_C0_DX1_P5_2 0 +#define USIC2_C0_DX1_SCLKOUT 6 +#define USIC2_C0_DX2_CCU41_SR1 4 +#define USIC2_C0_DX2_CCU81_SR1 5 +#define USIC2_C0_DX2_P5_3 0 +#define USIC2_C0_DX2_SELO0 6 +#define USIC2_C0_DX3_DOUT1 6 +#define USIC2_C0_DX4_DOUT2 6 +#define USIC2_C0_DX5_DOUT3 6 +#define USIC2_C1_DX0_DOUT0 6 +#define USIC2_C1_DX0_P3_12 3 +#define USIC2_C1_DX0_P3_4 1 +#define USIC2_C1_DX0_P3_5 0 +#define USIC2_C1_DX0_P4_0 2 +#define USIC2_C1_DX0_P4_6 4 +#define USIC2_C1_DX1_DX0INS 5 +#define USIC2_C1_DX1_P3_6 1 +#define USIC2_C1_DX1_P4_2 0 +#define USIC2_C1_DX1_SCLKOUT 6 +#define USIC2_C1_DX2_CCU43_SR1 4 +#define USIC2_C1_DX2_CCU81_SR1 5 +#define USIC2_C1_DX2_P4_1 0 +#define USIC2_C1_DX2_SELO0 6 +#define USIC2_C1_DX3_DOUT1 6 +#define USIC2_C1_DX4_DOUT2 6 +#define USIC2_C1_DX5_DOUT3 6 +#endif + +#endif /* XMC4_USIC_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_can.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_can.h new file mode 100644 index 00000000..7e6048fd --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_can.h @@ -0,0 +1,2198 @@ +/** + * @file xmc_can.h + * @date 2016-06-07 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Documentation improved
+ * + * 2015-05-20: + * - New elements have added in XMC_CAN_MO_t data structure
+ * - XMC_CAN_MO_Config() signature has changed
+ * - XMC_CAN_STATUS_t enum structure has updated.
+ * + * 2015-06-20: + * - New APIs added: XMC_CAN_NODE_ClearStatus(),XMC_CAN_MO_ReceiveData(), XMC_CAN_GATEWAY_InitDesObject().
+ * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-07-09: + * - New API added: XMC_CAN_NODE_Enable.
+ * + * 2015-09-01: + * - Removed fCANB clock support
+ * + * 2015-09-15: + * - Added "xmc_can_map.h" include
+ * + * 2016-06-07: + * - Added XMC_CAN_IsPanelControlReady() + * + * Details of use for node configuration related APIs
+ * Please use the XMC_CAN_NODE_SetInitBit() and XMC_CAN_NODE_EnableConfigurationChange() before calling node configuration + * related APIs. + * XMC_CAN_NODE_DisableConfigurationChange() and XMC_CAN_NODE_ResetInitBit() can be called for disable the configuration + * change and enable the node for communication afterwards. + * Do not use this when configuring the nominal bit time with XMC_CAN_NODE_NominalBitTimeConfigure(). In this case the + * Enable/Disable node configuration change is taken in account. + * + * Example Usage: + * @code + * //disabling the Node + * XMC_CAN_NODE_SetInitBit(CAN_NODE0) + * //allowing the configuration change + * XMC_CAN_NODE_EnableConfigurationChange(CAN_NODE0) + * //Node configuration + * XMC_CAN_NODE_FrameCounterConfigure(CAN_NODE0,&can_node_frame_counter); + * XMC_CAN_NODE_EnableLoopBack(CAN_NODE0) + * //disable configuration + * XMC_CAN_NODE_DisableConfigurationChange(CAN_NODE0) + * //Enabling node for communication + * XMC_CAN_NODE_ResetInitBit(CAN_NODE0) + * @endcode + * + * 2016-06-20: + * - Fixed bug in XMC_CAN_MO_Config()
+ * @endcond + * + */ + +#ifndef XMC_CAN_H +#define XMC_CAN_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_common.h" + +#if defined(CAN) + +#include "xmc_scu.h" +#include "xmc_can_map.h" +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup CAN + * @brief Controller Area Network Controller (CAN) driver for the XMC microcontroller family. + * + * CAN driver provides transfer of CAN frames in accordance with CAN specificetion V2.0 B (active). Each CAN node + * can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. + * All CAN nodes share a common set of message objects. Each message object can be individually allocated to one of the + * CAN nodes. + * Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build + * gateways between + * the CAN nodes or to setup a FIFO buffer. The CAN module provides Analyzer mode,Loop-back mode and bit timming for + * node analysis. + * + * The driver is divided into five sections: + * \par CAN Global features: + * -# Allows to configure module frequency using function XMC_CAN_Init(). + * -# Allows to configure Module interrupt using configuration structure XMC_CAN_NODE_INTERRUPT_TRIGGER_t and function + * XMC_CAN_EventTrigger(). + * + * \par CAN_NODE features: + * -# Allows to set baud rate by configuration structure XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t and Baudrate Configuration + * function XMC_CAN_NODE_NominalBitTimeConfigure(). + * -# Allows to configure loop-back mode using fuction XMC_CAN_NODE_EnableLoopBack(). + * -# Allows to configure CAN Node analyzer using function XMC_CAN_NODE_SetAnalyzerMode(). + * -# Allows CAN node events enable/ disable by enum structure XMC_CAN_NODE_EVENT_t and functions XMC_CAN_NODE_EnableEvent() + * and XMC_CAN_NODE_DisableEvent(). + * -# Provides bit timming analysis, configuration structure XMC_CAN_NODE_FRAME_COUNTER_t and function + * XMC_CAN_NODE_FrameCounterConfigure(). + * + * \par CAN_MO features: + * -# Allows message object initialization by configuration structure XMC_CAN_MO_t and function XMC_CAN_MO_Config(). + * -# Allows transfer of message objects using functions XMC_CAN_MO_Transmit() and XMC_CAN_MO_Receive(). + * -# Allows to configure Single Data Transfer and Single Transmit Trial using functions + * XMC_CAN_MO_EnableSingleTransmitTrial() and XMC_CAN_MO_EnableSingleTransmitTrial(). + * -# Allows to configure MO events using function XMC_CAN_MO_EnableEvent(). + * + * \par CAN_FIFO features: + * -# Allows message object FIFO structure by configuration structure XMC_CAN_FIFO_CONFIG_t and functions + * XMC_CAN_TXFIFO_ConfigMOBaseObject() , XMC_CAN_RXFIFO_ConfigMOBaseObject() and XMC_CAN_TXFIFO_Transmit(). + * + * \par CAN_GATEWAY features: + * -# Provides Gateway mode, configuration structure XMC_CAN_GATEWAY_CONFIG_t and function XMC_CAN_GATEWAY_InitSourceObject(). + * + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_CAN_MO_MOAR_STDID_Pos (18U) /**< Standard Identifier bitposition */ + +#define XMC_CAN_MO_MOAR_STDID_Msk ((0x000007FFUL) << XMC_CAN_MO_MOAR_STDID_Pos) /**< Standard Identifier bitMask */ + +#define CAN_NODE_NIPR_Msk (0x7UL) /**< Node event mask */ + +#define CAN_MO_MOIPR_Msk (0x7U) /**< Message Object event mask */ + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +/** + * Defines the status of CAN, to verify the CAN related API calls. Use type \a XMC_CAN_STATUS_t for this enum. +*/ +typedef enum XMC_CAN_STATUS +{ + XMC_CAN_STATUS_SUCCESS, /**< Driver accepted application request*/ + XMC_CAN_STATUS_ERROR, /**< Returned when unknown error occurred */ + XMC_CAN_STATUS_BUSY, /**< Driver is busy and can not handle request*/ + XMC_CAN_STATUS_MO_NOT_ACCEPTABLE, /**< Message object type not allowed*/ + XMC_CAN_STATUS_MO_DISABLED /**< Returned if Message object is disabled */ +} XMC_CAN_STATUS_t; + +/** +* Defines CAN module Panel Commands . Use type \a XMC_CAN_PANCMD_t for this enum. +*/ +typedef enum XMC_CAN_PANCMD +{ + XMC_CAN_PANCMD_INIT_LIST = 1U, /**< Command to initialize a list */ + XMC_CAN_PANCMD_STATIC_ALLOCATE = 2U, /**< Command to activate static allocation */ + XMC_CAN_PANCMD_DYNAMIC_ALLOCATE = 3U, /**< Command to activate dynamic allocation */ + + XMC_CAN_PANCMD_STATIC_INSERT_BEFORE = 4U, /**< Remove a message object from the list and insert it before a given object.*/ + XMC_CAN_PANCMD_DYNAMIC_INSERT_BEFORE = 5U, /**< Command to activate dynamic allocation */ + XMC_CAN_PANCMD_STATIC_INSERT_BEHIND = 6U, /**< Command to activate dynamic allocation */ + XMC_CAN_PANCMD_DYNAMIC_INSERT_BEHIND = 7U /**< Command to activate dynamic allocation */ +} XMC_CAN_PANCMD_t; + +/** +* Defines loop Back Mode, to enable/disable an in-system test of the MultiCAN module . +* Use type \a XMC_CAN_LOOKBACKMODE_t for this enum. +*/ +typedef enum XMC_CAN_LOOKBACKMODE +{ + XMC_CAN_LOOKBACKMODE_ENABLED, /**< Each CAN node can be connected to the internal CAN bus */ + XMC_CAN_LOOKBACKMODE_DISABLED /**< Each CAN node can be connected to the external CAN bus */ +} XMC_CAN_LOOKBACKMODE_t; + +/** + * Defines Message Object direction. Use type \a XMC_CAN_MO_TYPE_t for this enum. + */ +typedef enum XMC_CAN_MO_TYPE +{ + XMC_CAN_MO_TYPE_RECMSGOBJ, /**< Receive Message Object selected */ + XMC_CAN_MO_TYPE_TRANSMSGOBJ /**< Transmit Message Object selected */ +} XMC_CAN_MO_TYPE_t; + +/** + * Defines Data frame types. Use type \a XMC_CAN_FRAME_TYPE_t for this enum. + */ +typedef enum XMC_CAN_FRAME_TYPE +{ + XMC_CAN_FRAME_TYPE_STANDARD_11BITS, /**< Standard type identifier*/ + XMC_CAN_FRAME_TYPE_EXTENDED_29BITS /**< Extended type identifier*/ +} XMC_CAN_FRAME_TYPE_t; + + +/** + * Defines arbitration mode for transmit acceptance filtering. Use type \a XMC_CAN_ARBITRATION_MODE_t for this enum. + */ +typedef enum XMC_CAN_ARBITRATION_MODE +{ + XMC_CAN_ARBITRATION_MODE_ORDER_BASED_PRIO_1 = 1U, /**< Transmit acceptance based in the order(prio) */ + XMC_CAN_ARBITRATION_MODE_IDE_DIR_BASED_PRIO_2 = 2U, /**< Transmit acceptance filtering is based on the CAN identifier */ + XMC_CAN_ARBITRATION_MODE_ORDER_BASED_PRIO_3 = 3U /**< Transmit acceptance based in the order */ +} XMC_CAN_ARBITRATION_MODE_t; + +/** + * Defines the operation mode of the frame counter. Use type \a XMC_CAN_FRAME_COUNT_MODE_t for this enum. + */ +typedef enum XMC_CAN_FRAME_COUNT_MODE +{ + XMC_CAN_FRAME_COUNT_MODE = 0U, /**< Frame Count Mode */ + XMC_CAN_FRAME_COUNT_MODE_TIME_STAMP = 1U, /**< The frame counter is incremented with the beginning of a new bit time*/ + XMC_CAN_FRAME_COUNT_MODE_BIT_TIMING = 2U /**< Used for baud rate detection and analysis of the bit timing */ +} XMC_CAN_FRAME_COUNT_MODE_t; + +/** + * Defines the Divider Modes. Use type \a XMC_CAN_DM_t for this enum. + */ +typedef enum XMC_CAN_DM +{ + XMC_CAN_DM_NORMAL = 1U, /**< Normal divider mode */ + XMC_CAN_DM_FRACTIONAL = 2U, /**< Fractional divider mode */ + XMC_CAN_DM_OFF = 3U /**< Divider Mode in off-state*/ +} XMC_CAN_DM_t; + +/** + * Defines mask value for CAN Message Object set status. Use type \a XMC_CAN_MO_SET_STATUS_t for this enum. + */ +typedef enum XMC_CAN_MO_SET_STATUS +{ + XMC_CAN_MO_SET_STATUS_RX_PENDING = CAN_MO_MOCTR_SETRXPND_Msk, /**< Set receive pending */ + XMC_CAN_MO_SET_STATUS_TX_PENDING = CAN_MO_MOCTR_SETTXPND_Msk, /**< Set transmit pending */ + XMC_CAN_MO_SET_STATUS_RX_UPDATING = CAN_MO_MOCTR_SETRXUPD_Msk, /**< Set receive updating */ + XMC_CAN_MO_SET_STATUS_NEW_DATA = CAN_MO_MOCTR_SETNEWDAT_Msk, /**< Set new data */ + XMC_CAN_MO_SET_STATUS_MESSAGE_LOST = CAN_MO_MOCTR_SETMSGLST_Msk, /**< Set message lost */ + XMC_CAN_MO_SET_STATUS_MESSAGE_VALID = CAN_MO_MOCTR_SETMSGVAL_Msk, /**< Set message valid */ + XMC_CAN_MO_SET_STATUS_RX_TX_SELECTED = CAN_MO_MOCTR_SETRTSEL_Msk, /**< Set transmit/receive selected */ + XMC_CAN_MO_SET_STATUS_RX_ENABLE = CAN_MO_MOCTR_SETRXEN_Msk, /**< Set receive enable */ + XMC_CAN_MO_SET_STATUS_TX_REQUEST = CAN_MO_MOCTR_SETTXRQ_Msk, /**< Set transmit request */ + XMC_CAN_MO_SET_STATUS_TX_ENABLE0 = CAN_MO_MOCTR_SETTXEN0_Msk, /**< Set transmit enable 0 */ + XMC_CAN_MO_SET_STATUS_TX_ENABLE1 = CAN_MO_MOCTR_SETTXEN1_Msk, /**< Set transmit enable 1 */ + XMC_CAN_MO_SET_STATUS_MESSAGE_DIRECTION = CAN_MO_MOCTR_SETDIR_Msk /**< Set message direction */ +} XMC_CAN_MO_SET_STATUS_t; + +/** + * Defines mask value for CAN Message Object reset status. Use type \a XMC_CAN_MO_RESET_STATUS_t for this enum. + */ +typedef enum XMC_CAN_MO_RESET_STATUS +{ + XMC_CAN_MO_RESET_STATUS_RX_PENDING = CAN_MO_MOCTR_RESRXPND_Msk, /**< Reset receive pending */ + XMC_CAN_MO_RESET_STATUS_TX_PENDING = CAN_MO_MOCTR_RESTXPND_Msk, /**< Reset transmit pending */ + XMC_CAN_MO_RESET_STATUS_RX_UPDATING = CAN_MO_MOCTR_RESRXUPD_Msk, /**< Reset receive updating */ + XMC_CAN_MO_RESET_STATUS_NEW_DATA = CAN_MO_MOCTR_RESNEWDAT_Msk, /**< Reset new data */ + XMC_CAN_MO_RESET_STATUS_MESSAGE_LOST = CAN_MO_MOCTR_RESMSGLST_Msk, /**< Reset message lost */ + XMC_CAN_MO_RESET_STATUS_MESSAGE_VALID = CAN_MO_MOCTR_RESMSGVAL_Msk, /**< Reset message valid */ + XMC_CAN_MO_RESET_STATUS_RX_TX_SELECTED = CAN_MO_MOCTR_RESRTSEL_Msk, /**< Reset transmit/receive selected */ + XMC_CAN_MO_RESET_STATUS_RX_ENABLE = CAN_MO_MOCTR_RESRXEN_Msk, /**< Reset receive enable */ + XMC_CAN_MO_RESET_STATUS_TX_REQUEST = CAN_MO_MOCTR_RESTXRQ_Msk, /**< Reset transmit request */ + XMC_CAN_MO_RESET_STATUS_TX_ENABLE0 = CAN_MO_MOCTR_RESTXEN0_Msk, /**< Reset transmit enable 0 */ + XMC_CAN_MO_RESET_STATUS_TX_ENABLE1 = CAN_MO_MOCTR_RESTXEN1_Msk, /**< Reset transmit enable 1 */ + XMC_CAN_MO_RESET_STATUS_MESSAGE_DIRECTION = CAN_MO_MOCTR_RESDIR_Msk /**< Reset message direction */ +} XMC_CAN_MO_RESET_STATUS_t; + +/** + * Defines mask value for CAN Message Object status. Use type \a XMC_CAN_MO_STATUS_t for this enum. + */ +typedef enum XMC_CAN_MO_STATUS +{ + XMC_CAN_MO_STATUS_RX_PENDING = CAN_MO_MOSTAT_RXPND_Msk, /**< Defines message has been successfully received or not received */ + XMC_CAN_MO_STATUS_TX_PENDING = CAN_MO_MOSTAT_TXPND_Msk, /**< Defines message has been successfully transmitted or not transmitted */ + XMC_CAN_MO_STATUS_RX_UPDATING = CAN_MO_MOSTAT_RXUPD_Msk, /**< Defines Message identifier, DLC, and data of the message object are currently updated or not updated */ + XMC_CAN_MO_STATUS_NEW_DATA = CAN_MO_MOSTAT_NEWDAT_Msk, /**< Defines no update of the message object since last flag reset or Message object has been updated */ + XMC_CAN_MO_STATUS_MESSAGE_LOST = CAN_MO_MOSTAT_MSGLST_Msk, /**< CAN message is lost because NEWDAT has become set again when it has already been set or No CAN message is lost */ + XMC_CAN_MO_STATUS_MESSAGE_VALID = CAN_MO_MOSTAT_MSGVAL_Msk, /**< Message valid */ + XMC_CAN_MO_STATUS_RX_TX_SELECTED = CAN_MO_MOSTAT_RTSEL_Msk, /**< Transmit/Receive selected */ + XMC_CAN_MO_STATUS_RX_ENABLE = CAN_MO_MOSTAT_RXEN_Msk, /**< Receive enable */ + XMC_CAN_MO_STATUS_TX_REQUEST = CAN_MO_MOSTAT_TXRQ_Msk, /**< Transmit request */ + XMC_CAN_MO_STATUS_TX_ENABLE0 = CAN_MO_MOSTAT_TXEN0_Msk, /**< Transmit enable 0 */ + XMC_CAN_MO_STATUS_TX_ENABLE1 = CAN_MO_MOSTAT_TXEN1_Msk, /**< Transmit enable 1 */ + XMC_CAN_MO_STATUS_MESSAGE_DIRECTION = CAN_MO_MOSTAT_DIR_Msk, /**< Message direction */ + XMC_CAN_MO_STATUS_LIST = CAN_MO_MOSTAT_LIST_Msk, /**< List allocation */ + XMC_CAN_MO_STATUS_POINTER_TO_PREVIOUS_MO = CAN_MO_MOSTAT_PPREV_Msk, /**< Pointer to previous Message Object */ + XMC_CAN_MO_STATUS_POINTER_TO_NEXT_MO = (int32_t)CAN_MO_MOSTAT_PNEXT_Msk /**< Pointer to next Message Object */ +} XMC_CAN_MO_STATUS_t; + +/** + * Defines mask value for CAN Node status. Use type \a XMC_CAN_NODE_STATUS_t for this enum. + */ +typedef enum XMC_CAN_NODE_STATUS +{ + XMC_CAN_NODE_STATUS_LAST_ERROR_CODE = CAN_NODE_NSR_LEC_Msk, /**< Last Error Code */ + XMC_CAN_NODE_STATUS_TX_OK = CAN_NODE_NSR_TXOK_Msk, /**< Message transmitted successfully */ + XMC_CAN_NODE_STATUS_RX_OK = CAN_NODE_NSR_RXOK_Msk, /**< Message received successfully */ + XMC_CAN_NODE_STATUS_ALERT_WARNING = CAN_NODE_NSR_ALERT_Msk, /**< Alert warning */ + XMC_CAN_NODE_STATUS_ERROR_WARNING_STATUS = CAN_NODE_NSR_EWRN_Msk, /**< Error warning status */ + XMC_CAN_NODE_STATUS_BUS_OFF= CAN_NODE_NSR_BOFF_Msk, /**< Bus-off status */ + XMC_CAN_NODE_STATUS_LIST_LENGTH_ERROR = CAN_NODE_NSR_LLE_Msk, /**< List length error */ + XMC_CAN_NODE_STATUS_LIST_OBJECT_ERROR = CAN_NODE_NSR_LOE_Msk, /**< List object error */ +#if !defined(MULTICAN_PLUS) + XMC_CAN_NODE_STATUS_SUSPENDED_ACK = CAN_NODE_NSR_SUSACK_Msk /**< Suspend Acknowledge */ +#endif +} XMC_CAN_NODE_STATUS_t; + +/** + * Defines mask value for CAN Node control like initialization, node disable and analyzer mode . + * Use type \a XMC_CAN_NODE_CONTROL_t for this enum. + */ +typedef enum XMC_CAN_NODE_CONTROL +{ + XMC_CAN_NODE_CONTROL_NODE_INIT = CAN_NODE_NCR_INIT_Msk, /**< Node initialization */ + XMC_CAN_NODE_CONTROL_TX_INT_ENABLE = CAN_NODE_NCR_TRIE_Msk, /**< Transfer event enable */ + XMC_CAN_NODE_CONTROL_LEC_INT_ENABLE = CAN_NODE_NCR_LECIE_Msk, /**< LEC Indicated Error Event Enable */ + XMC_CAN_NODE_CONTROL_ALERT_INT_ENABLE = CAN_NODE_NCR_ALIE_Msk, /**< Alert Event Enable */ + XMC_CAN_NODE_CONTROL_CAN_DISABLE = CAN_NODE_NCR_CANDIS_Msk, /**< CAN disable */ + XMC_CAN_NODE_CONTROL_CONF_CHANGE_ENABLE= CAN_NODE_NCR_CCE_Msk, /**< Configuration change enable */ + XMC_CAN_NODE_CONTROL_CAN_ANALYZER_NODEDE = CAN_NODE_NCR_CALM_Msk, /**< CAN Analyzer mode */ +#if !defined(MULTICAN_PLUS) + XMC_CAN_NODE_CONTROL_SUSPENDED_ENABLE = CAN_NODE_NCR_SUSEN_Msk /**< Suspend Enable */ +#endif +} XMC_CAN_NODE_CONTROL_t; + +/** + * Defines mask value for CAN Node events. Use type \a XMC_CAN_NODE_EVENT_t for this enum. + */ +typedef enum XMC_CAN_NODE_EVENT +{ + XMC_CAN_NODE_EVENT_TX_INT = CAN_NODE_NCR_TRIE_Msk, /**< Node Transfer OK Event */ + XMC_CAN_NODE_EVENT_ALERT = CAN_NODE_NCR_ALIE_Msk, /**< Node Alert Event */ + XMC_CAN_NODE_EVENT_LEC = CAN_NODE_NCR_LECIE_Msk, /**< Last Error code Event */ + XMC_CAN_NODE_EVENT_CFCIE = CAN_NODE_NFCR_CFCIE_Msk /**< CAN Frame Count Event */ +} XMC_CAN_NODE_EVENT_t; + +/** + * Defines mask value for CAN node pointer events position. Use type \a XMC_CAN_NODE_POINTER_EVENT_t for this enum. + */ +typedef enum XMC_CAN_NODE_POINTER_EVENT +{ + XMC_CAN_NODE_POINTER_EVENT_ALERT = CAN_NODE_NIPR_ALINP_Pos, /**< Node Alert Event node pointer */ + XMC_CAN_NODE_POINTER_EVENT_LEC = CAN_NODE_NIPR_LECINP_Pos, /**< Last Error code Event node pointer */ + XMC_CAN_NODE_POINTER_EVENT_TRANSFER_OK = CAN_NODE_NIPR_TRINP_Pos, /**< Transmit Event node pointer */ + XMC_CAN_NODE_POINTER_EVENT_FRAME_COUNTER = CAN_NODE_NIPR_CFCINP_Pos /**< CAN Frame Count Event node pointer */ +} XMC_CAN_NODE_POINTER_EVENT_t; + +/** + * Defines CAN Message Object event node pointer position. Use type \a XMC_CAN_MO_POINTER_EVENT_t for this enum. + */ +typedef enum XMC_CAN_MO_POINTER_EVENT +{ + XMC_CAN_MO_POINTER_EVENT_TRANSMIT = CAN_MO_MOIPR_TXINP_Pos, /**< Transmit Event node pointer */ + XMC_CAN_MO_POINTER_EVENT_RECEIVE = CAN_MO_MOIPR_RXINP_Pos /**< Receive Event node pointer */ +} XMC_CAN_MO_POINTER_EVENT_t; + +/** + * Defines mask value for CAN Message Object event type. Use type \a XMC_CAN_MO_EVENT_t for this enum. + */ +typedef enum XMC_CAN_MO_EVENT +{ + XMC_CAN_MO_EVENT_TRANSMIT = CAN_MO_MOFCR_TXIE_Msk, /**< Message Object transmit event */ + XMC_CAN_MO_EVENT_RECEIVE = CAN_MO_MOFCR_RXIE_Msk, /**< Message Object receive event */ + XMC_CAN_MO_EVENT_OVERFLOW = CAN_MO_MOFCR_OVIE_Msk, /**< Message Object overflow event */ +} XMC_CAN_MO_EVENT_t; + +/** + * Defines the possible receive inputs. Use type \a XMC_CAN_NODE_RECEIVE_INPUT_t for this enum. + */ +typedef enum XMC_CAN_NODE_RECEIVE_INPUT +{ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCA, /**< CAN Receive Input A */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCB, /**< CAN Receive Input B */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCC, /**< CAN Receive Input C */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCD, /**< CAN Receive Input D */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCE, /**< CAN Receive Input E */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCF, /**< CAN Receive Input F */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCG, /**< CAN Receive Input G */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCH /**< CAN Receive Input H */ +} XMC_CAN_NODE_RECEIVE_INPUT_t; + +/** + * Defines last error transfer direction. Use type \a XMC_CAN_NODE_LAST_ERROR_DIR_t for this enum. + */ +typedef enum XMC_CAN_NODE_LAST_ERROR_DIR +{ + XMC_CAN_NODE_LAST_ERROR_DIR_WHILE_NODE_RECEPCION, /**< The last error occurred while the CAN node x was receiver */ + XMC_CAN_NODE_LAST_ERROR_DIR_WHILE_NODE_TRANSMISSION /**< The last error occurred while the CAN node x was transmitter */ +} XMC_CAN_NODE_LAST_ERROR_DIR_t; + + +/** + * Defines last error increment. Use type \a XMC_CAN_NODE_LAST_ERROR_INC_t for this enum. + */ +typedef enum XMC_CAN_NODE_LAST_ERROR_INC +{ + XMC_CAN_NODE_LAST_ERROR_INC_1, /**< The last error led to an error counter increment of 1. */ + XMC_CAN_NODE_LAST_ERROR_INC_8 /**< The last error led to an error counter increment of 8. */ +} XMC_CAN_NODE_LAST_ERROR_INC_t; + +/** + * Defines interrupt request on interrupt output line INT_O[n]. Use type \a XMC_CAN_NODE_INTERRUPT_TRIGGER_t for this enum. + */ +typedef enum XMC_CAN_NODE_INTERRUPT_TRIGGER +{ + XMC_CAN_NODE_INTR_TRIGGER_0 = 0x1U, + XMC_CAN_NODE_INTR_TRIGGER_1 = 0x2U, + XMC_CAN_NODE_INTR_TRIGGER_2 = 0x4U, + XMC_CAN_NODE_INTR_TRIGGER_3 = 0x8U, + XMC_CAN_NODE_INTR_TRIGGER_4 = 0x16U, + XMC_CAN_NODE_INTR_TRIGGER_5 = 0x32U, + XMC_CAN_NODE_INTR_TRIGGER_6 = 0x64U, + XMC_CAN_NODE_INTR_TRIGGER_7 = 0x128U, +} XMC_CAN_NODE_INTERRUPT_TRIGGER_t; + +#if defined(MULTICAN_PLUS) || defined(DOXYGEN) +/** + * Defines the Clock source used for the MCAN peripheral. @note Only available for XMC1400, XMC4800 and XMC4700 series + */ +typedef enum XMC_CAN_CANCLKSRC +{ +#if UC_FAMILY == XMC4 + XMC_CAN_CANCLKSRC_FPERI = 0x1U, + XMC_CAN_CANCLKSRC_FOHP = 0x2U, +#else + XMC_CAN_CANCLKSRC_MCLK = 0x1U, + XMC_CAN_CANCLKSRC_FOHP = 0x2U +#endif +} XMC_CAN_CANCLKSRC_t; +#endif + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ +/** + * Defines CAN node Nominal Bit Time. Use type \a XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t for this structure. +*/ +typedef struct XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG +{ + uint32_t can_frequency; /**< Frequency of the CAN module(fCAN). \a can_frequency shall be range of 5MHz to 120MHz */ + uint32_t baudrate; /**< Specifies the node baud rate. Unit: baud \a baudrate shall be range of 100Kbps to 1000Kbps*/ + uint16_t sample_point; /**< Sample point is used to compensate mismatch between transmitter and receiver clock phases detected in + the synchronization segment. Sample point. Range = [0, 10000] with respect [0%, 100%] of the total bit time.*/ + uint16_t sjw; /**< (Re) Synchronization Jump Width. Range:0-3 */ +} XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t; + +/** + * Defines base, top and bottom of CAN Message Object FIFO Structure. Use type \a XMC_CAN_FIFO_CONFIG_t for this structure. + * A FIFO consists of one base object and n slave objects. + */ +typedef struct XMC_CAN_FIFO_CONFIG +{ + uint8_t fifo_bottom; /**< points to the first element(slave object) in a FIFO structure.Range :0-63*/ + uint8_t fifo_top; /**< points to the last element(slave object) in a FIFO structure. Range :0-63*/ + uint8_t fifo_base; /**< points to the actual target object(Base object) within a FIFO/Gateway structure. Range :0-63*/ +} XMC_CAN_FIFO_CONFIG_t; + +/** + * Defines CAN Gateway FIFO structure and provides additional options for gateway destination object. + * Use type \a XMC_CAN_GATEWAY_CONFIG_t for this structure. + */ +typedef struct XMC_CAN_GATEWAY_CONFIG +{ + uint8_t gateway_bottom; /**< points to the first element(gateway destination object) in a FIFO structure. Range :0-63*/ + uint8_t gateway_top; /**< points to the last element(gateway destination object) in a FIFO structure. Range :0-63*/ + uint8_t gateway_base; /**< points to the actual target object within a FIFO/Gateway structure. Range :0-63*/ + bool gateway_data_frame_send; /**< TXRQ updated in the gateway destination object after the internal transfer from the gateway source + to the gateway destination object */ + bool gateway_identifier_copy; /**< The identifier of the gateway source object (after storing the received frame in the source) is copied + to the gateway destination object. */ + + bool gateway_data_length_code_copy; /**< Data length code of the gateway source object (after storing the received frame in the source) is copied to the + gateway destination object */ + bool gateway_data_copy; /**< Data fields in registers MODATALn and MODATAHn of the gateway source object (after storing the received frame in the source) + are copied to the gateway destination.*/ + +} XMC_CAN_GATEWAY_CONFIG_t; + +/** +* Defines CAN Global Initialization structure +*/ +typedef CAN_GLOBAL_TypeDef XMC_CAN_t; + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Defines frame counter configuration. Use type \a XMC_CAN_NODE_FRAME_COUNTER_t for this structure. + * It provides configuration of frame counter that counts transmitted/received CAN frames or obtains information about the time + * when a frame has been started to transmit or be received by the CAN node. +*/ +typedef struct XMC_CAN_NODE_FRAME_COUNTER +{ + + union{ + struct{ + uint32_t : 16; + uint32_t can_frame_count_selection:3; /**< Defines function of the frame counter */ + uint32_t can_frame_count_mode:2; /**< Determines the operation mode of the frame counter */ + uint32_t : 11; + }; + uint32_t nfcr; + + }; +} XMC_CAN_NODE_FRAME_COUNTER_t; + +/** + *Defines Node Runtime structure. +*/ +typedef CAN_NODE_TypeDef XMC_CAN_NODE_t; /**< pointer to the Node CAN register */ + +/** + * Defines CAN Message Object runtime elements. Use type \a XMC_CAN_MO_t for this structure. + */ +typedef struct XMC_CAN_MO +{ + CAN_MO_TypeDef *can_mo_ptr; /**< Pointer to the Message Object CAN register */ + union{ + struct{ + uint32_t can_identifier:29; /**< standard (11 bit)/Extended (29 bit) message identifier */ + uint32_t can_id_mode:1; /**< Standard/Extended identifier support */ + uint32_t can_priority:2; /**< Arbitration Mode/Priority */ + }; + uint32_t mo_ar; + }; + union{ + struct{ + uint32_t can_id_mask:29; /**< CAN Identifier of Message Object */ + uint32_t can_ide_mask:1; /**< Identifier Extension Bit of Message Object */ + }; + uint32_t mo_amr; + }; + uint8_t can_data_length; /**< Message data length, Range:0-8 */ + + union{ + + uint8_t can_data_byte[8]; /**< Each position of the array represents a data byte*/ + uint16_t can_data_word[4]; /**< Each position of the array represents a 16 bits data word*/ + uint32_t can_data[2]; /**< can_data[0] lower 4 bytes of the data. can_data[1], higher 4 bytes + of the data */ + uint64_t can_data_long; /** Data of the Message Object*/ + }; + + XMC_CAN_MO_TYPE_t can_mo_type; /**< Message Type */ + +} XMC_CAN_MO_t; +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @return None + * + * \parDescription:
+ * Disables CAN module. In disabled state, no registers of CAN module can be read or written except the CAN_CLC register. + * + * \parRelated APIs:
+ * XMC_CAN_Enable()\n\n\n + * + */ + +void XMC_CAN_Disable(XMC_CAN_t *const obj); + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @return None + * + * \parDescription:
+ * Enables CAN module and initializes all CAN registers to reset values. It is required to re-configure desired CAN nodes, + * before any data transfer. It configures CAN_CLC.DISR bit. + * + * \parRelated APIs:
+ * XMC_CAN_Disable()\n\n\n + * + */ + +void XMC_CAN_Enable(XMC_CAN_t *const obj); + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @param node_num CAN node number,Range : 0-2 + * @param mo_num CAN Message Object number,Range : 0-63 + * + * @return None + * + * \parDescription:
+ * Allocates Message Object from free list to node list. Each \a node_num is linked to one unique list of message objects. + * A CAN node performs message transfer only with the \a mo_num message objects that are allocated to the list of the CAN node. + * It configures PANCTR register. + * + * \parRelated APIs:
+ * None + * + */ + +void XMC_CAN_AllocateMOtoNodeList(XMC_CAN_t *const obj, const uint8_t node_num, const uint8_t mo_num); + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @return Ready status of list controller + * + * \parDescription:
+ * Returns ready status of the list controller + * + * \parRelated APIs:
+ * XMC_CAN_PanelControl() + * + */ +__STATIC_INLINE bool XMC_CAN_IsPanelControlReady(XMC_CAN_t *const obj) +{ + return (bool)((obj->PANCTR & (CAN_PANCTR_BUSY_Msk | CAN_PANCTR_RBUSY_Msk)) == 0); +} + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @param pancmd panal command selection. Refer @ref XMC_CAN_PANCMD_t for valid values. + * @param arg1 Panel Argument 1,Range : 0-2 + * @param arg2 Panel Argument 2, Range : 0-63 + * + * @return None + * + * \parDescription:
+ * Configures the panel command and panel arguments. A panel operation consists of a command code (PANCMD) and up to two + * panel arguments (PANAR1, PANAR2). Commands that have a return value deliver it to the PANAR1 bit field. Commands that + * return an error flag deliver it to bit 31 of the Panel Control Register, this means bit 7 of PANAR2. \a arg1 represents + * panel argument PANAR1,\a arg2 represents panel argument PANAR2 and \a pancmd represents command code. It configures PANCTR + * register. + * + * \parRelated APIs:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_PanelControl(XMC_CAN_t *const obj, + const XMC_CAN_PANCMD_t pancmd, + const uint8_t arg1, + const uint8_t arg2) +{ + obj->PANCTR = (((uint32_t)pancmd << CAN_PANCTR_PANCMD_Pos) & (uint32_t)CAN_PANCTR_PANCMD_Msk) | + (((uint32_t)arg1 << CAN_PANCTR_PANAR1_Pos) & (uint32_t)CAN_PANCTR_PANAR1_Msk) | + (((uint32_t)arg2 << CAN_PANCTR_PANAR2_Pos) & (uint32_t)CAN_PANCTR_PANAR2_Msk); +} + + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @param service_requestr Interrupt trigger number selection. Refer @ref XMC_CAN_NODE_INTERRUPT_TRIGGER_t for valid values. + * Multiple interrupt trigger events can be ORed. + * + * @return None + * + * \parDescription:
+ * Configures multiple interrupt requests with a single write operation. \a service_requestr represents single interrupt + * request or multiple.It configures MITR register. + * + * \parRelated APIs:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_EventTrigger(XMC_CAN_t *const obj,const XMC_CAN_NODE_INTERRUPT_TRIGGER_t service_requestr) +{ + obj->MITR = ((uint32_t)service_requestr << CAN_MITR_IT_Pos) & (uint32_t)CAN_MITR_IT_Msk; +} + + + + /*INIT APIs*/ + +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @param can_frequency CAN module frequency(fCAN). Range : 5MHz to 120MHz + * + * @return None + * + * \parDescription:
+ * Configures clock rate of the module timer clock fCAN. Altering CAN module \a can_frequency shall affects baud rate, + * call XMC_CAN_NODE_NominalBitTimeConfigure() to configure baud rate for current CAN frequency.It configures FDR register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_NominalBitTimeConfigure()\n\n\n + * + */ + + +#if defined(MULTICAN_PLUS) +void XMC_CAN_Init(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can_frequency); +/** + * + */ +XMC_CAN_CANCLKSRC_t XMC_CAN_GetBaudrateClockSource(XMC_CAN_t *const obj); +/** + * + */ +void XMC_CAN_SetBaudrateClockSource(XMC_CAN_t *const obj,const XMC_CAN_CANCLKSRC_t source); +/** + * + */ +uint32_t XMC_CAN_GetBaudrateClockFrequency(XMC_CAN_t *const obj); +#else +void XMC_CAN_Init(XMC_CAN_t *const obj, uint32_t can_frequency); +#endif + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Initializes CAN message object. Initialization includes configuring Message Object identifier type, Message Object + * identifier value, Message Object type, and transfer requests. It configures FDR register. + * + * \parRelated APIs:
+ * None + * + */ + +void XMC_CAN_MO_Config(const XMC_CAN_MO_t *const can_mo); + + + /*NODE APIs*/ + + +/** + * + * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers. + * @param ptr_event CAN_NODE interrupt pointer position. Refer @ref XMC_CAN_NODE_POINTER_EVENT_t structure for valid values. + * @param service_request Interrupt service request number. Range : 0-7 + * + * @return None + * + * \parDescription:
+ * Configures node interrupt pointer \a service_request for CAN Node events \a ptr_event. It configures NIPR register. + * + * \parRelated APIs:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_SetEventNodePointer(XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_POINTER_EVENT_t ptr_event, + const uint32_t service_request) +{ + can_node->NIPR = (uint32_t)((can_node->NIPR) & ~(uint32_t)(CAN_NODE_NIPR_Msk << (uint32_t)ptr_event)) | (service_request << (uint32_t)ptr_event); +} + + +/** + * + * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers. Range :CAN_NODE0-CAN_NODE2 + * @param can_bit_time Nominal bit time configuration data structure. Refer @ref XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t for details. + * + * @return None + * + * \parDescription:
+ * Configures CAN node Baudrate. \a can_bit_time specifies required baudrate for a specified \a can_node. + * It configures NBTR register. + * + * \parRelated APIs:
+ * None + * + */ +void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const can_bit_time); + +/** + * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param input CAN receive input selection. Refer @ref XMC_CAN_NODE_RECEIVE_INPUT_t for details. + * + * @return None + * + * \parDescription:
+ * \a input specifies CAN input receive pin. This API Configures NPCRx register,it is required to call + * XMC_CAN_NODE_EnableConfigurationChange(), before configuring NPCRx register, call XMC_CAN_NODE_DisableConfigurationChange() + * API after configuring NPCRx register. CAN input receive pins which falls under analog port pins should call + * XMC_GPIO_EnableDigitalInput(),to enable digital pad. + * + *\parRelated APIs:
+ * None + * + * \parNote:
+ * NPCRx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_SetReceiveInput(XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_RECEIVE_INPUT_t input) +{ + can_node->NPCR = ((can_node->NPCR) & ~(uint32_t)(CAN_NODE_NPCR_RXSEL_Msk)) | + (((uint32_t)input << CAN_NODE_NPCR_RXSEL_Pos) & (uint32_t)CAN_NODE_NPCR_RXSEL_Msk); +} + + +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Enable Node \a can_node in Loop-Back Mode. A Node is connected to an internal (virtual) loop-back CAN bus. All CAN + * nodes which are in Loop- Back Mode are connected to this virtual CAN bus so that they can communicate with each + * other internally. The external transmit line is forced recessive in Loop-Back Mode. This API Configures NPCRx register. + * call XMC_CAN_NODE_EnableConfigurationChange() API before NPCRx configuration, same way XMC_CAN_NODE_DisableConfigurationChange() + * API after NPCRx configuration configuration. + * + * \parRelated APIs:
] + * XMC_CAN_NODE_DisableLoopBack(). + * + * \parNote:
+ * NPCRx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_EnableLoopBack(XMC_CAN_NODE_t *const can_node) +{ + can_node->NPCR |= (uint32_t)CAN_NODE_NPCR_LBM_Msk; +} + + +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Disable Node Loop-Back Mode, disables internal (virtual) loop-back CAN bus. This API Configures NPCRx register. + * Call XMC_CAN_NODE_EnableConfigurationChange() API before NPCRx configuration, same way XMC_CAN_NODE_DisableConfigurationChange() + * API after NPCRx configuration. + * + * \parRelated APIs:
] + * XMC_CAN_NODE_EnableLoopBack() + * + * + * \parNote:
+ * NPCRx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_DisableLoopBack(XMC_CAN_NODE_t *const can_node) +{ + can_node->NPCR &= ~(uint32_t)CAN_NODE_NPCR_LBM_Msk; +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param event CAN node event mask value. Refer @ref XMC_CAN_NODE_EVENT_t structure for valid values. + * multiple events can be ORed. + * + * @return None + * + * \parDescription:
+ * Enable CAN Node events. It configures NFCR register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_DisableEvent() + * + */ + +void XMC_CAN_NODE_EnableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event); + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param event CAN node event mask value. Refer @ref XMC_CAN_NODE_EVENT_t structure for valid values. + * multiple events can be ORed. + * + * @return None + * + * \parDescription:
+ * Disable CAN Node events. It configures NFCR register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_EnableEvent() + * + */ + +void XMC_CAN_NODE_DisableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event); + + +/** + * + * @param node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return XMC_CAN_NODE_LAST_ERROR_DIR_t Last error transfer direction. Refer @ref XMC_CAN_NODE_LAST_ERROR_DIR_t. + * + * \parDescription:
+ * Returns NODE Last Error occurred during Transmit/receive direction. It returns value of NFCR register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetLastErrTransferInc()\n\n\n + * + */ + +__STATIC_INLINE XMC_CAN_NODE_LAST_ERROR_DIR_t XMC_CAN_NODE_GetLastErrTransferDir(XMC_CAN_NODE_t *const node) +{ + return (XMC_CAN_NODE_LAST_ERROR_DIR_t)(((node->NECNT) & CAN_NODE_NECNT_LETD_Msk) >> CAN_NODE_NECNT_LETD_Pos); +} + + +/** + * + * @param node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return XMC_CAN_NODE_LAST_ERROR_INC_t Last error transfer increment. Refer @ref XMC_CAN_NODE_LAST_ERROR_INC_t. + * + * \parDescription:
+ * Returns NODE Last Error Transfer Increment. It returns value of NFCR register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetLastErrTransferDir()\n\n\n + * + */ + +__STATIC_INLINE XMC_CAN_NODE_LAST_ERROR_INC_t XMC_CAN_NODE_GetLastErrTransferInc(XMC_CAN_NODE_t *const node) +{ + return (XMC_CAN_NODE_LAST_ERROR_INC_t)(((node->NECNT) & CAN_NODE_NECNT_LEINC_Msk)>> CAN_NODE_NECNT_LEINC_Pos); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param error_warning_level Error Warning level value. Range :0-255. + * + * @return None + * + * \parDescription:
+ * Configures error warning level in order to set the corresponding error warning bit EWRN. It configures \a error_warning_level + * into NECNT register. Before this configuration call XMC_CAN_NODE_EnableConfigurationChange() API. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetErrorWarningLevel()\n\n\n + * + * \parNote:
+ * NECNTx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_SetErrorWarningLevel(XMC_CAN_NODE_t *const can_node, uint8_t error_warning_level) +{ + can_node->NECNT = ((can_node->NECNT) & ~(uint32_t)(CAN_NODE_NECNT_EWRNLVL_Msk)) | + (((uint32_t)error_warning_level << CAN_NODE_NECNT_EWRNLVL_Pos) & (uint32_t)CAN_NODE_NECNT_EWRNLVL_Msk); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param can_tec transmit error counter value. Range :0-255 + * + * @return None + * + * \parDescription:
+ * Configures Transmit error counter. It configures \a can_tec into NECNT register. Before this configuration call + * XMC_CAN_NODE_EnableConfigurationChange() API. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetTransmitErrorCounter()\n\n\n + * + * \parNote:
+ * NECNTx can be written only if bit NCRx.CCE is set. + * + */ + + +__STATIC_INLINE void XMC_CAN_NODE_SetTransmitErrorCounter(XMC_CAN_NODE_t *const can_node, uint8_t can_tec) +{ + can_node->NECNT = ((can_node->NECNT) & ~(uint32_t)(CAN_NODE_NECNT_TEC_Msk)) | + (((uint32_t)can_tec << CAN_NODE_NECNT_TEC_Pos) & (uint32_t)CAN_NODE_NECNT_TEC_Msk); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param can_rec receive error counter value. Range :0-255 + * + * @return None + * + * \parDescription:
+ * Configures Receive Error Counter. It configures \a can_rec into NECNT register. Before this configuration call + * XMC_CAN_NODE_EnableConfigurationChange() API. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetReceiveErrorCounter()\n\n\n + * + * \parNote:
+ * NECNTx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_SetReceiveErrorCounter(XMC_CAN_NODE_t *const can_node, uint8_t can_rec) +{ + can_node->NECNT = ((can_node->NECNT) & ~(uint32_t)(CAN_NODE_NECNT_REC_Msk)) | + (((uint32_t)can_rec << CAN_NODE_NECNT_REC_Pos) & (uint32_t)CAN_NODE_NECNT_REC_Msk); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return uint8_t Error Warning Level. Range :0 - 255 + * + * \parDescription:
+ * Returns error warning level. This determines the threshold value (warning level, default 96) to be reached in order + * to set the corresponding error warning bit EWRN. It reads NECNT register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_SetErrorWarningLevel()\n\n\n + * + */ + + +__STATIC_INLINE uint8_t XMC_CAN_NODE_GetErrorWarningLevel(XMC_CAN_NODE_t *const can_node) +{ + return (uint8_t)((uint32_t)((can_node->NECNT) & CAN_NODE_NECNT_EWRNLVL_Msk) >> CAN_NODE_NECNT_EWRNLVL_Pos); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return uint8_t transmit error counter value. Range :0 - 255 + * + * \parDescription:
+ * Returns Transmit Error Counter value. If the Bitstream Processor detects an error while a transmit operation is + * running, the Transmit Error Counter is incremented by 8. An increment of 1 is used when the error condition was + * reported by an external CAN node via an Error Frame generation. It reads NECNT register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_SetTransmitErrorCounter() + * + * \parNote:
+ * NECNTx can be written only if bit NCRx.CCE is set. + * + */ + +__STATIC_INLINE uint8_t XMC_CAN_NODE_GetTransmitErrorCounter(XMC_CAN_NODE_t *const can_node) +{ + return (uint8_t)((uint32_t)((can_node->NECNT) & CAN_NODE_NECNT_TEC_Msk) >> CAN_NODE_NECNT_TEC_Pos); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return uint8_t receive error counter value. + * + * \parDescription:
+ * Returns Receive Error Counter value. It reads NECNT register. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_SetReceiveErrorCounter() + * + */ + +__STATIC_INLINE uint8_t XMC_CAN_NODE_GetReceiveErrorCounter(XMC_CAN_NODE_t *const can_node) +{ + return (uint8_t)((uint32_t)((can_node->NECNT) & CAN_NODE_NECNT_REC_Msk) >> CAN_NODE_NECNT_REC_Pos); +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return uint32_t Current status of the node. + * + * \parDescription:
+ * Returns errors status as well as successfully transferred CAN frames status. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_ClearStatus() + * + */ + +__STATIC_INLINE uint32_t XMC_CAN_NODE_GetStatus(XMC_CAN_NODE_t *const can_node) +{ + return ((can_node->NSR)); +} + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param can_node_status Status to clear.Refer @ref XMC_CAN_NODE_STATUS_t for valid values. + * + * @return None + * + * \parDescription:
+ * Clear errors status as well as successfully transferred CAN frames status. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_GetStatus() + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_ClearStatus(XMC_CAN_NODE_t *const can_node,XMC_CAN_NODE_STATUS_t can_node_status) +{ + can_node->NSR &= ~(uint32_t)can_node_status; +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Allow to change the configuration of the CAN node, like bit timing, CAN bus transmit/receive ports and error + * counters read. It configures NCRx.CCE bit. + * + * \parRelated APIs:
+ * XMC_CAN_NODE_DisableConfigurationChange() + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_EnableConfigurationChange(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_CCE_Msk; +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Forbid to change the configuration of the CAN node. It configures NCRx.CCE bit. + * + * \parRelated API's:
+ * XMC_CAN_NODE_EnableConfigurationChange() + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_DisableConfigurationChange(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR &= ~(uint32_t)CAN_NODE_NCR_CCE_Msk; +} + + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Disable CAN node participation in CAN traffic. Bit INIT is automatically set when the CAN node enters the bus-off + * state. It configures NCR.INIT bit. + * + * \parRelated API's:
+ * XMC_CAN_NODE_ResetInitBit() + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_SetInitBit(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_INIT_Msk; +} + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Enable CAN node participation in CAN traffic. Bit INIT is automatically set when the CAN node enters the bus-off + * state. It configures NCR.INIT bit. + * + * \parRelated API's:
+ * XMC_CAN_NODE_SetInitBit() + * + */ +__STATIC_INLINE void XMC_CAN_NODE_ResetInitBit(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR &= ~(uint32_t)CAN_NODE_NCR_INIT_Msk; +} + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Enable the CAN node, starts the participation in CAN traffic. It configures NCR.CANDIS and the NCR.INIT bits. + * + * \parRelated API's:
+ * None + * + */ +__STATIC_INLINE void XMC_CAN_NODE_Enable(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR &= ~(uint32_t)CAN_NODE_NCR_CANDIS_Msk; + XMC_CAN_NODE_ResetInitBit(can_node); +} + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Disable the CAN node, terminates participation in CAN traffic. It configures NCR.CANDIS bit. + * + * \parRelated API's:
+ * None + * + */ +__STATIC_INLINE void XMC_CAN_NODE_Disable(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_CANDIS_Msk; +} + +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Configure CAN node in Analyzer Mode. This means that messages may be received, but not transmitted. No acknowledge + * is sent on the CAN bus upon frame reception. Active-error flags are sent recessive instead of dominant. + * The transmit line is continuously held at recessive (1) level. XMC_CAN_NODE_SetInitBit() should be called before + * set / reset AnalyzerMode. It configures NCR.CALM bit. + * + * \parRelated API's:
+ * XMC_CAN_NODE_ReSetAnalyzerMode() + * + */ + + +__STATIC_INLINE void XMC_CAN_NODE_SetAnalyzerMode(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_CALM_Msk; +} + + +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Reset the Analyzer mode. CAN node is no more in Analyzer Mode. Please refer XMC_CAN_NODE_SetAnalyzerMode(). + * It configures NCR.CALM bit. XMC_CAN_NODE_SetInitBit() should be called before set / reset AnalyzerMode. + * + * \parRelated API's:
+ * XMC_CAN_NODE_SetAnalyzerMode() + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_ReSetAnalyzerMode(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR &= ~(uint32_t)CAN_NODE_NCR_CALM_Msk; +} + +#if !defined(MULTICAN_PLUS) +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Trigger the suspension of the CAN node. An OCDS(on chip debug support) suspend trigger disables the CAN node: As + * soon as the CAN node becomes bus-idle or bus-off, bit INIT is internally forced to 1 to disable the CAN node. + * The actual value of bit INIT remains unchanged. It configures NCR.SUSEN bit + * + * \parRelated API's:
+ * None + * + *\parNote:
+ * Bit SUSEN is reset via OCDS(on chip debug support) Reset. + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_EnableSuspend(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_SUSEN_Msk; +} +#else +/** + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return None + * + * \parDescription:
+ * Disables the transmission on CAN node x as soon as bus-idle is reached. + * + * \parRelated API's:
+ * None + * + * @note Only available for XMC1400,XMC4800 and XMC4700 series + */ + +__STATIC_INLINE void XMC_CAN_NODE_DisableTransmit(XMC_CAN_NODE_t *const can_node) +{ + can_node->NCR |= (uint32_t)CAN_NODE_NCR_TXDIS_Msk; +} +#endif + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param can_node_init frame counter mode selection. Refer @ref XMC_CAN_NODE_FRAME_COUNTER_t for valid values. + * + * @return None + * + * \parDescription:
+ * Configures frame counter functions. Each CAN \a can_node is equipped with a frame counter that counts transmitted/received + * CAN frames or obtains information about the time when a frame has been started to transmit or be received by the CAN + * node. It configures NFCR register. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_NODE_FrameCounterConfigure(XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_FRAME_COUNTER_t *const can_node_init) +{ + can_node->NFCR = (can_node->NFCR & ~(uint32_t)(CAN_NODE_NFCR_CFMOD_Msk | + CAN_NODE_NFCR_CFSEL_Msk)) | + can_node_init->nfcr; +} + + +/** + * + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * + * @return uint16_t current value of the CAN frame counter. Range :0-65535 + * + * \parDescription:
+ * Returns the frame counter value \a can_node of the CAN node. In Frame Count Mode (CFMOD = 00B), this API returns the frame + * count value. In Time Stamp Mode (CFMOD = 01B), this API returns the captured bit time count value, captured with + * the start of a new frame. In all Bit Timing Analysis Modes (CFMOD = 10B), this API always returns the number of + * fCLC clock cycles (measurement result) minus 1. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE uint16_t XMC_CAN_NODE_GetCANFrameCounter(XMC_CAN_NODE_t *const can_node) +{ + return (uint16_t)(((uint32_t)(can_node->NFCR & CAN_NODE_NFCR_CFC_Msk) >> CAN_NODE_NFCR_CFC_Pos)); +} + + /*MO APIs*/ + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * + * @return None + * + * \parDescription:
+ * Configures Data to be transmitted and data length code. + * + * \parRelated API's:
+ * XMC_CAN_MO_Config()\n\n\n + * + */ + + +XMC_CAN_STATUS_t XMC_CAN_MO_UpdateData(const XMC_CAN_MO_t *const can_mo); + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * + * \parDescription:
+ * Configures transmit request for sending data frame. It configures MOCTR register. Data shall be updated + * using XMC_CAN_MO_UpdateData() before calling this API. + * + * \parRelated API's:
+ * XMC_CAN_MO_UpdateData()\n\n\n + * + */ + +XMC_CAN_STATUS_t XMC_CAN_MO_Transmit(const XMC_CAN_MO_t *const can_mo); + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * + * \parDescription:
+ * Reads the Message Object data bytes, into message pointer passed as input parameter \a can_mo. + * can_data[0] of can_mo holds lower 4 bytes, can_data[1] of can_mo holds higher 4 bytes. + * + * \parRelated API's:
+ * None + * + */ + +XMC_CAN_STATUS_t XMC_CAN_MO_Receive(XMC_CAN_MO_t *can_mo); + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * + * \parDescription:
+ * Reads the Message Object data bytes, into message pointer passed as input parameter \a can_mo. + * can_data[0] of can_mo holds lower 4 bytes, can_data[1] of can_mo holds higher 4 bytes. + * + * \parRelated API's:
+ * None + * + */ +XMC_CAN_STATUS_t XMC_CAN_MO_ReceiveData (XMC_CAN_MO_t *can_mo); +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_mo_ptr_int Message Object event node pointer selection. Refer @ref XMC_CAN_MO_POINTER_EVENT_t structure + * for valid values. + * @param service_request interrupt output line of multiCAN module. + * + * @return None + * + * \parDescription:
+ * Configures Message Object event node pointer with \a service_request number. It configures MOIPR register. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_MO_SetEventNodePointer(const XMC_CAN_MO_t *const can_mo, + const XMC_CAN_MO_POINTER_EVENT_t can_mo_ptr_int, + const uint32_t service_request) +{ + can_mo->can_mo_ptr->MOIPR = ((can_mo->can_mo_ptr->MOIPR ) & ~(uint32_t)((uint32_t)CAN_MO_MOIPR_Msk << (uint32_t)can_mo_ptr_int)) | + (service_request << (uint32_t)can_mo_ptr_int); +} + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return uint32_t Current Message Object status. + * + * \parDescription:
+ * Returns Message Object status, that indicates message object transfer status and message object list status + * information such as the number of the current message object predecessor and successor message object, as well as + * the list number to which the message object is assigned. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE uint32_t XMC_CAN_MO_GetStatus(const XMC_CAN_MO_t *const can_mo) +{ + return ((can_mo->can_mo_ptr->MOSTAT)); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param mask Message Object set status selection. Refer @ref XMC_CAN_MO_SET_STATUS_t for details. + * Multiple enums can be ORed. + * @return None + * + * \parDescription:
+ * Configures Message Object set Status. It configures MOCTR register. + * + * \parRelated API's:
+ * XMC_CAN_MO_ResetStatus()\n\n\n + * + */ + +__STATIC_INLINE void XMC_CAN_MO_SetStatus(const XMC_CAN_MO_t *const can_mo, const uint32_t mask) +{ + can_mo->can_mo_ptr->MOCTR = mask; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param mask Message Object set status selection. Refer @ref XMC_CAN_MO_RESET_STATUS_t for details. + * Multiple enums can be ORed. + * @return None + * + * \parDescription:
+ * Clears Message Object interrupt events. It configures MOCTR register. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_MO_ResetStatus(const XMC_CAN_MO_t *const can_mo,const uint32_t mask) +{ + can_mo->can_mo_ptr->MOCTR = mask; +} + + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param event CAN node Message Object event selection. Refer @ref XMC_CAN_MO_EVENT_t for details. + * + * @return None + * + * \parDescription:
+ * Enable CAN Message Object events. \a event can be ORed multiple Message Object events. It configures MOFCR register. + * + * \parRelated API's:
+ * XMC_CAN_MO_DisableEvent() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_EnableEvent(const XMC_CAN_MO_t *const can_mo, + const uint32_t event) +{ + can_mo->can_mo_ptr->MOFCR |= event; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param event CAN node Message Object event selection. Refer @ref XMC_CAN_MO_EVENT_t for details. + * + * @return None + * + * \parDescription:
+ * Disable CAN Message Object events. \a event can be ORed multiple Message Object events. It configures MOFCR register. + * + * \parRelated API's:
+ * XMC_CAN_MO_EnableEvent() + * + * + */ + +__STATIC_INLINE void XMC_CAN_MO_DisableEvent(const XMC_CAN_MO_t *const can_mo, + const uint32_t event) +{ + can_mo->can_mo_ptr->MOFCR &= ~event; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Enable the single transmit trial(STT). In STT,TXRQ is cleared on transmission start of message object n. Thus, + * no transmission retry is performed in case of transmission failure. It configures MOFCR.STT bit. + * + * \parRelated API's:
+ * XMC_CAN_MO_DisableSingleTransmitTrial() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_EnableSingleTransmitTrial(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR |= (uint32_t) CAN_MO_MOFCR_STT_Msk; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Disable the single transmit trial(STT). In STT,TXRQ is cleared on transmission start of message object n. Thus, + * no transmission retry is performed in case of transmission failure. It configures MOFCR.STT bit. + * + * \parRelated API's:
+ * XMC_CAN_MO_EnableSingleTransmitTrial() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_DisableSingleTransmitTrial(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR &= ~(uint32_t)CAN_MO_MOFCR_STT_Msk; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param data_length_code transfer data length. Range:0-8 + * + * @return None + * + * \parDescription:
+ * Configures CAN Message Object Data Length Code. It configures MOFCR register. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_MO_DataLengthCode(const XMC_CAN_MO_t *const can_mo,const uint8_t data_length_code) +{ + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_DLC_Msk)) | + (((uint32_t)data_length_code << CAN_MO_MOFCR_DLC_Pos) & (uint32_t)CAN_MO_MOFCR_DLC_Msk); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param data_length_code transfer data length. Range:0-8 + * + * @return None + * + * \parDescription:
+ * Configures CAN Message Object Data Length Code. It configures MOFCR register. + * + * \parRelated API's:
+ * XMC_CAN_MO_GetDataLengthCode() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_SetDataLengthCode(XMC_CAN_MO_t *const can_mo,const uint8_t data_length_code) +{ + can_mo->can_data_length = data_length_code; + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_DLC_Msk)) | + (((uint32_t)data_length_code << CAN_MO_MOFCR_DLC_Pos) & (uint32_t)CAN_MO_MOFCR_DLC_Msk); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return Data length code + * + * \parDescription:
+ * Gets the Data Length Code. + * + * \parRelated API's:
+ * XMC_CAN_MO_SetDataLengthCode() + * + */ + +__STATIC_INLINE uint8_t XMC_CAN_MO_GetDataLengthCode(const XMC_CAN_MO_t *const can_mo) +{ + return (((can_mo->can_mo_ptr->MOFCR) & (uint32_t)(CAN_MO_MOFCR_DLC_Msk)) >> CAN_MO_MOFCR_DLC_Pos); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_identifier Identifier. + * + * @return None + * + * \parDescription:
+ * Configures CAN Message Object Identifier. It configures MOAR register. + * + * \parRelated API's:
+ * XMC_CAN_MO_GetIdentifier() + * + */ + +void XMC_CAN_MO_SetIdentifier(XMC_CAN_MO_t *const can_mo, const uint32_t can_identifier); + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return CAN MO identifier + * + * \parDescription:
+ * Gets the Identifier of the MO + * + * \parRelated API's:
+ * XMC_CAN_MO_SetIdentifier() + * + */ + +uint32_t XMC_CAN_MO_GetIdentifier(const XMC_CAN_MO_t *const can_mo); + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return Acceptance mask + * + * \parDescription:
+ * Gets the acceptance mask for the CAN MO. + * + * \parRelated API's:
+ * XMC_CAN_MO_SetAcceptanceMask() + * + */ + +uint32_t XMC_CAN_MO_GetAcceptanceMask(const XMC_CAN_MO_t *const can_mo); + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_id_mask CAN MO acceptance mask. + * + * @return None + * + * \parDescription:
+ * Sets the acceptance mask of the MO + * + * \parRelated API's:
+ * XMC_CAN_MO_GetAcceptanceMask() + * + */ + +void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo,const uint32_t can_id_mask); + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Message object receives frames only with matching IDE bit. + * + * \parRelated API's:
+ * XMC_CAN_MO_AcceptStandardAndExtendedID() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_AcceptOnlyMatchingIDE(XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_ide_mask = 1U; + can_mo->can_mo_ptr->MOAMR |=(uint32_t)(CAN_MO_MOAMR_MIDE_Msk); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Message object accepts the reception of both, standard and extended frames. + * + * \parRelated API's:
+ * XMC_CAN_MO_AcceptOnlyMatchingIDE() + * + */ + +__STATIC_INLINE void XMC_CAN_MO_AcceptStandardAndExtendedID(XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_ide_mask = 0U; + can_mo->can_mo_ptr->MOAMR &= ~(uint32_t)(CAN_MO_MOAMR_MIDE_Msk); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Message object handles standard frames with 11-bit identifier. + * + * \parRelated API's:
+ * XMC_CAN_MO_SetExtendedID() + * + * \parNote:
+ * After setting the identifier type user has to set the identifier value by using @ref XMC_CAN_MO_SetIdentifier() API. + */ + +__STATIC_INLINE void XMC_CAN_MO_SetStandardID(XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_STANDARD_11BITS; + can_mo->can_mo_ptr->MOAR &= ~(uint32_t)(CAN_MO_MOAR_IDE_Msk); +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Message object handles extended frames with 29-bit identifier. + * + * \parRelated API's:
+ * XMC_CAN_MO_SetStandardID() + * + * \parNote:
+ * After setting the identifier type user has to set the identifier value by using @ref XMC_CAN_MO_SetIdentifier() API. + * + */ + +__STATIC_INLINE void XMC_CAN_MO_SetExtendedID(XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_EXTENDED_29BITS; + can_mo->can_mo_ptr->MOAR |= (uint32_t)CAN_MO_MOAR_IDE_Msk; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to enable the FIFO Foreign Remote Request. This Specifies TXRQ of the message object referenced + * by the pointer CUR is set on reception of a matching Remote Frame. It configures MOFCR.FRREN register. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_DisableForeingRemoteRequest()\n\n\n + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_EnableForeignRemoteRequest(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR |= (uint32_t)CAN_MO_MOFCR_FRREN_Msk; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to disable the FIFO Foreign Remote Request. TXRQ of message object n is set on reception + * of a matching Remote Frame. It configures MOFCR.FRREN register. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_EnableForeignRemoteRequest()\n\n\n + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_DisableForeingRemoteRequest(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR &= ~(uint32_t)CAN_MO_MOFCR_FRREN_Msk; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to enable the FIFO Remote Monitoring. This Specifies identifier, IDE(Identifier Extension) bit, + * and DLC of a matching Remote Frame are copied to transmit object n in order to monitor incoming Remote Frames. + * It configures MOFCR.RMM bit. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_DisableRemoteMonitoring()\n\n\n + * + * \parNote:
+ * Remote monitoring(RMM) applies only to transmit objects and has no effect on receive objects. + * + */ +__STATIC_INLINE void XMC_CAN_FIFO_EnableRemoteMonitoring(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR |= (uint32_t)CAN_MO_MOFCR_RMM_Msk; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to disable the FIFO Remote Monitoring. This Specifies Identifier, Identifier Extension bit, + * and DLC of message object n remain unchanged upon the reception of a matching Remote Frame. + * It configures MOFCR.RMM bit. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_EnableRemoteMonitoring()\n\n\n + * + * \parNote:
+ * Remote monitoring(RMM) applies only to transmit objects and has no effect on receive objects. + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_DisableRemoteMonitoring(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR &= ~(uint32_t)CAN_MO_MOFCR_RMM_Msk; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param select_pointer Selected Message Object number. Range:0-63 + * + * @return None + * + * \parDescription:
+ * Set Object Select Pointer. If the current pointer CUR of FIFO base object becomes equal \a select_pointer, + * a FIFO overflow interrupt request is generated. Used for FIFO monitoring purpose. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_SetSELMO(const XMC_CAN_MO_t *const can_mo,const uint8_t select_pointer) +{ + can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_SEL_Msk)) | + (((uint32_t)select_pointer << CAN_MO_MOFGPR_SEL_Pos) & (uint32_t)CAN_MO_MOFGPR_SEL_Msk); +} + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return uint8_t Current Message Object Number. Range:0-63 + * + * \parDescription:
+ * Returns the current FIFO Message Object,points to the actual target object within a FIFO/Gateway structure. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE uint8_t XMC_CAN_FIFO_GetCurrentMO(const XMC_CAN_MO_t *const can_mo) +{ + return (uint8_t)((uint32_t)(can_mo->can_mo_ptr->MOFGPR & CAN_MO_MOFGPR_CUR_Msk) >> CAN_MO_MOFGPR_CUR_Pos); +} + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to enable the Single Data Transfer of the FIFO Message Object. If SDT = 1 and message object n + * is not a FIFO base object, then MSGVAL is reset when this object has taken part in a successful data transfer + * (receive or transmit). If SDT = 1 and message object n is a FIFO base object, then MSGVAL is reset when the pointer + * to the current object CUR reaches the value of SEL in the FIFO/Gateway Pointer Register. It configures MOFCR.SDT bit. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_DisableSingleDataTransfer() + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_EnableSingleDataTransfer(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR |= (uint32_t)CAN_MO_MOFCR_SDT_Msk; +} + + +/** + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configuration allows to disable the Single Data Transfer of the FIFO Message Object, with this configuration bit + * MSGVAL is not affected. It configures MOFCR.SDT bit. + * + * \parRelated API's:
+ * XMC_CAN_FIFO_EnableSingleDataTransfer() + * + */ + +__STATIC_INLINE void XMC_CAN_FIFO_DisableSingleDataTransfer(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOFCR &= ~(uint32_t)CAN_MO_MOFCR_SDT_Msk; +} + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_fifo CAN FIFO configuration data structure. Refer @ref XMC_CAN_FIFO_CONFIG_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the transmit FIFO. A FIFO consists of one base object and n slave objects. Please refer + * reference manual \b Transmit FIFO for more info. + * + * \parRelated API's:
+ * None. + * + */ + +void XMC_CAN_TXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo); + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_fifo CAN FIFO configuration data structure. Refer @ref XMC_CAN_FIFO_CONFIG_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the base object of receive FIFO. + * + * \parRelated API's:
+ * None + */ + +void XMC_CAN_RXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo); + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_fifo CAN FIFO configuration data structure. Refer @ref XMC_CAN_FIFO_CONFIG_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the slave object of transmit FIFO. + * + * \parRelated API's:
+ * None + * + */ +void XMC_CAN_TXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo); + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the slave Object of receive FIFO. It configures MOCTR.RESRXEN bit. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_RXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOCTR = (uint32_t)CAN_MO_MOCTR_RESRXEN_Msk; +} + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_gateway CAN gateway configuration data structure. Refer XMC_CAN_GATEWAY_CONFIG_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the Gateway source object. The Gateway Mode \a can_gateway makes it possible to establish an automatic + * information transfer between two independent CAN buses without CPU interaction. Please refer reference manual + * \b GatewayMode for more info. + * + * \parRelated API's:
+ * None + * + */ + +void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_GATEWAY_CONFIG_t can_gateway); + + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return None + * + * \parDescription:
+ * Configures the Gateway destination object. The Gateway Mode \a can_gateway makes it possible to establish an automatic + * information transfer between two independent CAN buses without CPU interaction. Please refer reference manual + * \b GatewayMode for more info. + * + * \parRelated API's:
+ * None + * + */ + +__STATIC_INLINE void XMC_CAN_GATEWAY_InitDesObject(const XMC_CAN_MO_t *const can_mo) +{ + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESRXEN_Msk | + CAN_MO_MOCTR_RESNEWDAT_Msk; +} + +/** + * + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * + * \parDescription:
+ * To transmit Message Object from the FIFO. Prior to this CAN node Message Object FIFO structure shall be made using + * XMC_CAN_TXFIFO_ConfigMOBaseObject(), XMC_CAN_TXFIFO_ConfigMOSlaveObject(),XMC_CAN_RXFIFO_ConfigMOBaseObject() API's. + * Please refer reference manual \b MessageObject \b FIFOStructure for more info. + * + * + */ +XMC_CAN_STATUS_t XMC_CAN_TXFIFO_Transmit(const XMC_CAN_MO_t *const can_mo); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CAN) */ + +#endif /* XMC_CAN_H */ + + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_can_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_can_map.h new file mode 100644 index 00000000..a8bff4d6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_can_map.h @@ -0,0 +1,629 @@ +/** + * @file xmc_can_map.h + * @date 2015-10-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-10-20: + * - Removed "const" in the MOs for avoiding compiler warnings + * + * 2015-09-15: + * - Initial version + * + * @endcond + * + */ + +#ifndef XMC_CAN_MAP_H +#define XMC_CAN_MAP_H + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN48) +#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#endif + +#if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN64) +#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#endif + +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48) +#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#endif + +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN64) +#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#endif + +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#endif + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + +#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#endif + + +#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + + +#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE5_RXD_P5_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#endif + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#endif + +#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LFBGA196) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE3_RXD_P7_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE4_RXD_P7_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE5_RXD_P5_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE5_RXD_P8_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#endif + +#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) +#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#endif + +#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || (UC_SERIES == XMC43)|| (UC_SERIES == XMC14) +#define CAN_MO0 ((CAN_MO_TypeDef *)&(CAN_MO->MO[0])) +#define CAN_MO1 ((CAN_MO_TypeDef *)&(CAN_MO->MO[1])) +#define CAN_MO2 ((CAN_MO_TypeDef *)&(CAN_MO->MO[2])) +#define CAN_MO3 ((CAN_MO_TypeDef *)&(CAN_MO->MO[3])) +#define CAN_MO4 ((CAN_MO_TypeDef *)&(CAN_MO->MO[4])) +#define CAN_MO5 ((CAN_MO_TypeDef *)&(CAN_MO->MO[5])) +#define CAN_MO6 ((CAN_MO_TypeDef *)&(CAN_MO->MO[6])) +#define CAN_MO7 ((CAN_MO_TypeDef *)&(CAN_MO->MO[7])) +#define CAN_MO8 ((CAN_MO_TypeDef *)&(CAN_MO->MO[8])) +#define CAN_MO9 ((CAN_MO_TypeDef *)&(CAN_MO->MO[9])) +#define CAN_MO10 ((CAN_MO_TypeDef *)&(CAN_MO->MO[10])) +#define CAN_MO11 ((CAN_MO_TypeDef *)&(CAN_MO->MO[11])) +#define CAN_MO12 ((CAN_MO_TypeDef *)&(CAN_MO->MO[12])) +#define CAN_MO13 ((CAN_MO_TypeDef *)&(CAN_MO->MO[13])) +#define CAN_MO14 ((CAN_MO_TypeDef *)&(CAN_MO->MO[14])) +#define CAN_MO15 ((CAN_MO_TypeDef *)&(CAN_MO->MO[15])) +#define CAN_MO16 ((CAN_MO_TypeDef *)&(CAN_MO->MO[16])) +#define CAN_MO17 ((CAN_MO_TypeDef *)&(CAN_MO->MO[17])) +#define CAN_MO18 ((CAN_MO_TypeDef *)&(CAN_MO->MO[18])) +#define CAN_MO19 ((CAN_MO_TypeDef *)&(CAN_MO->MO[19])) +#define CAN_MO20 ((CAN_MO_TypeDef *)&(CAN_MO->MO[20])) +#define CAN_MO21 ((CAN_MO_TypeDef *)&(CAN_MO->MO[21])) +#define CAN_MO22 ((CAN_MO_TypeDef *)&(CAN_MO->MO[22])) +#define CAN_MO23 ((CAN_MO_TypeDef *)&(CAN_MO->MO[23])) +#define CAN_MO24 ((CAN_MO_TypeDef *)&(CAN_MO->MO[24])) +#define CAN_MO25 ((CAN_MO_TypeDef *)&(CAN_MO->MO[25])) +#define CAN_MO26 ((CAN_MO_TypeDef *)&(CAN_MO->MO[26])) +#define CAN_MO27 ((CAN_MO_TypeDef *)&(CAN_MO->MO[27])) +#define CAN_MO28 ((CAN_MO_TypeDef *)&(CAN_MO->MO[28])) +#define CAN_MO29 ((CAN_MO_TypeDef *)&(CAN_MO->MO[29])) +#define CAN_MO30 ((CAN_MO_TypeDef *)&(CAN_MO->MO[30])) +#define CAN_MO31 ((CAN_MO_TypeDef *)&(CAN_MO->MO[31])) +#endif + + +#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48)|| (UC_SERIES == XMC43) +#define CAN_MO32 ((CAN_MO_TypeDef *)&(CAN_MO->MO[32])) +#define CAN_MO33 ((CAN_MO_TypeDef *)&(CAN_MO->MO[33])) +#define CAN_MO34 ((CAN_MO_TypeDef *)&(CAN_MO->MO[34])) +#define CAN_MO35 ((CAN_MO_TypeDef *)&(CAN_MO->MO[35])) +#define CAN_MO36 ((CAN_MO_TypeDef *)&(CAN_MO->MO[36])) +#define CAN_MO37 ((CAN_MO_TypeDef *)&(CAN_MO->MO[37])) +#define CAN_MO38 ((CAN_MO_TypeDef *)&(CAN_MO->MO[38])) +#define CAN_MO39 ((CAN_MO_TypeDef *)&(CAN_MO->MO[39])) +#define CAN_MO40 ((CAN_MO_TypeDef *)&(CAN_MO->MO[40])) +#define CAN_MO41 ((CAN_MO_TypeDef *)&(CAN_MO->MO[41])) +#define CAN_MO42 ((CAN_MO_TypeDef *)&(CAN_MO->MO[42])) +#define CAN_MO43 ((CAN_MO_TypeDef *)&(CAN_MO->MO[43])) +#define CAN_MO44 ((CAN_MO_TypeDef *)&(CAN_MO->MO[44])) +#define CAN_MO45 ((CAN_MO_TypeDef *)&(CAN_MO->MO[45])) +#define CAN_MO46 ((CAN_MO_TypeDef *)&(CAN_MO->MO[46])) +#define CAN_MO47 ((CAN_MO_TypeDef *)&(CAN_MO->MO[47])) +#define CAN_MO48 ((CAN_MO_TypeDef *)&(CAN_MO->MO[48])) +#define CAN_MO49 ((CAN_MO_TypeDef *)&(CAN_MO->MO[49])) +#define CAN_MO50 ((CAN_MO_TypeDef *)&(CAN_MO->MO[50])) +#define CAN_MO51 ((CAN_MO_TypeDef *)&(CAN_MO->MO[51])) +#define CAN_MO52 ((CAN_MO_TypeDef *)&(CAN_MO->MO[52])) +#define CAN_MO53 ((CAN_MO_TypeDef *)&(CAN_MO->MO[53])) +#define CAN_MO54 ((CAN_MO_TypeDef *)&(CAN_MO->MO[54])) +#define CAN_MO55 ((CAN_MO_TypeDef *)&(CAN_MO->MO[55])) +#define CAN_MO56 ((CAN_MO_TypeDef *)&(CAN_MO->MO[56])) +#define CAN_MO57 ((CAN_MO_TypeDef *)&(CAN_MO->MO[57])) +#define CAN_MO58 ((CAN_MO_TypeDef *)&(CAN_MO->MO[58])) +#define CAN_MO59 ((CAN_MO_TypeDef *)&(CAN_MO->MO[59])) +#define CAN_MO60 ((CAN_MO_TypeDef *)&(CAN_MO->MO[60])) +#define CAN_MO61 ((CAN_MO_TypeDef *)&(CAN_MO->MO[61])) +#define CAN_MO62 ((CAN_MO_TypeDef *)&(CAN_MO->MO[62])) +#define CAN_MO63 ((CAN_MO_TypeDef *)&(CAN_MO->MO[63])) +#if (UC_SERIES != XMC43) +#define CAN_MO64 ((CAN_MO_TypeDef *)&(CAN_MO->MO[64])) +#define CAN_MO65 ((CAN_MO_TypeDef *)&(CAN_MO->MO[65])) +#define CAN_MO66 ((CAN_MO_TypeDef *)&(CAN_MO->MO[66])) +#define CAN_MO67 ((CAN_MO_TypeDef *)&(CAN_MO->MO[67])) +#define CAN_MO68 ((CAN_MO_TypeDef *)&(CAN_MO->MO[68])) +#define CAN_MO69 ((CAN_MO_TypeDef *)&(CAN_MO->MO[69])) +#define CAN_MO70 ((CAN_MO_TypeDef *)&(CAN_MO->MO[70])) +#define CAN_MO71 ((CAN_MO_TypeDef *)&(CAN_MO->MO[71])) +#define CAN_MO72 ((CAN_MO_TypeDef *)&(CAN_MO->MO[72])) +#define CAN_MO73 ((CAN_MO_TypeDef *)&(CAN_MO->MO[73])) +#define CAN_MO74 ((CAN_MO_TypeDef *)&(CAN_MO->MO[74])) +#define CAN_MO75 ((CAN_MO_TypeDef *)&(CAN_MO->MO[75])) +#define CAN_MO76 ((CAN_MO_TypeDef *)&(CAN_MO->MO[76])) +#define CAN_MO77 ((CAN_MO_TypeDef *)&(CAN_MO->MO[77])) +#define CAN_MO78 ((CAN_MO_TypeDef *)&(CAN_MO->MO[78])) +#define CAN_MO79 ((CAN_MO_TypeDef *)&(CAN_MO->MO[79])) +#define CAN_MO80 ((CAN_MO_TypeDef *)&(CAN_MO->MO[80])) +#define CAN_MO81 ((CAN_MO_TypeDef *)&(CAN_MO->MO[81])) +#define CAN_MO82 ((CAN_MO_TypeDef *)&(CAN_MO->MO[82])) +#define CAN_MO83 ((CAN_MO_TypeDef *)&(CAN_MO->MO[83])) +#define CAN_MO84 ((CAN_MO_TypeDef *)&(CAN_MO->MO[84])) +#define CAN_MO85 ((CAN_MO_TypeDef *)&(CAN_MO->MO[85])) +#define CAN_MO86 ((CAN_MO_TypeDef *)&(CAN_MO->MO[86])) +#define CAN_MO87 ((CAN_MO_TypeDef *)&(CAN_MO->MO[87])) +#define CAN_MO88 ((CAN_MO_TypeDef *)&(CAN_MO->MO[88])) +#define CAN_MO89 ((CAN_MO_TypeDef *)&(CAN_MO->MO[89])) +#define CAN_MO90 ((CAN_MO_TypeDef *)&(CAN_MO->MO[90])) +#define CAN_MO91 ((CAN_MO_TypeDef *)&(CAN_MO->MO[91])) +#define CAN_MO92 ((CAN_MO_TypeDef *)&(CAN_MO->MO[92])) +#define CAN_MO93 ((CAN_MO_TypeDef *)&(CAN_MO->MO[93])) +#define CAN_MO94 ((CAN_MO_TypeDef *)&(CAN_MO->MO[94])) +#define CAN_MO95 ((CAN_MO_TypeDef *)&(CAN_MO->MO[95])) +#define CAN_MO96 ((CAN_MO_TypeDef *)&(CAN_MO->MO[96])) +#define CAN_MO97 ((CAN_MO_TypeDef *)&(CAN_MO->MO[97])) +#define CAN_MO98 ((CAN_MO_TypeDef *)&(CAN_MO->MO[98])) +#define CAN_MO99 ((CAN_MO_TypeDef *)&(CAN_MO->MO[99])) +#define CAN_MO100 ((CAN_MO_TypeDef *)&(CAN_MO->MO[100])) +#define CAN_MO101 ((CAN_MO_TypeDef *)&(CAN_MO->MO[101])) +#define CAN_MO102 ((CAN_MO_TypeDef *)&(CAN_MO->MO[102])) +#define CAN_MO103 ((CAN_MO_TypeDef *)&(CAN_MO->MO[103])) +#define CAN_MO104 ((CAN_MO_TypeDef *)&(CAN_MO->MO[104])) +#define CAN_MO105 ((CAN_MO_TypeDef *)&(CAN_MO->MO[105])) +#define CAN_MO106 ((CAN_MO_TypeDef *)&(CAN_MO->MO[106])) +#define CAN_MO107 ((CAN_MO_TypeDef *)&(CAN_MO->MO[107])) +#define CAN_MO108 ((CAN_MO_TypeDef *)&(CAN_MO->MO[108])) +#define CAN_MO109 ((CAN_MO_TypeDef *)&(CAN_MO->MO[109])) +#define CAN_MO110 ((CAN_MO_TypeDef *)&(CAN_MO->MO[110])) +#define CAN_MO111 ((CAN_MO_TypeDef *)&(CAN_MO->MO[111])) +#define CAN_MO112 ((CAN_MO_TypeDef *)&(CAN_MO->MO[112])) +#define CAN_MO113 ((CAN_MO_TypeDef *)&(CAN_MO->MO[113])) +#define CAN_MO114 ((CAN_MO_TypeDef *)&(CAN_MO->MO[114])) +#define CAN_MO115 ((CAN_MO_TypeDef *)&(CAN_MO->MO[115])) +#define CAN_MO116 ((CAN_MO_TypeDef *)&(CAN_MO->MO[116])) +#define CAN_MO117 ((CAN_MO_TypeDef *)&(CAN_MO->MO[117])) +#define CAN_MO118 ((CAN_MO_TypeDef *)&(CAN_MO->MO[118])) +#define CAN_MO119 ((CAN_MO_TypeDef *)&(CAN_MO->MO[119])) +#define CAN_MO120 ((CAN_MO_TypeDef *)&(CAN_MO->MO[120])) +#define CAN_MO121 ((CAN_MO_TypeDef *)&(CAN_MO->MO[121])) +#define CAN_MO122 ((CAN_MO_TypeDef *)&(CAN_MO->MO[122])) +#define CAN_MO123 ((CAN_MO_TypeDef *)&(CAN_MO->MO[123])) +#define CAN_MO124 ((CAN_MO_TypeDef *)&(CAN_MO->MO[124])) +#define CAN_MO125 ((CAN_MO_TypeDef *)&(CAN_MO->MO[125])) +#define CAN_MO126 ((CAN_MO_TypeDef *)&(CAN_MO->MO[126])) +#define CAN_MO127 ((CAN_MO_TypeDef *)&(CAN_MO->MO[127])) +#define CAN_MO128 ((CAN_MO_TypeDef *)&(CAN_MO->MO[128])) +#define CAN_MO129 ((CAN_MO_TypeDef *)&(CAN_MO->MO[129])) +#define CAN_MO130 ((CAN_MO_TypeDef *)&(CAN_MO->MO[130])) +#define CAN_MO131 ((CAN_MO_TypeDef *)&(CAN_MO->MO[131])) +#define CAN_MO132 ((CAN_MO_TypeDef *)&(CAN_MO->MO[132])) +#define CAN_MO133 ((CAN_MO_TypeDef *)&(CAN_MO->MO[133])) +#define CAN_MO134 ((CAN_MO_TypeDef *)&(CAN_MO->MO[134])) +#define CAN_MO135 ((CAN_MO_TypeDef *)&(CAN_MO->MO[135])) +#define CAN_MO136 ((CAN_MO_TypeDef *)&(CAN_MO->MO[136])) +#define CAN_MO137 ((CAN_MO_TypeDef *)&(CAN_MO->MO[137])) +#define CAN_MO138 ((CAN_MO_TypeDef *)&(CAN_MO->MO[138])) +#define CAN_MO139 ((CAN_MO_TypeDef *)&(CAN_MO->MO[139])) +#define CAN_MO140 ((CAN_MO_TypeDef *)&(CAN_MO->MO[140])) +#define CAN_MO141 ((CAN_MO_TypeDef *)&(CAN_MO->MO[141])) +#define CAN_MO142 ((CAN_MO_TypeDef *)&(CAN_MO->MO[142])) +#define CAN_MO143 ((CAN_MO_TypeDef *)&(CAN_MO->MO[143])) +#define CAN_MO144 ((CAN_MO_TypeDef *)&(CAN_MO->MO[144])) +#define CAN_MO145 ((CAN_MO_TypeDef *)&(CAN_MO->MO[145])) +#define CAN_MO146 ((CAN_MO_TypeDef *)&(CAN_MO->MO[146])) +#define CAN_MO147 ((CAN_MO_TypeDef *)&(CAN_MO->MO[147])) +#define CAN_MO148 ((CAN_MO_TypeDef *)&(CAN_MO->MO[148])) +#define CAN_MO149 ((CAN_MO_TypeDef *)&(CAN_MO->MO[149])) +#define CAN_MO150 ((CAN_MO_TypeDef *)&(CAN_MO->MO[150])) +#define CAN_MO151 ((CAN_MO_TypeDef *)&(CAN_MO->MO[151])) +#define CAN_MO152 ((CAN_MO_TypeDef *)&(CAN_MO->MO[152])) +#define CAN_MO153 ((CAN_MO_TypeDef *)&(CAN_MO->MO[153])) +#define CAN_MO154 ((CAN_MO_TypeDef *)&(CAN_MO->MO[154])) +#define CAN_MO155 ((CAN_MO_TypeDef *)&(CAN_MO->MO[155])) +#define CAN_MO156 ((CAN_MO_TypeDef *)&(CAN_MO->MO[156])) +#define CAN_MO157 ((CAN_MO_TypeDef *)&(CAN_MO->MO[157])) +#define CAN_MO158 ((CAN_MO_TypeDef *)&(CAN_MO->MO[158])) +#define CAN_MO159 ((CAN_MO_TypeDef *)&(CAN_MO->MO[159])) +#define CAN_MO160 ((CAN_MO_TypeDef *)&(CAN_MO->MO[160])) +#define CAN_MO161 ((CAN_MO_TypeDef *)&(CAN_MO->MO[161])) +#define CAN_MO162 ((CAN_MO_TypeDef *)&(CAN_MO->MO[162])) +#define CAN_MO163 ((CAN_MO_TypeDef *)&(CAN_MO->MO[163])) +#define CAN_MO164 ((CAN_MO_TypeDef *)&(CAN_MO->MO[164])) +#define CAN_MO165 ((CAN_MO_TypeDef *)&(CAN_MO->MO[165])) +#define CAN_MO166 ((CAN_MO_TypeDef *)&(CAN_MO->MO[166])) +#define CAN_MO167 ((CAN_MO_TypeDef *)&(CAN_MO->MO[167])) +#define CAN_MO168 ((CAN_MO_TypeDef *)&(CAN_MO->MO[168])) +#define CAN_MO169 ((CAN_MO_TypeDef *)&(CAN_MO->MO[169])) +#define CAN_MO170 ((CAN_MO_TypeDef *)&(CAN_MO->MO[170])) +#define CAN_MO171 ((CAN_MO_TypeDef *)&(CAN_MO->MO[171])) +#define CAN_MO172 ((CAN_MO_TypeDef *)&(CAN_MO->MO[172])) +#define CAN_MO173 ((CAN_MO_TypeDef *)&(CAN_MO->MO[173])) +#define CAN_MO174 ((CAN_MO_TypeDef *)&(CAN_MO->MO[174])) +#define CAN_MO175 ((CAN_MO_TypeDef *)&(CAN_MO->MO[175])) +#define CAN_MO176 ((CAN_MO_TypeDef *)&(CAN_MO->MO[176])) +#define CAN_MO177 ((CAN_MO_TypeDef *)&(CAN_MO->MO[177])) +#define CAN_MO178 ((CAN_MO_TypeDef *)&(CAN_MO->MO[178])) +#define CAN_MO179 ((CAN_MO_TypeDef *)&(CAN_MO->MO[179])) +#define CAN_MO180 ((CAN_MO_TypeDef *)&(CAN_MO->MO[180])) +#define CAN_MO181 ((CAN_MO_TypeDef *)&(CAN_MO->MO[181])) +#define CAN_MO182 ((CAN_MO_TypeDef *)&(CAN_MO->MO[182])) +#define CAN_MO183 ((CAN_MO_TypeDef *)&(CAN_MO->MO[183])) +#define CAN_MO184 ((CAN_MO_TypeDef *)&(CAN_MO->MO[184])) +#define CAN_MO185 ((CAN_MO_TypeDef *)&(CAN_MO->MO[185])) +#define CAN_MO186 ((CAN_MO_TypeDef *)&(CAN_MO->MO[186])) +#define CAN_MO187 ((CAN_MO_TypeDef *)&(CAN_MO->MO[187])) +#define CAN_MO188 ((CAN_MO_TypeDef *)&(CAN_MO->MO[188])) +#define CAN_MO189 ((CAN_MO_TypeDef *)&(CAN_MO->MO[189])) +#define CAN_MO190 ((CAN_MO_TypeDef *)&(CAN_MO->MO[190])) +#define CAN_MO191 ((CAN_MO_TypeDef *)&(CAN_MO->MO[191])) +#define CAN_MO192 ((CAN_MO_TypeDef *)&(CAN_MO->MO[192])) +#define CAN_MO193 ((CAN_MO_TypeDef *)&(CAN_MO->MO[193])) +#define CAN_MO194 ((CAN_MO_TypeDef *)&(CAN_MO->MO[194])) +#define CAN_MO195 ((CAN_MO_TypeDef *)&(CAN_MO->MO[195])) +#define CAN_MO196 ((CAN_MO_TypeDef *)&(CAN_MO->MO[196])) +#define CAN_MO197 ((CAN_MO_TypeDef *)&(CAN_MO->MO[197])) +#define CAN_MO198 ((CAN_MO_TypeDef *)&(CAN_MO->MO[198])) +#define CAN_MO199 ((CAN_MO_TypeDef *)&(CAN_MO->MO[199])) +#define CAN_MO200 ((CAN_MO_TypeDef *)&(CAN_MO->MO[200])) +#define CAN_MO201 ((CAN_MO_TypeDef *)&(CAN_MO->MO[201])) +#define CAN_MO202 ((CAN_MO_TypeDef *)&(CAN_MO->MO[202])) +#define CAN_MO203 ((CAN_MO_TypeDef *)&(CAN_MO->MO[203])) +#define CAN_MO204 ((CAN_MO_TypeDef *)&(CAN_MO->MO[204])) +#define CAN_MO205 ((CAN_MO_TypeDef *)&(CAN_MO->MO[205])) +#define CAN_MO206 ((CAN_MO_TypeDef *)&(CAN_MO->MO[206])) +#define CAN_MO207 ((CAN_MO_TypeDef *)&(CAN_MO->MO[207])) +#define CAN_MO208 ((CAN_MO_TypeDef *)&(CAN_MO->MO[208])) +#define CAN_MO209 ((CAN_MO_TypeDef *)&(CAN_MO->MO[209])) +#define CAN_MO210 ((CAN_MO_TypeDef *)&(CAN_MO->MO[210])) +#define CAN_MO211 ((CAN_MO_TypeDef *)&(CAN_MO->MO[211])) +#define CAN_MO212 ((CAN_MO_TypeDef *)&(CAN_MO->MO[212])) +#define CAN_MO213 ((CAN_MO_TypeDef *)&(CAN_MO->MO[213])) +#define CAN_MO214 ((CAN_MO_TypeDef *)&(CAN_MO->MO[214])) +#define CAN_MO215 ((CAN_MO_TypeDef *)&(CAN_MO->MO[215])) +#define CAN_MO216 ((CAN_MO_TypeDef *)&(CAN_MO->MO[216])) +#define CAN_MO217 ((CAN_MO_TypeDef *)&(CAN_MO->MO[217])) +#define CAN_MO218 ((CAN_MO_TypeDef *)&(CAN_MO->MO[218])) +#define CAN_MO219 ((CAN_MO_TypeDef *)&(CAN_MO->MO[219])) +#define CAN_MO220 ((CAN_MO_TypeDef *)&(CAN_MO->MO[220])) +#define CAN_MO221 ((CAN_MO_TypeDef *)&(CAN_MO->MO[221])) +#define CAN_MO222 ((CAN_MO_TypeDef *)&(CAN_MO->MO[222])) +#define CAN_MO223 ((CAN_MO_TypeDef *)&(CAN_MO->MO[223])) +#define CAN_MO224 ((CAN_MO_TypeDef *)&(CAN_MO->MO[224])) +#define CAN_MO225 ((CAN_MO_TypeDef *)&(CAN_MO->MO[225])) +#define CAN_MO226 ((CAN_MO_TypeDef *)&(CAN_MO->MO[226])) +#define CAN_MO227 ((CAN_MO_TypeDef *)&(CAN_MO->MO[227])) +#define CAN_MO228 ((CAN_MO_TypeDef *)&(CAN_MO->MO[228])) +#define CAN_MO229 ((CAN_MO_TypeDef *)&(CAN_MO->MO[229])) +#define CAN_MO230 ((CAN_MO_TypeDef *)&(CAN_MO->MO[230])) +#define CAN_MO231 ((CAN_MO_TypeDef *)&(CAN_MO->MO[231])) +#define CAN_MO232 ((CAN_MO_TypeDef *)&(CAN_MO->MO[232])) +#define CAN_MO233 ((CAN_MO_TypeDef *)&(CAN_MO->MO[233])) +#define CAN_MO234 ((CAN_MO_TypeDef *)&(CAN_MO->MO[234])) +#define CAN_MO235 ((CAN_MO_TypeDef *)&(CAN_MO->MO[235])) +#define CAN_MO236 ((CAN_MO_TypeDef *)&(CAN_MO->MO[236])) +#define CAN_MO237 ((CAN_MO_TypeDef *)&(CAN_MO->MO[237])) +#define CAN_MO238 ((CAN_MO_TypeDef *)&(CAN_MO->MO[238])) +#define CAN_MO239 ((CAN_MO_TypeDef *)&(CAN_MO->MO[239])) +#define CAN_MO240 ((CAN_MO_TypeDef *)&(CAN_MO->MO[240])) +#define CAN_MO241 ((CAN_MO_TypeDef *)&(CAN_MO->MO[241])) +#define CAN_MO242 ((CAN_MO_TypeDef *)&(CAN_MO->MO[242])) +#define CAN_MO243 ((CAN_MO_TypeDef *)&(CAN_MO->MO[243])) +#define CAN_MO244 ((CAN_MO_TypeDef *)&(CAN_MO->MO[244])) +#define CAN_MO245 ((CAN_MO_TypeDef *)&(CAN_MO->MO[245])) +#define CAN_MO246 ((CAN_MO_TypeDef *)&(CAN_MO->MO[246])) +#define CAN_MO247 ((CAN_MO_TypeDef *)&(CAN_MO->MO[247])) +#define CAN_MO248 ((CAN_MO_TypeDef *)&(CAN_MO->MO[248])) +#define CAN_MO249 ((CAN_MO_TypeDef *)&(CAN_MO->MO[249])) +#define CAN_MO250 ((CAN_MO_TypeDef *)&(CAN_MO->MO[250])) +#define CAN_MO251 ((CAN_MO_TypeDef *)&(CAN_MO->MO[251])) +#define CAN_MO252 ((CAN_MO_TypeDef *)&(CAN_MO->MO[252])) +#define CAN_MO253 ((CAN_MO_TypeDef *)&(CAN_MO->MO[253])) +#define CAN_MO254 ((CAN_MO_TypeDef *)&(CAN_MO->MO[254])) +#define CAN_MO255 ((CAN_MO_TypeDef *)&(CAN_MO->MO[255])) +#endif +#endif + +#endif /* XMC_CAN_MAP_H*/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ccu4.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ccu4.h new file mode 100644 index 00000000..5d5c02c8 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ccu4.h @@ -0,0 +1,2386 @@ +/** + * @file xmc_ccu4.h + * @date 2016-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Documentation updates
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-07-22: + * - XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
+ * + * 2015-08-17: + * - XMC_CCU4_SLICE_PRESCALER_t enum is added to set the prescaler divider.
+ * - XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t enum item names are updated according to the guidelines.
+ * - XMC_CCU4_EnableShadowTransfer() API is made as inline, to improve the speed.
+ * + * 2015-09-29: + * - In XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t, two more enum items are added to support external count direction + * settings. + * + * 2015-10-07: + * - XMC_CCU4_SLICE_GetEvent() is made as inline. + * - XMC_CCU4_SLICE_MULTI_IRQ_ID_t is added to support the XMC_CCU4_SLICE_EnableMultipleEvents() and + * XMC_CCU4_SLICE_DisableMultipleEvents() APIs. + * - DOC updates for the newly added APIs. + * + * 2016-03-09: + * - Optimization of write only registers + * + * 2016-05-20: + * - Added XMC_CCU4_SLICE_StopClearTimer() + * - Changed implementation of XMC_CCU4_SLICE_StopTimer() and XMC_CCU4_SLICE_ClearTimer() to avoid RMW access + * + * @endcond + */ + +#ifndef XMC_CCU4_H +#define XMC_CCU4_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_common.h" +#if defined(CCU40) + +#if UC_FAMILY == XMC1 + #include "xmc1_ccu4_map.h" +#endif + +#if UC_FAMILY == XMC4 + #include "xmc4_ccu4_map.h" +#endif + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup CCU4 + * @brief Capture Compare Unit 4 (CCU4) low level driver for XMC family of microcontrollers
+ * + * The CCU4 peripheral is a major component for systems that need general purpose timers for signal + * monitoring/conditioning and Pulse Width Modulation (PWM) signal generation. Power electronic control systems like + * switched mode power supplies or interruptible power supplies, can easily be implemented with the functions inside the + * CCU4 peripheral.\n + * Each CCU4 module is comprised of four identical 16 bit Capture/Compare Timer slices, CC4y (where y = [0..4]). Each + * timer slice can work in compare mode or in capture mode. + * + * APIs provided in this file cover the following functional blocks of CCU4:\n + * -- Timer configuration, Capture configuration, Function/Event configuration, Interrupt configuration\n + * \par Note: + * 1. SLICE (APIs prefixed with e.g. XMC_CCU4_SLICE_) + * 2. Module (APIs are not having any prefix e.g. XMC_CCU4_) + * + * \par Timer(Compare mode) configuration: + * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_COMPARE_CONFIG_t and the initialization + * function XMC_CCU4_SLICE_CompareInit(). + * + * It can be used to: + * -# Start and Stop the timer. (XMC_CCU4_SLICE_StartTimer(), XMC_CCU4_SLICE_StopTimer()) + * -# Update the period, compare, Dither, Prescaler and Passive values. (XMC_CCU4_SLICE_SetTimerPeriodMatch(), + * XMC_CCU4_SLICE_SetTimerCompareMatch(), XMC_CCU4_SLICE_SetPrescaler(), XMC_CCU4_SLICE_SetDitherCompareValue(), + * XMC_CCU4_SLICE_SetPassiveLevel()) + * -# Enable the slices to support multichannel mode. (XMC_CCU4_SLICE_EnableMultiChannelMode()) + * + * \par Capture configuration: + * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_CAPTURE_CONFIG_t and the initialization + * function XMC_CCU4_SLICE_CaptureInit(). + * + * It can be used to: + * -# Configure the capture functionality. (XMC_CCU4_SLICE_Capture0Config(), XMC_CCU4_SLICE_Capture1Config()) + * -# Read the captured values along with the status, which indicate the value is latest or not. + * (XMC_CCU4_SLICE_GetCaptureRegisterValue()) + * + * \par Function/Event configuration: + * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_EVENT_CONFIG_t.\n + * + * It can be used to: + * -# Enable and Disable the events. (XMC_CCU4_SLICE_EnableEvent(), XMC_CCU4_SLICE_DisableEvent()) + * -# Configure to start and stop the timer on external events.(XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_StopConfig()) + * -# Modulation, external load and Gating of the timer output.(XMC_CCU4_SLICE_ModulationConfig(), + * XMC_CCU4_SLICE_LoadConfig(), XMC_CCU4_SLICE_GateConfig()) + * -# Control the count direction of the timer based on the external event. (XMC_CCU4_SLICE_DirectionConfig()) + * -# Count the external events.(XMC_CCU4_SLICE_CountConfig()) + * -# External Trap. Which can be used as protective feature.(XMC_CCU4_SLICE_EnableTrap(), XMC_CCU4_SLICE_DisableTrap(), + * XMC_CCU4_SLICE_TrapConfig()) + * + * \par Interrupt configuration: + * This section of the LLD provides the function to configure the interrupt node to each event (XMC_CCU4_SLICE_SetInterruptNode()) + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +/* Macro to check if the interrupt enum passed is valid */ +#define XMC_CCU4_SLICE_CHECK_INTERRUPT(interrupt) \ + ((interrupt == XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN)|| \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT0) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT1) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT2) || \ + (interrupt == XMC_CCU4_SLICE_IRQ_ID_TRAP)) + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/** + * Typedef for CCU4 Global data structure + */ +typedef CCU4_GLOBAL_TypeDef XMC_CCU4_MODULE_t; + +/** + * Typedef for CCU4 Slice data structure + */ +typedef CCU4_CC4_TypeDef XMC_CCU4_SLICE_t; + +/** + * Return Value of an API + */ +typedef enum XMC_CCU4_STATUS +{ + XMC_CCU4_STATUS_OK = 0U, /**< API fulfils request */ + XMC_CCU4_STATUS_ERROR , /**< API cannot fulfil the request */ + XMC_CCU4_STATUS_RUNNING , /**< The timer slice is currently running */ + XMC_CCU4_STATUS_IDLE /**< The timer slice is currently idle */ +} XMC_CCU4_STATUS_t; + +/** + * CCU4 module clock + */ +typedef enum XMC_CCU4_CLOCK +{ + XMC_CCU4_CLOCK_SCU = 0U, /**< Select the fCCU as the clock */ + XMC_CCU4_CLOCK_EXTERNAL_A , /**< External clock-A */ + XMC_CCU4_CLOCK_EXTERNAL_B , /**< External clock-B */ + XMC_CCU4_CLOCK_EXTERNAL_C /**< External clock-C */ +} XMC_CCU4_CLOCK_t; + +/** + * CCU4 set the shadow transfer type for multichannel mode + */ +typedef enum XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER +{ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0 = (uint32_t)0x4000000, /**< Shadow transfer through software + only for slice 0*/ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0 = (uint32_t)0x4000400, /**< Shadow transfer through software + and hardware for slice 0 */ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1 = (uint32_t)0x8000000, /**< Shadow transfer through software + only for slice 1*/ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1 = (uint32_t)0x8000800, /**< Shadow transfer through software + and hardware for slice 1 */ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2 = (uint32_t)0x10000000, /**< Shadow transfer through software + only for slice 2 */ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE2 = (uint32_t)0x10001000, /**< Shadow transfer through software + and hardware for slice 2 */ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE3 = (uint32_t)0x20000000, /**< Shadow transfer through software + only for slice 3*/ + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE3 = (uint32_t)0x20002000 /**< Shadow transfer through software + and hardware for slice 3 */ +} XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_t; + +/** + * Operational modes of CCU4 slice + */ +typedef enum XMC_CCU4_SLICE_MODE +{ + XMC_CCU4_SLICE_MODE_COMPARE = 0U, /**< slice(CC4y) operates in Compare Mode */ + XMC_CCU4_SLICE_MODE_CAPTURE /**< slice(CC4y) operates in Capture Mode */ +} XMC_CCU4_SLICE_MODE_t; + +/** + * Timer counting modes for the slice + */ +typedef enum XMC_CCU4_SLICE_TIMER_COUNT_MODE +{ + XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA = 0U, /**< Edge Aligned Mode */ + XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA /**< Center Aligned Mode */ +} XMC_CCU4_SLICE_TIMER_COUNT_MODE_t; + +/** + * Timer repetition mode for the slice + */ +typedef enum XMC_CCU4_SLICE_TIMER_REPEAT_MODE +{ + XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT = 0U, /**< Repetitive mode: continuous mode of operation */ + XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE /**< Single shot mode: Once a Period match/One match + occurs timer goes to idle state */ +} XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t; + +/** + * Timer counting direction for the CCU4 slice + */ +typedef enum XMC_CCU4_SLICE_TIMER_COUNT_DIR +{ + XMC_CCU4_SLICE_TIMER_COUNT_DIR_UP = 0U, /**< Counting up */ + XMC_CCU4_SLICE_TIMER_COUNT_DIR_DOWN /**< Counting down */ +} XMC_CCU4_SLICE_TIMER_COUNT_DIR_t; + +/** + * Capture mode register sets + */ +typedef enum XMC_CCU4_SLICE_CAP_REG_SET +{ + XMC_CCU4_SLICE_CAP_REG_SET_LOW = 0U, /**< Capture register-0, Capture register-1 used */ + XMC_CCU4_SLICE_CAP_REG_SET_HIGH /**< Capture register-2, Capture register-3 used */ +} XMC_CCU4_SLICE_CAP_REG_SET_t; + +/** + * Prescaler mode + */ +typedef enum XMC_CCU4_SLICE_PRESCALER_MODE +{ + XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL = 0U, /**< Fixed division of module clock */ + XMC_CCU4_SLICE_PRESCALER_MODE_FLOAT /**< Floating divider. */ +} XMC_CCU4_SLICE_PRESCALER_MODE_t; + +/** + * Timer output passive level + */ +typedef enum XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL +{ + XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW = 0U, /**< Passive level = Low */ + XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH /**< Passive level = High */ +} XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t; + +/** + * Timer clock Divider + */ +typedef enum XMC_CCU4_SLICE_PRESCALER +{ + XMC_CCU4_SLICE_PRESCALER_1 = 0U, /**< Slice Clock = fccu4 */ + XMC_CCU4_SLICE_PRESCALER_2 , /**< Slice Clock = fccu4/2 */ + XMC_CCU4_SLICE_PRESCALER_4 , /**< Slice Clock = fccu4/4 */ + XMC_CCU4_SLICE_PRESCALER_8 , /**< Slice Clock = fccu4/8 */ + XMC_CCU4_SLICE_PRESCALER_16 , /**< Slice Clock = fccu4/16 */ + XMC_CCU4_SLICE_PRESCALER_32 , /**< Slice Clock = fccu4/32 */ + XMC_CCU4_SLICE_PRESCALER_64 , /**< Slice Clock = fccu4/64 */ + XMC_CCU4_SLICE_PRESCALER_128 , /**< Slice Clock = fccu4/128 */ + XMC_CCU4_SLICE_PRESCALER_256 , /**< Slice Clock = fccu4/256 */ + XMC_CCU4_SLICE_PRESCALER_512 , /**< Slice Clock = fccu4/512 */ + XMC_CCU4_SLICE_PRESCALER_1024 , /**< Slice Clock = fccu4/1024 */ + XMC_CCU4_SLICE_PRESCALER_2048 , /**< Slice Clock = fccu4/2048 */ + XMC_CCU4_SLICE_PRESCALER_4096 , /**< Slice Clock = fccu4/4096 */ + XMC_CCU4_SLICE_PRESCALER_8192 , /**< Slice Clock = fccu4/8192 */ + XMC_CCU4_SLICE_PRESCALER_16384 , /**< Slice Clock = fccu4/16384 */ + XMC_CCU4_SLICE_PRESCALER_32768 /**< Slice Clock = fccu4/32768 */ +} XMC_CCU4_SLICE_PRESCALER_t; + +/** + * External Function list + */ +typedef enum XMC_CCU4_SLICE_FUNCTION +{ + XMC_CCU4_SLICE_FUNCTION_START = 0U, /**< Start function */ + XMC_CCU4_SLICE_FUNCTION_STOP , /**< Stop function */ + XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT0 , /**< Capture Event-0 function, CCycapt0 signal is used for event + generation */ + XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT1 , /**< Capture Event-1 function, CCycapt1 signal is used for event + generation */ + XMC_CCU4_SLICE_FUNCTION_GATING , /**< Gating function */ + XMC_CCU4_SLICE_FUNCTION_DIRECTION , /**< Direction function */ + XMC_CCU4_SLICE_FUNCTION_LOAD , /**< Load function */ + XMC_CCU4_SLICE_FUNCTION_COUNT , /**< Counting function */ + XMC_CCU4_SLICE_FUNCTION_OVERRIDE , /**< Override function */ + XMC_CCU4_SLICE_FUNCTION_MODULATION , /**< Modulation function */ + XMC_CCU4_SLICE_FUNCTION_TRAP /**< Trap function */ +} XMC_CCU4_SLICE_FUNCTION_t; + +/** + * External Event list + */ +typedef enum XMC_CCU4_SLICE_EVENT +{ + XMC_CCU4_SLICE_EVENT_NONE = 0U, /**< None */ + XMC_CCU4_SLICE_EVENT_0 , /**< Event-0 */ + XMC_CCU4_SLICE_EVENT_1 , /**< Event-1 */ + XMC_CCU4_SLICE_EVENT_2 /**< Event-2 */ +} XMC_CCU4_SLICE_EVENT_t; + +/** + * External Event trigger criteria - Edge sensitivity + */ +typedef enum XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY +{ + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE = 0U, /**< None */ + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE , /**< Rising Edge of the input signal generates event trigger*/ + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE , /**< Falling Edge of the input signal generates event + trigger */ + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE /**< Both Rising and Falling edges cause an event trigger*/ +} XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t; + +/** + * External Event trigger criteria - Level sensitivity + */ +typedef enum XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY +{ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH = 0U, /**< Level sensitive functions react to a high signal level*/ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW = 1U, /**< Level sensitive functions react to a low signal level*/ + /* Below enum items can be utilised specific to the functionality */ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW = 0U, /**< Timer counts up, during Low state of the control signal */ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH = 1U /**< Timer counts up, during High state of the control signal */ +} XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t; + +/** + * Low pass filter Configuration. The External Event input should be stable for a selected number of clock cycles. + */ +typedef enum XMC_CCU4_SLICE_EVENT_FILTER +{ + XMC_CCU4_SLICE_EVENT_FILTER_DISABLED = 0U, /**< No Low Pass Filter */ + XMC_CCU4_SLICE_EVENT_FILTER_3_CYCLES , /**< 3 clock cycles */ + XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES , /**< 5 clock cycles */ + XMC_CCU4_SLICE_EVENT_FILTER_7_CYCLES /**< 7 clock cycles */ +} XMC_CCU4_SLICE_EVENT_FILTER_t; + +/** + * External Event Input list. This list depicts the possible input connections to the CCU4 slice. + * Interconnects are specific to each device. + */ +typedef uint8_t XMC_CCU4_SLICE_INPUT_t; + +/** + * Actions that can be performed upon detection of an external Timer STOP event + */ +typedef enum XMC_CCU4_SLICE_END_MODE +{ + XMC_CCU4_SLICE_END_MODE_TIMER_STOP = 0U, /**< Stops the timer, without clearing TIMER register */ + XMC_CCU4_SLICE_END_MODE_TIMER_CLEAR , /**< Without stopping timer, clears the TIMER register */ + XMC_CCU4_SLICE_END_MODE_TIMER_STOP_CLEAR /**< Stops the timer and clears the TIMER register */ +} XMC_CCU4_SLICE_END_MODE_t; + +/** + * Actions that can be performed upon detection of an external Timer START event + */ +typedef enum XMC_CCU4_SLICE_START_MODE +{ + XMC_CCU4_SLICE_START_MODE_TIMER_START = 0U, /**< Start the timer from the current count of TIMER register */ + XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR /**< Clears the TIMER register and start the timer */ +} XMC_CCU4_SLICE_START_MODE_t; + +/** + * Modulation of timer output signals + */ +typedef enum XMC_CCU4_SLICE_MODULATION_MODE +{ + XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_ST_OUT = 0U, /**< Clear ST and OUT signals */ + XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT /**< Clear only the OUT signal */ +} XMC_CCU4_SLICE_MODULATION_MODE_t; + +/** + * Trap exit mode + */ +typedef enum XMC_CCU4_SLICE_TRAP_EXIT_MODE +{ + XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC = 0U, /**< Clear trap state as soon as the trap signal is de-asserted */ + XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW /**< Clear only when acknowledged by software */ +} XMC_CCU4_SLICE_TRAP_EXIT_MODE_t; + +/** + * Timer clear on capture + */ +typedef enum XMC_CCU4_SLICE_TIMER_CLEAR_MODE +{ + XMC_CCU4_SLICE_TIMER_CLEAR_MODE_NEVER = 0U, /**< Never clear the timer on any capture event */ + XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_HIGH , /**< Clear only when timer value has been captured in C3V and C2V */ + XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_LOW , /**< Clear only when timer value has been captured in C1V and C0V */ + XMC_CCU4_SLICE_TIMER_CLEAR_MODE_ALWAYS /**< Always clear the timer upon detection of any capture event */ +} XMC_CCU4_SLICE_TIMER_CLEAR_MODE_t; + +/** + * Multi Channel Shadow transfer request configuration options + */ +typedef enum XMC_CCU4_SLICE_MCMS_ACTION +{ + XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR = 0U, /**< Transfer Compare and Period Shadow register values to + the actual registers upon MCS xfer request */ + XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP = 1U, /**< Transfer Compare, Period and Prescaler Compare Shadow + register values to the actual registers upon MCS xfer + request */ + XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT = 3U /**< Transfer Compare, Period ,Prescaler Compare and Dither + Compare register values to the actual registers upon + MCS xfer request */ +} XMC_CCU4_SLICE_MCMS_ACTION_t; + +/** + * Available Interrupt Event Ids + */ +typedef enum XMC_CCU4_SLICE_IRQ_ID +{ + XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH = 0U , /**< Period match counting up */ + XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH = 1U , /**< Period match -> One match counting down */ + XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP = 2U , /**< Compare match counting up */ + XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN = 3U , /**< Compare match counting down */ + XMC_CCU4_SLICE_IRQ_ID_EVENT0 = 8U , /**< Event-0 occurrence */ + XMC_CCU4_SLICE_IRQ_ID_EVENT1 = 9U , /**< Event-1 occurrence */ + XMC_CCU4_SLICE_IRQ_ID_EVENT2 = 10U, /**< Event-2 occurrence */ + XMC_CCU4_SLICE_IRQ_ID_TRAP = 11U /**< Trap occurrence */ +} XMC_CCU4_SLICE_IRQ_ID_t; + +/** + * Available Interrupt Event Ids, which is added to support multi event APIs + */ +typedef enum XMC_CCU4_SLICE_MULTI_IRQ_ID +{ + XMC_CCU4_SLICE_MULTI_IRQ_ID_PERIOD_MATCH = 0x1U, /**< Period match counting up */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_ONE_MATCH = 0x2U, /**< Period match -> One match counting down */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP = 0x4U, /**< Compare match counting up */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN = 0x8U, /**< Compare match counting down */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT0 = 0x100U, /**< Event-0 occurrence */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT1 = 0x200U, /**< Event-1 occurrence */ + XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT2 = 0x400U, /**< Event-2 occurrence */ +} XMC_CCU4_SLICE_MULTI_IRQ_ID_t; + +/** + * Service Request Lines for CCU4. Event are mapped to these SR lines and these are used to generate the interrupt. + */ +typedef enum XMC_CCU4_SLICE_SR_ID +{ + XMC_CCU4_SLICE_SR_ID_0 = 0U, /**< Service Request Line-0 selected */ + XMC_CCU4_SLICE_SR_ID_1 , /**< Service Request Line-1 selected */ + XMC_CCU4_SLICE_SR_ID_2 , /**< Service Request Line-2 selected */ + XMC_CCU4_SLICE_SR_ID_3 /**< Service Request Line-3 selected */ +} XMC_CCU4_SLICE_SR_ID_t; + +/** + * Slice shadow transfer options. + */ +typedef enum XMC_CCU4_SHADOW_TRANSFER +{ + XMC_CCU4_SHADOW_TRANSFER_SLICE_0 = CCU4_GCSS_S0SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-0 */ + XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_0 = CCU4_GCSS_S0DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-0 */ + XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_0 = CCU4_GCSS_S0PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-0 */ + XMC_CCU4_SHADOW_TRANSFER_SLICE_1 = CCU4_GCSS_S1SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-1 */ + XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_1 = CCU4_GCSS_S1DSE_Msk, /**< Transfer Dither compare shadow register value + to actual registers for SLICE-1 */ + XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_1 = CCU4_GCSS_S1PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-1 */ + XMC_CCU4_SHADOW_TRANSFER_SLICE_2 = CCU4_GCSS_S2SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-2 */ + XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_2 = CCU4_GCSS_S2DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-2 */ + XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_2 = CCU4_GCSS_S2PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-2 */ + XMC_CCU4_SHADOW_TRANSFER_SLICE_3 = CCU4_GCSS_S3SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-3 */ + XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_3 = CCU4_GCSS_S3DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-3 */ + XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_3 = CCU4_GCSS_S3PSE_Msk /**< Transfer Prescaler shadow register value to + actual register for SLICE-3 */ +} XMC_CCU4_SHADOW_TRANSFER_t; + +#if defined(CCU4V3) || defined(DOXYGEN)/* Defined for XMC1400 devices only */ +/** + * Slice shadow transfer mode options. + * @note Only available for XMC1400 series + */ +typedef enum XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE +{ + XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_IN_PERIOD_MATCH_AND_ONE_MATCH = 0U, /**< Shadow transfer is done in Period Match and + One match. */ + XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH = 1U, /**< Shadow transfer is done only in Period Match. */ + XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_ONE_MATCH = 2U /**< Shadow transfer is done only in One Match. */ +} XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t; + + +/** + * Immediate write into configuration register + * @note Only available for XMC1400 series + */ +typedef enum XMC_CCU4_SLICE_WRITE_INTO +{ + XMC_CCU4_SLICE_WRITE_INTO_PERIOD_CONFIGURATION = CCU4_CC4_STC_IRPC_Msk, /**< Immediate or Coherent + Write into Period + Configuration */ + XMC_CCU4_SLICE_WRITE_INTO_COMPARE_CONFIGURATION = CCU4_CC4_STC_IRCC_Msk, /**< Immediate or Coherent + Write into Compare + Configuration */ + XMC_CCU4_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION = CCU4_CC4_STC_IRLC_Msk, /**< Immediate or Coherent + Write into Passive Level + Configuration */ + XMC_CCU4_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRDC_Msk, /**< Immediate or Coherent + Write into Dither Value + Configuration */ + XMC_CCU4_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRFC_Msk /**< Immediate or Coherent + Write into Floating Prescaler + Value Configuration */ +} XMC_CCU4_SLICE_WRITE_INTO_t; + + +/** + * Automatic Shadow Transfer request when writing into shadow register + * @note Only available for XMC1400 series + */ +typedef enum XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO +{ + XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PERIOD_SHADOW = CCU4_CC4_STC_ASPC_Msk, /**< Automatic Shadow + Transfer request when + writing into Period + Shadow Register */ + XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_COMPARE_SHADOW = CCU4_CC4_STC_ASCC_Msk, /**< Automatic Shadow + transfer request + when writing into + Compare Shadow Register */ + XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PASSIVE_LEVEL = CCU4_CC4_STC_ASLC_Msk, /**< Automatic Shadow transfer + request when writing + into Passive Level Register*/ + XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_DITHER_SHADOW = CCU4_CC4_STC_ASDC_Msk, /**< Automatic Shadow transfer + request when writing + into Dither Shadow Register */ + XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_FLOATING_PRESCALER_SHADOW = CCU4_CC4_STC_ASFC_Msk /**< Automatic Shadow transfer + request when writing + into Floating Prescaler Shadow + register */ + +} XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t; +#endif +/** + * Used to create Mask needed for Multi-channel Shadow transfer enable/disable + */ +typedef enum XMC_CCU4_SLICE_MASK +{ + XMC_CCU4_SLICE_MASK_SLICE_0 = 1U , /**< SLICE-0 */ + XMC_CCU4_SLICE_MASK_SLICE_1 = 2U , /**< SLICE-1 */ + XMC_CCU4_SLICE_MASK_SLICE_2 = 4U , /**< SLICE-2 */ + XMC_CCU4_SLICE_MASK_SLICE_3 = 8U /**< SLICE-3 */ +} XMC_CCU4_SLICE_MASK_t; + + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/** + * Configuration data structure of an External Event(Event-0/1/2). + * Needed to configure the various aspects of an External Event. + * This structure will not connect the external event with an external function. + */ +typedef struct XMC_CCU4_SLICE_EVENT_CONFIG +{ + XMC_CCU4_SLICE_INPUT_t mapped_input; /**< Required input signal for the Event */ + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t edge; /**< Select the event edge of the input signal. + This is needed for an edge sensitive External function.*/ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t level; /**< Select the event level of the input signal. + This is needed for an level sensitive External function.*/ + XMC_CCU4_SLICE_EVENT_FILTER_t duration; /**< Low Pass filter duration in terms of fCCU clock cycles */ +} XMC_CCU4_SLICE_EVENT_CONFIG_t; + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Configuration data structure for CCU4 slice. Specifically configures the CCU4 slice to compare mode operation. + * This excludes event and function configuration. + */ +typedef struct XMC_CCU4_SLICE_COMPARE_CONFIG +{ + union + { + struct + { + uint32_t timer_mode : 1; /**< Edge aligned or Centre Aligned. + Accepts enum ::XMC_CCU4_SLICE_TIMER_COUNT_MODE_t */ + uint32_t monoshot : 1; /**< Single shot or Continuous mode . + Accepts enum :: XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t*/ + uint32_t shadow_xfer_clear : 1; /**< Should PR and CR shadow xfer happen when timer is cleared? */ + uint32_t : 10; + uint32_t dither_timer_period: 1; /**< Can the period of the timer dither? */ + uint32_t dither_duty_cycle : 1; /**< Can the compare match of the timer dither? */ + uint32_t : 1; + uint32_t prescaler_mode: 1; /**< Normal or floating prescaler mode. + Accepts enum :: XMC_CCU4_SLICE_PRESCALER_MODE_t*/ + uint32_t : 8; + uint32_t mcm_enable : 1; /**< Multi-Channel mode enable? */ + uint32_t : 6; + }; + uint32_t tc; + }; + uint32_t prescaler_initval : 4; /**< Initial prescaler divider value + Accepts enum :: XMC_CCU4_SLICE_PRESCALER_t */ + uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to */ + uint32_t dither_limit : 4; /**< The value that determines the spreading of dithering */ + uint32_t passive_level : 1; /**< Configuration of ST and OUT passive levels. + Accepts enum :: XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t*/ + uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer if true.*/ +} XMC_CCU4_SLICE_COMPARE_CONFIG_t; + +/** + * Configuration data structure for CCU4 slice. Specifically configures the CCU4 slice to capture mode operation. + * This excludes event and function configuration. + */ +typedef struct XMC_CCU4_SLICE_CAPTURE_CONFIG +{ + union + { + struct + { + uint32_t : 4; + uint32_t fifo_enable : 1; /**< Should the capture registers be setup as a FIFO?(Extended capture mode)*/ + uint32_t timer_clear_mode : 2; /**< How should the timer register be cleared upon detection of capture event? + Accepts enum ::XMC_CCU4_SLICE_TIMER_CLEAR_MODE_t*/ + uint32_t : 4; + uint32_t same_event : 1; /**< Should the capture event for C1V/C0V and C3V/C2V be same capture edge? */ + uint32_t ignore_full_flag : 1; /**< Should updates to capture registers follow full flag rules? */ + uint32_t : 3; + uint32_t prescaler_mode: 1; /**< Normal or floating prescaler Accepts enum :: XMC_CCU4_SLICE_PRESCALER_MODE_t*/ + uint32_t : 15; + }; + uint32_t tc; + }; + uint32_t prescaler_initval : 4; /**< Prescaler divider value */ + uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to */ + uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer */ +} XMC_CCU4_SLICE_CAPTURE_CONFIG_t; +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +__STATIC_INLINE bool XMC_CCU4_IsValidModule(const XMC_CCU4_MODULE_t *const module) +{ + bool tmp = false; + + tmp = (module == CCU40); + +#if defined(CCU41) + tmp = tmp || (module == CCU41); +#endif + +#if defined(CCU42) + tmp = tmp || (module == CCU42); +#endif + +#if defined(CCU43) + tmp = tmp || (module == CCU43); +#endif + + return tmp; +} + +__STATIC_INLINE bool XMC_CCU4_IsValidSlice(const XMC_CCU4_SLICE_t *const slice) +{ + bool tmp = false; + + tmp = (slice == CCU40_CC40); +#if defined(CCU40_CC41) + tmp = tmp || (slice == CCU40_CC41); +#endif +#if defined(CCU40_CC42) + tmp = tmp || (slice == CCU40_CC42); +#endif +#if defined(CCU40_CC43) + tmp = tmp || (slice == CCU40_CC43); +#endif +#if defined(CCU41) + tmp = tmp || (slice == CCU41_CC40); +#if defined(CCU41_CC41) + tmp = tmp || (slice == CCU41_CC41); +#endif +#if defined(CCU41_CC42) + tmp = tmp || (slice == CCU41_CC42); +#endif +#if defined(CCU41_CC43) + tmp = tmp || (slice == CCU41_CC43); +#endif +#endif +#if defined(CCU42) + tmp = tmp || (slice == CCU42_CC40); +#if defined(CCU42_CC41) + tmp = tmp || (slice == CCU42_CC41); +#endif +#if defined(CCU42_CC42) + tmp = tmp || (slice == CCU42_CC42); +#endif +#if defined(CCU42_CC43) + tmp = tmp || (slice == CCU42_CC43); +#endif +#endif +#if defined(CCU43) + tmp = tmp || (slice == CCU43_CC40); +#if defined(CCU43_CC41) + tmp = tmp || (slice == CCU43_CC41); +#endif +#if defined(CCU43_CC42) + tmp = tmp || (slice == CCU43_CC42); +#endif +#if defined(CCU43_CC43) + tmp = tmp || (slice == CCU43_CC43); +#endif +#endif + + return tmp; +} + +/** + * @param module Constant pointer to CCU4 module + * @param mcs_action multi-channel shadow transfer request configuration + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of global register GCTRL.
\n + * As part of module initialization, behaviour of the module upon detection + * Multi-Channel Mode trigger is configured. Will also invoke the XMC_CCU4_EnableModule(). + * The API call would bring up the required CCU4 module and also initialize the module for + * the required multi-channel shadow transfer. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_CompareInit()
XMC_CCU4_SLICE_CaptureInit(). + */ +void XMC_CCU4_Init(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_SLICE_MCMS_ACTION_t mcs_action); + +/** + * @param module Constant pointer to CCU4 module + * @param clock Choice of input clock to the module + * @return
+ * None
+ * + * \parDescription:
+ * Selects the Module Clock by configuring GCTRL.PCIS bits.
\n + * There are 3 potential clock sources. This API helps to select the required clock source. + * Call to this API is valid after the XMC_CCU4_Init(). + * + * \parRelated APIs:
+ * None.
+ */ +void XMC_CCU4_SetModuleClock(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_CLOCK_t clock); + +/** + * @param module Constant pointer to CCU4 module + * @return
+ * None
+ * + * \parDescription:
+ * Enables the CCU4 module and brings it to active state.
\n + * Also disables the gating of the clock signal (if applicable depending on the device being selected). + * Invoke this API before any operations are done on the CCU4 module. Invoked from XMC_CCU4_Init(). + * + * \parRelated APIs:
+ * XMC_CCU4_SetModuleClock()
XMC_CCU4_DisableModule()
XMC_CCU4_StartPrescaler(). + */ +void XMC_CCU4_EnableModule(XMC_CCU4_MODULE_t *const module); + +/** + * @param module Constant pointer to CCU4 module + * @return
+ * None
+ * + * \parDescription:
+ * Brings the CCU4 module to reset state and enables gating of the clock signal(if applicable depending + * on the device being selected).
\n + * Invoke this API when a CCU4 module needs to be disabled completely. + * Any operation on the CCU4 module will have no effect after this API is called. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableModule()
XMC_CCU4_DisableModule(). + */ +void XMC_CCU4_DisableModule(XMC_CCU4_MODULE_t *const module); + +/** + * @param module Constant pointer to CCU4 module + * @return
+ * None
+ * + * \parDescription:
+ * Starts the prescaler and restores clocks to the timer slices, by setting GIDLC.SPRB bit.
\n + * Once the input to the prescaler has been chosen and the prescaler divider of all slices programmed, + * the prescaler itself may be started. Invoke this API after XMC_CCU4_Init() + * (Mandatory to fully initialize the module).Directly accessed register is GIDLC. + * + * \parRelated APIs:
+ * XMC_CCU4_Init()
XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock()
XMC_CCU4_StartPrescaler()
+ * XMC_CCU4_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_StartPrescaler(XMC_CCU4_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU4_StartPrescaler:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + module->GIDLC |= (uint32_t) CCU4_GIDLC_SPRB_Msk; +} + +/** + * @param module Constant pointer to CCU4 module + * @return
+ * None
+ * + * \parDescription:
+ * Stops the prescaler and blocks clocks to the timer slices, by setting GIDLS.CPRB bit.
\n + * Opposite of the StartPrescaler routine. + * Clears the run bit of the prescaler. Ensures that the module clock is not supplied to + * the slices of the module.Registers directly accessed is GIDLS. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock()
XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_StopPrescaler(XMC_CCU4_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU4_StopPrescaler:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + module->GIDLS |= (uint32_t) CCU4_GIDLS_CPRB_Msk; +} + +/** + * @param module Constant pointer to CCU4 module + * @return
+ * None
+ * + * \parDescription:
+ * Returns the state of the prescaler, by reading GSTAT.PRB bit.
\n + * This will return true if the prescaler is running. If clock is being supplied to the slices of the + * module then returns as true. + * + * \parRelated APIs:
+ * XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler()
XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock(). + */ +__STATIC_INLINE bool XMC_CCU4_IsPrescalerRunning(XMC_CCU4_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU4_IsPrescalerRunning:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + return((bool)((module->GSTAT & (uint32_t) CCU4_GSTAT_PRB_Msk) == (uint32_t)CCU4_GSTAT_PRB_Msk)); +} + +/** + * @param module Constant pointer to CCU4 module + * @param clock_mask Slices whose clocks are to be enabled simultaneously. + * Bit location 0/1/2/3 represents slice-0/1/2/3 respectively. + * Range: [0x1 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Enables clocks of multiple slices at a time, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * GIDLC.CS3I bits.\n\n + * Takes an input clock_mask, which determines the slices that would receive the clock. Bring them out + * of the idle state simultaneously. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableClock()
XMC_CCU4_DisableClock(). + */ +__STATIC_INLINE void XMC_CCU4_EnableMultipleClocks(XMC_CCU4_MODULE_t *const module, const uint8_t clock_mask) +{ + XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Wrong clock mask", (clock_mask < 16U)); + + module->GIDLC |= (uint32_t) clock_mask; +} + +/** + * @param module Constant pointer to CCU4 module + * @param slice_number Slice for which the clock should be Enabled. + * Range: [0x0 to 0x3] + * @return
+ * None
+ * + * \parDescription:
+ * Enables the slice timer clock, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * GIDLC.CS3I bits according to the selected \a slice_number.\n\n + * It is possible to enable/disable clock at slice level. This uses the \b slice_number to indicate the + * slice whose clock needs to be enabled. + * + * \parRelated APIs:
+ * XMC_CCU4_DisableClock()
XMC_CCU4_EnableMultipleClocks()
XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_EnableClock(XMC_CCU4_MODULE_t *const module, const uint8_t slice_number) +{ + XMC_ASSERT("XMC_CCU4_EnableClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + XMC_ASSERT("XMC_CCU4_EnableClock:Invalid Slice Number", (slice_number < 4U)); + + module->GIDLC |= ((uint32_t) 1) << slice_number; +} + +/** + * @param module Constant pointer to CCU4 module + * @param slice_number Slice for which the clock should be disabled. + * Range: [0x0 to 0x3] + * @return
+ * None
+ * + * \parDescription:
+ * Disables the slice timer clock, by configuring GIDLS.SS0I, GIDLS.SSS1I, GIDLS.SSS2I, + * GIDLS.SSS3I bits according to the selected \a slice_number .\n\n + * It is possible to disable clock at slice level using the module pointer. + * \b slice_number is used to disable the clock to a given slice of the module. + * Directly accessed Register is GIDLS. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableClock()
XMC_CCU4_EnableMultipleClocks()
XMC_CCU4_StartPrescaler()
XMC_CCU4_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_DisableClock(XMC_CCU4_MODULE_t *const module, const uint8_t slice_number) +{ + XMC_ASSERT("XMC_CCU4_DisableClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + XMC_ASSERT("XMC_CCU4_DisableClock:Invalid Slice Number", (slice_number < 4U)); + + module->GIDLS |= ((uint32_t) 1) << slice_number; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param compare_init Pointer to slice configuration structure + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of a CC4 slice to compare mode, by configuring CC4yTC, CC4yCMC, CC4yPSC, CC4yDITH, CC4yPSL, + * CC4yFPCS, CC4yCHC registers.\n\n + * CC4 slice is configured with Timer configurations in this routine. + * After initialization user has to explicitly enable the shadow transfer for the required values by calling + * XMC_CCU4_EnableShadowTransfer() with appropriate mask. + * + * \parRelated APIs:
+ * None. + */ +void XMC_CCU4_SLICE_CompareInit(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_COMPARE_CONFIG_t *const compare_init); + +/** + * @param slice Constant pointer to CC4 Slice + * @param capture_init Pointer to slice configuration structure + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of a CC4 slice to capture mode, by configuring CC4yTC, CC4yCMC, CC4yPSC,CC4yFPCS registers.\n\n + * CC4 slice is configured with Capture configurations in this routine.After initialization user has to explicitly + * enable the shadow transfer for the required values by calling XMC_CCU4_EnableShadowTransfer() + * with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_Capture0Config()
XMC_CCU4_SLICE_Capture1Config(). + */ +void XMC_CCU4_SLICE_CaptureInit(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAPTURE_CONFIG_t *const capture_init); + + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Start Function + * @param start_mode Behavior of slice when the start function is activated + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Start Function of the slice, by configuring CC4yCMC.ENDS and CC4yTC.ENDM bits.\n\n + * Start function is mapped with one of the 3 events. An external signal can control when a CC4 timer should start. + * Additionally, the behaviour of the slice upon activation of the start function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StopConfig()
XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_StartConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_START_MODE_t start_mode); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Stop Function + * @param end_mode Behavior of slice when the stop function is activated + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Stop function for the slice, by configuring CC4yCMC.STRTS and CC4yTC.STRM bits.\n\n + * Stop function is mapped with one of the 3 events. An external signal can control when a CCU4 timer should stop. + * Additionally, the behaviour of the slice upon activation of the stop function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartConfig()
XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_StopConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_END_MODE_t end_mode); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External load Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Load Function for the slice, by configuring CC4yCMC.LDS bit.\n\n + * Load function is mapped with one of the 3 events. Up on occurrence of the event,\n + * if CC4yTCST.CDIR set to 0,CC4yTIMER register is reloaded with the value from compare register\n + * if CC4yTCST.CDIR set to 1,CC4yTIMER register is reloaded with the value from period register\n + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_LoadConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Modulation Function + * @param mod_mode Desired Modulation mode + * @param synch_with_pwm Option to synchronize modulation with PWM start + * Pass \b true if the modulation needs to be synchronized with PWM signal. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Output Modulation Function of the slice, by configuring CCeyCMC.MOS, CC4yTC.EMT and + * CC4yTC.EMS bits.\n\n + * Modulation function is mapped with one of the 3 events. The output signal of the CCU can + * be modulated according to a external input. Additionally, the behaviour of the slice upon activation + * of the modulation function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_ModulationConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_MODULATION_MODE_t mod_mode, + const bool synch_with_pwm); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Count Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Count Function of the slice, by configuring CC4yCMC.CNTS bit.\n\n + * Count function is mapped with one of the 3 events. CCU4 slice can take an external + * signal to act as the counting event. The CCU4 slice would count the + * edges present on the \b event selected. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_CountConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Gating Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Gating Function of the slice, by configuring CC4yCMC.GATES bit.\n\n + * Gating function is mapped with one of the 3 events. A CCU4 slice can use an input signal that would + * operate as counter gating. If the configured Active level is detected the counter will gate all the pulses. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_GateConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the Capture-0 Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Capture-0 Function of the slice, by configuring CC4yCMC.CAP0S bit.\n\n + * Capture function is mapped with one of the 3 events. A CCU4 slice can be configured into capture-0 mode + * with the selected \b event. In this mode the CCU4 will capture the timer value into CC4yC0V and CC4yC1V. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_Capture0Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the Capture-1 Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Capture-1 Function of the slice, by configuring CC4yCMC.CAP1S bit.\n\n + * Capture function is mapped with one of the 3 events. A CCU4 slice can be configured into capture-1 + * mode with the selected \b event. In this mode the CCU4 will capture the timer value into CC4yC2V and CC4yC3V. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_Capture1Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * bool would return true if the extended capture read back mode is enabled
+ * + * \parDescription:
+ * Checks if Extended capture mode read is enabled for particular slice or not, by reading CC4yTC.ECM bit.\n\n + * In this mode the there is only one associated read address for all the capture registers. + * Individual capture registers can still be accessed in this mode. + * + * \parRelated APIs:
+ * XMC_CCU4_GetCapturedValueFromFifo(). + */ +__STATIC_INLINE bool XMC_CCU4_SLICE_IsExtendedCapReadEnabled(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_IsExtendedCapReadEnabled:Invalid Module Pointer", XMC_CCU4_IsValidSlice(slice)); + return((bool)((slice->TC & (uint32_t) CCU4_CC4_TC_ECM_Msk) == (uint32_t)CCU4_CC4_TC_ECM_Msk)); +} + +#if defined(CCU4V1) /* Defined for XMC4500, XMC4400, XMC4200, XMC4100 devices only */ +/** + * @param module Constant pointer to CCU4 module + * @param slice_number to check whether read value belongs to required slice or not + * @return
+ * int32_t Returns -1 if the FIFO value being retrieved is not from the \b slice_number. + * Returns the value captured in the \b slice_number, if captured value is from the correct slice. + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Read captured value from FIFO(ECRD register).\n\n + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * derived/inferred from the captured values. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_IsExtendedCapReadEnabled(). + * @note Only available for XMC4500, XMC4400, XMC4200 and XMC4100 series + */ +int32_t XMC_CCU4_GetCapturedValueFromFifo(const XMC_CCU4_MODULE_t *const module, const uint8_t slice_number); +#else +/** + * @param slice Constant pointer to CC4 Slice + * @param set The capture register set from which the captured value is to be retrieved + * @return
+ * uint32_t Returns the value captured in the \b slice_number + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Read captured value from FIFO(CC4yECRD0 and CC4yECRD1).\n\n + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * derived/inferred from the captured values. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_IsExtendedCapReadEnabled(). + * @note Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only. For other devices use XMC_CCU4_GetCapturedValueFromFifo() API + */ +uint32_t XMC_CCU4_SLICE_GetCapturedValueFromFifo(const XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAP_REG_SET_t set); +#endif + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Map an External event to the External Count Direction Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Count Direction of the slice, by configuring CC4yCMC.UDS bit.\n\n + * Count direction function is mapped with one of the 3 events. A slice can be configured to change the + * CC4yTIMER count direction depending on an external signal. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_DirectionConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Configures the status bit override Function of the slice, by configuring CC4yCMC.OFS bit.\n\n + * Status bit override function is mapped with one of the 3 events. A slice can be configured to change the + * output of the timer's CC4yST signal depending on an external signal. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(). + */ +void XMC_CCU4_SLICE_StatusBitOverrideConfig(XMC_CCU4_SLICE_t *const slice); + +/** + * @param slice Constant pointer to CC4 Slice + * @param exit_mode How should a previously logged trap state be exited? + * @param synch_with_pwm Should exit of trap state be synchronized with PWM cycle start? + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Trap Function of the slice, by configuring CC4yCMC.TS, CC4yTC.TRPSE, and CC4yTC.TRPSW bits.\n\n + * Trap function is mapped with Event-2. Criteria for exiting the trap state is configured. + * This trap function allows PWM outputs to react on the state of an input pin. + * Thus PWM output can be forced to inactive state upon detection of a trap. + * It is also possible to synchronize the trap function with the PWM signal using the \b synch_with_pwm. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_ConfigureEvent()
XMC_CCU4_SLICE_SetInput(). + */ +void XMC_CCU4_SLICE_TrapConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_TRAP_EXIT_MODE_t exit_mode, + bool synch_with_pwm); + + +/** + * @param slice Constant pointer to CC4 Slice + * @param ev1_config Pointer to event 1 configuration data + * @param ev2_config Pointer to event 2 configuration data + * @return
+ * None
+ * + * + * \parDescription:
+ * Map Status bit override function with an Event1 & Event 2 of the slice and configure CC4yINS register.\n\n + * Details such as the input mapped to the event, event detection criteria and Low Pass filter options are programmed + * by this routine for the events 1 & 2. Event-1 input would be the trigger to override the value. + * Event-2 input would be the override value. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StatusBitOverrideConfig(). + */ +void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev2_config); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event The External Event which needs to be configured. + * @param config Pointer to event configuration data. + * @return
+ * None
+ * + * \parDescription:
+ * Configures an External Event of the slice, by updating CC4yINS register .\n\n + * Details such as the input mapped to the event, event detection criteria and low pass filter + * options are programmed by this routine. The Event \b config will configure the input selection, + * the edge selection, the level selection and the Low pass filter for the event. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartConfig()
XMC_CCU4_SLICE_StopConfig()
XMC_CCU4_SLICE_LoadConfig()
+ * XMC_CCU4_SLICE_ModulationConfig()
XMC_CCU4_SLICE_CountConfig()
XMC_CCU4_SLICE_GateConfig()
+ * XMC_CCU4_SLICE_Capture0Config()
XMC_CCU4_SLICE_Capture1Config()
XMC_CCU4_SLICE_DirectionConfig()
+ * XMC_CCU4_SLICE_StatusBitOverrideConfig()
XMC_CCU4_SLICE_TrapConfig(). + */ +void XMC_CCU4_SLICE_ConfigureEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const config); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event The External Event which needs to be configured. + * @param input One of the 16 inputs meant to be mapped to the desired event + * @return
+ * None
+ * + * + * \parDescription:
+ * Selects an input for an external event, by configuring CC4yINS register.\n\n + * It is possible to select one of the possible 16 input signals for a given Event. + * This configures the CC4yINS.EVxIS for the selected event. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartConfig()
XMC_CCU4_SLICE_StopConfig()
XMC_CCU4_SLICE_LoadConfig()
+ * XMC_CCU4_SLICE_ModulationConfig()
XMC_CCU4_SLICE_CountConfig()
XMC_CCU4_SLICE_GateConfig()
+ * XMC_CCU4_SLICE_Capture0Config()
XMC_CCU4_SLICE_Capture1Config()
XMC_CCU4_SLICE_DirectionConfig()
+ * XMC_CCU4_SLICE_StatusBitOverrideConfig()
XMC_CCU4_SLICE_TrapConfig(). + */ +void XMC_CCU4_SLICE_SetInput(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_INPUT_t input); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Enables the trap feature, by setting CC4yTC.TRAPE0, CC4yTC.TRAPE1, CC4yTC.TRAPE2 and CC4yTC.TRAPE3 bit based on the + * \a out_mask.\n\n + * A particularly useful feature where the PWM output can be forced inactive upon detection of a trap. The trap signal + * can be the output of a sensing element which has just detected an abnormal electrical condition. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_TrapConfig()
XMC_CCU4_SLICE_DisableTrap()
XMC_CCU4_SLICE_ConfigureEvent()
+ * XMC_CCU4_SLICE_SetInput(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableTrap(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableTrap:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC |= (uint32_t) CCU4_CC4_TC_TRAPE_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables the trap feature, by clearing CC4yTC.TRAPE0, CC4yTC.TRAPE1, CC4yTC.TRAPE2 and CC4yTC.TRAPE3 bit based on the + * \a out_mask.\n\n.\n\n + * This API will revert the changes done by XMC_CCU4_SLICE_EnableTrap(). + * This Ensures that the TRAP function has no effect on the output of the CCU4 slice. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableTrap(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableTrap(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableTrap:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU4_CC4_TC_TRAPE_Msk); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * bool returns \b true if the Timer is running else it returns \b false. + * + * \parDescription:
+ * Returns the state of the timer (Either Running or stopped(idle)), by reading CC4yTCST.TRB bit. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartTimer()
XMC_CCU4_SLICE_StopTimer(). + */ +__STATIC_INLINE bool XMC_CCU4_SLICE_IsTimerRunning(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetTimerStatus:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return (bool)(((slice->TCST) & CCU4_CC4_TCST_TRB_Msk) == CCU4_CC4_TCST_TRB_Msk); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * ::XMC_CCU4_SLICE_TIMER_COUNT_DIR_t returns the direction in which the timer is counting. + * + * \parDescription:
+ * Returns the timer counting direction, by reading CC4yTCST.CDIR bit.\n\n + * This API will return the direction in which the timer is currently + * incrementing(XMC_CCU4_SLICE_TIMER_COUNT_DIR_UP) or decrementing (XMC_CCU4_SLICE_TIMER_COUNT_DIR_DOWN). + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_CCU4_SLICE_TIMER_COUNT_DIR_t XMC_CCU4_SLICE_GetCountingDir(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetCountingDir:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((XMC_CCU4_SLICE_TIMER_COUNT_DIR_t)(((slice->TCST) & CCU4_CC4_TCST_CDIR_Msk) >> CCU4_CC4_TCST_CDIR_Pos)); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Starts the timer counting operation, by setting CC4yTCSET.TRBS bit.\n\n + * It is necessary to have configured the CC4 slice before starting its timer. + * Before the Timer is started ensure that the clock is provided to the slice. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StopTimer(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_StartTimer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_StartTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TCSET = CCU4_CC4_TCSET_TRBS_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Stops the Timer.
\n + * Timer counting operation can be stopped by invoking this API, by setting CC4yTCCLR.TRBC bit. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_StopTimer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_StopTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TCCLR = (uint32_t) CCU4_CC4_TCCLR_TRBC_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Resets the timer count to zero, by setting CC4yTCCLR.TCC bit.\n\n + * A timer which has been stopped can still retain the last counted value. + * After invoking this API the timer value will be cleared. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_ClearTimer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_ClearTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TCCLR = (uint32_t) CCU4_CC4_TCCLR_TCC_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Stops and resets the timer count to zero, by setting CC4yTCCLR.TCC and CC4yTCCLR.TRBC bit.\n\n + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_StopClearTimer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_StopClearTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TCCLR = CCU4_CC4_TCCLR_TRBC_Msk | CCU4_CC4_TCCLR_TCC_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * ::XMC_CCU4_SLICE_MODE_t returns XMC_CCU4_SLICE_MODE_COMPARE if the slice is operating in compare mode + * returns XMC_CCU4_SLICE_MODE_CAPTURE if the slice is operating in capture mode + * + * \parDescription:
+ * Retrieves the current mode of operation in the slice (either Capture mode or Compare mode), by reading + * CC4yTC.CMOD bit.\n\n + * Ensure that before invoking this API the CCU4 slice should be configured otherwise the output of this API is + * invalid. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_CCU4_SLICE_MODE_t XMC_CCU4_SLICE_GetSliceMode(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetSliceMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((XMC_CCU4_SLICE_MODE_t)(((slice->TC) & CCU4_CC4_TC_CMOD_Msk) >> CCU4_CC4_TC_CMOD_Pos)); +} +/** + * @param slice Constant pointer to CC4 Slice + * @param mode Desired repetition mode (Either single shot or Continuous) + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Timer to either Single shot mode or continuous mode, by configuring CC4yTC.TSSM bit.\n\n + * The timer will count up to the terminal count as specified in the period register and stops immediately if the repeat + * mode has been set to single shot. In the continuous mode of operation, the timer starts counting all over again after + * reaching the terminal count. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetTimerRepeatMode(). + */ +void XMC_CCU4_SLICE_SetTimerRepeatMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t mode); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * ::XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t returns XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT if continuous mode is selected + * returns XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE if single shot mode is selected + * + * \parDescription:
+ * Retrieves the Timer repeat mode, either Single shot mode or continuous mode, by reading CC4yTC.TSSM bit.\n\n + * The timer will count up to the terminal count as specified in the period register and stops immediately if the repeat + * mode has been set to single shot mode. In the continuous mode of operation, the timer starts counting + * all over again after reaching the terminal count. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetTimerRepeatMode(). + */ +__STATIC_INLINE XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t XMC_CCU4_SLICE_GetTimerRepeatMode( + const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TSSM_Msk) >> CCU4_CC4_TC_TSSM_Pos)); +} +/** + * @param slice Constant pointer to CC4 Slice + * @param mode Desired counting mode (Either Edge Aligned or Center Aligned) + * @return
+ * None
+ * + * \parDescription:
+ * Configures the timer counting mode either Edge Aligned or Center Aligned, by configuring CC4yTC.TCM bit.\n\n + * In the edge aligned mode, the timer counts from 0 to the terminal count. Once the timer count has reached a preset + * compare value, the timer status output asserts itself. It will now deassert only after the timer count reaches the + * terminal count.\n In the center aligned mode, the timer first counts from 0 to the terminal count and then back to 0. + * During this upward and downward counting, the timer status output stays asserted as long as the timer value is + * greater than the compare value. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetTimerCountingMode(). + */ +void XMC_CCU4_SLICE_SetTimerCountingMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_COUNT_MODE_t mode); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * ::XMC_CCU4_SLICE_TIMER_COUNT_MODE_t returns XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA if edge aligned mode is selected + * returns XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA if center aligned mode is selected + * + * \parDescription:
+ * Retrieves timer counting mode either Edge aligned or Center Aligned, by reading CC4yTC.TCM bit.\n\n + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetTimerCountingMode(). + */ +__STATIC_INLINE XMC_CCU4_SLICE_TIMER_COUNT_MODE_t XMC_CCU4_SLICE_GetTimerCountingMode( + const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetTimerCountingMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((XMC_CCU4_SLICE_TIMER_COUNT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TCM_Msk) >> CCU4_CC4_TC_TCM_Pos)); +} +/** + * @param slice Constant pointer to CC4 Slice + * @param period_val Timer period value + * Range: [0x0 to 0xFFFF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer period, by writing CC4yPRS register.\n\n + * The frequency of counting/ PWM frequency is determined by this value. The period value is written to a shadow + * register. Explicitly enable the shadow transfer for the the period value by calling + * XMC_CCU4_EnableShadowTransfer() with appropriate mask. If shadow transfer is enabled and the timer is running, + * a period match transfers the value from the shadow register to the actual period register. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetTimerPeriodMatch(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetTimerPeriodMatch(XMC_CCU4_SLICE_t *const slice, const uint16_t period_val) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->PRS = (uint32_t) period_val; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * uint16_t returns the current timer period value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the timer period value currently effective, by reading CC4yPR register.\n\n + * If the timer is active then the value being returned is currently being used for the PWM period. + * + * \parNote:
+ * The XMC_CCU4_SLICE_SetTimerPeriodMatch() would set the new period value to a shadow register. + * This would only transfer the new values into the actual period register if the shadow transfer request + * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU4_SLICE_GetTimerPeriodMatch() + * would not reflect the new values until the shadow transfer completes. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetTimerPeriodMatch(). + */ +__STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerPeriodMatch(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((uint16_t)slice->PR); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param compare_val Timer compare value + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer compare value, by writing CC4yCRS register.
\n + * The PWM duty cycle is determined by this value. + * The compare value is written to a shadow register. Explicitly enable the shadow transfer for + * the the period/compare value by calling XMC_CCU4_EnableShadowTransfer() with + * appropriate mask.If shadow transfer is enabled and the timer is running, + * a period match transfers the value from the shadow register to the actual compare register. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetTimerPeriodMatch(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetTimerCompareMatch(XMC_CCU4_SLICE_t *const slice, const uint16_t compare_val) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->CRS = (uint32_t) compare_val; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * uint16_t returns the current timer compare value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the timer compare value currently effective, by reading CC4yCRS register.\n\n + * If the timer is active then the value being returned is currently being for the PWM duty cycle( timer compare value). + * + * \parNote:
+ * The XMC_CCU4_SLICE_SetTimerCompareMatch() would set the new compare value to a shadow register. + * This would only transfer the new values into the actual compare register if the shadow transfer request + * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU4_SLICE_GetTimerCompareMatch() + * would not reflect the new values until the shadow transfer completes. + * Directly accessed Register is CC4yCR. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetTimerCompareMatch(). + */ +__STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerCompareMatch(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((uint16_t)slice->CR); +} + +/** + * @param module Constant pointer to CCU4 module + * @param shadow_transfer_msk Shadow transfer request mask for various transfers. + * Use ::XMC_CCU4_SHADOW_TRANSFER_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Requests of shadow transfer for Period, Compare, Passive level, dither and prescaler, by configuring + * the GCSS register.\n\n + * The transfer from the shadow registers to the actual registers is done in the immediate next occurrence of the + * shadow transfer trigger after the API is called. + * + * Any call to XMC_CCU4_SLICE_SetTimerPeriodMatch()
XMC_CCU4_SLICE_SetTimerCompareMatch()
+ * XMC_CCU4_SLICE_SetPrescaler()
XMC_CCU4_SLICE_CompareInit()
XMC_CCU4_SLICE_CaptureInit(). + * must be succeeded by this API. + * Directly accessed Register is GCSS. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_CCU4_EnableShadowTransfer(XMC_CCU4_MODULE_t *const module, const uint32_t shadow_transfer_msk) +{ + XMC_ASSERT("XMC_CCU4_EnableShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidModule(module)); + module->GCSS = (uint32_t)shadow_transfer_msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * uint16_t returns the current timer value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the latest timer value, from CC4yTIMER register.\n\n + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetTimerValue(). + */ +__STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerValue(const XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + return((uint16_t)slice->TIMER); +} +/** + * @param slice Constant pointer to CC4 Slice + * @param timer_val The new timer value that has to be loaded into the TIMER register. + * Range: [0x0 to 0xFFFF] + * @return
+ * None
+ * + * \parDescription:
+ * Loads a new timer value, by setting CC4yTIMER register.\n\n + * + * \parNote:
+ * Request to load is ignored if the timer is running. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetTimerValue(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetTimerValue(XMC_CCU4_SLICE_t *const slice, const uint16_t timer_val) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TIMER = (uint32_t) timer_val; +} +/** + * @param slice Constant pointer to CC4 Slice + * @param period_dither Boolean instruction on dithering of period match + * @param duty_dither Boolean instruction on dithering of compare match + * @param spread Dither compare value + * @return
+ * None
+ * + * \parDescription:
+ * Enables dithering of PWM frequency and duty cycle, by configuring CC4yTC.DITHE and CC4yDITS bits.\n\n + * Some control loops are slow in updating PWM frequency and duty cycle. In such a case, a Bresenham style dithering + * can help reduce long term errors. Dithering can be applied to period and duty individually, + * this can be selected using the parameter \b period_dither and \b duty_dither. + * The \b spread would provide the dither compare value. If the dither counter value is less than this \b spread then + * the period/compare values would be dithered according to the dither mode selected. This API would invoke + * XMC_CCU4_SLICE_SetDitherCompareValue(). + * + * \parNote:
+ * After this API call, XMC_CCU4_EnableShadowTransfer() has to be called with appropriate mask + * to transfer the dither value. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_DisableDithering(). + */ +void XMC_CCU4_SLICE_EnableDithering(XMC_CCU4_SLICE_t *const slice, + const bool period_dither, + const bool duty_dither, + const uint8_t spread); + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables dithering of PWM frequency and duty cycle, by clearing CC4yTC.DITHE bits.\n\n + * This disables the Dither mode that was set in XMC_CCU4_SLICE_EnableDithering(). + * This API will not clear the dither compare value. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableDithering(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableDithering(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableDithering:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU4_CC4_TC_DITHE_Msk); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Enables the floating prescaler, by setting CC4yTC.FPE bit.\n\n + * The prescaler divider starts with an initial value and increments upon every period match. It keeps incrementing + * until a ceiling (prescaler compare value) is hit and thereafter rolls back to the original prescaler divider value.\n + * It is necessary to have programmed an initial divider value and a compare value before the feature is enabled. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue()
XMC_CCU4_SLICE_DisableFloatingPrescaler()
+ * XMC_CCU4_SLICE_SetPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableFloatingPrescaler(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC |= (uint32_t) CCU4_CC4_TC_FPE_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables the floating prescaler, by clearing CC4yTC.FPE bit.\n\n + * This would return the prescaler to the normal mode. + * The prescaler that would be applied is the value present in CC4yPSC. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableFloatingPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableFloatingPrescaler(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU4_CC4_TC_FPE_Msk); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param comp_val Dither compare value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Sets the dither spread/compare value, by setting CC4yDITS.DCVS bits.\n\n + * This value is the cornerstone of PWM dithering feature. Dithering is applied/done when the value in the + * dithering counter is less than this compare/spread value. For all dithering counter values greater than + * the spread value, there is no dithering. After setting the value XMC_CCU4_EnableShadowTransfer() has to be + * called with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableDithering(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetDitherCompareValue(XMC_CCU4_SLICE_t *const slice, const uint8_t comp_val) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetDitherCompareValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->DITS = comp_val; +} +/** + * @param slice Constant pointer to CC4 Slice + * @param div_val Prescaler divider value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the slice specific prescaler divider, by configuring the CC4yPSC and CC4yFPC registers.\n\n + * The prescaler divider may only be programmed after the prescaler run bit has been cleared + * by calling XMC_CCU4_StopPrescaler(). + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue(). + */ +void XMC_CCU4_SLICE_SetPrescaler(XMC_CCU4_SLICE_t *const slice, const uint8_t div_val); + +/** + * @param slice Constant pointer to CC4 Slice + * @param cmp_val Prescaler divider compare value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the slice specific prescaler divider compare value, by configuring CC4yFPCS register.\n\n + * The compare value is applicable only in floating mode of operation. The prescaler divider starts with an initial + * value and increments to the compare value steadily upon every period match. Once prescaler divider + * equals the prescaler divider compare value, the value in the former resets back to the PVAL (from FPC). After setting + * the value, XMC_CCU4_EnableShadowTransfer() has to be called with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetPrescaler(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue(XMC_CCU4_SLICE_t *const slice, + const uint8_t cmp_val) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + /* write to the shadow register */ + slice->FPCS = (uint32_t) cmp_val; +} +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Enables the multichannel mode, by setting CC4yTC.MCME bit.
\n + * The output state of the Timer slices can be controlled in parallel by a single input signal. + * A particularly useful feature in motor control applications where the PWM output of multiple slices of a module can + * be gated and ungated by multi-channel gating inputs connected to the slices. A peripheral like POSIF connected to the + * motor knows exactly which of the power drive switches are to be turned on and off at any instant. It can thus through + * a gating bus (known as multi-channel inputs) control which of the slices output stays gated/ungated. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_DisableMultiChannelMode()
XMC_CCU4_SetMultiChannelShadowTransferMode(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableMultiChannelMode(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableMultiChannelMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC |= (uint32_t) CCU4_CC4_TC_MCME_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables the multichannel mode, by clearing CC4yTC.MCME bit.
\n + * This would return the slices to the normal operation mode. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableMultiChannelMode(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableMultiChannelMode(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableMultiChannelMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU4_CC4_TC_MCME_Msk); +} + +/** + * @param module Constant pointer to CCU4 module + * @param slice_mode_msk Slices for which the configuration has to be applied. + * Use ::XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Enables the Multi-channel shadow transfer request trigger signal either by software or hardware by configuring + * GCTRL.MSE0, GCTRL.MSE1, GCTRL.MSE2, and GCTRL.MSE3 based on the mask.\n\n + * The shadow transfer would take place either if it was requested by software or by the CCU4x.MCSS input. + * + * \parRelated APIs:
+ * None. +*/ +void XMC_CCU4_SetMultiChannelShadowTransferMode(XMC_CCU4_MODULE_t *const module, const uint32_t slice_mode_msk); + +/** + * @param slice Constant pointer to CC4 Slice + * @param reg_num The capture register from which the captured value is to be retrieved + * Range: [0,3] + * @return
+ * uint32_t Returns the Capture register value. + * Range: [0 to 0x1FFFFF] + * + * \parDescription:
+ * Retrieves timer value which has been captured in the Capture registers, by reading CC4yCV[\b reg_num] register.\n\n + * The signal whose timing characteristics are to be measured must be mapped to an event which in turn must be mapped + * to the capture function. Based on the capture criteria, the timer values are captured into capture registers. Timing + * characteristics of the input signal may then be derived/inferred from the captured values. The full flag will help + * to find out if there is a new captured value present. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetLastCapturedTimerValue(). + */ +uint32_t XMC_CCU4_SLICE_GetCaptureRegisterValue(const XMC_CCU4_SLICE_t *const slice, const uint8_t reg_num); + +/** + * @param slice Constant pointer to CC4 Slice + * @param set The capture register set, which must be evaluated + * @param val_ptr Out Parameter of the API.Stores the captured timer value into this out parameter. + * @return
+ * ::XMC_CCU4_STATUS_t Returns XMC_CCU4_STATUS_OK if there was new value present in the capture registers. + * returns XMC_CCU4_STATUS_ERROR if there was no new value present in the capture registers. + * + * \parDescription:
+ * Retrieves the latest captured timer value, by reading CC4yCV registers.\n\n + * Retrieve the timer value last stored by the slice. When separate capture events are used, + * users must specify the capture set to evaluate. If single capture event mode is used, all 4 capture registers are + * evaluated.\n + * The lowest register is evaluated first followed by the next higher ordered register and this continues until all + * capture registers have been evaluated. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_GetCaptureRegisterValue(). + */ +XMC_CCU4_STATUS_t XMC_CCU4_SLICE_GetLastCapturedTimerValue(const XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr); + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Enables the generation of an interrupt pulse for the event, by configuring CC4yINTE register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API merely enables the event. Binding with SR is performed by another API. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableMultipleEvents()
XMC_CCU4_SLICE_DisableEvent()
+ * XMC_CCU4_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_EnableEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + slice->INTE |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param intr_mask Event mask such that multiple events can be enabled. + * Use ::XMC_CCU4_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Enables the generation of an interrupt pulse for the required events, by configuring CC4yINTE register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API merely enables the events. Binding with SR is performed by another API. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_DisableEvent()
+ * XMC_CCU4_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableMultipleEvents(XMC_CCU4_SLICE_t *const slice, const uint16_t intr_mask) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableMultipleEvents:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->INTE |= (uint32_t)intr_mask; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Disables the generation of an interrupt pulse for the event, by clearing CC4yINTE register.\n\n + * Prevents the event from being asserted + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_EnableMultipleEvents()
+ * XMC_CCU4_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_DisableEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + slice->INTE &= ~(((uint32_t) 1) << ((uint32_t) event)); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param mask Event mask such that multiple events can be enabled. + * Use ::XMC_CCU4_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Disables the generation of an interrupt pulse for the required events, by clearing CC4yINTE register.\n\n + * Prevents selected events of the slice from being asserted. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_EnableMultipleEvents()
+ * XMC_CCU4_SLICE_DisableEvent(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableMultipleEvents(XMC_CCU4_SLICE_t *const slice, const uint16_t mask) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableMultipleEvents:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->INTE &= ~((uint32_t) mask); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Manually asserts the requested event, by setting CC4ySWS register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API manually asserts the requested event. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_SetInterruptNode()
XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_EnableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_SetEvent(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + slice->SWS |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Asserted event which must be acknowledged. + * @return
+ * None
+ * + * \parDescription:
+ * Acknowledges an asserted event, by setting CC4ySWR with respective event flag.\n\n + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent()
XMC_CCU4_SLICE_GetEvent(). + */ +__STATIC_INLINE void XMC_CCU4_SLICE_ClearEvent(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU4_SLICE_ClearEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_ClearEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + slice->SWR |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param event Event to be evaluated for assertion + * @return
+ * bool Returns true if event is set else false is returned. + * + * \parDescription:
+ * Evaluates if a given event is asserted or not, by reading CC4yINTS register.\n\n + * Return true if the event is asserted. For a event to be asserted it has to be + * first enabled. Only if that event is enabled the call to this API is valid. + * If the Event is enabled and has not yet occurred then a false is returned. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent(). + */ +__STATIC_INLINE bool XMC_CCU4_SLICE_GetEvent(const XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_GetEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + + return(((uint32_t)(slice->INTS & ((uint32_t)1 << (uint32_t)event))) != 0U); +} +/** + * @param slice Constant pointer to CC4 Slice + * @param event Event which must be bound to a service request line + * @param sr The Service request line which is bound to the \b event + * @return
+ * None
+ * + * \parDescription:
+ * Binds requested event to a service request line, by configuring CC4ySRS register with respective event.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API binds the requested event with the requested service request line(\b sr). + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent(). + */ +void XMC_CCU4_SLICE_SetInterruptNode(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_IRQ_ID_t event, + const XMC_CCU4_SLICE_SR_ID_t sr); + +/** + * @param slice Constant pointer to CC4 Slice + * @param level Slice output passive level + * @return
+ * None
+ * + * \parDescription:
+ * Configures the passive level for the slice output, by setting CC4yPSL register.\n\n + * Defines the passive level for the timer slice output pin. Selects either level high is passive + * or level low is passive. This is the level of the output before the compare match is value changes it. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableEvent()
XMC_CCU4_SLICE_SetEvent(). + */ +void XMC_CCU4_SLICE_SetPassiveLevel(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t level); + +#if defined(CCU4V3) || defined(DOXYGEN) /* Defined for XMC1400 devices only */ +/** + * @param slice Constant pointer to CC4 Slice + * + * @return
+ * None
+ * + * \parDescription:
+ * Cascades the shadow transfer operation throughout the CCU4 timer slices, by setting CSE bit in STC register.\n\n + * + * The shadow transfer enable bits needs to be set in all timer slices, that are being used in the cascaded architecture, + * at the same time. The shadow transfer enable bits, also need to be set for all slices even if the shadow values of + * some slices were not updated. It is possible to to cascade with the adjacent slices only. CC40 slice is a + * master to start the operation. + * + * \parNote:
+ * XMC_CCU4_EnableShadowTransfer() must be called to enable the shadow transfer of the all the slices, which needs to be + * cascaded. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableShadowTransfer(), XMC_CCU4_SLICE_DisableCascadedShadowTransfer()
. + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableCascadedShadowTransfer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC |= (uint32_t) CCU4_CC4_STC_CSE_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * + * @return
+ * None
+ * + * \parDescription:
+ * Disables the cascaded the shadow transfer operation, by clearing CSE bit in STC register.\n\n + * + * If in any slice the cascaded mode disabled, other slices from there onwards does not update the values in cascaded mode. + * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableCascadedShadowTransfer()
. + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableCascadedShadowTransfer(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC &= ~(uint32_t) CCU4_CC4_STC_CSE_Msk; +} + +/** + * @param slice Constant pointer to CC4 Slice + * @param shadow_transfer_mode mode to be configured + * Use :: XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t enum items for mode + * @return
+ * None
+ * + * \parDescription:
+ * Configures when the shadow transfer has to occur, by setting STM bit in STC register.\n\n + * + * After requesting for shadow transfer mode using XMC_CCU4_EnableShadowTransfer(), actual transfer occurs based on the + * selection done using this API (i.e. on period and One match, on Period match only, on One match only). + * + * \parNote:
+ * This is effective when the timer is configured in centre aligned mode. + * + * \parRelated APIs:
+ * XMC_CCU4_EnableShadowTransfer()
+ * @note Only available for XMC1400 series +*/ +__STATIC_INLINE void XMC_CCU4_SLICE_SetShadowTransferMode(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t shadow_transfer_mode) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetShadowTransferMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC = ((slice->STC) & ~(uint32_t)((uint32_t)CCU4_CC4_STC_STM_Msk << (uint32_t)CCU4_CC4_STC_STM_Pos)) | + ((shadow_transfer_mode << CCU4_CC4_STC_STM_Pos) & (uint32_t)CCU4_CC4_STC_STM_Msk); +} + + /** + * @param slice Constant pointer to CC4 Slice + * @param coherent_write specifies for what fields this mode has to be applied + * Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the specified fields shadow value to be updated in synchronous with PWM after shadow transfer request, by + * clearing IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n + * + * When coherent shadow is enabled, after calling XMC_CCU4_EnableShadowTransfer(), the value which are written in the + * respective shadow registers get updated according the configuration done using XMC_CCU4_SLICE_SetShadowTransferMode() + * API. \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU4_EnableShadowTransfer(), XMC_CCU4_SLICE_SetShadowTransferMode()
+ * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle(XMC_CCU4_SLICE_t *const slice, + const uint32_t coherent_write) +{ + XMC_ASSERT("XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC &= ~(uint32_t)coherent_write; +} + + /** + * @param slice Constant pointer to CC4 Slice + * @param immediate_write specifies for what fields this mode has to be applied + * Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the specified fields shadow value to be updated immediately after shadow transfer request, by setting + * IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n + * + * When immediate shadow is enabled, by calling XMC_CCU4_EnableShadowTransfer() the value which are written in the + * shadow registers get updated to the actual registers immediately. \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU4_EnableShadowTransfer()
+ * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer(XMC_CCU4_SLICE_t *const slice, + const uint32_t immediate_write) +{ + XMC_ASSERT("XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC |= immediate_write; +} + + /** + * @param slice Constant pointer to CC4 Slice + * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request is generated + * Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a + * bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configure on which shadow register update, automatic shadow transfer request generation has to be enabled. By setting + * ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n + * + * By updating the configured shadow register, the shadow transfer request is generated to update all the shadow registers. + * \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest(). + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t *const slice, + const uint32_t automatic_shadow_transfer) +{ + XMC_ASSERT("XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC |= automatic_shadow_transfer; +} + + /** + * @param slice Constant pointer to CC4 Slice + * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request should not be + * generated + * Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a + * bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configure on which shadow register update, automatic shadow transfer request generation has to be disabled. By + * clearing ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n + * + * This disables the generation of automatic shadow transfer request for the specified register update. + * \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest(). + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t *const slice, + const uint32_t automatic_shadow_transfer) +{ + XMC_ASSERT("XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + slice->STC &= ~(uint32_t)automatic_shadow_transfer; +} +#endif +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CCU40) */ + +#endif /* CCU4_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ccu8.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ccu8.h new file mode 100644 index 00000000..8b732444 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ccu8.h @@ -0,0 +1,2929 @@ +/** + * @file xmc_ccu8.h + * @date 2016-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Documentation updates
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * - Added XMC_CCU8_SLICE_LoadSelector() API, to select which compare register value has to be loaded + * during external load event. + * + * 2015-07-01: + * - In XMC_CCU8_SLICE_CHECK_INTERRUPT macro, fixed the missing item for compare match down for channel 2.
+ * + * 2015-07-24: + * - XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
+ * + * 2015-08-17: + * - XMC_CCU8_SLICE_PRESCALER_t enum is added to set the prescaler divider.
+ * - XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t is added for all the devices except XMC45 devices, to set when the + * shadow transfer has to happen.
+ * - XMC_CCU8_SOURCE_OUT0_t, XMC_CCU8_SOURCE_OUT1_t, XMC_CCU8_SOURCE_OUT2_t, XMC_CCU8_SOURCE_OUT3_t enums are added + * to maps one of the ST to OUT0, OUT1, OUT3, OUT4 signals. + * - In XMC_CCU8_SLICE_COMPARE_CONFIG_t structure, selector_out0, selector_out1, selector_out2, selector_out3 are + * added to support XMC14 devices. + * - XMC_CCU8_EnableShadowTransfer() API is made as inline, to improve the speed.
+ * - XMC_CCU8_SLICE_EnableCascadedShadowTransfer(), XMC_CCU8_SLICE_DisableCascadedShadowTransfer(), + * XMC_CCU8_SLICE_SetShadowTransferMode() API are supported for all the devices except XMC45. + * + * 2015-09-29: + * - In XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_t, two more enum items are added to support external count direction + * settings. + * + * 2015-10-07: + * - XMC_CCU8_SLICE_SetTimerCompareMatchChannel1(), XMC_CCU8_SLICE_SetTimerCompareMatchChannel2() inline APIs are + * added to update the respective compare registers directly. + * - XMC_CCU8_SLICE_GetEvent() is made as inline. + * - XMC_CCU8_SLICE_MULTI_IRQ_ID_t is added to support the XMC_CCU8_SLICE_EnableMultipleEvents() and + * XMC_CCU8_SLICE_DisableMultipleEvents() APIs. + * - DOC updates for the newly added APIs. + * + * 2016-03-09: + * - Optimization of write only registers + * + * 2016-05-20: + * - Added XMC_CCU8_SLICE_StopClearTimer() + * - Changed XMC_CCU8_SLICE_StopTimer() and XMC_CCU8_SLICE_ClearTimer() + * + * @endcond + */ + +#ifndef XMC_CCU8_H +#define XMC_CCU8_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_common.h" + +#if defined(CCU80) + +#if UC_FAMILY == XMC1 + #include "xmc1_ccu8_map.h" +#endif + +#if UC_FAMILY == XMC4 + #include "xmc4_ccu8_map.h" +#endif + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup CCU8 + * + * @brief Capture Compare Unit 8 (CCU8) low level driver for XMC family of microcontrollers
+ * + * The CCU8 peripheral functions play a major role in applications that need complex Pulse Width Modulation (PWM) signal + * generation, with complementary high side and low side switches, multi phase control. These functions in conjunction + * with a very flexible and programmable signal conditioning scheme, make the CCU8 the must have peripheral for state + * of the art motor control, multi phase and multi level power electronics systems.\n + * Each CCU8 module is comprised of four identical 16 bit Capture/Compare Timer slices, CC8y (where y = [0..4]). Each + * timer slice can work in compare mode or in capture mode. + * + * APIs provided in this file cover the following functional blocks of CCU8: + * -- Timer configuration, Capture configuration, Function/Event configuration, Interrupt configuration + * \par Note: + * 1. SLICE (APIs prefixed with e.g. XMC_CCU8_SLICE_) + * 2. Module (APIs are not having any prefix e.g. XMC_CCU8_) + * + * \par Timer(Compare mode) configuration: + * This section of the LLD provides the configuration structure XMC_CCU8_SLICE_COMPARE_CONFIG_t, + * XMC_CCU8_SLICE_DEAD_TIME_CONFIG_t and the initialization functions XMC_CCU8_SLICE_CompareInit(), XMC_CCU8_SLICE_DeadTimeInit(). + * + * It can be used to: + * -# Start and Stop the timer. (XMC_CCU8_SLICE_StartTimer(), XMC_CCU8_SLICE_StopTimer()) + * -# Update the period, compare, Dither, Prescaler and Passive values. (XMC_CCU8_SLICE_SetTimerPeriodMatch(), + * XMC_CCU8_SLICE_SetTimerCompareMatch(), XMC_CCU8_SLICE_SetPrescaler(), XMC_CCU8_SLICE_SetDitherCompareValue(), + * XMC_CCU8_SLICE_SetPassiveLevel()) + * -# Configure the dead time.(XMC_CCU8_SLICE_SetDeadTimeValue(), XMC_CCU8_SLICE_SetDeadTimePrescaler()) + * -# Enable the slices to support multichannel mode. (XMC_CCU8_SLICE_EnableMultiChannelMode()) + * + * \par Capture configuration: + * This section of the LLD provides the configuration structure XMC_CCU8_SLICE_CAPTURE_CONFIG_t and the initialization + * function XMC_CCU8_SLICE_CaptureInit(). + * + * It can be used to: + * -# Configure the capture functionality. (XMC_CCU8_SLICE_Capture0Config(), XMC_CCU8_SLICE_Capture1Config()) + * -# Read the captured values along with the status, which indicate the value is latest or not. + * (XMC_CCU8_SLICE_GetCaptureRegisterValue()) + * + * \par Function/Event configuration: + * This section of the LLD provides the configuration structure XMC_CCU8_SLICE_EVENT_CONFIG_t. + * + * It can be used to: + * -# Enable and Disable the events. (XMC_CCU8_SLICE_EnableEvent(), XMC_CCU8_SLICE_DisableEvent()) + * -# Configure to start and stop the timer on external events.(XMC_CCU8_SLICE_StartConfig(), XMC_CCU8_SLICE_StopConfig()) + * -# Modulation, external load and Gating of the timer output.(XMC_CCU8_SLICE_ModulationConfig(), + * XMC_CCU8_SLICE_LoadConfig(), XMC_CCU8_SLICE_GateConfig()) + * -# Control the count direction of the timer based on the external event. (XMC_CCU8_SLICE_DirectionConfig()) + * -# Count the external events.(XMC_CCU8_SLICE_CountConfig()) + * -# External Trap. Which can be used as protective feature.(XMC_CCU8_SLICE_EnableTrap(), XMC_CCU8_SLICE_DisableTrap(), + * XMC_CCU8_SLICE_TrapConfig()) + * + * \par Interrupt configuration: + * This section of the LLD provides the function to configure the interrupt node to each event (XMC_CCU8_SLICE_SetInterruptNode()) + * + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_CCU8_SLICE_CHECK_INTERRUPT(interrupt) \ + ((interrupt == XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_1) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_1)|| \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_2) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_2)|| \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_EVENT0) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_EVENT1) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_EVENT2) || \ + (interrupt == XMC_CCU8_SLICE_IRQ_ID_TRAP)) + +/* Macro to check if the slice ptr passed is valid */ +#define XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(cmp_channel) \ + ((cmp_channel == XMC_CCU8_SLICE_COMPARE_CHANNEL_1) || \ + (cmp_channel == XMC_CCU8_SLICE_COMPARE_CHANNEL_2)) + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/** + * Typedef for CCU8 Global data structure + */ +typedef CCU8_GLOBAL_TypeDef XMC_CCU8_MODULE_t; + +/** + * Typedef for CCU8 Slice data structure + */ +typedef CCU8_CC8_TypeDef XMC_CCU8_SLICE_t; + +/** + * Return Value of an API + */ +typedef enum XMC_CCU8_STATUS +{ + XMC_CCU8_STATUS_OK = 0U, /**< API fulfils request */ + XMC_CCU8_STATUS_ERROR , /**< API cannot fulfil request */ + XMC_CCU8_STATUS_RUNNING , /**< The timer slice is currently running */ + XMC_CCU8_STATUS_IDLE /**< The timer slice is currently idle */ +} XMC_CCU8_STATUS_t; + +/** + * CCU8 module clock + */ +typedef enum XMC_CCU8_CLOCK +{ + XMC_CCU8_CLOCK_SCU = 0U, /**< Select the fCCU as the clock */ + XMC_CCU8_CLOCK_EXTERNAL_A , /**< External clock-A */ + XMC_CCU8_CLOCK_EXTERNAL_B , /**< External clock-B */ + XMC_CCU8_CLOCK_EXTERNAL_C /**< External clock-C */ +} XMC_CCU8_CLOCK_t; + +/** + * CCU8 set the shadow transfer type for multichannel mode + */ +typedef enum XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER +{ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0 = (uint32_t)0x4000000, /**< Shadow transfer through software + only for slice 0*/ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0 = (uint32_t)0x4000400, /**< Shadow transfer through software + and hardware for slice 0 */ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1 = (uint32_t)0x8000000, /**< Shadow transfer through software + only for slice 1*/ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1 = (uint32_t)0x8000800, /**< Shadow transfer through software + and hardware for slice 1 */ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2 = (uint32_t)0x10000000, /**< Shadow transfer through software + only for slice 2 */ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE2 = (uint32_t)0x10001000, /**< Shadow transfer through software + and hardware for slice 2 */ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE3 = (uint32_t)0x20000000, /**< Shadow transfer through software + only for slice 3*/ + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE3 = (uint32_t)0x20002000 /**< Shadow transfer through software + and hardware for slice 3 */ +} XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_t; + +/** + * Operational modes of CCU8 slice + */ +typedef enum XMC_CCU8_SLICE_MODE +{ + XMC_CCU8_SLICE_MODE_COMPARE = 0U, /**< slice(CC8y) operates in Compare Mode */ + XMC_CCU8_SLICE_MODE_CAPTURE /**< slice(CC8y) operates in Capture Mode */ +} XMC_CCU8_SLICE_MODE_t; + +/** + * Slice Output selection + */ +typedef enum XMC_CCU8_SLICE_OUTPUT +{ + XMC_CCU8_SLICE_OUTPUT_0 = 1U, /**< Slice Output-0 */ + XMC_CCU8_SLICE_OUTPUT_1 = 2U, /**< Slice Output-1 */ + XMC_CCU8_SLICE_OUTPUT_2 = 4U, /**< Slice Output-2 */ + XMC_CCU8_SLICE_OUTPUT_3 = 8U /**< Slice Output-3 */ +} XMC_CCU8_SLICE_OUTPUT_t; + +/** + * Timer counting modes for the slice + */ +typedef enum XMC_CCU8_SLICE_TIMER_COUNT_MODE +{ + XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA = 0U, /**< Edge Aligned Mode */ + XMC_CCU8_SLICE_TIMER_COUNT_MODE_CA /**< Centre Aligned Mode */ +} XMC_CCU8_SLICE_TIMER_COUNT_MODE_t; + +/** + * Timer repetition mode for the slice + */ +typedef enum XMC_CCU8_SLICE_TIMER_REPEAT_MODE +{ + XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT = 0U, /**< Repetitive mode: continuous mode of operation */ + XMC_CCU8_SLICE_TIMER_REPEAT_MODE_SINGLE /**< Single shot mode: Once a Period match/One match + occurs timer goes to idle state */ +} XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t; + +/** + * Timer counting direction for the CCU8 slice + */ +typedef enum XMC_CCU8_SLICE_TIMER_COUNT_DIR +{ + XMC_CCU8_SLICE_TIMER_COUNT_DIR_UP = 0U, /**< Counting up */ + XMC_CCU8_SLICE_TIMER_COUNT_DIR_DOWN /**< Counting down */ +} XMC_CCU8_SLICE_TIMER_COUNT_DIR_t; + +/** + * Capture mode register sets + */ +typedef enum XMC_CCU8_SLICE_CAP_REG_SET +{ + XMC_CCU8_SLICE_CAP_REG_SET_LOW = 0U, /**< Capture register-0, Capture register-1 used */ + XMC_CCU8_SLICE_CAP_REG_SET_HIGH /**< Capture register-0, Capture register-1 used */ +} XMC_CCU8_SLICE_CAP_REG_SET_t; + +/** + * Prescaler mode + */ +typedef enum XMC_CCU8_SLICE_PRESCALER_MODE +{ + XMC_CCU8_SLICE_PRESCALER_MODE_NORMAL = 0U, /**< Fixed division of module clock */ + XMC_CCU8_SLICE_PRESCALER_MODE_FLOAT /**< Floating divider */ +} XMC_CCU8_SLICE_PRESCALER_MODE_t; + +/** + * Timer output passive level + */ +typedef enum XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL +{ + XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_LOW = 0U, /**< Passive level = Low */ + XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH /**< Passive level = High */ +} XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t; + +/** + * Compare Channel selection + */ +typedef enum XMC_CCU8_SLICE_COMPARE_CHANNEL +{ + XMC_CCU8_SLICE_COMPARE_CHANNEL_1 = 0U, /**< Compare Channel-1 */ + XMC_CCU8_SLICE_COMPARE_CHANNEL_2 /**< Compare Channel-2 */ +} XMC_CCU8_SLICE_COMPARE_CHANNEL_t; + +/** + * Timer clock Divider + */ +typedef enum XMC_CCU8_SLICE_PRESCALER +{ + XMC_CCU8_SLICE_PRESCALER_1 = 0U, /**< Slice Clock = fccu8 */ + XMC_CCU8_SLICE_PRESCALER_2 , /**< Slice Clock = fccu8/2 */ + XMC_CCU8_SLICE_PRESCALER_4 , /**< Slice Clock = fccu8/4 */ + XMC_CCU8_SLICE_PRESCALER_8 , /**< Slice Clock = fccu8/8 */ + XMC_CCU8_SLICE_PRESCALER_16 , /**< Slice Clock = fccu8/16 */ + XMC_CCU8_SLICE_PRESCALER_32 , /**< Slice Clock = fccu8/32 */ + XMC_CCU8_SLICE_PRESCALER_64 , /**< Slice Clock = fccu8/64 */ + XMC_CCU8_SLICE_PRESCALER_128 , /**< Slice Clock = fccu8/128 */ + XMC_CCU8_SLICE_PRESCALER_256 , /**< Slice Clock = fccu8/256 */ + XMC_CCU8_SLICE_PRESCALER_512 , /**< Slice Clock = fccu8/512 */ + XMC_CCU8_SLICE_PRESCALER_1024 , /**< Slice Clock = fccu8/1024 */ + XMC_CCU8_SLICE_PRESCALER_2048 , /**< Slice Clock = fccu8/2048 */ + XMC_CCU8_SLICE_PRESCALER_4096 , /**< Slice Clock = fccu8/4096 */ + XMC_CCU8_SLICE_PRESCALER_8192 , /**< Slice Clock = fccu8/8192 */ + XMC_CCU8_SLICE_PRESCALER_16384 , /**< Slice Clock = fccu8/16384 */ + XMC_CCU8_SLICE_PRESCALER_32768 /**< Slice Clock = fccu8/32768 */ +} XMC_CCU8_SLICE_PRESCALER_t; + +/** + * Dead Time Generator Clock Divider + */ +typedef enum XMC_CCU8_SLICE_DTC_DIV +{ + XMC_CCU8_SLICE_DTC_DIV_1 = 0U, /**< DTC clock = Slice Clock */ + XMC_CCU8_SLICE_DTC_DIV_2 , /**< DTC clock = Slice Clock/2 */ + XMC_CCU8_SLICE_DTC_DIV_4 , /**< DTC clock = Slice Clock/4 */ + XMC_CCU8_SLICE_DTC_DIV_8 /**< DTC clock = Slice Clock/8 */ +} XMC_CCU8_SLICE_DTC_DIV_t; + + +/** + * The compare channel output which is routed to the slice output signal(STy). + */ +typedef enum XMC_CCU8_SLICE_STATUS +{ + XMC_CCU8_SLICE_STATUS_CHANNEL_1 = 0U, /**< Channel-1 status connected to Slice Status */ + XMC_CCU8_SLICE_STATUS_CHANNEL_2 , /**< Channel-2 status connected to Slice Status */ + XMC_CCU8_SLICE_STATUS_CHANNEL_1_AND_2 , /**< \b Wired \b AND of Channel-1 and Channel-2 status connected to + Slice status */ +#if ((UC_SERIES == XMC13) || (UC_SERIES == XMC14)) || defined(DOXYGEN) + XMC_CCU8_SLICE_STATUS_CHANNEL_1_OR_2 /**< \b Wired \b OR of Channel-1 and Channel-2 status connected to Slice + status. @note Only available for XMC1300 and XMC1400 series */ +#endif +} XMC_CCU8_SLICE_STATUS_t; + +/** + * Compare channel for which modulation has to be applied + */ +typedef enum XMC_CCU8_SLICE_MODULATION_CHANNEL +{ + XMC_CCU8_SLICE_MODULATION_CHANNEL_NONE = 0U, /**< No modulation */ + XMC_CCU8_SLICE_MODULATION_CHANNEL_1 , /**< Modulation for Compare Channel-1 */ + XMC_CCU8_SLICE_MODULATION_CHANNEL_2 , /**< Modulation for Compare Channel-2 */ + XMC_CCU8_SLICE_MODULATION_CHANNEL_1_AND_2 /**< Modulation for Compare Channel-1 and Compare Channel-2 */ +} XMC_CCU8_SLICE_MODULATION_CHANNEL_t; + +/** + * External Function list + */ +typedef enum XMC_CCU8_SLICE_FUNCTION +{ + XMC_CCU8_SLICE_FUNCTION_START = 0U, /**< Start function */ + XMC_CCU8_SLICE_FUNCTION_STOP , /**< Stop function */ + XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT0 , /**< Capture Event-0 function, CCycapt0 signal is used for event + generation */ + XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT1 , /**< Capture Event-1 function, CCycapt1 signal is used for event + generation */ + XMC_CCU8_SLICE_FUNCTION_GATING , /**< Gating function */ + XMC_CCU8_SLICE_FUNCTION_DIRECTION , /**< Direction function */ + XMC_CCU8_SLICE_FUNCTION_LOAD , /**< Load function */ + XMC_CCU8_SLICE_FUNCTION_COUNT , /**< Counting function */ + XMC_CCU8_SLICE_FUNCTION_OVERRIDE , /**< Override function */ + XMC_CCU8_SLICE_FUNCTION_MODULATION , /**< Modulation function */ + XMC_CCU8_SLICE_FUNCTION_TRAP /**< Trap function */ +} XMC_CCU8_SLICE_FUNCTION_t; + +/** + * External Event list + */ +typedef enum XMC_CCU8_SLICE_EVENT +{ + XMC_CCU8_SLICE_EVENT_NONE = 0U, /**< None */ + XMC_CCU8_SLICE_EVENT_0 , /**< Event-0 */ + XMC_CCU8_SLICE_EVENT_1 , /**< Event-1 */ + XMC_CCU8_SLICE_EVENT_2 /**< Event-2 */ +} XMC_CCU8_SLICE_EVENT_t; + +/** + * External Event trigger criteria - Edge sensitivity + */ +typedef enum XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY +{ + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_NONE = 0U, /**< None */ + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE , /**< Rising Edge of the input signal generates + event trigger */ + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE , /**< Falling Edge of the input signal generates event + trigger */ + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE /**< Both Rising and Falling edges cause an event trigger */ +} XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_t; + +/** + * External Event trigger criteria - Level sensitivity + */ +typedef enum XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY +{ + XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH = 0U, /**< Level sensitive functions react to a high signal level*/ + XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW = 1U, /**< Level sensitive functions react to a low signal level */ + /* Below enum items can be utilised specific to the functionality */ + XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW = 0U, /**< Timer counts up, during Low state of the control signal */ + XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH = 1U /**< Timer counts up, during High state of the control signal */ +} XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_t; + +/** + * Low pass filter Configuration. The External Event input should be stable for a selected number of clock cycles. + */ +typedef enum XMC_CCU8_SLICE_EVENT_FILTER +{ + XMC_CCU8_SLICE_EVENT_FILTER_DISABLED = 0U, /**< No Low Pass Filtering is applied */ + XMC_CCU8_SLICE_EVENT_FILTER_3_CYCLES , /**< Input should be stable for 3 clock cycles */ + XMC_CCU8_SLICE_EVENT_FILTER_5_CYCLES , /**< Input should be stable for 5 clock cycles */ + XMC_CCU8_SLICE_EVENT_FILTER_7_CYCLES /**< Input should be stable for 7 clock cycles */ +} XMC_CCU8_SLICE_EVENT_FILTER_t; + +/** + * External Event Input list. This list depicts the possible input connections to the CCU8 slice. + * Interconnects are specific to each device. + */ +typedef uint8_t XMC_CCU8_SLICE_INPUT_t; + + +/** + * Actions that can be performed upon detection of an external Timer STOP event + */ +typedef enum XMC_CCU8_SLICE_END_MODE +{ + XMC_CCU8_SLICE_END_MODE_TIMER_STOP = 0U, /**< Stops the timer, without clearing TIMER register */ + XMC_CCU8_SLICE_END_MODE_TIMER_CLEAR , /**< Without stopping timer, clears the TIMER register */ + XMC_CCU8_SLICE_END_MODE_TIMER_STOP_CLEAR /**< Stops the timer and clears the TIMER register */ +} XMC_CCU8_SLICE_END_MODE_t; + +/** + * Actions that can be performed upon detection of an external Timer START event + */ +typedef enum XMC_CCU8_SLICE_START_MODE +{ + XMC_CCU8_SLICE_START_MODE_TIMER_START = 0U, /**< Start the timer from the current count of TIMER register */ + XMC_CCU8_SLICE_START_MODE_TIMER_START_CLEAR /**< Clears the TIMER register and start the timer */ +} XMC_CCU8_SLICE_START_MODE_t; + +/** + * Modulation of timer output signals + */ +typedef enum XMC_CCU8_SLICE_MODULATION_MODE +{ + XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_ST_OUT = 0U, /**< Clear ST and OUT signals */ + XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_OUT /**< Clear only the OUT signal */ +} XMC_CCU8_SLICE_MODULATION_MODE_t; + +/** + * Trap exit mode + */ +typedef enum XMC_CCU8_SLICE_TRAP_EXIT_MODE +{ + XMC_CCU8_SLICE_TRAP_EXIT_MODE_AUTOMATIC = 0U, /**< Clear trap state as soon as the trap signal is de-asserted */ + XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW /**< Clear only when acknowledged by software */ +} XMC_CCU8_SLICE_TRAP_EXIT_MODE_t; + +/** + * Timer clear on capture + */ +typedef enum XMC_CCU8_SLICE_TIMER_CLEAR_MODE +{ + XMC_CCU8_SLICE_TIMER_CLEAR_MODE_NEVER = 0U, /**< Never clear the timer on any capture event */ + XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_HIGH , /**< Clear only when timer value has been captured in C3V and C2V */ + XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_LOW , /**< Clear only when timer value has been captured in C1V and C0V */ + XMC_CCU8_SLICE_TIMER_CLEAR_MODE_ALWAYS /**< Always clear the timer upon detection of any capture event */ +} XMC_CCU8_SLICE_TIMER_CLEAR_MODE_t; + +/** + * Multi Channel Shadow transfer request configuration options + */ +typedef enum XMC_CCU8_SLICE_MCMS_ACTION +{ + XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR = 0U, /**< Transfer Compare and Period Shadow register values to + the actual registers upon MCS xfer request */ + XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP = 1U, /**< Transfer Compare, Period and Prescaler Compare Shadow + register values to the actual registers upon MCS xfer + request */ + XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT = 3U /**< Transfer Compare, Period ,Prescaler Compare and Dither + Compare register values to the actual registers upon + MCS xfer request */ +} XMC_CCU8_SLICE_MCMS_ACTION_t; + +/** + * Available Interrupt Event Ids + */ +typedef enum XMC_CCU8_SLICE_IRQ_ID +{ + XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH = 0U , /**< Period match counting up */ + XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH = 1U , /**< One match counting down */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_1 = 2U , /**< Compare match counting up for channel 1 */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_1 = 3U , /**< Compare match counting down for channel 1 */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_2 = 4U , /**< Compare match counting up for channel 2 */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_2 = 5U , /**< Compare match counting down for channel 2 */ + XMC_CCU8_SLICE_IRQ_ID_EVENT0 = 8U , /**< Event-0 occurrence */ + XMC_CCU8_SLICE_IRQ_ID_EVENT1 = 9U , /**< Event-1 occurrence */ + XMC_CCU8_SLICE_IRQ_ID_EVENT2 = 10U, /**< Event-2 occurrence */ + XMC_CCU8_SLICE_IRQ_ID_TRAP = 11U /**< Trap occurrence */ +} XMC_CCU8_SLICE_IRQ_ID_t; + +/** + * Available Interrupt Event Ids, which is added to support multi event APIs + */ +typedef enum XMC_CCU8_SLICE_MULTI_IRQ_ID +{ + XMC_CCU8_SLICE_MULTI_IRQ_ID_PERIOD_MATCH = 0x1U, /**< Period match counting up */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_ONE_MATCH = 0x2U, /**< One match counting down */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP_CH_1 = 0x4U, /**< Compare match counting up for channel 1 */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN_CH_1 = 0x8U, /**< Compare match counting down for channel 1 */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP_CH_2 = 0x10U, /**< Compare match counting up for channel 2 */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN_CH_2 = 0x20U, /**< Compare match counting down for channel 2 */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT0 = 0x100U, /**< Event-0 occurrence */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT1 = 0x200U, /**< Event-1 occurrence */ + XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT2 = 0x400U, /**< Event-2 occurrence */ +} XMC_CCU8_SLICE_MULTI_IRQ_ID_t; + +/** + * Service Request Lines for CCU8. Event are mapped to these SR lines and these are used to generate the interrupt. + */ +typedef enum XMC_CCU8_SLICE_SR_ID +{ + XMC_CCU8_SLICE_SR_ID_0 = 0U, /**< Service Request Line-0 selected */ + XMC_CCU8_SLICE_SR_ID_1 , /**< Service Request Line-1 selected */ + XMC_CCU8_SLICE_SR_ID_2 , /**< Service Request Line-2 selected */ + XMC_CCU8_SLICE_SR_ID_3 /**< Service Request Line-3 selected */ +} XMC_CCU8_SLICE_SR_ID_t; + + +/** + * Slice shadow transfer options. + */ +typedef enum XMC_CCU8_SHADOW_TRANSFER +{ + XMC_CCU8_SHADOW_TRANSFER_SLICE_0 = CCU8_GCSS_S0SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-0 */ + XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_0 = CCU8_GCSS_S0DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-0 */ + XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_0 = CCU8_GCSS_S0PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-0 */ + XMC_CCU8_SHADOW_TRANSFER_SLICE_1 = CCU8_GCSS_S1SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-1 */ + XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_1 = CCU8_GCSS_S1DSE_Msk, /**< Transfer Dither compare shadow register value + to actual registers for SLICE-1 */ + XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_1 = CCU8_GCSS_S1PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-1 */ + XMC_CCU8_SHADOW_TRANSFER_SLICE_2 = CCU8_GCSS_S2SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-2 */ + XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_2 = CCU8_GCSS_S2DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-2 */ + XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_2 = CCU8_GCSS_S2PSE_Msk, /**< Transfer Prescaler shadow register value to + actual register for SLICE-2 */ + XMC_CCU8_SHADOW_TRANSFER_SLICE_3 = CCU8_GCSS_S3SE_Msk, /**< Transfer Period, Compare and Passive Level + shadow register values to actual registers for + SLICE-3 */ + XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_3 = CCU8_GCSS_S3DSE_Msk, /**< Transfer Dither compare shadow register value + to actual register for SLICE-3 */ + XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_3 = CCU8_GCSS_S3PSE_Msk /**< Transfer Prescaler shadow register value to + actual register for SLICE-3 */ +} XMC_CCU8_SHADOW_TRANSFER_t; + +#if (UC_SERIES != XMC45) || defined(DOXYGEN) +/** + * Slice shadow transfer mode options. + * @note Not available for XMC4500 series + */ +typedef enum XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE +{ + XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_IN_PERIOD_MATCH_AND_ONE_MATCH = 0U, /**< Shadow transfer is done in Period Match and + One match. */ + XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH = 1U, /**< Shadow transfer is done only in Period Match. */ + XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_ONE_MATCH = 2U /**< Shadow transfer is done only in One Match. */ +} XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t; +#endif + +#if defined(CCU8V3) || defined(DOXYGEN) /* Defined for XMC1400 devices only */ +/** + * Output sources for OUTy0 signal + * @note Only available for XMC1400 series + */ + typedef enum XMC_CCU8_SOURCE_OUT0 +{ + XMC_CCU8_SOURCE_OUT0_ST1 = (uint32_t)0x0, /**< CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_SOURCE_OUT0_INV_ST1 = (uint32_t)0x1, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_SOURCE_OUT0_ST2 = (uint32_t)0x2, /**< CCU8yST2 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_SOURCE_OUT0_INV_ST2 = (uint32_t)0x3 /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT0 */ +} XMC_CCU8_SOURCE_OUT0_t; + +/** + * Output sources for OUTy1 signal + * @note Only available for XMC1400 series + */ + typedef enum XMC_CCU8_SOURCE_OUT1 +{ + XMC_CCU8_SOURCE_OUT1_ST1 = (uint32_t)0x1, /**< CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_SOURCE_OUT1_INV_ST1 = (uint32_t)0x0, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_SOURCE_OUT1_ST2 = (uint32_t)0x3, /**< CCU8yST2 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_SOURCE_OUT1_INV_ST2 = (uint32_t)0x2 /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT1 */ +} XMC_CCU8_SOURCE_OUT1_t; + +/** + * Output sources for OUTy2 signal + * @note Only available for XMC1400 series + */ + typedef enum XMC_CCU8_SOURCE_OUT2 +{ + XMC_CCU8_SOURCE_OUT2_ST2 = (uint32_t)0x0, /**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT2_INV_ST2 = (uint32_t)0x1, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT2_ST1 = (uint32_t)0x2, /**< CCU8yST1 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT2_INV_ST1 = (uint32_t)0x3 /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT2 */ +} XMC_CCU8_SOURCE_OUT2_t; + +/** + * Output sources for OUTy3 signal + * @note Only available for XMC1400 series + */ + typedef enum XMC_CCU8_SOURCE_OUT3 +{ + XMC_CCU8_SOURCE_OUT3_ST2 = (uint32_t)0x1, /**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT3_INV_ST2 = (uint32_t)0x0, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT3_ST1 = (uint32_t)0x3, /**< CCU8yST1 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_SOURCE_OUT3_INV_ST1 = (uint32_t)0x2 /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT2 */ +} XMC_CCU8_SOURCE_OUT3_t; +#endif + + +/** + * Output selector for CCU8x.OUT0-3 + */ +#if !defined(CCU8V3) /* Defined for all devices except XMC1400 */ +typedef enum XMC_CCU8_OUT_PATH +{ + XMC_CCU8_OUT_PATH_OUT0_ST1 = (uint32_t)0x20000, /**< CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_OUT_PATH_OUT0_INV_ST1 = (uint32_t)0x20002, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_OUT_PATH_OUT1_ST1 = (uint32_t)0x40000, /**< CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_OUT_PATH_OUT1_INV_ST1 = (uint32_t)0x40004, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_OUT_PATH_OUT2_ST2 = (uint32_t)0x80000, /**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_OUT_PATH_OUT2_INV_ST2 = (uint32_t)0x80008, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_OUT_PATH_OUT3_ST2 = (uint32_t)0x100000,/**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_OUT_PATH_OUT3_INV_ST1 = (uint32_t)0x100010 /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT3 */ +} XMC_CCU8_OUT_PATH_t; +#else +typedef enum XMC_CCU8_OUT_PATH +{ + XMC_CCU8_OUT_PATH_OUT0_ST1 = (uint32_t)0x000C0, /**< CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_OUT_PATH_OUT0_INV_ST1 = (uint32_t)0x000D0, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT0 */ + XMC_CCU8_OUT_PATH_OUT0_ST2 = (uint32_t)0x000E0, /**< CCU8yST2 signal path is connected the CCU8x.OUT0. @note Only available for XMC1400 series*/ + XMC_CCU8_OUT_PATH_OUT0_INV_ST2 = (uint32_t)0x000F0, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT0. @note Only available for XMC1400 series*/ + XMC_CCU8_OUT_PATH_OUT1_ST1 = (uint32_t)0x00D00, /**< CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_OUT_PATH_OUT1_INV_ST1 = (uint32_t)0x00C00, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT1 */ + XMC_CCU8_OUT_PATH_OUT1_ST2 = (uint32_t)0x00F00, /**< CCU8yST2 signal path is connected the CCU8x.OUT1. @note Only available for XMC1400 series*/ + XMC_CCU8_OUT_PATH_OUT1_INV_ST2 = (uint32_t)0x00E00, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT1. @note Only available for XMC1400 series */ + XMC_CCU8_OUT_PATH_OUT2_ST2 = (uint32_t)0x0C000, /**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_OUT_PATH_OUT2_INV_ST2 = (uint32_t)0x0D000, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT2 */ + XMC_CCU8_OUT_PATH_OUT2_ST1 = (uint32_t)0x0E000, /**< CCU8yST1 signal path is connected the CCU8x.OUT2. @note Only available for XMC1400 series*/ + XMC_CCU8_OUT_PATH_OUT2_INV_ST1 = (uint32_t)0x0F000, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT2.@note Only available for XMC1400 series */ + XMC_CCU8_OUT_PATH_OUT3_ST2 = (uint32_t)0xD0000, /**< CCU8yST2 signal path is connected the CCU8x.OUT3 */ + XMC_CCU8_OUT_PATH_OUT3_INV_ST2 = (uint32_t)0xC0000, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT3.@note Only available for XMC1400 series */ + XMC_CCU8_OUT_PATH_OUT3_ST1 = (uint32_t)0xF0000, /**< CCU8yST1 signal path is connected the CCU8x.OUT3.@note Only available for XMC1400 series */ + XMC_CCU8_OUT_PATH_OUT3_INV_ST1 = (uint32_t)0xE0000 /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT3 */ +} XMC_CCU8_OUT_PATH_t; + +/** + * Immediate write into configuration register + * @note Only available for XMC1400 series + */ +typedef enum XMC_CCU8_SLICE_WRITE_INTO +{ + XMC_CCU8_SLICE_WRITE_INTO_PERIOD_CONFIGURATION = CCU8_CC8_STC_IRPC_Msk, /**< Immediate or Coherent + Write into Period + Configuration */ + XMC_CCU8_SLICE_WRITE_INTO_COMPARE1_CONFIGURATION = CCU8_CC8_STC_IRCC1_Msk, /**< Immediate or Coherent + Write into Compare 1 + Configuration */ + XMC_CCU8_SLICE_WRITE_INTO_COMPARE2_CONFIGURATION = CCU8_CC8_STC_IRCC2_Msk, /**< Immediate or Coherent + Write into Compare 2 + Configuration */ + XMC_CCU8_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION = CCU8_CC8_STC_IRLC_Msk, /**< Immediate or Coherent + Write into Passive Level + Configuration */ + XMC_CCU8_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION = CCU8_CC8_STC_IRDC_Msk, /**< Immediate or Coherent + Write into Dither Value + Configuration */ + XMC_CCU8_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION = CCU8_CC8_STC_IRFC_Msk /**< Immediate or Coherent + Write into Floating Prescaler + Value Configuration */ +} XMC_CCU8_SLICE_WRITE_INTO_t; + + +/** + * Automatic Shadow Transfer request when writing into shadow register + * @note Only available for XMC1400 series + */ +typedef enum XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO +{ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PERIOD_SHADOW = CCU8_CC8_STC_ASPC_Msk, /**< Automatic Shadow + Transfer request when + writing into Period + Shadow Register */ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_COMPARE1_SHADOW = CCU8_CC8_STC_ASCC1_Msk, /**< Automatic Shadow + transfer request + when writing into + Compare 1 Shadow Register */ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_COMPARE2_SHADOW = CCU8_CC8_STC_ASCC2_Msk, /**< Automatic Shadow + transfer request + when writing into + Compare 2 Shadow Register */ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PASSIVE_LEVEL = CCU8_CC8_STC_ASLC_Msk, /**< Automatic Shadow transfer + request when writing + into Passive Level Register*/ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_DITHER_SHADOW = CCU8_CC8_STC_ASDC_Msk, /**< Automatic Shadow transfer + request when writing + into Dither Shadow Register */ + XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_FLOATING_PRESCALER_SHADOW = CCU8_CC8_STC_ASFC_Msk /**< Automatic Shadow transfer + request when writing + into Floating Prescaler Shadow + register */ + +} XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t; +#endif +/** + * CCU8 slice mask which can be used for the APIs as input where multi slice support is available + */ +typedef enum XMC_CCU8_SLICE_MASK +{ + XMC_CCU8_SLICE_MASK_SLICE_0 = 1U , /**< SLICE-0 */ + XMC_CCU8_SLICE_MASK_SLICE_1 = 2U , /**< SLICE-1 */ + XMC_CCU8_SLICE_MASK_SLICE_2 = 4U , /**< SLICE-2 */ + XMC_CCU8_SLICE_MASK_SLICE_3 = 8U /**< SLICE-3 */ +} XMC_CCU8_SLICE_MASK_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/** + * Configuration data structure of an External Event(Event-0/1/2). + * Needed to configure the various aspects of an External Event. + * This structure will not connect the external event with an external function. + */ +typedef struct XMC_CCU8_SLICE_EVENT_CONFIG +{ + XMC_CCU8_SLICE_INPUT_t mapped_input; /**< Required input signal for the Event. */ + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_t edge; /**< Select the event edge of the input signal. + This is needed for an edge sensitive External function.*/ + XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_t level; /**< Select the event level of the input signal. + This is needed for an level sensitive External function.*/ + XMC_CCU8_SLICE_EVENT_FILTER_t duration; /**< Low Pass filter duration in terms of fCCU clock cycles. */ +} XMC_CCU8_SLICE_EVENT_CONFIG_t; + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Dead Time configuration + */ +typedef struct XMC_CCU8_SLICE_DEAD_TIME_CONFIG +{ + union + { + struct + { + uint32_t enable_dead_time_channel1 : 1; /**< Enable dead time for Compare Channel-1 */ + uint32_t enable_dead_time_channel2 : 1; /**< Enable dead time for Compare Channel-2 */ + uint32_t channel1_st_path : 1; /**< Should dead time be applied to ST output of Compare Channel-1? */ + uint32_t channel1_inv_st_path : 1; /**< Should dead time be applied to inverse ST output of + Compare Channel-1? */ + uint32_t channel2_st_path : 1; /**< Should dead time be applied to ST output of Compare Channel-2? */ + uint32_t channel2_inv_st_path : 1; /**< Should dead time be applied to inverse ST output of + Compare Channel-2? */ + uint32_t div : 2; /**< Dead time prescaler divider value. + Accepts enum ::XMC_CCU8_SLICE_DTC_DIV_t*/ + uint32_t : 24; + }; + uint32_t dtc; + }; + union + { + struct + { + uint32_t channel1_st_rising_edge_counter : 8; /**< Contains the delay value that is applied to the rising edge + for compare channel-1. Range: [0x0 to 0xFF] */ + uint32_t channel1_st_falling_edge_counter : 8; /**< Contains the delay value that is applied to the falling edge + for compare channel-1. Range: [0x0 to 0xFF] */ + uint32_t : 16; + }; + uint32_t dc1r; + }; + union + { + struct + { + uint32_t channel2_st_rising_edge_counter : 8; /**< Contains the delay value that is applied to the rising edge + for compare channel-2. Range: [0x0 to 0xFF]*/ + uint32_t channel2_st_falling_edge_counter : 8; /**< Contains the delay value that is applied to the falling edge + for compare channel-2. Range: [0x0 to 0xFF]*/ + uint32_t : 16; + }; + uint32_t dc2r; + }; +} XMC_CCU8_SLICE_DEAD_TIME_CONFIG_t; + +/** + * Configuration data structure for CCU8 slice. Specifically configures the CCU8 slice to compare mode operation. + * This excludes event and function configuration. + */ +typedef struct XMC_CCU8_SLICE_COMPARE_CONFIG +{ + union + { + struct + { + uint32_t timer_mode : 1; /**< Edge aligned or Centre Aligned. + Accepts enum :: XMC_CCU8_SLICE_TIMER_COUNT_MODE_t */ + uint32_t monoshot : 1; /**< Single shot or Continuous mode . + Accepts enum :: XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t */ + uint32_t shadow_xfer_clear : 1; /**< Should PR and CR shadow xfer happen when timer is cleared? */ + uint32_t : 10; + uint32_t dither_timer_period: 1; /**< Can the period of the timer dither? */ + uint32_t dither_duty_cycle : 1; /**< Can the compare match of the timer dither? */ + uint32_t : 1; + uint32_t prescaler_mode: 1; /**< Normal or floating prescaler mode. + Accepts enum :: XMC_CCU8_SLICE_PRESCALER_MODE_t */ + uint32_t : 8; + uint32_t mcm_ch1_enable : 1; /**< Multi-Channel mode for compare channel 1 enable? */ + uint32_t mcm_ch2_enable : 1; /**< Multi-Channel mode for compare channel 2 enable? */ + uint32_t : 2; + uint32_t slice_status : 2; /**< Which of the two channels drives the slice status output. + Accepts enum :: XMC_CCU8_SLICE_STATUS_t*/ + uint32_t : 1; + }; + uint32_t tc; + }; + union + { + struct + { + uint32_t passive_level_out0 : 1; /**< ST and OUT passive levels Configuration for OUT0. + Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ + uint32_t passive_level_out1 : 1; /**< ST and OUT passive levels Configuration for OUT1. + Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ + uint32_t passive_level_out2 : 1; /**< ST and OUT passive levels Configuration for OUT2. + Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ + uint32_t passive_level_out3 : 1; /**< ST and OUT passive levels Configuration for OUT3. + Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ + uint32_t : 28; + }; + uint32_t psl; + }; + union + { + struct + { + uint32_t asymmetric_pwm : 1; /**< Should the PWM be a function of the 2 compare channels + rather than period value? */ + #if !defined(CCU8V3) /* Defined for all devices except XMC1400 */ + uint32_t invert_out0 : 1; /**< Should inverted ST of Channel-1 be connected to OUT0? */ + uint32_t invert_out1 : 1; /**< Should inverted ST of Channel-1 be connected to OUT1? */ + uint32_t invert_out2 : 1; /**< Should inverted ST of Channel-2 be connected to OUT2? */ + uint32_t invert_out3 : 1; /**< Should inverted ST of Channel-2 be connected to OUT3? */ + uint32_t : 27; + #else + uint32_t : 3; + uint32_t selector_out0 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT0 + Accepts enum :: XMC_CCU8_SOURCE_OUT0_t + refer OCS1 bit-field of CHC register. + @note Only available for XMC1400 series */ + uint32_t : 2; + uint32_t selector_out1 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT1 + Accepts enum :: XMC_CCU8_SOURCE_OUT1_t + refer OCS2 bit-field of CHC register. + @note Only available for XMC1400 series */ + uint32_t : 2; + uint32_t selector_out2 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT2 + Accepts enum :: XMC_CCU8_SOURCE_OUT2_t + refer OCS3 bit-field of CHC register. + @note Only available for XMC1400 series */ + uint32_t : 2; + uint32_t selector_out3 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT3 + Accepts enum :: XMC_CCU8_SOURCE_OUT3_t + refer OCS4 bit-field of CHC register. + @note Only available for XMC1400 series */ + uint32_t : 14; + #endif + }; + uint32_t chc; + }; + uint32_t prescaler_initval : 4; /**< Initial prescaler divider value + Accepts enum :: XMC_CCU8_SLICE_PRESCALER_t */ + uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to. + Range : [0 to 15] */ + uint32_t dither_limit : 4; /**< The value that determines the spreading of dithering + Range : [0 to 15] */ + uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer if true*/ +} XMC_CCU8_SLICE_COMPARE_CONFIG_t; + +/** + * Configuration data structure for CCU8 slice. Specifically configures the CCU8 slice to capture mode operation. + * This excludes event and function configuration. + */ +typedef struct XMC_CCU8_SLICE_CAPTURE_CONFIG +{ + union + { + struct + { + uint32_t : 4; + uint32_t fifo_enable : 1; /**< Should the capture registers be setup as a FIFO?(Extended capture mode) */ + uint32_t timer_clear_mode : 2; /**< How should the timer register be cleared upon detection of capture event? + Accepts enum ::XMC_CCU8_SLICE_TIMER_CLEAR_MODE_t */ + uint32_t : 4; + uint32_t same_event : 1; /**< Should the capture event for C1V/C0V and C3V/C2V be same capture edge? */ + uint32_t ignore_full_flag : 1; /**< Should updates to capture registers follow full flag rules? */ + uint32_t : 3; + uint32_t prescaler_mode: 1; /**< Normal or floating prescaler Accepts enum :: XMC_CCU8_SLICE_PRESCALER_MODE_t*/ + uint32_t : 15; + }; + uint32_t tc; + }; + uint32_t prescaler_initval : 4; /**< Prescaler divider value */ + uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to */ + uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer */ +} XMC_CCU8_SLICE_CAPTURE_CONFIG_t; +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +__STATIC_INLINE bool XMC_CCU8_IsValidModule(const XMC_CCU8_MODULE_t *const module) +{ + bool tmp = false; + + tmp = (module == CCU80); + +#if defined(CCU81) + tmp = tmp || (module == CCU81); +#endif + + return tmp; +} + +__STATIC_INLINE bool XMC_CCU8_IsValidSlice(const XMC_CCU8_SLICE_t *const slice) +{ + bool tmp = false; + + tmp = (slice == CCU80_CC80); +#if defined(CCU80_CC81) + tmp = tmp || (slice == CCU80_CC81); +#endif +#if defined(CCU80_CC82) + tmp = tmp || (slice == CCU80_CC82); +#endif +#if defined(CCU80_CC83) + tmp = tmp || (slice == CCU80_CC83); +#endif +#if defined(CCU81) + tmp = tmp || (slice == CCU81_CC80); +#if defined(CCU81_CC81) + tmp = tmp || (slice == CCU81_CC81); +#endif +#if defined(CCU81_CC82) + tmp = tmp || (slice == CCU81_CC82); +#endif +#if defined(CCU81_CC83) + tmp = tmp || (slice == CCU81_CC83); +#endif +#endif + + return tmp; +} + +/** + * @param module Constant pointer to CCU8 module + * @param mcs_action multi-channel shadow transfer request configuration + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of global register GCTRL.\n\n + * As part of module initialization, behaviour of the module upon detection + * Multi-Channel Mode trigger is configured. Will also invoke the XMC_CCU8_EnableModule(). + * The API call would bring up the required CCU8 module and also initialize the module for + * the required multi-channel shadow transfer. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_CompareInit()
XMC_CCU8_SLICE_CaptureInit(). + */ +void XMC_CCU8_Init(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_SLICE_MCMS_ACTION_t mcs_action); + +/** + * @param module Constant pointer to CCU8 module + * @return
+ * None
+ * + * \parDescription:
+ * Enables the CCU8 module and brings it to active state.\n\n + * Also disables the gating of the clock signal (if applicable depending on the device being selected). + * Invoke this API before any operations are done on the CCU8 module. Invoked from XMC_CCU8_Init(). + * + * \parRelated APIs:
+ * XMC_CCU8_SetModuleClock()
XMC_CCU8_DisableModule()
XMC_CCU8_StartPrescaler(). + */ +void XMC_CCU8_EnableModule(XMC_CCU8_MODULE_t *const module); + +/** + * @param module Constant pointer to CCU8 module + * @return
+ * None
+ * + * \parDescription:
+ * Brings the CCU8 module to reset state and enables gating of the clock signal(if applicable depending + * on the device being selected).\n\n + * Invoke this API when a CCU8 module needs to be disabled completely. + * Any operation on the CCU8 module will have no effect after this API is called. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableModule()
XMC_CCU8_DisableModule(). + */ +void XMC_CCU8_DisableModule(XMC_CCU8_MODULE_t *const module); + +/** + * @param module Constant pointer to CCU8 module + * @param clock Choice of input clock to the module + * @return
+ * None
+ * + * \parDescription:
+ * Selects the Module Clock by configuring GCTRL.PCIS bits.\n\n + * There are 3 potential clock sources. This API helps to select the required clock source. + * Call to this API is valid after the XMC_CCU8_Init(). + * + * \parRelated APIs:
+ * None.
+ */ +void XMC_CCU8_SetModuleClock(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_CLOCK_t clock); + + +/** + * @param module Constant pointer to CCU8 module + * @return
+ * None
+ * + * \parDescription:
+ * Starts the prescaler and restores clocks to the timer slices, by setting GIDLC.SPRB bit.
\n + * Once the input to the prescaler has been chosen and the prescaler divider of all slices programmed, + * the prescaler itself may be started. Invoke this API after XMC_CCU8_Init() + * (Mandatory to fully initialize the module). + * + * \parRelated APIs:
+ * XMC_CCU8_Init()
XMC_CCU8_EnableClock()
XMC_CCU8_DisableClock()
XMC_CCU8_StartPrescaler()
+ * XMC_CCU8_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_StartPrescaler(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_StartPrescaler:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + module->GIDLC |= (uint32_t) CCU8_GIDLC_SPRB_Msk; +} + +/** + * @param module Constant pointer to CCU8 module + * @return
+ * None
+ * + * \parDescription:
+ * Stops the prescaler and blocks clocks to the timer slices, by setting GIDLS.CPRB bit.\n\n + * Clears the run bit of the prescaler. Ensures that the module clock is not supplied to + * the slices of the module. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableClock()
XMC_CCU8_DisableClock()
XMC_CCU8_StartPrescaler()
XMC_CCU8_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_StopPrescaler(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_StopPrescaler:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + module->GIDLS |= (uint32_t) CCU8_GIDLS_CPRB_Msk; +} + +/** + * @param module Constant pointer to CCU8 module + * @return
+ * None
+ * + * \parDescription:
+ * Returns the state of the prescaler, by reading GSTAT.PRB bit.\n\n + * If clock is being supplied to the slices of the module then returns as true. + * + * \parRelated APIs:
+ * XMC_CCU8_StartPrescaler()
XMC_CCU8_StopPrescaler()
XMC_CCU8_EnableClock()
XMC_CCU8_DisableClock(). + */ +__STATIC_INLINE bool XMC_CCU8_IsPrescalerRunning(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_IsPrescalerRunning:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + return((bool)((module->GSTAT & (uint32_t) CCU8_GSTAT_PRB_Msk) == CCU8_GSTAT_PRB_Msk)); +} + +/** + * @param module Constant pointer to CCU8 module + * @param clock_mask Slices whose clocks are to be enabled simultaneously. + * Bit location 0/1/2/3 represents slice-0/1/2/3 respectively. + * Range: [0x1 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Enables clocks of multiple slices at a time, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * GIDLC.CS3I bits.\n\n + * Takes an input clock_mask, which determines the slices that would receive the clock. Bring them out + * of the idle state simultaneously. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableClock()
XMC_CCU8_DisableClock(). + */ +__STATIC_INLINE void XMC_CCU8_EnableMultipleClocks(XMC_CCU8_MODULE_t *const module, const uint8_t clock_mask) +{ + XMC_ASSERT("XMC_CCU8_EnableMultipleClocks:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_EnableMultipleClocks:Invalid clock mask", (clock_mask < 16U)); + + module->GIDLC |= (uint32_t) clock_mask; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param compare_init Pointer to slice configuration structure + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of a CC8 slice to compare mode, by configuring CC8yTC, CC8yCMC, CC8yPSC, CC8yDITH, CC8yPSL, + * CC8yFPCS, CC8yCHC registers.\n\n + * CC8 slice is configured with Timer configurations in this routine. Timer is stopped before initialization + * by calling XMC_CCU8_SLICE_StopTimer(). After initialization user has to explicitly enable + * the shadow transfer for the required values by calling XMC_CCU8_EnableShadowTransfer() with appropriate mask. + * + * \parRelated APIs:
+ * None. + */ +void XMC_CCU8_SLICE_CompareInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CONFIG_t *const compare_init); + +/** + * @param slice Constant pointer to CC8 Slice + * @param capture_init Pointer to slice configuration structure + * @return
+ * None
+ * + * \parDescription:
+ * Initialization of a CC8 slice to capture mode, by configuring CC8yTC, CC8yCMC, CC8yPSC,CC8yFPCS registers.\n\n + * CC8 slice is configured with Capture configurations in this routine. Timer is stopped before initialization + * by calling XMC_CCU8_SLICE_StopTimer(). After initialization user has to explicitly enable the shadow transfer + * for the required values by calling XMC_CCU8_EnableShadowTransfer() with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_Capture0Config()
XMC_CCU8_SLICE_Capture1Config(). + */ +void XMC_CCU8_SLICE_CaptureInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_CAPTURE_CONFIG_t *const capture_init); + +/** + * @param module Constant pointer to CCU8 module + * @param slice_number Slice for which the clock should be Enabled. + * Range: [0x0 to 0x3] + * @return
+ * None
+ * + * \parDescription:
+ * Enables the slice timer clock, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * GIDLC.CS3I bits according to the selected \a slice_number.\n\n + * It is possible to enable/disable clock at slice level. This uses the \b slice_number to indicate the + * slice whose clock needs to be enabled. Directly accessed register is GIDLC. + * + * \parRelated APIs:
+ * XMC_CCU8_DisableClock()
XMC_CCU8_EnableMultipleClocks()
XMC_CCU8_StartPrescaler()
XMC_CCU8_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_EnableClock(XMC_CCU8_MODULE_t *const module, const uint8_t slice_number) +{ + XMC_ASSERT("XMC_CCU8_EnableClock:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_EnableClock:Invalid Slice Number", (slice_number < 4U)); + + module->GIDLC |= ((uint32_t) 1 << slice_number); +} + +/** + * @param module Constant pointer to CCU8 module + * @param slice_number Slice for which the clock should be disabled. + * Range: [0x0 to 0x3] + * @return
+ * None
+ * + * \parDescription:
+ * Disables the slice timer clock, by configuring GIDLS.SS0I, GIDLS.SSS1I, GIDLS.SSS2I, + * GIDLS.SSS3I bits according to the selected \a slice_number .\n\n + * It is possible to disable clock at slice level using the module pointer. + * \b slice_number is used to disable the clock to a given slice of the module. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableClock()
XMC_CCU8_EnableMultipleClocks()
XMC_CCU8_StartPrescaler()
XMC_CCU8_StopPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_DisableClock(XMC_CCU8_MODULE_t *const module, const uint8_t slice_number) +{ + XMC_ASSERT("XMC_CCU8_DisableClock:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_DisableClock:Invalid Slice Number", (slice_number < 4U)); + + module->GIDLS |= ((uint32_t) 1 << slice_number); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param out_path_msk configuration for output path selection. + * combination of XMC_CCU8_OUT_PATH_t enum items can be used to create a mask. + * + * @return
+ * None
+ * + * \parDescription:
+ * Configure the out the path of the two compare channels with specified ST signal, by configuring the + ^ CC8yCHC register.\n\n + * + * For the two compare channels it is possible to select either direct ST signal or inverted ST signal. + * \b out_path_msk is used to set the required out put path. + * + * \parRelated APIs:
+ * None +*/ +void XMC_CCU8_SLICE_SetOutPath(XMC_CCU8_SLICE_t *const slice, const uint32_t out_path_msk); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Start Function + * @param start_mode Behaviour of slice when the start function is activated + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Start Function of the slice, by configuring CC8yCMC.ENDS and CC8yTC.ENDM bits.\n\n + * Start function is mapped with one of the 3 events. An external signal can control when a CC8 timer should start. + * Additionally, the behaviour of the slice upon activation of the start function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StopConfig()
XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_StartConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_START_MODE_t start_mode); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Stop Function + * @param end_mode Behaviour of slice when the stop function is activated + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Stop function for the slice, by configuring CC8yCMC.STRTS and CC8yTC.STRM bits.\n\n + * Stop function is mapped with one of the 3 events. An external signal can control when a CCU8 timer should stop. + * Additionally, the behaviour of the slice upon activation of the stop function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartConfig()
XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_StopConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_END_MODE_t end_mode); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External load Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Load Function for the slice, by configuring CC8yCMC.LDS bit.\n\n + * Load function is mapped with one of the 3 events. Up on occurrence of the event,\n + * if CC8yTCST.CDIR set to 0,CC8yTIMER register is reloaded with the value from compare channel 1 or + * compare channel 2\n + * if CC8yTCST.CDIR set to 1,CC8yTIMER register is reloaded with the value from period register\n + * + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_LoadConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @param ch_num Select which compare channel value has to be loaded to the Timer register during external load event. + * @return
+ * None
+ * + * \parDescription:
+ * Up on occurrence of the external load event, if CC8yTCST.CDIR set to 0, CC8yTIMER register can be reloaded\n + * with the value from compare channel 1 or compare channel 2\n + * If CC8yTC.TLS is 0, compare channel 1 value is loaded to the CC8yTIMER register\n + * If CC8yTC.TLS is 1, compare channel 2 value is loaded to the CC8yTIMER register\n + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_LoadSelector(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Modulation Function + * @param mod_mode Desired Modulation mode + * @param channel Specify the channel(s) on which the modulation should be applied. + * @param synch_with_pwm Option to synchronize modulation with PWM start + * Pass \b true if the modulation needs to be synchronized with PWM signal. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Output Modulation Function of the slice, by configuring CC8yCMC.MOS, CC8yTC.EMT and + * CC8yTC.EMS bits.\n\n + * Modulation function is mapped with one of the 3 events. The output signal of the CCU can + * be modulated according to a external input. Additionally, the behaviour of the slice upon activation + * of the modulation function is configured as well. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_ModulationConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_MODULATION_MODE_t mod_mode, + const XMC_CCU8_SLICE_MODULATION_CHANNEL_t channel, + const bool synch_with_pwm + ); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Count Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Count Function of the slice, by configuring CC8yCMC.CNTS bit.\n\n + * Count function is mapped with one of the 3 events. CCU8 slice can take an external + * signal to act as the counting event. The CCU8 slice would count the + * edges present on the \b event selected. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_CountConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Gating Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Gating Function of the slice, by configuring CC8yCMC.GATES bit.\n\n + * Gating function is mapped with one of the 3 events. A CCU8 slice can use an input signal that would + * operate as counter gating. If the configured Active level is detected the counter will gate all the pulses. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_GateConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the Capture-0 Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Capture-0 Function of the slice, by configuring CC8yCMC.CAP0S bit.\n\n + * Capture function is mapped with one of the 3 events. A CCU8 slice can be configured into capture-0 mode + * with the selected \b event. In this mode the CCU8 will capture the timer value into CC8yC0V and CC8yC1V. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_Capture0Config(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the Capture-1 Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Capture-1 Function of the slice, by configuring CC8yCMC.CAP1S bit.\n\n + * Capture function is mapped with one of the 3 events. A CCU8 slice can be configured into capture-1 + * mode with the selected \b event. In this mode the CCU8 will capture the timer value into CC8yC2V and CC8yC3V. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_Capture1Config(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * bool would return true if the extended capture read back mode is enabled
+ * + * \parDescription:
+ * Checks if Extended capture mode read is enabled for particular slice or not, by reading CC8yTC.ECM bit.\n\n + * In this mode the there is only one associated read address for all the capture registers. + * Individual capture registers can still be accessed in this mode. + * + * \parRelated APIs:
+ * XMC_CCU8_GetCapturedValueFromFifo(). + */ +__STATIC_INLINE bool XMC_CCU8_SLICE_IsExtendedCapReadEnabled(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_IsPrescalerRunning:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((bool)((slice->TC & (uint32_t) CCU8_CC8_TC_ECM_Msk) == (uint32_t)CCU8_CC8_TC_ECM_Msk)); +} + +#if defined(CCU8V1) /* Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only */ +/** + * @param module Constant pointer to CCU8 module + * @param slice_number to check whether read value belongs to required slice or not + * @return
+ * int32_t Returns -1 if the FIFO value being retrieved is not from the \b slice_number. + * Returns the value captured in the \b slice_number, if captured value is from the correct slice. + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Read captured value from FIFO(ECRD register).\n\n + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * derived/inferred from the captured values. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_IsExtendedCapReadEnabled(). + */ +int32_t XMC_CCU8_GetCapturedValueFromFifo(const XMC_CCU8_MODULE_t *const module, const uint8_t slice_number); +#else +/** + * @param slice Constant pointer to CC8 Slice + * @param set The capture register set from which the captured value is to be retrieved + * @return
+ * uint32_t Returns the value captured in the \b slice_number + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Read captured value from FIFO(CC8yECRD0 and CC8yECRD1).\n\n + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * derived/inferred from the captured values. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_IsExtendedCapReadEnabled(). + * @note Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only. For other devices use XMC_CCU8_GetCapturedValueFromFifo() API + */ +uint32_t XMC_CCU8_SLICE_GetCapturedValueFromFifo(const XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_CAP_REG_SET_t set); +#endif + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Map an External event to the External Count Direction Function + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Count Direction of the slice, by configuring CC8yCMC.UDS bit.\n\n + * Count direction function is mapped with one of the 3 events. A slice can be configured to change the + * CC8yTIMER count direction depending on an external signal. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_DirectionConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Configures the status bit override Function of the slice, by configuring CC8yCMC.OFS bit.\n\n + * Status bit override function is mapped with one of the 3 events. A slice can be configured to change the + * output of the timer's CC8yST1 signal depending on an external signal. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent(). + */ +void XMC_CCU8_SLICE_StatusBitOverrideConfig(XMC_CCU8_SLICE_t *const slice); + +/** + * @param slice Constant pointer to CC8 Slice + * @param exit_mode How should a previously logged trap state be exited? + * @param synch_with_pwm Should exit of trap state be synchronized with PWM cycle start? + * @return
+ * None
+ * + * + * \parDescription:
+ * Configures the Trap Function of the slice, by configuring CC8yCMC.TS, CC8yTC.TRPSE, and CC8yTC.TRPSW bits.\n\n + * Trap function is mapped with Event-2. Criteria for exiting the trap state is configured. + * This trap function allows PWM outputs to react on the state of an input pin. + * Thus PWM output can be forced to inactive state upon detection of a trap. + * It is also possible to synchronize the trap function with the PWM signal using the \b synch_with_pwm. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureEvent()
XMC_CCU8_SLICE_SetInput(). + */ +void XMC_CCU8_SLICE_TrapConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_TRAP_EXIT_MODE_t exit_mode, + bool synch_with_pwm); + +/** + * @param slice Constant pointer to CC8 Slice + * @param ev1_config Pointer to event 1 configuration data + * @param ev2_config Pointer to event 2 configuration data + * @return
+ * None
+ * + * + * \parDescription:
+ * Map Status bit override function with an Event1 & Event 2 of the slice and configure CC8yINS register.\n\n + * Details such as the input mapped to the event, event detection criteria and Low Pass filter options are programmed + * by this routine for the events 1 & 2. Event-1 input would be the trigger to override the value. + * Event-2 input would be the override value. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StatusBitOverrideConfig(). + */ +void XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev2_config); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event The External Event which needs to be configured. + * @param config Pointer to event configuration data. + * @return
+ * None
+ * + * \parDescription:
+ * Configures an External Event of the slice, by updating CC8yINS register .\n\n + * Details such as the input mapped to the event, event detection criteria and low pass filter + * options are programmed by this routine. The Event \b config will configure the input selection, + * the edge selection, the level selection and the Low pass filter for the event. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartConfig()
XMC_CCU8_SLICE_StopConfig()
XMC_CCU8_SLICE_LoadConfig()
+ * XMC_CCU8_SLICE_ModulationConfig()
XMC_CCU8_SLICE_CountConfig()
XMC_CCU8_SLICE_GateConfig()
+ * XMC_CCU8_SLICE_Capture0Config()
XMC_CCU8_SLICE_Capture1Config()
XMC_CCU8_SLICE_DirectionConfig()
+ * XMC_CCU8_SLICE_StatusBitOverrideConfig()
XMC_CCU8_SLICE_TrapConfig(). + */ +void XMC_CCU8_SLICE_ConfigureEvent(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *config); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event The External Event which needs to be configured. + * @param input One of the 16 inputs meant to be mapped to the desired event + * @return
+ * None
+ * + * + * \parDescription:
+ * Selects an input for an external event, by configuring CC8yINS register.\n\n + * It is possible to select one of the possible 16 input signals for a given Event. + * This configures the CC8yINS.EVxIS for the selected event. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartConfig()
XMC_CCU8_SLICE_StopConfig()
XMC_CCU8_SLICE_LoadConfig()
+ * XMC_CCU8_SLICE_ModulationConfig()
XMC_CCU8_SLICE_CountConfig()
XMC_CCU8_SLICE_GateConfig()
+ * XMC_CCU8_SLICE_Capture0Config()
XMC_CCU8_SLICE_Capture1Config()
XMC_CCU8_SLICE_DirectionConfig()
+ * XMC_CCU8_SLICE_StatusBitOverrideConfig()
XMC_CCU8_SLICE_TrapConfig(). + */ +void XMC_CCU8_SLICE_SetInput(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_INPUT_t input); + +/** + * @param slice Constant pointer to CC8 Slice + * @param out_mask Output signals for which the Trap function needs to be activated. + * Use ::XMC_CCU8_SLICE_OUTPUT_t enum items to create a mask of choice, + * using a bit wise OR operation + * Range: [0x1 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Enables the trap feature, by setting CC8yTC.TRAPE0, CC8yTC.TRAPE1, CC8yTC.TRAPE2 and CC8yTC.TRAPE3 bit based on the + * \a out_mask.\n\n + * A particularly useful feature where the PWM output can be forced inactive upon detection of a trap. The trap signal + * can be the output of a sensing element which has just detected an abnormal electrical condition. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_TrapConfig()
XMC_CCU8_SLICE_DisableTrap()
XMC_CCU8_SLICE_ConfigureEvent()
+ * XMC_CCU8_SLICE_SetInput(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableTrap(XMC_CCU8_SLICE_t *const slice, const uint32_t out_mask) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableTrap:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TC |= (uint32_t)out_mask << CCU8_CC8_TC_TRAPE0_Pos; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param out_mask Output signals for which the Trap function needs to be deactivated. + * Use ::XMC_CCU8_SLICE_OUTPUT_t enum items to create a mask of choice, + * using a bit wise OR operation. + * Range: [0x1 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Disables the trap feature, by clearing CC8yTC.TRAPE0, CC8yTC.TRAPE1, CC8yTC.TRAPE2 and CC8yTC.TRAPE3 bit based on the + * \a out_mask.\n\n.\n\n + * This API will revert the changes done by XMC_CCU8_SLICE_EnableTrap(). + * This Ensures that the TRAP function has no effect on the output of the CCU8 slice. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableTrap(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableTrap(XMC_CCU8_SLICE_t *const slice, const uint32_t out_mask) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableTrap:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + + slice->TC &= ~((uint32_t)out_mask << CCU8_CC8_TC_TRAPE0_Pos); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * bool returns \b true if the Timer is running else it returns \b false. + * + * \parDescription:
+ * Returns the state of the timer (Either Running or stopped(idle)), by reading CC8yTCST.TRB bit. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartTimer()
XMC_CCU8_SLICE_StopTimer(). + */ +__STATIC_INLINE bool XMC_CCU8_SLICE_IsTimerRunning(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetTimerStatus:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return(bool)(((slice->TCST) & CCU8_CC8_TCST_TRB_Msk) == (uint32_t)CCU8_CC8_TCST_TRB_Msk); +} + +/** + * @param slice Pointer to an instance of CC8 slice + * @return
+ * bool returns \b true if the dead time counter of Compare channel-1 is running else it returns \b false. + * + * \parDescription:
+ * Returns the state of the Dead time counter 1 (Either Running or stopped(idle)), by reading CC8yTCST.DTR1 bit. + * This returns the state of the dead time counter which is linked to Compare channel-1. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). + */ +__STATIC_INLINE bool XMC_CCU8_SLICE_IsDeadTimeCntr1Running(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_IsDeadTimeCntr1Running:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return(bool)(((slice->TCST) & CCU8_CC8_TCST_DTR1_Msk) == (uint32_t)CCU8_CC8_TCST_DTR1_Msk); +} + +/** + * @param slice Pointer to an instance of CC8 slice + * @return
+ * bool returns \b true if the dead time counter of Compare channel-2 is running else it returns \b false. + * + * \parDescription:
+ * Returns the state of the Dead time counter 2 (Either Running or stopped(idle)), by reading CC8yTCST.DTR2 bit. + * This returns the state of the dead time counter which is linked to Compare channel-2. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_IsDeadTimeCntr1Running(). + */ +__STATIC_INLINE bool XMC_CCU8_SLICE_IsDeadTimeCntr2Running(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_IsDeadTimeCntr2Running:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return(bool)(((slice->TCST) & CCU8_CC8_TCST_DTR2_Msk) == (uint32_t)CCU8_CC8_TCST_DTR2_Msk); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * ::XMC_CCU8_SLICE_TIMER_COUNT_DIR_t returns the direction in which the timer is counting. + * + * \parDescription:
+ * Returns the timer counting direction, by reading CC8yTCST.CDIR bit.\n\n + * This API will return the direction in which the timer is currently + * incrementing(XMC_CCU8_SLICE_TIMER_COUNT_DIR_UP) or decrementing (XMC_CCU8_SLICE_TIMER_COUNT_DIR_DOWN). + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_CCU8_SLICE_TIMER_COUNT_DIR_t XMC_CCU8_SLICE_GetCountingDir(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetCountingDir:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((XMC_CCU8_SLICE_TIMER_COUNT_DIR_t)(((slice->TCST) & CCU8_CC8_TCST_CDIR_Msk) >> CCU8_CC8_TCST_CDIR_Pos)); +} +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Starts the timer counting operation, by setting CC8yTCSET.TRBS bit.\n\n + * It is necessary to have configured the CC8 slice before starting its timer. + * Before the Timer is started ensure that the clock is provided to the slice. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StopTimer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_StartTimer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_StartTimer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TCSET = CCU8_CC8_TCSET_TRBS_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Stops the Timer.\n\n + * Timer counting operation can be stopped by invoking this API, by setting CC8yTCCLR.TRBC bit. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_StopTimer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_StopTimer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TCCLR = (uint32_t) CCU8_CC8_TCCLR_TRBC_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Resets the timer count to zero, by setting CC8yTCCLR.TCC bit.\n\n + * A timer which has been stopped can still retain the last counted value. + * After invoking this API the timer value will be cleared. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_ClearTimer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ClearTimer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TCCLR = (uint32_t) CCU8_CC8_TCCLR_TCC_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Stops and resets the timer count to zero, by setting CC8yTCCLR.TCC and CC8yTCCLR.TRBC bit.\n\n + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_StartTimer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_StopClearTimer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_StopClearTimer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TCCLR = CCU8_CC8_TCCLR_TRBC_Msk | CCU8_CC8_TCCLR_TCC_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * ::XMC_CCU8_SLICE_MODE_t returns XMC_CCU8_SLICE_MODE_COMPARE if the slice is operating in compare mode + * returns XMC_CCU8_SLICE_MODE_CAPTURE if the slice is operating in capture mode + * + * \parDescription:
+ * Retrieves the current mode of operation in the slice (either Capture mode or Compare mode), by reading + * CC8yTC.CMOD bit.\n\n + * Ensure that before invoking this API the CCU8 slice should be configured otherwise the output of this API is + * invalid. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_CCU8_SLICE_MODE_t XMC_CCU8_SLICE_GetSliceMode(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetSliceMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((XMC_CCU8_SLICE_MODE_t)(((slice->TC) & CCU8_CC8_TC_CMOD_Msk) >> CCU8_CC8_TC_CMOD_Pos)); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param mode Desired repetition mode (Either single shot or Continuous) + * @return
+ * None
+ * + * \parDescription:
+ * Configures the Timer to either Single shot mode or continuous mode, by configuring CC8yTC.TSSM bit.\n\n + * The timer will count up to the terminal count as specified in the period register and stops immediately if the repeat + * mode has been set to single shot. In the continuous mode of operation, the timer starts counting all over again after + * reaching the terminal count. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetTimerRepeatMode(). + */ +void XMC_CCU8_SLICE_SetTimerRepeatMode(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t mode); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * ::XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t returns XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT if continuous mode is selected + * returns XMC_CCU8_SLICE_TIMER_REPEAT_MODE_SINGLE if single shot mode is selected + * + * \parDescription:
+ * Retrieves the Timer repeat mode, either Single shot mode or continuous mode, by reading CC8yTC.TSSM bit.\n\n + * The timer will count upto the terminal count as specified in the period register and stops immediately if the repeat + * mode has been set to single shot mode. In the continuous mode of operation, the timer starts counting + * all over again after reaching the terminal count. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetTimerRepeatMode(). + */ +__STATIC_INLINE XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t XMC_CCU8_SLICE_GetTimerRepeatMode( + const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t)(((slice->TC) & CCU8_CC8_TC_TSSM_Msk) >> CCU8_CC8_TC_TSSM_Pos)); +} +/** + * @param slice Constant pointer to CC8 Slice + * @param mode Desired counting mode (Either Edge Aligned or Center Aligned) + * @return
+ * None
+ * + * \parDescription:
+ * Configures the timer counting mode either Edge Aligned or Center Aligned, by configuring CC8yTC.TCM bit.\n\n + * In the edge aligned mode, the timer counts from 0 to the terminal count. Once the timer count has reached a preset + * compare value, the timer status output asserts itself. It will now deassert only after the timer count reaches the + * terminal count.\n In the center aligned mode, the timer first counts from 0 to the terminal count and then back to 0. + * During this upward and downward counting, the timer status output stays asserted as long as the timer value is + * greater than the compare value. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetTimerCountingMode(). + */ +void XMC_CCU8_SLICE_SetTimerCountingMode(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_TIMER_COUNT_MODE_t mode); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * ::XMC_CCU8_SLICE_TIMER_COUNT_MODE_t returns XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA if edge aligned mode is selected + * returns XMC_CCU8_SLICE_TIMER_COUNT_MODE_CA if center aligned mode is selected + * + * \parDescription:
+ * Retrieves timer counting mode either Edge aligned or Center Aligned, by reading CC8yTC.TCM bit.\n\n + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetTimerCountingMode(). + */ +__STATIC_INLINE XMC_CCU8_SLICE_TIMER_COUNT_MODE_t XMC_CCU8_SLICE_GetTimerCountingMode( + const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetTimerCountingMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((XMC_CCU8_SLICE_TIMER_COUNT_MODE_t)(((slice->TC) & CCU8_CC8_TC_TCM_Msk) >> CCU8_CC8_TC_TCM_Pos)); +} +/** + * @param slice Constant pointer to CC8 Slice + * @param period_val Timer period value + * Range: [0x0 to 0xFFFF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer period, by writing CC8yPRS register.\n\n + * The frequency of counting/ PWM frequency is determined by this value. The period value is written to a shadow + * register. Explicitly enable the shadow transfer for the the period value by calling + * XMC_CCU8_EnableShadowTransfer() with appropriate mask. If shadow transfer is enabled and the timer is running, + * a period match transfers the value from the shadow register to the actual period register. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetTimerPeriodMatch(). + */ +void XMC_CCU8_SLICE_SetTimerPeriodMatch(XMC_CCU8_SLICE_t *const slice, const uint16_t period_val); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * uint16_t returns the current timer period value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the timer period value currently effective, by reading CC8yPR register.\n\n + * If the timer is active then the value being returned is currently being used for the PWM period. + * + * \parNote:
+ * The XMC_CCU8_SLICE_SetTimerPeriodMatch() would set the new period value to a shadow register. + * This would only transfer the new values into the actual period register if the shadow transfer request + * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU8_SLICE_GetTimerPeriodMatch() + * would not reflect the new values until the shadow transfer completes. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetTimerPeriodMatch(). + */ +__STATIC_INLINE uint16_t XMC_CCU8_SLICE_GetTimerPeriodMatch(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((uint16_t) slice->PR); +} +/** + * @param slice Constant pointer to CC8 Slice + * @param channel Select the compare channel to which the \b compare_val has to programmed. + * @param compare_val Timer compare value + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer compare value, by writing CC8yCR1S and CC8yCR2S registers.\n\n + * The PWM duty cycle is determined by this value.\n\n + * The compare value is written to a shadow register. Explicitly enable the shadow transfer for + * the the period/compare value by calling XMC_CCU8_EnableShadowTransfer() with + * appropriate mask.If shadow transfer is enabled and the timer is running, + * a period match transfers the value from the shadow register to the actual compare register. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer(). + */ +void XMC_CCU8_SLICE_SetTimerCompareMatch(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, + const uint16_t compare_val); + +/** + * @param slice Constant pointer to CC8 Slice + * @param compare_val Timer compare value + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer compare1 value, by writing CC8yCR1S register.\n\n + * The PWM duty cycle is determined by this value.\n\n + * The compare value is written to a shadow register. Explicitly enable the shadow transfer for + * the the period/compare value by calling XMC_CCU8_EnableShadowTransfer() with appropriate mask. + * If shadow transfer is enabled and the timer is running, a period match transfers the value from + * the shadow register to the actual compare register. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetTimerCompareMatchChannel1(XMC_CCU8_SLICE_t *const slice, const uint16_t compare_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCompareMatchChannel1:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->CR1S = (uint32_t) compare_val; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param compare_val Timer compare value + * @return
+ * None
+ * + * \parDescription:
+ * Programs the timer compare2 value, by writing CC8yCR2S register.\n\n + * The PWM duty cycle is determined by this value.\n\n + * The compare value is written to a shadow register. Explicitly enable the shadow transfer for + * the the period/compare value by calling XMC_CCU8_EnableShadowTransfer() with appropriate mask. + * If shadow transfer is enabled and the timer is running, a period match transfers the value from + * the shadow register to the actual compare register. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetTimerCompareMatchChannel2(XMC_CCU8_SLICE_t *const slice, const uint16_t compare_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCompareMatchChannel2:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->CR2S = (uint32_t) compare_val; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param channel Select the compare channel to retrieve from. + * @return
+ * uint16_t returns the current timer compare value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the timer compare value currently effective, by reading CC8yCR1S and CC8yCR2S registers.\n\n + * If the timer is active then the value being returned is currently being for the PWM duty cycle( timer compare value). + * + * \parNote:
+ * The XMC_CCU8_SLICE_SetTimerCompareMatch() would set the new compare value to a shadow register. + * This would only transfer the new values into the actual compare register if the shadow transfer request + * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU8_SLICE_GetTimerCompareMatch() + * would not reflect the new values until the shadow transfer completes. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetTimerCompareMatch(). + */ +uint16_t XMC_CCU8_SLICE_GetTimerCompareMatch(const XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel); + +/** + * @param module Constant pointer to CCU8 module + * @param shadow_transfer_msk Shadow transfer request mask for various transfers. + * Use ::XMC_CCU8_SHADOW_TRANSFER_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Requests of shadow transfer for Period, Compare, Passive level, dither and prescaler, by configuring + * the GCSS register.\n\n + * The transfer from the shadow registers to the actual registers is done in the immediate next occurrence of the + * shadow transfer trigger after the API is called. + * + * Any call to XMC_CCU8_SLICE_SetTimerPeriodMatch()
XMC_CCU8_SLICE_SetTimerCompareMatch()
+ * XMC_XMC_CCU8_SLICE_SetPrescaler()
XMC_CCU8_SLICE_CompareInit()
XMC_CCU8_SLICE_CaptureInit(). + * must be succeeded by this API. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_CCU8_EnableShadowTransfer(XMC_CCU8_MODULE_t *const module, const uint32_t shadow_transfer_msk) +{ + XMC_ASSERT("XMC_CCU8_EnableShadowTransfer:Invalid module Pointer", XMC_CCU8_IsValidModule(module)); + module->GCSS = (uint32_t)shadow_transfer_msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * uint16_t returns the current timer value + * Range: [0x0 to 0xFFFF] + * + * \parDescription:
+ * Retrieves the latest timer value, from CC8yTIMER register.\n\n + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetTimerValue(). + */ +__STATIC_INLINE uint16_t XMC_CCU8_SLICE_GetTimerValue(const XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetTimerValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return((uint16_t) slice->TIMER); +} +/** + * @param slice Constant pointer to CC8 Slice + * @param timer_val The new timer value that has to be loaded into the TIMER register. + * Range: [0x0 to 0xFFFF] + * @return
+ * None
+ * + * \parDescription:
+ * Loads a new timer value, by setting CC8yTIMER register.\n\n + * + * \parNote:
+ * Request to load is ignored if the timer is running. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetTimerValue(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetTimerValue(XMC_CCU8_SLICE_t *const slice, const uint16_t timer_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TIMER = (uint32_t) timer_val; +} +/** + * @param slice Constant pointer to CC8 Slice + * @param period_dither Boolean instruction on dithering of period match + * @param duty_dither Boolean instruction on dithering of compare match + * @param spread Dither compare value + * @return
+ * None
+ * + * \parDescription:
+ * Enables dithering of PWM frequency and duty cycle, by configuring CC8yTC.DITHE and CC8yDITS bits.\n\n + * Some control loops are slow in updating PWM frequency and duty cycle. In such a case, a Bresenham style dithering + * can help reduce long term errors. Dithering can be applied to period and duty individually, + * this can be selected using the parameter \b period_dither and \b duty_dither. + * The \b spread would provide the dither compare value. If the dither counter value is less than this \b spread then + * the period/compare values would be dithered according to the dither mode selected. This API would invoke + * XMC_CCU8_SLICE_SetDitherCompareValue(). + * + * \parNote:
+ * After this API call, XMC_CCU8_EnableShadowTransfer() has to be called with appropriate mask + * to transfer the dither value. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DisableDithering(). + */ +void XMC_CCU8_SLICE_EnableDithering(XMC_CCU8_SLICE_t *const slice, + const bool period_dither, + const bool duty_dither, + const uint8_t spread); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables dithering of PWM frequency and duty cycle, by clearing CC8yTC.DITHE bits.\n\n + * This disables the Dither mode that was set in XMC_CCU8_SLICE_EnableDithering(). + * This API will not clear the dither compare value. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableDithering(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableDithering(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableDithering:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU8_CC8_TC_DITHE_Msk); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Enables the floating prescaler, by setting CC8yTC.FPE bit.\n\n + * The prescaler divider starts with an initial value and increments upon every period match. It keeps incrementing + * until a ceiling (prescaler compare value) is hit and thereafter rolls back to the original prescaler divider value.\n + * It is necessary to have programmed an initial divider value and a compare value before the feature is enabled. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue()
XMC_CCU8_SLICE_DisableFloatingPrescaler()
+ * XMC_XMC_CCU8_SLICE_SetPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableFloatingPrescaler(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TC |= (uint32_t) CCU8_CC8_TC_FPE_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Disables the floating prescaler, by clearing CC8yTC.FPE bit.\n\n + * This would return the prescaler to the normal mode. + * The prescaler that would be applied is the value present in CC8yPSC. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableFloatingPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableFloatingPrescaler(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->TC &= ~((uint32_t) CCU8_CC8_TC_FPE_Msk); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param comp_val Dither compare value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Sets the dither spread/compare value, by setting CC8yDITS.DCVS bits.\n\n + * This value is the cornerstone of PWM dithering feature. Dithering is applied/done when the value in the + * dithering counter is less than this compare/spread value. For all dithering counter values greater than + * the spread value, there is no dithering. After setting the value XMC_CCU8_EnableShadowTransfer() has to be + * called with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableDithering(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetDitherCompareValue(XMC_CCU8_SLICE_t *const slice, const uint8_t comp_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetDitherCompareValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetDitherCompareValue:Invalid Dither compare value", (comp_val <= 15U)); + + slice->DITS = comp_val; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param div_val Prescaler divider value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the slice specific prescaler divider, by configuring the CC8yPSC and CC8yFPC registers.\n\n + * The prescaler divider may only be programmed after the prescaler run bit has been cleared + * by calling XMC_CCU8_StopPrescaler(). + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue(). + */ +void XMC_CCU8_SLICE_SetPrescaler(XMC_CCU8_SLICE_t *const slice, const uint8_t div_val); + +/** + * @param slice Constant pointer to CC8 Slice + * @param cmp_val Prescaler divider compare value + * Range: [0x0 to 0xF] + * @return
+ * None
+ * + * \parDescription:
+ * Programs the slice specific prescaler divider compare value, by configuring CC8yFPCS register.\n\n + * The compare value is applicable only in floating mode of operation. The prescaler divider starts with an initial + * value and increments to the compare value steadily upon every period match. Once prescaler divider + * equals the prescaler divider compare value, the value in the former resets back to the PVAL (from FPC). After setting + * the value, XMC_CCU8_EnableShadowTransfer() has to be called with appropriate mask. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetPrescaler(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue(XMC_CCU8_SLICE_t *const slice, + const uint8_t cmp_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + /* First, write to the shadow register */ + slice->FPCS = (uint32_t) cmp_val; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param ch_num Compare channel for which the multi-channel mode is needed. + * @return
+ * None
+ * + * \parDescription:
+ * Enables the multichannel mode, by setting CC8yTC.MCME1 or CC8yTC.MCME1 bits based on the \a ch_num.\n\n + * The output state of the Timer slices can be controlled in parallel by a single input signal. + * A particularly useful feature in motor control applications where the PWM output of multiple slices of a module can + * be gated and ungated by multi-channel gating inputs connected to the slices. A peripheral like POSIF connected to the + * motor knows exactly which of the power drive switches are to be turned on and off at any instant. It can thus through + * a gating bus (known as multi-channel inputs) control which of the slices output stays gated/ungated. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DisableMultiChannelMode()
XMC_CCU8_SetMultiChannelShadowTransferMode(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableMultiChannelMode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableMultiChannelMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_EnableMultiChannelMode:Invalid Channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(ch_num)); + + slice->TC |= (uint32_t)CCU8_CC8_TC_MCME1_Msk << ch_num; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param ch_num Compare channel for which the multi-channel mode needs to be disabled. + * @return
+ * None
+ * + * \parDescription:
+ * Disables the multichannel mode, by clearing CC8yTC.MCME1 or CC8yTC.MCME1 bits based on the \a ch_num.\n\n + * Returns the slices to the normal operation mode. This takes the slice number as input and + * configures the multi channel mode for it. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableMultiChannelMode(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableMultiChannelMode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableMultiChannelMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_DisableMultiChannelMode:Invalid Channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(ch_num)); + + slice->TC &= ~((uint32_t)CCU8_CC8_TC_MCME1_Msk << ch_num); +} + +/** + * @param module Constant pointer to CCU8 module + * @param slice_mode_msk Slices for which the configuration has to be applied. + * Use ::XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Enables the Multi-channel shadow transfer request trigger signal either by software or hardware by configuring + * GCTRL.MSE0, GCTRL.MSE1, GCTRL.MSE2, and GCTRL.MSE3 based on the mask.\n\n + * The shadow transfer would take place either if it was requested by software or by the CCU8x.MCSS input. + * + * \parRelated APIs:
+ * None. +*/ +void XMC_CCU8_SetMultiChannelShadowTransferMode(XMC_CCU8_MODULE_t *const module, const uint32_t slice_mode_msk); + +/** + * @param slice Constant pointer to CC8 Slice + * @param reg_num The capture register from which the captured value is to be retrieved + * Range: [0,3] + * @return
+ * uint32_t Returns the Capture register value. + * Range: [0 to 0x1FFFFF] + * + * \parDescription:
+ * Retrieves timer value which has been captured in the Capture registers, by reading CC8yCV[\b reg_num] register.\n\n + * The signal whose timing characteristics are to be measured must be mapped to an event which in turn must be mapped + * to the capture function. Based on the capture criteria, the timer values are captured into capture registers. Timing + * characteristics of the input signal may then be derived/inferred from the captured values. The full flag will help + * to find out if there is a new captured value present. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetLastCapturedTimerValue(). + */ +uint32_t XMC_CCU8_SLICE_GetCaptureRegisterValue(const XMC_CCU8_SLICE_t *const slice, const uint8_t reg_num); + +/** + * @param slice Constant pointer to CC8 Slice + * @param set The capture register set, which must be evaluated + * @param val_ptr Out Parameter of the API.Stores the captured timer value into this out parameter. + * @return
+ * ::XMC_CCU8_STATUS_t Returns XMC_CCU8_STATUS_OK if there was new value present in the capture registers. + * returns XMC_CCU8_STATUS_ERROR if there was no new value present in the capture registers. + * + * \parDescription:
+ * Retrieves the latest captured timer value, by reading CC8yCV registers.\n\n + * Retrieve the timer value last stored by the slice. When separate capture events are used, + * users must specify the capture set to evaluate. If single capture event mode is used, all 8 capture registers are + * evaluated.\n + * The lowest register is evaluated first followed by the next higher ordered register and this continues until all + * capture registers have been evaluated. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_GetCaptureregisterValue(). + */ +XMC_CCU8_STATUS_t XMC_CCU8_SLICE_GetLastCapturedTimerValue(const XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr); + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Enables the generation of an interrupt pulse for the event, by configuring CC8yINTE register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API merely enables the event. Binding with SR is performed by another API. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetInterruptNode()
XMC_CCU8_SLICE_EnableMultipleEvents()
XMC_CCU8_SLICE_DisableEvent()
+ * XMC_CCU8_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableEvent(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_EnableEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + + slice->INTE |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param mask Event mask such that multiple events can be enabled. + * Use ::XMC_CCU8_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Enables the generation of an interrupt pulse for the required events, by configuring CC8yINTE register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API merely enables the events. Binding with SR is performed by another API. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetInterruptNode()
XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_DisableEvent()
+ * XMC_CCU8_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableMultipleEvents(XMC_CCU8_SLICE_t *const slice, const uint16_t mask) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableMultipleEvents:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->INTE = (uint32_t) mask; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Disables the generation of an interrupt pulse for the event, by clearing CC8yINTE register.\n\n + * Prevents the event from being asserted. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetInterruptNode()
XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_EnableMultipleEvents()
+ * XMC_CCU8_SLICE_DisableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableEvent(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_DisableEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + + slice->INTE &= ~(((uint32_t) 1) << ((uint32_t) event)); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param mask Event mask such that multiple events can be enabled. + * Use ::XMC_CCU8_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice, + * using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Disables the generation of an interrupt pulse for the required events, by clearing CC8yINTE register.\n\n + * Prevents selected events of the slice from being asserted. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetInterruptNode()
XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_EnableMultipleEvents()
+ * XMC_CCU8_SLICE_DisableEvent(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableMultipleEvents(XMC_CCU8_SLICE_t *const slice, const uint16_t mask) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableMultipleEvents:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->INTE &= ~((uint32_t) mask); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Event whose assertion can potentially lead to an interrupt + * @return
+ * None
+ * + * \parDescription:
+ * Manually asserts the requested event, by setting CC8ySWS register.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API manually asserts the requested event. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_SetInterruptNode()
XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_EnableMultipleEvents(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetEvent(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + + slice->SWS |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Asserted event which must be acknowledged. + * @return
+ * None
+ * + * \parDescription:
+ * Acknowledges an asserted event, by setting CC8ySWR with respective event flag.\n\n + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_SetEvent()
XMC_CCU8_SLICE_GetEvent(). + * + */ +__STATIC_INLINE void XMC_CCU8_SLICE_ClearEvent(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ClearEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ClearEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + slice->SWR |= ((uint32_t) 1) << ((uint32_t) event); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Event to be evaluated for assertion + * @return
+ * bool Returns true if event is set else false is returned. + * + * \parDescription:
+ * Evaluates if a given event is asserted or not, by reading CC8yINTS register.\n\n + * Return true if the event is asserted. For a event to be asserted it has to be + * first enabled. Only if that event is enabled the call to this API is valid. + * If the Event is enabled and has not yet occurred then a false is returned. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_SetEvent(). + */ +__STATIC_INLINE bool XMC_CCU8_SLICE_GetEvent(const XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GetEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + return(((uint32_t)(slice->INTS & ((uint32_t)1 << event))) != 0U); + } + +/** + * @param slice Constant pointer to CC8 Slice + * @param event Event which must be bound to a service request line + * @param sr The Service request line which is bound to the \b event + * @return
+ * None
+ * + * \parDescription:
+ * Binds requested event to a service request line, by configuring CC8ySRS register with respective event.\n\n + * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding + * NVIC node must be enabled as well. This API binds the requested event with the requested service request line(\b sr). + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_SetEvent(). + * + */ +void XMC_CCU8_SLICE_SetInterruptNode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_IRQ_ID_t event, + const XMC_CCU8_SLICE_SR_ID_t sr); + +/** + * @param slice Constant pointer to CC8 Slice + * @param out Output signal for which the passive level needs to be set. + * @param level Output passive level for the \b out signal + * @return
+ * None
+ * + * \parDescription:
+ * Configures the passive level for the slice output, by setting CC8yPSL register.\n\n + * Defines the passive level for the timer slice output pin. Selects either level high is passive + * or level low is passive. This is the level of the output before the compare match is value changes it. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableEvent()
XMC_CCU8_SLICE_SetEvent(). + */ +void XMC_CCU8_SLICE_SetPassiveLevel(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_OUTPUT_t out, + const XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t level); + +/** + * @param slice Constant pointer to CC8 Slice + * @param config Pointer to dead time configuration data + * @return
+ * None
+ * + * \parDescription:
+ * Initializes Dead time configuration for the slice outputs, by configuring CC8yDC1R, CC8yDC2R, CC8yDTC registers.\n\n + * This routine programs dead time delays (rising & falling) and dead time clock prescaler. + * Details such as the choice of dead time for channel1, channel2, ST1, Inverted ST1, ST2, Inverted ST2, are also + * programmed by this routine. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_ConfigureDeadTime()
XMC_CCU8_SLICE_SetDeadTimeValue()
XMC_CCU8_SLICE_SetDeadTimePrescaler()
+ * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). + */ +void XMC_CCU8_SLICE_DeadTimeInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_DEAD_TIME_CONFIG_t *const config); + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Configures the slice to generate PWM in asymmetric compare mode, by setting CC8yCHC.ASE bit.\n\n + * In asymmetric compare mode, the compare channels 1 & 2 are grouped to generate the PWM.This would + * generate an inverted PWM at OUT0 & OUT1. + * In Edge Aligned mode (counting up), the Status bit is set when a compare match of + * Compare channel-1 occurs and cleared when a compare match event of Compare channel-2 occurs.\n + * In Center Aligned mode, the status bit is set when a compare match event of Compare channel-1 occurs while + * counting up and cleared when a compare match event of Compare channel-2 occurs while counting down. + * + * \parNote:
+ * External count direction function is enabled then the asymmetric mode of operation is not possible. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableSymmetricCompareMode()
+ */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableAsymmetricCompareMode(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableAsymmetricCompareMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->CHC |= (uint32_t) CCU8_CC8_CHC_ASE_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return
+ * None
+ * + * \parDescription:
+ * Configures the slice to generate PWM in symmetric(standard) compare mode, by clearing CC8yCHC.ASE bit.\n\n + * In symmetric compare mode, the compare channels 1 & 2 are independent of each other & each channel generates the + * PWM & inverted PWM at OUT0, OUT1, OUT2 & OUT3. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableAsymmetricCompareMode(). + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableSymmetricCompareMode(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableSymmetricCompareMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->CHC &= ~((uint32_t) CCU8_CC8_CHC_ASE_Msk); +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param mask The Dead Time configuration mask. + * Do a bitwise OR operation on the following values depending on the need. + * Value 0x1: Dead Time Enable for Compare Channel 1 + * Value 0x2: Dead Time Enable for Compare Channel 2 + * Value 0x4: Dead Time Enable for CC8yST1 path is enabled. + * Value 0x8: Dead Time Enable for Inverted CC8yST1 path is enabled. + * Value 0x10: Dead Time Enable for CC8yST2 path is enabled. + * Value 0x20: Dead Time Enable for Inverted CC8yST2 path is enabled. + * Range: [0x0 to 0x3F] + * + * \parDescription:
+ * Activates or deactivates dead time for compare channel and ST path, by configuring CC8y.DC1R, CC8y.DC1R and + * CC8y.DTC registers.\n\n + * Use the provided masks to enable/disable the dead time for the compare channels and the ST signals. It is possible + * to deactivate the dead time for all the options by passing a 0x0 as the mask. + * Details such as the choice of dead time for channel1, channel2, ST1, Inverted ST1, ST2, Inverted ST2, are + * programmed by this routine. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DeadTimeInit()
XMC_CCU8_SLICE_SetDeadTimeValue()
XMC_CCU8_SLICE_SetDeadTimePrescaler()
+ * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). + */ +void XMC_CCU8_SLICE_ConfigureDeadTime(XMC_CCU8_SLICE_t *const slice, const uint8_t mask); + +/** + * @param slice Constant pointer to CC8 Slice + * @param channel Compare channel number + * @param rise_value Programs rising edge delay + * Range: [0x0 to 0xFF] + * @param fall_value Programs falling edge delay + * Range: [0x0 to 0xFF] + * @return
+ * None
+ * + * \parDescription:
+ * Configures the dead time for rising and falling edges, by updating CC8y.DC1R, CC8y.DC1R registers.\n\n + * This API will Configure the delay that is need either when the value changes from 0 to 1 (rising edge) or + * value changes from 1 to 0(falling edge). Directly accessed registers are CC8yDC1R, CC8yDC2R. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DeadTimeInit()
XMC_CCU8_SLICE_SetDeadTimeValue()
XMC_CCU8_SLICE_ConfigureDeadTime()
+ * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). + */ +void XMC_CCU8_SLICE_SetDeadTimeValue(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, + const uint8_t rise_value, + const uint8_t fall_value); + +/** + * @param slice Pointer to an instance of CC8 slice + * @param div_val Prescaler divider value + * @return
+ * None
+ * + * \parDescription:
+ * Configures clock division factor for dead time generator, by configuring CC8yDTC.DTCC bit. + * The Clock divider works on the timer clock. It is possible to scale the timer clock for the dead time + * generator by a factor of 1/2/4/8. This selection is passed as an argument to the API. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DeadTimeInit()
XMC_CCU8_SLICE_SetDeadTimeValue()
XMC_CCU8_SLICE_ConfigureDeadTime()
+ * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). + */ +void XMC_CCU8_SLICE_SetDeadTimePrescaler(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_DTC_DIV_t div_val); + +/** + * @param slice Constant pointer to CC8 Slice + * @param channel which channel status has to be give as out + * @return
+ * None
+ * + * \parDescription:
+ * Configures status ST1, ST2 mapping to STy, by configuring CC8yTC.STOS bits.\n\n + * This routine defines the output STy as a function of ST1 or ST2 or both ST1 & ST2. + * It is possible to make the CCU8x.STy signal to reflect the CC8y.ST1/CC8y.ST2 or a function of the 2 signals. + * + * \parRelated APIs:
+ * None. + */ +void XMC_CCU8_SLICE_ConfigureStatusBitOutput(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_STATUS_t channel); + +#if (UC_SERIES != XMC45) || defined(DOXYGEN) +/** + * @param slice Constant pointer to CC8 Slice + * + * @return
+ * None
+ * + * \parDescription:
+ * Cascades the shadow transfer operation throughout the CCU8 timer slices, by setting CSE bit in STC register.\n\n + * + * The shadow transfer enable bits needs to be set in all timer slices, that are being used in the cascaded architecture, + * at the same time. The shadow transfer enable bits, also need to be set for all slices even if the shadow values of + * some slices were not updated. It is possible to to cascade with the adjacent slices only. CC80 slice is a + * master to start the operation. + * + * \parNote:
+ * XMC_CCU8_EnableShadowTransfer() must be called to enable the shadow transfer of the all the slices, which needs to be + * cascaded. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer(), XMC_CCU8_SLICE_DisableCascadedShadowTransfer()
. + * @note Not available for XMC4500 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableCascadedShadowTransfer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC |= (uint32_t) CCU8_CC8_STC_CSE_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * + * @return
+ * None
+ * + * \parDescription:
+ * Disables the cascaded the shadow transfer operation, by clearing CSE bit in STC register.\n\n + * + * If in any slice the cascaded mode disabled, other slices from there onwards does not update the values in cascaded mode. + * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableCascadedShadowTransfer()
. + * @note Not available for XMC4500 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableCascadedShadowTransfer(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC &= ~(uint32_t) CCU8_CC8_STC_CSE_Msk; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @param shadow_transfer_mode mode to be configured + * Use :: XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t enum items for mode + * @return
+ * None
+ * + * \parDescription:
+ * Configures when the shadow transfer has to occur, by setting STM bit in STC register.\n\n + * + * After requesting for shadow transfer mode using XMC_CCU8_EnableShadowTransfer(), actual transfer occurs based on the + * selection done using this API (i.e. on period and One match, on Period match only, on One match only). + * + * \parNote:
+ * This is effective when the timer is configured in centre aligned mode. + * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer()
+ * @note Not available for XMC4500 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_SetShadowTransferMode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t shadow_transfer_mode) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetShadowTransferMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC = ((slice->STC) & ~(uint32_t)((uint32_t)CCU8_CC8_STC_STM_Msk << (uint32_t)CCU8_CC8_STC_STM_Pos)) | + ((shadow_transfer_mode << CCU8_CC8_STC_STM_Pos) & (uint32_t)CCU8_CC8_STC_STM_Msk); +} +#endif + +#if defined(CCU8V3) || defined(DOXYGEN)/* Defined for XMC1400 devices only */ + /** + * @param slice Constant pointer to CC8 Slice + * @param immediate_write specifies for what fields this mode has to be applied + * Use :: XMC_CCU8_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the specified fields shadow value to be updated immediately after shadow transfer request, by setting + * IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n + * + * When immediate shadow is enabled, by calling XMC_CCU8_EnableShadowTransfer() the value which are written in the + * shadow registers get updated to the actual registers immediately. \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer()
+ * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_WriteImmediateAfterShadowTransfer(XMC_CCU8_SLICE_t *const slice, + const uint32_t immediate_write) +{ + XMC_ASSERT("XMC_CCU8_SLICE_WriteImmediateAfterShadowTransfer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC |= immediate_write; +} + + /** + * @param slice Constant pointer to CC8 Slice + * @param coherent_write specifies for what fields this mode has to be applied + * Use :: XMC_CCU8_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configures the specified fields shadow value to be updated in synchronous with PWM after shadow transfer request, by + * clearing IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n + * + * When coherent shadow is enabled, after calling XMC_CCU8_EnableShadowTransfer(), the value which are written in the + * respective shadow registers get updated according the configuration done using XMC_CCU8_SLICE_SetShadowTransferMode() + * API. \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU8_EnableShadowTransfer(), XMC_CCU8_SLICE_SetShadowTransferMode()
+ * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_WriteCoherentlyWithPWMCycle(XMC_CCU8_SLICE_t *const slice, + const uint32_t coherent_write) +{ + XMC_ASSERT("XMC_CCU8_SLICE_WriteCoherentlyWithPWMCycle:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC &= ~(uint32_t)coherent_write; +} + + /** + * @param slice Constant pointer to CC8 Slice + * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request is generated + * Use :: XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a + * bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configure on which shadow register update, automatic shadow transfer request generation has to be enabled. By setting + * ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n + * + * By updating the configured shadow register, the shadow transfer request is generated to update all the shadow registers. + * \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest(). + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest(XMC_CCU8_SLICE_t *const slice, + const uint32_t automatic_shadow_transfer) +{ + XMC_ASSERT("XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC |= automatic_shadow_transfer; +} + + /** + * @param slice Constant pointer to CC8 Slice + * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request should not be + * generated + * Use :: XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a + * bit wise OR operation. + * @return
+ * None
+ * + * \parDescription:
+ * Configure on which shadow register update, automatic shadow transfer request generation has to be disabled. By + * clearing ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n + * + * This disables the generation of automatic shadow transfer request for the specified register update. + * \parNote:
+ * + * \parRelated APIs:
+ * XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest(). + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest(XMC_CCU8_SLICE_t *const slice, + const uint32_t automatic_shadow_transfer) +{ + XMC_ASSERT("XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->STC &= ~(uint32_t)automatic_shadow_transfer; +} +#endif +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CCU80) */ + +#endif /* XMC_CCU8_H */ + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_common.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_common.h new file mode 100644 index 00000000..77ff7e07 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_common.h @@ -0,0 +1,285 @@ +/** + * @file xmc_common.h + * @date 2017-04-04 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * - Brief section updated + * - Added XMC_LIB_VERSION macro + * + * 2016-02-26: + * - Updated XMC_LIB_VERSION macro to v2.1.6 + * + * 2016-05-30: + * - Updated XMC_LIB_VERSION macro to v2.1.8 + * + * 2016-11-18: + * - Updated XMC_LIB_VERSION macro to v2.1.10 + * - Changed type of size in XMC_PRIOARRAY_t to fix compilation warnings + * + * 2017-04-04: + * - Updated XMC_LIB_VERSION macro to v2.1.12 + * + * @endcond + * + */ + +#ifndef XMC_COMMON_H +#define XMC_COMMON_H + +#include +#include +#include +#include + +#include "xmc_device.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup COMMON + * @brief Common APIs to all peripherals for XMC microcontroller family + * @{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ +#define XMC_LIB_MAJOR_VERSION (2U) +#define XMC_LIB_MINOR_VERSION (1U) +#define XMC_LIB_PATCH_VERSION (12U) + +#define XMC_LIB_VERSION ((XMC_LIB_MAJOR_VERSION << 16U) + (XMC_LIB_MINOR_VERSION << 8U) + XMC_LIB_PATCH_VERSION) + +/* Define WEAK attribute */ +#if !defined(__WEAK) +#if defined ( __CC_ARM ) +#define __WEAK __attribute__ ((weak)) +#elif defined ( __ICCARM__ ) +#define __WEAK __weak +#elif defined ( __GNUC__ ) +#define __WEAK __attribute__ ((weak)) +#elif defined ( __TASKING__ ) +#define __WEAK __attribute__ ((weak)) +#endif +#endif + +#ifdef XMC_ASSERT_ENABLE + #define XMC_ASSERT(msg, exp) { if(!(exp)) {XMC_AssertHandler(msg, __FILE__, __LINE__);} } +#else + #define XMC_ASSERT(msg, exp) { ; } +#endif + +#ifdef XMC_DEBUG_ENABLE + #include + #define XMC_DEBUG(...) { printf(__VA_ARGS__); } +#else + #define XMC_DEBUG(...) { ; } +#endif + +#define XMC_UNUSED_ARG(x) (void)x + +#define XMC_STRUCT_INIT(m) memset(&m, 0, sizeof(m)) + +#define XMC_PRIOARRAY_DEF(name, size) \ +XMC_PRIOARRAY_ITEM_t prioarray_m_##name[size + 2]; \ +XMC_PRIOARRAY_t prioarray_def_##name = {(size), (prioarray_m_##name)}; + +#define XMC_PRIOARRAY(name) \ +&prioarray_def_##name + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ +/* + * + */ +typedef struct XMC_DRIVER_VERSION +{ + uint8_t major; + uint8_t minor; + uint8_t patch; +} XMC_DRIVER_VERSION_t; + +/* + * + */ +typedef void *XMC_LIST_t; + +/* + * + */ +typedef struct XMC_PRIOARRAY_ITEM +{ + int32_t priority; + int32_t previous; + int32_t next; +} XMC_PRIOARRAY_ITEM_t; + +/* + * + */ +typedef struct XMC_PRIOARRAY +{ + int32_t size; + XMC_PRIOARRAY_ITEM_t *items; +} XMC_PRIOARRAY_t; + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * + */ +void XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line); + +/* + * + */ +void XMC_LIST_Init(XMC_LIST_t *list); + +/* + * + */ +void XMC_LIST_Add(XMC_LIST_t *list, void *const item); + +/* + * + */ +void XMC_LIST_Remove(XMC_LIST_t *list, void *const item); + +/* + * + */ +uint32_t XMC_LIST_GetLength(XMC_LIST_t *list); + +/* + * + */ +void *XMC_LIST_GetHead(XMC_LIST_t *list); + +/* + * + */ +void *XMC_LIST_GetTail(XMC_LIST_t *list); + +/* + * + */ +void XMC_LIST_Insert(XMC_LIST_t *list, void *prev_item, void *new_item); + +/* + * + */ +void XMC_PRIOARRAY_Init(XMC_PRIOARRAY_t *prioarray); + +/* + * + */ +void XMC_PRIOARRAY_Add(XMC_PRIOARRAY_t *prioarray, int32_t item, int32_t priority); + +/* + * + */ +void XMC_PRIOARRAY_Remove(XMC_PRIOARRAY_t *prioarray, int32_t item); + +/* + * + */ +__STATIC_INLINE int32_t XMC_PRIOARRAY_GetHead(XMC_PRIOARRAY_t *prioarray) +{ + XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL); + return prioarray->items[prioarray->size].next; +} + +/* + * + */ +__STATIC_INLINE int32_t XMC_PRIOARRAY_GetTail(XMC_PRIOARRAY_t *prioarray) +{ + XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL); + return prioarray->items[prioarray->size + 1].previous; +} + +/* + * + */ +__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPriority(XMC_PRIOARRAY_t *prioarray, int32_t item) +{ + XMC_ASSERT("XMC_PRIOARRAY_GetItemPriority: item out of range", (item >= 0) && (item < prioarray->size)); + return prioarray->items[item].priority; +} + +/* + * + */ +__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemNext(XMC_PRIOARRAY_t *prioarray, int32_t item) +{ + XMC_ASSERT("XMC_PRIOARRAY_GetItemNext: item out of range", (item >= 0) && (item < prioarray->size)); + return prioarray->items[item].next; +} + +/* + * + */ +__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPrevious(XMC_PRIOARRAY_t *prioarray, int32_t item) +{ + XMC_ASSERT("XMC_PRIOARRAY_GetItemPrevious: item out of range", (item >= 0) && (item < prioarray->size)); + return prioarray->items[item].previous; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XMC_COMMON_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dac.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dac.h new file mode 100644 index 00000000..2c9d8b4e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dac.h @@ -0,0 +1,1357 @@ +/** + * @file xmc_dac.h + * @date 2015-08-31 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Initial version + * + * 2015-02-20: + * - Driver description added + * + * 2015-06-19: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-08-31: + * - Help document updated + * @endcond + * + */ + +#ifndef XMC_DAC_H +#define XMC_DAC_H + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include + +/* DAC peripheral is not available on XMC1X devices. */ +#if defined(DAC) + +/** + * @addtogroup XMClib + * @{ + */ + +/** + * @addtogroup DAC + * @{ + * + * @brief Digital to Analog Converter (DAC) driver for XMC 4000 microcontroller family.
+ * + * DAC driver uses DAC peripheral to convert digital value to analog value. XMC4000 microcontroller family has two DAC channels of 12-bit resolution + * and maximum conversion rate of 2MHz with full accuracy and 5MHz with reduced accuracy. + * It consists of inbuilt pattern generator, ramp generator and noise generator modes. Additionally, waveforms can be generated by configuring data registers + * in single value mode and in data mode. + * It has DMA handling capability to generate custom waveforms in data mode without CPU intervention. + * + * DAC driver features: + * -# Configuration structure XMC_DAC_CH_CONFIG_t and initialization function XMC_DAC_CH_Init() to initialize DAC and configure channel settings + * -# Pattern Generator Mode: + * - DAC is configured in pattern generator mode using XMC_DAC_CH_StartPatternMode() + * - XMC_DAC_CH_SetPattern() is used to set the waveform pattern values in pattern register for one quarter + * - Allows to change the trigger frequency using XMC_DAC_CH_SetPatternFrequency() + * -# Single Value Mode: + * - DAC is configured in single value mode using XMC_DAC_CH_StartSingleValueMode() + * - Allows to change the trigger frequency using XMC_DAC_CH_SetFrequency() + * -# Data Mode: + * - DAC is configured in data mode using XMC_DAC_CH_StartDataMode() + * - Allows to change the trigger frequency using XMC_DAC_CH_SetFrequency() + * -# Ramp Mode: + * - DAC is configured in ramp generator mode using XMC_DAC_CH_StartRampMode() + * - Allows to change the trigger frequency using XMC_DAC_CH_SetRampFrequency() + * - Allows to set the start and stop values of the ramp using XMC_DAC_CH_SetRampStart() and XMC_DAC_CH_SetRampStop() + * -# Noise Mode: + * - DAC is configured in noise mode using XMC_DAC_CH_StartNoiseMode() + * - Allows to change the trigger frequency using XMC_DAC_CH_SetFrequency() + * -# Allows to change the scale, offset dynamically using XMC_DAC_CH_SetOutputScale() and XMC_DAC_CH_SetOutputOffset() respectively + * -# Allows to select one of the eight possible trigger sources using XMC_DAC_CH_SetTrigger() + * -# 2 DAC channels can be used in synchronization in single value mode and data mode to generate two analog outputs in sync. XMC_DAC_EnableSimultaneousDataMode() + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define XMC_DAC0 ((XMC_DAC_t *)DAC_BASE) /**< DAC module register base */ + +#define XMC_DAC_DACCFG_NEGATE_Msk (0x10000000UL) /*< DAC negation enable mask in XMC44 device */ +#define XMC_DAC_NO_CHANNELS (2U) /**< DAC maximum channels */ +#define XMC_DAC_SAMPLES_PER_PERIOD (32U) /**< DAC samples per period in pattern mode */ + +#define XMC_DAC_PATTERN_TRIANGLE {0U, 4U, 8U, 12U, 16U, 19U, 23U, 27U, 31U} /**< First quarter Triangle waveform samples */ +#define XMC_DAC_PATTERN_SINE {0U, 6U, 12U, 17U, 22U, 26U, 29U, 30U, 31U} /**< First quarter Sine waveform samples */ +#define XMC_DAC_PATTERN_RECTANGLE {31U, 31U, 31U, 31U, 31U, 31U, 31U, 31U, 31U} /**< First quarter Rectangle waveform samples */ + +#define XMC_DAC_IS_DAC_VALID(PTR) ((PTR) == XMC_DAC0) +#define XMC_DAC_IS_CHANNEL_VALID(CH) (CH < XMC_DAC_NO_CHANNELS) +#define XMC_DAC_IS_TRIGGER_VALID(TRIGGER) ((TRIGGER == XMC_DAC_CH_TRIGGER_INTERNAL) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_CCU80_SR1) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_CCU40_SR1) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_CCU41_SR1) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_P2_9) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_P2_8) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_U0C0_DX1INS) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_EXTERNAL_U1C0_DX1INS) ||\ + (TRIGGER == XMC_DAC_CH_TRIGGER_SOFTWARE)) +#define XMC_DAC_IS_MODE_VALID(MODE) ((MODE == XMC_DAC_CH_MODE_IDLE) ||\ + (MODE == XMC_DAC_CH_MODE_SINGLE) ||\ + (MODE == XMC_DAC_CH_MODE_DATA) ||\ + (MODE == XMC_DAC_CH_MODE_PATTERN) ||\ + (MODE == XMC_DAC_CH_MODE_NOISE) ||\ + (MODE == XMC_DAC_CH_MODE_RAMP)) +#define XMC_DAC_IS_OUTPUT_SCALE_VALID(SCALE) ((SCALE == XMC_DAC_CH_OUTPUT_SCALE_NONE) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_2) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_4) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_8) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_16) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_32) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_64) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_MUL_128) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_2) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_4) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_8) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_16) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_32) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_64) ||\ + (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_128)) + + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * Return types of the API's + */ +typedef enum XMC_DAC_CH_STATUS +{ + XMC_DAC_CH_STATUS_OK = 0U, /**< Status is ok, no error detected */ + XMC_DAC_CH_STATUS_ERROR = 1U, /**< Error detected */ + XMC_DAC_CH_STATUS_BUSY = 2U, /**< DAC is busy */ + XMC_DAC_CH_STATUS_ERROR_FREQ2LOW = 3U, /**< Frequency can't be configured. Frequency is to low. */ + XMC_DAC_CH_STATUS_ERROR_FREQ2HIGH = 4U /**< Frequency can't be configured. Frequency is to high. */ +} XMC_DAC_CH_STATUS_t; + +/** + * Operating modes of DAC + */ +typedef enum XMC_DAC_CH_MODE +{ + XMC_DAC_CH_MODE_IDLE = 0x0U << DAC_DAC0CFG0_MODE_Pos, /**< DAC is disabled */ + XMC_DAC_CH_MODE_SINGLE = 0x1U << DAC_DAC0CFG0_MODE_Pos, /**< Single value mode - single data value is updated and maintained */ + XMC_DAC_CH_MODE_DATA = 0x2U << DAC_DAC0CFG0_MODE_Pos, /**< Data mode - continuous data processing */ + XMC_DAC_CH_MODE_PATTERN = 0x3U << DAC_DAC0CFG0_MODE_Pos, /**< Pattern mode - inbuilt pattern waveform generation - + Sine, Triangle, Rectangle */ + XMC_DAC_CH_MODE_NOISE = 0x4U << DAC_DAC0CFG0_MODE_Pos, /**< Noise mode - pseudo-random noise generation */ + XMC_DAC_CH_MODE_RAMP = 0x5U << DAC_DAC0CFG0_MODE_Pos /**< Ramp mode - ramp generation */ +} XMC_DAC_CH_MODE_t; + +/** + * Trigger sources for the data update + */ +typedef enum XMC_DAC_CH_TRIGGER +{ + XMC_DAC_CH_TRIGGER_INTERNAL = + (0x0U << DAC_DAC0CFG1_TRIGMOD_Pos), /**< Internal trigger as per frequency divider value */ + XMC_DAC_CH_TRIGGER_EXTERNAL_CCU80_SR1 = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | 0x0U, /**< External trigger from CCU80 Interrupt SR1 */ + XMC_DAC_CH_TRIGGER_EXTERNAL_CCU40_SR1 = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x2U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from CCU40 Interrupt SR1 */ + XMC_DAC_CH_TRIGGER_EXTERNAL_CCU41_SR1 = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x3U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from CCU41 Interrupt SR1 */ + XMC_DAC_CH_TRIGGER_EXTERNAL_P2_9 = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x4U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from pin 2.9 */ + XMC_DAC_CH_TRIGGER_EXTERNAL_P2_8 = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x5U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from pin 2.8 */ + XMC_DAC_CH_TRIGGER_EXTERNAL_U0C0_DX1INS = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x6U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from USIC-0 DX1 Input Signal */ + XMC_DAC_CH_TRIGGER_EXTERNAL_U1C0_DX1INS = + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x7U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from USIC-1 DX1 Input Signal */ + XMC_DAC_CH_TRIGGER_SOFTWARE = + (0x2U << DAC_DAC0CFG1_TRIGMOD_Pos) /**< Software trigger */ +} XMC_DAC_CH_TRIGGER_t; + +/** + * Data type of the input data + */ +typedef enum XMC_DAC_CH_DATA_TYPE +{ + XMC_DAC_CH_DATA_TYPE_UNSIGNED = 0U , /**< input data is unsigned */ + XMC_DAC_CH_DATA_TYPE_SIGNED = 1U /**< input data is signed */ +} XMC_DAC_CH_DATA_TYPE_t; + +/** + * Scaling of the input data + */ +typedef enum XMC_DAC_CH_OUTPUT_SCALE +{ + XMC_DAC_CH_OUTPUT_SCALE_NONE = + 0x0U, /**< No scaling */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_2 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x1U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 2 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_4 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x2U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 4 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_8 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x3U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 8 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_16 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x4U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 16 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_32 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x5U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 32 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_64 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x6U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 64 */ + XMC_DAC_CH_OUTPUT_SCALE_MUL_128 = + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x7U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 128 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_2 = + 0x1U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 2 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_4 = + 0x2U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 4 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_8 = + 0x3U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 8 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_16 = + 0x4U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 16 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_32 = + 0x5U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 32 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_64 = + 0x6U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 64 */ + XMC_DAC_CH_OUTPUT_SCALE_DIV_128 = + 0x7U << DAC_DAC0CFG1_SCALE_Pos /**< divided by 128 */ +} XMC_DAC_CH_OUTPUT_SCALE_t; + +/** + * Negation of input data (applicable only for XMC44 device) + */ +typedef enum XMC_DAC_CH_OUTPUT_NEGATION +{ + XMC_DAC_CH_OUTPUT_NEGATION_DISABLED = 0U, /**< XMC_DAC_CH_OUTPUT_NEGATION_DISABLED */ + XMC_DAC_CH_OUTPUT_NEGATION_ENABLED = 1U /**< XMC_DAC_CH_OUTPUT_NEGATION_ENABLED */ +} XMC_DAC_CH_OUTPUT_NEGATION_t; + +/** + * Output sign signal for the Pattern Generation Mode + */ +typedef enum XMC_DAC_CH_PATTERN_SIGN_OUTPUT +{ + XMC_DAC_CH_PATTERN_SIGN_OUTPUT_DISABLED = 0U, /**< Sign output signal generation is disabled */ + XMC_DAC_CH_PATTERN_SIGN_OUTPUT_ENABLED = 1U /**< Sign output signal generation is enabled */ +} XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ +/** + * DAC peripheral registers configuration. + */ +typedef struct +{ + __I uint32_t ID; + + struct + { + __IO uint32_t low; + __IO uint32_t high; + } DACCFG[XMC_DAC_NO_CHANNELS]; + + __IO uint32_t DACDATA[XMC_DAC_NO_CHANNELS]; + __IO uint32_t DAC01DATA; + + struct + { + __IO uint32_t low; + __IO uint32_t high; + } DACPAT[XMC_DAC_NO_CHANNELS]; + +} XMC_DAC_t; + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Channel related configuration + */ +typedef struct XMC_DAC_CH_CONFIG +{ + union + { + struct + { + uint32_t :23; /**< Not used bits */ + uint32_t data_type:1; /**< input data type - unsigned / signed */ + uint32_t :4; /**< Not used bits */ + uint32_t output_negation:1; /**< Negation of the output waveform enabled/disabled */ + uint32_t :3; + }; + uint32_t cfg0; + }; + union + { + struct + { + uint32_t output_scale:4; /**< Scale value of type XMC_DAC_CH_OUTPUT_SCALE_t. It includes scaling + mul/div bit */ + uint32_t output_offset:8; /**< offset value */ + uint32_t :20; + }; + uint32_t cfg1; + }; +} XMC_DAC_CH_CONFIG_t; +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param dac Pointer to an instance of DAC module + * + * @return None + * + * \parDescription:
+ * Enables DAC clock and releases DAC reset.
+ * + * \par + * Enabling DAC is the first step of DAC initialisation. This API is called by XMC_DAC_CH_Init(). + * DAC clock is enabled by setting \a DAC bit of \a CGATCLR1 register. DAC reset is released by setting \a DACRS bit of \a PRCLR1 register. + * + * + * \parRelated APIs:
+ * XMC_DAC_IsEnabled(), XMC_DAC_Disable(), XMC_DAC_CH_Init()\n\n\n + * + */ +void XMC_DAC_Enable(XMC_DAC_t *const dac); + +/** + * @param dac Pointer to an instance of DAC module + * + * @return None + * + * \parDescription:
+ * Disables DAC clock and resets DAC. + * + * \par + * DAC clock is disabled by setting \a DAC bit of \a CGATSET1 register. DAC is reset by setting \a DACRS bit of \a PRSET1 register. + * + * \parRelated APIs:
+ * XMC_DAC_IsEnabled(), XMC_DAC_Enable()\n\n\n + * + */ +void XMC_DAC_Disable(XMC_DAC_t *const dac); + +/** + * @param dac Pointer to an instance of DAC module + * + * @return bool
+ * true - if DAC is enabled
+ * false - if DAC is disabled + * + * \parDescription:
+ * Returns the state of the DAC. + * + * \par + * DAC enabled status is determined by referring to \a DACRS bit of \a PRSTAT1 register. + * + * \parRelated APIs:
+ * XMC_DAC_Enable(), XMC_DAC_Disable()\n\n\n + * + */ +bool XMC_DAC_IsEnabled(const XMC_DAC_t *const dac); + +/** + * @param dac Pointer to an instance of DAC module + * + * @return None + * + * \parDescription:
+ * DAC switches to Simultaneous data mode from Independent data mode. + * + * \par + * Independent data mode is the default data mode. + * Simultaneous data mode is enabled by setting \a DATMOD bit of \a DAC0CFG1 register. + * + * \parNote:
+ * Set channel 0 and channel 1 to Data mode before calling this API. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartSingleValueMode(), XMC_DAC_CH_StartDataMode(), XMC_DAC_SimultaneousWrite(), XMC_DAC_DisableSimultaneousDataMode()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_EnableSimultaneousDataMode(XMC_DAC_t *const dac) +{ + XMC_ASSERT("XMC_DAC_EnableSimultaneousDataMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + + dac->DACCFG[0].high |= DAC_DAC0CFG1_DATMOD_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * + * @return None + * + * \parDescription:
+ * DAC switches to independent data mode from simultaneous Data mode. + * + * \par + * Independent data mode is the default data mode. + * Simultaneous data mode is disabled by clearing \a DATMOD bit of \a DAC0CFG1 register. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartDataMode(), XMC_DAC_EnableSimultaneousDataMode()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_DisableSimultaneousDataMode(XMC_DAC_t *const dac) +{ + XMC_ASSERT("XMC_DAC_DisableSimultaneousDataMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + + dac->DACCFG[0].high &= ~DAC_DAC0CFG1_DATMOD_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param data0 Data for DAC channel 0 [0-4095] + * @param data1 Data for DAC channel 1 [0-4095] + * + * @return None + * + * \parDescription:
+ * The data (\e data0 & \e data1) to be converted by channel 0 & channel 1 are updated to \a DATA1 bit-fields of \a DAC01DATA register. + * data0 and data1 have the range of [0-4095]. + * + * \parNote:
+ * Channel 0 and Channel 1 should be set to simultaneous data mode before calling this API. + * + * \parRelated APIs:
+ * XMC_DAC_EnableSimultaneousDataMode()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_SimultaneousWrite(XMC_DAC_t *const dac, const uint16_t data0, const uint16_t data1) +{ + XMC_ASSERT("XMC_DAC_SimultaneousWrite: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + + dac->DAC01DATA = (data0 << DAC_DAC01DATA_DATA0_Pos) | (data1 << DAC_DAC01DATA_DATA1_Pos); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param config Pointer to the DAC channel configuration structure + * + * @return None + * + * \parDescription:
+ * Initialises and configures the DAC \e channel with the configuration date pointed by \e config. + * + * \par + * DAC channel is initialised by configuring the registers \a DAC0CFG0 and \a DAC0CFG1 registers (for channel 0) / \a DAC1CFG0 and \a DAC1CFG1 registers (for channel 1). + * It enables the channel output by calling XMC_DAC_CH_EnableOutput(). + * + */ +void XMC_DAC_CH_Init(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_CONFIG_t *const config); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Channel \a channel output is enabled by setting the \a ANAEN bit of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \parNote:
+ * \a tSTARTUP time for DAC analog output starts after the \a ANAEN bit is set to one. + * After the expiry of the startup time the default value is driven to DAC output and a new value can be written. + * + * \parRelated APIs:
+ * XMC_DAC_CH_DisableOutput(), XMC_DAC_CH_IsOutputEnabled()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_EnableOutput(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_EnableOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_EnableOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].high |= DAC_DAC0CFG1_ANAEN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Channel \a channel output is disabled by clearing the \a ANAEN bit of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \par + * A call to this API stops driving the converted digital input to its output. + * + * \parRelated APIs:
+ * XMC_DAC_CH_EnableOutput(), XMC_DAC_CH_IsOutputEnabled()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_DisableOutput(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_DisableOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_DisableOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].high &= ~DAC_DAC0CFG1_ANAEN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return bool
+ * true - if analog output is enabled
+ * false - if analog output is disabled
+ * + * \parDescription:
+ * Returns the status of DAC analog output. + * + * \par + * Channel \a channel output enabled or disabled is determined by reading the \a ANAEN bit of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_EnableOutput(), XMC_DAC_CH_DisableOutput()\n\n\n + * + */ +__STATIC_INLINE bool XMC_DAC_CH_IsOutputEnabled(const XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_IsOutputEnabled: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_IsOutputEnabled: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return (bool)(dac->DACCFG[channel].high & DAC_DAC0CFG1_ANAEN_Msk); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param data Data to be written [0-4095] + * + * @return None + * + * \parDescription:
+ * Writes the \e data to the \e channel's DATA register. + * + * \par + * The \e data is then converted and driven to the output. + * If the trigger is set, On a trigger event the data in DATA register is converted and driven to \e channel output. + * Data \a data is written to the \a channel by loading \a data to \a DATA0 bit-field of \a DAC0DATA (for channel 0) / \a DATA1 bit-field of \a DAC1DATA register (for channel 1). + * data has the range of [0-4095]. + * + * \parNote:
+ * The API can be used for Single Value Mode, Data Mode (Individual) & Ramp Mode. + * Call XMC_DAC_CH_EnableOutput() API to enable analog output. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartSingleValueMode(), XMC_DAC_CH_StartDataMode(), XMC_DAC_CH_StartRampMode()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_Write(XMC_DAC_t *const dac, const uint8_t channel, const uint16_t data) +{ + XMC_ASSERT("XMC_DAC_CH_Write: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_Write: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACDATA[channel] = data; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Sets the \e channel to Single Value Mode by calling XMC_DAC_CH_SetMode(). + * + * \parNote:
+ * Call XMC_DAC_CH_Write() API to write the data. + * + * \parRelated APIs:
+ * XMC_DAC_CH_Write()\n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartSingleValueMode(XMC_DAC_t *const dac, const uint8_t channel); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param trigger Data points update trigger + * @param frequency Waveform frequency [Hz] + * + * @return XMC_DAC_CH_STATUS_t status + * + * \parDescription:
+ * Sets the \e channel to Data mode. Trigger and frequency are configured. + * + * \parNote:
+ * Call XMC_DAC_CH_Write() API to write the data. Call XMC_DAC_EnableSimultaneousDataMode() to switch to Simultaneous data mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_Init(), XMC_DAC_CH_Write(), XMC_DAC_EnableSimultaneousDataMode() \n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartDataMode(XMC_DAC_t *const dac, + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param start Start point of the ramp [0-4095] + * @param stop Stop point of the ramp [0-4095] + * @param trigger Data points update trigger + * @param frequency Ramp frequency in [Hz] + * + * @return XMC_DAC_CH_STATUS_t status + * + * \parDescription:
+ * Sets the \e channel to Ramp mode. Trigger, frequency, start and stop values are configured. + * On a \e trigger ramp values are converted and driven to \e channel output. + * Start and stop have the range of [0-4095]. Stop should be equal or greater than start. + * + * \parNote:
+ * If the ramp counter reaches its \e stop value, it restarts from the \e start value with the next trigger pulse. + * + * \parRelated APIs:
+ * XMC_DAC_CH_Init(), XMC_DAC_CH_GetRampStart(), XMC_DAC_CH_GetRampStop() \n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartRampMode(XMC_DAC_t *const dac, + const uint8_t channel, + const uint16_t start, + const uint16_t stop, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param pattern Data table of a pattern + * @param sign_output Sign information of the waveform + * @param trigger Data points update trigger + * @param frequency Waveform frequency in [Hz] + * + * @return XMC_DAC_CH_STATUS_t status + * + * \parDescription:
+ * Sets the \e channel to Pattern mode. Trigger, frequency, sign output and data are configured. + * On a \e trigger, the \e pattern values are converted and driven to \e channel output. + * + * \parRelated APIs:
+ * XMC_DAC_CH_Init(), XMC_DAC_CH_DisablePatternSignOutput() \n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartPatternMode(XMC_DAC_t *const dac, + const uint8_t channel, + const uint8_t *const pattern, + const XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t sign_output, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param trigger Data points update trigger + * @param frequency Waveform frequency in [Hz] + * + * @return XMC_DAC_CH_STATUS_t status + * + * \parDescription:
+ * Sets the \e channel to Noise mode. Trigger and frequency are configured. + * On a \e trigger the DAC starts converting and drives to \e channel output. + * + * \parRelated APIs:
+ * XMC_DAC_CH_Init()\n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartNoiseMode(XMC_DAC_t *const dac, + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param pattern Pointer to the data table + * + * @return None + * + * \parDescription:
+ * The data for the Pattern mode is written to the \a DAC0PATL and \a DAC0PATH registers. + * The API is called by XMC_DAC_CH_StartPatternMode(). + * + * \parNote:
+ * Call this API if the \a channel is set to Pattern mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_EnablePatternSignOutput(), XMC_DAC_CH_DisablePatternSignOutput()\n\n\n + * + */ +void XMC_DAC_CH_SetPattern(XMC_DAC_t *const dac, const uint8_t channel, const uint8_t *const pattern); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Enables the output sign information for Pattern Mode. + * + * \par + * Sign output is enabled by setting \a SIGNEN bit of \a DAC0CFG0 register (for channel 0) / DAC1CFG0 register (for channel 1). + * + * \parNote:
+ * Call this API if the \e channel is set to Pattern mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartPatternMode(), XMC_DAC_CH_DisablePatternSignOutput()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_EnablePatternSignOutput(XMC_DAC_t *const dac, + const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_EnablePatternSignOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_EnablePatternSignOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low |= DAC_DAC0CFG0_SIGNEN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Disables output sign information for Pattern Mode. + * + * \par + * Sign output is disabled by clearing \a SIGNEN bit of \a DAC0CFG0 register (for channel 0) / DAC1CFG0 register (for channel 1). + * + * \parNote:
+ * Call this API if the \e channel is set to Pattern mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartPatternMode(), XMC_DAC_CH_EnablePatternSignOutput()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_DisablePatternSignOutput(XMC_DAC_t *const dac, + const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_DisablePatternSignOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_DisablePatternSignOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low &= ~DAC_DAC0CFG0_SIGNEN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param start Ramp start point [0-4095] + * + * @return None + * + * \parDescription:
+ * Sets the ramp start value by writing to the register \a DAC0DATA (for \e channel 0) or \a DAC1DATA (for \e channel 1). + * If the ramp counter reaches its stop value, it restarts from the \a start value with the next trigger pulse. + * Ensure \e start value is lower than the stop value. + * + * \parNote:
+ * Call this API if the \a channel is set to Ramp mode. + * Start value is a 12 bit data. + * + * \parRelated APIs:
+ * XMC_DAC_CH_GetRampStart(), XMC_DAC_CH_GetRampStop(), XMC_DAC_CH_SetRampStop()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetRampStart(XMC_DAC_t *const dac, const uint8_t channel, const uint16_t start) +{ + XMC_ASSERT("XMC_DAC_CH_SetRampStart: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetRampStart: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACDATA[channel] = start; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return uint16_t + * + * \parDescription:
+ * Gets the ramp start value by reading \a DATA0 bit-field of \a DAC0DATA register (for channel 0) / \a DATA1 bit-field of \a DAC1DATA register (for channel 1). + * If the ramp counter reaches its stop value, it restarts from the start value with the next trigger pulse. + * + * \parNote:
+ * Call this API if the \e channel is set to Ramp mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetRampStart(), XMC_DAC_CH_StartRampMode(), XMC_DAC_CH_GetRampStop(), XMC_DAC_CH_SetRampStop()\n\n\n + * + */ +__STATIC_INLINE uint16_t XMC_DAC_CH_GetRampStart(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_GetRampStart: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_GetRampStart: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return (uint16_t)(dac->DACDATA[channel]); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param stop Ramp stop point [0-4095] + * + * @return None + * + * \parDescription:
+ * Sets the ramp stop value by writing to the bit-field \a DATA0 (for \e channel 0) or \a DATA1 (for \e channel 1) of \a DAC01DATA register. + * If the ramp counter reaches its \a stop value, it restarts from the start value with the next trigger pulse. + * Ensure \e stop value is higher than the start value. + * + * \parNote:
+ * Call this API if the \e channel is set to Ramp mode. + * Stop value is a 12 bit data. + * + * \parRelated APIs:
+ * XMC_DAC_CH_GetRampStop(), XMC_DAC_CH_SetRampStart()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetRampStop(XMC_DAC_t *const dac, const uint8_t channel, const uint16_t stop) +{ + XMC_ASSERT("XMC_DAC_CH_SetRampStop: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetRampStop: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DAC01DATA = (dac->DAC01DATA & ~(DAC_DAC01DATA_DATA0_Msk << (channel * DAC_DAC01DATA_DATA1_Pos))) | + (stop << (channel * DAC_DAC01DATA_DATA1_Pos)); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return uint16_t + * + * \parDescription:
+ * Gets the ramp stop value by reading \a DATA0 bit-field of \a DAC01DATA register (for channel 0) / \a DATA1 bit-field of \a DAC01DATA register (for channel 1). + * If the ramp counter reaches its stop value, it restarts from the start value with the next trigger pulse. + * + * \parNote:
+ * Call this API if the \e channel is set to Ramp mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetRampStop(), XMC_DAC_CH_StartRampMode(), XMC_DAC_CH_GetRampStart()\n\n\n + * + */ +__STATIC_INLINE uint16_t XMC_DAC_CH_GetRampStop(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_GetRampStop: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_GetRampStop: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return((dac->DAC01DATA >> (channel * DAC_DAC01DATA_DATA1_Pos)) & DAC_DAC01DATA_DATA0_Msk); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param trigger Trigger source + * + * @return None + * + * \parDescription:
+ * Selects the \e trigger source for the \e channel by configuring the bits TRIGSEL & TRIGMOD of CFG register. + * + * \par + * Channel \a channel trigger source is selected by \a TRIGSEL bit-field of \a DAC0CFG1 register (for channel 0) / DAC1CFG1 register(for channel 1). + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetTrigger(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_TRIGGER_t trigger) +{ + XMC_ASSERT("XMC_DAC_CH_SetTrigger: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetTrigger: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_SetTrigger: trigger parameter not valid\n", XMC_DAC_IS_TRIGGER_VALID(trigger)); + + dac->DACCFG[channel].high = (dac->DACCFG[channel].high & ~(DAC_DAC0CFG1_TRIGSEL_Msk | DAC_DAC0CFG1_TRIGMOD_Msk)) | + trigger; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param frequency Waveform frequency in [Hz] + * + * @return XMC_DAC_CH_STATUS_t + * + * \parDescription:
+ * Sets the \e frequency of DAC channel. + * + * \par + * The value \e frequency acts as clock divider. The smallest \e frequency divider value is 16. + * A valid \e frequency value should be within the range XMC_DAC_MIN_FREQ_DIVIDER to XMC_DAC_MAX_FREQ_DIVIDER. A value outside this range is considered as in valid and API returns error. + * Frequency \a frequency is configured by setting \a FREQ bit-field of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parNote:
+ * Call this API only for Single value mode, Data mode and Noise mode. + * Call XMC_DAC_CH_SetRampFrequency() in case of Ramp mode and XMC_DAC_CH_SetPatternFrequency() in case of Pattern mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetRampFrequency(), XMC_DAC_CH_SetPatternFrequency()\n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetFrequency(XMC_DAC_t *const dac, const uint8_t channel, const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param frequency [Hz] + * + * @return XMC_DAC_CH_STATUS_t + * + * \parDescription:
+ * Sets the \e frequency of DAC channel by calling XMC_DAC_CH_SetFrequency(). + * + * \par + * For the Ramp mode, the \a frequency of operation depends on the total number of sample points (\a stop - \a start). + * Frequency \e frequency is multiplied by the total number of sample points, so that each trigger instance converts all the sample points of ramp. + * + * \parNote:
+ * Call this API only if the \a channel is set to Ramp mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartRampMode()\n\n\n + * + */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetRampFrequency(XMC_DAC_t *const dac, const uint8_t channel, const uint32_t frequency); + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param frequency in [Hz] + * + * @return XMC_DAC_CH_STATUS_t + * + * \parDescription:
+ * Sets the \e frequency of DAC channel by calling XMC_DAC_CH_SetFrequency(). + * + * \par + * For the Pattern mode, the \a frequency of operation depends on the total number of sample points \a XMC_DAC_SAMPLES_PER_PERIOD. + * Frequency \e frequency is multiplied by the total number of sample points, so that each trigger instance converts all the sample points of the pattern. + * + * \parNote:
+ * Call this API only if the \a channel is set to Pattern mode. + * + * \parRelated APIs:
+ * XMC_DAC_CH_StartPatternMode()\n\n\n + * + */ +__STATIC_INLINE XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetPatternFrequency(XMC_DAC_t *const dac, + const uint8_t channel, + const uint32_t frequency) +{ + XMC_ASSERT("XMC_DAC_CH_SetPatternFrequency: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetPatternFrequency: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return XMC_DAC_CH_SetFrequency(dac, channel, frequency * XMC_DAC_SAMPLES_PER_PERIOD); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param mode DAC operation mode + * + * @return None + * + * \parDescription:
+ * Sets the operating \e mode for the \e channel by setting the \a MODE bit-field of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * Different modes of DAC operation are defined by enum XMC_DAC_CH_MODE_t. + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetMode(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_MODE_t mode) +{ + XMC_ASSERT("XMC_DAC_CH_SetMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_SetMode: trigger parameter not valid\n", XMC_DAC_IS_MODE_VALID(mode)); + + dac->DACCFG[channel].low = (dac->DACCFG[channel].low & ~DAC_DAC0CFG0_MODE_Msk) | + mode; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Sets the \e channel's data to signed type by setting \a SIGN bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * The data for the conversion would then be treated as signed data type. + * + * \parNote:
+ * Offset and scaling can be applied to the data by calling XMC_DAC_CH_SetOutputOffset(), XMC_DAC_CH_SetOutputScale(). + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetUnsignedDataType()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetSignedDataType(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_SetSignedDataType: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetSignedDataType: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low |= (DAC_DAC0CFG0_SIGN_Msk); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Sets the \e channel's data to unsigned type by clearing \a SIGN bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * The data for the conversion would then be treated as unsigned data type. + * + * \parNote:
+ * Offset and scaling can be applied to the data by calling XMC_DAC_CH_SetOutputOffset(), XMC_DAC_CH_SetOutputScale(). + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetSignedDataType()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetUnsignedDataType(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_SetUnsignedDataType: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetUnsignedDataType: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low &= ~(DAC_DAC0CFG0_SIGN_Msk); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * A call to this API generates a trigger pulse by setting \a SWTRIG bit of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1), + * provided the \a TRIGMOD bit of CFG register is set to \a XMC_DAC_CH_TRIGGER_SOFTWARE. + * + * \parNote:
+ * If the \e channel is set to simultaneous data mode, SWTRIG bit of \e channel 1 is not valid. + * Only \a SWTRIG bit of channel 0 is used for channel 1. + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetTrigger(), XMC_DAC_CH_EnableEvent()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SoftwareTrigger(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_SoftwareTrigger: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SoftwareTrigger: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].high |= DAC_DAC0CFG1_SWTRIG_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Enables service request by setting \a SREN bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * Trigger signal is generated upon conversion of each data. + * + * \parNote:
+ * The service request signal can be connected to NVIC, DMA.\n + * + * \parRelated APIs:
+ * XMC_DAC_CH_DisableEvent()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_EnableEvent(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_EnableEvent: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_EnableEvent: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low |= DAC_DAC0CFG0_SREN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return None + * + * \parDescription:
+ * Disables service request by clearing \a SREN bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_EnableEvent()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_DisableEvent(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_DisableEvent: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_DisableEvent: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low &= ~DAC_DAC0CFG0_SREN_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param offset + * + * @return None + * + * \parDescription:
+ * Sets the offset value.\n + * Offset range:0 - 255\n + * interpreted as : -128 to 127 (twos complement) in signed mode and 0 to 255 in unsigned mode. + * + * \parNote:
+ * Scaling can be applied to the output data after adding the \e offset value. + * + * \par + * Channel \a channel \a offset value is loaded to the bit-field \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetOutputScale()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetOutputOffset(XMC_DAC_t *const dac, const uint8_t channel, const uint8_t offset) +{ + XMC_ASSERT("XMC_DAC_CH_SetOutputOffset: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetOutputOffset: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].high = (dac->DACCFG[channel].high & ~DAC_DAC0CFG1_OFFS_Msk) | + offset << DAC_DAC0CFG1_OFFS_Pos; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * @param scale Input data scaling + * + * @return None + * + * \parDescription:
+ * Data of the \e channel is scaled. + * + * \par + * The data can either be scaled up-scaled (multiplied), down-scaled (divided) or no scaling (as is) based on the value of \e scale. + * Scaling is configured by setting bit-fields \a MULDIV and \a SCALE of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_GetOutputScale()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_SetOutputScale(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_OUTPUT_SCALE_t scale) +{ + XMC_ASSERT("XMC_DAC_CH_SetOutputScale: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetOutputScale: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_SetOutputScale: scale parameter not valid\n", XMC_DAC_IS_OUTPUT_SCALE_VALID(scale)); + + dac->DACCFG[channel].high = (dac->DACCFG[channel].high & ~(DAC_DAC0CFG1_MULDIV_Msk | DAC_DAC0CFG1_SCALE_Msk)) | + scale; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return XMC_DAC_CH_OUTPUT_SCALE_t + * + * \parDescription:
+ * Returns scaling information for the data. + * The input data could be either up-scaled (multiplied), down-scaled (divided) or without scaling (as is).\n + * Scaling factor is determined by reading bit-fields \a MULDIV and \a SCALE of \a DAC0CFG1 register (for channel 0) / \a DAC1CFG1 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_SetOutputScale()\n\n\n + * + */ +__STATIC_INLINE XMC_DAC_CH_OUTPUT_SCALE_t XMC_DAC_CH_GetOutputScale(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_GetOutputScale: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_GetOutputScale: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return (XMC_DAC_CH_OUTPUT_SCALE_t)(dac->DACCFG[channel].high & (DAC_DAC0CFG1_MULDIV_Msk | DAC_DAC0CFG1_SCALE_Msk)); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * \parDescription:
+ * Enables output negation. + * + * \par + * By negating the DAC value is converted to its two's complement values. + * Can be used in Ramp mode to generate negative ramp. + * Negation in enabled by setting \a NEGATE bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parNote:
+ * Negation feature is not applicable for XMC45 devices. Calling this API in XMC45 devices doesn't have any effect. + * + * \parRelated APIs:
+ * XMC_DAC_CH_DisableOutputNegation(), XMC_DAC_CH_StartRampMode()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_EnableOutputNegation(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_EnableOutputNegation: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_EnableOutputNegation: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low |= XMC_DAC_DACCFG_NEGATE_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * \parDescription:
+ * Disables output negation. + * + * \par + * Negation is disabled by clearing \a NEGATE bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parNote:
+ * Negation feature is not applicable for XMC45 devices. Calling this API in XMC45 devices doesn't have any effect. + * + * \parRelated APIs:
+ * XMC_DAC_CH_EnableOutputNegation()\n\n\n + * + */ +__STATIC_INLINE void XMC_DAC_CH_DisableOutputNegation(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_DisableOutputNegation: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_DisableOutputNegation: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + dac->DACCFG[channel].low &= ~XMC_DAC_DACCFG_NEGATE_Msk; +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return bool\n + * true - if FIFO is full\n + * false - if FIFO is not full + * + * \parDescription:
+ * Returns FIFO status.\n + * + * \par + * FIFIO full status is determined by reading \a FIFOFUL bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_IsFifoEmpty()\n\n\n + * + */ +__STATIC_INLINE bool XMC_DAC_CH_IsFifoFull(const XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_IsFifoFull: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_IsFifoFull: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return (bool)(dac->DACCFG[channel].low & DAC_DAC0CFG0_FIFOFUL_Msk); +} + +/** + * @param dac Pointer to an instance of DAC module + * @param channel DAC channel number + * + * @return bool\n + * true - if FIFO is empty\n + * false - if FIFO is not empty + * + * \parDescription:
+ * Returns FIFO status. + * + * \par + * FIFIO empty status is determined by reading \a FIFOEMP bit of \a DAC0CFG0 register (for channel 0) / \a DAC1CFG0 register (for channel 1). + * + * \parRelated APIs:
+ * XMC_DAC_CH_IsFifoFull()\n\n\n + * + */ +__STATIC_INLINE bool XMC_DAC_CH_IsFifoEmpty(const XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_IsFifoEmpty: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_IsFifoEmpty: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + + return (bool)(dac->DACCFG[channel].low & DAC_DAC0CFG0_FIFOEMP_Msk); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(DAC) */ + +#endif /* XMC_DAC_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_device.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_device.h new file mode 100644 index 00000000..fe346210 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_device.h @@ -0,0 +1,1514 @@ +/** + * @file xmc_device.h + * @date 2016-07-21 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial version + * + * 2015-09-23: + * - Added XMC14 and XMC48/47 + * + * 2015-11-19: + * - Added XMC43 + * + * 2016-02-26: + * - Fixed CCU8 version for XMC43/47/48 + * + * 2016-06-14: + * - Added XMC1201_T028x0016, XMC1202_T016x0064, XMC1301_T016x0032, XMC1302_Q040x0200, + * XMC1302_T028x0016, XMC1402_T038x0032, XMC1402_T038x0064, XMC1402_T038x0128, + * XMC1403_Q040x0064, XMC1403_Q040x0128, XMC1403_Q040x0200, XMC1402_T038x0200 + * XMC1402_Q040x0200, XMC1402_Q048x0200, XMC1201_T028x0032 + * @endcond + * + */ + +#ifndef XMC_DEVICE_H +#define XMC_DEVICE_H + +/* Family definitions */ +#define XMC4 (4) +#define XMC1 (1) + +/* Series definitions */ +#define XMC48 (48) +#define XMC47 (47) +#define XMC45 (45) +#define XMC44 (44) +#define XMC43 (43) +#define XMC42 (42) +#define XMC41 (41) +#define XMC14 (14) +#define XMC13 (13) +#define XMC12 (12) +#define XMC11 (11) + +/* Device definitions */ +#define XMC4800 (4800) +#define XMC4700 (4700) +#define XMC4500 (4500) +#define XMC4502 (4502) +#define XMC4504 (4504) +#define XMC4400 (4400) +#define XMC4402 (4402) +#define XMC4300 (4300) +#define XMC4200 (4200) +#define XMC4100 (4100) +#define XMC4104 (4104) +#define XMC4108 (4108) +#define XMC1401 (1401) +#define XMC1402 (1402) +#define XMC1403 (1403) +#define XMC1404 (1404) +#define XMC1300 (1300) +#define XMC1301 (1301) +#define XMC1302 (1302) +#define XMC1200 (1200) +#define XMC1201 (1201) +#define XMC1202 (1202) +#define XMC1203 (1203) +#define XMC1100 (1100) + +/* Package definitions */ +#define BGA144 (1) +#define LQFP144 (2) +#define LQFP100 (3) +#define BGA64 (4) +#define LQFP64 (5) +#define VQFN48 (6) +#define TSSOP38 (7) +#define TSSOP28 (8) +#define TSSOP16 (9) +#define VQFN24 (10) +#define VQFN40 (11) +#define VQFN64 (12) +#define BGA196 (13) + +#if defined(XMC4800_E196x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE BGA196 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F144x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F100x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_E196x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE BGA196 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F144x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F100x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_E196x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE BGA196 +#define UC_FLASH (1024UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F144x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (1024UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4800_F100x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC48 +#define UC_DEVICE XMC4800 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (1024UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_E196x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE BGA196 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_F144x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_F100x2048) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (2048UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_E196x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE BGA196 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_F144x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4700_F100x1536) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC47 +#define UC_DEVICE XMC4700 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (1536UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4500_E144x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4500 +#define UC_PACKAGE BGA144 +#define UC_FLASH (1024UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4500_F144x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4500 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (1024UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4500_F100x1024) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4500 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (1024UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4500_F144x768) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4500 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (768UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4500_F100x768) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4500 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (768UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4502_F100x768) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4502 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (768UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4504_F100x512) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4504 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (512UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4504_F144x512) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC45 +#define UC_DEVICE XMC4504 +#define UC_PACKAGE LQFP144 +#define UC_FLASH (512UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4400_F100x512) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4400 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (512UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4400_F64x512) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4400 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (512UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4400_F100x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4400 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4400_F64x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4400 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4402_F100x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4402 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4402_F64x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC44 +#define UC_DEVICE XMC4402 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4300_F100x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC43 +#define UC_DEVICE XMC4300 +#define UC_PACKAGE LQFP100 +#define UC_FLASH (256UL) +#define MULTICAN_PLUS +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC4200_E64x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC42 +#define UC_DEVICE XMC4200 +#define UC_PACKAGE BGA64 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4200_F64x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC42 +#define UC_DEVICE XMC4200 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4200_Q48x256) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC42 +#define UC_DEVICE XMC4200 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (256UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4100_E64x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4100 +#define UC_PACKAGE BGA64 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4100_F64x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4100 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4100_Q48x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4100 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_E64x64) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE BGA64 +#define UC_FLASH (64UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_F64x64) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (64UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_Q48x64) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_E64x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE BGA64 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_F64x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4104_Q48x128) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4104 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4108_Q48x64) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4108 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC4108_F64x64) +#define UC_FAMILY XMC4 +#define UC_SERIES XMC41 +#define UC_DEVICE XMC4108 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (64UL) +#define CCU4V1 +#define CCU8V1 + +#elif defined(XMC1100_Q024x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (8UL) +#define CCU4V2 + +#elif defined(XMC1100_Q024x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1100_Q024x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1100_Q024x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1100_Q040x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1100_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1100_Q040x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1100_T016x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (8UL) +#define CCU4V2 + +#elif defined(XMC1100_T016x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1100_T016x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1100_T016x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1100_T038x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1100_T038x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1100_T038x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC11 +#define UC_DEVICE XMC1100 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1201_Q040x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1201_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1201_Q040x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1201_Q040x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (128UL) +#define CCU4V2 + +#elif defined(XMC1201_Q040x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (200UL) +#define CCU4V2 + +#elif defined(XMC1201_T038x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1201_T038x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1201_T038x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1201_T038x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (128UL) +#define CCU4V2 + +#elif defined(XMC1201_T038x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (200UL) +#define CCU4V2 + +#elif defined(XMC1201_T028x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1201_T028x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1201 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1202_Q024x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1202_Q024x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1202_Q040x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1202_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1202_T016x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1202_T016x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1202_T016x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1202_T028x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (16UL) +#define CCU4V2 + +#elif defined(XMC1202_T028x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (64UL) +#define CCU4V2 + +#elif defined(XMC1202_T028x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1202 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (32UL) +#define CCU4V2 + +#elif defined(XMC1200_T038x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC12 +#define UC_DEVICE XMC1200 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (200UL) +#define CCU4V2 + +#elif defined(XMC1301_Q024x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (8UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_Q024x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_Q040x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (8UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_Q040x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T016x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (8UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T016x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T016x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T038x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (8UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T038x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T038x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1301_T038x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1301 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (64UL) + +#elif defined(XMC1302_Q024x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q024x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q024x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN24 +#define UC_FLASH (64UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q040x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q040x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (64UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q040x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (128UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_Q040x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (200UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T038x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T038x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T038x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (64UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T038x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (128UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T038x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (200UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T028x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T016x0008) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (8UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T016x0016) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (16UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T016x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP16 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1401_Q048x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1401 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define CCU4V3 + +#elif defined(XMC1401_Q048x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1401 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define CCU4V3 + +#elif defined(XMC1401_F064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1401 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (64UL) +#define CCU4V3 + +#elif defined(XMC1401_F064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1401 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (128UL) +#define CCU4V3 + +#elif defined(XMC1402_T038x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (32UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_T038x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (64UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_T038x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (128UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_T038x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE TSSOP38 +#define UC_FLASH (200UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q040x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (32UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q040x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (64UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q040x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (128UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q040x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (200UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q048x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (32UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q048x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q048x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q048x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (200UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (64UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (128UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_Q064x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (200UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_F064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (64UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_F064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (128UL) +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1402_F064x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1402 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (200UL) +#define CCU4V3 +#define CCU8V3 + + +#elif defined(XMC1403_Q048x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q048x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q048x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q040x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q040x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q040x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1403_Q064x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1403 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 + +#elif defined(XMC1404_Q048x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q048x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q048x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN48 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q064x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN64 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_F064x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_F064x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_F064x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE LQFP64 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#else +#error "xmc_device.h: device not supported" +#endif + +#if UC_SERIES == XMC45 +#include "XMC4500.h" +#define PERIPHERAL_RESET_SUPPORTED +#define USB_OTG_SUPPORTED + +#elif UC_SERIES == XMC44 +#include "XMC4400.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED +#define USB_OTG_SUPPORTED + +#elif UC_SERIES == XMC43 +#include "XMC4300.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED +#define USB_OTG_SUPPORTED + +#elif UC_SERIES == XMC42 +#include "XMC4200.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED + +#elif UC_SERIES == XMC41 +#include "XMC4100.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED + +#elif UC_SERIES == XMC47 +#include "XMC4700.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED +#define USB_OTG_SUPPORTED + +#elif UC_SERIES == XMC48 +#include "XMC4800.h" +#define CLOCK_GATING_SUPPORTED +#define PERIPHERAL_RESET_SUPPORTED +#define USB_OTG_SUPPORTED + +#elif UC_SERIES == XMC11 +#include "XMC1100.h" +#define CLOCK_GATING_SUPPORTED + +#elif UC_SERIES == XMC12 +#include "XMC1200.h" +#define CLOCK_GATING_SUPPORTED + +#elif UC_SERIES == XMC13 +#include "XMC1300.h" +#define CLOCK_GATING_SUPPORTED + +#elif UC_SERIES == XMC14 +#include "XMC1400.h" +#define CLOCK_GATING_SUPPORTED +#endif + +#endif /* XMC_DEVICE_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dma.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dma.h new file mode 100644 index 00000000..786cd555 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dma.h @@ -0,0 +1,1269 @@ + +/** + * @file xmc_dma.h + * @date 2016-10-28 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Add the declarations for the following APIs:
+ * XMC_DMA_DisableRequestLine, XMC_DMA_ClearRequestLine,
+ * XMC_DMA_CH_ClearSourcePeripheralRequest,
+ * XMC_DMA_CH_ClearDestinationPeripheralRequest
+ * - Documentation updates
+ * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2016-10-28: + * - Fix documentation on maximum block size + * + * @endcond + */ + +#ifndef XMC_DMA_H +#define XMC_DMA_H + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_common.h" + +#if defined (GPDMA0) + +#include "xmc_dma_map.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup DMA + * @brief General purpose DMA (GPDMA) driver for the XMC4000 microcontroller family + * + * The GPDMA is a highly configurable DMA controller that allows high-speed data transfers + * between peripherals and memories. Complex data transfers can be done with minimal + * intervention of the processor, making CPU available for other operations. + * + * GPDMA provides extensive support for XMC microcontroller peripherals like A/D, D/A + * converters and timers. Data transfers through communication interfaces (USIC) using the + * GPDMA increase efficiency and parallelism for real-time applications. + * + * The DMA low level driver provides functions to configure and initialize the GPDMA + * hardware peripheral. + * @{ + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#if defined (GPDMA0) +#define XMC_DMA0 ((XMC_DMA_t *)GPDMA0_CH0_BASE) /**< DMA module 0 */ +#define XMC_DMA0_NUM_CHANNELS 8 +#endif + +#if defined (GPDMA1) +#define XMC_DMA1 ((XMC_DMA_t *)GPDMA1_CH0_BASE) /**< DMA module 1, only available in XMC45xx series */ +#define XMC_DMA1_NUM_CHANNELS 4 +#endif + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * DMA transfer types + */ +typedef enum XMC_DMA_CH_TRANSFER_TYPE +{ + XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK, /**< Single block */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_RELOAD, /**< Multi-block: src address contiguous, dst address reload */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_CONTIGUOUS, /**< Multi-block: src address reload, dst address contiguous */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD, /**< Multi-block: src address reload, dst address reload */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_LINKED, /**< Multi-block: src address contiguous, dst address linked */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED, /**< Multi-block: src address reload, dst address linked */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_CONTIGUOUS, /**< Multi-block: src address linked, dst address contiguous */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_RELOAD, /**< Multi-block: src address linked, dst address reload */ + XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED /**< Multi-block: src address linked, dst address linked */ +} XMC_DMA_CH_TRANSFER_TYPE_t; + +/** + * DMA transfer flow modes + */ +typedef enum XMC_DMA_CH_TRANSFER_FLOW +{ + XMC_DMA_CH_TRANSFER_FLOW_M2M_DMA = 0x0UL, /**< Memory to memory (DMA flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA = 0x1UL, /**< Memory to peripheral (DMA flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA = 0x2UL, /**< Peripheral to memory (DMA flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA = 0x3UL, /**< Peripheral to peripheral (DMA flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_P2M_PER = 0x4UL, /**< Peripheral to memory (Peripheral flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_P2P_SRCPER = 0x5UL, /**< Peripheral to peripheral (Source peripheral flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_M2P_PER = 0x6UL, /**< Memory to peripheral (Peripheral flow controller) */ + XMC_DMA_CH_TRANSFER_FLOW_P2P_DSTPER = 0x7UL /**< Peripheral to peripheral (Destination peripheral flow controller) */ +} XMC_DMA_CH_TRANSFER_FLOW_t; + +/** + * Valid burst length values + */ +typedef enum XMC_DMA_CH_BURST_LENGTH +{ + XMC_DMA_CH_BURST_LENGTH_1 = 0x0UL, /**< Burst length: 1 word */ + XMC_DMA_CH_BURST_LENGTH_4 = 0x1UL, /**< Burst length: 4 words */ + XMC_DMA_CH_BURST_LENGTH_8 = 0x2UL /**< Burst length: 8 words */ +} XMC_DMA_CH_BURST_LENGTH_t; + +/** + * Valid transfer width values + */ +typedef enum XMC_DMA_CH_TRANSFER_WIDTH +{ + XMC_DMA_CH_TRANSFER_WIDTH_8 = 0x0UL, /**< 8-bit transfer width */ + XMC_DMA_CH_TRANSFER_WIDTH_16 = 0x1UL, /**< 16-bit transfer width */ + XMC_DMA_CH_TRANSFER_WIDTH_32 = 0x2UL /**< 32-bit transfer width */ +} XMC_DMA_CH_TRANSFER_WIDTH_t; + +/** + * DMA address count mode + */ +typedef enum XMC_DMA_CH_ADDRESS_COUNT_MODE +{ + XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT = 0x0UL, /**< Address count mode: increment */ + XMC_DMA_CH_ADDRESS_COUNT_MODE_DECREMENT = 0x1UL, /**< Address count mode: decrement */ + XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE = 0x2UL /**< Address count mode: no change */ +} XMC_DMA_CH_ADDRESS_COUNT_MODE_t; + +/** + * DMA channel priorities + */ +typedef enum XMC_DMA_CH_PRIORITY +{ + XMC_DMA_CH_PRIORITY_0 = 0x0UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 0 (low) */ + XMC_DMA_CH_PRIORITY_1 = 0x1UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 1 */ + XMC_DMA_CH_PRIORITY_2 = 0x2UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 2 */ + XMC_DMA_CH_PRIORITY_3 = 0x3UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 3 */ + XMC_DMA_CH_PRIORITY_4 = 0x4UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 4 */ + XMC_DMA_CH_PRIORITY_5 = 0x5UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 5 */ + XMC_DMA_CH_PRIORITY_6 = 0x6UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos, /**< DMA channel priority 6 */ + XMC_DMA_CH_PRIORITY_7 = 0x7UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos /**< DMA channel priority 7 (high) */ +} XMC_DMA_CH_PRIORITY_t; + +/** + * Source handshake interface + */ +typedef enum XMC_DMA_CH_SRC_HANDSHAKING +{ + XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE = 0x0UL << GPDMA0_CH_CFGL_HS_SEL_SRC_Pos, /**< Source: hardware handshake */ + XMC_DMA_CH_SRC_HANDSHAKING_SOFTWARE = 0x1UL << GPDMA0_CH_CFGL_HS_SEL_SRC_Pos /**< Source: software handshake */ +} XMC_DMA_CH_SRC_HANDSHAKING_t; + +/** + * Destination handshake interface + */ +typedef enum XMC_DMA_CH_DST_HANDSHAKING +{ + XMC_DMA_CH_DST_HANDSHAKING_HARDWARE = 0x0UL << GPDMA0_CH_CFGL_HS_SEL_DST_Pos, /**< Destination: hardware handshake */ + XMC_DMA_CH_DST_HANDSHAKING_SOFTWARE = 0x1UL << GPDMA0_CH_CFGL_HS_SEL_DST_Pos /**< Destination: software handshake */ +} XMC_DMA_CH_DST_HANDSHAKING_t; + +/** + * DMA hardware handshaking interface + * Hardware handshaking available only if DMA is flow controller + */ +typedef enum XMC_DMA_CH_HARDWARE_HANDSHAKING_IF +{ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_0 = 0x0UL, /**< Hardware handshaking interface 0 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_1 = 0x1UL, /**< Hardware handshaking interface 1 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_2 = 0x2UL, /**< Hardware handshaking interface 2 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_3 = 0x3UL, /**< Hardware handshaking interface 3 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_4 = 0x4UL, /**< Hardware handshaking interface 4 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_5 = 0x5UL, /**< Hardware handshaking interface 5 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_6 = 0x6UL, /**< Hardware handshaking interface 6 */ + XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_7 = 0x7UL /**< Hardware handshaking interface 7 */ +} XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_t; + +/** + * DMA events + */ +typedef enum XMC_DMA_CH_EVENT +{ + XMC_DMA_CH_EVENT_TRANSFER_COMPLETE = 0x1UL, /**< Transfer complete event */ + XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE = 0x2UL, /**< Block transfer complete event */ + XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE = 0x4UL, /**< Source transaction complete event */ + XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE = 0x8UL, /**< Destination transaction complete event */ + XMC_DMA_CH_EVENT_ERROR = 0x10UL /**< DMA error event */ +} XMC_DMA_CH_EVENT_t; + +/** + * Transaction types + */ +typedef enum XMC_DMA_CH_TRANSACTION_TYPE +{ + XMC_DMA_CH_TRANSACTION_TYPE_SINGLE, /**< Single DMA transaction */ + XMC_DMA_CH_TRANSACTION_TYPE_BURST /**< Burst transaction */ +} XMC_DMA_CH_TRANSACTION_TYPE_t; + +/** + * DMA channel status values + */ +typedef enum XMC_DMA_CH_STATUS +{ + XMC_DMA_CH_STATUS_OK, /**< DMA status OK */ + XMC_DMA_CH_STATUS_ERROR, /**< DMA status error */ + XMC_DMA_CH_STATUS_BUSY /**< DMA is busy */ +} XMC_DMA_CH_STATUS_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ + +/** + * DMA channel configuration structure
+ * + * The structure represents a collection of all hardware registers used + * to configure the DMA channel. It is contained within the ::XMC_DMA_t + * structure. It's registers can be used to configure DMA transfer details + * like source address, destination address, block size, incrementation + * modes and the like. + */ + +typedef struct { + __IO uint32_t SAR; + __I uint32_t RESERVED0; + __IO uint32_t DAR; + __I uint32_t RESERVED1; + __IO uint32_t LLP; + __I uint32_t RESERVED2; + __IO uint32_t CTLL; + __IO uint32_t CTLH; + __IO uint32_t SSTAT; + __I uint32_t RESERVED3; + __IO uint32_t DSTAT; + __I uint32_t RESERVED4; + __IO uint32_t SSTATAR; + __I uint32_t RESERVED5; + __IO uint32_t DSTATAR; + __I uint32_t RESERVED6; + __IO uint32_t CFGL; + __IO uint32_t CFGH; + __IO uint32_t SGR; + __I uint32_t RESERVED7; + __IO uint32_t DSR; + __I uint32_t RESERVED8; +} GPDMA_CH_t; + +/** + * DMA device structure
+ * + * The structure represents a collection of all hardware registers used + * to configure the GPDMA peripheral on the XMC4000 series of microcontrollers. + * The registers can be accessed with ::XMC_DMA0 and ::XMC_DMA1. + */ +typedef struct { + GPDMA_CH_t CH[8]; + + __IO uint32_t RAWCHEV[10]; + __I uint32_t STATUSCHEV[10]; + __IO uint32_t MASKCHEV[10]; + __O uint32_t CLEARCHEV[10]; + __I uint32_t STATUSGLEV; + __I uint32_t RESERVED20; + __IO uint32_t REQSRCREG; + __I uint32_t RESERVED21; + __IO uint32_t REQDSTREG; + __I uint32_t RESERVED22; + __IO uint32_t SGLREQSRCREG; + __I uint32_t RESERVED23; + __IO uint32_t SGLREQDSTREG; + __I uint32_t RESERVED24; + __IO uint32_t LSTSRCREG; + __I uint32_t RESERVED25; + __IO uint32_t LSTDSTREG; + __I uint32_t RESERVED26; + __IO uint32_t DMACFGREG; + __I uint32_t RESERVED27; + __IO uint32_t CHENREG; + __I uint32_t RESERVED28; + __I uint32_t ID; + __I uint32_t RESERVED29[19]; + __I uint32_t TYPE; + __I uint32_t VERSION; +} XMC_DMA_t; + +/* Anonymous structure/union guard start */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__TASKING__) + #pragma warning 586 +#endif + +/** + * DMA channel linked list item. + * Note: Needs to be word aligned + */ +typedef struct XMC_DMA_LLI +{ + uint32_t src_addr; /**< Source address */ + uint32_t dst_addr; /**< Destination address */ + struct XMC_DMA_LLI *llp; /**< Linked list pointer of type XMC_DMA_LLI_t */ + union + { + struct + { + uint32_t enable_interrupt: 1; /**< Enable interrupts? */ + uint32_t dst_transfer_width: 3; /**< Destination transfer width */ + uint32_t src_transfer_width: 3; /**< Source transfer width */ + uint32_t dst_address_count_mode: 2; /**< Destination address count mode */ + uint32_t src_address_count_mode: 2; /**< Source address count mode */ + uint32_t dst_burst_length: 3; /**< Destination burst length */ + uint32_t src_burst_length: 3; /**< Source burst length */ + uint32_t enable_src_gather: 1; /**< Enable source gather? */ + uint32_t enable_dst_scatter: 1; /**< Enable destination scatter? */ + uint32_t : 1; /**< Reserved bits */ + uint32_t transfer_flow: 3; /**< DMA transfer flow */ + uint32_t : 4; /**< Reserved bits */ + uint32_t enable_dst_linked_list: 1; /**< Enable destination linked list? */ + uint32_t enable_src_linked_list: 1; /**< Enable source linked list? */ + uint32_t : 3; /**< Reserved bits */ + }; + uint32_t control; + }; + uint32_t block_size; /**< Transfer block size */ + uint32_t src_status; /**< Source status */ + uint32_t dst_status; /**< Destination status */ +} XMC_DMA_LLI_t; + +typedef XMC_DMA_LLI_t **XMC_DMA_LIST_t; /**< Type definition for a linked list pointer */ + +/** + * DMA channel configuration structure + */ +typedef struct XMC_DMA_CH_CONFIG +{ + union + { + uint32_t control; + struct + { + uint32_t enable_interrupt: 1; /**< Enable interrupts? */ + uint32_t dst_transfer_width: 3; /**< Destination transfer width */ + uint32_t src_transfer_width: 3; /**< Source transfer width */ + uint32_t dst_address_count_mode: 2; /**< Destination address count mode */ + uint32_t src_address_count_mode: 2; /**< Source address count mode */ + uint32_t dst_burst_length: 3; /**< Destination burst length */ + uint32_t src_burst_length: 3; /**< Source burst length */ + uint32_t enable_src_gather: 1; /**< Enable source gather? */ + uint32_t enable_dst_scatter: 1; /**< Enable destination scatter? */ + uint32_t : 1; + uint32_t transfer_flow: 3; /**< DMA transfer flow */ + uint32_t : 9; + }; + }; + + uint32_t src_addr; /**< Source address */ + uint32_t dst_addr; /**< Destination address */ + XMC_DMA_LLI_t *linked_list_pointer; /**< Linked list pointer */ + + union + { + uint32_t src_gather_control; + struct + { + uint32_t src_gather_interval: 20; /**< Source gather interval */ + uint32_t src_gather_count: 12; /**< Source gather count */ + }; + }; + + union + { + uint32_t dst_scatter_control; + struct + { + uint32_t dst_scatter_interval: 20; /**< Destination scatter interval */ + uint32_t dst_scatter_count: 12; /**< Destination scatter count */ + }; + }; + + uint16_t block_size; /**< Block size for DMA controlled transfers [max. 4095]*/ + XMC_DMA_CH_TRANSFER_TYPE_t transfer_type; /**< DMA transfer type */ + XMC_DMA_CH_PRIORITY_t priority; /**< DMA channel priority */ + XMC_DMA_CH_SRC_HANDSHAKING_t src_handshaking; /**< DMA source handshaking interface */ + uint8_t src_peripheral_request; /**< Source peripheral request */ + XMC_DMA_CH_DST_HANDSHAKING_t dst_handshaking; /**< DMA destination handshaking interface */ + uint8_t dst_peripheral_request; /**< Destination peripheral request */ +} XMC_DMA_CH_CONFIG_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__TASKING__) + #pragma warning restore +#endif + +/** + * DMA channel event handler + */ +typedef void (*XMC_DMA_CH_EVENT_HANDLER_t)(XMC_DMA_CH_EVENT_t event); + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return None + * + * \parDescription:
+ * Initialize the GPDMA peripheral
+ * + * \par + * The function initializes a prioritized list of DMA channels and enables the GPDMA + * peripheral. + */ +void XMC_DMA_Init(XMC_DMA_t *const dma); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return None + * + * \parDescription:
+ * Enable the GPDMA peripheral
+ * + * \par + * The function de-asserts the GPDMA peripheral reset. In addition, it un-gates the + * GPDMA0 peripheral clock for all XMC4000 series of microcontrollers with an exception + * of the XMC4500 microcontroller. The XMC4500 doesn't support gating. + */ +void XMC_DMA_Enable(XMC_DMA_t *const dma); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return None + * + * \parDescription:
+ * Disable the GPDMA peripheral
+ * + * \par + * The function asserts the GPDMA peripheral reset. In addition, it gates the GPDMA0 + * peripheral clock for all XMC4000 series of microcontrollers with an exception of + * the XMC4500 microcontroller. The XMC4500 doesn't support gating. + */ +void XMC_DMA_Disable(XMC_DMA_t *const dma); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return bool + * + * \parDescription:
+ * Check if the GPDMA peripheral is enabled
+ * + * \par + * For the XMC4500 microcontroller, the function checks if the GPDMA module is asserted + * and returns "false" if it is. In addition, it also checks if the clock is gated + * for the other XMC4000 series of microcontrollers. It returns "true" if the peripheral + * is enabled. + */ +bool XMC_DMA_IsEnabled(const XMC_DMA_t *const dma); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA event status + * + * \parDescription:
+ * Get DMA event status
+ * + * \par + * The function returns the collective (global) status of GPDMA events. The following + * lists the various DMA events and their corresponding enumeration. The return value + * of this function may then be masked with any one of the following enumerations to + * obtain the status of individual DMA events.
+ * + * \par + * Transfer complete -> ::XMC_DMA_CH_EVENT_TRANSFER_COMPLETE
+ * Block transfer complete -> ::XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE
+ * Source transaction complete -> ::XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE
+ * Destination transaction complete -> ::XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE
+ * DMA error event -> ::XMC_DMA_CH_EVENT_ERROR
+ */ +__STATIC_INLINE uint32_t XMC_DMA_GetEventStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSGLEV); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA transfer complete status + * + * \parDescription:
+ * Get transfer complete status
+ * + * \par + * The function returns GPDMA transfer complete interrupt status.
+ */ +__STATIC_INLINE uint32_t XMC_DMA_GetChannelsTransferCompleteStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSCHEV[0]); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA block complete status + * + * \parDescription:
+ * Get block transfer complete status
+ * + * \par + * The function returns GPDMA block transfer complete interrupt status.
+ */ +__STATIC_INLINE uint32_t XMC_DMA_GetChannelsBlockCompleteStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSCHEV[2]); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA event status + * + * \parDescription:
+ * Get source transaction complete status
+ * + * \par + * The function returns the source transaction complete interrupt status.
+ * + * \parNote:
+ * If the source peripheral is memory, the source transaction complete interrupt is + * ignored. + */ +__STATIC_INLINE uint32_t XMC_DMA_GetChannelsSourceTransactionCompleteStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSCHEV[4]); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA event status + * + * \parDescription:
+ * Get destination transaction complete status
+ * + * \par + * The function returns the destination transaction complete interrupt status
+ * + * \parNote:
+ * If the destination peripheral is memory, the destination transaction complete + * interrupt is ignored. + */ +__STATIC_INLINE uint32_t XMC_DMA_GetChannelsDestinationTransactionCompleteStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSCHEV[6]); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return uint32_t DMA error event status + * + * \parDescription:
+ * Get DMA error event status
+ * + * \par + * The function returns error interrupt status.
+ */ +__STATIC_INLINE uint32_t XMC_DMA_GetChannelsErrorStatus(XMC_DMA_t *const dma) +{ + return (dma->STATUSCHEV[8]); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param line Which DLR (DMA line router) line should the function use? + * @param peripheral Which hardware peripheral is the GPDMA communicating with? + * @return None + * + * \parDescription:
+ * Enable request line
+ * + * \par + * The function enables a DLR (DMA line router) line and selects a service request + * source, resulting in the trigger of a DMA transfer.
+ * + * \parNote:
+ * The DLR is used for a DMA transfer typically involving a peripheral; For example, + * the ADC peripheral may use the DLR in hardware handshaking mode to transfer + * ADC conversion values to a destination memory block. + */ +void XMC_DMA_EnableRequestLine(XMC_DMA_t *const dma, uint8_t line, uint8_t peripheral); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param line Which DLR (DMA line router) line should the function use? + * @return None + * + * \parDescription:
+ * Disable request line
+ * + * \par + * The function disables a DLR (DMA line router) line by clearing appropriate bits + * in the LNEN register.
+ */ +void XMC_DMA_DisableRequestLine(XMC_DMA_t *const dma, uint8_t line); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param line Which DLR (DMA line router) line should the function use? + * @return None + * + * \parDescription:
+ * Clear request line
+ * + * \par + * The function clears a DLR (DMA line router) request line.
+ */ +void XMC_DMA_ClearRequestLine(XMC_DMA_t *const dma, uint8_t line); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param line The line for which the overrun status is requested + * @return bool "true" if overrun occured, "false" otherwise + * + * \parDescription:
+ * Get overrun status of a DLR line
+ * + * \par + * The DLR module's OVERSTAT register keeps track of DMA service request overruns. + * Should an overrun occur, the bit corresponding to the used DLR line is set. The + * function simply reads this status and returns "true" if an overrun is detected + * It returns "false" if an overrun isn't registered. + */ +bool XMC_DMA_GetOverrunStatus(XMC_DMA_t *const dma, const uint8_t line); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param line The line for which the overrun status must be cleared + * @return None + * + * \parDescription:
+ * Clear overrun status of a DLR line
+ * + * \par + * The function clears the overrun status of a line by setting the corresponding + * line bit in the DLR's OVERCLR register. + */ +void XMC_DMA_ClearOverrunStatus(XMC_DMA_t *const dma, const uint8_t line); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The GPDMA channel (number) which needs to be initialized + * @param config A constant pointer to ::XMC_DMA_CH_CONFIG_t, pointing to a const + * channel configuration + * @return XMC_DMA_CH_STATUS_t Initialization status + * + * \parDescription:
+ * Initialize a GPDMA channel with provided channel configuration
+ * + * \par + * The function sets up the following channel configuration parameters for a GPDMA + * channel (specified by the parameter channel):
+ * 1) Source and destination addresses (and linked list address if requested)
+ * 2) Source and destination handshaking interface (hardware or software?)
+ * 3) Scatter/gather configuration
+ * 4) Source and destination peripheral request (DMA is the flow controller)
+ * 5) Transfer flow and type
+ * + * \par + * The function returns one of the following values:
+ * 1) In case the DMA channel is not enabled: ::XMC_DMA_CH_STATUS_BUSY
+ * 2) If the GPDMA module itself is not enabled: ::XMC_DMA_CH_STATUS_ERROR
+ * 3) If the configuration was successful: ::XMC_DMA_CH_STATUS_OK
+ * + * \par + * Once the initialization is successful, calling ::XMC_DMA_CH_Enable() will trigger + * a GPDMA transfer. + */ +XMC_DMA_CH_STATUS_t XMC_DMA_CH_Init(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_CONFIG_t *const config); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should be enabled? + * @return None + * + * \parDescription:
+ * Enable a GPDMA channel
+ * + * \par + * The function sets the GPDMA's CHENREG register to enable a DMA channel. Please + * ensure that the GPDMA module itself is enabled before calling this function. + * See ::XMC_DMA_Enable() for details. + */ +__STATIC_INLINE void XMC_DMA_CH_Enable(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CHENREG = (uint32_t)(0x101UL << channel); +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should be disabled? + * @return None + * + * \parDescription:
+ * Disable a GPDMA channel
+ * + * \par + * The function resets the GPDMA's CHENREG register to disable a DMA channel. + */ +void XMC_DMA_CH_Disable(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should be disabled? + * @return bool + * + * \parDescription:
+ * Check if a GPDMA channel is enabled
+ * + * \par + * The function reads the GPDMA's CHENREG register to check if a DMA channel is + * enabled or not. The function returns "true" is the requested channel is enabled, + * "false" otherwise. + */ +bool XMC_DMA_CH_IsEnabled(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should suspend transfer? + * @return None + * + * \parDescription:
+ * Suspend a GPDMA channel transfer
+ * + * \par + * The function sets the CH_SUSP bit of the GPDMA's GFGL register to initiate a + * DMA transfer suspend. The function may be called after enabling the DMA channel. + * Please see ::XMC_DMA_CH_Enable() for more information. + * + * \parRelated API:
+ * ::XMC_DMA_CH_Resume()
+ */ +void XMC_DMA_CH_Suspend(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should resume transfer? + * @return None + * + * \parDescription:
+ * Resume a GPDMA channel
+ * + * \par + * The function clears the CH_SUSP bit of the GPDMA's GFGL register to resume a + * DMA transfer. The function may be called after enabling the DMA channel. Please + * see ::XMC_DMA_CH_Enable() for more information. + * + * \parRelated API:
+ * ::XMC_DMA_CH_Suspend()
+ */ +void XMC_DMA_CH_Resume(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel A DMA channel + * @param addr source address + * @return None + * + * \parDescription:
+ * This function sets the source address of the specified channel
+ * + * \par + * The function may be called after enabling the DMA channel. Please + * see ::XMC_DMA_CH_Enable() for more information. + * + * \parRelated API:
+ * ::XMC_DMA_CH_SetDestinationAddress()
+ */ +__STATIC_INLINE void XMC_DMA_CH_SetSourceAddress(XMC_DMA_t *const dma, const uint8_t channel, uint32_t addr) +{ + dma->CH[channel].SAR = addr; +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel A DMA channel + * @param addr destination address + * @return None + * + * \parDescription:
+ * This function sets the destination address of the specified channel
+ * + * \par + * The function may be called after enabling the DMA channel. Please + * see ::XMC_DMA_CH_Enable() for more information. + * + * \parRelated API:
+ * ::XMC_DMA_CH_SetSourceAddress()
+ */ +__STATIC_INLINE void XMC_DMA_CH_SetDestinationAddress(XMC_DMA_t *const dma, const uint8_t channel, uint32_t addr) +{ + dma->CH[channel].DAR = addr; +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel A DMA channel + * @param block_size Transfer size [1-2048] + * @return None + * + * \parDescription:
+ * This function sets the block size of a transfer
+ * + * \par + * The function may be called after enabling the DMA channel. Please + * see ::XMC_DMA_CH_Enable() for more information. + * + */ +__STATIC_INLINE void XMC_DMA_CH_SetBlockSize(XMC_DMA_t *const dma, const uint8_t channel, uint32_t block_size) +{ + dma->CH[channel].CTLH = block_size; +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel A DMA channel + * @param ll_ptr linked list pointer + * @return None + * + * \parDescription:
+ * This function sets the linked list pointer
+ * + * \par + * The function may be called after enabling the DMA channel. Please + * see ::XMC_DMA_CH_Enable() for more information. + * + */ +__STATIC_INLINE void XMC_DMA_CH_SetLinkedListPointer(XMC_DMA_t *const dma, const uint8_t channel, XMC_DMA_LLI_t *ll_ptr) +{ + dma->CH[channel].LLP = (uint32_t)ll_ptr; +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel should be checked for a suspended transfer? + * @return bool + * + * \parDescription:
+ * Check if a GPDMA
+ * + * \par + * The function reads the CH_SUSP bit of the GPDMA's GFGL register to check if a + * DMA transfer for the requested channel has been suspended. The function returns + * "true" if it detects a transfer suspension or "false" if it doesn't. + * + * \parRelated API:
+ * ::XMC_DMA_CH_Suspend(), ::XMC_DMA_CH_Resume()
+ */ +bool XMC_DMA_CH_IsSuspended(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the event(s) need(s) to be enabled + * @param event A valid GPDMA event (::XMC_DMA_CH_EVENT_t) or a valid combination + * of logically OR'd GPDMA events + * @return None + * + * \parDescription:
+ * Enable GPDMA event(s)
+ * + * \par + * The following events are supported by the GPDMA peripheral:
+ * 1) Transfer complete event
+ * 2) Block transfer complete event
+ * 3) Source transaction complete event
+ * 4) Destination transaction complete event
+ * 5) DMA error event
+ * + * \par + * The function can be used to enable one (or more) of the aforementioned events. + * Once the events have been enabled, ::XMC_DMA_CH_SetEventHandler() API can be + * used to set a callback function. + */ +void XMC_DMA_CH_EnableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the event(s) need(s) to be disabled + * @param event A valid GPDMA event (::XMC_DMA_CH_EVENT_t) or a valid combination + * of logically OR'd GPDMA events + * @return None + * + * \parDescription:
+ * Disable GPDMA event(s)
+ * + * \par + * The following events are supported by the GPDMA peripheral:
+ * 1) Transfer complete event
+ * 2) Block transfer complete event
+ * 3) Source transaction complete event
+ * 4) Destination transaction complete event
+ * 5) DMA error event
+ * + * \par + * The function can be used to disable one (or more) of the aforementioned events. + */ +void XMC_DMA_CH_DisableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the event(s) need(s) to be disabled + * @param event A valid GPDMA event (::XMC_DMA_CH_EVENT_t) or a valid combination + * of logically OR'd GPDMA events + * @return None + * + * \parDescription:
+ * Clear GPDMA event status
+ * + * \par + * The following events are supported by the GPDMA peripheral:
+ * 1) Transfer complete event
+ * 2) Block transfer complete event
+ * 3) Source transaction complete event
+ * 4) Destination transaction complete event
+ * 5) DMA error event
+ * + * \par + * The function is used to clear the status of one (or more) of the aforementioned + * events. Typically, its use is in the GPDMA interrupt handler function. Once an + * event is detected, an appropriate callback function must run and the event status + * should be cleared. + */ +void XMC_DMA_CH_ClearEventStatus(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the event(s) status must be obtained + * @return Event status + * + * \parDescription:
+ * Get GPDMA channel event status
+ * + * \par + * The function is used obtain the status of one (or more) of the aforementioned + * events. The return value may then be masked with any one of the following + * enumerations to obtain the status of individual DMA events.
+ * + * \par + * Transfer complete -> ::XMC_DMA_CH_EVENT_TRANSFER_COMPLETE
+ * Block transfer complete -> ::XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE
+ * Source transaction complete -> ::XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE
+ * Destination transaction complete -> ::XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE
+ * DMA error event -> ::XMC_DMA_CH_EVENT_ERROR
+ * + * \par + * Typically, its use is in the GPDMA interrupt handler function. Once an event is + * detected, an appropriate callback function must run and the event status should + * be cleared. + */ +uint32_t XMC_DMA_CH_GetEventStatus(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel is used for source gather? + * @param interval Gather interval + * @param count Gather count + * @return None + * + * \parDescription:
+ * Enable source gather
+ * + * \par + * The function is used to enable the source gather feature in the GPDMA peripheral. + * The user must also specify the gather count and interval. Once the configuration + * is successful, calling ::XMC_DMA_CH_EnableEvent() will initiate source gather. + * This function is normally used in conjunction with destination scatter. Please + * see ::XMC_DMA_CH_EnableDestinationScatter() for additional information. + */ +void XMC_DMA_CH_EnableSourceGather(XMC_DMA_t *const dma, const uint8_t channel, uint32_t interval, uint16_t count); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The source gather for which DMA channel is to be disabled? + * @return None + * + * \parDescription:
+ * Disable source gather
+ * + * \par + * The function is used to disable the source gather feature in the GPDMA peripheral. + */ +void XMC_DMA_CH_DisableSourceGather(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel is used for destination scatter? + * @param interval Scatter interval + * @param count Scatter count + * @return None + * + * \parDescription:
+ * Enable destination scatter
+ * + * \par + * The function is used to enable the destination scatter feature in the GPDMA + * peripheral. The user must also specify the scatter count and interval. Once + * the configuration is successful, calling ::XMC_DMA_CH_EnableEvent() will + * initiate destination gather. This function is normally used in conjunction + * with source gather. Please see ::XMC_DMA_CH_EnableSourceGather() for + * additional information. + */ +void XMC_DMA_CH_EnableDestinationScatter(XMC_DMA_t *const dma, const uint8_t channel, uint32_t interval, uint16_t count); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The source gather for which DMA channel is to be disabled? + * @return None + * + * \parDescription:
+ * Disable source gather
+ * + * \par + * The function is used to disable the destination scatter feature in the GPDMA + * peripheral. + */ +void XMC_DMA_CH_DisableDestinationScatter(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel is being used? + * @param type Transaction type: Single/burst mode + * @param last Specify "true" if it is the last source request trigger, "false" + * otherwise + * @return None + * + * \parDescription:
+ * Trigger source request
+ * + * \par + * The function can be used for GPDMA transfers involving a peripheral in software + * handshaking mode viz. Memory -> peripheral and peripheral -> peripheral. + * + * \par + * One would typically use this function in a (destination) peripheral's event + * callback function to trigger the source request. + */ +void XMC_DMA_CH_TriggerSourceRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel is being used? + * @param type Transaction type: Single/burst mode + * @param last Specify "true" if it is the last destination request trigger, "false" + * otherwise + * @return None + * + * \parDescription:
+ * Trigger destination request
+ * + * \par + * The function can be used for GPDMA transfers involving a peripheral in software + * handshaking mode viz. Peripheral -> memory and peripheral -> peripheral. + * + * \par + * One would typically use this function in a (source) peripheral's event + * callback function to trigger the destination request. + */ +void XMC_DMA_CH_TriggerDestinationRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the source address must be reloaded + * @return None + * + * \parDescription:
+ * Enable source address reload
+ * + * \par + * The function is used to automatically reload the source DMA address (from its + * initial value) at the end of every block in a multi-block transfer. The auto- + * reload will begin soon after the DMA channel initialization (configured for a + * multi-block transaction). + */ +void XMC_DMA_CH_EnableSourceAddressReload(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the source address reload must be disabled + * @return None + * + * \parDescription:
+ * Disable source address reload
+ * + * \par + * The source DMA address can be automatically reloaded from its initial value at + * the end of every block in a multi-block transfer. To disable this feature, use + * this function. + */ +void XMC_DMA_CH_DisableSourceAddressReload(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the destination address must be reloaded + * @return None + * + * \parDescription:
+ * Enable source address reload
+ * + * \par + * The function is used to automatically reload the destination DMA address (from + * its initial value) at the end of every block in a multi-block transfer. The auto- + * reload will begin soon after the DMA channel initialization (configured for a + * multi-block transaction). + */ +void XMC_DMA_CH_EnableDestinationAddressReload(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the destination address reload must be + * disabled + * @return None + * + * \parDescription:
+ * Disable destination address reload
+ * + * \par + * The destination DMA address can be automatically reloaded from its initial value + * at the end of every block in a multi-block transfer. To disable this feature, + * use this function. + */ +void XMC_DMA_CH_DisableDestinationAddressReload(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel Which DMA channel is participating in a multi-block transfer? + * @return None + * + * \parDescription:
+ * Trigger the end of a multi-block transfer
+ * + * \par + * The function is used signal the end of multi-block DMA transfer. It clears the + * RELOAD_SRC and RELOAD_DST bits of the CFGL register to keep the source and + * destination addresses from getting updated. The function is typically used in + * an event handler to signal that the next block getting transferred is the last + * block in the transfer sequence. + */ +void XMC_DMA_CH_RequestLastMultiblockTransfer(XMC_DMA_t *const dma, const uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The channel for which the event handler is being registered + * @param event_handler The event handler which will be invoked when the DMA event + * occurs + * @return None + * + * \parDescription:
+ * Set a GPDMA event handler to service GPDMA events
+ * + * \par + * The function is used to register user callback functions for servicing DMA events. + * Call this function after enabling the GPDMA events (See ::XMC_DMA_CH_EnableEvent()) + */ +void XMC_DMA_CH_SetEventHandler(XMC_DMA_t *const dma, const uint8_t channel, XMC_DMA_CH_EVENT_HANDLER_t event_handler); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The source peripheral request for which DMA channel is to be cleared? + * @return None + * + * \parDescription:
+ * Clear source peripheral request
+ * + * \par + * The function is used to clear the source peripheral request for a given DMA + * channel. + */ +void XMC_DMA_CH_ClearSourcePeripheralRequest(XMC_DMA_t *const dma, uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The destination peripheral request for which DMA channel is to be cleared? + * @return None + * + * \parDescription:
+ * Clear destination peripheral request
+ * + * \par + * The function is used to clear the destination peripheral request for a given DMA + * channel. + */ +void XMC_DMA_CH_ClearDestinationPeripheralRequest(XMC_DMA_t *const dma, uint8_t channel); + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @return None + * + * \parDescription:
+ * Default GPDMA IRQ handler
+ * + * \par + * The function implements a default GPDMA IRQ handler. It can be used within the + * following (device specific) routines:
+ * 1) GPDMA0_0_IRQHandler
+ * 2) GPDMA1_0_IRQHandler
+ * + * The function handles the enabled GPDMA events and runs the user callback function + * registered by the user to service the event. To register a callback function, + * see ::XMC_DMA_CH_SetEventHandler() + */ +void XMC_DMA_IRQHandler(XMC_DMA_t *const dma); + +#ifdef __cplusplus +} +#endif + +/** + * @} (end addtogroup DMA) + */ + +/** + * @} (end addtogroup XMClib) + */ + +#endif /* defined (GPDMA0) */ +#endif /* XMC_DMA_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dma_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dma_map.h new file mode 100644 index 00000000..e31476b7 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dma_map.h @@ -0,0 +1,345 @@ + +/** + * @file xmc_dma_map.h + * @date 2015-05-07 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial version + * + * 2015-05-07: + * - Change line numbering for DMA1
+ * + * @endcond + */ + +#ifndef XMC_DMA_MAP_H +#define XMC_DMA_MAP_H + +#define DMA_PERIPHERAL_REQUEST(line, sel) (uint8_t)(line | (sel << 4U)) + +/* + * DMA LINE 0 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR0_0 DMA_PERIPHERAL_REQUEST(0, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR3_0 DMA_PERIPHERAL_REQUEST(0, 2) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR0_0 DMA_PERIPHERAL_REQUEST(0, 3) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR3_0 DMA_PERIPHERAL_REQUEST(0, 4) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM0_0 DMA_PERIPHERAL_REQUEST(0, 5) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CCU40_SR0_0 DMA_PERIPHERAL_REQUEST(0, 6) +#define DMA0_PERIPHERAL_REQUEST_CCU80_SR0_0 DMA_PERIPHERAL_REQUEST(0, 7) +#define DMA0_PERIPHERAL_REQUEST_CAN_SR0_0 DMA_PERIPHERAL_REQUEST(0, 9) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_0 DMA_PERIPHERAL_REQUEST(0, 11) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR3_0 DMA_PERIPHERAL_REQUEST(0, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU42_SR0_0 DMA_PERIPHERAL_REQUEST(0, 14) +#endif + +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) +#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 15) +#endif + +/* + * DMA LINE 1 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR3_1 DMA_PERIPHERAL_REQUEST(1, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR1_1 DMA_PERIPHERAL_REQUEST(1, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_1 DMA_PERIPHERAL_REQUEST(1, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR0_1 DMA_PERIPHERAL_REQUEST(1, 3) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR2_1 DMA_PERIPHERAL_REQUEST(1, 4) +#endif + +#define DMA0_PERIPHERAL_REQUEST_DAC_SR0_1 DMA_PERIPHERAL_REQUEST(1, 5) +#define DMA0_PERIPHERAL_REQUEST_CCU40_SR0_1 DMA_PERIPHERAL_REQUEST(1, 6) +#define DMA0_PERIPHERAL_REQUEST_CCU80_SR0_1 DMA_PERIPHERAL_REQUEST(1, 7) +#define DMA0_PERIPHERAL_REQUEST_CAN_SR0_1 DMA_PERIPHERAL_REQUEST(1, 9) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_1 DMA_PERIPHERAL_REQUEST(1, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_1 DMA_PERIPHERAL_REQUEST(1, 11) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR0_1 DMA_PERIPHERAL_REQUEST(1, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU42_SR0_1 DMA_PERIPHERAL_REQUEST(1, 14) +#endif + +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) +#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR1_1 DMA_PERIPHERAL_REQUEST(1, 15) +#endif + +/* + * DMA LINE 2 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR1_2 DMA_PERIPHERAL_REQUEST(2, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR2_2 DMA_PERIPHERAL_REQUEST(2, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR3_2 DMA_PERIPHERAL_REQUEST(2, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR3_2 DMA_PERIPHERAL_REQUEST(2, 3) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR1_2 DMA_PERIPHERAL_REQUEST(2, 4) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM1_2 DMA_PERIPHERAL_REQUEST(2, 5) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM3_2 DMA_PERIPHERAL_REQUEST(2, 6) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CCU40_SR1_2 DMA_PERIPHERAL_REQUEST(2, 7) +#define DMA0_PERIPHERAL_REQUEST_CCU80_SR1_2 DMA_PERIPHERAL_REQUEST(2, 8) +#define DMA0_PERIPHERAL_REQUEST_CAN_SR1_2 DMA_PERIPHERAL_REQUEST(2, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_2 DMA_PERIPHERAL_REQUEST(2, 11) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_2 DMA_PERIPHERAL_REQUEST(2, 12) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR2_2 DMA_PERIPHERAL_REQUEST(2, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU42_SR1_2 DMA_PERIPHERAL_REQUEST(2, 14) +#endif + +/* + * DMA LINE 3 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR2_3 DMA_PERIPHERAL_REQUEST(3, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR2_3 DMA_PERIPHERAL_REQUEST(3, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR3_3 DMA_PERIPHERAL_REQUEST(3, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR1_3 DMA_PERIPHERAL_REQUEST(3, 3) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR2_3 DMA_PERIPHERAL_REQUEST(3, 4) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM2_3 DMA_PERIPHERAL_REQUEST(3, 5) +#endif + +#define DMA0_PERIPHERAL_REQUEST_DAC_SR1_3 DMA_PERIPHERAL_REQUEST(3, 6) +#define DMA0_PERIPHERAL_REQUEST_CCU40_SR1_3 DMA_PERIPHERAL_REQUEST(3, 7) +#define DMA0_PERIPHERAL_REQUEST_CCU80_SR1_3 DMA_PERIPHERAL_REQUEST(3, 8) +#define DMA0_PERIPHERAL_REQUEST_CAN_SR1_3 DMA_PERIPHERAL_REQUEST(3, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_3 DMA_PERIPHERAL_REQUEST(3, 11) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_3 DMA_PERIPHERAL_REQUEST(3, 12) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR1_3 DMA_PERIPHERAL_REQUEST(3, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU42_SR1_3 DMA_PERIPHERAL_REQUEST(3, 14) +#endif + +/* + * DMA LINE 4 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR2_4 DMA_PERIPHERAL_REQUEST(4, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR0_4 DMA_PERIPHERAL_REQUEST(4, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR1_4 DMA_PERIPHERAL_REQUEST(4, 2) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR1_4 DMA_PERIPHERAL_REQUEST(4, 3) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR2_4 DMA_PERIPHERAL_REQUEST(4, 4) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM2_4 DMA_PERIPHERAL_REQUEST(4, 5) +#endif + +#define DMA0_PERIPHERAL_REQUEST_DAC_SR1_4 DMA_PERIPHERAL_REQUEST(4, 6) +#define DMA0_PERIPHERAL_REQUEST_CCU41_SR0_4 DMA_PERIPHERAL_REQUEST(4, 7) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_CCU81_SR0_4 DMA_PERIPHERAL_REQUEST(4, 8) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CAN_SR2_4 DMA_PERIPHERAL_REQUEST(4, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_4 DMA_PERIPHERAL_REQUEST(4, 11) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_4 DMA_PERIPHERAL_REQUEST(4, 12) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR1_4 DMA_PERIPHERAL_REQUEST(4, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU43_SR0_4 DMA_PERIPHERAL_REQUEST(4, 14) +#endif + +/* + * DMA LINE 5 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR1_5 DMA_PERIPHERAL_REQUEST(5, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR0_5 DMA_PERIPHERAL_REQUEST(5, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR1_5 DMA_PERIPHERAL_REQUEST(5, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR2_5 DMA_PERIPHERAL_REQUEST(5, 3) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR0_5 DMA_PERIPHERAL_REQUEST(5, 4) +#endif + +#define DMA0_PERIPHERAL_REQUEST_DAC_SR0_5 DMA_PERIPHERAL_REQUEST(5, 5) +#define DMA0_PERIPHERAL_REQUEST_CCU41_SR0_5 DMA_PERIPHERAL_REQUEST(5, 6) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_CCU81_SR0_5 DMA_PERIPHERAL_REQUEST(5, 7) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CAN_SR2_5 DMA_PERIPHERAL_REQUEST(5, 9) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_5 DMA_PERIPHERAL_REQUEST(5, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_5 DMA_PERIPHERAL_REQUEST(5, 11) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR2_5 DMA_PERIPHERAL_REQUEST(5, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU43_SR0_5 DMA_PERIPHERAL_REQUEST(5, 14) +#endif + +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) +#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR0_5 DMA_PERIPHERAL_REQUEST(5, 15) +#endif + +/* + * DMA LINE 6 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR3_6 DMA_PERIPHERAL_REQUEST(6, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR1_6 DMA_PERIPHERAL_REQUEST(6, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_6 DMA_PERIPHERAL_REQUEST(6, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR1_6 DMA_PERIPHERAL_REQUEST(6, 3) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR3_6 DMA_PERIPHERAL_REQUEST(6, 4) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM1_6 DMA_PERIPHERAL_REQUEST(6, 5) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM3_6 DMA_PERIPHERAL_REQUEST(6, 6) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CCU41_SR1_6 DMA_PERIPHERAL_REQUEST(6, 7) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_CCU81_SR1_6 DMA_PERIPHERAL_REQUEST(6, 8) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CAN_SR3_6 DMA_PERIPHERAL_REQUEST(6, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_6 DMA_PERIPHERAL_REQUEST(6, 11) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_6 DMA_PERIPHERAL_REQUEST(6, 12) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR0_6 DMA_PERIPHERAL_REQUEST(6, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU43_SR1_6 DMA_PERIPHERAL_REQUEST(6, 14) +#endif + +/* + * DMA LINE 7 of DMA0 + */ + +#define DMA0_PERIPHERAL_REQUEST_ERU0_SR0_7 DMA_PERIPHERAL_REQUEST(7, 0) +#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR0_7 DMA_PERIPHERAL_REQUEST(7, 1) +#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR3_7 DMA_PERIPHERAL_REQUEST(7, 2) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR0_7 DMA_PERIPHERAL_REQUEST(7, 3) +#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR3_7 DMA_PERIPHERAL_REQUEST(7, 4) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_DSD_SRM0_7 DMA_PERIPHERAL_REQUEST(7, 5) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CCU41_SR1_7 DMA_PERIPHERAL_REQUEST(7, 6) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_CCU81_SR1_7 DMA_PERIPHERAL_REQUEST(7, 7) +#endif + +#define DMA0_PERIPHERAL_REQUEST_CAN_SR3_7 DMA_PERIPHERAL_REQUEST(7, 9) +#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_7 DMA_PERIPHERAL_REQUEST(7, 10) +#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_7 DMA_PERIPHERAL_REQUEST(7, 11) + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) +#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR3_7 DMA_PERIPHERAL_REQUEST(7, 13) +#define DMA0_PERIPHERAL_REQUEST_CCU43_SR1_7 DMA_PERIPHERAL_REQUEST(7, 14) +#endif + +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) +#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR1_7 DMA_PERIPHERAL_REQUEST(7, 15) +#endif + +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || UC_SERIES == XMC45) +/* + * DMA LINE 0 of DMA1 + */ + +#define DMA1_PERIPHERAL_REQUEST_ERU0_SR0_8 DMA_PERIPHERAL_REQUEST(0, 0) +#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR0_8 DMA_PERIPHERAL_REQUEST(0, 1) +#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR0_8 DMA_PERIPHERAL_REQUEST(0, 2) +#define DMA1_PERIPHERAL_REQUEST_DSD_SRM0_8 DMA_PERIPHERAL_REQUEST(0, 3) +#define DMA1_PERIPHERAL_REQUEST_DAC_SR0_8 DMA_PERIPHERAL_REQUEST(0, 4) +#define DMA1_PERIPHERAL_REQUEST_CCU42_SR0_8 DMA_PERIPHERAL_REQUEST(0, 5) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR0_8 DMA_PERIPHERAL_REQUEST(0, 6) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR2_8 DMA_PERIPHERAL_REQUEST(0, 7) + +/* + * DMA LINE 1 of DMA1 + */ + +#define DMA1_PERIPHERAL_REQUEST_ERU0_SR1_9 DMA_PERIPHERAL_REQUEST(1, 0) +#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR1_9 DMA_PERIPHERAL_REQUEST(1, 1) +#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR1_9 DMA_PERIPHERAL_REQUEST(1, 2) +#define DMA1_PERIPHERAL_REQUEST_DSD_SRM1_9 DMA_PERIPHERAL_REQUEST(1, 3) +#define DMA1_PERIPHERAL_REQUEST_DAC_SR1_9 DMA_PERIPHERAL_REQUEST(1, 4) +#define DMA1_PERIPHERAL_REQUEST_CCU42_SR1_9 DMA_PERIPHERAL_REQUEST(1, 5) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR1_9 DMA_PERIPHERAL_REQUEST(1, 6) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR3_9 DMA_PERIPHERAL_REQUEST(1, 7) + +/* + * DMA LINE 2 of DMA1 + */ + +#define DMA1_PERIPHERAL_REQUEST_ERU0_SR2_10 DMA_PERIPHERAL_REQUEST(2, 0) +#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR2_10 DMA_PERIPHERAL_REQUEST(2, 1) +#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR2_10 DMA_PERIPHERAL_REQUEST(2, 2) +#define DMA1_PERIPHERAL_REQUEST_DSD_SRM2_10 DMA_PERIPHERAL_REQUEST(2, 3) +#define DMA1_PERIPHERAL_REQUEST_DAC_SR0_10 DMA_PERIPHERAL_REQUEST(2, 4) +#define DMA1_PERIPHERAL_REQUEST_CCU43_SR0_10 DMA_PERIPHERAL_REQUEST(2, 5) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR0_10 DMA_PERIPHERAL_REQUEST(2, 6) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR2_10 DMA_PERIPHERAL_REQUEST(2, 7) + +/* + * DMA LINE 3 of DMA1 + */ + +#define DMA1_PERIPHERAL_REQUEST_ERU0_SR3_11 DMA_PERIPHERAL_REQUEST(3, 0) +#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR3_11 DMA_PERIPHERAL_REQUEST(3, 1) +#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR3_11 DMA_PERIPHERAL_REQUEST(3, 2) +#define DMA1_PERIPHERAL_REQUEST_DSD_SRM3_11 DMA_PERIPHERAL_REQUEST(3, 3) +#define DMA1_PERIPHERAL_REQUEST_DAC_SR1_11 DMA_PERIPHERAL_REQUEST(3, 4) +#define DMA1_PERIPHERAL_REQUEST_CCU43_SR1_11 DMA_PERIPHERAL_REQUEST(3, 5) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR1_11 DMA_PERIPHERAL_REQUEST(3, 6) +#define DMA1_PERIPHERAL_REQUEST_USIC2_SR3_11 DMA_PERIPHERAL_REQUEST(3, 7) + +#endif /* (UC_SERIES == XMC45) */ + +#endif /* XMC_DMA_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dsd.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dsd.h new file mode 100644 index 00000000..53a90794 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_dsd.h @@ -0,0 +1,1185 @@ +/** + * @file xmc_dsd.h + * @date 2015-09-18 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-03-30: + * - Initial version + * + * 2015-06-19: + * - Removed version macros and declaration of GetDriverVersion API
+ * - Added API XMC_DSD_CH_GetRectifyDelay
+ * + * 2015-07-16: + * - Renamed API “XMC_DSD_CH_AuxFilter_SetBoudary()†to “XMC_DSD_CH_AuxFilter_SetBoundary()â€
+ * + * 2015-09-18: + * - Added APIs "XMC_DSD_SetResultEventFlag()","XMC_DSD_ClearResultEventFlag()" + * "XMC_DSD_SetAlarmEventFlag()" and "XMC_DSD_ClearAlarmEventFlag()"
+ * - Support added for XMC4800 microcontroller family
+ * @endcond + * + */ + + +#ifndef XMC_DSD_H +#define XMC_DSD_H + + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ +#include + +#if defined(DSD) +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup DSD +* @{ +* @brief Delta Sigma Demodulator (DSD) driver for the XMC4500, XMC4400 and XMC4800 microcontroller family
+ * + * The DSD unit provides a series of digital input channels accepting data streams from external modulators + * using the Delta/Sigma (DS) conversion principle. The on-chip demodulator channels convert these inputs to + * discrete digital values. + * DSD unit can be used for isolated current/voltage measurement and for sensor interfaces.
+ * + * Driver is divided in six DSD functional blocks - + * - Main Filter (APIs prefixed with XMC_DSD_CH_MainFilter), + * - Aux Filter (APIs prefixed with XMC_DSD_CH_AuxFilter), + * - Integrator (APIs prefixed with XMC_DSD_CH_Integrator), + * - Timestamp (APIs prefixed with XMC_DSD_CH_Timestamp), + * - Rectification (APIs prefixed with XMC_DSD_CH_Rectify), + * - Carrier Generator (APIs prefixed with XMC_DSD_Generator) + * + * DSD driver features: + * -# DSD channel Configuration structure XMC_DSD_CH_CONFIG_t initialization function XMC_DSD_CH_Init() to configure all the functional blocks (except carrier generator) + * -# Configuration structure XMC_DSD_GENERATOR_CONFIG_t and initialization function XMC_DSD_Generator_Init() to configure carrier generator + * -# Configuration structure XMC_DSD_CH_FILTER_CONFIG_t and initialization function XMC_DSD_CH_MainFilter_Init() to configure main filter + * -# Configuration structure XMC_DSD_CH_AUX_FILTER_CONFIG_t and initialization function XMC_DSD_CH_AuxFilter_Init() to configure auxilary filter + * -# Configuration structure XMC_DSD_CH_INTEGRATOR_CONFIG_t and initialization function XMC_DSD_CH_Integrator_Init() to configure integrator + * -# Configuration structure XMC_DSD_CH_TIMESTAMP_CONFIG_t and initialization function XMC_DSD_CH_Timestamp_Init() to configure timestamp + * -# Configuration structure XMC_DSD_CH_RECTIFY_CONFIG_t and initialization function XMC_DSD_CH_Rectify_Init() to configure rectifier + */ + + /********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + #define XMC_DSD_CHECK_MODULE_PTR(PTR) ( ((PTR)== DSD)) + #define XMC_DSD_CHECK_CHANNEL_PTR(PTR) ( ((PTR) == DSD_CH0) || ((PTR) == DSD_CH1) || ((PTR) == DSD_CH2) || ((PTR) == DSD_CH3)) + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ +/** + * DSD Channel + */ +typedef DSD_CH_TypeDef XMC_DSD_CH_t; + +/** + * DSD Module + */ +typedef DSD_GLOBAL_TypeDef XMC_DSD_t; + + +/** + * Return types of the API's.Use type @ref XMC_DSD_STATUS_t for this enum. + */ +typedef enum XMC_DSD_STATUS +{ + + XMC_DSD_STATUS_OK, /**< API fulfills request */ + XMC_DSD_STATUS_ERROR /**< Error detected */ + +} XMC_DSD_STATUS_t; + +/** + * Enumerates the divider factor for the PWM pattern signal generator. + * Use divider factor to derive input frequency of the carrier signal generator(fCG), + * from the selected internal clock source(fCLK). + * Use type @ref XMC_DSD_GENERATOR_CLKDIV_t for this enum. + */ +typedef enum XMC_DSD_GENERATOR_CLKDIV +{ + XMC_DSD_GENERATOR_CLKDIV_2048 = 0x00U, /**< fCG = (fCLK/2)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_4096 = 0x01U, /**< fCG = (fCLK/4)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_6144 = 0x02U, /**< fCG = (fCLK/6)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_8192 = 0x03U, /**< fCG = (fCLK/8)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_10240 = 0x04U, /**< fCG = (fCLK/10)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_12288 = 0x05U, /**< fCG = (fCLK/12)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_14336 = 0x06U, /**< fCG = (fCLK/14)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_16384 = 0x07U, /**< fCG = (fCLK/16)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_18432 = 0x08U, /**< fCG = (fCLK/18)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_20480 = 0x09U, /**< fCG = (fCLK/20)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_22528 = 0x0AU, /**< fCG = (fCLK/22)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_24576 = 0x0BU, /**< fCG = (fCLK/24)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_26624 = 0x0CU, /**< fCG = (fCLK/26)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_28672 = 0x0DU, /**< fCG = (fCLK/28)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_30720 = 0x0EU, /**< fCG = (fCLK/30)/1024 */ + XMC_DSD_GENERATOR_CLKDIV_32768 = 0x0FU /**< fCG = (fCLK/32)/1024 */ + +} XMC_DSD_GENERATOR_CLKDIV_t; + + +/** + * Enumerates the carrier generator operating mode. + * Use type @ref XMC_DSD_GENERATOR_MODE_t for this enum. + */ +typedef enum XMC_DSD_GENERATOR_MODE +{ + XMC_DSD_GENERATOR_MODE_STOPPED = 0x00U, /**< Stopped */ + XMC_DSD_GENERATOR_MODE_RECTANGLE = 0x01U, /**< Square wave */ + XMC_DSD_GENERATOR_MODE_TRIANGLE = 0x02U, /**< Triangle */ + XMC_DSD_GENERATOR_MODE_SINE = 0x03U /**< Sine wave*/ + +} XMC_DSD_GENERATOR_MODE_t; + + +/** + * Enumerates the CIC(cyclic integrating comb) filter type. + * Use type @ref XMC_DSD_CH_FILTER_TYPE_t for this enum. + */ +typedef enum XMC_DSD_CH_FILTER_TYPE +{ + + XMC_DSD_CH_FILTER_TYPE_CIC1, /**< CIC1 filter*/ + XMC_DSD_CH_FILTER_TYPE_CIC2, /**< CIC2 filter*/ + XMC_DSD_CH_FILTER_TYPE_CIC3, /**< CIC3 filter*/ + XMC_DSD_CH_FILTER_TYPE_CICF /**< CICF filter*/ + +} XMC_DSD_CH_FILTER_TYPE_t; + +/** + * Enumerates the input data source select. + * Use type @ref XMC_DSD_CH_DATA_SOURCE_t for this enum. + */ +typedef enum XMC_DSD_CH_DATA_SOURCE +{ + + XMC_DSD_CH_DATA_SOURCE_DISCONNECT = 0U, /**< Disconnected */ + XMC_DSD_CH_DATA_SOURCE_A_DIRECT = 2U, /**< External source, from input A, direct */ + XMC_DSD_CH_DATA_SOURCE_A_INVERTED = 3U, /**< External source, from input A, inverted */ + XMC_DSD_CH_DATA_SOURCE_B_DIRECT = 4U, /**< External source, from input B, direct */ + XMC_DSD_CH_DATA_SOURCE_B_INVERTED = 5U /**< External source, from input B, inverted */ + +} XMC_DSD_CH_DATA_SOURCE_t; + +/** + * Enumerates the sample clock source select. + * Use type @ref XMC_DSD_CH_CLOCK_SOURCE_t for this enum. + */ +typedef enum XMC_DSD_CH_CLOCK_SOURCE +{ + + XMC_DSD_CH_CLOCK_SOURCE_A = 1U, /**< External source, from input A */ + XMC_DSD_CH_CLOCK_SOURCE_B = 2U, /**< External source, from input B */ + XMC_DSD_CH_CLOCK_SOURCE_C = 3U, /**< External source, from input C */ + XMC_DSD_CH_CLOCK_SOURCE_D = 4U, /**< External source, from input D */ + XMC_DSD_CH_CLOCK_SOURCE_INTERN = 15U /**< Internal clock source */ + +} XMC_DSD_CH_CLOCK_SOURCE_t; + + +/** + * Enumerates the data strobe generation Mode. + * Use type @ref XMC_DSD_CH_STROBE_t for this enum. + */ +typedef enum XMC_DSD_CH_STROBE +{ + + XMC_DSD_CH_STROBE_DIRECT_CLOCK_RISE = 1U, /* Direct clock, a sample trigger is generated at each rising clock edge */ + XMC_DSD_CH_STROBE_DIRECT_CLOCK_FALL = 2U, /* Direct clock, a sample trigger is generated at each falling clock edge */ + XMC_DSD_CH_STROBE_DOUBLE_DATA = 3U, /* Double data, a sample trigger is generated at each rising and falling clock edge */ + XMC_DSD_CH_STROBE_DOUBLE_CLOCK_RISE = 5U, /* Double clock, a sample trigger is generated at every 2nd rising clock edge */ + XMC_DSD_CH_STROBE_DOUBLE_CLOCK_FALL = 6U /* Double clock, a sample trigger is generated at every 2nd falling clock edge */ + +} XMC_DSD_CH_STROBE_t; + + +/** + * Enumerates the divider factor for modulator clock (fMOD). + * Use divider factor to derive modulator clock frequency(fMOD), + * from the selected internal clock source(fCLK). + * Use type @ref XMC_DSD_CH_CLK_t for this enum. + */ +typedef enum XMC_DSD_CH_CLK_DIV +{ + + XMC_DSD_CH_CLK_DIV_2, /**< fMOD = fCLK/2 */ + XMC_DSD_CH_CLK_DIV_4, /**< fMOD = fCLK/4 */ + XMC_DSD_CH_CLK_DIV_6, /**< fMOD = fCLK/6 */ + XMC_DSD_CH_CLK_DIV_8, /**< fMOD = fCLK/8 */ + XMC_DSD_CH_CLK_DIV_10, /**< fMOD = fCLK/10 */ + XMC_DSD_CH_CLK_DIV_12, /**< fMOD = fCLK/12 */ + XMC_DSD_CH_CLK_DIV_14, /**< fMOD = fCLK/14 */ + XMC_DSD_CH_CLK_DIV_16, /**< fMOD = fCLK/16 */ + XMC_DSD_CH_CLK_DIV_18, /**< fMOD = fCLK/18 */ + XMC_DSD_CH_CLK_DIV_20, /**< fMOD = fCLK/20 */ + XMC_DSD_CH_CLK_DIV_22, /**< fMOD = fCLK/22 */ + XMC_DSD_CH_CLK_DIV_24, /**< fMOD = fCLK/24 */ + XMC_DSD_CH_CLK_DIV_26, /**< fMOD = fCLK/26 */ + XMC_DSD_CH_CLK_DIV_28, /**< fMOD = fCLK/28 */ + XMC_DSD_CH_CLK_DIV_30, /**< fMOD = fCLK/30 */ + XMC_DSD_CH_CLK_DIV_32 /**< fMOD = fCLK/32 */ + +} XMC_DSD_CH_CLK_t; + +/** + * Enumerates the integrator trigger mode. + * Use type @ref XMC_DSD_CH_INTEGRATOR_START_t for this enum. + */ +typedef enum XMC_DSD_CH_INTEGRATOR_START +{ + XMC_DSD_CH_INTEGRATOR_START_OFF, /**< No integration trigger */ + XMC_DSD_CH_INTEGRATOR_START_TRIGGER_FALL, /**< Trigger event upon a falling edge */ + XMC_DSD_CH_INTEGRATOR_START_TRIGGER_RISE, /**< Trigger event upon a rising edge */ + XMC_DSD_CH_INTEGRATOR_START_ALLWAYS_ON /**< No trigger, integrator active all the time */ + +} XMC_DSD_CH_INTEGRATOR_START_t; + +/** + * Enumerates the integration enable. + * Use type @ref XMC_DSD_CH_INTEGRATOR_STOP_t for this enum. + */ +typedef enum XMC_DSD_CH_INTEGRATOR_STOP +{ + XMC_DSD_CH_INTEGRATOR_STOP_END_OF_LOOPS, /**< Integration stopped upon the inverse trigger event */ + XMC_DSD_CH_INTEGRATOR_STOP_ENDLESS_OR_INVERSE_TRIGGER /**< Integration enabled upon the defined trigger event. */ + +} XMC_DSD_CH_INTEGRATOR_STOP_t; + + +/** + * Enumerates the trigger signal. + * Use type @ref XMC_DSD_CH_TRIGGER_SOURCE_t for this enum. + */ +typedef enum XMC_DSD_CH_TRIGGER_SOURCE +{ + + XMC_DSD_CH_TRIGGER_SOURCE_A = 0U, /**< Trigger signal,input A*/ + XMC_DSD_CH_TRIGGER_SOURCE_B = 1U, /**< Trigger signal,input B*/ + XMC_DSD_CH_TRIGGER_SOURCE_C = 2U, /**< Trigger signal,input C*/ + XMC_DSD_CH_TRIGGER_SOURCE_D = 3U, /**< Trigger signal,input D*/ + XMC_DSD_CH_TRIGGER_SOURCE_E = 4U, /**< Trigger signal,input E*/ + XMC_DSD_CH_TRIGGER_SOURCE_F = 5U, /**< Trigger signal,input F*/ + XMC_DSD_CH_TRIGGER_SOURCE_G = 6U, /**< Trigger signal,input G*/ + XMC_DSD_CH_TRIGGER_SOURCE_H = 7U /**< Trigger signal,input H*/ + +} XMC_DSD_CH_TRIGGER_SOURCE_t; + +/** + * Enumerates the timestamp trigger mode. + * Use type @ref XMC_DSD_CH_TIMESTAMP_TRIGGER_t for this enum. + */ +typedef enum XMC_DSD_CH_TIMESTAMP_TRIGGER +{ + XMC_DSD_CH_TIMESTAMP_TRIGGER_DISABLE, /**< No trigger event*/ + XMC_DSD_CH_TIMESTAMP_TRIGGER_FALL, /**< Trigger event upon a falling edge*/ + XMC_DSD_CH_TIMESTAMP_TRIGGER_RISE, /**< Trigger event upon a rising edge*/ + XMC_DSD_CH_TIMESTAMP_TRIGGER_BOTH_EDGES /**< Trigger event upon both the edge*/ + +} XMC_DSD_CH_TIMESTAMP_TRIGGER_t; + +/** + * Enumerates the carrier generation mode. + * Use type @ref XMC_DSD_CH_SIGN_SOURCE_t for this enum. + */ +typedef enum XMC_DSD_CH_SIGN_SOURCE +{ + XMC_DSD_CH_SIGN_SOURCE_ON_CHIP_GENERATOR, /**< Carrier is generated internally by DSD */ + XMC_DSD_CH_SIGN_SOURCE_NEXT_CHANNEL, /**< Carrier sign signal is generated internally by next channel*/ + XMC_DSD_CH_SIGN_SOURCE_EXTERNAL_A, /**< Carrier is generated externally, External sign signal A*/ + XMC_DSD_CH_SIGN_SOURCE_EXTERNAL_B /**< Carrier is generated externally, External sign signal B*/ + +} XMC_DSD_CH_SIGN_SOURCE_t; + +/** + * Enumerates the channel run control bit register value in global run control register. + * Use type @ref XMC_DSD_CH_ID_t for this enum. + */ +typedef enum XMC_DSD_CH_ID +{ + XMC_DSD_CH_ID_0 = 1U, /**< Register value for channel 0 */ + XMC_DSD_CH_ID_1 = 2U, /**< Register value for channel 1 */ + XMC_DSD_CH_ID_2 = 4U, /**< Register value for channel 2 */ + XMC_DSD_CH_ID_3 = 8U /**< Register value for channel 3 */ + +} XMC_DSD_CH_ID_t; + +/** + * Enumerates the service request generation mode for auxiliary filter. + * Use type @ref XMC_DSD_CH_AUX_EVENT_t for this enum. + * Note: This is combined ENUM for SRGA + ESEL bit fields + */ +typedef enum XMC_DSD_CH_AUX_EVENT +{ + XMC_DSD_CH_AUX_EVENT_DISABLED = 0U, /**< Service request is disabled */ + XMC_DSD_CH_AUX_EVENT_EVERY_NEW_RESULT = 1U, /**< Service request generated for aux filter for every new result */ + XMC_DSD_CH_AUX_EVENT_CAPTURE_SIGN_DELAY = 2U, /**< Service request generated for alternate source */ + XMC_DSD_CH_AUX_EVENT_INSIDE_BOUNDARY = 5U, /**< Service request generated for aux filter if result is inside boundary */ + XMC_DSD_CH_AUX_EVENT_OUTSIDE_BOUNDARY = 9U /**< Service request generated for aux filter if result is outside boundary */ + +} XMC_DSD_CH_AUX_EVENT_t; + +/** + * Enumerates the service request generation for main chain filter. + * Use type @ref XMC_DSD_CH_RESULT_EVENT_t for this enum. + */ +typedef enum XMC_DSD_CH_RESULT_EVENT +{ + XMC_DSD_CH_RESULT_EVENT_DISABLE = 0U, /**< Disable service request */ + XMC_DSD_CH_RESULT_EVENT_ENABLE = 3U /**< Enable service request for each new result value */ + +} XMC_DSD_CH_RESULT_EVENT_t; + + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * DSD generator generates several pattern and frequencies. + * Use type @ref XMC_DSD_GENERATOR_CONFIG_t for this data structure. + * Note: Output pins have to be enabled by user. + */ +typedef struct XMC_DSD_GENERATOR_CONFIG +{ + union + { + struct + { + uint32_t mode: 2; /**< carrier generator operating mode. This parameter can take a value of XMC_DSD_GENERATOR_MODE_t */ + uint32_t bit_reverse: 1; /**< should PWM signal be bit-reversed? 0: Normal mode, 1:Bit-reverse mode */ + uint32_t inverted_polarity: 1; /**< should PWM signal start from negative max. 0: Normal, 1: Inverted */ + uint32_t frequency: 4; /**< Frequency divider value of PWM signal. This parameter can take a value of XMC_DSD_GENERATOR_CLKDIV_t */ + uint32_t :24; + }; + uint32_t generator_conf; /**< Carrier generator configuration register(CGCFG)*/ + }; +} XMC_DSD_GENERATOR_CONFIG_t; + + +/** + * DSD filter is the basic module of the DSD. It can be used separately or can be combined with the other modules like + * integrator, rectify, auxiliary filter etc. + * The filter demodulates the incoming bit stream from the delta sigma modulator to a 16 bit result. + * Note: Configure or reconfigure filter parameters while the channel is inactive. + */ +typedef struct XMC_DSD_CH_FILTER_CONFIG +{ + uint32_t clock_divider: 4; /**< This parameter can take a value of XMC_DSD_CH_CLK_t */ + int16_t offset; /**< Offset subtracted from result.This parameter can take a value of int16_t */ + union + { + struct + { + uint32_t data_source: 4; /**< This parameter can take a value of XMC_DSD_CH_DATA_SOURCE_t */ + uint32_t : 12; + uint32_t clock_source: 4; /**< This parameter can take a value of XMC_DSD_CH_CLOCK_SOURCE_t */ + uint32_t strobe: 4; /**< This parameter can take a value of XMC_DSD_CH_STROBE_t */ + uint32_t :8; + }; + uint32_t demodulator_conf; /*Demodulator Input Configuration Register*/ + }; + union + { + struct + { + uint32_t : 8; + uint32_t filter_type: 2; /**< This parameter can take a value of XMC_DSD_CH_FILTER_TYPE_t */ + uint32_t : 4; + uint32_t result_event : 2; /**< This parameter can take a value of XMC_DSD_CH_RESULT_EVENT_t */ + uint32_t : 8; + uint32_t : 8; + }; + uint32_t main_filter_conf; + + }; + uint32_t decimation_factor; /**< This parameter can be in range of 4 - 256[dec] */ + uint32_t filter_start_value; /**< This parameter can be in range of 4 - decimation_factor[dec]*/ + +} XMC_DSD_CH_FILTER_CONFIG_t; + +/** + * The integrator is mainly used for high accurate measurement. + * Note:DSD Filter is mandatory to use this block. + */ +typedef struct XMC_DSD_CH_INTEGRATOR_CONFIG +{ + union + { + struct + { + uint32_t :8; + uint32_t start_condition: 2; /**< Can take a value of XMC_DSD_CH_INTEGRATOR_START_t.Bitfields \a ITRMODE of \a DICFG.*/ + uint32_t :2; + uint32_t trigger_source: 3; /**< Can take a value of XMC_DSD_CH_TRIGGER_SOURCE_t.Bitfields \a TRSEL of \a DICFG. */ + uint32_t :17; + }; + uint32_t integrator_trigger; /**< Demodulator Input Configuration Register(\a DICFG).*/ + + }; + uint32_t integration_loop; /**< Integration loops to see stop condition. Bitfields \a REPVAL of \a IWCTR.*/ + uint32_t discarded_values; /**< Number of mainfilter results,discarded before integration starts.Bitfields \a NVALDIS of \a IWCTR.*/ + uint32_t stop_condition; /**< Integrator stop condition. Can take a value of XMC_DSD_CH_INTEGRATOR_STOP_t.Bitfields \a IWS of \a IWCTR.*/ + uint32_t counted_values; /**< Number of mainfilter results, integrated to a integrator result.Bitfields \a NVALINT of \a IWCTR.*/ + +} XMC_DSD_CH_INTEGRATOR_CONFIG_t; + +/** + * DSD timestamp saves result, filter counter register and integrator count register. + * Note: Trigger source for timestamp and integrator trigger are shared. + * DSD Filter is mandatory to use this block. + */ +typedef struct XMC_DSD_CH_TIMESTAMP_CONFIG +{ + union + { + struct + { + uint32_t :10; + uint32_t trigger_mode:2; /**< This parameter can take a value of XMC_DSD_CH_TIMESTAMP_TRIGGER_t */ + uint32_t trigger_source: 3; /**< This parameter can take a value of XMC_DSD_CH_TRIGGER_SOURCE_t */ + uint32_t : 17; + }; + uint32_t timestamp_conf; + }; +} XMC_DSD_CH_TIMESTAMP_CONFIG_t; + +/** + * DSD auxiliary Filter is used as fast filter to detect overvoltage or current by defining the boundaries. + */ +typedef struct XMC_DSD_CH_AUX_FILTER_CONFIG +{ + union + { + struct + { + uint32_t : 8; /**< This parameter can be in range of 4 - 256[dec] */ + uint32_t filter_type : 2; /**< This parameter can take a value of XMC_DSD_CH_FILTER_TYPE_t */ + uint32_t result_event_type : 4; /**< Result event for aux filter and the event select configuration. + Use enum XMC_DSD_CH_AUX_EVENT_t */ + uint32_t enable_integrator_coupling : 1; /**< Only enable AUX filter when Integrator is enabled*/ + uint32_t : 17; + }; + uint32_t aux_filter_conf; + }; + union + { + struct + { + uint32_t lower_boundary : 16; /**< This parameter can take a value of int16_t */ + uint32_t upper_boundary : 16; /**< This parameter can take a value of int16_t */ + }; + uint32_t boundary_conf; + }; + + uint32_t decimation_factor; /**< This parameter can be in range of 4 - 256[dec]*/ + +} XMC_DSD_CH_AUX_FILTER_CONFIG_t; + + +/** + * DSD Rectify. + * Note: DSD Filter and integrator is mandatory to use this block. + */ +typedef struct XMC_DSD_CH_RECTIFY_CONFIG +{ + union + { + struct + { + uint32_t :4; + uint32_t sign_source: 2; /**< Can take a value of XMC_DSD_CH_SIGN_SOURCE_t.Bitfields \a SSRC of \a RECTCFG.*/ + uint32_t :26; + }; + uint32_t rectify_config; /**< Rectification configuration register(\a RECTCFG)*/ + }; + + uint8_t delay; + uint8_t half_cycle; + +} XMC_DSD_CH_RECTIFY_CONFIG_t; + + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +/** + * DSD Enable Channel + */ +typedef struct XMC_DSD_CONFIG +{ + XMC_DSD_CH_FILTER_CONFIG_t *const filter; /**< Pointer to the filter configuration */ + XMC_DSD_CH_INTEGRATOR_CONFIG_t *const integrator; /**< Pointer to the integrator configuration*/ + XMC_DSD_CH_TIMESTAMP_CONFIG_t *const timestamp; /**< Pointer to the time stamp configuration*/ + XMC_DSD_CH_AUX_FILTER_CONFIG_t *const aux; /**< Pointer to the aux_filter configuration*/ + XMC_DSD_CH_RECTIFY_CONFIG_t *const rectify; /**< Pointer to the rectify configuration*/ +} XMC_DSD_CH_CONFIG_t; + + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * De-asserts the DSD module from reset.\n + * Configures \a PRCLR0 register's \a DSDRS bit field. + * If running on XMC44/XMC48 device then it will ungate the peripheral clock. + * + * \parNote
+ * It is internally called by XMC_DSD_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_Disable(),XMC_DSD_Init() \n\n\n + */ +void XMC_DSD_Enable(XMC_DSD_t *const dsd); + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * Asserts the DSD module into reset.\n + * Configures \a PRSET0 register's \a DSDRS bit field. + * If running on XMC44/XMC48 device then it will gate the peripheral clock. + * + * \parRelated APIs:
+ * XMC_DSD_Enable()\n\n\n + */ +void XMC_DSD_Disable(XMC_DSD_t *const dsd); +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * Enable the module clock and internal module clock for DSD.\n + * Configures bit field \a MCSEL of register \a GLOBCFG and bit field \a DISR of register \a CLC. + * + * \parNote
+ * It is internally called by XMC_DSD_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_DisableClock(),XMC_DSD_Init() \n\n\n + */ +void XMC_DSD_EnableClock(XMC_DSD_t *const dsd); +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * Stop the module clock and disable internal module clock for DSD.\n + * Configures bit field \a MCSEL of register \a GLOBCFG and bit field \a DISR of register \a CLC. + * + * \parRelated APIs:
+ * XMC_DSD_DisableClock()\n\n\n + */ +void XMC_DSD_DisableClock(XMC_DSD_t *const dsd); +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return bool Return 1 if success else 0. + * + * \parDescription
+ * Find out if the DSD reset is asserted.\n + * Read \a PRSTAT0 register's \a DSDRS bit field.\n\n\n + */ +bool XMC_DSD_IsEnabled(XMC_DSD_t *const dsd); + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * Enable the DSD module and clock.\n + * + * \parNote
+ * This is the first API which application must invoke to configure DSD. + * + * \parRelated APIs:
+ * XMC_DSD_Enable(),XMC_DSD_EnableClock()\n\n\n + */ +void XMC_DSD_Init(XMC_DSD_t *const dsd); +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_TIMESTAMP_CONFIG_t + * @return None + * + * \parDescription
+ * Initialize timestamp mode of DSD module with \a init.\n + * Configures bits \a TRSEL and \a TSTRMODE of register \a DICFG . + * + * \parNote
+ * Trigger source for timestamp and integrator are shared. + * It is internally called by XMC_DSD_CH_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_CH_Init()\n\n\n +*/ +void XMC_DSD_CH_Timestamp_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_TIMESTAMP_CONFIG_t *const init); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_CONFIG_t + * @return XMC_DSD_STATUS_t if success Returns @ref XMC_DSD_STATUS_OK + * else return @ref XMC_DSD_STATUS_ERROR. + * + * \parDescription
+ * Initialize main filter,auxiliary filter,integrator, rectifier and timestamp of DSD module with \a init.\n + * Internally this API invoke main filter, auxiliary filter, integrator, rectifier and timestamp init API. + * + * \parRelated APIs:
+ * XMC_DSD_CH_MainFilter_Init(),XMC_DSD_CH_AuxFilter_Init(),XMC_DSD_CH_Integrator_Init(), + * XMC_DSD_CH_Rectify_Init(),XMC_DSD_CH_Timestamp_Init()\n\n\n +*/ +XMC_DSD_STATUS_t XMC_DSD_CH_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_CONFIG_t *const init); + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param channel Channel run control bit register value + * @return None + * + * \parDescription
+ * Start demodulator channel by enabling run control bit. + * Multiple channel can be start at a time. + * For an example: To start all four channel, call this function as + * XMC_DSD_Start(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1|XMC_DSD_CH_ID_2|XMC_DSD_CH_ID_3)); + * + * \parNote
+ * All filter blocks are cleared when CHxRUN is set. + * + * \parRelated APIs:
+ * XMC_DSD_Stop(),XMC_DSD_IsChannelStarted()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_Start(XMC_DSD_t *const dsd, const uint32_t channel) +{ + XMC_ASSERT("XMC_DSD_Start:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->GLOBRC |= channel; +} + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t\n + * @param channel Channel run control bit register value\n + * @return None\n + * + * \parDescription
+ * Stop demodulator channel by resetting run control bit. + * Multiple channel can be stop at a time. + * For an example: To stop all four channel, call this function as + * XMC_DSD_Stop(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1|XMC_DSD_CH_ID_2|XMC_DSD_CH_ID_3)); + * + * + * \parRelated APIs:
+ * XMC_DSD_Start(),XMC_DSD_IsChannelStarted()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_Stop(XMC_DSD_t *const dsd, const uint32_t channel) +{ + XMC_ASSERT("XMC_DSD_Stop:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->GLOBRC &= (uint32_t) ~channel; +} + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t\n + * @param channel Channel run control bit register value of type @ref XMC_DSD_CH_ID_t\n + * @return bool Return 1 if started else 0.\n + * + * \parDescription
+ * Find out if particular demodulator channel is started or not.\n + * + * \parRelated APIs:
+ * XMC_DSD_Start(),XMC_DSD_Stop()\n\n\n + */ +__STATIC_INLINE bool XMC_DSD_IsChannelStarted(XMC_DSD_t *const dsd, const XMC_DSD_CH_ID_t channel) +{ + bool status; + XMC_ASSERT("XMC_DSD_IsChannelStarted:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + if (dsd->GLOBRC & (uint32_t)channel) + { + status = true; + } + else + { + status = false; + } + return (status); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param dsd_Result pointer point to the address of 16 bit variable + * @return None + * + * \parDescription:
+ * Returns the result of most recent conversion associated with this channel.\n + * A call to this API would access the register bit field \a RESMx.RESULT (x = 0 - 3). + * + * \parRelated APIs:
+ * XMC_DSD_CH_GetResult_TS()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_CH_GetResult(XMC_DSD_CH_t *const channel, int16_t* dsd_Result) +{ + uint16_t result; + result = (uint16_t)((uint32_t)channel->RESM & DSD_CH_RESM_RESULT_Msk); + *dsd_Result = (int16_t)result; +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t\n + * @param dsd_Result pointer point to the address of 16 bit variable holds result value\n + * @param dsd_filter_loop pointer point to the address of 8 bit variable holds decimation counter value\n + * @param dsd_integration_loop pointer point to the address of 8 bit integration counter variable holds value\n + * @return None\n + * + * \parDescription:
+ * API to get the result of the last conversion associated with this channel with + * CIC filter decimation counter and number of values counted.\n + * A call to this API would access the register bit field \a TSTMPx.RESULT \a TSTMPx.CFMDCNT and \a TSTMPx.NVALCNT where (x = 0 - 3). + * + * \parRelated APIs:
+ * XMC_DSD_CH_GetResult(),XMC_DSD_CH_GetResult_TS_Time()\n\n\n + */ +void XMC_DSD_CH_GetResult_TS( + XMC_DSD_CH_t *const channel, + int16_t* dsd_Result, + uint8_t* dsd_filter_loop, + uint8_t* dsd_integration_loop); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t\n + * @param dsd_Result pointer point to the address of 16 bit variable holds result value\n + * @param time pointer point to the address of 32 bit variable holds the time\n + * @return None + * + * \parDescription:
+ * API to get the result of the last conversion with the time, associated with this channel.\n + * + * \parRelated APIs:
+ * XMC_DSD_CH_GetResult(),XMC_DSD_CH_GetResult_TS()\n\n\n + */ +void XMC_DSD_CH_GetResult_TS_Time(XMC_DSD_CH_t *const channel, int16_t* dsd_Result, uint32_t* time); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param dsd_Result pointer point to the address of 16 bit variable + * @return None + * + * \parDescription:
+ * Returns the most recent conversion result values of the auxiliary filter associated with this channel.\n + * A call to this API would access the register bit field \a RESAx.RESULT (x = 0 - 3). + * + * \parRelated APIs:
+ * XMC_DSD_CH_GetResult_TS()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_CH_GetResult_AUX(XMC_DSD_CH_t *const channel, int16_t* dsd_Result) +{ + uint16_t result; + result = (uint16_t) (channel->RESA & DSD_CH_RESA_RESULT_Msk); + *dsd_Result = (int16_t) (result); +} + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_GENERATOR_CONFIG_t + * @return None + * + * \parDescription
+ * This API initialize generator module with \a init, to generate a wave for a resolver. + * Three types of waveforms can be generated: Rectangle, Triangle and Sine. + * +*/ +void XMC_DSD_Generator_Init(XMC_DSD_t *const dsd, const XMC_DSD_GENERATOR_CONFIG_t *const init); + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param config Pointer to an instance of data structure of type @ref XMC_DSD_GENERATOR_CONFIG_t + * @return None + * + * \parDescription
+ * Start carrier generator by configuring operating mode. + * Configures bit field \a CGMOD of register \a CGCFG. + * + * + * \parRelated APIs:
+ * XMC_DSD_Generator_Stop()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_Generator_Start(XMC_DSD_t *const dsd, const XMC_DSD_GENERATOR_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_DSD_Generator_Start:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_ASSERT("XMC_DSD_Generator_Start:NULL Pointer", (config != (XMC_DSD_GENERATOR_CONFIG_t *)NULL) ); + dsd->CGCFG |= config->mode; +} + +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @return None + * + * \parDescription
+ * Stop carrier generator by configuring operating mode. + * Reset bit field \a CGMOD of register \a CGCFG. + * + * \parNote
+ * Stopping the carrier generator terminates the PWM output after completion of the current period. + * + * \parRelated APIs:
+ * XMC_DSD_Generator_Start()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_Generator_Stop(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_Generator_Stop:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->CGCFG &= ~((uint32_t)DSD_CGCFG_CGMOD_Msk); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_FILTER_CONFIG_t + * @return None + * + * \parDescription
+ * This API initialize main filter module with \a init. + * The filter demodulates the incoming bit stream from the delta sigma modulator to a 16 bit result. + * + * + * \parNote
+ * It is internally called by XMC_DSD_CH_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_CH_Init()\n\n\n +*/ +void XMC_DSD_CH_MainFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_FILTER_CONFIG_t *const init); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param offset Signed Offset value to be set + * @return None + * + * \parDescription
+ * API set the signed offset value for this channel. + * This offset value is subtracted from each result before being written to the corresponding result register \a RESMx. + * + * \parNote
+ * The offset value is measured for each channel separately. + * +*/ +__STATIC_INLINE void XMC_DSD_CH_MainFilter_SetOffset(XMC_DSD_CH_t *const channel, const int16_t offset) +{ + XMC_ASSERT("XMC_DSD_CH_MainFilter_SetOffset:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->OFFM = (uint32_t)offset; +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @return None + * + * \parDescription
+ * This API enable the service request generation for result of this channel. + * Result events are generated at the output rate of the configured main filter chain. + * Configure bit field \a SRGM of register \a FCFGC + * +*/ +__STATIC_INLINE void XMC_DSD_CH_MainFilter_EnableEvent(XMC_DSD_CH_t *const channel) +{ + XMC_ASSERT("XMC_DSD_CH_MainFilter_EnableEvent:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->FCFGC |= (uint32_t)DSD_CH_FCFGC_SRGM_Msk; +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @return None + * + * \parDescription
+ * This API disable the service request generation for result of this channel. + * Configure bit field \a SRGM of register \a FCFGC + * +*/ +__STATIC_INLINE void XMC_DSD_CH_MainFilter_DisableEvent(XMC_DSD_CH_t *const channel) +{ + XMC_ASSERT("XMC_DSD_CH_MainFilter_DisableEvent:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->FCFGC &= ~((uint32_t)DSD_CH_FCFGC_SRGM_Msk); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_AUX_FILTER_CONFIG_t + * @return None + * + * \parDescription
+ * This API initialize auxiliary filter module with \a init. The auxiliary Filter is mainly used as fast filter.\n + * Adding the auxiliary filter to the system structure helps by defining the boundaries and filter configurations.\n + * + * + * \parNote
+ * It is internally called by XMC_DSD_CH_Init().\n + * + * \parRelated APIs:
+ * XMC_DSD_CH_Init()\n\n\n +*/ +void XMC_DSD_CH_AuxFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_AUX_FILTER_CONFIG_t *const init); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param lower_boundary lower boundary value for limit checking + * @param upper_boundary upper boundary value for limit checking + * @return None + * + * \parDescription
+ * Invoke this API, to set the lower and upper boundary for limit checking for this channel. + * This (two’s complement) value is compared to the results of the parallel filter. + * Configure bit fields \a BOUNDARYU and \a BOUNDARYL of register \a BOUNDSEL. + * + * \parNote
+ * Lower and upper boundaries are internally configured by function XMC_DSD_CH_AuxFilter_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_CH_AuxFilter_Init()\n\n\n +*/ +__STATIC_INLINE void XMC_DSD_CH_AuxFilter_SetBoundary( + XMC_DSD_CH_t *const channel, + const int16_t lower_boundary, + const int16_t upper_boundary) +{ + XMC_ASSERT("XMC_DSD_CH_AuxFilter_SetBoundary:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->BOUNDSEL = (((uint32_t)upper_boundary << (uint32_t)DSD_CH_BOUNDSEL_BOUNDARYU_Pos) + | ((uint32_t)lower_boundary & (uint32_t)DSD_CH_BOUNDSEL_BOUNDARYL_Msk)); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param event to select the type of event which will be enabled of type @ref XMC_DSD_CH_AUX_EVENT_t + * @return None + * + * \parDescription
+ * This API enable the service request generation for this channel. + * Result events are generated at the output rate of the configured auxiliary filter chain. + * Configure bit field \a SRGA and ESEL of register \a FCFGA + * +*/ +__STATIC_INLINE void XMC_DSD_CH_AuxFilter_EnableEvent(XMC_DSD_CH_t *const channel, XMC_DSD_CH_AUX_EVENT_t event) +{ + XMC_ASSERT("XMC_DSD_CH_AuxFilter_EnableEvent:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->FCFGA &= ~((uint32_t)DSD_CH_FCFGA_ESEL_Msk|(uint32_t)DSD_CH_FCFGA_SRGA_Msk); + channel->FCFGA |= ((uint32_t)event << DSD_CH_FCFGA_SRGA_Pos); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @return None + * + * \parDescription
+ * This API disable the auxiliary filter service request generation for this channel. + * Clear the bit fields \a SRGA and ESEL of register \a FCFGA. + * +*/ +__STATIC_INLINE void XMC_DSD_CH_AuxFilter_DisableEvent(XMC_DSD_CH_t *const channel) +{ + XMC_ASSERT("XMC_DSD_CH_AuxFilter_DisableEvent:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + channel->FCFGA &= ~((uint32_t)DSD_CH_FCFGA_ESEL_Msk|(uint32_t)DSD_CH_FCFGA_SRGA_Msk); +} + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_INTEGRATOR_CONFIG_t + * @return None + * + * \parDescription
+ * Initialize integrator of DSD module.The integrator is mainly used for resolver feedback but can also be used for high accurate measurement. + * This API configures number of integration loops, number of results are discarded before integration starts, integrator stop condition, + * number of integrator loop to get integration result and trigger mode. + * + * \parNote
+ * Trigger source for timestamp and integrator are shared. + * It is internally called by XMC_DSD_CH_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_CH_Init()\n\n\n +*/ +void XMC_DSD_CH_Integrator_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_INTEGRATOR_CONFIG_t *const init); +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param init Pointer to an instance of data structure of type @ref XMC_DSD_CH_RECTIFY_CONFIG_t + * @return None + * + * \parDescription
+ * Initialize rectification for this channel. + * In a resolver feedback system, rectifier is used to rectify the result from the integrator. + * Configure bit field \a RFEN and \a SSRC of register \a RECTCFG. Also configure sign delay + * value for positive halfwave(\a SDPOS) and negative halfwave(\a SDNEG). + * \parNote
+ * For the operational capability of rectifier the filter and the integrator is mandatory. + * It is internally called by XMC_DSD_CH_Init(). + * + * \parRelated APIs:
+ * XMC_DSD_CH_Init()\n\n\n +*/ +void XMC_DSD_CH_Rectify_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_RECTIFY_CONFIG_t *const init); + +/** + * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t + * @param delay Captured value + * @return uint8_t + * + * \parDescription
+ * This API, capture sign delay value for DSD channel. + * Captured value indicates the values counted between the begin of the positive + * halfwave of the carrier signal and the first received positive value. + * Read bit field \a SDCAP of register \a CGSYNC + * +*/ +__STATIC_INLINE void XMC_DSD_CH_GetRectifyDelay(XMC_DSD_CH_t *const channel, uint8_t* delay) +{ + XMC_ASSERT("XMC_DSD_CH_GetRectifyDelay:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + *delay = (uint8_t)((channel->CGSYNC & DSD_CH_CGSYNC_SDCAP_Msk ) >> DSD_CH_CGSYNC_SDCAP_Pos); +} +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param channel_id Channel number register value of type @ref XMC_DSD_CH_ID_t + * @return None + * + * \parDescription
+ * Set the result event flag and trigger the corresponding event.\n + * Set bit fields \a RESEVx of register \a EVFLAG.Clearing these bits has no effect. + * + * \parNote
+ * API call for channel-0 : XMC_DSD_SetResultEventFlag(DSD,(uint32_t)XMC_DSD_CH_ID_0); + * API call for channel-0 and 1: XMC_DSD_SetResultEventFlag(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1)); + * + * \parRelated APIs:
+ * XMC_DSD_ClearResultEventFlag()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_SetResultEventFlag(XMC_DSD_t *const dsd, const uint32_t channel_id) +{ + XMC_ASSERT("XMC_DSD_SetResultEventFlag:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->EVFLAG = channel_id; +} +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param channel_id Channel number register value of type @ref XMC_DSD_CH_ID_t + * @return None + * + * \parDescription
+ * Clear the result event flag.\n + * Set bit fields \a RESECx of register \a EVFLAGCLR.Clearing these bits has no effect. + * + * \parNote
+ * API call for channel-0 : XMC_DSD_ClearResultEventFlag(DSD,(uint32_t)XMC_DSD_CH_ID_0); + * API call for channel-0 and 1: XMC_DSD_ClearResultEventFlag(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1)); + * + * \parRelated APIs:
+ * XMC_DSD_SetResultEventFlag()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_ClearResultEventFlag(XMC_DSD_t *const dsd, const uint32_t channel_id) +{ + XMC_ASSERT("XMC_DSD_ClearResultEventFlag:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->EVFLAGCLR = channel_id; +} +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param channel_id Channel number register value of type @ref XMC_DSD_CH_ID_t + * @return None + * + * \parDescription
+ * Set the alarm event flag.\n + * Set bit fields \a ALEVx of register \a EVFLAG.Clearing these bits has no effect. + * + * \parNote
+ * API call for channel-0 : XMC_DSD_SetAlarmEventFlag(DSD,(uint32_t)XMC_DSD_CH_ID_0); + * API call for channel-0 and 1: XMC_DSD_SetAlarmEventFlag(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1)); + * + * \parRelated APIs:
+ * XMC_DSD_ClearAlarmEventFlag()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_SetAlarmEventFlag(XMC_DSD_t *const dsd, const uint32_t channel_id) +{ + XMC_ASSERT("XMC_DSD_SetAlarmEventFlag:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->EVFLAG = (channel_id<< DSD_EVFLAGCLR_ALEC0_Pos); +} +/** + * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t + * @param channel_id Channel number register value of type @ref XMC_DSD_CH_ID_t + * @return None + * + * \parDescription
+ * Clear the result event flag.\n + * Set bit fields \a ALECx of register \a EVFLAGCLR.Clearing these bits has no effect. + * + * \parNote
+ * API call for channel-0 : XMC_DSD_ClearResultEventFlag(DSD,(uint32_t)XMC_DSD_CH_ID_0); + * API call for channel-0 and 1: XMC_DSD_ClearResultEventFlag(DSD,(uint32_t)(XMC_DSD_CH_ID_0|XMC_DSD_CH_ID_1)); + * + * \parRelated APIs:
+ * XMC_DSD_SetAlarmEventFlag()\n\n\n + */ +__STATIC_INLINE void XMC_DSD_ClearAlarmEventFlag(XMC_DSD_t *const dsd, const uint32_t channel_id) +{ + XMC_ASSERT("XMC_DSD_ClearAlarmEventFlag:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + dsd->EVFLAGCLR = (channel_id< +#if defined (EBU) +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup EBU + * @brief External Bus Unit (EBU) driver for the XMC4500 microcontroller + * + * The External Bus Unit (EBU) controls the transactions between external memories or + * peripheral units, and the internal memories and peripheral units. Several external + * device configurations are supported; e.g. Asynchronous static memories, SDRAM + * and various flash memory types. It supports multiple programmable address regions. + * + * The EBU low level driver provides functions to configure and initialize the EBU + * hardware peripheral. + * @{ + */ + +/********************************************************************************************************************** + * MACROS +**********************************************************************************************************************/ + +/** + * A convenient symbol for the EBU peripheral base address + */ +#if defined (EBU) +# define XMC_EBU ((XMC_EBU_t *)EBU_BASE) +#else +# error 'EBU' base peripheral pointer not defined +#endif + + +/* + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_EBU_CHECK_MODULE_PTR(p) ((p) == XMC_EBU) + +/********************************************************************************************************************** + * ENUMS +**********************************************************************************************************************/ + +/** + * Status return values for EBU low level driver + */ +typedef enum XMC_EBU_STATUS +{ + XMC_EBU_STATUS_OK = 0U, /**< Operation successful */ + XMC_EBU_STATUS_BUSY = 1U, /**< Busy with a previous request */ + XMC_EBU_STATUS_ERROR = 3U /**< Operation unsuccessful */ +} XMC_EBU_STATUS_t; + +/** + * EBU clock divide ratio + */ +typedef enum XMC_EBU_CLOCK_DIVIDE_RATIO +{ + XMC_EBU_CLOCK_DIVIDED_BY_1 = 0U, /**< Clock divided by 1 */ + XMC_EBU_CLOCK_DIVIDED_BY_2 = 1U, /**< Clock divided by 2 */ + XMC_EBU_CLOCK_DIVIDED_BY_3 = 2U, /**< Clock divided by 3 */ + XMC_EBU_CLOCK_DIVIDED_BY_4 = 3U /**< Clock divided by 4 */ +} XMC_EBU_CLOCK_DIVIDE_RATIO_t; + +/** + * EBU DIV2 clocking mode + */ +typedef enum XMC_EBU_DIV2_CLK_MODE +{ + XMC_EBU_DIV2_CLK_MODE_OFF = 0U, /**< Divider 2 clock mode OFF */ + XMC_EBU_DIV2_CLK_MODE_ON = 1U /**< Divider 2 clock mode ON */ +} XMC_EBU_DIV2_CLK_MODE_t; + +/** + * EBU clocking mode + */ +typedef enum XMC_EBU_CLK_MODE +{ + XMC_EBU_CLK_MODE_ASYNCHRONOUS_TO_AHB = 0U, /**< EBU is using standard clocking mode */ + XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU = 1U /**< EBU is running at AHB bus clock divided by 2 */ +} XMC_EBU_CLK_MODE_t; + +/** + * EBU arbitration mode + */ +typedef enum XMC_EBU_ARB_MODE +{ + XMC_EBU_ARB_MODE_NOT_SELECTED = 0U, /**< No Bus arbitration mode selected */ + XMC_EBU_ARB_MODE_ARBITER_MODE = 1U, /**< Arbiter Mode arbitration mode selected */ + XMC_EBU_ARB_MODE_PARTICIPANT_MODE = 2U, /**< Participant arbitration mode selected */ + XMC_EBU_ARB_MODE_SOLE_MASTER_MODE = 3U /**< Sole Master arbitration mode selected */ +} XMC_EBU_ARB_MODE_t; + +/** + * EBU ALE mode + */ +typedef enum XMC_EBU_ALE_MODE +{ + XMC_EBU_ALE_OUTPUT_IS_INV_ADV = 0U, /**< Output is ADV */ + XMC_EBU_ALE_OUTPUT_IS_ALE = 1U /**< Output is ALE */ +} XMC_EBU_ALE_MODE_t; + +/** + * EBU clock status + */ +typedef enum XMC_EBU_CLK_STATUS +{ + XMC_EBU_CLK_STATUS_DISABLE_BIT = EBU_CLC_DISS_Msk, /**< EBU Disable Status Bit */ + XMC_EBU_CLK_STATUS_MODE = EBU_CLC_SYNCACK_Msk, /**< EBU Clocking Mode Status */ + XMC_EBU_CLK_STATUS_DIV2_MODE = EBU_CLC_DIV2ACK_Msk, /**< DIV2 Clocking Mode Status */ + XMC_EBU_CLK_STATUS_DIV_RATIO = EBU_CLC_EBUDIVACK_Msk /**< EBU Clock Divide Ratio Status */ +} XMC_EBU_CLK_STATUS_t; + +/** + * EBU address selection + */ +typedef enum XMC_EBU_ADDRESS_SELECT +{ + XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE = EBU_ADDRSEL0_REGENAB_Msk, /**< Memory Region Enable */ + XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE = EBU_ADDRSEL0_ALTENAB_Msk, /**< Alternate Region Enable */ + XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_WRITE_PROTECT = EBU_ADDRSEL0_WPROT_Msk /**< Memory Region Write Protect */ +} XMC_EBU_ADDRESS_SELECT_t; + +/** + * EBU bus write configuration status + */ +typedef enum XMC_EBU_BUSWCON_SELECT +{ + XMC_EBU_BUSWCON_SELECT_NAN_WORKAROUND = EBU_BUSWCON0_NAA_Msk, /**< Enable flash non-array access workaround */ + XMC_EBU_BUSWCON_SELECT_DEVICE_ADDRESSING_MODE = EBU_BUSWCON0_PORTW_Msk, /**< Device Addressing Mode */ +} XMC_EBU_BUSWCON_SELECT_t; + +/** + * EBU burst length for synchronous burst + */ +typedef enum XMC_EBU_BURST_LENGTH_SYNC +{ + XMC_EBU_BURST_LENGTH_SYNC_1_DATA_ACCESS = 0U, /**< 1 data access (default after reset) */ + XMC_EBU_BURST_LENGTH_SYNC_2_DATA_ACCESSES = 1U, /**< 2 data access */ + XMC_EBU_BURST_LENGTH_SYNC_4_DATA_ACCESSES = 2U, /**< 3 data access */ + XMC_EBU_BURST_LENGTH_SYNC_8_DATA_ACCESSES = 3U, /**< 4 data access */ +} XMC_EBU_BURST_LENGTH_SYNC_t; + +/** + * EBU burst buffer mode + */ +typedef enum XMC_EBU_BURST_BUFFER_SYNC_MODE +{ + XMC_EBU_BURST_BUFFER_SYNC_LENGTH_SYNC_ENABLE = 0U, /**< Burst buffer length defined by value in FETBLEN */ + XMC_EBU_BURST_BUFFER_SYNC_SINGLE_MODE = 1U /**< All data required for transaction (single burst transfer) */ +} XMC_EBU_BURST_BUFFER_SYNC_MODE_t; + +/** + * Read single stage synchronization + */ +typedef enum XMC_EBU_READ_STAGES_SYNC +{ + XMC_EBU_READ_STAGES_SYNC_TWO = 0U, /**< Two stages of synchronization used (maximum margin) */ + XMC_EBU_READ_STAGES_SYNC_ONE = 1U /**< One stage of synchronization used (minimum latency) */ +} XMC_EBU_READ_STAGES_SYNC_t; + +/** + * EBU burst flash clock feedback enable/disable + */ +typedef enum XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK +{ + XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_DISABLE = 0U, /**< BFCLK feedback not used */ + XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE = 1U /**< BFCLK feedback used */ +} XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_t; + +/** + * EBU burst flash clock mode select + */ +typedef enum XMC_EBU_BURST_FLASH_CLOCK_MODE +{ + XMC_EBU_BURST_FLASH_CLOCK_MODE_RUN_CONTINUOSLY = 0U, /**< Burst flash clock runs continuously */ + XMC_EBU_BURST_FLASH_CLOCK_MODE_DISABLED_BETWEEN_ACCESSES = 1U /**< Burst flash clock disabled */ +} XMC_EBU_BURST_FLASH_CLOCK_MODE_t; + +/** + * EBU flash non-array access + */ +typedef enum XMC_EBU_FLASH_NON_ARRAY_ACCESS +{ + XMC_EBU_FLASH_NON_ARRAY_ACCESS_DISNABLE = 0U, /**< Disable non-array access */ + XMC_EBU_FLASH_NON_ARRAY_ACCESS_ENABLE = 1U /**< Enable non-array access */ +} XMC_EBU_FLASH_NON_ARRAY_ACCESS_t; + +/** + * EBU early chip select for synchronous burst + */ +typedef enum XMC_EBU_EARLY_CHIP_SELECT_SYNC_BURST +{ + XMC_EBU_EARLY_CHIP_SELECT_DELAYED = 0U, /**< Chip select delayed */ + XMC_EBU_EARLY_CHIP_SELECT_NOT_DELAYED = 1U /**< Chip select not delayed */ +} XMC_EBU_EARLY_CHIP_SELECT_SYNC_BURST_t; + +/** + * EBU early burst signal enable for synchronous burst + */ +typedef enum XMC_EBU_BURST_SIGNAL_SYNC_BURST +{ + XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_DELAYED = 0U, /**< Chip select delayed */ + XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_NOT_DELAYED = 1U /**< Chip select not delayed */ +} XMC_EBU_BURST_SIGNAL_SYNC_BURST_t; + +/** + * EBU burst address wrapping + */ +typedef enum XMC_EBU_BURST_ADDRESS_WRAPPING +{ + XMC_EBU_BURST_ADDRESS_WRAPPING_DISABLED = 0U, /**< Automatically re-aligns any non-aligned synchronous burst access */ + XMC_EBU_BURST_ADDRESS_WRAPPING_ENABLED = 1U /**< Starts any burst access at address specified by the AHB request */ +} XMC_EBU_BURST_ADDRESS_WRAPPING_t; + +/** + * EBU reversed polarity at WAIT + */ +typedef enum XMC_EBU_WAIT_SIGNAL_POLARITY +{ + XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_LOW = 0U, /**< OFF, input at WAIT pin is active low */ + XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_HIGH = 1U /**< Polarity reversed, input at WAIT pin is active high */ +} XMC_EBU_WAIT_SIGNAL_POLARITY_t; + +/** + * EBU byte control signal control + */ +typedef enum XMC_EBU_BYTE_CONTROL +{ + XMC_EBU_BYTE_CONTROL_FOLLOWS_CHIP_SELECT_TIMMING = 0U, /**< Control signals follow chip select timing */ + XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING = 1U, /**< Control signals follow control signal timing */ + XMC_EBU_BYTE_CONTROL_FOLLOWS_WRITE_ENABLE_SIGNAL_TIMMING = 2U /**< Control signals follow write enable timing */ +} XMC_EBU_BYTE_CONTROL_t; + +/** + * EBU device addressing mode + */ +typedef enum XMC_EBU_DEVICE_ADDRESSING_MODE +{ + XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS = 1U, /**< Address will only be driven onto AD[15:0] */ + XMC_EBU_DEVICE_ADDRESSING_MODE_TWIN_16_BITS_MULTIPLEXED = 2U, /**< Lower 16b will be driven onto A[15:0] & AD[15:0] */ + XMC_EBU_DEVICE_ADDRESSING_MODE_32_BITS_MULTIPLEXED = 3U /**< Full address driven onto A[15:0] & AD[15:0] */ +} XMC_EBU_DEVICE_ADDRESSING_MODE_t; + +/** + * EBU external wait control + */ +typedef enum XMC_EBU_WAIT_CONTROL +{ + XMC_EBU_WAIT_CONTROL_OFF = 0U, /**< Default after reset; Wait control off */ + XMC_EBU_WAIT_CONTROL_SYNC_EARLY_WAIT_ASYNC_ASYNC_INPUT_AT_WAIT = 1U, /**< SYNC: Wait for page load (Early WAIT); + ASYNC: Asynchronous input at WAIT */ + XMC_EBU_WAIT_CONTROL_SYNC_WAIT_WITH_DATA_ASYNC_SYNC_INPUT_AT_WAIT = 2U, /**< SYNC: Wait for page load (WAIT with data); + ASYNC: Synchronous input at WAIT; */ + XMC_EBU_WAIT_CONTROL_SYNC_ABORT_AND_RETRY_ACCESS = 3U /**< SYNC: Abort and retry access; */ +} XMC_EBU_WAIT_CONTROL_t; + +/** + * EBU asynchronous address phase + */ +typedef enum XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE +{ + XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_CLOCK_ENABLED_AT_BEGINNING_OF_ACCESS = 0U, /**< Enabled at beginning of access */ + XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_CLOCK_ENABLED_AFTER_ADDRESS_PHASE = 1U /**< Enabled after address phase */ +} XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_t; + +/** + * EBU device type for region + */ +typedef enum XMC_EBU_DEVICE_TYPE +{ + XMC_EBU_DEVICE_TYPE_MUXED_ASYNCHRONOUS_TYPE = 0U, /**< Device type muxed asynchronous */ + XMC_EBU_DEVICE_TYPE_MUXED_BURST_TYPE = 1U, /**< Device type muxed burst */ + XMC_EBU_DEVICE_TYPE_NAND_FLASH = 2U, /**< Device type NAND flash */ + XMC_EBU_DEVICE_TYPE_MUXED_CELLULAR_RAM = 3U, /**< Device type muxed cellular RAM */ + XMC_EBU_DEVICE_TYPE_DEMUXED_ASYNCHRONOUS_TYPE = 4U, /**< Device type de-muxed asynchronous */ + XMC_EBU_DEVICE_TYPE_DEMUXED_BURST_TYPE = 5U, /**< Device type de-muxed burst */ + XMC_EBU_DEVICE_TYPE_DEMUXED_PAGE_MODE = 6U, /**< Device type de-muxed page mode */ + XMC_EBU_DEVICE_TYPE_DEMUXED_CELLULAR_RAM = 7U, /**< Device type de-muxed cellular RAM */ + XMC_EBU_DEVICE_TYPE_SDRAM = 8U /**< Device type SDRAM */ +} XMC_EBU_DEVICE_TYPE_t; + +/** + * EBU lock chip select + */ +typedef enum XMC_EBU_LOCK_CHIP_SELECT +{ + XMC_EBU_LOCK_CHIP_SELECT_DISABLED = 0U, /**< Chip select cannot be locked */ + XMC_EBU_LOCK_CHIP_SELECT_ENABLED = 1U /**< Chip select automatically locked after a write operation */ +} XMC_EBU_LOCK_CHIP_SELECT_t; + +/** + * EBU Frequency of external clock at pin BFCLKO + */ +typedef enum XMC_EBU_FREQUENCY_EXT_CLK_PIN +{ + XMC_EBU_FREQ_EXT_CLK_PIN_EQUAL_TO_INT_CLK = 0U, /**< Equal to INT_CLK frequency */ + XMC_EBU_FREQ_EXT_CLK_PIN_HALF_OF_INT_CLK = 1U, /**< 1/2 of INT_CLK frequency */ + XMC_EBU_FREQ_EXT_CLK_PIN_THIRD_OF_INT_CLK = 2U, /**< 1/3 of INT_CLK frequency */ + XMC_EBU_FREQ_EXT_CLK_PIN_QUARTER_OF_INT_CLK = 3U /**< 1/4 of INT_CLK frequency */ +} XMC_EBU_FREQ_EXT_CLK_PIN_t; + +/** + * EBU extended data + */ +typedef enum XMC_EBU_EXT_DATA +{ + XMC_EBU_EXT_DATA_OUTPUT_EVERY_1_BFCLK_CYCLES = 0U, /**< External memory outputs data every BFCLK cycle */ + XMC_EBU_EXT_DATA_OUTPUT_EVERY_2_BFCLK_CYCLES = 1U, /**< External memory outputs data every two BFCLK cycles */ + XMC_EBU_EXT_DATA_OUTPUT_EVERY_4_BFCLK_CYCLES = 2U, /**< External memory outputs data every four BFCLK cycles */ + XMC_EBU_EXT_DATA_OUTPUT_EVERY_8_BFCLK_CYCLES = 3U /**< External memory outputs data every eight BFCLK cycles */ +} XMC_EBU_EXT_DATA_t; + +/** + * EBU SDRAM clock mode select + */ +typedef enum XMC_EBU_SDRAM_CLK_MODE +{ + XMC_EBU_SDRAM_CLK_MODE_CONTINUOUSLY_RUNS = 0U, /**< Clock continuously running */ + XMC_EBU_SDRAM_CLK_MODE_DISABLED_BETWEEN_ACCESSES = 1U /**< Clock disabled between accesses */ +} XMC_EBU_SDRAM_CLK_MODE_t; + +/** + * EBU power save mode used for gated clock mode + */ +typedef enum XMC_EBU_SDRAM_PWR_MODE +{ + XMC_EBU_SDRAM_PWR_MODE_PRECHARGE_BEFORE_CLK_STOP = 0U, /**< Precharge before clock stop */ + XMC_EBU_SDRAM_PWR_MODE_AUTO_PRECHARGE_BEFORE_CLK_STOP = 1U, /**< Auto-precharge before clock stop */ + XMC_EBU_SDRAM_PWR_MODE_ACTIVE_PWR_DOWN = 2U, /**< Active power down (stop clock without precharge) */ + XMC_EBU_SDRAM_PWR_MODE_CLK_STOP_PWR_DOWN = 3U /**< Clock stop power down */ +} XMC_EBU_SDRAM_PWR_MODE_t; + +/** + * EBU disable SDRAM clock output + */ +typedef enum XMC_EBU_SDRAM_CLK_OUTPUT +{ + XMC_EBU_SDRAM_CLK_OUTPUT_ENABLED = 0U, /**< Clock output enabled */ + XMC_EBU_SDRAM_CLK_OUTPUT_DISABLED = 1U /**< Clock output disabled */ +} XMC_EBU_SDRAM_CLK_OUTPUT_t; + +/** + * EBU mask for bank tag + */ +typedef enum XMC_EBU_SDRAM_MASK_FOR_BANKM_TAG +{ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_21_to_20 = 1U, /**< Mask for bank tag addresses 21 to 20 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_22_to_21 = 2U, /**< Mask for bank tag addresses 22 to 21 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_23_to_22 = 3U, /**< Mask for bank tag addresses 23 to 22 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_24_to_23 = 4U, /**< Mask for bank tag addresses 24 to 23 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_25_to_24 = 5U, /**< Mask for bank tag addresses 25 to 24 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_26_to_25 = 6U, /**< Mask for bank tag addresses 26 to 25 */ + XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_26 = 7U /**< Mask for bank tag addresses 26 */ +} XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_t; + +/** + * EBU Mask for row tag + */ +typedef enum XMC_EBU_SDRAM_MASK_FOR_ROW_TAG +{ + XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_9 = 1U, /**< Mask for row tag addresses 26 to 9 */ + XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_10 = 2U, /**< Mask for row tag addresses 26 to 10 */ + XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_11 = 3U, /**< Mask for row tag addresses 26 to 11 */ + XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_12 = 4U, /**< Mask for row tag addresses 26 to 12 */ + XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_13 = 5U /**< Mask for row tag addresses 26 to 13 */ +} XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_t; + +/** + * Number of address bits from bit 0 to be used for column address + */ +typedef enum XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS +{ + XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_8_to_0 = 1U, /**< Address [8:0] */ + XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_9_to_0 = 2U, /**< Address [9:0] */ + XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_10_to_0 = 3U /**< Address [10:0] */ +} XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_t; + +/** + * Number of clocks between a READ command and the availability of data + */ +typedef enum XMC_EBU_SDRAM_CAS_LATENCY +{ + XMC_EBU_SDRAM_CAS_LATENCY_2_CLKS = 2U, /**< 2 clocks between a READ command and the availability of data */ + XMC_EBU_SDRAM_CAS_LATENCY_3_CLKS = 3U /**< 3 clocks between a READ command and the availability of data */ +} XMC_EBU_SDRAM_CAS_LATENCY_t; + +/** + * Number of locations can be accessed with a single command + */ +typedef enum XMC_EBU_SDRAM_BURST_LENGTH +{ + XMC_EBU_SDRAM_BURST_LENGTH_1_LOCATION = 0U, /**< One location accessed with a single command */ + XMC_EBU_SDRAM_BURST_LENGTH_2_LOCATION = 1U, /**< Two location accessed with a single command */ + XMC_EBU_SDRAM_BURST_LENGTH_4_LOCATION = 2U, /**< Four location accessed with a single command */ + XMC_EBU_SDRAM_BURST_LENGTH_8_LOCATION = 3U, /**< Eight location accessed with a single command */ + XMC_EBU_SDRAM_BURST_LENGTH_16_LOCATION = 4U /**< Sixteen location accessed with a single command */ +} XMC_EBU_SDRAM_BURST_LENGTH_t; + +/** + * EBU SDRAM status + */ +typedef enum XMC_EBU_SDRAM_STATUS +{ + XMC_EBU_SDRAM_STATUS_RX_ERROR = EBU_SDRSTAT_SDERR_Msk, /**< Detected an error when returning read data */ + XMC_EBU_SDRAM_STATUS_BUSY = EBU_SDRSTAT_SDRMBUSY_Msk, /**< The status of power-up initialization sequence */ + XMC_EBU_SDRAM_STATUS_REFRESH_ERROR = EBU_SDRSTAT_REFERR_Msk /**< Failed previous refresh req collides with new req */ +} XMC_EBU_SDRAM_STATUS_t; + +/** + * SDRAM refresh status + */ +typedef enum XMC_EBU_SDRAM_RFRSH_STATUS +{ + XMC_EBU_SDRAM_RFRSH_STATUS_SELF_REFRESH_ENTRY_STATUS = EBU_SDRMREF_SELFRENST_Msk, /**< Self refresh entry command issue successful */ + XMC_EBU_SDRAM_RFRSH_STATUS_SELF_REFRESH_EXIT_STATUS = EBU_SDRMREF_SELFREXST_Msk /**< Self refresh exit command issue successful */ +} XMC_EBU_SDRAM_RFRSH_STATUS_t; + + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ + +/* Anonymous structure/union guard start */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__TASKING__) + #pragma warning 586 +#endif + +/** + * Clock configuration values of EBU
+ * + * The structure presents a convenient way to set/obtain the clock configuration + * values for clock mode, div2 clock mode and clock divide ratio of EBU. + * The XMC_EBU_Init() can be used to populate the structure with the clock + * configuration values of the EBU module. + */ +typedef struct XMC_EBU_CLK_CONFIG +{ + union + { + uint32_t raw0; + struct + { + uint32_t : 16; + uint32_t ebu_clk_mode : 1; /**< Clocking mode */ + uint32_t ebu_div2_clk_mode : 1; /**< DIV2 clocking mode */ + uint32_t ebu_clock_divide_ratio : 2; /**< Clock divide ratio */ + uint32_t : 12; + }; + }; +} XMC_EBU_CLK_CONFIG_t; + +/** + * Mode configuration values for EBU
+ * + * The structure presents a convenient way to set/obtain the mode configuration, + * SDRAM tristate, external clock, arbitration, timeout control and ALE mode for + * EBU. The XMC_EBU_Init() can be used to populate the structure with the + * clock configuration values of the EBU module. + */ +typedef struct XMC_EBU_MODE_CONFIG +{ + union + { + uint32_t raw0; + struct + { + uint32_t : 2; + uint32_t ebu_sdram_tristate : 1; /**< 0 - SDRAM cannot be shared; 1 - SDRAM can be shared */ + uint32_t : 1; + uint32_t ebu_extlock : 1; /**< 0 - ext bus is not locked after the EBU gains ownership; 1 - ext bus is not locked */ + uint32_t ebu_arbsync : 1; /**< 0 - arbitration inputs are sync; 1 - arbitration inputs are async */ + uint32_t ebu_arbitration_mode : 2; /**< Arbitration mode */ + /**< Determines num of inactive cycles leading to a bus timeout after the EBU gains ownership
+ 00H: Timeout is disabled
+ 01H: Timeout is generated after 1 x 8 clock cycles
+ FFH: Timeout is generated after 255 x 8 clock cycles */ + uint32_t bus_timeout_control : 8; /**< Determines num of inactive cycles leading to a bus timeout after the EBU gains ownership
+ 00H: Timeout is disabled
+ 01H: Timeout is generated after 1 x 8 clock cycles
+ FFH: Timeout is generated after 255 x 8 clock cycles
*/ + uint32_t : 15; + uint32_t ebu_ale_mode : 1; /**< ALE mode */ + }; + }; +} XMC_EBU_MODE_CONFIG_t; + +/** + * GPIO mode configuration for the allocated EBU ports
+ * Configuring this structure frees the allocated EBU ports for GPIO + * functionality. The XMC_EBU_Init() is used to populate the structure + * with the GPIO mode for the allocated EBU ports. + */ +typedef struct XMC_EBU_FREE_PINS_TO_GPIO +{ + union + { + uint32_t raw0; + struct + { + uint32_t : 16; + uint32_t address_pins_gpio : 9; /**< 0 - Address bit required for addressing memory; 1 - Address bit available as GPIO */ + uint32_t adv_pin_gpio : 1; /**< Adv pin to GPIO mode */ + uint32_t : 6; + }; + }; +} XMC_EBU_FREE_PINS_TO_GPIO_t; + +/** + * Read configuration for a region of EBU
+ * + * The structure presents a convenient way to set/obtain the read and read timing + * configuration for a region for EBU. The XMC_EBU_ConfigureRegion() can be + * used to populate the structure with the read configuration values for EBU. + */ +typedef struct XMC_EBU_BUS_READ_CONFIG +{ + /* EBU read configuration parameters */ + union + { + uint32_t raw0; + struct + { + uint32_t ebu_burst_length_sync : 3; /**< Burst length for synchronous burst */ + uint32_t ebu_burst_buffer_sync_mode : 1; /**< Burst buffer mode */ + uint32_t ebu_read_stages_synch : 1; /**< Read single stage synchronization */ + uint32_t ebu_burst_flash_clock_feedback : 1; /**< Burst flash clock feedback enable/disable */ + uint32_t ebu_burst_flash_clock_mode : 1; /**< Burst flash clock mode select */ + uint32_t ebu_flash_non_array_access : 1; /**< flash non-array access */ + uint32_t : 8; + uint32_t ebu_early_chip_select_sync_burst : 1; /**< Early chip select for sync burst */ + uint32_t ebu_burst_signal_sync : 1; /**< Early burst signal enable for synchronous burst */ + uint32_t ebu_burst_address_wrapping : 1; /**< Burst address wrapping */ + uint32_t ebu_wait_signal_polarity : 1; /**< Reversed polarity at WAIT */ + uint32_t ebu_byte_control : 2; /**< Byte control signal control */ + uint32_t ebu_device_addressing_mode : 2; /**< Device addressing mode */ + uint32_t ebu_wait_control : 2; /**< External wait control */ + uint32_t ebu_asynchronous_address_phase : 1; /**< Asynchronous address phase */ + uint32_t : 1; + uint32_t ebu_device_type : 4; /**< Device type for region */ + }; + }; + /* EBU read access parameters */ + union + { + uint32_t raw1; + struct + { + uint32_t ebu_recovery_cycles_between_different_regions : 4; + /** + * Recovery cycles after read accesses:
+ * 000B: No recovery phase clock cycles available
+ * 001B: 1 clock cycle selected
+ * ...
+ * 110B: 6 clock cycles selected
+ * 111B: 7 clock cycles selected
+ */ + uint32_t ebu_recovery_cycles_after_read_accesses : 3; + /** + * Programmed wait states for read accesses:
+ * 00000B: 1 wait state
+ * 00001B: 1 wait state
+ * 00010B: 2 wait state
+ * ...
+ * 11110B: 30 wait states
+ * 11111B: 31 wait states
+ */ + uint32_t ebu_programmed_wait_states_for_read_accesses : 5; + /** + * + */ + uint32_t ebu_data_hold_cycles_for_read_accesses: 4; + /** + * Frequency of external clock at pin BFCLKO + */ + uint32_t ebu_freq_ext_clk_pin : 2; + /** + * EBU Extended data + */ + uint32_t ebu_ext_data : 2; + /** + * Command delay cycles:
+ * 0000B: 0 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t command_delay_lines : 4; + /** + * Address hold cycles:
+ * 0000B: 0 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t address_hold_cycles : 4; + /** + * Address Cycles: + * 0000B: 1 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t address_cycles : 4; + }; + }; +} XMC_EBU_BUS_READ_CONFIG_t; + +/** + * Write configuration for a region of EBU
+ * + * The structure presents a convenient way to set/obtain the write and write timing + * configurations for a region of EBU. The XMC_EBU_ConfigureRegion() can be used + * to populate the structure with the write configuration values of EBU. + */ +typedef struct XMC_EBU_BUS_WRITE_CONFIG +{ + /* EBU write configuration parameters */ + union + { + uint32_t raw0; + struct + { + uint32_t ebu_burst_length_sync : 3; /**< Burst length for synchronous burst */ + uint32_t ebu_burst_buffer_sync_mode : 1; /**< Burst buffer mode */ + uint32_t : 12; + uint32_t ebu_early_chip_select_sync_burst : 1; /**< Early chip select for sync burst*/ + uint32_t ebu_burst_signal_sync : 1; /**< Early burst signal enable for synchronous burst */ + uint32_t : 1; + uint32_t ebu_wait_signal_polarity : 1; /**< Reversed polarity at WAIT */ + uint32_t ebu_byte_control : 2; /**< Byte control signal control */ + uint32_t ebu_device_addressing_mode : 2; /**< Device addressing mode */ + uint32_t ebu_wait_control : 2; /**< External wait control */ + uint32_t ebu_asynchronous_address_phase : 1; /**< Asynchronous address phase */ + uint32_t ebu_lock_chip_select : 1; /**< Lock chip select */ + uint32_t ebu_device_type : 4; /**< Device type for region */ + }; + }; + /* EBU write access parameters */ + union + { + uint32_t raw1; + struct + { + /** + * Recovery cycles between different regions:
+ * 0000B: No recovery phase clock cycles available
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t ebu_recovery_cycles_between_different_regions : 4; + + /** + * Recovery cycles after write accesses:
+ * 000B: No recovery phase clock cycles available
+ * 001B: 1 clock cycle selected
+ * ...
+ * 110B: 6 clock cycles selected
+ * 111B: 7 clock cycles selected
+ */ + uint32_t ebu_recovery_cycles_after_write_accesses : 3; + + /** + * Programmed wait states for write accesses:
+ * 00000B: 1 wait state
+ * 00001B: 1 wait state
+ * 00010B: 2 wait state
+ * ...
+ * 11110B: 30 wait states
+ * 11111B: 31 wait states
+ */ + uint32_t ebu_programmed_wait_states_for_write_accesses : 5; + + /** + * + */ + uint32_t ebu_data_hold_cycles_for_write_accesses : 4; + /**< + * Frequency of external clock at pin BFCLKO + */ + uint32_t ebu_freq_ext_clk_pin : 2; + /** + * EBU extended data + */ + uint32_t ebu_ext_data : 2; + /** + * Command delay cycles:
+ * 0000B: 0 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t command_delay_lines : 4; + /** Address hold cycles:
+ * 0000B: 0 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t address_hold_cycles : 4; + /** + * Address cycles:
+ * 0000B: 1 clock cycle selected
+ * 0001B: 1 clock cycle selected
+ * ...
+ * 1110B: 14 clock cycles selected
+ * 1111B: 15 clock cycles selected
+ */ + uint32_t address_cycles : 4; + }; + }; +}XMC_EBU_BUS_WRITE_CONFIG_t; + +/** + * SDRAM configuration structure
+ * + * The structure is a placeholder for setting (and obtaining) the SDRAM configuration, + * operation mode configuration and the right refresh parameters. The XMC_EBU_ConfigureSdram() + * can be used to populate the structure with the SDRAM operation mode and + * refresh parameters configuration. + */ +typedef struct XMC_EBU_SDRAM_CONFIG +{ + /* EBU SDRAM control parameters */ + union + { + uint32_t raw0; + struct + { + /** + * Number of clock cycles between row activate command and a precharge + * command + */ + uint32_t ebu_row_precharge_delay_counter : 4; + /** + * (CRFSH) Number of refresh commands issued during powerup init sequence: + * Perform CRFSH + 1 refresh cycles + */ + uint32_t ebu_init_refresh_commands_counter : 4; + /** + * (CRSC) Number of NOP cycles after a mode register set command: + * Insert CRSC + 1 NOP cycles + */ + uint32_t ebu_mode_register_set_up_time : 2; + /** + * (CRP) Number of NOP cycles inserted after a precharge command: + * Insert CRP + 1 NOP cycles + */ + uint32_t ebu_row_precharge_time_counter : 2; + /** + * Number of address bits from bit 0 to be used for column address + */ + uint32_t ebu_sdram_width_of_column_address : 2; + /** + * (CRCD) Number of NOP cycles between a row address and a column + * address: Insert CRCD + 1 NOP cycles + */ + uint32_t ebu_sdram_row_to_column_delay_counter : 2; + /** + * Row cycle time counter: Insert (CRCE * 8) + CRC + 1 NOP cycles + */ + uint32_t ebu_sdram_row_cycle_time_counter : 3; + /** + * Mask for row tag + */ + uint32_t ebu_sdram_mask_for_row_tag : 3; + /** + * Mask for bank tag + */ + uint32_t ebu_sdram_mask_for_bank_tag : 3; + /** + * Extension to the Row cycle time counter (CRCE) + */ + uint32_t ebu_sdram_row_cycle_time_counter_extension : 3; + /** + * Disable SDRAM clock output + */ + uint32_t ebu_sdram_clk_output : 1; + /** + * Power Save Mode used for gated clock mode + */ + uint32_t ebu_sdram_pwr_mode : 2; + /** + * SDRAM clock mode select + */ + uint32_t ebu_sdram_clk_mode : 1; + }; + }; + /* EBU SDRAM mode parameters */ + union + { + uint32_t raw1; + struct + { + /** + * Number of locations can be accessed with a single command + */ + uint32_t ebu_sdram_burst_length : 3; + uint32_t : 1; + /** + * Number of clocks between a READ command and the availability + * of data + */ + uint32_t ebu_sdram_casclk_mode : 3; + uint32_t : 8; + /** + * Cold start + */ + uint32_t ebu_sdram_cold_start: 1; + /** + * Value to be written to the extended mode register of a mobile + * SDRAM device + */ + uint32_t ebu_sdram_extended_operation_mode : 12; + /** + * Value to be written to the bank select pins of a mobile SDRAM + * device during an extended mode register write operation + */ + uint32_t ebu_sdram_extended_operation_bank_select : 4; + }; + }; + /* EBU SDRAM refresh parameters */ + union + { + uint32_t raw2; + struct + { + /** + * Number of refresh counter period: + * Refresh period is 'num_refresh_counter_period' x 64 clock cycles + */ + uint32_t ebu_sdram_num_refresh_counter_period : 6; + /** + * Number of refresh commands + */ + uint32_t ebu_sdram_num_refresh_cmnds : 3; + uint32_t : 1; + /** + * If 1, the self refresh exit command is issued to all SDRAM devices + * regardless of their attachment to type 0 or type 1 + */ + uint32_t ebu_sdram_self_refresh_exit : 1; + uint32_t : 1; + /** + * If "1", the self refresh entry command is issued to all SDRAM devices, + * regardless regardless of their attachment to type 0 or type 1 + */ + uint32_t ebu_sdram_self_refresh_entry : 1; + /** + * If 1, memory controller will automatically issue the "self refresh + * entry" command to all SDRAM devices when it gives up control of the + * external bus. It will also automatically issue "self refresh exit" + * when it regains control of the bus + */ + uint32_t ebu_sdram_auto_self_refresh : 1; + /** + * Extended number of refresh counter period + */ + uint32_t ebu_sdram_extended_refresh_counter_period : 2; + /** + * Number of NOP cycles inserted after a self refresh exit before a + * command is permitted to the SDRAM/DDRAM + */ + uint32_t ebu_sdram_self_refresh_exit_delay : 8; + /** + * If 1, an auto refresh cycle will be performed; If 0, no refresh will + * be performed + */ + uint32_t ebu_sdram_auto_refresh : 1; + /** + * Number of NOPs after the SDRAM controller exits power down before an + * active command is permitted + */ + uint32_t ebu_sdram_delay_on_power_down_exit : 3; + uint32_t : 4; + }; + }; +} XMC_EBU_SDRAM_CONFIG_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__TASKING__) + #pragma warning restore +#endif + +/** + * EBU region initialization with read configurations
+ * + * The structure presents a convenient way to set/obtain the read and read timing + * configurations for a region of EBU. The XMC_EBU_ConfigureRegion() can be + * used to populate the structure with the read configuration values of EBU + */ +typedef struct XMC_EBU_REGION_READ_CONFIG +{ + const uint32_t ebu_region_no; /**< Number of region*/ + XMC_EBU_BUS_READ_CONFIG_t ebu_bus_read_config; /**< Read configuration and access parameters structure */ +} XMC_EBU_REGION_READ_CONFIG_t; + +/** + * EBU region initialization with write configurations
+ * + * The structure presents a convenient way to set/obtain the write and write + * timing configurations for a region of EBU. The XMC_EBU_ConfigureRegion() + * can be used to populate the structure with the write configuration + * values of EBU. + */ +typedef struct XMC_EBU_REGION_WRITE_CONFIG +{ + const uint32_t ebu_region_no; /**< Number of refresh counter period */ + XMC_EBU_BUS_WRITE_CONFIG_t ebu_bus_write_config; /**< Write configuration and access parameters structure */ +} XMC_EBU_REGION_WRITE_CONFIG_t; + +/** + * EBU region initialization with read and write configurations
+ * + * The structure presents a convenient way to set/obtain the read, read timing, + * write and write timing configurations for a region of EBU. The + * XMC_EBU_ConfigureRegion() can be used to populate the structure with the + * region read and write configuration values of EBU. + */ +typedef struct XMC_EBU_REGION +{ + XMC_EBU_REGION_READ_CONFIG_t read_config; + XMC_EBU_REGION_WRITE_CONFIG_t write_config; +} XMC_EBU_REGION_t; + +/** + * EBU global configurations
+ * + * The structure presents a convenient way to set/obtain the global configurations + * of the EBU like clock, mode and GPIO mode. The XMC_EBU_Init() can be + * used to populate the structure with the region read and write configuration + * values of EBU. + */ +typedef struct XMC_EBU_CONFIG +{ + XMC_EBU_CLK_CONFIG_t ebu_clk_config; /**< Clock configuration structure */ + XMC_EBU_MODE_CONFIG_t ebu_mode_config; /**< Mode configuration structure */ + XMC_EBU_FREE_PINS_TO_GPIO_t ebu_free_pins_to_gpio; /**< Free allocated EBU ports for GPIO */ +} XMC_EBU_CONFIG_t; + +/** + * External Bus Unit (EBU) device structure
+ * + * The structure represents a collection of all hardware registers + * used to configure the EBU peripheral on the XMC4500 microcontroller. + * The registers can be accessed with ::XMC_EBU. + */ +typedef struct +{ + __IO uint32_t CLC; + __IO uint32_t MODCON; + __I uint32_t ID; + __IO uint32_t USERCON; + __I uint32_t RESERVED0[2]; + __IO uint32_t ADDRSEL[4]; + struct + { + __IO uint32_t RDCON; + __IO uint32_t RDAPR; + __IO uint32_t WRCON; + __IO uint32_t WRAPR; + } BUS[4]; + __IO uint32_t SDRMCON; + __IO uint32_t SDRMOD; + __IO uint32_t SDRMREF; + __I uint32_t SDRSTAT; +} XMC_EBU_t; + +/********************************************************************************************************************** + * API PROTOTYPES +**********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param config Constant pointer to a constant ::XMC_EBU_CONFIG_t structure containing the + * clock mode and clock configuration. + * @return XMC_EBU_STATUS_t Always returns XMC_EBU_STATUS_OK (Only register assignment statements) + * + * \parDescription:
+ * Initialize the EBU peripheral
+ * + * \par + * The function enables the EBU peripheral, configures time values for clock mode, div2 + * clock mode, mode configuration, SDRAM tristate, external clock, arbitration, timeout + * control, ALE mode and configuration to free up the allocated EBU ports for GPIO + * functionality (if required). + */ +XMC_EBU_STATUS_t XMC_EBU_Init(XMC_EBU_t *const ebu, const XMC_EBU_CONFIG_t *const config); + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param config Constant pointer to a constant ::XMC_EBU_SDRAM_CONFIG_t structure containing + * the SDRAM configuration, operation mode configuration and right refresh + * parameters + * @return None + * + * \parDescription:
+ * Configures the SDRAM
+ * + * \par + * The function enables the SDRAM, sets SDRAM configuration parameters such as operation + * mode and refresh parameters. Please see ::XMC_EBU_SDRAM_CONFIG_t for more information. + */ +void XMC_EBU_ConfigureSdram(XMC_EBU_t *const ebu, const XMC_EBU_SDRAM_CONFIG_t *const config); + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param region Constant pointer to a constant ::XMC_EBU_REGION_t structure containing the + * read, read timing, write and write timing configurations for a region of + * EBU + * @return None + * + * \parDescription:
+ * Configures the SDRAM
+ * + * \par + * The function configures the EBU region read, read timing, write and write timing parameter + * configuration. It also configures the region registers for read and write accesses. Please + * see ::XMC_EBU_REGION_t for more information. + * + */ +void XMC_EBU_ConfigureRegion(XMC_EBU_t *const ebu, const XMC_EBU_REGION_t *const region); + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Enable EBU peripheral
+ * + * \par + * The function de-asserts the peripheral reset. The peripheral needs to be initialized. + * It also enables the control of the EBU. + * + * \parRelated APIs:
+ * XMC_EBU_Disable(), XMC_SCU_RESET_AssertPeripheralReset() + */ +__STATIC_INLINE void XMC_EBU_Enable(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_Enable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_EBU); + ebu->CLC &= ~EBU_CLC_DISR_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Disable EBU peripheral
+ * + * \par + * The function asserts the peripheral reset. It also disables the control of the EBU. + * + * \parRelated APIs:
+ * XMC_EBU_Enable(), XMC_SCU_RESET_DeassertPeripheralReset() + */ +__STATIC_INLINE void XMC_EBU_Disable(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_Disable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->CLC |= EBU_CLC_DISR_Msk; + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_EBU); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param clk_status Constant structure ::XMC_EBU_CLK_STATUS_t, containing the + * disable status, clock mode status, DIV2 clock mode status + * and clock divide ratio + * @return Status Returns clock status, disable status, clock mode status, DIV2 clock + * mode status and clock divide ratio + * + * \parDescription:
+ * Gets the clock status of EBU peripheral
+ * + * \par + * The function returns the clock staus of the EBU peripheral. The return value will + * indicate the following parameters:
+ * 1) Is EBU disabled?
+ * 2) Clocking mode
+ * 3) DIV2 clocking mode
+ * 4) Clock divide ratio
+ * + * \parRelated APIs:
+ * XMC_EBU_Enable(), XMC_EBU_Disable() and XMC_EBU_CLKDivideRatio() + */ +__STATIC_INLINE uint32_t XMC_EBU_GetCLKStatus(XMC_EBU_t *const ebu, const XMC_EBU_CLK_STATUS_t clk_status) +{ + XMC_ASSERT("XMC_EBU_GetCLKStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + return (uint32_t)(ebu->CLC & clk_status); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param clock_divide_ratio Structure ::XMC_EBU_CLOCK_DIVIDE_RATIO_t, containing the + * clock division factors of 1, 2, 3 and 4 respectively + * @return None + * + * \parDescription:
+ * Sets the clock divide ratio for EBU peripheral
+ * + * \par + * The function sets the CLC.EBUDIV bit-field to configure the clock divide ratio + * value (input clock divide by factor). + * + * \parRelated APIs:
+ * XMC_EBU_Enable(), XMC_EBU_Disable() and XMC_EBU_GetCLKStatus() + */ +__STATIC_INLINE void XMC_EBU_CLKDivideRatio(XMC_EBU_t *ebu, XMC_EBU_CLOCK_DIVIDE_RATIO_t clock_divide_ratio) +{ + XMC_ASSERT("XMC_EBU_CLKDivideRatio: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->CLC |= ((clock_divide_ratio << EBU_CLC_EBUDIV_Pos) & EBU_CLC_EBUDIV_Msk); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Sets the SDRAM self refresh exit (Power up)
+ * + * \par + * The function sets the SDRMREF.SELFREX bit to issue the self refresh command to + * all the SDRAM units. This ensures that the SDRAM units come out of the power down + * mode. The function also resets the bit SDRMREF.SELFRENST(Self refresh entry status). + */ +__STATIC_INLINE void XMC_EBU_SdramSetSelfRefreshExit(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramSetSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF |= EBU_SDRMREF_SELFREX_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Sets the SDRAM self refresh entry
+ * + * \par + * The function sets the SDRMREF.SELFREN bit-field to issue the self refresh command + * to all the SDRAM units. This ensures that the SDRAM units enter the power down mode + * after pre-charge. The function also resets the bit SDRMREF.SELFREXST(Self refresh + * exit status). + */ +__STATIC_INLINE void XMC_EBU_SdramSetSelfRefreshEntry(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramSetSelfRefreshEntry: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF |= EBU_SDRMREF_SELFREN_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Resets the SDRAM self refresh exit (Power up)
+ * + * \par + * The function resets the SDRMREF.SELFREX bit-field to stop issuing the self + * refresh command to all the SDRAM units connected to the bus. This ensures that + * the SDRAM units don't come out of the power down mode. + * + */ +__STATIC_INLINE void XMC_EBU_SdramResetSelfRefreshExit(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramResetSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF &= ~EBU_SDRMREF_SELFREX_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Resets the SDRAM self refresh entry
+ * + * \par + * The function resets the SDRMREF.SELFREN bit-field to stop issuing the self + * refresh command to all the SDRAM units. This ensures that the SDRAM units + * don't go into the power down mode after the pre-charge is all done. + * + */ +__STATIC_INLINE void XMC_EBU_SdramResetSelfRefreshEntry(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramResetSelfRefreshEntry: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF &= ~EBU_SDRMREF_SELFREN_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Sets the SDRAM auto refresh on self refresh exit
+ * + * \par + * The function sets the SDRMREF.ARFSH bit-field to enable an auto refresh cycle + * on existing self refresh before the self refresh exit delay. + * + * \parRelated APIs:
+ * XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit() + */ +__STATIC_INLINE void XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF |= EBU_SDRMREF_ARFSH_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Resets the SDRAM auto refresh on self refresh exit
+ * + * \par + * The function resets the SDRMREF.ARFSH bit to disable an auto refresh cycle + * on existing self refresh before the self refresh exit delay. No refresh will be + * performed. + * + * \parRelated APIs:
+ * XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit() + */ +__STATIC_INLINE void XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF &= ~EBU_SDRMREF_ARFSH_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Sets the SDRAM automatic self refresh
+ * + * \par + * The function sets the SDRMREF.AUTOSELFR bit-field. When set, the memory controller + * automatically issues the self refresh entry command to all SDRAM units + * devices when it gives up control of the external bus. It will also automatically + * issue the self refresh exit command when it regains control of the bus. + * + * \parRelated APIs:
+ * XMC_EBU_SdramDisableAutomaticSelfRefresh() + */ +__STATIC_INLINE void XMC_EBU_SdramEnableAutomaticSelfRefresh(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramEnableAutomaticSelfRefresh: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF |= EBU_SDRMREF_AUTOSELFR_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return None + * + * \parDescription:
+ * Resets the SDRAM automatic self refresh
+ * + * \par + * The function resets the SDRMREF.AUTOSELFR bit-field. When reset, the memory controller + * doesn't issue the self refresh entry command when it gives up control of the external + * bus. It will also not issue the self refresh exit command when it regains control of + * the bus. + * + * \parRelated APIs:
+ * XMC_EBU_SdramEnableAutomaticSelfRefresh() + */ +__STATIC_INLINE void XMC_EBU_SdramDisableAutomaticSelfRefresh(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramDisableAutomaticSelfRefresh: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->SDRMREF &= ~EBU_SDRMREF_AUTOSELFR_Msk; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu_addr_select_en Choose between a memory region enable or an alternate region enable + * @param ebu_region_n A valid region number for which enable and protection settings + * need to be configured + * @return None + * + * \parDescription:
+ * Controls the enable and protection settings of a region
+ * + * \par + * The function controls the enable and protection settings of a memory or alternate + * region. It configures the memory region enable, alternate region enable and the memory + * region's write protection. The bit-fields ADDRSEL.REGENAB, ADDRSEL.ALTENAB and + * ADDRSEL.WPROT are configured. + * + * \parRelated APIs:
+ * XMC_EBU_AddressSelectDisable() + */ +__STATIC_INLINE void XMC_EBU_AddressSelectEnable(XMC_EBU_t *const ebu, + uint32_t ebu_addr_select_en, + const uint32_t ebu_region_n) +{ + XMC_ASSERT("XMC_EBU_AddressSelectEnable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->ADDRSEL[ebu_region_n] |= ebu_addr_select_en; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu_addr_select_dis Choose between a memory region disable or an alternate + * region disable + * @param ebu_region_n A valid region number for which disable and protection + * settings configured + * @return None + * + * \parDescription:
+ * Controls the disable and protection settings of a region
+ * + * \par + * The function controls the disable and protection settings of a memory or alternate + * region. It configures the memory region disable, alternate region disable and the + * memory region write protect disable for write accesses. The bits ADDRSEL.REGENAB, + * ADDRSEL.ALTENAB and ADDRSEL.WPROT are configured. + * + * \parRelated APIs:
+ * XMC_EBU_AddressSelectEnable() + */ +__STATIC_INLINE void XMC_EBU_AddressSelectDisable(XMC_EBU_t *const ebu, + uint32_t ebu_addr_select_dis, + const uint32_t ebu_region_n) +{ + XMC_ASSERT("XMC_EBU_AddressSelectDisable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + ebu->ADDRSEL[ebu_region_n] &= ~ebu_addr_select_dis; +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu_buswcon_status Enumeration of type ::XMC_EBU_BUSWCON_SELECT_t, representing + * values for non-array access and device addressing modes. + * @param ebu_region_n A valid region number for which status pertaining to WRITE is required + * @return Status Status of non-array access and device addressing mode + * + * \parDescription:
+ * Gets WRITE specific status for a region
+ * + * \par + * The function gets status of the various WRITE specific settings for a region. Status for + * non-array access enable and device addressing mode are obtained. The status bits of the + * BUSWCON register are returned. + * + * \parRelated APIs:
+ * XMC_EBU_ConfigureRegion() + */ +__STATIC_INLINE uint32_t XMC_EBU_GetBusWriteConfStatus(XMC_EBU_t *const ebu, + const XMC_EBU_BUSWCON_SELECT_t ebu_buswcon_status, + const uint32_t ebu_region_n) +{ + XMC_ASSERT("XMC_EBU_GetBusWriteConfStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + return (ebu->BUS[ebu_region_n].WRCON & ebu_buswcon_status); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return Status SDRAM error or busy states + * + * \parDescription:
+ * Gets SDRAM error or busy states
+ * + * \par + * The function gets SDRAM read error, refresh error and busy states. The bit-fields of SDRSTAT + * indicate the various states. REFERR reflects a failed previous refresh request collision + * with a new request. SDRMBUSY indicates the status of power-up initialization sequence. It + * indicates if it is running or not running. SDERR indicates if the SDRAM controller has + * detected an error when returning the read data. + * + * \parRelated APIs:
+ * XMC_EBU_ConfigureSdram() + */ +__STATIC_INLINE uint32_t XMC_EBU_SdramGetStatus(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_SdramGetStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + return (uint32_t)(ebu->SDRSTAT); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param sdram_rfrsh_status Constant enum of type ::XMC_EBU_SDRAM_RFRSH_STATUS_t + * @return Status Status of self refresh entry and exit command issue + * + * \parDescription:
+ * Gets SDRAM refresh status
+ * + * \par + * The function gets SDRAM refresh status for self refresh entry/exit command successful issue. + * The bit-fields of SDRMREF indicate various states:
+ * SELFRENST reflects successful issue of self refresh entry command
+ * SELFREXST reflects successful issue of self refresh exit command
+ * + * \parRelated APIs:
+ * XMC_EBU_SdramResetSelfRefreshEntry(), XMC_EBU_SdramResetSelfRefreshExit() + */ +__STATIC_INLINE uint32_t XMC_EBU_SdramGetRefreshStatus(XMC_EBU_t *const ebu, + const XMC_EBU_SDRAM_RFRSH_STATUS_t sdram_rfrsh_status) +{ + XMC_ASSERT("XMC_EBU_SdramGetRefreshStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + return (uint32_t)(ebu->SDRMREF & sdram_rfrsh_status); +} + +/** + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @return bool Returns if the arbitration mode is selected or not + * + * \parDescription:
+ * Check if arbitration mode of EBU peripheral is selected + * + * \par + * The bit field ARBMODE of MODCON indicates the selected arbitration mode of the + * EBU. The follwing are the supported arbitration modes:
+ * 1) Arbiter Mode arbitration mode
+ * 2) Participant arbitration mode
+ * 3) Sole Master arbitration mode
+ * + * If any of the above modes are selected, the function returns "true". It returns + * false otherwise. + * + * \parRelated APIs:
+ * XMC_EBU_Init() \n\n\n + */ +__STATIC_INLINE bool XMC_EBU_IsBusAribitrationSelected(XMC_EBU_t *const ebu) +{ + XMC_ASSERT("XMC_EBU_IsBusAribitrationSelected: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + return (bool)(ebu->MODCON & EBU_MODCON_ARBMODE_Msk); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EBU) */ + +#endif /* XMC_EBU_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ecat.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ecat.h new file mode 100644 index 00000000..45f1ff4e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ecat.h @@ -0,0 +1,462 @@ + +/** + * @file xmc_ecat.h + * @date 2015-12-27 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-12-27: + * - Initial Version
+ * + * @endcond + */ + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup ECAT + * @brief EtherCAT Low level driver for XMC4800/XMC4300 series. + * + * EtherCAT is an Ethernet-based fieldbus system. + * The EtherCAT Slave Controller (ECAT) read the data addressed to them while the telegram passes through the device. + * An EtherCAT Slave Controller (ESC) takes care of the EtherCAT communication as an interface between the EtherCAT + * fieldbus and the slave application. EtherCAT uses standard IEEE 802.3 Ethernet frames, thus a standard network + * controller can be used and no special hardware is required on master side. EtherCAT has a reserved EtherType of + * 0x88A4 that distinguishes it from other Ethernet frames. Thus, EtherCAT can run in parallel to other Ethernet + * protocols. EtherCAT does not require the IP protocol, however it can be encapsulated in IP/UDP. The EtherCAT + * Slave Controller processes the frame in hardware. Thus, communication performance is independent from processor + * power. + * + * The XMC_ECAT low level driver provides functions to configure and initialize the ECAT hardware peripheral. + * For EHTERCAT stack integration, the necessary hardware accees layer APIs shall be explicitly implemented depending + * upon the stack provider. The XMC_ECAT lld layer provides only the hardware initialization functions for start up and + * basic functionalities. + * @{ + */ + +#ifndef XMC_ECAT_H +#define XMC_ECAT_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_common.h" + +#if defined (ECAT0) + +#include "xmc_ecat_map.h" + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + +/** + * ECAT status return values + */ +typedef enum XMC_ECAT_STATUS +{ + XMC_ECAT_STATUS_OK = 0U, /**< Driver accepted application request */ + XMC_ECAT_STATUS_BUSY = 1U, /**< Driver is busy and cannot handle request */ + XMC_ECAT_STATUS_ERROR = 2U /**< Driver could not fulfil application request */ +} XMC_ECAT_STATUS_t; + +/** + * EtherCAT event enumeration types + */ +typedef enum XMC_ECAT_EVENT +{ + XMC_ECAT_EVENT_AL_CONTROL = ECAT_AL_EVENT_MASK_AL_CE_MASK_Msk, /**< Application control event mask */ + XMC_ECAT_EVENT_DC_LATCH = ECAT_AL_EVENT_MASK_DC_LE_MASK_Msk, /**< Distributed Clock latch event mask */ + XMC_ECAT_EVENT_DC_SYNC0 = ECAT_AL_EVENT_MASK_ST_S0_MASK_Msk, /**< State of distributed clock sync-0 event mask */ + XMC_ECAT_EVENT_DC_SYNC1 = ECAT_AL_EVENT_MASK_ST_S1_MASK_Msk, /**< State of distributed clock sync-1 event mask */ + XMC_ECAT_EVENT_SM_ACTIVATION_REGISTER = ECAT_AL_EVENT_MASK_SM_A_MASK_Msk, /**< SyncManager activation register mask*/ + XMC_ECAT_EVENT_EEPROM = ECAT_AL_EVENT_MASK_EEP_E_MASK_Msk, /**< EEPROM Emulation event mask*/ + XMC_ECAT_EVENT_WATCHDOG = ECAT_AL_EVENT_MASK_WP_D_MASK_Msk, /**< WATCHDOG process data event mask*/ + XMC_ECAT_EVENT_SM0 = ECAT_AL_EVENT_MASK_SMI_0_MASK_Msk, /**< Sync Manager 0 event mask*/ + XMC_ECAT_EVENT_SM1 = ECAT_AL_EVENT_MASK_SMI_1_MASK_Msk, /**< Sync Manager 1 event mask*/ + XMC_ECAT_EVENT_SM2 = ECAT_AL_EVENT_MASK_SMI_2_MASK_Msk, /**< Sync Manager 2 event mask*/ + XMC_ECAT_EVENT_SM3 = ECAT_AL_EVENT_MASK_SMI_3_MASK_Msk, /**< Sync Manager 3 event mask*/ + XMC_ECAT_EVENT_SM4 = ECAT_AL_EVENT_MASK_SMI_4_MASK_Msk, /**< Sync Manager 4 event mask*/ + XMC_ECAT_EVENT_SM5 = ECAT_AL_EVENT_MASK_SMI_5_MASK_Msk, /**< Sync Manager 5 event mask*/ + XMC_ECAT_EVENT_SM6 = ECAT_AL_EVENT_MASK_SMI_6_MASK_Msk, /**< Sync Manager 6 event mask*/ + XMC_ECAT_EVENT_SM7 = ECAT_AL_EVENT_MASK_SMI_7_MASK_Msk /**< Sync Manager 7 event mask*/ +} XMC_ECAT_EVENT_t; + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ + +/* Anonymous structure/union guard start */ +#if defined (__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined (__TASKING__) +#pragma warning 586 +#endif + +/** + * ECAT port control data structure + */ +typedef struct XMC_ECAT_PORT_CTRL +{ + union + { + struct + { + uint32_t enable_rstreq: 1; /**< Master can trigger a reset of the XMC4700 / XMC4800 (::bool) */ + uint32_t: 7; /**< Reserved bits */ + uint32_t latch_input0: 2; /**< Latch input 0 selection (::XMC_ECAT_PORT_LATCHIN0_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t latch_input1: 2; /**< Latch input 1 selection (::XMC_ECAT_PORT_LATCHIN1_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t phyaddr_offset: 5; /**< Ethernet PHY address offset, address of port 0 */ + uint32_t: 1; /**< Reserved bits */ + uint32_t mdio: 2; /**< Bidirectional, push-pull management data I/O line (::XMC_ETH_MAC_PORT_CTRL_MDIO_t) */ + uint32_t: 8; /**< Reserved bits */ + }; + + uint32_t raw; + } common; + + union + { + struct + { + uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ECAT_PORT0_CTRL_RXD0_t) */ + uint32_t rxd1: 2; /**< Receive data bit 1 (::XMC_ECAT_PORT0_CTRL_RXD1_t) */ + uint32_t rxd2: 2; /**< Receive data bit 2 (::XMC_ECAT_PORT0_CTRL_RXD2_t) */ + uint32_t rxd3: 2; /**< Receive data bit 3 (::XMC_ECAT_PORT0_CTRL_RXD3_t) */ + uint32_t rx_err: 2; /**< RX Error (::XMC_ECAT_PORT0_CTRL_RX_ERR_t) */ + uint32_t rx_dv: 2; /**< RX Data valid (::XMC_ECAT_PORT0_CTRL_RX_DV_t) */ + uint32_t rx_clk: 2; /**< RX Clock (::XMC_ECAT_PORT0_CTRL_RX_CLK_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t link: 2; /**< Link status (::XMC_ECAT_PORT0_CTRL_LINK_t) */ + uint32_t: 10; /**< Reserved bits */ + uint32_t tx_clk: 2; /**< TX Clock (::XMC_ECAT_PORT0_CTRL_TX_CLK_t) */ + uint32_t tx_shift: 2; /**< TX signal delay (::XMC_ECAT_PORT0_CTRL_TX_SHIFT_t) */ + }; + + uint32_t raw; + } port0; + + union + { + struct + { + uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ECAT_PORT_CTRL_RXD0_t) */ + uint32_t rxd1: 2; /**< Receive data bit 1 (::XMC_ECAT_PORT_CTRL_RXD1_t) */ + uint32_t rxd2: 2; /**< Receive data bit 2 (::XMC_ECAT_PORT_CTRL_RXD2_t) */ + uint32_t rxd3: 2; /**< Receive data bit 3 (::XMC_ECAT_PORT_CTRL_RXD3_t) */ + uint32_t rx_err: 2; /**< RX Error (::XMC_ECAT_PORT_CTRL_RX_ERR_t) */ + uint32_t rx_dv: 2; /**< RX Data valid (::XMC_ECAT_PORT_CTRL_RX_DV_t) */ + uint32_t rx_clk: 2; /**< RX Clock (::XMC_ECAT_PORT_CTRL_RX_CLK_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t link: 2; /**< Link status (::XMC_ECAT_PORT_CTRL_LINK_t) */ + uint32_t: 10; /**< Reserved bits */ + uint32_t tx_clk: 2; /**< TX Clock (::XMC_ECAT_PORT_CTRL_TX_CLK_t) */ + uint32_t tx_shift: 2; /**< TX signal delay (::XMC_ECAT_PORT1_CTRL_TX_SHIFT_t) */ + }; + + uint32_t raw; + } port1; + +} XMC_ECAT_PORT_CTRL_t; + +/** + * ECAT EEPROM configuration area data structure + */ +typedef union XMC_ECAT_CONFIG +{ + struct + { + uint32_t : 8; + + uint32_t : 2; + uint32_t enable_dc_sync_out : 1; + uint32_t enable_dc_latch_in : 1; + uint32_t enable_enhanced_link_p0 : 1; + uint32_t enable_enhanced_link_p1 : 1; + uint32_t : 2; + + uint32_t : 16; + + uint16_t sync_pulse_length; /**< Initialization value for Pulse Length of SYNC Signals register*/ + + uint32_t : 16; + + uint16_t station_alias; /**< Initialization value for Configured Station Alias Address register */ + + uint16_t : 16; + + uint16_t : 16; + + uint16_t checksum; + }; + + uint32_t dword[4]; /**< Four 32 bit double word equivalent to 8 16 bit configuration area word. */ +} XMC_ECAT_CONFIG_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) +#pragma pop +#elif defined (__TASKING__) +#pragma warning restore +#endif + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param config XMC_ECAT_CONFIG_t + * @return XMC_ECAT_STATUS_t ECAT Initialization status + * + * \parDescription:
+ * Initialize the Ethernet MAC peripheral
+ * + * \par + * The function sets the link speed, applies the duplex mode, sets auto-negotiation + * and loop-back settings. + */ +void XMC_ECAT_Init(XMC_ECAT_CONFIG_t *const config); + +/** + * @param None + * @return None + * + * \parDescription:
+ * Enable the EtherCAT peripheral
+ * + * \par + * The function de-asserts the peripheral reset. + */ +void XMC_ECAT_Enable(void); + +/** + * @param None + * @return None + * + * \parDescription:
+ * Disable the EtherCAT peripheral
+ * + * \par + * The function asserts the peripheral reset. + */ +void XMC_ECAT_Disable(void); + +/** + * @param phy_addr PHY address + * @param reg_addr Register address + * @param data The destination to which the read data needs to be copied to. + * + * @return XMC_ECAT_STATUS_t EtherCAT Read PHY API return status + * + * \parDescription:
+ * Read a PHY register
+ * + * \par + * The function reads a PHY register. It essentially polls busy bit during max + * PHY_TIMEOUT time and reads the information into 'data' when not busy. + */ +XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); + +/** + * @param phy_addr PHY address + * @param reg_addr Register address + * @param data The data to write + * @return XMC_ECAT_STATUS_t EtherCAT Write PHY API return status + * + * \parDescription:
+ * Write a PHY register
+ * + * \par + * The function reads a PHY register. It essentially writes the data and polls + * the busy bit until it is no longer busy. + */ +XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t data); + +/** + * @param port_ctrl Port control configuration + * @return None + * + * \parDescription:
+ * Set port control configuration
+ * + * \par + * The function sets the port control by writing the configuration into the ECAT CON register. + * + */ +__STATIC_INLINE void XMC_ECAT_SetPortControl(const XMC_ECAT_PORT_CTRL_t port_ctrl) +{ + ECAT0_CON->CON = (uint32_t)port_ctrl.common.raw; + ECAT0_CON->CONP0 = (uint32_t)port_ctrl.port0.raw; + ECAT0_CON->CONP1 = (uint32_t)port_ctrl.port1.raw; +} + +/** + * @param event Single or logically OR'd events specified in the enum type @refXMC_ECAT_EVENT_t + * @return None + * + * \parDescription:
+ * Enable ECAT event(s)
+ * + * \par + * The function can be used to enable ECAT event(s). + */ +void XMC_ECAT_EnableEvent(uint32_t event); + +/** + * @param event Single or logically OR'd events specified in the enum type @refXMC_ECAT_EVENT_t + * @return None + * + * \parDescription:
+ * Disable an ECAT event(s)
+ * + * \par + * The function can be used to disable ECAT event(s). + */ +void XMC_ECAT_DisableEvent(uint32_t event); + +/** + * @param None + * @return uint32_t Event status + * + * \parDescription:
+ * Get event status
+ * + * \par + * The function returns the ECAT status and interrupt status as a single word. The user + * can then check the status of the events by using an appropriate mask. + */ +uint32_t XMC_ECAT_GetEventStatus(void); + + +/** + * @param channel SyncManager channel number. + * @return None + * + * \parDescription:
+ * Disables selected SyncManager channel
+ * + * \par + * Sets bit 0 of the corresponding 0x807 register. + */ +void XMC_ECAT_DisableSyncManChannel(const uint8_t channel); + +/** + * @param channel SyncManager channel number. + * @return None + * + * \parDescription:
+ * Enables selected SyncManager channel
+ * + * \par + * Resets bit 0 of the corresponding 0x807 register. + */ +void XMC_ECAT_EnableSyncManChannel(const uint8_t channel); + +/** + * @param None + * @return uint16_t Content of register 0x220-0x221 + * + * \parDescription:
+ * Get content of AL event register
+ * + * \par + * Get the first two bytes of the AL Event register (0x220-0x221). + */ +__STATIC_INLINE uint16_t XMC_ECAT_GetALEventRegister(void) +{ + return ((uint16_t)ECAT0->AL_EVENT_REQ); +} + +/** + * @param None + * @return uint16_t Content of register 0x220-0x221 + * + * \parDescription:
+ * Get content of AL event register
+ * + * \par + * Get the first two bytes of the AL Event register (0x220-0x221). + */ +__STATIC_INLINE uint16_t XMC_ECAT_GetALEventMask(void) +{ + return ((uint16_t)ECAT0->AL_EVENT_MASK); +} + +/** + * @param intMask Interrupt mask (disabled interrupt shall be zero) + * @return None + * + * \parDescription:
+ * Sets application event mask register
+ * + * \par + * Performs a logical OR with the AL Event Mask register (0x0204 : 0x0205). + */ +__STATIC_INLINE void XMC_ECAT_SetALEventMask(uint16_t intMask) +{ + ECAT0->AL_EVENT_MASK |= (uint32_t)(intMask); +} + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (ECAT) */ + +#endif /* XMC_ECAT_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ecat_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ecat_map.h new file mode 100644 index 00000000..6053e7ba --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ecat_map.h @@ -0,0 +1,287 @@ +/** + * @file xmc_ecat_map.h + * @date 2016-07-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-09-09: + * - Initial + * + * 2015-07-20: + * - Added XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 and XMC_ECAT_PORT_CTRL_LATCHIN0_P9_1 + * + * @endcond + */ + +#ifndef XMC_ECAT_MAP_H +#define XMC_ECAT_MAP_H + +/** + * ECAT PORT 0 receive data 0 line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RXD0 +{ + XMC_ECAT_PORT0_CTRL_RXD0_P1_4 = 0U, /**< RXD0A receive data line */ + XMC_ECAT_PORT0_CTRL_RXD0_P5_0 = 1U, /**< RXD0B receive data line */ + XMC_ECAT_PORT0_CTRL_RXD0_P7_4 = 2U, /**< RXD0C receive data line */ +} XMC_ECAT_PORT0_CTRL_RXD0_t; + +/** + * ECAT PORT 0 receive data 1 line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RXD1 +{ + XMC_ECAT_PORT0_CTRL_RXD1_P1_5 = 0U, /**< RXD1A receive data line */ + XMC_ECAT_PORT0_CTRL_RXD1_P5_1 = 1U, /**< RXD1B receive data line */ + XMC_ECAT_PORT0_CTRL_RXD1_P7_5 = 2U, /**< RXD1C receive data line */ +} XMC_ECAT_PORT0_CTRL_RXD1_t; + +/** + * ECAT PORT 0 receive data 2 line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RXD2 +{ + XMC_ECAT_PORT0_CTRL_RXD2_P1_10 = 0U, /**< RXD2A receive data line */ + XMC_ECAT_PORT0_CTRL_RXD2_P5_2 = 1U, /**< RXD2B receive data line */ + XMC_ECAT_PORT0_CTRL_RXD2_P7_6 = 2U /**< RXD2C receive data line */ +} XMC_ECAT_PORT0_CTRL_RXD2_t; + +/** + * ECAT PORT 0 receive data 3 line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RXD3 +{ + XMC_ECAT_PORT0_CTRL_RXD3_P1_11 = 0U, /**< RXD3A Receive data line */ + XMC_ECAT_PORT0_CTRL_RXD3_P5_7 = 1U, /**< RXD3B Receive data line */ + XMC_ECAT_PORT0_CTRL_RXD3_P7_7 = 2U /**< RXD3C Receive data line */ +} XMC_ECAT_PORT0_CTRL_RXD3_t; + +/** + * ECAT PORT 0 receive error line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RX_ERR +{ + XMC_ECAT_PORT0_CTRL_RX_ERR_P4_0 = 0U, /**< RX_ERRA Receive error line */ + XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6 = 1U, /**< RX_ERRB Receive error line */ + XMC_ECAT_PORT0_CTRL_RX_ERR_P7_9 = 2U /**< RX_ERRC Receive error line */ +} XMC_ECAT_PORT0_CTRL_RX_ERR_t; + +/** + * ECAT PORT 0 receive clock line + */ +typedef enum XMC_ECAT_PORT0_CTRL_RX_CLK +{ + XMC_ECAT_PORT0_CTRL_RX_CLK_P1_1 = 0U, /**< RX_CLKA Recevive clock */ + XMC_ECAT_PORT0_CTRL_RX_CLK_P5_4 = 1U, /**< RX_CLKB Recevive clock */ + XMC_ECAT_PORT0_CTRL_RX_CLK_P7_10 = 2U, /**< RX_CLKC Recevive clock */ +} XMC_ECAT_PORT0_CTRL_RX_CLK_t; + +/** + * ECAT PORT 0 data valid + */ +typedef enum XMC_ECAT_PORT0_CTRL_RX_DV +{ + XMC_ECAT_PORT0_CTRL_RX_DV_P1_9 = 0U, /**< RX_DVA Receive data valid */ + XMC_ECAT_PORT0_CTRL_RX_DV_P5_6 = 1U, /**< RX_DVB Receive data valid */ + XMC_ECAT_PORT0_CTRL_RX_DV_P7_11 = 2U, /**< RX_DVC Receive data valid */ +} XMC_ECAT_PORT0_CTRL_RX_DV_t; + +/** + * ECAT PORT 0 link status + */ +typedef enum XMC_ECAT_PORT0_CTRL_LINK +{ + XMC_ECAT_PORT0_CTRL_LINK_P4_1 = 0U, /**< LINKA Link status */ + XMC_ECAT_PORT0_CTRL_LINK_P1_15 = 1U, /**< LINKB Link status */ + XMC_ECAT_PORT0_CTRL_LINK_P9_10 = 2U, /**< LINKC Link status */ +} XMC_ECAT_PORT0_CTRL_LINK_t; + +/** + * ECAT PORT 0 transmit clock + */ +typedef enum XMC_ECAT_PORT0_CTRL_TX_CLK +{ + XMC_ECAT_PORT0_CTRL_TX_CLK_P1_0 = 0U, /**< TX_CLKA transmit clock */ + XMC_ECAT_PORT0_CTRL_TX_CLK_P5_5 = 1U, /**< TX_CLKB transmit clock */ + XMC_ECAT_PORT0_CTRL_TX_CLK_P9_1 = 2U, /**< TX_CLKC transmit clock */ +} XMC_ECAT_PORT0_CTRL_TX_CLK_t; + +/** + * ECAT PORT 1 receive data 0 line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RXD0 +{ + XMC_ECAT_PORT1_CTRL_RXD0_P0_11 = 0U, /**< RXD0A receive data line */ + XMC_ECAT_PORT1_CTRL_RXD0_P14_7 = 1U, /**< RXD0B receive data line */ + XMC_ECAT_PORT1_CTRL_RXD0_P8_4 = 2U, /**< RXD0C receive data line */ +} XMC_ECAT_PORT1_CTRL_RXD0_t; + +/** + * ECAT PORT 1 receive data 1 line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RXD1 +{ + XMC_ECAT_PORT1_CTRL_RXD1_P0_6 = 0U, /**< RXD1A receive data line */ + XMC_ECAT_PORT1_CTRL_RXD1_P14_12 = 1U, /**< RXD1B receive data line */ + XMC_ECAT_PORT1_CTRL_RXD1_P8_5 = 2U, /**< RXD1C receive data line */ +} XMC_ECAT_PORT1_CTRL_RXD1_t; + +/** + * ECAT PORT 1 receive data 2 line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RXD2 +{ + XMC_ECAT_PORT1_CTRL_RXD2_P0_5 = 0U, /**< RXD2A receive data line */ + XMC_ECAT_PORT1_CTRL_RXD2_P14_13 = 1U, /**< RXD2B receive data line */ + XMC_ECAT_PORT1_CTRL_RXD2_P8_6 = 2U /**< RXD2C receive data line */ +} XMC_ECAT_PORT1_CTRL_RXD2_t; + +/** + * ECAT PORT 1 receive data 3 line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RXD3 +{ + XMC_ECAT_PORT1_CTRL_RXD3_P0_4 = 0U, /**< RXD3A Receive data line */ + XMC_ECAT_PORT1_CTRL_RXD3_P14_14 = 1U, /**< RXD3B Receive data line */ + XMC_ECAT_PORT1_CTRL_RXD3_P8_7 = 2U /**< RXD3C Receive data line */ +} XMC_ECAT_PORT1_CTRL_RXD3_t; + +/** + * ECAT PORT 1 receive error line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RX_ERR +{ + XMC_ECAT_PORT1_CTRL_RX_ERR_P3_5 = 0U, /**< RX_ERRA Receive error line */ + XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2 = 1U, /**< RX_ERRB Receive error line */ + XMC_ECAT_PORT1_CTRL_RX_ERR_P8_9 = 2U /**< RX_ERRC Receive error line */ +} XMC_ECAT_PORT1_CTRL_RX_ERR_t; + +/** + * ECAT PORT 1 receive clock line + */ +typedef enum XMC_ECAT_PORT1_CTRL_RX_CLK +{ + XMC_ECAT_PORT1_CTRL_RX_CLK_P0_1 = 0U, /**< RX_CLKA Recevive clock */ + XMC_ECAT_PORT1_CTRL_RX_CLK_P14_6 = 1U, /**< RX_CLKB Recevive clock */ + XMC_ECAT_PORT1_CTRL_RX_CLK_P8_10 = 2U, /**< RX_CLKC Recevive clock */ +} XMC_ECAT_PORT1_CTRL_RX_CLK_t; + +/** + * ECAT PORT 1 data valid + */ +typedef enum XMC_ECAT_PORT1_CTRL_RX_DV +{ + XMC_ECAT_PORT1_CTRL_RX_DV_P0_9 = 0U, /**< RX_DVA Receive data valid */ + XMC_ECAT_PORT1_CTRL_RX_DV_P14_15 = 1U, /**< RX_DVB Receive data valid */ + XMC_ECAT_PORT1_CTRL_RX_DV_P8_11 = 2U, /**< RX_DVC Receive data valid */ +} XMC_ECAT_PORT1_CTRL_RX_DV_t; + +/** + * ECAT PORT 0 link status + */ +typedef enum XMC_ECAT_PORT1_CTRL_LINK +{ + XMC_ECAT_PORT1_CTRL_LINK_P3_4 = 0U, /**< LINKA Link status */ + XMC_ECAT_PORT1_CTRL_LINK_P15_3 = 1U, /**< LINKB Link status */ + XMC_ECAT_PORT1_CTRL_LINK_P9_11 = 2U, /**< LINKC Link status */ +} XMC_ECAT_PORT1_CTRL_LINK_t; + +/** + * ECAT PORT 1 transmit clock + */ +typedef enum XMC_ECAT_PORT1_CTRL_TX_CLK +{ + XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10 = 0U, /**< TX_CLKA transmit clock */ + XMC_ECAT_PORT1_CTRL_TX_CLK_P5_9 = 1U, /**< TX_CLKB transmit clock */ + XMC_ECAT_PORT1_CTRL_TX_CLK_P9_0 = 2U, /**< TX_CLKC transmit clock */ +} XMC_ECAT_PORT1_CTRL_TX_CLK_t; + +/** + * ECAT management data I/O + */ +typedef enum XMC_ECAT_PORT_CTRL_MDIO +{ + XMC_ECAT_PORT_CTRL_MDIO_P0_12 = 0U, /**< MDIOA management data I/O */ + XMC_ECAT_PORT_CTRL_MDIO_P4_2 = 1U, /**< MDIOB management data I/O */ + XMC_ECAT_PORT_CTRL_MDIO_P9_7 = 2U /**< MDIOC management data I/O */ +} XMC_ECAT_PORT_CTRL_MDIO_t; + +/** + * ECAT latch 0 + */ +typedef enum XMC_ECAT_PORT_CTRL_LATCHIN0 +{ + XMC_ECAT_PORT_CTRL_LATCHIN0_P14_5 = 0U, /**< LATCH0A line */ + XMC_ECAT_PORT_CTRL_LATCHIN0_9_0 = 1U, /**< LATCH0B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 */ + XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 = 1U, /**< LATCH0B line */ + XMC_ECAT_PORT_CTRL_LATCHIN0_ERU0_PDOUT0 = 2U, /**< LATCH0C line */ + XMC_ECAT_PORT_CTRL_LATCHIN0_ERU1_PDOUT0 = 3U, /**< LATCH0D line */ +} XMC_ECAT_PORT_CTRL_LATCHIN0_t; + +/** + * ECAT latch 1 + */ +typedef enum XMC_ECAT_PORT_CTRL_LATCHIN1 +{ + XMC_ECAT_PORT_CTRL_LATCHIN1_P14_4 = 0U, /**< LATCH1 A line */ + XMC_ECAT_PORT_CTRL_LATCHIN1_9_1 = 1U, /**< LATCH1 B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1 */ + XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1 = 1U, /**< LATCH1 B line */ + XMC_ECAT_PORT_CTRL_LATCHIN1_ERU0_PDOUT1 = 2U, /**< LATCH1C line */ + XMC_ECAT_PORT_CTRL_LATCHIN1_ERU1_PDOUT1 = 3U, /**< LATCH1D line */ +} XMC_ECAT_PORT_CTRL_LATCHIN1_t; + +/** + * ECAT Port 0 Manual TX Shift configuration + */ +typedef enum XMC_ECAT_PORT0_CTRL_TX_SHIFT +{ + XMC_ECAT_PORT0_CTRL_TX_SHIFT_0NS = 0U, /**< ECAT Port 0 Manual TX Shift compensation 0 nanoseconds */ + XMC_ECAT_PORT0_CTRL_TX_SHIFT_10NS = 1U, /**< ECAT Port 0 Manual TX Shift compensation 10 nanoseconds */ + XMC_ECAT_PORT0_CTRL_TX_SHIFT_20NS = 2U, /**< ECAT Port 0 Manual TX Shift compensation 20 nanoseconds */ + XMC_ECAT_PORT0_CTRL_TX_SHIFT_30NS = 3U /**< ECAT Port 0 Manual TX Shift compensation 30 nanoseconds */ +} XMC_ECAT_PORT0_CTRL_TX_SHIFT_t; + +/** + * ECAT Port 1 Manual TX Shift configuration + */ +typedef enum XMC_ECAT_PORT1_CTRL_TX_SHIFT +{ + XMC_ECAT_PORT1_CTRL_TX_SHIFT_0NS = 0U, /**< ECAT Port 0 Manual TX Shift compensation 0 nanoseconds */ + XMC_ECAT_PORT1_CTRL_TX_SHIFT_10NS = 1U, /**< ECAT Port 0 Manual TX Shift compensation 10 nanoseconds */ + XMC_ECAT_PORT1_CTRL_TX_SHIFT_20NS = 2U, /**< ECAT Port 0 Manual TX Shift compensation 20 nanoseconds */ + XMC_ECAT_PORT1_CTRL_TX_SHIFT_30NS = 3U /**< ECAT Port 0 Manual TX Shift compensation 30 nanoseconds */ +} XMC_ECAT_PORT1_CTRL_TX_SHIFT_t; + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eru.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eru.h new file mode 100644 index 00000000..e5c04096 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eru.h @@ -0,0 +1,884 @@ +/** + * @file xmc_eru.h + * @date 2016-03-10 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Documentation updates
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-10-07: + * - Doc update for XMC_ERU_ETL_CONFIG_t field
+ * + * 2016-03-10: + * - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation.
+ * + * @endcond + */ + +#ifndef XMC_ERU_H +#define XMC_ERU_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_common.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup ERU + * @brief Event Request Unit (ERU) driver for the XMC microcontroller family. + * + * The Event Request Unit (ERU) is a versatile multiple input event detection and processing unit. + * The ERU module can be used to expand the P-to-P connections of the device: ports-to-peripherals, + * peripherals-to-peripherals and ports-to-ports. It also offers configurable logic, that allows the generation of + * triggers, pattern detection and real-time signal monitoring. + * + * @image html "eru_overview.png" + * + * The driver is divided into two sections: + * \par Event trigger logic (ERU_ETL): + * This section of the LLD provides the configuration structure XMC_ERU_ETL_CONFIG_t and the initialization function + * XMC_ERU_ETL_Init().\n + * It can be used to: + * -# Select one out of two inputs (A and B). For each of these two inputs, a vector of 4 possible signals is available. + * (XMC_ERU_ETL_SetSource()) + * -# Logically combine the two input signals to a common trigger. (XMC_ERU_ETL_SetSource()) + * -# Define the transition (edge selection, or by software) that leads to a trigger event and can also store this status. + * (XMC_ERU_ETL_SetEdgeDetection() and XMC_ERU_ETL_SetStatusFlag()) + * -# Distribute the events and status flags to the output channels. (XMC_ERU_ETL_EnableOutputTrigger()) + * + * \par Output gating unit (ERU_OGU): + * This section of the LLD provides the provides the configuration structure XMC_ERU_OGU_CONFIG_t and the initialization + * function XMC_ERU_ETL_OGU_Init(). + * It can be used to: + * -# Combine the trigger events and status information and gates the output depending on a gating signal. + * (XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_DisablePeripheralTrigger(), XMC_ERU_OGU_SetServiceRequestMode()) + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#if defined(ERU0) +#define XMC_ERU0 ((XMC_ERU_t *) ERU0_BASE) /**< ERU module 0 */ +#endif + +#if defined(ERU1) +#define XMC_ERU1 ((XMC_ERU_t *) ERU1_BASE) /**< ERU module 1, only available in XMC4 family */ +#endif + +#if UC_FAMILY == XMC1 + #include "xmc1_eru_map.h" +#endif + +#if UC_FAMILY == XMC4 + #include "xmc4_eru_map.h" +#endif + +#if defined(XMC_ERU0) && defined(XMC_ERU1) +#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0) | ((PTR)== XMC_ERU1)) +#elif defined(XMC_ERU0) +#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0)) +#elif defined(XMC_ERU1) +#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0)) +#endif + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/** + * Defines input signal for path A of ERSx(Event request source, x = [0 to 3]) unit. + * @image html "eru_input_a.png" "ETLx Input A selection" +*/ +typedef enum XMC_ERU_ETL_INPUT_A +{ + XMC_ERU_ETL_INPUT_A0 = 0x0U, /**< input A0 is selected */ + XMC_ERU_ETL_INPUT_A1 = 0x1U, /**< input A1 is selected */ + XMC_ERU_ETL_INPUT_A2 = 0x2U, /**< input A2 is selected */ + XMC_ERU_ETL_INPUT_A3 = 0x3U /**< input A3 is selected */ +} XMC_ERU_ETL_INPUT_A_t; + +/** + * Defines input signal for path B of ERSx(Event request source, x = [0 to 3]) unit. + * @image html "eru_input_b.png" "ETLx Input B selection" + */ +typedef enum XMC_ERU_ETL_INPUT_B +{ + XMC_ERU_ETL_INPUT_B0 = 0x0U, /**< input B0 is selected */ + XMC_ERU_ETL_INPUT_B1 = 0x1U, /**< input B1 is selected */ + XMC_ERU_ETL_INPUT_B2 = 0x2U, /**< input B2 is selected */ + XMC_ERU_ETL_INPUT_B3 = 0x3U /**< input B3 is selected */ +} XMC_ERU_ETL_INPUT_B_t; + +/** + * Defines input path combination along with polarity for event generation by ERSx(Event request source) unit to + * ETLx(Event trigger logic),x = [0 to 3] unit. + * @image html "eru_input_trigger.png" "ETLx input trigger signal generation" + */ +typedef enum XMC_ERU_ETL_SOURCE +{ + XMC_ERU_ETL_SOURCE_A = 0x0U, /**< select (A) path as a event source */ + XMC_ERU_ETL_SOURCE_B = 0x1U, /**< select (B) path as a event source */ + XMC_ERU_ETL_SOURCE_A_OR_B = 0x2U, /**< select (A OR B) path as a event source */ + XMC_ERU_ETL_SOURCE_A_AND_B = 0x3U, /**< select (A AND B) path as a event source */ + XMC_ERU_ETL_SOURCE_NOT_A = 0x4U, /**< select (inverted A) path as a event source */ + XMC_ERU_ETL_SOURCE_NOT_A_OR_B = 0x6U, /**< select (inverted A OR B) path as a event source */ + XMC_ERU_ETL_SOURCE_NOT_A_AND_B = 0x7U, /**< select (inverted A AND B) path as a event source */ + XMC_ERU_ETL_SOURCE_NOT_B = 0x9U, /**< select (inverted B) path as a event source */ + XMC_ERU_ETL_SOURCE_A_OR_NOT_B = 0xaU, /**< select (A OR inverted B) path as a event source */ + XMC_ERU_ETL_SOURCE_A_AND_NOT_B = 0xbU, /**< select (A AND inverted B) path as a event source */ + XMC_ERU_ETL_SOURCE_NOT_A_OR_NOT_B = 0xeU, /**< select (inverted A OR inverted B) path as a event + source */ + XMC_ERU_ETL_SOURCE_NOT_A_AND_NOT_B = 0xfU /**< select (inverted A AND inverted B) path as a event + source */ +} XMC_ERU_ETL_SOURCE_t; + +/** + * Defines trigger edge for the event generation by ETLx (Event Trigger Logic, x = [0 to 3]) unit, by getting the signal + * from ERSx(Event request source, x = [0 to 3]) unit. + */ +typedef enum XMC_ERU_ETL_EDGE_DETECTION +{ + XMC_ERU_ETL_EDGE_DETECTION_DISABLED = 0U, /**< no event enabled */ + XMC_ERU_ETL_EDGE_DETECTION_RISING = 1U, /**< detection of rising edge generates the event */ + XMC_ERU_ETL_EDGE_DETECTION_FALLING = 2U, /**< detection of falling edge generates the event */ + XMC_ERU_ETL_EDGE_DETECTION_BOTH = 3U /**< detection of either edges generates the event */ +} XMC_ERU_ETL_EDGE_DETECTION_t; + +/** + * Defines Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by + * ETLx(Event Trigger Logic, x = [0 to 3]) unit. + * @note Generation of output trigger pulse need to be enabled @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t + * @image html "eru_connection_matrix.png" "ERU_ETL ERU_OGU Connection matrix" + */ +typedef enum XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL +{ + XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0 = 0U, /**< Event from input ETLx triggers output OGU0 */ + XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL1 = 1U, /**< Event from input ETLx triggers output OGU1 */ + XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL2 = 2U, /**< Event from input ETLx triggers output OGU2 */ + XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL3 = 3U, /**< Event from input ETLx triggers output OGU3 */ +} XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t; + +/** + * Defines generation of the trigger pulse by ETLx(Event Trigger Logic, x = [0 to 3]) unit. + * Use type XMC_ERU_ETL_OUTPUT_TRIGGER_t for this enum. + */ +typedef enum XMC_ERU_ETL_OUTPUT_TRIGGER +{ + XMC_ERU_ETL_OUTPUT_TRIGGER_DISABLED = 0U, /**< trigger pulse generation disabled */ + XMC_ERU_ETL_OUTPUT_TRIGGER_ENABLED = 1U /**< trigger pulse generation enabled */ +} XMC_ERU_ETL_OUTPUT_TRIGGER_t; + +/** + * Defines status flag reset mode generated by ETLx(Event Trigger Logic, x = [0 to 3]) unit. + * Use type XMC_ERU_ETL_STATUS_FLAG_MODE_t for this enum. + */ +typedef enum XMC_ERU_ETL_STATUS_FLAG_MODE +{ + XMC_ERU_ETL_STATUS_FLAG_MODE_SWCTRL = 0U, /**< Status flag is in sticky mode. Retain the same state until + cleared by software. In case of pattern match this mode + is used. */ + XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL = 1U /**< Status flag is in non-sticky mode. Automatically cleared by + the opposite edge detection.\n + eg. if positive edge is selected as trigger event, for the + negative edge event the status flag is cleared. */ +} XMC_ERU_ETL_STATUS_FLAG_MODE_t; + +/** + * Defines pattern detection feature to be enabled or not in OGUy(Output gating unit, y = [0 to 3]). + * + */ +typedef enum XMC_ERU_OGU_PATTERN_DETECTION +{ + XMC_ERU_OGU_PATTERN_DETECTION_DISABLED = 0U, /**< Pattern match is disabled */ + XMC_ERU_OGU_PATTERN_DETECTION_ENABLED = 1U /**< Pattern match is enabled, the selected status flags of + ETLx(Event Trigger Logic, x = [0 to 3]) unit, are + used in pattern detection. */ +} XMC_ERU_OGU_PATTERN_DETECTION_t; + +/** + * Defines the inputs for Pattern detection. The configured status flag signal from the ETLx(Event Trigger Logic, + * x = [0 to 3]) unit indicates the pattern to be detected. + */ +typedef enum XMC_ERU_OGU_PATTERN_DETECTION_INPUT +{ + XMC_ERU_OGU_PATTERN_DETECTION_INPUT0 = 1U, /**< Status flag ETL0, participating in pattern match */ + XMC_ERU_OGU_PATTERN_DETECTION_INPUT1 = 2U, /**< Status flag ETL1, participating in pattern match */ + XMC_ERU_OGU_PATTERN_DETECTION_INPUT2 = 4U, /**< Status flag ETL0, participating in pattern match */ + XMC_ERU_OGU_PATTERN_DETECTION_INPUT3 = 8U /**< Status flag ETL0, participating in pattern match */ +} XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t; + +/** + * Defines peripheral trigger signal for event generation. Based on the selected peripheral for event generation, + * the trigger signal is mapped. + */ +typedef enum XMC_ERU_OGU_PERIPHERAL_TRIGGER +{ + XMC_ERU_OGU_PERIPHERAL_TRIGGER1 = 1U, /**< OGUy1 signal is mapped for event generation */ + XMC_ERU_OGU_PERIPHERAL_TRIGGER2 = 2U, /**< OGUy2 signal is mapped for event generation */ + XMC_ERU_OGU_PERIPHERAL_TRIGGER3 = 3U /**< OGUy3 signal is mapped for event generation */ +} XMC_ERU_OGU_PERIPHERAL_TRIGGER_t; + +/** + * Defines the gating scheme for service request generation. In later stage of the OGUy(Output gating unit, + * y = [0 to 3]) based on the gating scheme selected ERU_GOUTy(gated output signal) output is defined. + * @image html "interrupt_gating_signal.png" "Interrupt gating signal" + */ +typedef enum XMC_ERU_OGU_SERVICE_REQUEST +{ + XMC_ERU_OGU_SERVICE_REQUEST_DISABLED = 0U, /**< Service request blocked, ERUx_GOUTy = 0 */ + XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER = 1U, /**< Service request generated enabled, ERUx_GOUTy = 1 */ + XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH = 2U, /**< Service request generated on trigger + event and input pattern match, + ERUx_GOUTy = ~pattern matching result*/ + XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH = 3U/**< Service request generated on trigger + event and input pattern mismatch, + ERUx_GOUTy = pattern matching result*/ +} XMC_ERU_OGU_SERVICE_REQUEST_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * ERU module + */ +typedef struct { + union { + __IO uint32_t EXISEL; + + struct { + __IO uint32_t EXS0A : 2; + __IO uint32_t EXS0B : 2; + __IO uint32_t EXS1A : 2; + __IO uint32_t EXS1B : 2; + __IO uint32_t EXS2A : 2; + __IO uint32_t EXS2B : 2; + __IO uint32_t EXS3A : 2; + __IO uint32_t EXS3B : 2; + } EXISEL_b; + }; + __I uint32_t RESERVED0[3]; + + union { + __IO uint32_t EXICON[4]; + + struct { + __IO uint32_t PE : 1; + __IO uint32_t LD : 1; + __IO uint32_t ED : 2; + __IO uint32_t OCS : 3; + __IO uint32_t FL : 1; + __IO uint32_t SS : 4; + __I uint32_t RESERVED1 : 20; + } EXICON_b[4]; + }; + + union { + __IO uint32_t EXOCON[4]; + + struct { + __IO uint32_t ISS : 2; + __IO uint32_t GEEN : 1; + __I uint32_t PDR : 1; + __IO uint32_t GP : 2; + uint32_t : 6; + __IO uint32_t IPEN : 4; + __I uint32_t RESERVED2 : 16; + } EXOCON_b[4]; + }; +} XMC_ERU_t; + +/** + * \if XMC4 + * Structure for initializing ERUx_ETLy (x = [0..1], y = [0..4]) module. + * \endif + * \if XMC1 + * Structure for initializing ERUx_ETLy (x = [0], y = [0..4]) module. + * \endif + */ +typedef struct XMC_ERU_ETL_CONFIG +{ + union + { + uint32_t input; /**< While configuring the bit fields, the values have to be shifted according to the position */ + struct + { + uint32_t input_a: 2; /**< Configures input A. Refer @ref XMC_ERU_ETL_INPUT_A_t for valid values */ + uint32_t input_b: 2; /**< Configures input B. Refer @ref XMC_ERU_ETL_INPUT_B_t for valid values */ + uint32_t : 28; + }; + }; + + union + { + uint32_t raw; + struct + { + uint32_t enable_output_trigger: 1; /**< Enables the generation of trigger pulse(PE), for the configured edge + detection. This accepts boolean values as input. */ + uint32_t status_flag_mode: 1; /**< Enables the status flag auto clear(LD), for the opposite edge of the + configured event edge. This accepts boolean values as input. */ + uint32_t edge_detection: 2; /**< Configure the event trigger edge(FE, RE). + Refer @ref XMC_ERU_ETL_EDGE_DETECTION_t for valid values. */ + uint32_t output_trigger_channel: 3; /**< Output channel select(OCS) for ETLx output trigger pulse. + Refer @ref XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t for valid values. */ + uint32_t : 1; + uint32_t source: 4; /**< Input path combination along with polarity for event generation. + Refer @ref XMC_ERU_ETL_SOURCE_t for valid values. */ + uint32_t : 20; + }; + }; +} XMC_ERU_ETL_CONFIG_t; + +/** + * \if XMC4 + * Structure for initializing ERUx_OGUy (x = [0..1], y = [0..4]) module. + * \endif + * \if XMC1 + * Structure for initializing ERUx_OGUy (x = [0], y = [0..4]) module. + * \endif + */ +typedef union XMC_ERU_OGU_CONFIG +{ + uint32_t raw; + + struct + { + uint32_t peripheral_trigger: 2; /**< peripheral trigger(ISS) input selection. + Refer @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t for valid values. */ + uint32_t enable_pattern_detection: 1; /**< Enable generation of(GEEN) event for pattern detection result change. + This accepts boolean values as input. */ + uint32_t : 1; + uint32_t service_request: 2; /**< Gating(GP) on service request generation for pattern detection result. + Refer @ref XMC_ERU_OGU_SERVICE_REQUEST_t for valid values. */ + uint32_t : 6; + uint32_t pattern_detection_input: 4; /**< Enable input for the pattern detection(IPENx, x = [0 to 3]). + Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values. + OR combination of the enum items given as input */ + uint32_t : 16; + }; +} XMC_ERU_OGU_CONFIG_t; + +/*Anonymous structure/union guard end */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * API PROTOTYPES + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * + * @return None + * + * \parDescription:
+ * \if XMC4 + * If ERU1 module is selected, it enables clock and releases reset.
+ * \endif + * \if XMC1 + * Abstract API, not mandatory to call.
+ * \endif + * \par + * This API is called by XMC_ERU_ETL_Init() or XMC_ERU_OGU_Init() and therefore no need to call it explicitly during + * initialization sequence. Call this API to enable ERU1 module once again if the module is disabled by calling + * XMC_ERU_Disable(). For ERU0 module clock gating and reset features are not available. + * + * \parNote:
+ * \if XMC4 + * 1. Required to configure ERU1 module again after calling XMC_ERU_Disable(). Since the all the registers are + * reset with default values. + * \endif + * \parRelated APIs:
+ * XMC_ERU_ETL_Init(), XMC_ERU_OGU_Init(), XMC_ERU_Disable(). + */ +void XMC_ERU_Enable(XMC_ERU_t *const eru); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * + * @return None + * + * \parDescription:
+ * \if XMC4 + * Disables clock and releases reset for ERU1 module.
+ * \endif + * \if XMC1 + * Abstract API, not mandatory to call.
+ * \endif + * + * \parNote:
+ * \if XMC4 + * 1. Required to configure ERU1 module again after calling XMC_ERU_ETL_Init() or XMC_ERU_OGU_Init(). Since the all the + * registers are reset with default values. + * \endif + * \parRelated APIs:
+ * XMC_ERU_Enable() + */ +void XMC_ERU_Disable(XMC_ERU_t *const eru); + +/* ERU_ETL APIs */ + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_ETLx(Event trigger logic unit) channel + * Range : [0 to 3] + * @param config pointer to a constant ERU_ETLx configuration data structure. + * Refer data structure XMC_ERU_ETL_CONFIG_t for detail. + * + * @return None + * + * Description:
+ * Initializes the selected ERU_ETLx \a channel with the \a config structure.
+ * + * Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures + *
    + *
  • Input signal for path A and Path B,
    • + *
  • Trigger pulse generation,
    • + *
  • status flag clear mode,
    • + *
  • Event Trigger edge,
    • + *
  • Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse,
    • + *
  • input path combination along with polarity for event generation
    • + *
. + */ +void XMC_ERU_ETL_Init(XMC_ERU_t *const eru, const uint8_t channel, const XMC_ERU_ETL_CONFIG_t *const config); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * @param input_a input signal for path A of ERSx(Event request source, x = [0 to 3]) unit.\n + * Refer XMC_ERU_ETL_INPUT_A_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of + * the input is done based on selected signal.\n + * e.g: ERU0_ETL3_INPUTA_P2_7. + * @param input_b input signal for path B of ERSx(Event request source, x = [0 to 3]) unit.\n + * Refer XMC_ERU_ETL_INPUT_B_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of + * the input is done based on selected signal.\n + * e.g: ERU0_ETL0_INPUTB_P2_0. + * + * @return None + * + * \parDescription:
+ * Configures the event source for path A and path B in with selected \a input_a and \a input_b respectively.
+ * \par + * These values are set during initialization in XMC_ERU_ETL_Init(). Call this to change the input, as needed later in + * the program. According to the ports/peripheral selected, the event source has to be changed. + */ +void XMC_ERU_ETL_SetInput(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_INPUT_A_t input_a, + const XMC_ERU_ETL_INPUT_B_t input_b); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * @param source input path combination along with polarity for event generation by ERSx(Event request source) unit. + * Refer @ref XMC_ERU_ETL_SOURCE_t enum for valid input values. + * + * @return None + * + * \parDescription:
+ * Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits in + * ERSx(Event request source) unit
+ * \par + * The signal ERSxO is generated from the selection and this is connected to ETLx(Event trigger logic, + * x = [0 to 3]) for further action. These values are set during initialization in XMC_ERU_ETL_Init(). Call this to + * change the source, as needed later in the program. + */ +void XMC_ERU_ETL_SetSource(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_SOURCE_t source); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * @param edge_detection event trigger edge. + * Refer @ref XMC_ERU_ETL_EDGE_DETECTION_t enum for valid values. + * + * @return None + * + * \parDescription:
+ * Configure event trigger edge/s by setting (RE, FE) bits of EXICONx(x = [0 to 3]) register.
+ * \par + * Rising edge, falling edge or either edges can be selected to generate the event.These values are set during + * initialization in XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program. + */ +void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_EDGE_DETECTION_t edge_detection); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * + * @return XMC_ERU_ETL_EDGE_DETECTION_t indicate which egde/s is configured for event generation + * + * \parDescription:
+ * Return event trigger edge/s by reading (RE, FE) bits of EXICONx(x = [0 to 3]) register.
+ * \par + * Rising edge, falling edge or either edges can be selected to generate the event. + * Call this to get the configured trigger edge. */ +XMC_ERU_ETL_EDGE_DETECTION_t XMC_ERU_ETL_GetEdgeDetection(XMC_ERU_t *const eru, + const uint8_t channel); +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * + * @return None + * + * \parDescription:
+ * Set the status flag bit(FL) in EXICONx(x = [0 to 3]).
+ * \par + * The status flag indicates that the configured event has occurred. This status flag is used in Pattern match detection + * by OGUy(Output gating unit, y = [0 to 3]). + * \par + * \parRelated APIs:
+ * XMC_ERU_ETL_ClearStatusFlag(), XMC_ERU_ETL_GetStatusFlag() + */ +__STATIC_INLINE void XMC_ERU_ETL_SetStatusFlag(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_ETL_SetStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_SetStatusFlag:Invalid Channel Number", (channel < 4U)); + + eru->EXICON_b[channel].FL = true; +} + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3] + * + * @return None + * + * \parDescription:
+ * Set the status flag bit(FL) in EXICONx(x = [0 to 3]).
+ * \par + * If auto clear of the status flag is not enabled by detection of the opposite edge of the event edge, this API clears + * the Flag. SO that next event is considered as new event. + * \parRelated APIs:
+ * XMC_ERU_ETL_SetStatusFlag(), XMC_ERU_ETL_GetStatusFlag() + */ +__STATIC_INLINE void XMC_ERU_ETL_ClearStatusFlag(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_ETL_ClearStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_ClearStatusFlag:Invalid Channel Number", (channel < 4U)); + + eru->EXICON_b[channel].FL = false; +} + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3]. + * + * @return uint32_t Current state of the status flag bit(FL). Result is in 32-bit format. + * + * \parDescription:
+ * Returns status flag state of \a channel. + * \par + * The function can typically be used to clear the status flag using software, when auto clear is not enabled. + * + * \parRelated APIs:
+ * XMC_ERU_ETL_SetStatusFlag(), XMC_ERU_ETL_ClearStatusFlag() + */ +__STATIC_INLINE uint32_t XMC_ERU_ETL_GetStatusFlag(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_ETL_GetStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_GetStatusFlag:Invalid Channel Number", (channel < 4U)); + + return (uint32_t)eru->EXICON_b[channel].FL; +} + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3]. + * @param mode Set whether status flag has to be cleared by software or hardware. + * Refer @ref XMC_ERU_ETL_STATUS_FLAG_MODE_t for valid value. + * + * @return None + * + * \parDescription:
+ * Set the mode for status flag mode by setting (LD) bit in EXICONx(x = \a channel) register.
+ * \par + * If SWCTRL is selected, status flag has to be cleared by software. This is typically used for pattern match detection. + * If HWCTRL is selected, status flag is cleared by hardware. If Positive edge is selected as event edge, for negative + * edge status flag is cleared and vice versa.This is typically used for continuous event detection.These values are set + * during initialization in XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_ERU_ETL_ClearStatusFlag(), XMC_ERU_ETL_GetStatusFlag() + */ +void XMC_ERU_ETL_SetStatusFlagMode(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_STATUS_FLAG_MODE_t mode); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3]. + * @param trigger Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse + * Refer @ref XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t for valid value. + * + * @return None + * + * \parDescription:
+ * Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by + * ETLx(Event Trigger Logic, x = \a channel) by setting (OCS and PE) bit fields. + * \par + * The trigger pulse is generated for one clock pulse along with the flag status update. This is typically used to + * trigger the ISR for the external events. The configured OGUy(Output gating unit y = [0 to 3]), generates the event + * based on the trigger pulse.If output trigger pulse generation is disabled by XMC_ERU_ETL_DisableOutputTrigger(), + * XMC_ERU_ETL_EnableOutputTrigger() can called to reconfigure. These values are set during initialization in + * XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_ERU_ETL_DisableOutputTrigger() + */ +void XMC_ERU_ETL_EnableOutputTrigger(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t trigger); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. + * @param channel ERU_ETLx(Event trigger logic unit) channel. + * Range : [0 to 3]. + * + * @return None + * + * \parDescription:
+ * Disables the trigger pulse generation by clearing the (PE) of the EXICONx(x = \a channel). + * \par + * Typically this can used when only pattern match is being used for event generation. + * + * \parRelated APIs:
+ * XMC_ERU_ETL_EnableOutputTrigger() + */ +void XMC_ERU_ETL_DisableOutputTrigger(XMC_ERU_t *const eru, const uint8_t channel); + +/* ERU_OGU APIs */ + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * @param config pointer to constant ERU_OGUy configuration data structure. + * Refer data structure XMC_ERU_OGU_CONFIG_t for detail. + * + * @return None + * + * Description:
+ * Initializes the selected ERU_OGUy \a channel with the \a config structure.
+ * + * Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures + *
    + *
  • Pattern detection,
    • + *
  • Peripheral trigger input,
    • + *
  • Gating for service request generation
    • + *
. + */ +void XMC_ERU_OGU_Init(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_CONFIG_t *const config); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * @param input ERU_ETLx(x = [0 to 3]), for pattern match detection. + * Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values. Logical OR combination of the + * enum items can be passed as the input. + * + * @return None + * + * \parDescription:
+ * Configures ERU_ETLx(x = [0 to 3]) for pattern match detection by setting IPENx(x = [0 to 3]) and GEEN bits. + * \par + * These bits are dedicated to each channel of the ERU_ETLx(x = [0 to 3]). These values are set during initialization in + * XMC_ERU_OGU_Init(). Call this to change the pattern, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_ERU_OGU_DisablePatternDetection(), XMC_ERU_OGU_GetPatternDetectionStatus() + */ +void XMC_ERU_OGU_EnablePatternDetection(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t input); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * + * @return None + * + * \parDescription:
+ * Disable the pattern detection by clearing (GEEN) bit. + * \par + * Typically XMC_ERU_OGU_DisablePatternDetection is used when events has to be generated peripheral triggers. + * + * \parRelated APIs:
+ * XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_GetPatternDetectionStatus() + */ +void XMC_ERU_OGU_DisablePatternDetection(XMC_ERU_t *const eru, const uint8_t channel); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * + * @return uint32_t returns the pattern match result. Result is in 32-bit format. + * + * \parDescription:
+ * This API returns the pattern match result by reading (PDR) bit. + * \par + * \parRelated APIs:
+ * XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_DisablePatternDetection() + */ +__STATIC_INLINE uint32_t XMC_ERU_OGU_GetPatternDetectionStatus(XMC_ERU_t *const eru, + const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_OGU_GetPatternDetectionStatus:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_GetPatternDetectionStatus:Invalid Channel Number", (channel < 4U)); + + return (uint32_t)eru->EXOCON_b[channel].PDR; +} + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * @param peripheral_trigger which peripheral trigger signal is used for event generation. + * Refer @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t for the valid values, or + xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of the peripheral input is done based + on input. e.g: ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0. + * + * @return None + * + * \parDescription:
+ * Configures peripheral trigger input, by setting (ISS) bit. + * \par + * Based on the peripheral the input signal has to be selected. These values are set during initialization in + * XMC_ERU_OGU_Init(). Call this to change the input, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_ERU_OGU_DisablePeripheralTrigger() + */ +void XMC_ERU_OGU_EnablePeripheralTrigger(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * + * @return None + * + * \parDescription:
+ * Disables event generation based on peripheral trigger by clearing (ISS) bit. + * \par + * This is typically used when peripheral trigger is no longer need. After calling + * XMC_ERU_OGU_DisablePeripheralTrigger(), XMC_ERU_OGU_EnablePeripheralTrigger() has to be called to reconfigure the + * signals again. + * + * \parRelated APIs:
+ * XMC_ERU_OGU_EnablePeripheralTrigger() + */ +void XMC_ERU_OGU_DisablePeripheralTrigger(XMC_ERU_t *const eru, + const uint8_t channel); + +/** + * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address + * @param channel ERU_OGUy(Output gating unit) channel + * Range : [0 to 3] + * @param mode gating scheme for service request generation. + * Refer @ref XMC_ERU_OGU_SERVICE_REQUEST_t for valid values. + * + * @return None + * + * \parDescription:
+ * Configures the gating scheme for service request generation by setting (GP) bit.
+ * \par + * Typically this function is used to change the service request generation scheme. These values are set during + * initialization in XMC_ERU_OGU_Init(). Call this to change the gating mode, as needed later in the program. + * + */ +void XMC_ERU_OGU_SetServiceRequestMode(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_SERVICE_REQUEST_t mode); + +#ifdef __cplusplus +} +#endif + +/** + * @} (end addtogroup ERU) + */ + +/** + * @} (end addtogroup XMClib) + */ + +#endif /* XMC_ERU_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eth_mac.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eth_mac.h new file mode 100644 index 00000000..25488673 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eth_mac.h @@ -0,0 +1,1791 @@ + +/** + * @file xmc_eth_mac.h + * @date 2017-04-17 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * + * 2016-04-25: + * - Change XMC_ETH_MAC_BUF_SIZE to 1524 to allow for Tagged MAC frame format + * + * 2016-05-19: + * - Added XMC_ETH_MAC_GetTxBuffer() and XMC_ETH_MAC_GetRxBuffer() + * - Added XMC_ETH_MAC_SetTxBufferSize() + * + * 2016-06-08: + * - Added XMC_ETH_MAC_IsRxDescriptorOwnedByDma() + * + * 2017-02-25: + * - XMC_ETH_MAC_SetPortControl() fixed compilation warning + * + * 2017-04-02: + * - Added XMC_ETH_MAC_InitPTPEx() + * - Added XMC_ETH_MAC_SetPTPTime() + * - Added XMC_ETH_MAC_UpdateAddend() + * + * 2017-04-11: + * - Added XMC_ETH_MAC_EnablePTPAlarm() and XMC_ETH_MAC_DisablePTPAlarm + * + * 2017-04-17: + * - Fixed ordering of PTP nanoseconds and seconds in XMC_ETH_MAC_DMA_DESC_t + * + * @endcond + */ + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup ETH_MAC + * @brief Ethernet Low level driver for XMC4000 microcontroller family. + * + * The Ethernet MAC (ETH) is a major communication peripheral that supports 10/100 + * MBit/s data transfer rates in compliance with the IEEE 802.3-2002 standard. The ETH + * may be used to implement internet connected applications using IPv4 and IPv6. The + * ETH also includes support for IEEE1588 time synchronisation to allow implementation + * of Real Time Ethernet protocols. + * + * The XMC_ETH_MAC low level driver provides functions to configure and initialize + * the ETH_MAC hardware peripheral. + * @{ + */ + +#ifndef XMC_ETH_MAC_H +#define XMC_ETH_MAC_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_common.h" + +#if defined (ETH0) + +#include "xmc_eth_mac_map.h" + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +#define XMC_ETH_MAC_BUF_SIZE (1524) /**< ETH MAC buffer size */ +#define XMC_ETH_MAC_PHY_MAX_RETRIES (0xffffUL) /**< Maximum retries */ +#define XMC_ETH_WAKEUP_REGISTER_LENGTH (8U) /**< Remote wakeup frame reg length */ + +/** + * TDES0 Descriptor TX Packet Control/Status + */ +#define ETH_MAC_DMA_TDES0_OWN (0x80000000U) /**< Own bit 1=DMA, 0=CPU */ +#define ETH_MAC_DMA_TDES0_IC (0x40000000U) /**< Interrupt on competition */ +#define ETH_MAC_DMA_TDES0_LS (0x20000000U) /**< Last segment */ +#define ETH_MAC_DMA_TDES0_FS (0x10000000U) /**< First segment */ +#define ETH_MAC_DMA_TDES0_DC (0x08000000U) /**< Disable CRC */ +#define ETH_MAC_DMA_TDES0_DP (0x04000000U) /**< Disable pad */ +#define ETH_MAC_DMA_TDES0_TTSE (0x02000000U) /**< Transmit time stamp enable */ +#define ETH_MAC_DMA_TDES0_CIC (0x00C00000U) /**< Checksum insertion control */ +#define ETH_MAC_DMA_TDES0_TER (0x00200000U) /**< Transmit end of ring */ +#define ETH_MAC_DMA_TDES0_TCH (0x00100000U) /**< Second address chained */ +#define ETH_MAC_DMA_TDES0_TTSS (0x00020000U) /**< Transmit time stamp status */ +#define ETH_MAC_DMA_TDES0_IHE (0x00010000U) /**< IP header error */ +#define ETH_MAC_DMA_TDES0_ES (0x00008000U) /**< Error summary */ +#define ETH_MAC_DMA_TDES0_JT (0x00004000U) /**< Jabber timeout */ +#define ETH_MAC_DMA_TDES0_FF (0x00002000U) /**< Frame flushed */ +#define ETH_MAC_DMA_TDES0_IPE (0x00001000U) /**< IP payload error */ +#define ETH_MAC_DMA_TDES0_LOC (0x00000800U) /**< Loss of carrier */ +#define ETH_MAC_DMA_TDES0_NC (0x00000400U) /**< No carrier */ +#define ETH_MAC_DMA_TDES0_LC (0x00000200U) /**< Late collision */ +#define ETH_MAC_DMA_TDES0_EC (0x00000100U) /**< Excessive collision */ +#define ETH_MAC_DMA_TDES0_VF (0x00000080U) /**< VLAN frame */ +#define ETH_MAC_DMA_TDES0_CC (0x00000078U) /**< Collision count */ +#define ETH_MAC_DMA_TDES0_ED (0x00000004U) /**< Excessive deferral */ +#define ETH_MAC_DMA_TDES0_UF (0x00000002U) /**< Underflow error */ +#define ETH_MAC_DMA_TDES0_DB (0x00000001U) /**< Deferred bit */ + +/** + * RDES0 Descriptor RX Packet Status + */ +#define ETH_MAC_DMA_RDES0_OWN (0x80000000U) /**< Own bit 1=DMA, 0=CPU */ +#define ETH_MAC_DMA_RDES0_AFM (0x40000000U) /**< Destination address filter fail */ +#define ETH_MAC_DMA_RDES0_FL (0x3FFF0000U) /**< Frame length mask */ +#define ETH_MAC_DMA_RDES0_ES (0x00008000U) /**< Error summary */ +#define ETH_MAC_DMA_RDES0_DE (0x00004000U) /**< Descriptor error */ +#define ETH_MAC_DMA_RDES0_SAF (0x00002000U) /**< Source address filter fail */ +#define ETH_MAC_DMA_RDES0_LE (0x00001000U) /**< Length error */ +#define ETH_MAC_DMA_RDES0_OE (0x00000800U) /**< Overflow error */ +#define ETH_MAC_DMA_RDES0_VLAN (0x00000400U) /**< VLAN tag */ +#define ETH_MAC_DMA_RDES0_FS (0x00000200U) /**< First descriptor */ +#define ETH_MAC_DMA_RDES0_LS (0x00000100U) /**< Last descriptor */ +#define ETH_MAC_DMA_RDES0_TSA (0x00000080U) /**< Timestamp available */ +#define ETH_MAC_DMA_RDES0_LC (0x00000040U) /**< Late collision */ +#define ETH_MAC_DMA_RDES0_FT (0x00000020U) /**< Frame type */ +#define ETH_MAC_DMA_RDES0_RWT (0x00000010U) /**< Receive watchdog timeout */ +#define ETH_MAC_DMA_RDES0_RE (0x00000008U) /**< Receive error */ +#define ETH_MAC_DMA_RDES0_DBE (0x00000004U) /**< Dribble bit error */ +#define ETH_MAC_DMA_RDES0_CE (0x00000002U) /**< CRC error */ +#define ETH_MAC_DMA_RDES0_ESA (0x00000001U) /**< Extended Status/Rx MAC address */ + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + +/** + * Ethernet MAC status return values + */ +typedef enum XMC_ETH_MAC_STATUS +{ + XMC_ETH_MAC_STATUS_OK = 0U, /**< Driver accepted application request */ + XMC_ETH_MAC_STATUS_BUSY = 1U, /**< Driver is busy and cannot handle request */ + XMC_ETH_MAC_STATUS_ERROR = 2U /**< Driver could not fulfil application request */ +} XMC_ETH_MAC_STATUS_t; + +/** + * Transmission frame + */ +typedef enum XMC_ETH_MAC_TX_FRAME +{ + XMC_ETH_MAC_TX_FRAME_FRAGMENT = 0x1U, /**< Indicate frame fragment */ + XMC_ETH_MAC_TX_FRAME_EVENT = 0x2U, /**< Generate event when frame is transmitted */ + XMC_ETH_MAC_TX_FRAME_TIMESTAMP = 0x4U /**< Capture frame time stamp */ +} XMC_ETH_MAC_TX_FRAME_t; + +/** + * ETH MAC event + */ +typedef enum XMC_ETH_MAC_EVENT +{ + XMC_ETH_MAC_EVENT_PMT = ETH_INTERRUPT_MASK_PMTIM_Msk << 16, /**< Power management event */ + XMC_ETH_MAC_EVENT_TIMESTAMP = ETH_INTERRUPT_MASK_TSIM_Msk << 16, /**< Time stamp event */ + XMC_ETH_MAC_EVENT_EARLY_RECEIVE = ETH_STATUS_ERI_Msk, /**< Early receive */ + XMC_ETH_MAC_EVENT_BUS_ERROR = ETH_STATUS_FBI_Msk, /**< Bus error */ + XMC_ETH_MAC_EVENT_EARLY_TRANSMIT = ETH_STATUS_ETI_Msk, /**< Early transmit */ + XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT = ETH_STATUS_RWT_Msk, /**< Receive watchdog time-out */ + XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED = ETH_STATUS_RPS_Msk, /**< Receive process stopped */ + XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE = ETH_STATUS_RU_Msk, /**< Receive buffer unavailable */ + XMC_ETH_MAC_EVENT_RECEIVE = ETH_STATUS_RI_Msk, /**< Receive event */ + XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW = ETH_STATUS_UNF_Msk, /**< Transmit underflow */ + XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW = ETH_STATUS_OVF_Msk, /**< Receive overflow */ + XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT = ETH_STATUS_TJT_Msk, /**< Transmit jabber time-out */ + XMC_ETH_MAC_EVENT_TRANSMIT_BUFFER_UNAVAILABLE = ETH_STATUS_TU_Msk, /**< Transmit buffer unavailable */ + XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED = ETH_STATUS_TPS_Msk, /**< Transmit process stopped */ + XMC_ETH_MAC_EVENT_TRANSMIT = ETH_STATUS_TI_Msk /**< Transmit event */ +} XMC_ETH_MAC_EVENT_t; + +/** + * Link interface + */ +typedef enum XMC_ETH_LINK_INTERFACE +{ + XMC_ETH_LINK_INTERFACE_MII, /**< Link interface: Media independent interface */ + XMC_ETH_LINK_INTERFACE_RMII /**< Link interface: Reduced media independent interface */ +} XMC_ETH_LINK_INTERFACE_t; + +/** + * ETH link status + */ +typedef enum XMC_ETH_LINK_STATUS +{ + XMC_ETH_LINK_STATUS_DOWN, /**< Link status down */ + XMC_ETH_LINK_STATUS_UP /**< Link status up */ +} XMC_ETH_LINK_STATUS_t; + +/** + * ETH link speed + */ +typedef enum XMC_ETH_LINK_SPEED +{ + XMC_ETH_LINK_SPEED_10M = 0UL << ETH_MAC_CONFIGURATION_FES_Pos, /**< Link speed: 10M */ + XMC_ETH_LINK_SPEED_100M = 1UL << ETH_MAC_CONFIGURATION_FES_Pos /**< Link speed: 100M */ +} XMC_ETH_LINK_SPEED_t; + +/** + * ETH duplex settings (full/half?) + */ +typedef enum XMC_ETH_LINK_DUPLEX +{ + XMC_ETH_LINK_DUPLEX_HALF = 0UL << ETH_MAC_CONFIGURATION_DM_Pos, /**< Half duplex */ + XMC_ETH_LINK_DUPLEX_FULL = 1UL << ETH_MAC_CONFIGURATION_DM_Pos /**< Full duplex */ +} XMC_ETH_LINK_DUPLEX_t; + +/** + * MAC address filter + */ +typedef enum XMC_ETH_MAC_ADDR_FILTER +{ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE0 = 0x01000000UL, /**< Address filter mask: byte 0 */ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE1 = 0x02000000UL, /**< Address filter mask: byte 1 */ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE2 = 0x04000000UL, /**< Address filter mask: byte 2 */ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE3 = 0x08000000UL, /**< Address filter mask: byte 3 */ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE4 = 0x10000000UL, /**< Address filter mask: byte 4 */ + XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE5 = 0x20000000UL, /**< Address filter mask: byte 5 */ + XMC_ETH_MAC_ADDR_FILTER_SA = 0x40000000UL /**< Address filter SA */ +} XMC_ETH_MAC_ADDR_FILTER_t; + +/** + * Power management events that triggers a PMT interrupt + */ +typedef enum XMC_ETH_MAC_PMT_EVENT +{ + XMC_ETH_MAC_PMT_EVENT_ON_WAKEUP_FRAME = ETH_PMT_CONTROL_STATUS_RWKPKTEN_Msk, /**< Wakeup frame */ + XMC_ETH_MAC_PMT_EVENT_ON_MAGIC_PACKET = ETH_PMT_CONTROL_STATUS_MGKPKTEN_Msk, /**< Magic packet */ + XMC_ETH_MAC_PMT_EVENT_ON_UNICAST_FRAME_FILTER = ETH_PMT_CONTROL_STATUS_GLBLUCAST_Msk /**< Unicast frame filter */ +} XMC_ETH_MAC_PMT_EVENT_t; + + +/** + * ETH MAC time-stamp configuration enable + */ +typedef enum XMC_ETH_MAC_TIMESTAMP_CONFIG +{ + XMC_ETH_MAC_TIMESTAMP_CONFIG_FINE_UPDATE = ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk, /**< Fine update */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_TS_INTERRUPT = ETH_TIMESTAMP_CONTROL_TSTRIG_Msk, /**< Timestamp Interrupt Trigger Enable */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_ALL_FRAMES = ETH_TIMESTAMP_CONTROL_TSENALL_Msk, /**< Enable all frames */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTPV2 = ETH_TIMESTAMP_CONTROL_TSVER2ENA_Msk, /**< PTPV2 */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_ETHERNET = ETH_TIMESTAMP_CONTROL_TSIPENA_Msk, /**< PTP over ETH */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_IPV6 = ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Msk, /**< PTP over IPV6 */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_IPV4 = ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Msk, /**< PTP over IPV4 */ + XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_MAC_ADDRESS_FILTER = ETH_TIMESTAMP_CONTROL_TSENMACADDR_Msk /**< MAC address filter */ +} XMC_ETH_MAC_TIMESTAMP_CONFIG_t; + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ + +/* Anonymous structure/union guard start */ +#if defined (__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined (__TASKING__) +#pragma warning 586 +#endif + +/** + * ETH MAC port control + */ +typedef union XMC_ETH_MAC_PORT_CTRL +{ + struct + { + uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ETH_MAC_PORT_CTRL_RXD0_t) */ + uint32_t rxd1: 2; /**< Receive data bit 1 (::XMC_ETH_MAC_PORT_CTRL_RXD1_t) */ + uint32_t rxd2: 2; /**< Receive data bit 2 (only MII) (::XMC_ETH_MAC_PORT_CTRL_RXD2_t) */ + uint32_t rxd3: 2; /**< Receive data bit 3 (only MII) (::XMC_ETH_MAC_PORT_CTRL_RXD3_t) */ + uint32_t clk_rmii: 2; /**< RMII: Continuous 50 MHz reference clock. + MII: Receive clock, 25 MHz for 100Mbit/s, 2.5 MHz for 10Mbit/s + (::XMC_ETH_MAC_PORT_CTRL_CLK_RMII_t) */ + uint32_t crs_dv: 2; /**< RMII: carrier sense/RX_Data valid. MII: RX_Data valid (::XMC_ETH_MAC_PORT_CTRL_CRS_DV_t) */ + uint32_t crs: 2; /**< Carrier sense for only MII (::XMC_ETH_MAC_PORT_CTRL_CRS_t) */ + uint32_t rxer: 2; /**< Receive error (::XMC_ETH_MAC_PORT_CTRL_RXER_t) */ + uint32_t col: 2; /**< Collision Detect for only MII (::XMC_ETH_MAC_PORT_CTRL_COL_t) */ + uint32_t clk_tx: 2; /**< Transmit clock (only MII), 25 MHz for 100Mbit/s, 2.5 MHz for 10Mbit/s (::XMC_ETH_MAC_PORT_CTRL_CLK_TX_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t mdio: 2; /**< Bidirectional, push-pull management data I/O line (::XMC_ETH_MAC_PORT_CTRL_MDIO_t) */ + uint32_t: 2; /**< Reserved bits */ + uint32_t mode: 1; /**< RMII or MII (::XMC_ETH_MAC_PORT_CTRL_MODE_t) */ + }; + + uint32_t raw; +} XMC_ETH_MAC_PORT_CTRL_t; + +/** + * ETH MAC DMA descriptor + */ +typedef struct XMC_ETH_MAC_DMA_DESC +{ + uint32_t status; /**< DMA descriptor status */ + uint32_t length; /**< Descriptor length */ + uint32_t buffer1; /**< Buffer 1 */ + uint32_t buffer2; /**< Buffer 2 */ + uint32_t extended_status; /**< Extended status */ + uint32_t reserved; /**< Reserved */ + uint32_t time_stamp_nanoseconds; /**< Time stamp low */ + uint32_t time_stamp_seconds; /**< Time stamp high */ +} XMC_ETH_MAC_DMA_DESC_t; + +/** + * ETH MAC time + */ +typedef struct XMC_ETH_MAC_TIME +{ + uint32_t seconds; /**< Seconds */ + int32_t nanoseconds; /**< Nanoseconds */ +} XMC_ETH_MAC_TIME_t; + +/** + * ETH driver structure + */ +typedef struct XMC_ETH_MAC +{ + ETH_GLOBAL_TypeDef *regs; /**< ETH module 0 (now, we have a single ETH module) */ + uint64_t address; /**< MAC address */ + XMC_ETH_MAC_DMA_DESC_t *rx_desc; /**< DMA descriptor: RX */ + XMC_ETH_MAC_DMA_DESC_t *tx_desc; /**< DMA descriptor: TX */ + uint8_t *rx_buf; /**< RX buffer */ + uint8_t *tx_buf; /**< TX buffer */ + uint8_t *frame_end; /**< End of assembled frame fragments */ + uint8_t num_rx_buf; /**< How many RX descriptors? */ + uint8_t num_tx_buf; /**< How many TX descriptors? */ + uint8_t tx_index; /**< Transmit descriptor index */ + uint8_t rx_index; /**< Receive descriptor index */ + uint8_t tx_ts_index; /**< Transmit time-stamp descriptor index */ +} XMC_ETH_MAC_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) +#pragma pop +#elif defined (__TASKING__) +#pragma warning restore +#endif + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return XMC_ETH_MAC_STATUS_t Initialization status + * + * \parDescription:
+ * Initialize the Ethernet MAC peripheral
+ * + * \par + * The function sets the link speed, applies the duplex mode, sets auto-negotiation + * and loop-back settings. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_Init(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Initialize the RX DMA descriptors
+ * + * \par + * The function initializes the RX descriptors in a chained configuration. It sets + * up the status bit, control bit, buffer length and the buffer pointer. + */ +void XMC_ETH_MAC_InitRxDescriptors(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Initialize the TX DMA descriptors
+ * + * \par + * The function initializes the TX descriptors in a chained configuration. It sets + * up the status bit, control bit, buffer length and the buffer pointer. + */ +void XMC_ETH_MAC_InitTxDescriptors(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable the Ethernet MAC peripheral
+ * + * \par + * The function de-asserts the peripheral reset. + */ +void XMC_ETH_MAC_Enable(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable the Ethernet MAC peripheral
+ * + * \par + * The function asserts the peripheral reset. + */ +void XMC_ETH_MAC_Disable(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return bool + * + * \parDescription:
+ * Check if the ETH MAC is enabled
+ * + * \par + * The function checks if the ETH MAC is enabled or not. It returns "true" if the + * peripheral is enabled, "false" otherwise. + */ +bool XMC_ETH_MAC_IsEnabled(const XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Reset the ETH MAC peripheral
+ * + * \par + * The function resets the ETH MAC peripheral. It blocks until reset. + */ +__STATIC_INLINE void XMC_ETH_MAC_Reset(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->BUS_MODE |= (uint32_t)ETH_BUS_MODE_SWR_Msk; + while ((eth_mac->regs->BUS_MODE & (uint32_t)ETH_BUS_MODE_SWR_Msk) != 0U) + { + } +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr PHY address + * @param reg_addr Register address + * @param data The destination to which the read data needs to be copied to + * @return XMC_ETH_MAC_STATUS_t ETH MAC status + * + * \parDescription:
+ * Read a PHY register
+ * + * \par + * The function reads a PHY register. It essentially polls busy bit during max + * PHY_TIMEOUT time and reads the information into 'data' when not busy. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_ReadPhy(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr PHY address + * @param reg_addr Register address + * @param data The data to write + * @return XMC_ETH_MAC_STATUS_t ETH MAC status + * + * \parDescription:
+ * Write a PHY register
+ * + * \par + * The function reads a PHY register. It essentially writes the data and polls + * the busy bit until it is no longer busy. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_WritePhy(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, uint8_t reg_addr, uint16_t data); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param port_ctrl Port control configuration + * @return None + * + * \parDescription:
+ * Set port control configuration
+ * + * \par + * The function sets the port control by writing the configuration into the + * CON register. + * + * \note + * MII Mode is only available in: + * - XMC4500 LQFP144 and BGA144 packages + * - XMC4700 LQFP144 and BGA196 packages + * - XMC4800 LQFP144 and BGA196 packages + * + */ +__STATIC_INLINE void XMC_ETH_MAC_SetPortControl(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_PORT_CTRL_t port_ctrl) +{ + XMC_UNUSED_ARG(eth_mac); + ETH0_CON->CON = (uint32_t)port_ctrl.raw; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return XMC_ETH_MAC_STATUS_t ETH MAC status + * + * \parDescription:
+ * Set management clock divider
+ * + * \par + * The function sets the management clock divider by writing to the GMII_ADDRESS + * register. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SetManagmentClockDivider(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param addr The MAC address to set + * @return None + * + * \parDescription:
+ * Set MAC address
+ * + * \par + * The function sets the MAC address by writing to the MAC_ADDRESS0_HIGH and + * MAC_ADDRESS0_LOW registers. + */ +__STATIC_INLINE void XMC_ETH_MAC_SetAddress(XMC_ETH_MAC_t *const eth_mac, uint64_t addr) +{ + eth_mac->regs->MAC_ADDRESS0_HIGH = (uint32_t)(addr >> 32); + eth_mac->regs->MAC_ADDRESS0_LOW = (uint32_t)addr; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return uint64_t The MAC address which has been set + * + * \parDescription:
+ * Get MAC address
+ * + * \par + * The function returns the current ETH MAC address. + */ +__STATIC_INLINE uint64_t XMC_ETH_MAC_GetAddress(XMC_ETH_MAC_t *const eth_mac) +{ + return ((((uint64_t)eth_mac->regs->MAC_ADDRESS0_HIGH << 32)) | (uint64_t)eth_mac->regs->MAC_ADDRESS0_LOW); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param index Table entry index + * @param addr Address value + * @param flags Compare control. OR'ed combination of @ref XMC_ETH_MAC_ADDR_FILTER_t or zero. + * + * @return None + * + * \parDescription:
+ * Set perfect filter for address filtering
+ * + * \par + * The function can be used to set perfect filter for address filtering. + */ +void XMC_ETH_MAC_SetAddressPerfectFilter(XMC_ETH_MAC_t *const eth_mac, uint8_t index, const uint64_t addr, uint32_t flags); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param hash The hash to be used for filtering + * @return None + * + * \parDescription:
+ * Set hash filter for group address filtering
+ * + * \par + * The function sets up a hash filter for group address filtering. It writes the + * given hash value into the HASH_TABLE_LOW and HASH_TABLE_HIGH registers. + */ +void XMC_ETH_MAC_SetAddressHashFilter(XMC_ETH_MAC_t *const eth_mac, const uint64_t hash); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable frame filter
+ * + * \par + * The function resets the RA bitfield of the MAC_FRAME_FILTER register. This + * ensures that the receiver module passes only those frames (to the application) + * that pass the SA or DA address filter. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableFrameFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_RA_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable frame filter
+ * + * \par + * The function sets the RA bitfield of the MAC_FRAME_FILTER register. This + * ensures that the receiver module passes all received frames, irrespective + * of whether they pass the address filter or not. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableFrameFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_RA_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable hash perfect filter
+ * + * \par + * The function sets the HPF bitfield of the MAC_FRAME_FILTER register. The + * function configures the address filter to pass a frame if it matches + * either the perfect filtering or the hash filtering. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableHashPerfectFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_HPF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable perfect filter
+ * + * \par + * The function clears the HPF bitfield of the MAC_FRAME_FILTER register. When the + * function is invoked, the frame is passed only if it matches the hash filter. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnablePerfectFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_HPF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable source address filter
+ * + * \par + * The function sets the SAF bitfield of the MAC_FRAME_FILTER register. Verbatim + * from the reference manual - "When invoked, the MAC compares the SA field of the + * received frames with the values programmed in the enabled SA registers. If the + * comparison matches, then the SA Match bit of RxStatus Word is set high. When + * this bit is set high and the SA filter fails, the MAC drops the frame. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableSourceAddressFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_SAF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable source address filter
+ * + * \par + * The function resets the SAF bitfield of the MAC_FRAME_FILTER register. Verbatim + * from the reference manual - "When invoked, the MAC forwards the received frame to + * the application and updates the SA Match bit of the RxStatus depending on + * the SA address comparison". + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableSourceAddressFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_SAF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable source address inverse filtering
+ * + * \par + * The function resets the SAIF bitfield of the MAC_FRAME_FILTER register. Verbatim + * from the reference manual - "When invoked, the address check block operates in + * inverse filtering mode for the SA address comparison. The frames whose SA matches + * the SA registers are marked as failing the SA Address filter". + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableSourceAddressInverseFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_SAIF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable source address inverse filtering
+ * + * \par + * The function resets the SAIF bitfield of the MAC_FRAME_FILTER register. Verbatim + * from the reference manual - "When invoked, frames whose SA does not match the SA + * registers are marked as failing the SA Address filter". + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableSourceAddressInverseFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_SAIF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable destination address inverse filtering
+ * + * \par + * The function sets the DAIF bitfield of the MAC_FRAME_FILTER register. Verbatim + * from the reference manual - "When invoked, the address check block operates in + * inverse filtering mode for the DA address comparison for both unicast and + * multicast frames". + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableDestinationAddressInverseFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_DAIF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable destination address inverse filtering
+ * + * \par + * The function sets the DAIF bitfield of the MAC_FRAME_FILTER register. It can + * be used to perform normal filtering of frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableDestinationAddressInverseFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_DAIF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable multicast hash filter
+ * + * \par + * When invoked, the MAC performs destination address filtering of received + * multicast frames according to the hash table. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableMulticastHashFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_HMC_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable multicast hash filter
+ * + * \par + * The function disables multicast hash filtering. The MAC performs a perfect + * destination address filtering for multicast frames post invocation. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableMulticastHashFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_HMC_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable unicast hash filter
+ * + * \par + * The function enables the MAC to perform destination address filtering of + * unicast frames according to the hash table. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableUnicastHashFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_HUC_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable unicast hash filter
+ * + * \par + * The function disables unicast hash filtering. When invoked, the MAC performs a + * perfect destination address filtering for unicast frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableUnicastHashFilter(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_HUC_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param frame A pointer to a uint8_t constant, holding the frame to be transmitted + * @param len Length of the frame to transmit + * @param flags Additional flags: ored combination of ::XMC_ETH_MAC_TX_FRAME_t or zero. + * @return XMC_ETH_MAC_STATUS_t ETH MAC status (XMC_ETH_MAC_STATUS_BUSY if busy, + * XMC_ETH_MAC_STATUS_OK otherwise). + * + * \parDescription:
+ * Send a frame
+ * + * \par + * The function is used to send a frame. The transmission is done using + * the ETH MAC's dedicated DMA unit. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SendFrame(XMC_ETH_MAC_t *const eth_mac, + const uint8_t *frame, + uint32_t len, + uint32_t flags); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param frame A constant pointer to a uint8_t constant, holding the received frame + * @param len Frame length? + * @return uint32_t Length of the frame + * + * \parDescription:
+ * Read a frame
+ * + * \par + * The function is used to read a frame. The function returns 'len', the length + * as specified as the actual parameter in the function call. + */ +uint32_t XMC_ETH_MAC_ReadFrame(XMC_ETH_MAC_t *const eth_mac, uint8_t *const frame, uint32_t len); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return uint32_t RX frame size + * + * \parDescription:
+ * Get RX frame size
+ * + * \par + * The function is used to get the effective length of the RX frame size. + */ +uint32_t XMC_ETH_MAC_GetRxFrameSize(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable reception of broadcast frames
+ * + * \par + * This function enables the AFM module to pass all received broadcast frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableReceptionBroadcastFrames(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_DBF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable reception of broadcast frames
+ * + * \par + * The function sets the DBF bitfield of the MAC_FRAME_FILTER register. When set, + * the AFM module filters all incoming broadcast frames. In addition, it overrides + * all other filter settings. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableReceptionBroadcastFrames(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_DBF_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable reception of multicast frames
+ * + * \par + * The function sets the DBF bitfield of the MAC_FRAME_FILTER register. When set, + * the AFM module filters all incoming broadcast frames. In addition, it overrides + * all other filter settings. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableReceptionMulticastFrames(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_PM_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable reception of multicast frames
+ * + * \par + * The function disables the reception of multicast frames. When invoked, the AFM + * module passes all received broadcast frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableReceptionMulticastFrames(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_PM_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable promiscuous mode
+ * + * \par + * The function enables the promiscuous mode. In this mode, the address filter + * module passes all incoming frames regardless of its destination or source + * address. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnablePromiscuousMode(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_PR_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable promiscuous mode
+ * + * \par + * The function disables the promiscuous mode. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisablePromiscuousMode(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_PR_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable RX watchdog
+ * + * \par + * The function enables the RX watchdog by clearing the WD bitfield of the + * MAC_CONFIGURATION register. When invoked, the MAC does not allow more + * than 2048 bytes of the frame being received. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableRxWatchdog(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_WD_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable RX watchdog
+ * + * \par + * The function disables the RX watchdog by disabling the timer on the RX. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableRxWatchdog(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_WD_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable TX jabber
+ * + * \par + * When the function is invoked, the MAC cuts off the transmitter if the application + * sends out more than 2,048 bytes of data during transmission (10,240 bytes if + * jumbo frames are enabled) + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableTxJabber(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_JD_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable TX jabber
+ * + * \par + * When the function is invoked, the MAC disables the jabber timer on TX. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableTxJabber(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_JD_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Frame burst enable
+ * + * \par + * The function can be used to enable frame bursting during transmission in the + * MII half-duplex mode. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableFrameBurst(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_BE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Frame burst disable
+ * + * \par + * The function can be used to disable frame bursting. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableFrameBurst(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_BE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Jumbo frame enable
+ * + * \par + * The function can be used to enable jumbo frames. When enabled, the MAC allows + * jumbo frames of 9,018 bytes without reporting a giant frame error in the receive + * frame status. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableJumboFrame(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_JE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Jumbo frame disable
+ * + * \par + * The function can be used to disable jumbo frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableJumboFrame(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_JE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable receive own
+ * + * \par + * The function enables the MAC to receive all packets that are given by the PHY + * while transmitting. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableRxOwn(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_DO_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable receive own
+ * + * \par + * On invocation of the function, the MAC disables the reception of frames in the + * half-duplex mode. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableRxOwn(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_DO_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable loopback mode
+ * + * \par + * The function enables the MAC to operate in the loopback mode using the MII. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableLoopback(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_LM_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable loopback mode
+ * + * \par + * The function can be used to disable the loopback mode. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableLoopback(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_LM_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param speed The speed at which the link is set (10M or 100M?) + * @param duplex Duplex settings (half or full duplex?) + * @return None + * + * \parDescription:
+ * Set link
+ * + * \par + * The function sets the link speed and duplex settings. + */ +__STATIC_INLINE void XMC_ETH_MAC_SetLink(XMC_ETH_MAC_t *const eth_mac, + XMC_ETH_LINK_SPEED_t speed, + XMC_ETH_LINK_DUPLEX_t duplex) +{ + eth_mac->regs->MAC_CONFIGURATION = (eth_mac->regs->MAC_CONFIGURATION & + (uint32_t)~(ETH_MAC_CONFIGURATION_DM_Msk | ETH_MAC_CONFIGURATION_FES_Msk)) | + (uint32_t)speed | (uint32_t)duplex; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Return RX descriptor
+ * + * \par + * The function sets the specified DMA RX descriptor own bit. + */ +void XMC_ETH_MAC_ReturnRxDescriptor(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return bool true if RX descriptor is owned by DMA, false otherwise + * + * \parDescription:
+ * Is RX descriptor owned by DMA?
+ * + * \par + * The function checks if the RX descriptor is owned by the DMA. + */ +__STATIC_INLINE bool XMC_ETH_MAC_IsRxDescriptorOwnedByDma(XMC_ETH_MAC_t *const eth_mac) +{ + return ((eth_mac->rx_desc[eth_mac->rx_index].status & ETH_MAC_DMA_RDES0_OWN) != 0U); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Return TX descriptor
+ * + * \par + * The function sets the specified DMA TX descriptor own bit. + */ +void XMC_ETH_MAC_ReturnTxDescriptor(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return bool true if TX descriptor is owned by DMA, false otherwise + * + * \parDescription:
+ * Is TX descriptor owned by DMA?
+ * + * \par + * The function checks if the TX descriptor is owned by the DMA. + */ +__STATIC_INLINE bool XMC_ETH_MAC_IsTxDescriptorOwnedByDma(XMC_ETH_MAC_t *const eth_mac) +{ + return ((eth_mac->tx_desc[eth_mac->tx_index].status & ETH_MAC_DMA_TDES0_OWN) != 0U); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * ETH MAC Enable RX
+ * + * \par + * The function enables the receiver state machine of the MAC and puts the + * receive process in running state. The DMA then acquires the descriptor + * from the receive list and processes the received frames. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableRx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->OPERATION_MODE |= (uint32_t)ETH_OPERATION_MODE_SR_Msk; + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_RE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * ETH MAC Disable RX
+ * + * \par + * The function disables the receive process. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableRx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_RE_Msk; + eth_mac->regs->OPERATION_MODE &= (uint32_t)~ETH_OPERATION_MODE_SR_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * ETH MAC Enable TX
+ * + * \par + * The function enables the transmit state machine of the MAC and puts the + * transmit process in running state. The DMA then checks the TX list at the + * current position for transmitting a frame. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnableTx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->OPERATION_MODE |= (uint32_t)ETH_OPERATION_MODE_ST_Msk; + eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_TE_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * ETH MAC Disable TX
+ * + * \par + * The function disables the transmit process. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisableTx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->MAC_CONFIGURATION &= (uint32_t)~ETH_MAC_CONFIGURATION_TE_Msk; + eth_mac->regs->OPERATION_MODE &= (uint32_t)~ETH_OPERATION_MODE_ST_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Flush TX
+ * + * \par + * The function initializes the TX DMA descriptors and enables the DMA transmission. + */ +void XMC_ETH_MAC_FlushTx(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Flush RX
+ * + * \par + * The function initializes the RX DMA descriptors and enables the DMA transmission. + */ +void XMC_ETH_MAC_FlushRx(XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Resume TX
+ * + * \par + * Verbatim from the reference manual, the function enables the DMA to read the + * current descriptor pointed to by the "current host transmit descriptor" reg. + * If that descriptor is not available (owned by the CPU), the transmission + * returns to the suspend state else the transmission resumes. + */ +__STATIC_INLINE void XMC_ETH_MAC_ResumeTx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_TPS_Msk; + eth_mac->regs->TRANSMIT_POLL_DEMAND = 0U; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Resume RX
+ * + * \par + * Verbatim from the reference manual the function enables the DMA to read the + * current descriptor pointed to by the "current host transmit descriptor" reg. + * If that descriptor is not available (owned by the CPU), the transmission + * returns to the suspend state else the transmission resumes. + */ +__STATIC_INLINE void XMC_ETH_MAC_ResumeRx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_RU_Msk; + eth_mac->regs->RECEIVE_POLL_DEMAND = 0U; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return Pointer to current TX buffer + * + * \parDescription:
+ * Returns the current TX buffer. + */ +__STATIC_INLINE uint8_t *XMC_ETH_MAC_GetTxBuffer(XMC_ETH_MAC_t *const eth_mac) +{ + return (uint8_t *)(eth_mac->tx_desc[eth_mac->tx_index].buffer1); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return Pointer to current RX buffer + * + * \parDescription:
+ * Returns the current RX buffer. + */ +__STATIC_INLINE uint8_t *XMC_ETH_MAC_GetRxBuffer(XMC_ETH_MAC_t *const eth_mac) +{ + return (uint8_t *)(eth_mac->rx_desc[eth_mac->rx_index].buffer1); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param size Size of buffer + * @return None + * + * \parDescription:
+ * Sets the current TX buffer size. + */ +__STATIC_INLINE void XMC_ETH_MAC_SetTxBufferSize(XMC_ETH_MAC_t *const eth_mac, uint32_t size) +{ + eth_mac->tx_desc[eth_mac->tx_index].length = size; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param event A valid ETH PMT event (XMC_ETH_MAC_PMT_EVENT_t) or a valid combination + * of logically OR'd events + * @return None + * + * \parDescription:
+ * Enable power management event(s)
+ * + * \par + * The function enables the event(s) that trigger(s) a PMT interrupt. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnablePowerManagmentEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event) +{ + eth_mac->regs->PMT_CONTROL_STATUS |= (uint32_t)event; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param event A valid ETH PMT event (XMC_ETH_MAC_PMT_EVENT_t) or a valid combination + * of logically OR'd events + * @return None + * + * \parDescription:
+ * Disable power management event(s)
+ * + * \par + * The function disables the event(s) that trigger(s) a PMT interrupt. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisablePowerManagmentEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event) +{ + eth_mac->regs->PMT_CONTROL_STATUS &= ~(uint32_t)event; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param filter wake-up filter registers + * @return None + * + * \parDescription:
+ * Set wakeup frame filter
+ * + * \par + * The function populates the remote wakeup frame registers. + */ +void XMC_ETH_MAC_SetWakeUpFrameFilter(XMC_ETH_MAC_t *const eth_mac, + const uint32_t (*const filter)[XMC_ETH_WAKEUP_REGISTER_LENGTH]); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return bool true if the received packet is a magic packet, false otherwise + * + * \parDescription:
+ * Is magic packet received?
+ * + * \par + * The function checks if the packet received is a magic packet. + */ +__STATIC_INLINE bool XMC_ETH_MAC_IsMagicPacketReceived(XMC_ETH_MAC_t *const eth_mac) +{ + return (bool)(eth_mac->regs->PMT_CONTROL_STATUS & (uint32_t)ETH_PMT_CONTROL_STATUS_MGKPRCVD_Msk); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return bool true if the received packet is a wakeup frame, false otherwise + * + * \parDescription:
+ * Is wakeup frame received?
+ * + * \par + * The function checks if the packet received is a wakeup frame. + */ +__STATIC_INLINE bool XMC_ETH_MAC_IsWakeupFrameReceived(XMC_ETH_MAC_t *const eth_mac) +{ + return (bool)(eth_mac->regs->PMT_CONTROL_STATUS & (uint32_t)ETH_PMT_CONTROL_STATUS_RWKPRCVD_Msk); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enable power down mode
+ * + * \par + * The function enables the power down mode of the ETH MAC. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnablePowerDownMode(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->PMT_CONTROL_STATUS |= (uint32_t)ETH_PMT_CONTROL_STATUS_PWRDWN_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disable power down mode
+ * + * \par + * The function disables the power down mode of the ETH MAC. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisablePowerDownMode(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->PMT_CONTROL_STATUS &= ~(uint32_t)ETH_PMT_CONTROL_STATUS_PWRDWN_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param tag The (16 bit) VLAN tag to set + * @return None + * + * \parDescription:
+ * Set VLAN tag
+ * + * \par + * The function sets the VLAN tag to identify the VLAN frames. + */ +void XMC_ETH_MAC_SetVLANTag(XMC_ETH_MAC_t *const eth_mac, uint16_t tag); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param config The configuration the PTP should be configured with + * @return None + * + * \parDescription:
+ * Initialize PTP
+ * + * \par + * The function can be used to initialize PTP. + */ +void XMC_ETH_MAC_InitPTP(XMC_ETH_MAC_t *const eth_mac, uint32_t config); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param config Configuration of PTP module. See ::XMC_ETH_MAC_TIMESTAMP_CONFIG_t + * @param time Initialization time + * @return None + * + * \parDescription:
+ * Initialize PTP
+ * + * \par + * The function can be used to initialize PTP given a time parameter in addition + */ +void XMC_ETH_MAC_InitPTPEx(XMC_ETH_MAC_t *const eth_mac, uint32_t config, XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the PTP time + * @return None + * + * \parDescription:
+ * Get PTP time
+ * + * \par + * The function obtains the PTP time and writes the nanoseconds and seconds info + * to the 'time' argument. + */ +void XMC_ETH_MAC_GetPTPTime(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the PTP time + * @return None + * + * \parDescription:
+ * Get PTP time
+ * + * \par + * The function sets the PTP time give by the time parameter + */ +void XMC_ETH_MAC_SetPTPTime(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the PTP time + * @return None + * + * \parDescription:
+ * Update PTP time
+ * + * \par + * The function updates the PTP time with the nanoseconds and seconds info contained in + * the 'time' argument. + */ +void XMC_ETH_MAC_UpdatePTPTime(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the PTP time + * @return None + * + * \parDescription:
+ * Set PTP alarm
+ * + * \par + * The function programs the TARGET_TIME_NANOSECONDS and TARGET_TIME_SECONDS registers. It can + * be used to schedule an interrupt event triggered when the set alarm time limit is reached. + */ +void XMC_ETH_MAC_SetPTPAlarm(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Enables timestamp interrupt
+ * + * \par + * The timestamp interrupt is generated when the System Time becomes greater than the value written + * in the Target Time register (Alarm). After the generation of the Timestamp Trigger Interrupt, the interrupt is disabled. + */ +__STATIC_INLINE void XMC_ETH_MAC_EnablePTPAlarm(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSTRIG_Msk; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
+ * Disables timestamp interrupt
+ * + * \par + * The timestamp interrupt is generated when the System Time becomes greater than the value written + * in the Target Time register (Alarm). After the generation of the Timestamp Trigger Interrupt, the interrupt is disabled. + */ +__STATIC_INLINE void XMC_ETH_MAC_DisablePTPAlarm(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->TIMESTAMP_CONTROL &= (uint32_t)~ETH_TIMESTAMP_CONTROL_TSTRIG_Msk; +} + + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param addend Addend value + * @return None + * + * \parDescription:
+ * Adjust PTP clock
+ * + * \par + * The function is used to adjust the PTP clock (time synchronization) to compensate a reference clock drift. + */ +void XMC_ETH_MAC_UpdateAddend(XMC_ETH_MAC_t *const eth_mac, uint32_t addend); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param correction Correction factor + * @return None + * + * \parDescription:
+ * Adjust PTP clock
+ * + * \par + * The function can be used to adjust the PTP clock (time synchronization). Please see the + * function implementation for more information. + */ +void XMC_ETH_MAC_AdjustPTPClock(XMC_ETH_MAC_t *const eth_mac, uint32_t correction); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return uint32_t Timestamp status + * + * \parDescription:
+ * Get PTP status
+ * + * \par + * The function returns the timestamp status by reading the TIMESTAMP_STATUS register. + * As indicated in the reference manual, all bits of the TIMESTAMP_STATUS register (except + * bits [27:25]) are cleared after the invocation of this function. + */ +uint32_t XMC_ETH_MAC_GetPTPStatus(const XMC_ETH_MAC_t *const eth_mac); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the RX timestamp + * @return XMC_ETH_MAC_STATUS_t ETH MAC status + * + * \parDescription:
+ * Get RX timestamp
+ * + * \par + * The function can be used to get the RX timestamp. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_GetRxTimeStamp(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param time A constant pointer to XMC_ETH_MAC_TIME_t, pointing to the TX timestamp + * @return XMC_ETH_MAC_STATUS_t ETH MAC status + * + * \parDescription:
+ * Get TX timestamp
+ * + * \par + * The function can be used to get the TX timestamp. + */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_GetTxTimeStamp(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param event Which event (or a combination of logically OR'd events) needs to be enabled? + * @return None + * + * \parDescription:
+ * Enable ETH MAC event(s)
+ * + * \par + * The function can be used to enable ETH MAC event(s). + */ +void XMC_ETH_MAC_EnableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param event Which event (or a combination of logically OR'd events) needs to be disabled? + * @return None + * + * \parDescription:
+ * Disable an ETH MAC event(s)
+ * + * \par + * The function can be used to disable ETH MAC event(s). + */ +void XMC_ETH_MAC_DisableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param event The status of which event (or a combination of logically OR'd events) needs to be cleared + * @return None + * + * \parDescription:
+ * Clear event status
+ * + * \par + * The function clears the status of an event passed as a parameter to the function. + */ +void XMC_ETH_MAC_ClearEventStatus(XMC_ETH_MAC_t *const eth_mac, uint32_t event); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return uint32_t Event status + * + * \parDescription:
+ * Get event status
+ * + * \par + * The function returns the ETH status and interrupt status as a single word. The user + * can then check the status of the events by using an appropriate mask. + */ +uint32_t XMC_ETH_MAC_GetEventStatus(const XMC_ETH_MAC_t *const eth_mac); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (ETH0) */ + +#endif /* XMC_ETH_MAC_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eth_mac_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eth_mac_map.h new file mode 100644 index 00000000..eb41fb92 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eth_mac_map.h @@ -0,0 +1,166 @@ +/** + * @file xmc_eth_mac_map.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial
+ * + * @endcond + */ + +#ifndef XMC_ETH_MAC_MAP_H +#define XMC_ETH_MAC_MAP_H + +/** + * ETH MAC interface mode + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_MODE +{ + XMC_ETH_MAC_PORT_CTRL_MODE_MII = 0x0U, /**< MII mode */ + XMC_ETH_MAC_PORT_CTRL_MODE_RMII = 0x1U /**< RMII mode */ +} XMC_ETH_MAC_PORT_CTRL_MODE_t; + +/** + * ETH MAC receive data 0 line + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_RXD0 +{ + XMC_ETH_MAC_PORT_CTRL_RXD0_P2_2 = 0U, /**< RXD0A receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD0_P0_2 = 1U, /**< RXD0B receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD0_P14_8 = 2U, /**< RXD0C receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD0_P5_0 = 3U /**< RXD0D receive data line */ +} XMC_ETH_MAC_PORT_CTRL_RXD0_t; + +/** + * ETH MAC receive data 1 line + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_RXD1 +{ + XMC_ETH_MAC_PORT_CTRL_RXD1_P2_3 = 0U, /**< RXD1A receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD1_P0_3 = 1U, /**< RXD1B receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD1_P14_9 = 2U, /**< RXD1C receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD1_P5_1 = 3U /**< RXD1D receive data line */ +} XMC_ETH_MAC_PORT_CTRL_RXD1_t; + +/** + * ETH MAC receive data 2 line + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_RXD2 +{ + XMC_ETH_MAC_PORT_CTRL_RXD2_P5_8 = 0U, /**< RXD2A receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD2_P6_4 = 1U /**< RXD2B receive data line */ +} XMC_ETH_MAC_PORT_CTRL_RXD2_t; + +/** + * ETH MAC receive data 3 line + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_RXD3 +{ + XMC_ETH_MAC_PORT_CTRL_RXD3_P5_9 = 0U, /**< RXD3A Receive data line */ + XMC_ETH_MAC_PORT_CTRL_RXD3_P6_3 = 1U /**< RXD3B Receive data line */ +} XMC_ETH_MAC_PORT_CTRL_RXD3_t; + +/** + * ETH MAC PHY clock + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_RMII +{ + XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P2_1 = 0U, /**< XMC_ETH_RMIIA PHY clock */ + XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P0_0 = 1U, /**< XMC_ETH_RMIIB PHY clock */ + XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P15_8 = 2U, /**< XMC_ETH_RMIIC PHY clock */ + XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P6_5 = 3U /**< XMC_ETH_RMIID PHY clock */ +} XMC_ETH_MAC_PORT_CTRL_CLK_RMII_t; + +/** + * ETH MAC carrier sense data valid + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_CRS_DV +{ + XMC_ETH_MAC_PORT_CTRL_CRS_DV_P2_5 = 0U, /**< XMC_ETH_CRS_DVA carrier sense data valid */ + XMC_ETH_MAC_PORT_CTRL_CRS_DV_P0_1 = 1U, /**< XMC_ETH_CRS_DVB carrier sense data valid */ + XMC_ETH_MAC_PORT_CTRL_CRS_DV_P15_9 = 2U, /**< XMC_ETH_CRS_DVC carrier sense data valid */ + XMC_ETH_MAC_PORT_CTRL_CRS_DV_P5_2 = 3U /**< XMC_ETH_CRS_DVD carrier sense data valid */ +} XMC_ETH_MAC_PORT_CTRL_CRS_DV_t; + +/** + * ETH MAC carrier sense + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_CRS +{ + XMC_ETH_MAC_PORT_CTRL_CRS_P5_11 = 0U, /**< XMC_ETH_CRSA carrier sense */ + XMC_ETH_MAC_PORT_CTRL_CRS_P5_4 = 3U /**< XMC_ETH_CRSD carrier sense */ +} XMC_ETH_MAC_PORT_CTRL_CRS_t; + +/** + * ETH MAC receive error + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_RXER +{ + XMC_ETH_MAC_PORT_CTRL_RXER_P2_4 = 0U, /**< XMC_ETH_RXERA carrier sense */ + XMC_ETH_MAC_PORT_CTRL_RXER_P0_11 = 1U, /**< XMC_ETH_RXERB carrier sense */ + XMC_ETH_MAC_PORT_CTRL_RXER_P5_3 = 3U /**< XMC_ETH_RXERD carrier sense */ +} XMC_ETH_MAC_PORT_CTRL_RXER_t; + +/** + * ETH MAC collision detection + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_COL +{ + XMC_ETH_MAC_PORT_CTRL_COL_P2_15 = 0U, /**< XMC_ETH_COLA collision detection */ + XMC_ETH_MAC_PORT_CTRL_COL_P5_5 = 3U /**< XMC_ETH_COLD collision detection */ +} XMC_ETH_MAC_PORT_CTRL_COL_t; + +/** + * ETH PHY transmit clock + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_TX +{ + XMC_ETH_MAC_PORT_CTRL_CLK_TX_P5_10 = 0U, /**< XMC_ETH_CLK_TXA PHY transmit clock */ + XMC_ETH_MAC_PORT_CTRL_CLK_TX_P6_6 = 1U /**< XMC_ETH_CLK_TXB PHY transmit clock */ +} XMC_ETH_MAC_PORT_CTRL_CLK_TX_t; + +/** + * ETH management data I/O + */ +typedef enum XMC_ETH_MAC_PORT_CTRL_MDIO +{ + XMC_ETH_MAC_PORT_CTRL_MDIO_P0_9 = 0U, /**< XMC_ETH_MDIOA management data I/O */ + XMC_ETH_MAC_PORT_CTRL_MDIO_P2_0 = 1U, /**< XMC_ETH_MDIOB management data I/O */ + XMC_ETH_MAC_PORT_CTRL_MDIO_P1_11 = 2U /**< XMC_ETH_MDIOC management data I/O */ +} XMC_ETH_MAC_PORT_CTRL_MDIO_t; + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eth_phy.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eth_phy.h new file mode 100644 index 00000000..081370e4 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_eth_phy.h @@ -0,0 +1,222 @@ +/** + * @file xmc_eth_phy.h + * @date 2015-12-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * + * 2015-12-15: + * - Added XMC_ETH_PHY_ExitPowerDown and XMC_ETH_PHY_Reset + * + * @endcond + */ + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup ETH_PHY + * @brief Ethernet PHY driver for XMC4000 microcontroller family. + * + * The XMC_ETH_PHY low level driver provides functions used by XMC_ETH_MAC. + * @{ + */ + +#ifndef XMC_ETH_PHY_H +#define XMC_ETH_PHY_H + +/******************************************************************************* + * INCLUDES + *******************************************************************************/ + +#include + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * ETH PHY status returns + */ +typedef enum XMC_ETH_PHY_STATUS +{ + XMC_ETH_PHY_STATUS_OK = 0U, /**< OK. All is well! */ + XMC_ETH_PHY_STATUS_BUSY = 1U, /**< Busy */ + XMC_ETH_PHY_STATUS_ERROR = 2U, /**< Error */ + XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID = 3U, /**< Error in device identifier */ + XMC_ETH_PHY_STATUS_ERROR_TIMEOUT = 4U /**< Time-out error */ +} XMC_ETH_PHY_STATUS_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ + +/** + * ETH PHY configuration + */ +typedef struct XMC_ETH_PHY_CONFIG +{ + XMC_ETH_LINK_INTERFACE_t interface; /**< Link interface */ + XMC_ETH_LINK_SPEED_t speed; /**< ETH speed: 100M or 10M? */ + XMC_ETH_LINK_DUPLEX_t duplex; /**< Half or full duplex? */ + bool enable_auto_negotiate; /**< Enable auto-negotiate? */ + bool enable_loop_back; /**< Enable loop-back? */ +} XMC_ETH_PHY_CONFIG_t; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @param config A constant pointer to XMC_ETH_PHY_CONFIG_t, pointing to a physical layer config + * @return int32_t return status XMC_ETH_PHY_STATUS_t + * + * \parDescription:
+ * Initialize the ETH physical layer interface
+ * + * \par + * The function sets the link speed, applies the duplex mode, sets auto-negotiation + * and loop-back settings. + */ +int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return int32_t return status XMC_ETH_PHY_STATUS_t + * + * \parDescription:
+ * Enter power down mode
+ * + */ +int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return int32_t return status XMC_ETH_PHY_STATUS_t + * + * \parDescription:
+ * Exit power down mode
+ * + */ +int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return int32_t return status XMC_ETH_PHY_STATUS_t + * + * \parDescription:
+ * Reset transciver
+ * + */ +int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return XMC_ETH_LINK_STATUS_t ETH link status + * + * \parDescription:
+ * Get link status
+ * + * \par + * The function reads the physical layer interface and returns the link status. + * It returns either ::XMC_ETH_LINK_STATUS_UP or ::XMC_ETH_LINK_STATUS_DOWN. + */ +XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return XMC_ETH_LINK_SPEED_t ETH link speed + * + * \parDescription:
+ * Get link speed
+ * + * \par + * The function reads the physical layer interface and returns the link speed. + * It returns either ::XMC_ETH_LINK_SPEED_100M or ::XMC_ETH_LINK_SPEED_10M. + */ +XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return XMC_ETH_LINK_DUPLEX_t ETH link duplex settings + * + * \parDescription:
+ * Get link duplex settings
+ * + * \par + * The function reads the physical layer interface and returns the link duplex settings. + * It returns either ::XMC_ETH_LINK_DUPLEX_FULL or ::XMC_ETH_LINK_DUPLEX_HALF. + */ +XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param phy_addr Physical address + * @return bool True if autonegotiation process is finished otherwise false + * + * \parDescription:
+ * Get status of autonegotiation
+ */ +bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XMC_ETH_PHY_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_fce.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_fce.h new file mode 100644 index 00000000..08d52888 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_fce.h @@ -0,0 +1,697 @@ +/** + * @file xmc_fce.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial + * + * 2015-05-20: + * - Description updated
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * @endcond + * + */ + +#ifndef XMC_FCE_H +#define XMC_FCE_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ + +#include + +#if defined (FCE) + +/** + * @addtogroup XMClib + * @{ + */ + +/** + * @addtogroup FCE + * @brief Flexible CRC Engine(FCE) driver for the XMC microcontroller family. + * + * The FCE provides a parallel implementation of Cyclic Redundancy Code (CRC) + * algorithms. The current FCE version for the XMC4000 microcontroller family implements the + * IEEE 802.3 ethernet CRC32, the CCITT CRC16 and the SAE J1850 CRC8 polynomials. + * The primary target of FCE is to be used as an hardware acceleration engine for software + * applications or operating systems services using CRC signatures. + * + * @image html fce_overview.png + * @image latex ../images/fce_overview.png + * FCE Features:
+ * @image html fce_polynomials.png + * @image latex ../images/fce_polynomials.png + * * CRC kernel 0 and 1: IEEE 802.3 CRC32 ethernet polynomial: 0x04C11DB71
+ * * CRC kernel 2: CCITT CRC16 polynomial: 0x1021
+ * * CRC kernel 3: SAE J1850 CRC8 polynomial: 0x1D
+ * * Configuration Registers enable to control the CRC operation and perform automatic checksum checks at + * the end of a message.
+ * * Extended register interface to control reliability of FCE execution in safety applications.
+ * * Error notification scheme via dedicated interrupt node for:
+ a)Transient error detection: Error interrupt generation (maskable) with local status register + (cleared by software)
+ b)Checksum failure: Error interrupt generation (maskable) with local status register (cleared by software)
+ + FCE provides one interrupt line to the interrupt system. Each CRC engine has its own set of flag registers.
+ + * @{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +#define XMC_FCE_CRC32_0 FCE_KE0 /**< Kernel 0
*/ +#define XMC_FCE_CRC32_1 FCE_KE1 /**< Kernel 1
*/ +#define XMC_FCE_CRC16 FCE_KE2 /**< Kernel 2
*/ +#define XMC_FCE_CRC8 FCE_KE3 /**< Kernel 3
*/ + +#define XMC_FCE_REFIN_SET (1U) /**< Enables input reflection */ +#define XMC_FCE_REFIN_RESET (0U) /**< Disables input reflection */ +#define XMC_FCE_REFOUT_SET (1U) /**< Enables output reflection */ +#define XMC_FCE_REFOUT_RESET (0U) /**< Disables output reflection */ +#define XMC_FCE_INVSEL_SET (1U) /**< Enables output inversion */ +#define XMC_FCE_INVSEL_RESET (0U) /**< Disables output inversion */ + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + +/** + * FCE interrupt configuration + */ +typedef enum XMC_FCE_CONFIG_INTERRUPT +{ + XMC_FCE_CFG_CONFIG_CMI = FCE_KE_CFG_CMI_Msk, /**< Enables CRC Mismatch interrupt \n*/ + XMC_FCE_CFG_CONFIG_CEI = FCE_KE_CFG_CEI_Msk, /**< Enables Configuration error interrupt \n*/ + XMC_FCE_CFG_CONFIG_LEI = FCE_KE_CFG_LEI_Msk, /**< Enables Length error interrupt \n*/ + XMC_FCE_CFG_CONFIG_BEI = FCE_KE_CFG_BEI_Msk /**< Enables Bus error interrupt \n*/ +} XMC_FCE_CONFIG_INTERRUPT_t; + +/** + * FCE operation configuration + */ +typedef enum XMC_FCE_CONFIG_OPERATION +{ + XMC_FCE_CFG_CONFIG_CCE = FCE_KE_CFG_CCE_Msk, /**< Enables CRC check */ + XMC_FCE_CFG_CONFIG_ALR = FCE_KE_CFG_ALR_Msk /**< Enables Automatic length reload */ +} XMC_FCE_CONFIG_OPERATION_t; + +/** + * FCE algorithm configuration + */ +typedef enum XMC_FCE_CONFIG_ALGO +{ + XMC_FCE_CFG_CONFIG_REFIN = FCE_KE_CFG_REFIN_Msk, /**< Enables input byte reflection */ + XMC_FCE_CFG_CONFIG_REFOUT = FCE_KE_CFG_REFOUT_Msk, /**< Enables Final CRC reflection */ + XMC_FCE_CFG_CONFIG_XSEL = FCE_KE_CFG_XSEL_Msk /**< Enables output inversion */ +} XMC_FCE_CONFIG_ALGO_t; + +/** + * FCE status flag configuration + */ +typedef enum XMC_FCE_STS_FLAG +{ + XMC_FCE_STS_MISMATCH_CRC = FCE_KE_STS_CMF_Msk, /**< CRC Mismatch flag */ + XMC_FCE_STS_CONFIG_ERROR = FCE_KE_STS_CEF_Msk, /**< Configuration Error flag */ + XMC_FCE_STS_LENGTH_ERROR = FCE_KE_STS_LEF_Msk, /**< Length Error flag */ + XMC_FCE_STS_BUS_ERROR = FCE_KE_STS_BEF_Msk /**< Bus Error flag */ +} XMC_FCE_STS_FLAG_t; + +/** + * FCE control configuration + */ +typedef enum XMC_FCE_CTR_TEST +{ + XMC_FCE_CTR_MISMATCH_CRC = FCE_KE_CTR_FCM_Msk, /**< Forces CRC mismatch */ + XMC_FCE_CTR_MISMATCH_CFG = FCE_KE_CTR_FRM_CFG_Msk, /**< Forces CFG Register mismatch */ + XMC_FCE_CTR_MISMATCH_CHECK = FCE_KE_CTR_FRM_CHECK_Msk /**< Forces CRC Check Register mismatch */ +} XMC_FCE_CTR_TEST_t; + +/** + * FCE status enumeration + */ +typedef enum XMC_FCE_STATUS +{ + XMC_FCE_STATUS_OK = 0, /**< Returns OK on success */ + XMC_FCE_STATUS_BUSY, /**< Returns BUSY when API is busy with a previous request */ + XMC_FCE_STATUS_ERROR /**< Returns ERROR when API cannot fulfil request */ +} XMC_FCE_STATUS_t; + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ + +/** + * FCE kernel + */ +typedef FCE_KE_TypeDef XMC_FCE_Kernel_t; + +/* Anonymous structure/union guard start */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__TASKING__) + #pragma warning 586 +#endif + +/** + * @brief XMC_FCE configuration structure + */ +typedef struct XMC_FCE_CONFIG +{ + union + { + uint32_t regval; + struct + { + uint32_t : 8; + uint32_t config_refin : 1; /**< Enables byte-wise reflection */ + uint32_t config_refout : 1; /**< Enables bit-wise reflection */ + uint32_t config_xsel : 1; /**< Enables output inversion */ + uint32_t : 21; /**< Reserved bits */ + }; + }; +} XMC_FCE_CONFIG_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__TASKING__) + #pragma warning restore +#endif + +/** + * FCE handler + */ +typedef struct XMC_FCE +{ + XMC_FCE_Kernel_t *kernel_ptr; /**< FCE Kernel Pointer */ + XMC_FCE_CONFIG_t fce_cfg_update; /**< FCE CFG register update */ + uint32_t seedvalue; /**< CRC seed value to be used */ +} XMC_FCE_t; + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param None + * @return uint32_t Module revision number + * + * \parDescription:
+ * Read FCE module revision number
+ * + * \par + * The value of a module revision starts with 0x01 (first revision). The current revision + * number is 0x01. + */ +__STATIC_INLINE uint32_t XMC_FCE_ReadModuleRev(void) +{ + return (uint32_t)(FCE->ID & FCE_ID_MOD_REV_Msk); +} + +/** + * @param None + * @return uint32_t Module type + * + * \parDescription:
+ * Read the FCE module type
+ * + * \par + * The return value is currently 0xC0. It defines the module as a 32-bit module. + */ +__STATIC_INLINE uint32_t XMC_FCE_ReadModuleType(void) +{ + return (uint32_t)((FCE->ID & FCE_ID_MOD_TYPE_Msk) >> FCE_ID_MOD_TYPE_Pos); +} + +/** + * @param None + * @return uint32_t Module number + * + * \parDescription:
+ * Read FCE module number
+ * + * \par + * The return value for FCE module is currently 0x00CA. + */ +__STATIC_INLINE uint32_t XMC_FCE_ReadModuleNumber(void) +{ + return ((uint32_t)((FCE->ID & FCE_ID_MOD_NUMBER_Msk) >> FCE_ID_MOD_NUMBER_Pos)); +} + +/** + * @param None + * @return bool Disable status + * + * + * \parDescription:
+ * Return the disable status
+ * + * \par + * The function reads the FCE module disable status (DISS) bit. It returns "true" if + * set, "false" otherwise. + */ +__STATIC_INLINE bool XMC_FCE_Get_DisableStatus(void) +{ + return (bool)(FCE->CLC &= (uint32_t)~FCE_CLC_DISS_Msk); +} + +/** + * @param None + * @return None + * + * \parDescription:
+ * Disable the FCE module
+ * + * \par + * The function asserts the FCE peripheral reset and sets the DISR bit in the CLC + * register. + * + * \parNote:
+ * All pending transactions running on the bus slave interface must be completed before + * entering the disabled state. + */ +void XMC_FCE_Disable(void); + +/** + * @param None + * @return None + * + * \parDescription:
+ * Enable the FCE module
+ * + * \par + * The function de-asserts the peripheral reset and clears the DISR bit CLC register. + */ +void XMC_FCE_Enable(void); + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @return ::XMC_FCE_STATUS_t + * + * \parDescription:
+ * Initialize the FCE engine
+ * + * \par + * The function sets to the CFG and CRC registers with the FCE configuration and + * seeds values. The function always returns XMC_FCE_STATUS_SUCCESS. + * + * \parNote:
+ * The software must first ensure that the CRC kernel is properly configured with the + * initial CRC value (seed value). + */ +XMC_FCE_STATUS_t XMC_FCE_Init(const XMC_FCE_t *const engine); + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param seedvalue Initial CRC value + * @return None + * + * \parDescription:
+ * Initialize FCE seed value + * + * \par + * The function sets the initial CRC (seed) value in the CRC register. + */ +__STATIC_INLINE void XMC_FCE_InitializeSeedValue(const XMC_FCE_t *const engine, uint32_t seedvalue) +{ + engine->kernel_ptr->CRC = seedvalue; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param event OR'd values of ::XMC_FCE_CONFIG_INTERRUPT_t enumeration values + * @return None + * + * \parDescription:
+ * Enable FCE event(s)
+ * + * \par + * The function sets the CFG register to enable FCE event(s). + */ +__STATIC_INLINE void XMC_FCE_EnableEvent(const XMC_FCE_t *const engine, uint32_t event) +{ + engine->kernel_ptr->CFG |= (uint32_t)event; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param event OR'd values of ::XMC_FCE_CONFIG_INTERRUPT_t enumeration values + * @return None + * + * \parDescription:
+ * Disable FCE event(s)
+ * + * \par + * The function clears the CFG register to disable FCE event(s). + */ +__STATIC_INLINE void XMC_FCE_DisableEvent(const XMC_FCE_t *const engine, uint32_t event) +{ + engine->kernel_ptr->CFG &= ~(uint32_t)event; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param event Event of type ::XMC_FCE_STS_FLAG_t + * @return bool + * + * \parDescription:
+ * Return the event status of FCE event
+ * + * \par + * The function returns the status of a single requested FCE event by reading the + * appropriate bit-fields of the STS register. + */ +__STATIC_INLINE bool XMC_FCE_GetEventStatus(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event) +{ + return (bool) (engine->kernel_ptr->STS & (uint32_t)event); +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param event Event of type ::XMC_FCE_STS_FLAG_t + * @return None + * + * \parDescription:
+ * Clear an FCE event
+ * + * \par + * The function clears requested FCE events by setting the bit-fields of the STS + * register. + */ +__STATIC_INLINE void XMC_FCE_ClearEvent(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event) +{ + engine->kernel_ptr->STS |= (uint32_t)event; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param operation FCE operation of type ::XMC_FCE_CONFIG_OPERATION_t + * @return None + * + * \parDescription:
+ * Enable CRC operations
+ * + * \par + * The function enables FRC operations by writing to the CFG register. + * + * \parNote:
+ * CRC comparison check (at the end of message) can be enabled using the CCE bit-field. + * Automatic reload of LENGTH field (at the end of message) can be enabled using the + * ALR bit field. + */ +__STATIC_INLINE void XMC_FCE_EnableOperation(const XMC_FCE_t *const engine, uint32_t operation) +{ + engine->kernel_ptr->CFG |= operation; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param operation FCE operation of type ::XMC_FCE_CONFIG_OPERATION_t + * @return None + * + * \parDescription:
+ * Disable CRC operations
+ * + * \par + * The function disables FRC operations by writing to the CFG register. + * + * \parNote:
+ * CRC comparison check (at the end of message) can be disabled using the CCE bit-field. + * Automatic reload of LENGTH field (at the end of message) can be disabled using the + * ALR bit field. + */ +__STATIC_INLINE void XMC_FCE_DisableOperation(const XMC_FCE_t *const engine, uint32_t operation) +{ + engine->kernel_ptr->CFG &= ~(uint32_t)operation; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param algo A valid algorithm of type ::XMC_FCE_CONFIG_ALGO_t or a valid combination + * of logically OR'd algorithms + * @return None + * + * \parDescription:
+ * Enables CRC algorithm(s)
+ * + * \parNote:
+ * Options for enabling CRC algorithm:
+ * REFIN: Input byte wise reflection
+ * REFOUT: Output bit wise reflection
+ * XSEL: Value to be XORed with final CRC
+ */ +__STATIC_INLINE void XMC_FCE_EnableCRCAlgorithm(const XMC_FCE_t *const engine, uint32_t algo) +{ + engine->kernel_ptr->CFG |= (uint32_t)algo; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param algo A valid algorithm of type ::XMC_FCE_CONFIG_ALGO_t or a valid combination + * of logically OR'd algorithms + * @return None + * + * \parDescription:
+ * Disable CRC algorithm(s)
+ * + * \parNote:
+ * Options for disabling CRC algorithm:
+ * REFIN: Input byte wise reflection
+ * REFOUT: Output bit wise reflection
+ * XSEL: Value to be XORed with final CRC
+ */ +__STATIC_INLINE void XMC_FCE_DisableCRCAlgorithm(const XMC_FCE_t *const engine, uint32_t algo) +{ + engine->kernel_ptr->CFG &= ~(uint32_t)algo; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param checkvalue Checksum value + * @return None + * + * \parDescription:
+ * Updates CRC check value
+ * + * \par + * When the CFG.CCE bit field is set, every time the IR register is written, the + * LENGTH register is decremented by one until it reaches zero. The hardware monitors + * the transition of the LENGTH register from 1 to 0 to detect the end of the + * message and proceed with the comparison of the result register (RES) value with + * the CHECK register value. + */ +__STATIC_INLINE void XMC_FCE_UpdateCRCCheck(const XMC_FCE_t *const engine, const uint32_t checkvalue) +{ + engine->kernel_ptr->CHECK = 0xFACECAFEU; + engine->kernel_ptr->CHECK = checkvalue; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param checklength Checksum length + * @return None
+ * + * \parDescription:
+ * Updates CRC length specified in the input parameter
+ * + * \par + * When the ALR bit field is set to 1, every write to the IR register decrements + * the value of the LENGTH bit field. The LENGTH field shall be reloaded with its + * configuration value at the end of the cycle where LENGTH reaches 0. + */ +__STATIC_INLINE void XMC_FCE_UpdateLength(const XMC_FCE_t *const engine, const uint32_t checklength) +{ + engine->kernel_ptr->LENGTH = 0xFACECAFEU; + engine->kernel_ptr->LENGTH = checklength; +} + +/** + * @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address + * @param data Pointer to the data buffer + * @param length Total number of bytes of data buffer + * @param result Pointer to computed CRC result + * @return XMC_FCE_STATUS_ERROR on error + * @return XMC_FCE_STATUS_SUCCESS otherwise. + * + * \parDescription:
+ * Calculate and updates the CRC8 checksum in the result pointer
+ * + * \parNote:
+ * A write to IRm (m = 3) triggers the CRC kernel to update the message checksum + * according to the IR and current CRC register contents. Any write transaction + * is allowed to this IRm register. Only the lower 8-bit of the write transactions + * will be used. ::XMC_FCE_GetCRCResult() should be called after invoking + * ::XMC_FCE_CalculateCRC8() to get final CRC value. + */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine, + const uint8_t *data, + uint32_t length, + uint8_t *result); + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param data Pointer to the data buffer + * @param length Length of data buffer + * @param result Pointer to computed CRC result + * @return XMC_FCE_STATUS_ERROR on error + * @return XMC_FCE_STATUS_SUCCESS otherwise. + * + * \parDescription:
+ * Calculate and update the RC16 checksum in the result pointer
+ * + * \parNote:
+ * A write to Internal Register (IRm m = 2) triggers the CRC kernel to update the + * message checksum according to the IR and current CRC register contents. Only 32-bit + * or 16-bit write transactions are permitted. Any other bus write transaction will + * lead to a bus error. Only the lower 16-bit of the write transactions will be used. + * ::XMC_FCE_GetCRCResult() should be called after ::XMC_FCE_CalculateCRC16() to get + * final CRC value. + */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine, + const uint16_t *data, + uint32_t length, + uint16_t *result); + +/** + * @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address + * @param data Pointer to the data buffer + * @param length Total number of bytes of data buffer + * @param result Pointer to computed CRC result + * @return XMC_FCE_STATUS_ERROR on error + * @return XMC_FCE_STATUS_SUCCESS otherwise. + * + * \parDescription
+ * Calculate and update the calculated CRC32 checksum in the result pointer
+ * + * \parNote:
+ * A write to Internal Register (IRm, m = 0-1) triggers the CRC kernel to update + * the message checksum according to the IR and current CRC register contents. Only + * 32-bit write transactions are permitted. Any other bus write transaction will + * lead to a bus error. ::XMC_FCE_GetCRCResult() should be called after + * ::XMC_FCE_CalculateCRC32() to get final CRC value. + */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine, + const uint32_t *data, + uint32_t length, + uint32_t *result); + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param result Pointer to CRC result + * @return None + * + * \parDescription:
+ * Read the final CRC value from RES register
+ */ +__STATIC_INLINE void XMC_FCE_GetCRCResult(const XMC_FCE_t *const engine, uint32_t *result) +{ + *result= engine->kernel_ptr->RES; +} + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param test values of type ::XMC_FCE_CTR_TEST_t + * @return None + * + * \parDescription:
+ * Trigger the CTR register to generate a CRC mismatch/register mismatch/check register + * mismatch interrupt
+ */ +void XMC_FCE_TriggerMismatch(const XMC_FCE_t *const engine, XMC_FCE_CTR_TEST_t test); + +/** + * @param inbuffer Pointer to input data buffer + * @param outbuffer Pointer to the output data buffer + * @param length Length of the input buffer + * @return None + * + * \parDescription:
+ * Convert input data buffer's endianness from big endian to little endian
+ * + * \par + * The function stores the converted data in output data buffer. + * + * \parNote:
+ * This function should be invoked before using ::XMC_FCE_CalculateCRC16() to compute + * the CRC value. + */ +void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t length); + +/** + * @param inbuffer Pointer to input data buffer + * @param outbuffer Pointer to the output data buffer + * @param length Length of the input buffer + * @return None + * + * \parDescription:
+ * Convert input data buffer's endianness from big endian to little endian
+ * + * \par + * The function stores the converted data in output data buffer. + * + * \parNote:
+ * This function should be invoked before using ::XMC_FCE_CalculateCRC32() to compute + * the CRC value. + */ +void XMC_FCE_LittleEndian32bit(uint8_t* inbuffer, uint32_t* outbuffer, uint16_t length); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FCE) */ + +#endif /* XMC_FCE_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_flash.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_flash.h new file mode 100644 index 00000000..355dc3b5 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_flash.h @@ -0,0 +1,276 @@ +/** + * @file xmc_flash.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2014-12-10: + * - Initial
+ * 2015-02-20: + * - Updated for Documentation related changes
+ * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * @endcond + * + */ + + +#ifndef XMC_FLASH_H +#define XMC_FLASH_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_common.h" + +#if UC_FAMILY == XMC1 + #include "xmc1_flash.h" +#endif + +#if UC_FAMILY == XMC4 + #include "xmc4_flash.h" +#endif + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup FLASH + * @brief Flash driver for XMC microcontroller family. + * + * Flash is a non volatile memory module used to store instruction code or constant data. + * The flash low level driver provides support to the following functionalities of flash memory.
+ *
    + * \if XMC4 + *
  1. Provides function to program a page. ( XMC_FLASH_ProgramPage() )

    2. + *
  2. Provides functions to support read and write protection. ( XMC_FLASH_InstallProtection(), + * XMC_FLASH_ConfirmProtection(), XMC_FLASH_VerifyReadProtection(), XMC_FLASH_VerifyWriteProtection() )

    3. + *
  3. Provides function to erase sector. ( XMC_FLASH_EraseSector() )

    4. + * \endif + * \if XMC1 + *
  4. Provides functions to program and verify pages. ( XMC_FLASH_ProgramPage(), XMC_FLASH_ProgramPages() + * XMC_FLASH_ProgramVerifyPage() )

    5. + *
  5. Provides functions to write and verify blocks. ( XMC_FLASH_WriteBlocks(), XMC_FLASH_VerifyBlocks() )

    6. + *
  6. Provides functions to read data in terms of word and blocks. ( XMC_FLASH_ReadBlocks(), XMC_FLASH_ReadWord() ) + *

    7. + *
  7. Provides function to erase page. ( XMC_FLASH_ErasePage() )

    8. + * \endif + *
+ * @{ + */ + +/******************************************************************************* + * API PROTOTYPE + *******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + * @param None + * + * @return None + * + * \parDescription:
+ * \if XMC1 + * Clears the previous error status by reseting the ECC and VERR error status bits of NVMSTATUS register.\n\n + * Call this API before starting any flash programming / erase related APIs to ensure all previous errors are cleared. + * \endif + * \if XMC4 + * Clears the previous error status by reseting the FSR status register.\n\n Call this API before starting any flash + * programming / erase related APIs to ensure all previous errors are cleared. + * \endif + * + * \parRelated APIs:
+ * None + * + */ +void XMC_FLASH_ClearStatus(void); + +/** + * + * @param None + * + * @return uint32_t Status of the previous flash operation. + * + * \parDescription:
+ * \if XMC1 + * Informs the status of flash by reading the NVMSTATUS register.\n\n It indicates the ECC, VERR(verification error), + * WRPERR (Write protocol error) errors as well as the current flash state. After calling the flash read/write/erase + * operation related APIs, call this API to get the verification status. The return value of this API shall be checked + * against the members of @ref XMC_FLASH_STATUS_t enumeration to get the relevant status. + * \endif + * \if XMC4 + * Informs the status of flash by reading the FSR register.\n\n It indicates the error status such as PFOPER, SQER, + * PROER, PFDBER, ORIER, VER errors as well as the current flash state. After calling the flash read/write/erase + * operation related APIs, call this API to verify flash status. The return value of this API shall be checked against + * the members of @ref XMC_FLASH_STATUS_t enumeration to get the relevant status. + * \endif + * + * \parRelated APIs:
+ * None + * + */ +uint32_t XMC_FLASH_GetStatus(void); + +/** + * + * @param event_msk ORed values of @ref XMC_FLASH_EVENT_t enumeration + * + * @return None + * + * \parDescription:
+ * Enables the particular flash events as specified in the input parameter.\n + * + * \parRelated APIs:
+ * XMC_FLASH_DisableEvent()\n\n\n + * + */ +void XMC_FLASH_EnableEvent(const uint32_t event_msk); + +/** + * + * @param event_msk ORed values of @ref XMC_FLASH_EVENT_t enumeration + * + * @return None + * + * \parDescription:
+ * Disables the particular flash events as specified in the input parameter.\n + * + * \parRelated APIs:
+ * XMC_FLASH_EnableEvent()\n\n\n + * + */ +void XMC_FLASH_DisableEvent(const uint32_t event_msk); + +/** + * + * @param address Pointer to the starting address of flash page from where the programming starts. + * @param data Pointer to the source address where targeted data is located. + * + * @return None + * + * \parDescription:
+ * \if XMC1 + * Programs a single flash page associated with the specified \a address.\n\n XMC1000 Flash can be programmed with one + * page (256 bytes) using this API. It calls the Flash Firmware routine \a XMC1000_NvmProgVerify(unsigned long pageAddr) + * to perform the programming. Refer XMC1000 reference manual of for more details on flash firmware routines + * (Section 25.3). Call XMC_FLASH_GetStatus() API after calling this API, to verify the programming operation. + * \endif + * \if XMC4 + * Programs a single flash page associated with the specified \a address.\n\n XMC4000 flash can be programmed with a + * granularity of 256 bytes page using this API. Before entering into page write process, it clears the error status + * bits inside status register. It starts the write process by issuing the page mode command followed by the load page + * command which loads the targeted \a data blocks into internal assembly buffer. Finally, it issues the write page + * command which programs the \a data into flash. Call XMC_FLASH_GetStatus() API after calling this API, to verify the + * programming operation.\n + * \endif + * + * \parNote:
+ * Flash will be busy state during write is ongoing, hence no operations allowed until it completes. + * + * \parRelated APIs:
+ * None + * + */ +void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data); + +/** + * + * @param address Pointer to the starting address of the page to be erased. + * + * @return None + * + * \parDescription:
+ * \if XMC1 + * Erases a complete sector starting from the \a address specified.\n\n XMC1000 Flash can be erased with granularity + * of one page = 16 blocks of 16 Bytes = 256 Bytes using this API. It internally calls XMC_FLASH_ErasePages API 16 + * times starting from the first page of the sector.. Call XMC_FLASH_GetStatus() API after calling this API, + * to verify the erase operation.\n + * \endif + * + * \if XMC4 + * Erases a sector associated with the specified \a address.\n\n Before erase, it clears the error status bits inside + * FSR status register. Issues the erase sector command sequence with the specified starting \a address to start flash + * erase process. Call XMC_FLASH_GetStatus() API after calling this API, to verify the erase operation.\n + * \endif + * \if XMC1 + * \parRelated APIs:
+ * XMC_FLASH_ErasePages() \n\n\n + * \endif + * \if XMC4 + * \parRelated APIs:
+ * None + * \endif + */ +void XMC_FLASH_EraseSector(uint32_t *address); + +/** + * + * @param None + * + * @return true if flash is in busy state else returns \a false. + * + * \parDescription:
+ * Checks whether flash is in busy state or not.\n\n It is checked by calling the XMC_FLASH_GetStatus() API internally. + * Refer XMC_FLASH_GetStatus() for more details.\n + * + * \parRelated APIs:
+ * XMC_FLASH_GetStatus()\n\n\n + * + */ +__STATIC_INLINE bool XMC_FLASH_IsBusy(void) +{ + return (bool)(XMC_FLASH_GetStatus() & XMC_FLASH_STATUS_BUSY); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_gpio.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_gpio.h new file mode 100644 index 00000000..671cdc0b --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_gpio.h @@ -0,0 +1,478 @@ +/** + * @file xmc_gpio.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * - Documentation improved
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * @endcond + * + */ + +#ifndef XMC_GPIO_H +#define XMC_GPIO_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_common.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup GPIO + * @brief General Purpose Input Output (GPIO) driver for the XMC microcontroller family. + * + * GPIO driver provide a generic and very flexible software interface for all standard digital I/O port pins. + * Each port slice has individual interfaces for the operation as General Purpose I/O and it further provides the + * connectivity to the on-chip periphery and the control for the pad characteristics. + * + * The driver is divided into Input and Output mode. + * + * Input mode features: + * -# Configuration structure XMC_GPIO_CONFIG_t and initialization function XMC_GPIO_Init() + * -# Allows the selection of weak pull-up or pull-down device. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() + * \if XMC1 + * -# Allows the selection of input hysteresis. XMC_GPIO_SetInputHysteresis() + * \endif + * + * + * Output mode features: + * -# Allows the selection of push pull/open drain and Alternate output. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() + * \if XMC4 + * -# Allows the selection of pad driver strength. Configuration structure XMC_GPIO_OUTPUT_STRENGTH_t and function XMC_GPIO_SetOutputStrength() + * \endif + * + * -# Allows the selection of initial output level. Configuration structure XMC_GPIO_OUTPUT_LEVEL_t and function XMC_GPIO_SetOutputLevel() + * + *@{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +#define PORT_IOCR_PC_Pos PORT0_IOCR0_PC0_Pos +#define PORT_IOCR_PC_Msk PORT0_IOCR0_PC0_Msk + +#define PORT_IOCR_PC_Size (8U) + + +#define XMC_GPIO_CHECK_OUTPUT_LEVEL(level) ((level == XMC_GPIO_OUTPUT_LEVEL_LOW) || \ + (level == XMC_GPIO_OUTPUT_LEVEL_HIGH)) + +#define XMC_GPIO_CHECK_HWCTRL(hwctrl) ((hwctrl == XMC_GPIO_HWCTRL_DISABLED) || \ + (hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL1) || \ + (hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL2)) + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + + +/** + * Defines output level of a pin. Use type \a XMC_GPIO_OUTPUT_LEVEL_t for this enum. + */ +typedef enum XMC_GPIO_OUTPUT_LEVEL +{ + XMC_GPIO_OUTPUT_LEVEL_LOW = 0x10000U, /**< Reset bit */ + XMC_GPIO_OUTPUT_LEVEL_HIGH = 0x1U, /**< Set bit */ +} XMC_GPIO_OUTPUT_LEVEL_t; + +/** + * Defines direct hardware control characteristics of the pin . Use type \a XMC_GPIO_HWCTRL_t for this enum. + */ +typedef enum XMC_GPIO_HWCTRL +{ + XMC_GPIO_HWCTRL_DISABLED = 0x0U, /**< Software control only */ + XMC_GPIO_HWCTRL_PERIPHERAL1 = 0x1U, /**< HWI0/HWO0 control path can override the software configuration */ + XMC_GPIO_HWCTRL_PERIPHERAL2 = 0x2U /**< HWI1/HWO1 control path can override the software configuration */ +} XMC_GPIO_HWCTRL_t; + +/********************************************************************************************************************** + * DEVICE FAMILY EXTENSIONS + *********************************************************************************************************************/ + + #if UC_FAMILY == XMC1 +#include "xmc1_gpio.h" +#elif UC_FAMILY == XMC4 +#include "xmc4_gpio.h" +#else +#error "xmc_gpio.h: family device not supported" +#endif + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @param port Constant pointer pointing to GPIO port, to access port registers like Pn_OUT,Pn_OMR,Pn_IOCR etc. + * @param pin Port pin number. + * @param config GPIO configuration data structure. Refer data structure @ref XMC_GPIO_CONFIG_t for details. + * + * @return None + * + * \parDescription:
+ * \if XMC1 + * Initializes input / output mode settings like, pull up / pull down devices,hysteresis, push pull /open drain. + * Also configures alternate function outputs and clears hardware port control for a selected \a port \a and \a pin. + * \a config provides selected I/O settings. It configures hardware registers Pn_IOCR,Pn_OUT, Pn_OMR,Pn_PDISC and Pn_PHCR. + * \endif + * \if XMC4 + * Initializes input / output mode settings like, pull up / pull down devices,push pull /open drain, and pad driver mode. + * Also configures alternate function outputs and clears hardware port control for selected \a port and \a pin . + * It configures hardware registers Pn_IOCR,Pn_OUT,Pn_OMR,Pn_PDISC and Pn_PDR.\n + * \endif + * + * \parRelated APIs:
+ * None + * + * \parNote:
+ * This API is called in definition of DAVE_init by code generation and therefore should not be explicitly called + * for the normal operation. Use other APIs only after DAVE_init is called successfully (returns DAVE_STATUS_SUCCESS). + * + * + */ + + +void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config); + +/** + * + * @param port Constant pointer pointing to GPIO port, to access hardware register Pn_IOCR. + * @param pin Port pin number. + * @param mode input / output functionality selection. Refer @ref XMC_GPIO_MODE_t for valid values. + * + * @return None + * + * \parDescription:
+ * Sets digital input and output driver functionality and characteristics of a GPIO port pin. It configures hardware + * registers Pn_IOCR. \a mode is initially configured during initialization in XMC_GPIO_Init(). Call this API to alter + * the port direction functionality as needed later in the program. + * + * \parRelated APIs:
+ * None + * + */ + +void XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode); + + +/** + * + * @param port Constant pointer pointing to GPIO port, to access hardware register Pn_OMR. + * @param pin Port pin number. + * @param level output level selection. Refer @ref XMC_GPIO_OUTPUT_LEVEL_t for valid values. + * + * @return None + * + * \parDescription:
+ * Set port pin output level to high or low.It configures hardware registers Pn_OMR.\a level is initially + * configured during initialization in XMC_GPIO_Init(). Call this API to alter output level as needed later in the program. + * + * \parRelated APIs:
+ * XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow(). + * + * \parNote:
+ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). + * + */ + + +__STATIC_INLINE void XMC_GPIO_SetOutputLevel(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_OUTPUT_LEVEL_t level) +{ + XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); + XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid output level", XMC_GPIO_CHECK_OUTPUT_LEVEL(level)); + + port->OMR = (uint32_t)level << pin; +} + + +/** + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. + * @param pin Port pin number. + * + * @return None + * + * \parDescription:
+ * Sets port pin output to high. It configures hardware registers Pn_OMR. + * + * \parRelated APIs:
+ * XMC_GPIO_SetOutputLow() + * + * \parNote:
+ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().\n + * Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0. + * + */ + +__STATIC_INLINE void XMC_GPIO_SetOutputHigh(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_SetOutputHigh: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); + + port->OMR = (uint32_t)0x1U << pin; +} + +/** + * + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. + * @param pin port pin number. + * + * @return None + * + *\parDescription:
+ * Sets port pin output to low. It configures hardware registers Pn_OMR.\n + * + * \parRelated APIs:
> + * XMC_GPIO_SetOutputHigh() + * + *\parNote:
+ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). + * Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0.\n + * + */ + +__STATIC_INLINE void XMC_GPIO_SetOutputLow(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_SetOutputLow: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); + + port->OMR = 0x10000U << pin; +} + +/** + * + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. + * @param pin port pin number. + * + * @return None + * + * \parDescription:
+ * Configures port pin output to Toggle. It configures hardware registers Pn_OMR. + * + * \parRelated APIs:
+ * XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow(). + * + * \parNote:
+ * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). Register Pn_OMR is virtual + * and does not contain any flip-flop. A read action delivers the value of 0. + * + */ + +__STATIC_INLINE void XMC_GPIO_ToggleOutput(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_ToggleOutput: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); + + port->OMR = 0x10001U << pin; +} + +/** + * + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_IN. + * @param pin Port pin number. + * + * @return uint32_t pin logic level status. + * + *\parDescription:
+ * Reads the Pn_IN register and returns the current logical value at the GPIO pin. + * + * \parRelated APIs:
+ * None + * + * \parNote:
+ * Prior to this api, user has to configure port pin to input mode using XMC_GPIO_SetMode(). + * + */ + +__STATIC_INLINE uint32_t XMC_GPIO_GetInput(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_GetInput: Invalid port", XMC_GPIO_CHECK_PORT(port)); + + return (((port->IN) >> pin) & 0x1U); +} + +/** + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS. + * @param pin port pin number. + * + * @return None + * + * \parDescription:
+ * Enables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller enters + * Deep Sleep mode.Port pin enabled with power save mode option are set to a defined state and the input Schmitt-Trigger + * as well as the output driver stage are switched off. By default port pin does not react to power save mode request. + * + * \parRelated APIs:
+ * XMC_GPIO_DisablePowerSaveMode() + * + * Note:
+ * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so + * may result in an undefined behavior of the pin when the device enters the Deep Sleep state. + * + */ + + +__STATIC_INLINE void XMC_GPIO_EnablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_EnablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port)); + + port->PPS |= (uint32_t)0x1U << pin; +} + + +/** + * + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS. + * @param pin port pin number. + * + * @return None + * + * \parDescription:
+ * Disables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller enters + * Deep Sleep mode. This configuration enables input Schmitt-Trigger and output driver stage(if pin is enabled power + * save mode previously). By default port \a pin does not react to power save mode request. + * + * \parRelated APIs:
+ * XMC_GPIO_EnablePowerSaveMode() + * + *\parNote:
+ * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so + * may result in an undefined behavior of the pin when the device enters the Deep Sleep state. + * + */ + +__STATIC_INLINE void XMC_GPIO_DisablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_DisablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port)); + + port->PPS &= ~(uint32_t)((uint32_t)0x1U << pin); +} + + +/** + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_HWSEL. + * @param pin port pin number. + * @param hwctrl direct hardware control selection. Refer @ref XMC_GPIO_HWCTRL_t for valid values. + * + * @return None + * + * \parDescription:
+ * Selects direct hard ware control and configures Pn_HWSEL register.This configuration is useful for the port pins + * overlaid with peripheral functions for which the connected peripheral needs hardware control. + * + * \parRelated APIs:
+ * None + * + *\parNote:
+ * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). + * Doing so may result in an undefined behavior of the pin when the device enters the Deep Sleep state. + * + */ + +void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl); + + +/** + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC. + * @param pin port pin number. + * + * @return None + * + * \parRelated APIs:
+ * None + * + * \parDescription:
+ * Enable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only for + * analog port pins. + * + */ +__STATIC_INLINE void XMC_GPIO_EnableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port)); + + port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin); +} + + +/** + * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC. + * @param pin port pin number. + * + * @return None + * + * \parRelated APIs:
+ * None + * + * \parDescription:
+ * Disable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only + * for analog port pins. + * + */ + +__STATIC_INLINE void XMC_GPIO_DisableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin) +{ + XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port)); + + port->PDISC |= (uint32_t)0x1U << pin; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} (end addtogroup GPIO) + */ + +/** + * @} (end addtogroup XMClib) + */ + +#endif /* XMC_GPIO_H */ + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_hrpwm.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_hrpwm.h new file mode 100644 index 00000000..655ef047 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_hrpwm.h @@ -0,0 +1,2317 @@ + +/** + * @file xmc_hrpwm.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Driver description updated
+ * - API's are renamed
+ * XMC_HRPWM_HRC_SetResolutionCR1() -> XMC_HRPWM_HRC_SetCompare1()
+ * XMC_HRPWM_HRC_SetResolutionCR2() -> XMC_HRPWM_HRC_SetCompare2()
+ * XMC_HRPWM_HRC_SetDeadTimeDCF() -> XMC_HRPWM_HRC_SetDeadTimeFalling()
+ * XMC_HRPWM_HRC_SetDeadTimeDCR() -> XMC_HRPWM_HRC_SetDeadTimeRising()
+ * + * 2015-05-12: + * - XMC_HRPWM_CSG_SelClampingInput() api is added to select the clamping input
+ * - Enum XMC_HRPWM_SHADOW_TX_t is renamed to XMC_HRPWM_SHADOW_TX_DAC_t to represent that shadow transfer is for DAC
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * - Updated copyright and change history section. + * + * @endcond + * + */ + +#ifndef HRPWM_H +#define HRPWM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** + * HEADER FILES + **********************************************************************************************************************/ +#include + +#if defined(HRPWM0) +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup HRPWM + * @brief High Resolution PWM Unit (HRPWM) driver for the XMC microcontroller family.
+ * + * The HRPWM extends the capabilities of the associated Capture/Compare Unit(CCU8), that simplifies the design various of SMPS. + * It allows easy and fast implementation of control loop, reduced total number of external components, avoid susceptibility + * to environmental and process variations there by reducing the size of the power supply.
+ * + *Comparator Slope Generator(CSG)
+ * HRPWM module consists 3 Comparator Slope Generator(CSG) units. Each CSG unit comprised of one High Speed Comparator, + * a dedicated 10 bit 30 MS/s DAC and one hardware controlled Slope Compensation module.
+ * + * CSG features include:
+ *
    + *
  1. 3 High Speed Comparators, that can be use to compare an external signal against the DAC value
    + *
  2. 3 (30MS/s) 10 bit DAC
    + *
  3. 3 Slope generation blocks, that are used to generate the DAC input value
    + *
  4. different slope generations schemes, for a flexible and automated DAC voltage generation
    + *
  5. 2 DAC reference values, to allow flexible hysteretic mode control
    + *
  6. Input multiplexer for the inverting comparator input, allowing several analog inputs to be connected to each comparator and also dynamic input switching.
    + *
  7. blanking compare mode, to avoid premature switch OFF due to noise
    + *
  8. a dedicated output per Comparator
    + *
  9. programmable clock prescaler
    + *
  10. programmable clock pulse swallower for slope linearization with uneven clock scale
    + *
  11. different slope generation schemes:
    + * – incrementing mode
    + * – decrementing mode
    + * – triangular mode
    + *
  12. shadow transfer for one DAC reference value
    + *
  13. external trigger for the DAC
    + *
  14. external control for the DAC reference values
    + *
  15. four dedicated service request lines
    + *
+ * + *High Resolution Channel unit(HRC)
+ * It also has 4 High Resolution Channel unit(HRC) that upgrades 4 compare channels of a Capture/Compare unit (CCU8), enabling + * generation of PWM with 150ps resolution. ie; the rise time and/or fall time of PWM can be changed in steps of 150ps.
+ * + * HRC features include:
+ *
    + *
  1. Upgrade up to 4 PWM signals of CCU8 outputs for high resolution positioning.
    + *
  2. Independent control of PWM set and reset.
    + *
  3. Delay the PWM rise time in steps of 150ps. This does not insert dead time.
    + *
  4. Extent the fall time of PWM in steps of 150ps. This does not insert dead time.
    + *
  5. Dead time insertion on complementary signals
    + *
  6. Passive level selection on outputs.
    + *
+ * @{ + */ +/*********************************************************************************************************************** + * MACROS + ********************************************************************************************************************/ +#define XMC_HRPWM_CSG0_MEMORY_ADDRESS 0x40020A40 /* CSG0 memory location */ +#define XMC_HRPWM_CSG1_MEMORY_ADDRESS 0x40020B40 /* CSG1 memory location */ +#define XMC_HRPWM_CSG2_MEMORY_ADDRESS 0x40020C40 /* CSG2 memory location */ + +#define XMC_HRPWM_COMPARATOR_STATUS (HRPWM0_CSGTRSG_D0STE_Msk + HRPWM0_CSGTRSG_D1STE_Msk + HRPWM0_CSGTRSG_D2STE_Msk) + +#define XMC_HRPWM_CHECK_MODULE_PTR(PTR) ((PTR)== HRPWM0) +#define XMC_HRPWM_CHECK_HRC_PTR(PTR) ( ((PTR)== HRPWM0_HRC0) || ((PTR)== HRPWM0_HRC1) || ((PTR)== HRPWM0_HRC2) || ((PTR)== HRPWM0_HRC3) ) +#define XMC_HRPWM_CHECK_CSG_PTR(PTR) ( ((PTR)== HRPWM0_CSG0) || ((PTR)== HRPWM0_CSG1) || ((PTR)== HRPWM0_CSG2) ) + +/*********************************************************************************************************************** + * ENUMS - General + **********************************************************************************************************************/ +/** + * Return HRPWM driver status + */ +typedef enum XMC_HRPWM_STATUS +{ + XMC_HRPWM_STATUS_OK = 0U, /**< Driver successfully completed the request */ + XMC_HRPWM_STATUS_BUSY, /**< Driver busy, cannot handle request */ + XMC_HRPWM_STATUS_ERROR /**< Driver cannot fulfill request, error occurred */ +} XMC_HRPWM_STATUS_t; + +/*********************************************************************************************************************** + * ENUMS - HRPWM + **********************************************************************************************************************/ +/** + * HRPWM module clock frequency + */ +typedef enum XMC_HRPWM_CLK_FREQ +{ + XMC_HRPWM_CLK_FREQ_NONE = 0U, /**< No clock frequency is selected */ + XMC_HRPWM_CLK_FREQ_180MHZ, /**< Module clock frequency is 180MHz */ + XMC_HRPWM_CLK_FREQ_120MHZ, /**< Module clock frequency is 120MHz */ + XMC_HRPWM_CLK_FREQ_80MHZ /**< Module clock frequency is 80MHz */ +} XMC_HRPWM_CLK_FREQ_t; + +/*********************************************************************************************************************** + * ENUMS - HRPWM HRC + **********************************************************************************************************************/ +/** + * HRPWM HRC High Resolution mode configuration + */ +typedef enum XMC_HRPWM_HRC_HR_EDGE +{ + XMC_HRPWM_HRC_HR_EDGE_SEL_RISING = 0U, /**< Rising edge high resolution signal positioning enabled */ + XMC_HRPWM_HRC_HR_EDGE_SEL_FALLING, /**< Falling edge high resolution signal positioning enabled */ + XMC_HRPWM_HRC_HR_EDGE_SEL_BOTH, /**< Both edges high resolution signal positioning enabled */ + XMC_HRPWM_HRC_HR_EDGE_SEL_NONE /**< No high resolution signal positioning */ +} XMC_HRPWM_HRC_HR_EDGE_t; + +/** + * HRPWM HRC source selector input + */ +typedef enum XMC_HRPWM_HRC_SRC_INPUT +{ + XMC_HRPWM_HRC_SRC_INPUT_CCU = 0U, /**< Source selector is controlled via CCU timer signal */ + XMC_HRPWM_HRC_SRC_INPUT_CSG /**< Source selector is controlled via CSG output signal */ +} XMC_HRPWM_HRC_SRC_INPUT_t; + +/** + * HRPWM HRC source selector - connection of source selector to which CSG unit + */ +typedef enum XMC_HRPWM_HRC_CMP_SEL +{ + XMC_HRPWM_HRC_CMP_SEL_CSG0 = 0U, /**< Comparator output of CSG0 selected */ + XMC_HRPWM_HRC_CMP_SEL_CSG1, /**< Comparator output of CSG1 selected */ + XMC_HRPWM_HRC_CMP_SEL_CSG2 /**< Comparator output of CSG2 selected */ +} XMC_HRPWM_HRC_CMP_SEL_t; + +/** + * HRPWM HRC source selector - connection of source selector to which CCU timer + */ +typedef enum XMC_HRPWM_HRC_TIMER_SEL +{ + XMC_HRPWM_HRC_TIMER_SEL_CCU_CC0 = 0U, /**< CCU timer 0 selected */ + XMC_HRPWM_HRC_TIMER_SEL_CCU_CC1, /**< CCU timer 1 selected */ + XMC_HRPWM_HRC_TIMER_SEL_CCU_CC2, /**< CCU timer 2 selected */ + XMC_HRPWM_HRC_TIMER_SEL_CCU_CC3 /**< CCU timer 3 selected */ +} XMC_HRPWM_HRC_TIMER_SEL_t; + +/** + * HR source selector edge configuration (GSEL) + */ +typedef enum XMC_HRPWM_HRC_SRC_EDGE_SEL +{ + XMC_HRPWM_HRC_SRC_EDGE_SEL_DISABLED = 0U, /**< source signal generation disabled */ + XMC_HRPWM_HRC_SRC_EDGE_SEL_RISING, /**< source signal generation on rising edge */ + XMC_HRPWM_HRC_SRC_EDGE_SEL_FALLING, /**< source signal generation on falling edge */ + XMC_HRPWM_HRC_SRC_EDGE_SEL_BOTH /**< source signal generation on both edges */ +} XMC_HRPWM_HRC_SRC_EDGE_SEL_t; + +/** + * HRPWM function Enable / Disable status + */ +typedef enum XMC_HRPWM_FUNC_STATUS +{ + XMC_HRPWM_FUNC_STATUS_DISABLE = 0U, /**< Function is disabled */ + XMC_HRPWM_FUNC_STATUS_ENABLE = 1U /**< Function is enabled */ +} XMC_HRPWM_FUNC_STATUS_t; + +/** + * HRPWM high resolution module status + */ +typedef enum XMC_HRPWM_HR_LOGIC +{ + XMC_HRPWM_HR_LOGIC_NOT_WORKING = 0U, /**< High resolution signal path is switched off for all HRC channels */ + XMC_HRPWM_HR_LOGIC_WORKING /**< High resolution signal path is switched on for all HRC channels */ +} XMC_HRPWM_HR_LOGIC_t; + +/** + * High resolution paths for HRC channels + */ +typedef enum XMC_HRPWM_HR_PATH +{ + XMC_HRPWM_HR_PATH_HRC0 = HRPWM0_HRCCFG_HRC0E_Msk, /**< HRC0 path selected for High resolution */ + XMC_HRPWM_HR_PATH_HRC1 = HRPWM0_HRCCFG_HRC1E_Msk, /**< HRC1 path selected for High resolution */ + XMC_HRPWM_HR_PATH_HRC2 = HRPWM0_HRCCFG_HRC2E_Msk, /**< HRC2 path selected for High resolution */ + XMC_HRPWM_HR_PATH_HRC3 = HRPWM0_HRCCFG_HRC3E_Msk, /**< HRC3 path selected for High resolution */ +} XMC_HRPWM_HR_PATH_t; + +/** + * @brief Low resolution paths for HRC channels + */ +typedef enum XMC_HRPWM_LR_PATH +{ + XMC_HRPWM_LR_PATH_HRC0 = HRPWM0_HRCCFG_LRC0E_Msk, /**< LRC0 path selected for Low resolution */ + XMC_HRPWM_LR_PATH_HRC1 = HRPWM0_HRCCFG_LRC1E_Msk, /**< LRC0 path selected for Low resolution */ + XMC_HRPWM_LR_PATH_HRC2 = HRPWM0_HRCCFG_LRC2E_Msk, /**< LRC0 path selected for Low resolution */ + XMC_HRPWM_LR_PATH_HRC3 = HRPWM0_HRCCFG_LRC3E_Msk /**< LRC0 path selected for Low resolution */ +} XMC_HRPWM_LR_PATH_t; + +/** + * Shadow transfer for HRC values + * The enum is used to access the bitfields of registers HRCSTRG, HRCCTRG, HRCSTSG + */ +typedef enum XMC_HRPWM_HRC_SHADOW_TX +{ + XMC_HRPWM_HRC_SHADOW_TX_HRC0_VALUE = 0x1U, /**< HRC0 shadow transfer mask for CR1 & CR2 */ + XMC_HRPWM_HRC_SHADOW_TX_HRC0_DT_VALUE = 0x2U, /**< HRC0 shadow transfer mask for DCR & DCRF */ + XMC_HRPWM_HRC_SHADOW_TX_HRC1_VALUE = 0x10U, /**< HRC1 shadow transfer mask for CR1 & CR2 */ + XMC_HRPWM_HRC_SHADOW_TX_HRC1_DT_VALUE = 0x20U, /**< HRC1 shadow transfer mask for DCR & DCRF */ + XMC_HRPWM_HRC_SHADOW_TX_HRC2_VALUE = 0x100U, /**< HRC2 shadow transfer mask for CR1 & CR2 */ + XMC_HRPWM_HRC_SHADOW_TX_HRC2_DT_VALUE = 0x200U, /**< HRC2 shadow transfer mask for DCR & DCRF */ + XMC_HRPWM_HRC_SHADOW_TX_HRC3_VALUE = 0x1000U, /**< HRC3 shadow transfer mask for CR1 & CR2 */ + XMC_HRPWM_HRC_SHADOW_TX_HRC3_DT_VALUE = 0x2000U /**< HRC3 shadow transfer mask for DCR & DCRF */ +} XMC_HRPWM_HRC_SHADOW_TX_t; + +/** + * HR source selector + */ +typedef enum XMC_HRPWM_HRC_SOURCE +{ + XMC_HRPWM_HRC_SOURCE_0 = 0U, /**< High resolution source 0 */ + XMC_HRPWM_HRC_SOURCE_1 /**< High resolution source 1 */ +} XMC_HRPWM_HRC_SOURCE_t; + +/** + * HRC dead time shadow transfer trigger selection + */ +typedef enum XMC_HRPWM_HRC_DT_TR_SEL +{ + XMC_HRPWM_HRC_DT_TR_SEL_TIMER = 0U, /**< Source for shadow transfer trigger is CCU8 timer. */ + XMC_HRPWM_HRC_DT_TR_SEL_OVERFLOW /**< Source for shadow transfer trigger is dead time timer overflow. */ +} XMC_HRPWM_HRC_DT_TR_SEL_t; + +/** + * HRPWM HRC output - Passive level + */ +typedef enum XMC_HRPWM_HRC_OUT_PASSIVE_LVL +{ + XMC_HRPWM_HRC_OUT_PASSIVE_LVL_LOW = 0U, /**< Passive low output */ + XMC_HRPWM_HRC_OUT_PASSIVE_LVL_HIGH /**< Passive high output */ +} XMC_HRPWM_HRC_OUT_PASSIVE_LVL_t; + +/*********************************************************************************************************************** + * ENUMS - HRPWM CSG + **********************************************************************************************************************/ +/** + * CSG power modes + */ + typedef enum XMC_HRPWM_CSG_POWER_MODE +{ + XMC_HRPWM_CSG_POWER_MODE_OFF = 0U << HRPWM0_CSGCFG_C0PM_Pos, /**< Comparator slope generator turned off */ + XMC_HRPWM_CSG_POWER_MODE_LOW_SPEED = 1U << HRPWM0_CSGCFG_C0PM_Pos, /**< Comparator slope generator in low speed mode */ + XMC_HRPWM_CSG_POWER_MODE_HI_SPEED = 3U << HRPWM0_CSGCFG_C0PM_Pos /**< Comparator slope generator in high speed mode */ +} XMC_HRPWM_CSG_POWER_MODE_t; + +/** + * DAC, Comparator start controls & Comparator clamped state control + * The enum is used to access the bitfields of registers CSGSETG, CSGCLRG, CSGSTATG + */ +typedef enum XMC_HRPWM_CSG_RUN_BIT +{ + XMC_HRPWM_CSG_RUN_BIT_DAC0 = 0x1U, /**< Start DAC0 */ + XMC_HRPWM_CSG_RUN_BIT_CMP0 = 0x2U, /**< Start comparator 0 */ + XMC_HRPWM_CSG_RUN_BIT_CMP0_PSL = 0x4U, /**< Set comparator 0 output to clamped state */ + XMC_HRPWM_CSG_RUN_BIT_DAC1 = 0x10U, /**< Start DAC1 */ + XMC_HRPWM_CSG_RUN_BIT_CMP1 = 0x20U, /**< Start comparator 1 */ + XMC_HRPWM_CSG_RUN_BIT_CMP1_PSL = 0x40U, /**< Set comparator 1 output to clamped state */ + XMC_HRPWM_CSG_RUN_BIT_DAC2 = 0x100U, /**< Start DAC2 */ + XMC_HRPWM_CSG_RUN_BIT_CMP2 = 0x200U, /**< Start comparator2 */ + XMC_HRPWM_CSG_RUN_BIT_CMP2_PSL = 0x400U /**< Set comparator 2 output to clamped state */ +} XMC_HRPWM_CSG_RUN_BIT_t; + +/** + * Slope start for DAC units + */ +typedef enum XMC_HRPWM_CSG_SLOPE_START +{ + XMC_HRPWM_CSG_SLOPE_START_DAC0 = HRPWM0_CSGFCG_S0STR_Msk, /**< Start slope generation for DAC0 */ + XMC_HRPWM_CSG_SLOPE_START_DAC1 = HRPWM0_CSGFCG_S1STR_Msk, /**< Start slope generation for DAC1 */ + XMC_HRPWM_CSG_SLOPE_START_DAC2 = HRPWM0_CSGFCG_S2STR_Msk /**< Start slope generation for DAC2 */ +} XMC_HRPWM_CSG_SLOPE_START_t; + +/** + * Slope stop for DAC units + */ +typedef enum XMC_HRPWM_CSG_SLOPE_STOP +{ + XMC_HRPWM_CSG_SLOPE_STOP_DAC0 = HRPWM0_CSGFCG_S0STP_Msk, /**< Stop slope generation for DAC0 */ + XMC_HRPWM_CSG_SLOPE_STOP_DAC1 = HRPWM0_CSGFCG_S1STP_Msk, /**< Stop slope generation for DAC1 */ + XMC_HRPWM_CSG_SLOPE_STOP_DAC2 = HRPWM0_CSGFCG_S2STP_Msk /**< Stop slope generation for DAC2 */ +} XMC_HRPWM_CSG_SLOPE_STOP_t; + +/** + * Prescaler start in CSG + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_START +{ + XMC_HRPWM_CSG_PRESCALER_START_CSG0 = HRPWM0_CSGFCG_PS0STR_Msk, /**< Start prescaler of CSG0 */ + XMC_HRPWM_CSG_PRESCALER_START_CSG1 = HRPWM0_CSGFCG_PS1STR_Msk, /**< Start prescaler of CSG1 */ + XMC_HRPWM_CSG_PRESCALER_START_CSG2 = HRPWM0_CSGFCG_PS2STR_Msk /**< Start prescaler of CSG2 */ +} XMC_HRPWM_CSG_PRESCALER_START_t; + +/** + * Prescaler stop in CSG + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_STOP +{ + XMC_HRPWM_CSG_PRESCALER_STOP_CSG0 = HRPWM0_CSGFCG_PS0STP_Msk, /**< Stop prescaler of CSG0 */ + XMC_HRPWM_CSG_PRESCALER_STOP_CSG1 = HRPWM0_CSGFCG_PS1STP_Msk, /**< Stop prescaler of CSG1 */ + XMC_HRPWM_CSG_PRESCALER_STOP_CSG2 = HRPWM0_CSGFCG_PS2STP_Msk /**< Stop prescaler of CSG2 */ +} XMC_HRPWM_CSG_PRESCALER_STOP_t; + +/** + * Clear prescaler in CSG + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_CLR +{ + XMC_HRPWM_CSG_PRESCALER_CLR_CSG0 = HRPWM0_CSGFCG_PS0CLR_Msk, /**< Clear prescaler of CSG0 */ + XMC_HRPWM_CSG_PRESCALER_CLR_CSG1 = HRPWM0_CSGFCG_PS1CLR_Msk, /**< Clear prescaler of CSG1 */ + XMC_HRPWM_CSG_PRESCALER_CLR_CSG2 = HRPWM0_CSGFCG_PS2CLR_Msk /**< Clear prescaler of CSG2 */ +} XMC_HRPWM_CSG_PRESCALER_CLR_t; + +/** + * DAC slope generation status + */ +typedef enum XMC_HRPWM_DAC_SLOPE_GEN_STATUS +{ + XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC0 = HRPWM0_CSGFSG_S0RB_Msk, /**< Slope generation status mask for DAC0 */ + XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC1 = HRPWM0_CSGFSG_S1RB_Msk, /**< Slope generation status mask for DAC1 */ + XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC2 = HRPWM0_CSGFSG_S2RB_Msk /**< Slope generation status mask for DAC2 */ +} XMC_HRPWM_DAC_SLOPE_GEN_STATUS_t; + +/** + * CSG prescaler status + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_STATUS +{ + XMC_HRPWM_CSG_PRESCALER_STATUS_CSG0 = HRPWM0_CSGFSG_P0RB_Msk, /**< Prescaler status in CSG0 */ + XMC_HRPWM_CSG_PRESCALER_STATUS_CSG1 = HRPWM0_CSGFSG_P1RB_Msk, /**< Prescaler status in CSG1 */ + XMC_HRPWM_CSG_PRESCALER_STATUS_CSG2 = HRPWM0_CSGFSG_P2RB_Msk /**< Prescaler status in CSG2 */ +} XMC_HRPWM_CSG_PRESCALER_STATUS_t; + +/** + * Comparator inputs + */ +typedef enum XMC_HRPWM_CSG_CMP_INPUT +{ + XMC_HRPWM_CSG_CMP_INPUT_CINA = 0U, /**< Input for comparator is CINA */ + XMC_HRPWM_CSG_CMP_INPUT_CINB /**< Input for comparator is CINB */ +} XMC_HRPWM_CSG_CMP_INPUT_t; + +/** + * CSG comparator input switch request + */ +typedef enum XMC_HRPWM_CSG_SWITCH_CMP_INPUT +{ + XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP0 = HRPWM0_CSGTRSG_SW0ST_Msk, /**< Request to switch the analog input connected to the comparator 0 between CINA and CINB */ + XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP1 = HRPWM0_CSGTRSG_SW1ST_Msk, /**< Request to switch the analog input connected to the comparator 1 between CINA and CINB */ + XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP2 = HRPWM0_CSGTRSG_SW2ST_Msk /**< Request to switch the analog input connected to the comparator 2 between CINA and CINB */ +} XMC_HRPWM_CSG_SWITCH_CMP_INPUT_t; + +/** + * CSG comparator input switch request + */ +typedef enum XMC_HRPWM_CSG_CMP_INVERTING_INPUT +{ + XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP0 = HRPWM0_CSGTRSG_D0STE_Msk, /**< Comparator 0 inverting input connection */ + XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP1 = HRPWM0_CSGTRSG_D1STE_Msk, /**< Comparator 1 inverting input connection */ + XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP2 = HRPWM0_CSGTRSG_D2STE_Msk /**< Comparator 2 inverting input connection */ +} XMC_HRPWM_CSG_CMP_INVERTING_INPUT_t; + +/** + * Input list to CSG + */ +typedef enum XMC_HRPWM_CSG_INPUT_SEL +{ + XMC_HRPWM_CSG_INPUT_SEL_IA = 0U, /**< Input selected for blanking or comparator switch: Input-A */ + XMC_HRPWM_CSG_INPUT_SEL_IB, /**< Input selected for blanking or comparator switch: Input-B */ + XMC_HRPWM_CSG_INPUT_SEL_IC, /**< Input selected for blanking or comparator switch: Input-C */ + XMC_HRPWM_CSG_INPUT_SEL_ID, /**< Input selected for blanking or comparator switch: Input-D */ + XMC_HRPWM_CSG_INPUT_SEL_IE, /**< Input selected for blanking or comparator switch: Input-E */ + XMC_HRPWM_CSG_INPUT_SEL_IF, /**< Input selected for blanking or comparator switch: Input-F */ + XMC_HRPWM_CSG_INPUT_SEL_IG, /**< Input selected for blanking or comparator switch: Input-G */ + XMC_HRPWM_CSG_INPUT_SEL_IH, /**< Input selected for blanking or comparator switch: Input-H */ + XMC_HRPWM_CSG_INPUT_SEL_II, /**< Input selected for blanking or comparator switch: Input-I */ + XMC_HRPWM_CSG_INPUT_SEL_IJ, /**< Input selected for blanking or comparator switch: Input-J */ + XMC_HRPWM_CSG_INPUT_SEL_IK, /**< Input selected for blanking or comparator switch: Input-K */ + XMC_HRPWM_CSG_INPUT_SEL_IL, /**< Input selected for blanking or comparator switch: Input-L */ + XMC_HRPWM_CSG_INPUT_SEL_IM, /**< Input selected for blanking or comparator switch: Input-M */ + XMC_HRPWM_CSG_INPUT_SEL_IN, /**< Input selected for blanking or comparator switch: Input-N */ + XMC_HRPWM_CSG_INPUT_SEL_IO, /**< Input selected for blanking or comparator switch: Input-O */ + XMC_HRPWM_CSG_INPUT_SEL_IP /**< Input selected for blanking or comparator switch: Input-P */ +} XMC_HRPWM_CSG_INPUT_SEL_t; + +/** + * HRPWM CSG - Selection of edge sensitivity + */ +typedef enum XMC_HRPWM_CSG_EDGE_SEL +{ + XMC_HRPWM_CSG_EDGE_SEL_DISABLED = 0U, /**< Trigger event not generated */ + XMC_HRPWM_CSG_EDGE_SEL_RISING_EDGE, /**< Trigger event not generated in rising edge */ + XMC_HRPWM_CSG_EDGE_SEL_FALLING_EDGE, /**< Trigger event not generated in falling edge */ + XMC_HRPWM_CSG_EDGE_SEL_BOTH_EDGE /**< Trigger event not generated in both edges */ +} XMC_HRPWM_CSG_EDGE_SEL_t; + +/** + * HRPWM CSG - Selection of level sensitivity + */ +typedef enum XMC_HRPWM_CSG_LVL_SEL +{ + XMC_HRPWM_CSG_LVL_SEL_DISABLED = 0U, /**< Level sensitivity is disabled */ + XMC_HRPWM_CSG_LVL_SEL_HIGH, /**< Level sensitivity is High */ + XMC_HRPWM_CSG_LVL_SEL_LOW /**< Level sensitivity is Low */ +} XMC_HRPWM_CSG_LVL_SEL_t; + +/** + * HRPWM CSG - Slope Generation clock selection + */ +typedef enum XMC_HRPWM_CSG_CLK_INPUT +{ + XMC_HRPWM_CSG_CLK_INPUT_MCLK = 0U, /**< Clock for CSG is module clock */ + XMC_HRPWM_CSG_CLK_INPUT_ECLKA, /**< Clock for CSG is external clock A */ + XMC_HRPWM_CSG_CLK_INPUT_ECLKB, /**< Clock for CSG is external clock B */ + XMC_HRPWM_CSG_CLK_INPUT_ECLKC /**< Clock for CSG is external clock C */ +} XMC_HRPWM_CSG_CLK_INPUT_t; + +/** + * HRPWM CSG - IRQ Event Id + * The enum is used to access the bitfields of registers CSGySRE, CSGySRS, CSGySWS, CSGySWC, CSGyISTAT + */ +typedef enum XMC_HRPWM_CSG_IRQ_ID +{ + XMC_HRPWM_CSG_IRQ_ID_VLS1 = 0x1U, /**< Interrupt on DAC value switch from CSGyDSV1 to CSGyDSV2 interrupt */ + XMC_HRPWM_CSG_IRQ_ID_VLS2 = 0x2U, /**< Interrupt on DAC value switch from CSGyDSV2 to CSGyDSV1 interrupt */ + XMC_HRPWM_CSG_IRQ_ID_TRGS = 0x4U, /**< Interrupt on DAC conversion trigger */ + XMC_HRPWM_CSG_IRQ_ID_STRS = 0x8U, /**< Interrupt on DAC start trigger */ + XMC_HRPWM_CSG_IRQ_ID_STPS = 0x10U, /**< Interrupt on DAC stop trigger */ + XMC_HRPWM_CSG_IRQ_ID_STD = 0x20U, /**< Interrupt on DAC shadow transfer */ + XMC_HRPWM_CSG_IRQ_ID_CRSE = 0x40U, /**< Interrupt on comparator output rise edge */ + XMC_HRPWM_CSG_IRQ_ID_CFSE = 0x80U, /**< Interrupt on comparator output fall edge */ + XMC_HRPWM_CSG_IRQ_ID_CSEE = 0x100U /**< Interrupt on comparator output clamped state */ +} XMC_HRPWM_CSG_IRQ_ID_t; + +/** + * HRPWM CSG - Initial DAC start mode + */ +typedef enum XMC_HRPWM_CSG_SWSM +{ + XMC_HRPWM_CSG_SWSM_DSV2_W_TRIGGER = 0U, /**< DSV2 is used as initial DAC value & conversion trigger is generated */ + XMC_HRPWM_CSG_SWSM_DSV1_W_TRIGGER, /**< DSV1 is used as initial DAC value & conversion trigger is generated */ + XMC_HRPWM_CSG_SWSM_DSV2_NO_TRIGGER, /**< DSV2 is used as initial DAC value & no conversion trigger generated */ + XMC_HRPWM_CSG_SWSM_DSV1_NO_TRIGGER /**< DSV1 is used as initial DAC value & no conversion trigger generated */ +} XMC_HRPWM_CSG_SWSM_t; + +/** + * HRPWM CSG - Configuration for Clock disable + */ +typedef enum XMC_HRPWM_CSG_CLK +{ + XMC_HRPWM_CSG_CLK_CSG0 = HRPWM0_CSGCFG_C0CD_Msk, /**< CSG0 clock mask */ + XMC_HRPWM_CSG_CLK_CSG1 = HRPWM0_CSGCFG_C1CD_Msk, /**< CSG1 clock mask */ + XMC_HRPWM_CSG_CLK_CSG2 = HRPWM0_CSGCFG_C2CD_Msk /**< CSG2 clock mask */ +} XMC_HRPWM_CSG_CLK_t; + +/** + * HRPWM CSG - DAC shadow transfer values + */ +typedef enum XMC_HRPWM_SHADOW_TX +{ + XMC_HRPWM_SHADOW_TX_DAC0 = HRPWM0_CSGTRC_D0SEC_Msk, /**< Shadow transfer mask for DAC0 - reference value 1 & Pulse swallow value */ + XMC_HRPWM_SHADOW_TX_DAC1 = HRPWM0_CSGTRC_D1SEC_Msk, /**< Shadow transfer mask for DAC1 - reference value 1 & Pulse swallow value */ + XMC_HRPWM_SHADOW_TX_DAC2 = HRPWM0_CSGTRC_D2SEC_Msk /**< Shadow transfer mask for DAC2 - reference value 1 & Pulse swallow value */ +} XMC_HRPWM_SHADOW_TX_DAC_t; + +/** + * HRPWM CSG - Service request line + */ +typedef enum XMC_HRPWM_CSG_IRQ_SR_LINE +{ + XMC_HRPWM_CSG_IRQ_SR_LINE_0 = 0U, /**< CSG - Service request SR-0 */ + XMC_HRPWM_CSG_IRQ_SR_LINE_1 = 1U, /**< CSG - Service request SR-1 */ + XMC_HRPWM_CSG_IRQ_SR_LINE_2 = 2U, /**< CSG - Service request SR-2 */ + XMC_HRPWM_CSG_IRQ_SR_LINE_3 = 3U /**< CSG - Service request SR-3 */ +} XMC_HRPWM_CSG_IRQ_SR_LINE_t; + +/** + * HRPWM CSG - Slope Generation control mode + */ +typedef enum XMC_HRPWM_CSG_SLOPE_CTRL_MODE +{ + XMC_HRPWM_CSG_SLOPE_CTRL_MODE_STATIC = 0U, /**< Slope generation mode - Static mode */ + XMC_HRPWM_CSG_SLOPE_CTRL_MODE_DEC_GEN, /**< Slope generation mode - Decrementing slope generation */ + XMC_HRPWM_CSG_SLOPE_CTRL_MODE_INC_GEN, /**< Slope generation mode - Incrementing slope generation */ + XMC_HRPWM_CSG_SLOPE_CTRL_MODE_TRIANGULAR /**< Slope generation mode - Triangular slope generation */ +} XMC_HRPWM_CSG_SLOPE_CTRL_MODE_t; + +/** + * HRPWM CSG - Prescaler external start configuration + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_EXT_START +{ + XMC_HRPWM_CSG_PRESCALER_EXT_START_IGNORE = 0U, /**< Prescaler operation on external start trigger is: Ignore */ + XMC_HRPWM_CSG_PRESCALER_EXT_START_STRT, /**< Prescaler operation on external start trigger is: Start prescaler */ + XMC_HRPWM_CSG_PRESCALER_EXT_START_CLR, /**< Prescaler operation on external start trigger is: Clear prescaler */ + XMC_HRPWM_CSG_PRESCALER_EXT_START_CLR_N_STRT /**< Prescaler operation on external start trigger is: Clear & Start prescaler */ +} XMC_HRPWM_CSG_PRESCALER_EXT_START_t; + +/** + * HRPWM CSG - Prescaler external stop configuration + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_EXT_STOP +{ + XMC_HRPWM_CSG_PRESCALER_EXT_STOP_IGNORE = 0U, /**< Prescaler operation on external stop trigger is: Ignore */ + XMC_HRPWM_CSG_PRESCALER_EXT_STOP_STP, /**< Prescaler operation on external stop trigger is: Stop prescaler */ + XMC_HRPWM_CSG_PRESCALER_EXT_STOP_CLR, /**< Prescaler operation on external stop trigger is: Clear prescaler */ + XMC_HRPWM_CSG_PRESCALER_EXT_STOP_CLR_N_STOP /**< Prescaler operation on external stop trigger is: Clear & Stop prescaler */ +} XMC_HRPWM_CSG_PRESCALER_EXT_STOP_t; + +/** + * HRPWM CSG - Slope Generation external start configuration + */ +typedef enum XMC_HRPWM_CSG_SLOPE_EXT_START +{ + XMC_HRPWM_CSG_SLOPE_EXT_START_IGNORE = 0U, /**< Slope generation on external start trigger is: Ignore */ + XMC_HRPWM_CSG_SLOPE_EXT_START_STRT, /**< Slope generation on external start trigger is: Start/restart slope generation */ + XMC_HRPWM_CSG_SLOPE_EXT_START_RESUME, /**< Slope generation on external start trigger is: Resumes slope generation */ +} XMC_HRPWM_CSG_SLOPE_EXT_START_t; + +/** + * HRPWM CGS - Slope Generation external stop configuration + */ +typedef enum XMC_HRPWM_CSG_SLOPE_EXT_STOP +{ + XMC_HRPWM_CSG_SLOPE_EXT_STOP_IGNORE = 0U, /**< Slope generation on external stop trigger is: Ignore */ + XMC_HRPWM_CSG_SLOPE_EXT_STOP_STP, /**< Slope generation on external stop trigger is: Stops/Halts the slope generation */ + XMC_HRPWM_CSG_SLOPE_EXT_STOP_FREEZE, /**< Slope generation on external stop trigger is: Freezes slope generation & feeds constantly + the value programmed in CSGyDSV2 to the DAC */ +} XMC_HRPWM_CSG_SLOPE_EXT_STOP_t; + +/** + * HRPWM CSG - Slice numbers + */ +typedef enum XMC_HRPWM_CSG_SLICE +{ + XMC_HRPWM_CSG_SLICE_0 = 0U, /**< CSG slice number is 0 */ + XMC_HRPWM_CSG_SLICE_1, /**< CSG slice number is 1 */ + XMC_HRPWM_CSG_SLICE_2 /**< CSG slice number is 2 */ +} XMC_HRPWM_CSG_SLICE_t; + +/** + * HRPWM CSG - Comparator output filter window + */ +typedef enum XMC_HRPWM_CSG_CMP_FILTER_WINDOW +{ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_2_CLK_CYCLES = 0U , /**< Needs to be stable for 2 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_3_CLK_CYCLES, /**< Needs to be stable for 3 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_4_CLK_CYCLES, /**< Needs to be stable for 4 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_5_CLK_CYCLES, /**< Needs to be stable for 5 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_6_CLK_CYCLES, /**< Needs to be stable for 6 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_7_CLK_CYCLES, /**< Needs to be stable for 7 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_8_CLK_CYCLES, /**< Needs to be stable for 8 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_9_CLK_CYCLES, /**< Needs to be stable for 9 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_10_CLK_CYCLES, /**< Needs to be stable for 10 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_11_CLK_CYCLES, /**< Needs to be stable for 11 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_12_CLK_CYCLES, /**< Needs to be stable for 12 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_13_CLK_CYCLES, /**< Needs to be stable for 13 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_14_CLK_CYCLES, /**< Needs to be stable for 14 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_15_CLK_CYCLES, /**< Needs to be stable for 15 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_16_CLK_CYCLES, /**< Needs to be stable for 16 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_32_CLK_CYCLES /**< Needs to be stable for 32 clk cycles */ +} XMC_HRPWM_CSG_CMP_FILTER_WINDOW_t; + +/** + * HRPWM CSG - Slope step gain + */ +typedef enum XMC_HRPWM_CSG_SLOPE_STEP_GAIN +{ + XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_1 = 0U, /**< slope step has an increment/decrement of 1 */ + XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_2, /**< slope step has an increment/decrement of 2 */ + XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_4, /**< slope step has an increment/decrement of 4 */ + XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_8 /**< slope step has an increment/decrement of 8 */ +} XMC_HRPWM_CSG_SLOPE_STEP_GAIN_t; + +/** + * HRPWM CSG - Slope step gain + */ +typedef enum XMC_HRPWM_CSG_PRESCALER_DIVISION +{ + XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_1 = 0U, /**< Division by 1 */ + XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_2, /**< Division by 2 */ + XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_4, /**< Division by 4 */ + XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_8 /**< Division by 8 */ +} XMC_HRPWM_CSG_PRESCALER_DIVISION_t; + +/********************************************************************************************************************* + * DATA STRUCTURES - HRPWM + ********************************************************************************************************************/ +/** + * Typedef for HRPWM Global registers data structure + */ +typedef HRPWM0_Type XMC_HRPWM_t; + +/** + * Typedef for HRPWM high resolution channel registers data structure + */ +typedef HRPWM0_HRC_Type XMC_HRPWM_HRC_t; + +/** + * Typedef for CSG unit registers data structure + */ +typedef HRPWM0_CSG_Type XMC_HRPWM_CSG_t; + +/** + * HRPWM HRC source path configuration + */ +typedef struct XMC_HRPWM_HRC_SRC_CONFIG +{ + XMC_HRPWM_HRC_HR_EDGE_t high_res_mode; /**< high resolution mode configuration */ + XMC_HRPWM_HRC_SRC_INPUT_t set_config; /**< Selection of input for set configuration */ + XMC_HRPWM_HRC_SRC_INPUT_t clear_config; /**< Selection of input clear configuration */ + XMC_HRPWM_HRC_CMP_SEL_t cmp_set; /**< Selection of comparator for set configuration */ + XMC_HRPWM_HRC_CMP_SEL_t cmp_clear; /**< Selection of comparator for clear configuration */ + XMC_HRPWM_HRC_TIMER_SEL_t timer_sel; /**< Selection of timer */ + XMC_HRPWM_HRC_SRC_EDGE_SEL_t set_edge_config; /**< Selection of edge for generating set signal */ + XMC_HRPWM_HRC_SRC_EDGE_SEL_t clear_edge_config; /**< Selection of edge for generating clear signal */ + XMC_HRPWM_FUNC_STATUS_t src_trap_enable; /**< Selection of source for trap signal generation */ +} XMC_HRPWM_HRC_SRC_CONFIG_t; + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * HRPWM HRC configuration + */ +typedef struct XMC_HRPWM_HRC_CONFIG +{ + union + { + struct + { + uint32_t : 2; + uint32_t : 2; + uint32_t : 4; + uint32_t dt_enable: 1; /**< Enables dead time. Accepts enum @ref XMC_HRPWM_FUNC_STATUS_t */ + uint32_t hr_out0_trap_enable: 1; /**< Enables trap for HROUT0. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t hr_out1_trap_enable: 1; /**< Enables trap for HROUT1. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t hrc_shadow_xfer_linktoCCU8: 1; /**< Shadow transfer for CR1 and CR2 linked to shadow transfer trigger of CCU8 slice. + Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t dt_shadow_xfer_linktoCCU8: 1; /**< Shadow transfer for DCR and DCF linked to shadow transfer trigger of CCU8 slice. + Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t hr_out0_inv_enable: 1; /**< Enables inversion of HROUT0 output pin. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t hr_out1_inv_enable: 1; /**< Enables inversion of HROUT1 output pin. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t : 1; + uint32_t dt_trigger_sel: 1; /**< Selection of trigger for dead time shadow transfer. Accepts enum XMC_HRPWM_HRC_DT_TR_SEL_t */ + uint32_t : 15; + }; + uint32_t gc; /**< General high resolution channel configuration */ + }; + + union + { + struct + { + uint32_t hr_out0_passive_level_out: 1; /**< Selection of HROUT0 passive level. Accepts enum XMC_HRPWM_HRC_OUT_PASSIVE_LVL_t */ + uint32_t hr_out1_passive_level_out: 1; /**< Selection of HROUT0 passive level. Accepts enum XMC_HRPWM_HRC_OUT_PASSIVE_LVL_t */ + uint32_t : 30; + }; + uint32_t psl; /**< Output passive level configuration */ + }; +} XMC_HRPWM_HRC_CONFIG_t; + +/*********************************************************************************************************************** + * DATA STRUCTURES - CSG + **********************************************************************************************************************/ +/** + * Configuration data structure of a CSG input selection + */ +typedef struct XMC_HRPWM_CSG_INPUT_CONFIG +{ + XMC_HRPWM_CSG_INPUT_SEL_t mapped_input; /**< CSG input selection */ + XMC_HRPWM_CSG_EDGE_SEL_t edge; /**< Active edge of mapped_input */ + XMC_HRPWM_CSG_LVL_SEL_t level; /**< Active level of mapped_input */ +} XMC_HRPWM_CSG_INPUT_CONFIG_t; + +/** + *CSG Unit - Comparator configuration + */ +typedef struct XMC_HRPWM_CSG_CMP +{ + union + { + struct + { + uint32_t : 4; + uint32_t : 4; + uint32_t cmp_input_sel: 1; /**< Comparator input pin selection. Accepts enum XMC_HRPWM_CSG_CMP_INPUT_t */ + uint32_t cmp_input_sw: 2; /**< Comparator input switching configuration. Accepts enum XMC_HRPWM_CSG_LVL_SEL_t */ + uint32_t cmp_ext_sw_enable: 1; /**< Enable switching of input between CINA and CINB via external trigger. + Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t cmp_out_inv: 1; /**< Invert comparator output. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t : 1; /*Enable Comparator output synchronization */ + uint32_t blanking_mode: 2; /**< Select the edge for blanking. Accepts enum XMC_HRPWM_CSG_EDGE_SEL_t */ + uint32_t blank_ext_enable: 1; /**< Enable blanking via external trigger. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t filter_enable: 1; /**< Enable comparator output filter. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t filter_window: 4; /**< Select the comparator output filter window */ + uint32_t : 2; + uint32_t filter_control: 2; /**< Select the filter application condition + 00B Filtering is always done if enabled + 01B Filtering is only done when CSGyDSV1 value is currently fed to the DAC + 10B Filtering is only done when the CSGyDSV2 value is currently fed to the DAC */ + uint32_t : 6; + }; + uint32_t cc; /**< Comparator general configuration */ + }; + + uint32_t blanking_val; /**< blanking value, blanking time = blanking_val * module clk freq */ + + union + { + struct + { + uint32_t : 4; + uint32_t : 4; + uint32_t clamp_ctrl_lvl: 2; /**< Select the trigger signal level for clamping the comparator output. + Accepts enum XMC_HRPWM_CSG_LVL_SEL_t */ + uint32_t clamp_level: 1; /**< Select the comparator output passive level value. */ + uint32_t clamp_exit_sw_config: 1; /**< Clamped state exit software configuration */ + uint32_t clamp_enter_config: 2; /**< Clamping level enter configuration */ + uint32_t clamp_exit_config: 2; /**< Clamping level exit configuration */ + uint32_t : 16; + }; + uint32_t plc; /**< Comparator passive level configuration */ + }; +} XMC_HRPWM_CSG_CMP_t; + +/** + * CSG Unit - DAC configuration + */ +typedef struct XMC_HRPWM_CSG_DAC +{ + XMC_HRPWM_CSG_SWSM_t start_mode; /**< Initial DAC start mode */ + uint32_t dac_dsv1; /**< DAC reference value 1 */ + uint32_t dac_dsv2; /**< DAC reference value 2 */ +} XMC_HRPWM_CSG_DAC_t; + +/** + * CSG Unit - Slope Generation configuration + */ +typedef struct XMC_HRPWM_CSG_SGEN +{ + union + { + struct + { + uint32_t prescaler_ext_start_mode: 2; /**< Pre-scaler external start mode. Accepts enum XMC_HRPWM_CSG_PRESCALER_EXT_START_t */ + uint32_t prescaler_ext_stop_mode: 2; /**< Pre-scaler external stop mode. Accepts enum XMC_HRPWM_CSG_PRESCALER_EXT_STOP_t */ + uint32_t fixed_prescaler_enable: 1; /**< Fixed pre-scaler, 0:enabled, 1:disabled */ + uint32_t prescaler: 2; /**< Pre-scaler division factor */ + uint32_t : 1; + uint32_t ctrl_mode: 2; /**< Slope control mode. Accepts enum XMC_HRPWM_CSG_SLOPE_CTRL_MODE_t */ + uint32_t ext_start_mode: 2; /**< Slope external start mode. Accepts enum XMC_HRPWM_CSG_SLOPE_EXT_START_t */ + uint32_t ext_stop_mode: 2; /**< Slope external stop mode. Accepts enum XMC_HRPWM_CSG_SLOPE_EXT_STOP_t */ + uint32_t slope_ref_val_mode: 2; /**< Slope reference value mode */ + uint32_t : 2; /* start_mode */ + uint32_t step_gain: 2; /**< Slope step gain configuration */ + uint32_t static_mode_ist_enable: 1; /**< Immediate shadow transfer in static mode enabled. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t pulse_swallow_enable: 1; /**< Pulse swallow enable / disable. Accepts enum XMC_HRPWM_FUNC_STATUS_t */ + uint32_t : 2; + uint32_t pulse_swallow_win_mode: 2; /**< Pulse swallow window mode */ + uint32_t : 6; + }; + uint32_t sc; /**< Slope Generation Configuration */ + }; + uint32_t pulse_swallow_val; /**< Pulse swallow value */ +} XMC_HRPWM_CSG_SGEN_t; + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +/** + * HRPWM CSG configuration + */ +typedef struct XMC_HRPWM_CSG_CONFIG +{ + XMC_HRPWM_CSG_CMP_t cmp_config; /**< Comparator set up */ + XMC_HRPWM_CSG_DAC_t dac_config; /**< DAC configuration of CSG */ + XMC_HRPWM_CSG_SGEN_t sgen_config; /**< Slope generation related configurations */ +} XMC_HRPWM_CSG_CONFIG_t; + +/*********************************************************************************************************************** + * API PROTOTYPES + **********************************************************************************************************************/ +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return XMC_HRPWM_STATUS_t + * + * \parDescription + *
HRPWM Init
\n + * + * This function initializes the HRPWM global registers. It configures the CSG trimming data. + * This is the first function that needs to be called in initializing HRC or CSG modules. + * + * \parRelated APIs:
+ * XMC_SDMMC_TriggerEvent()\n\n\n + + */ +XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm); + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Enable global high resolution generation
\n + * + * Enables global high resolution generation by setting GLBANA.GHREN bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_DisableGlobalHR()
+ */ +void XMC_HRPWM_EnableGlobalHR(XMC_HRPWM_t *const hrpwm); + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Disable global high resolution generation
\n + * + * Disables global high resolution generation by clearing GLBANA.GHREN bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableGlobalHR()
+ */ + +void XMC_HRPWM_DisableGlobalHR(XMC_HRPWM_t *const hrpwm); + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Enables the bias generation
\n + * + * Enables the bias generation of high resolution generation by setting HRBSC.HRBE bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_DisableBias()
+ */ + +__STATIC_INLINE void XMC_HRPWM_EnableBias(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_EnableBias:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRBSC |= HRPWM0_HRBSC_HRBE_Msk; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Disables the bias generation
\n + * + * Disables the bias generation of high resolution generation by clearing HRBSC.HRBE bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableBias()
+ */ +__STATIC_INLINE void XMC_HRPWM_DisableBias(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_DisableBias:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRBSC &= ~(HRPWM0_HRBSC_HRBE_Msk); +} + +/*********************************************************************************************************************** + * API PROTOTYPES - HRPWM HRC GLOBAL + **********************************************************************************************************************/ +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return XMC_HRPWM_HR_LOGIC_t + * + * \parDescription + *
Returns the status of the high resolution logic.
\n + * + * Returns status of the high resolution logic by checking HRGHRS.HRGR bit. + * The return value should be @ref XMC_HRPWM_HR_LOGIC_WORKING for proper generation of high resolution signal positioning. + */ + +XMC_HRPWM_HR_LOGIC_t XMC_HRPWM_GetHRGenReadyStatus(XMC_HRPWM_t *const hrpwm); + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HR_PATH_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the high resolution path.
\n + * + * Enables the high resolution path determined by passed mask value, by setting HRCCFG.HRC0E bit. + * By default signals from source selector 0 are linked to HR path and signals from source selector 1 are linked to LR path. + * This connections can be reversed at runtime, if bit HRCySC.ST is set to 1. + * + * \parRelated APIs:
+ * XMC_HRPWM_HRC_Set_HR_Source()
+ * XMC_HRPWM_DisableHighResolutionPath()
+ * XMC_HRPWM_EnableLowResolutionPath()
+ * XMC_HRPWM_DisableLowResolutionPath()
+ * XMC_HRPWM_EnableHRPowerMode()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_EnableHighResolutionPath(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_EnableHighResolutionPath:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCFG |= mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HR_PATH_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the high resolution path
\n + * + * Disables the high resolution path determined by passed mask value, by clearing HRCCFG.HRC0E bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionPath()
+ * XMC_HRPWM_EnableLowResolutionPath()
+ * XMC_HRPWM_DisableLowResolutionPath()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_DisableHighResolutionPath(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_DisableHighResolutionPath:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCFG &= ~mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_LR_PATH_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the low resolution path
\n + * + * Enables the low resolution path determined by passed mask value, by setting HRCCFG.LRC0E bit. + * By default signals from source selector 0 are linked to HR path and signals from source selector 1 are linked to LR path. + * This connections can be reversed at runtime, if bit HRCySC.ST is set to 1. + * + * \parRelated APIs:
+ * XMC_HRPWM_HRC_Set_HR_Source()
+ * XMC_HRPWM_EnableHighResolutionPath()
+ * XMC_HRPWM_DisableHighResolutionPath()
+ * XMC_HRPWM_DisableLowResolutionPath()
+ * XMC_HRPWM_EnableHRPowerMode()
+ */ + +__STATIC_INLINE void XMC_HRPWM_EnableLowResolutionPath(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_EnableLowResolutionPath:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCFG |= mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_LR_PATH_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the low resolution path
\n + * + * Disables the low resolution path determined by passed mask value, by clearing HRCCFG.LRC0E bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionPath()
+ * XMC_HRPWM_DisableHighResolutionPath()
+ * XMC_HRPWM_EnableLowResolutionPath()
+ * + */ + __STATIC_INLINE void XMC_HRPWM_DisableLowResolutionPath(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_DisableLowResolutionPath:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCFG &= ~mask; +} + + /** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HRC_SHADOW_TX_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the high resolution shadow transfer
\n + * + * Enables the high resolution shadow transfer determined by passed mask value, by setting HRCSTRG.H0ES, HRCSTRG.H0DES bits. + * The input for trigger for shadow transfer needs to be configured correctly. + * + * \parRelated APIs:
+ * XMC_HRPWM_DisableHighResolutionShadowTransfer()
+ * XMC_HRPWM_GetHighResolutionShadowTransferStatus()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_EnableHighResolutionShadowTransfer(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_EnableHighResolutionShadowTransfer:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCSTRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HRC_SHADOW_TX_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the high resolution shadow transfer
\n + * + * Disables the high resolution shadow transfer determined by passed mask value, by setting HRCCTRG.H0EC, HRCCTRG.H0DEC bits. + * It cancels shadow transfer request by @ref XMC_HRPWM_EnableHighResolutionShadowTransfer(), provided the shadow transfer has not occurred. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_DisableHighResolutionShadowTransfer(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_DisableHighResolutionShadowTransfer:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCTRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HRC_SHADOW_TX_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Returns the shadow transfer request status
\n + * + * Returns the shadow transfer request status, by checking HRCSTSG.H0STE, HRCSTSG.H0DSTE bits. + * Returns a non zero value if corresponding shadow transfer request has been performed. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * + */ +__STATIC_INLINE uint32_t XMC_HRPWM_GetHighResolutionShadowTransferStatus(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_GetHighResolutionShadowTransferStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return (hrpwm->HRCSTSG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Turns ON the power to all HR and LR path
\n + * + * Turns ON the power to all HR and LR path by setting HRCCFG.HRCPM bit. Enable the HR and LR paths as per requirement by + * calling following API @ref XMC_HRPWM_EnableHighResolutionPath() and @ref XMC_HRPWM_EnableLowResolutionPath(). + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionPath()
+ * XMC_HRPWM_EnableLowResolutionPath()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_EnableHRPowerMode(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_EnableHRPowerMode:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->HRCCFG |= HRPWM0_HRCCFG_HRCPM_Msk; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return None + * + * \parDescription + *
Turns OFF the power to all HR and LR path
\n + * + * Turns OFF the power to all HR and LR path by clearing HRCCFG.HRCPM bit. + * This disables all HR and LR paths. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHRPowerMode()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_DisableHRPowerMode(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_DisableHRPowerMode:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + /* Turn off high resolution generation logic */ + hrpwm->HRCCFG &= ~(HRPWM0_HRCCFG_HRCPM_Msk); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param clk_freq The operating clock frequency of HRPWM module. Use the enum type @ref XMC_HRPWM_CLK_FREQ_t to generate the mask. + * @return None + * + * \parDescription + *
Configures the clock frequency of operation of HRPWM module
\n + * + * Configures the clock frequency of operation of HRPWM module by configuring HRCCFG.CLKC bits. + * The clock is generally selected based on the device type selected. + * + */ + +__STATIC_INLINE void XMC_HRPWM_ModuleClkFreq(XMC_HRPWM_t *const hrpwm, const XMC_HRPWM_CLK_FREQ_t clk_freq) +{ + XMC_ASSERT("XMC_HRPWM_ModuleClkFreq:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + hrpwm->HRCCFG &= ~(HRPWM0_HRCCFG_CLKC_Msk); + hrpwm->HRCCFG |= (clk_freq << HRPWM0_HRCCFG_CLKC_Pos); +} + +/*********************************************************************************************************************** + * API PROTOTYPES - HRPWM CSG GLOBAL + **********************************************************************************************************************/ +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the operation of comparator
\n + * + * Enables the operation of comparator by setting CSGSETG.SC0R bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_StopComparator()
+ * XMC_HRPWM_IsComparatorRunning()
+ */ + +__STATIC_INLINE void XMC_HRPWM_StartComparator(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StartComparator:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGSETG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the operation of comparator
\n + * + * Disables the operation of comparator by setting CSGCLRG.CC0R bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_StartComparator()
+ * XMC_HRPWM_IsComparatorRunning()
+ */ +__STATIC_INLINE void XMC_HRPWM_StopComparator(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StopComparator:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGCLRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return bool + * + * \parDescription + *
Checks if comparator is enabled
\n + * + * Checks if comparator is enabled by checking CSGSTATG.C0RB bit. + * Returns true if comparator run bit is set, else returns false. + * + * \parRelated APIs:
+ * XMC_HRPWM_StartComparator()
+ * XMC_HRPWM_StopComparator()
+ */ +__STATIC_INLINE bool XMC_HRPWM_IsComparatorRunning(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + bool status; + + XMC_ASSERT("XMC_HRPWM_IsComparatorRunning:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + if(hrpwm->CSGSTATG & mask) + { + status = true; + } + else + { + status = false; + } + + return (status); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the operation of CSG DAC
\n + * + * Enables the operation of CSG DAC by setting CSGSETG.SD0R bit. + * The DAC operation is enabled. Either the value in DSV1 or DSV2 is sent to DAC, based on configuration. + * + * \parRelated APIs:
+ * XMC_HRPWM_StopDac()
+ * XMC_HRPWM_IsDacRunning()
+ */ + +__STATIC_INLINE void XMC_HRPWM_StartDac(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StartDac:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGSETG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the operation of CSG DAC
\n + * + * Disables the operation of CSG DAC by setting CSGCLRG.CD0R bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_StartDac()
+ * XMC_HRPWM_IsDacRunning()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_StopDac(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StopDac:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGCLRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Checks if CSG DAC is operational
\n + * + * Checks if CSG DAC is operational by checking CSGSTATG.D0RB bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_StartDac()
+ * XMC_HRPWM_StopDac()
+ */ +__STATIC_INLINE uint32_t XMC_HRPWM_IsDacRunning(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_IsDacRunning:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return (hrpwm->CSGSTATG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Set the comparator output to clamp state
\n + * + * Sets the comparator to clamped state via software by setting CSGSETG.SC0P bit. The output of comparator is now not dependent on its inputs pins. + * The clamped state is defined by comparator output passive level value. Output passive level can be set to high or low. + * + * \parRelated APIs:
+ * XMC_HRPWM_UnClampComparatorOutput()
+ * XMC_HRPWM_IsComparatorClamped()
+ */ + +__STATIC_INLINE void XMC_HRPWM_ClampComparatorOutput(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_ClampComparatorOutput:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + hrpwm->CSGSETG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Clear the comparator output from clamp state
\n + * + * Un-clamps the output of comparator from clamped state set via software by setting CSGCLRG.CC0P bit. The output of + * comparator is now dependent on the inputs of comparator. + * + * \parRelated APIs:
+ * XMC_HRPWM_ClampComparatorOutput()
+ * XMC_HRPWM_IsComparatorClamped()
+ */ +__STATIC_INLINE void XMC_HRPWM_UnClampComparatorOutput(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_UnClampComparatorOutput:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + hrpwm->CSGCLRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Checks if comparator is in clamped state
\n + * + * Checks if comparator is in clamped state by checking CSGSTATG.PSLS0 bit. + * Returns bit encoded status if comparator is set to clamped state via software. + * + * \parRelated APIs:
+ * XMC_HRPWM_ClampComparatorOutput()
+ * XMC_HRPWM_UnClampComparatorOutput()
+ */ + +__STATIC_INLINE uint32_t XMC_HRPWM_IsComparatorClamped(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_IsComparatorClamped:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + return (hrpwm->CSGSTATG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Returns bit encoded status of multiple DACs and Comparators, defined by the mask.
\n + * + * Returns bit encoded status of multiple DACs and Comparators from register CSGSTATG, defined by the mask. + * The mask is generated by bitwise ORing multiple Enums.
+ * mask = (uint32_t) (XMC_HRPWM_CSG_RUN_BIT_CMP0 | XMC_HRPWM_CSG_RUN_BIT_DAC0 | XMC_HRPWM_CSG_RUN_BIT_CMP0_PSL); + * + * \parRelated APIs:
+ * XMC_HRPWM_IsDacRunning()
+ * XMC_HRPWM_IsComparatorClamped()
+ */ + +__STATIC_INLINE uint32_t XMC_HRPWM_GetRunBitStatus(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_GetRunBitStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return (hrpwm->CSGSTATG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Start the prescaler & slope generation of DAC
\n + * + * Start the prescaler & slope generation of DAC by setting CSGFCG.S0STR and CSGFCG.PS0STR bits. + * The mask is generated by bitwise ORing multiple Enums.
+ * mask = (uint32_t) (XMC_HRPWM_CSG_SLOPE_START_DAC0 | XMC_HRPWM_CSG_PRESCALER_START_CSG0); + * + * \parRelated APIs:
+ * XMC_HRPWM_StopSlopeGeneration()
+ * XMC_HRPWM_IsSlopeGenerationRunning()
+ */ + +__STATIC_INLINE void XMC_HRPWM_StartSlopeGeneration(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StartSlopeGeneration:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGFCG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return None + * + * \parDescription + *
Stops the prescaler & slope generation of DAC
\n + * + * Stops the prescaler & slope generation of DAC by setting CSGFCG.S0STP and CSGFCG.PS0STP bits. + * The mask is generated by bitwise ORing multiple Enums.
+ * mask = (uint32_t) (XMC_HRPWM_CSG_SLOPE_START_DAC0 | XMC_HRPWM_CSG_PRESCALER_START_CSG0); + * + * \parRelated APIs:
+ * XMC_HRPWM_StartSlopeGeneration()
+ * XMC_HRPWM_IsSlopeGenerationRunning()
+ */ +__STATIC_INLINE void XMC_HRPWM_StopSlopeGeneration(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_StopSlopeGeneration:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGFCG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_RUN_BIT_t to generate the mask. + * @return bool + * + * \parDescription + *
Checks if Prescaler & slope generation is running
\n + * + * Checks if Prescaler & slope generation is running by checking CSGFSG.S0RB CSGFSG.P0RB bits. + * The mask is generated by bitwise ORing multiple Enums.
+ * mask = (uint32_t) (XMC_HRPWM_CSG_SLOPE_START_DAC0 | XMC_HRPWM_CSG_PRESCALER_START_CSG0); + * + * \parRelated APIs:
+ * XMC_HRPWM_StartSlopeGeneration()
+ * XMC_HRPWM_StopSlopeGeneration()
+ */ +__STATIC_INLINE bool XMC_HRPWM_IsSlopeGenerationRunning(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + bool status; + + XMC_ASSERT("XMC_HRPWM_IsSlopeGenerationRunning:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + if (hrpwm->CSGFSG & mask) + { + status = true; + } + else + { + status = false; + } + + return (status); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_SHADOW_TX_DAC_t to generate the mask. + * @return None + * + * \parDescription + *
Enables the shadow transfer of DSV1 and pulse swallow registers of DACs selected by mask
\n + * + * Enables the shadow transfer of DSV1 and pulse swallow registers of DACs selected by mask by setting CSGTRG.D0SES bit. + * The transfer is done at the next shadow transfer trigger. + * + * \parRelated APIs:
+ * XMC_HRPWM_DisableComparatorShadowTransfer()
+ * XMC_HRPWM_GetComparatorShadowTransferStatus()
+ */ +__STATIC_INLINE void XMC_HRPWM_EnableComparatorShadowTransfer(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_EnableComparatorShadowTransfer:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGTRG = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_SHADOW_TX_DAC_t to generate the mask. + * @return None + * + * \parDescription + *
Cancels the shadow transfer of DSV1 and pulse swallow registers
\n + * + * Cancels the shadow transfer of DSV1 and pulse swallow registers by setting CSGTRC.D0SEC bit. + * The transfer request is canceled. Needs to be called before the next shadow transfer trigger. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableComparatorShadowTransfer()
+ * XMC_HRPWM_GetComparatorShadowTransferStatus()
+ */ + +__STATIC_INLINE void XMC_HRPWM_DisableComparatorShadowTransfer(XMC_HRPWM_t *const hrpwm, uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_DisableComparatorShadowTransfer:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGTRC = mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @return uint32_t + * + * \parDescription + *
Gets the shadow transfer status of DSV1 and pulse swallow registers of all the DACs
\n + * + * Gets the shadow transfer status of DSV1 and pulse swallow registers of all the DACs by checking the register CSGTRSG + * The return value is not zero if shadow transfer has been requested, but is still pending completion. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableComparatorShadowTransfer()
+ * XMC_HRPWM_DisableComparatorShadowTransfer()
+ */ +__STATIC_INLINE uint32_t XMC_HRPWM_GetComparatorShadowTransferStatus(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_GetComparatorShadowTransferStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return(hrpwm->CSGTRSG & XMC_HRPWM_COMPARATOR_STATUS); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_PRESCALER_STATUS_t to generate the mask. + * @return None + * + * \parDescription + *
Clears the prescaler registers of DACs selected by mask
\n + * + * Clears the prescaler registers of DACs selected by mask, by setting CSGFCG.PS0CLR bit. + * + * \parRelated APIs:
+ * XMC_HRPWM_IsPrescalerRunning()
+ */ +__STATIC_INLINE void XMC_HRPWM_ClearPreScaler(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_ClearPreScaler:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGFCG |= mask; +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_PRESCALER_STATUS_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Checks the prescaler status of DACs selected by mask
\n + * + * Checks the prescaler status of DACs selected by mask, by checking CSGFCG.P0RB bit. + * Returns the bit encoded status information of prescaler. + * + * \parRelated APIs:
+ * XMC_HRPWM_ClearPreScaler()
+ * XMC_HRPWM_StartSlopeGeneration()
+ */ +__STATIC_INLINE uint32_t XMC_HRPWM_IsPrescalerRunning(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_IsPrescalerRunning:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return (hrpwm->CSGFSG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_SWITCH_CMP_INPUT_t to generate the mask. + * @return uint32_t + * + * \parDescription + *
Returns the bit encoded status of HW pin connected to comparator inverting pin
\n + * + * Returns the bit encoded status of HW pin connected to comparator inverting pin by checking CSGTRSG.SW0ST bit. + * The bit position is set to 1 if CINB is connected, else its CINA. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_SetCMPInput()
+ */ + +__STATIC_INLINE uint32_t XMC_HRPWM_GetCMPInput(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_GetCMPInput:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + return (hrpwm->CSGTRSG & mask); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param slice Slice NO. + * @param power_mode The mode to be put in. + * @return None + * + * \parDescription + *
Sets the DAC in OFF, Low speed or High speed mode
\n + * + * Sets the DAC in OFF, Low speed or High speed mode, by setting CSGCFG.C0PM bits. + * + * \parRelated APIs:
+ * + */ +__STATIC_INLINE void XMC_HRPWM_SetCsgPowerMode(XMC_HRPWM_t *const hrpwm, + const XMC_HRPWM_CSG_SLICE_t slice, + const XMC_HRPWM_CSG_POWER_MODE_t power_mode) +{ + XMC_ASSERT("XMC_HRPWM_SetCsgPowerMode:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + hrpwm->CSGCFG &= ~(3U << (slice * 2U)); + hrpwm->CSGCFG |= power_mode << (slice * 2U); +} + +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_CLK_t to generate the mask. + * @return None + * + * \parDescription + *
Disables the clock of selected CSG subunits
\n + * + * Disables the clock of selected CSG subunits by setting the CSGCFG.C0CD bit. + * + * \parRelated APIs:
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_DisableCsgClock(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_DisableCsgClock:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + hrpwm->CSGCFG |= mask; +} + +/*********************************************************************************************************************** + * API PROTOTYPES - HRPWM HRC CHANNEL + **********************************************************************************************************************/ +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Initializes the HRC channel.
\n + * + * Initializes the HRC channel functionality.
+ * These include:
+ * 1) Dead time configuration.
+ * 3) Trap Configuration.
+ * 4) Shadow transfer configuration.
+ * 5) Output inversion configuration.
+ * 6) Passive levels of HRC outputs.
+ */ + +void XMC_HRPWM_HRC_Init(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_CONFIG_t *const config); + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Initializes the source 0 of HRC channel.
\n + * + * Initialize the source 0 functionality of HRC channel.
+ * This include:
+ * 1) general configuration for source 0 HRC channel.
+ * 2) Configuration of which inputs are being used to generate the set and clear for the latch and therefore controlling + * the generation of the output PWM signal.
+ * 3) Configuration for which timer from the Capture/Compare Unit is used for the Source Selector 0 and Source Selector 1.
+ * + * \parRelated APIs:
+ * XMC_HRPWM_HRC_ConfigSourceSelect1()
+ */ + + +void XMC_HRPWM_HRC_ConfigSourceSelect0(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config); + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Initializes the source 1 of HRC channel.
\n + * + * Initialize the source 1 functionality of HRC channel.
\n + * This include:
+ * 1) general configuration for source 1 HRC channel.
+ * 2) Configuration of which inputs are being used to generate the set and clear for the latch and therefore controlling + * the generation of the output PWM signal.
+ * 3) Configuration for which timer from the Capture/Compare Unit is used for the Source Selector 0 and Source Selector 1.
+ * + * \parRelated APIs:
+ * XMC_HRPWM_HRC_ConfigSourceSelect0()
+ */ + +void XMC_HRPWM_HRC_ConfigSourceSelect1(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config); + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param cr1_value high resolution positioning value. + * @return None + * + * \parDescription + *
Sets the shadow transfer register of high resolution positioning for rising edge
\n + * + * Call the shadow transfer update API for transfer to CR1 register. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * XMC_HRPWM_HRC_SetCompare2()
+ */ +__STATIC_INLINE void XMC_HRPWM_HRC_SetCompare1(XMC_HRPWM_HRC_t *const hrc, const uint8_t cr1_value) +{ + XMC_ASSERT("XMC_HRPWM_HRC_SetCompare1:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + hrc->SCR1 = (uint32_t) cr1_value; +} + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param cr2_value high resolution positioning value. + * @return None + * + * \parDescription + *
Sets the shadow transfer register of high resolution positioning for falling edge
\n + * + * Call the shadow transfer update API for transfer to CR2 register. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * XMC_HRPWM_HRC_SetCompare1()
+ */ +__STATIC_INLINE void XMC_HRPWM_HRC_SetCompare2(XMC_HRPWM_HRC_t *const hrc, const uint8_t cr2_value) +{ + XMC_ASSERT("XMC_HRPWM_HRC_SetCompare2:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + hrc->SCR2 = (uint32_t) cr2_value; +} + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param dcr_value Rising edge dead time value. + * @return None + * + * \parDescription + *
Sets the shadow transfer register of rising edge dead time.
\n + * + * Call the shadow transfer update API for transfer to DCR register. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * XMC_HRPWM_HRC_SetDeadTimeFalling()
+ */ + +__STATIC_INLINE void XMC_HRPWM_HRC_SetDeadTimeRising(XMC_HRPWM_HRC_t *const hrc, uint16_t dcr_value) +{ + XMC_ASSERT("XMC_HRPWM_HRC_SetDeadTimeRising:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + hrc->SDCR = (uint32_t) dcr_value; +} + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param dcf_value Falling edge dead time value. + * @return None + * + * \parDescription + *
Sets the shadow transfer register of falling edge dead time.
\n + * + * Call the shadow transfer update API for transfer to DCR register. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * XMC_HRPWM_HRC_SetDeadTimeRising()
+ */ +__STATIC_INLINE void XMC_HRPWM_HRC_SetDeadTimeFalling(XMC_HRPWM_HRC_t *const hrc, uint16_t dcf_value) +{ + XMC_ASSERT("XMC_HRPWM_HRC_SetDeadTimeFalling:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + hrc->SDCF = (uint32_t) dcf_value; +} + +/** + * @param hrc Constant pointer to XMC_HRPWM_HRC_t, pointing to the HRC channel base address + * @param source Source connected to high resolution channel. + * @return None + * + * \parDescription + *
Sets the source to high resolution channel
\n + * + * Sets the shadow transfer register deciding the source connected to high resolution channel. + * This also affects the CCU8 timer used for linking shadow transfer trigger. + * Call the shadow transfer update API. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ */ + +__STATIC_INLINE void XMC_HRPWM_HRC_Set_HR_Source(XMC_HRPWM_HRC_t *const hrc, XMC_HRPWM_HRC_SOURCE_t source) +{ + XMC_ASSERT("XMC_HRPWM_HRC_Set_HR_Source:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + hrc->SSC = (uint32_t) source; +} + +/*********************************************************************************************************************** + * API PROTOTYPES - HRPWM CSG SLICE + **********************************************************************************************************************/ + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Initializes the CSG channel.
\n + * + * This function is used to initialize the CSG channel.
\n + * These include:
+ * 1) Comparator setup.
+ * 2) DAC Configuration.
+ * 3) Slope generation configuration.
+ */ +void XMC_HRPWM_CSG_Init(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param input Input to comparator. Use the enum type @ref XMC_HRPWM_CSG_CMP_INPUT_t to generate the input. + * @return None + * + * \parDescription + *
Configures the input connection to inverting pin of comparator
\n + * + * Selects the HW pin that gets connected to inverting pin of comparator.
+ * Either CINA or CINB can be set. + * The non-inverting pin is connected to DAC output. + * + * \parRelated APIs:
+ * XMC_HRPWM_GetCMPInput() + */ +void XMC_HRPWM_CSG_SetCMPInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CMP_INPUT_t input); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configures the input signal to blank the comparator output
\n + * + * Configures the input signal that is used as trigger signal to blank the comparator output.
+ * It configures the signal source, required edge or level. + * The comparator output is blanked and set to passive level. + * + */ +void XMC_HRPWM_CSG_SelBlankingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configures the input signal to clamp the comparator output
\n + * + * Configures the input signal that is used as level signal to clamp the comparator output.
+ * It configures the signal source and required level. + * + */ +void XMC_HRPWM_CSG_SelClampingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configures the input signal to start the DAC slope generation
\n + * + * Configures the input signal that is used as trigger signal to start the slope generation.
+ * It configures the signal source, required edge or level. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_StopSlopeGenConfig()
+ * + */ + +void XMC_HRPWM_CSG_StartSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configures the input signal to stop the DAC slope generation
\n + * + * Configures the input that is used as trigger signal to stop the slope generation.
+ * It configures the signal source, required edge or level. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_StartSlopeGenConfig()
+ */ + +void XMC_HRPWM_CSG_StopSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configures the input signal to trigger the DAC conversion
\n + * + * Configures the input signal that is used as trigger signal to perform the DAC conversion.
+ * It configures the signal source, required edge or level.
+ * This is used when DAC is configured in static mode. + * + */ + +void XMC_HRPWM_CSG_TriggerDACConvConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configure input selection for triggering shadow transfer
\n + * + * Configure the signal used to triggering shadow transfer.
+ * It configures the signal source, required edge or level. + * + */ + +void XMC_HRPWM_CSG_TriggerShadowXferConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param config Pointer to configuration structure. + * @return None + * + * \parDescription + *
Configure input selection for switching DAC value between DSV1 and DSV2.
\n + * + * Configure the signal used to switch DAC value between DSV1 and DSV2.
+ * It configures the signal source, required edge or level. + * + */ + + +void XMC_HRPWM_CSG_DACRefValSwitchingConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param input_clk Clock selection. + * @return None + * + * \parDescription + *
Select the clock for slope generation
\n + * + * Selects the clock source used for slope generation.
+ * These are :
+ * module clock
+ * external clock A
+ * external clock B
+ * external clock C
+ * + */ + +void XMC_HRPWM_CSG_SelSlopeGenClkInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CLK_INPUT_t input_clk); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param event Event selected for interrupt. + * @param sr Service request node. + * @return None + * + * \parDescription + *
Connects the interrupt request to serve node
\n + * + * Enables the connection between interrupt request and serve node.
+ * Each event may be connected to any of four service node available. + * Each event/interrupt needs to be enabled individually. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_EnableEvent()
+ * XMC_HRPWM_CSG_GetEventStatus()
+ */ + +void XMC_HRPWM_CSG_SetSRNode(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_IRQ_ID_t event, + const XMC_HRPWM_CSG_IRQ_SR_LINE_t sr); + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param mask masked values of selected CSG modules. Use the enum type @ref XMC_HRPWM_CSG_IRQ_ID_t to generate the input. + * @return uint32_t + * + * \parDescription + *
Returns the bit encoded status of selected events
\n + * + * Checks the status of selected events. The return value is non-zero is the status is set. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_EnableEvent()
+ * XMC_HRPWM_CSG_SetSRNode()
+ * + */ +__STATIC_INLINE uint32_t XMC_HRPWM_CSG_GetEventStatus(XMC_HRPWM_CSG_t *const csg, const uint32_t mask) +{ + XMC_ASSERT("XMC_HRPWM_CSG_GetEventStatus:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + return (csg->ISTAT & mask); +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param value Value to be written to DSV2 register. + * @return None + * + * \parDescription + *
Updates the DSV2 register
\n + * + * Updates the DSV2 register.
+ * Note DSV2 register does not have shadow register. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_UpdateDACRefDSV1()
+ */ +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateDACRefDSV2(XMC_HRPWM_CSG_t *const csg, uint32_t value) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateDACRefDSV2:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->DSV2 = value & HRPWM0_CSG_DSV2_DSV2_Msk; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param value Value to be written to blanking register. + * @return None + * + * \parDescription + *
Updates the BLV register
\n + * + * Updates the blanking register.
+ * Note BLV register does not have shadow register. + * + */ +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateBlankingValue(XMC_HRPWM_CSG_t *const csg, uint8_t value) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateBlankingValue:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->BLV = (uint32_t) value; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param window Size of filter window. + * @return None + * + * \parDescription + *
Updates the filter window size
\n + * + * Updates the filter window size used for pulse swallowing, in slope generation.
+ * This value is used in slope generation when filter window is enabled. + * A certain no of clock pulses in the filter window are swallowed and applied to slope generation. + * The pulse swallowed are determined by "Pulse swallow value" + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_UpdatePulseClk()
+ */ + +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateFilterWindow(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_CMP_FILTER_WINDOW_t window) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateFilterWindow:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->CC &= ~(HRPWM0_CSG_CC_COFM_Msk); + csg->CC |= (uint32_t) window << HRPWM0_CSG_CC_COFM_Pos; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param value No of clock pulses to be swallowed in the filter window. + * @return None + * + * \parDescription + *
Updates the no of clock pulses to be swallowed in the filter window
\n + * + * Update the pulse swallow value.
+ * This value is used in slope generation when filter window is enabled for slope generation. + * No of clock pulse swallow is determined by this value. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_UpdateFilterWindow()
+ */ + +__STATIC_INLINE void XMC_HRPWM_CSG_UpdatePulseClk(XMC_HRPWM_CSG_t *const csg, uint32_t value) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdatePulseClk:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SPC = value & HRPWM0_CSG_SPC_SPSWV_Msk; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param value Value to be written to DSV1 shadow register. + * @return None + * + * \parDescription + *
Updates the DSV1 shadow register
\n + * + * Update the DSV1 shadow register.
+ * Call the shadow transfer update API. + * A shadow transfer request in corresponding CCU8 slice may also be required. + * + * \parRelated APIs:
+ * XMC_HRPWM_EnableHighResolutionShadowTransfer()
+ * XMC_HRPWM_CSG_UpdateDACRefDSV2()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateDACRefDSV1(XMC_HRPWM_CSG_t *const csg, uint32_t value) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateDACRefDSV1:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SDSV1 = value & HRPWM0_CSG_SDSV1_SDSV1_Msk; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param gain Gain value. + * @return None + * + * \parDescription + *
Updates the gain value of slope generation
\n + * + * Updates the gain value of slope generation by setting SC.GCFG bits. + * The value by which DAC increments/decrements is determined by the step gain. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_UpdateDACPrescaler()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateDACStepGain(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_SLOPE_STEP_GAIN_t gain) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateDACStepGain:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SC &= ~(HRPWM0_CSG_SC_GCFG_Msk); + csg->SC |= (uint32_t) gain << HRPWM0_CSG_SC_GCFG_Pos; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param div_value Prescaler value. + * @return None + * + * \parDescription + *
Updates the prescaler value of slope generation
\n + * + * Updates the prescaler value of slope generation by setting SC.PSV + * The rate of DAC value update is determined by prescaler. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_UpdateDACStepGain()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_CSG_UpdateDACPrescaler(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_PRESCALER_DIVISION_t div_value) +{ + XMC_ASSERT("XMC_HRPWM_CSG_UpdateDACPrescaler:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SC &= ~(HRPWM0_CSG_SC_PSV_Msk); + csg->SC |= (uint32_t) div_value << HRPWM0_CSG_SC_PSV_Pos; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param event Event selected for interrupt. + * @return None + * + * \parDescription + *
Enables the interrupt
\n + * + * Enables the selected interrupt request which may be forwarded to service node. + * The enabled event may be connected to any of the four service nodes. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_DisableEvent()
+ * XMC_HRPWM_CSG_GetEventStatus()
+ * XMC_HRPWM_CSG_SetSRNode()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_CSG_EnableEvent(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_HRPWM_CSG_EnableEvent:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SRE |= event; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param event Event selected for interrupt. + * @return None + * + * \parDescription + *
Disables the interrupt
\n + * + * Disables the selected interrupt request which may be forwarded to service node. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_EnableEvent()
+ * XMC_HRPWM_CSG_GetEventStatus()
+ * XMC_HRPWM_CSG_SetSRNode()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_CSG_DisableEvent(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_HRPWM_CSG_DisableEvent:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SRE &= ~event; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param event Event selected for software trigger. + * @return None + * + * \parDescription + *
Software request for selected event
\n + * + * Perform a software request for selected event.This overrides any hardware trigger. + * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_EnableEvent()
+ * XMC_HRPWM_CSG_GetEventStatus()
+ * XMC_HRPWM_CSG_SetSRNode()
+ * XMC_HRPWM_CSG_ClrEventSW()
+ * + */ + +__STATIC_INLINE void XMC_HRPWM_CSG_SetEventSW(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_HRPWM_CSG_SetEventSW:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SWS = event; +} + +/** + * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address + * @param event Event selected for software trigger. + * @return None + * + * \parDescription + *
Cancel software request for selected event
\n + * + * Cancel the Event trigger request performed via software.
+ * + * \parRelated APIs:
+ * XMC_HRPWM_CSG_EnableEvent()
+ * XMC_HRPWM_CSG_GetEventStatus()
+ * XMC_HRPWM_CSG_SetSRNode()
+ * XMC_HRPWM_CSG_SetEventSW()
+ * + */ +__STATIC_INLINE void XMC_HRPWM_CSG_ClrEventSW(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) +{ + XMC_ASSERT("XMC_HRPWM_CSG_ClrEventSW:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + csg->SWC = event; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* #if defined(HRPWM0) */ + +#ifdef __cplusplus +} +#endif + +#endif /* HRPWM_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_hrpwm_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_hrpwm_map.h new file mode 100644 index 00000000..21a3a3b6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_hrpwm_map.h @@ -0,0 +1,176 @@ + +/** + * @file xmc_hrpwm_map.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-06-20: + * - Updated copyright and change history section. + * + * @endcond + * + */ + +/** + * + * @brief HRPWM mapping for XMC4 microcontroller family.
+ * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_hrpwm.h" + +#ifndef XMC_HRPWM_MAP_H +#define XMC_HRPWM_MAP_H + +#if ((UC_DEVICE == XMC4400) || (UC_DEVICE == XMC4200) || (UC_DEVICE == XMC4100)) +/* CSG0 - General input to control Blanking and Switch of the Comparator */ +#define XMC_HRPWM_CSG0_BL_P1_4 XMC_HRPWM_CSG_INPUT_SEL_IA +#define XMC_HRPWM_CSG0_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG0_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG0_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG0_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG0_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG0_BL_CCU40_ST0 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG0_BL_CCU41_ST0 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG0_BL_HRPWM_QOUT0 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG0_BL_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG0_BL_CCU40_SR0 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG0_BL_CCU41_SR0 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG0_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG0_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG0_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG0_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +/* CSG0 - General input to control start/stop/trigger for Slope Control Logic */ +#define XMC_HRPWM_CSG0_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG0_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG0_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG0_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG0_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG0_SC_CCU40_ST0 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG0_SC_CCU41_ST0 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG0_SC_HRPWM_QOUT0 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG0_SC_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG0_SC_CCU40_SR0 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG0_SC_CCU41_SR0 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG0_SC_HRPWM_C0O XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG0_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG0_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG0_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +/* CSG1 - General input to control Blanking and Switch of the Comparator */ +#define XMC_HRPWM_CSG1_BL_P2_4 XMC_HRPWM_CSG_INPUT_SEL_IA +#define XMC_HRPWM_CSG1_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG1_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG1_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG1_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG1_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG1_BL_CCU40_ST1 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG1_BL_CCU41_ST1 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG1_BL_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG1_BL_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG1_BL_CCU40_SR1 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG1_BL_CCU41_SR1 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG1_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG1_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG1_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG1_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +/* CSG1 - General input to control start/stop/trigger for Slope Control Logic */ +#define XMC_HRPWM_CSG1_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG1_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG1_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG1_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG1_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG1_SC_CCU40_ST1 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG1_SC_CCU41_ST1 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG1_SC_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG1_SC_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG1_SC_CCU40_SR1 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG1_SC_CCU41_SR1 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG1_SC_HRPWM_C1O XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG1_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG1_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG1_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +/* CSG2 - General input to control Blanking and Switch of the Comparator */ +#define XMC_HRPWM_CSG2_BL_P2_5 XMC_HRPWM_CSG_INPUT_SEL_IA +#define XMC_HRPWM_CSG2_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG2_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG2_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG2_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG2_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG2_BL_CCU40_ST2 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG2_BL_CCU41_ST2 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG2_BL_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG2_BL_HRPWM_QOUT3 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG2_BL_CCU40_SR2 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG2_BL_CCU41_SR2 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG2_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG2_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG2_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG2_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +/* CSG2 - General input to control start/stop/trigger for Slope Control Logic */ +#define XMC_HRPWM_CSG2_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB +#define XMC_HRPWM_CSG2_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC +#define XMC_HRPWM_CSG2_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID +#define XMC_HRPWM_CSG2_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE +#define XMC_HRPWM_CSG2_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF +#define XMC_HRPWM_CSG2_SC_CCU40_ST2 XMC_HRPWM_CSG_INPUT_SEL_IG +#define XMC_HRPWM_CSG2_SC_CCU41_ST2 XMC_HRPWM_CSG_INPUT_SEL_IH +#define XMC_HRPWM_CSG2_SC_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_II +#define XMC_HRPWM_CSG2_SC_HRPWM_QOUT3 XMC_HRPWM_CSG_INPUT_SEL_IJ +#define XMC_HRPWM_CSG2_SC_CCU40_SR2 XMC_HRPWM_CSG_INPUT_SEL_IK +#define XMC_HRPWM_CSG2_SC_CCU41_SR2 XMC_HRPWM_CSG_INPUT_SEL_IL +#define XMC_HRPWM_CSG2_SC_HRPWM_C2O XMC_HRPWM_CSG_INPUT_SEL_IM +#define XMC_HRPWM_CSG2_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN +#define XMC_HRPWM_CSG2_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO +#define XMC_HRPWM_CSG2_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP + +#endif + +#endif /* XMC_HRPWM_MAP_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_i2c.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_i2c.h new file mode 100644 index 00000000..78ffb946 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_i2c.h @@ -0,0 +1,782 @@ +/** + * @file xmc_i2c.h + * @date 2016-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - Description updated
+ * - Added XMC_I2C_CH_TriggerServiceRequest() and XMC_I2C_CH_SelectInterruptNodePointer()
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-08-27: + * - Added APIs for external input for BRG configuration:XMC_I2C_CH_ConfigExternalInputSignalToBRG()
+ * + * 2015-09-01: + * - Added APIs for enabling or disabling the ACK response to a 0x00 slave address: XMC_I2C_CH_EnableSlaveAcknowledgeTo00() and + * XMC_I2C_CH_DisableSlaveAcknowledgeTo00().
+ * - Modified XMC_I2C_CH_SetInputSource() API for avoiding complete DXCR register overwriting.
+ * - Modified XMC_I2C_CH_EVENT_t enum for supporting XMC_I2C_CH_EnableEvent() and XMC_I2C_CH_DisableEvent() + * for supporting multiple events configuration
+ * + * 2015-10-02: + * - Fix 10bit addressing + * + * 2015-10-07: + * - Fix register access in XMC_I2C_CH_EnableSlaveAcknowledgeTo00() and XMC_I2C_CH_DisableSlaveAcknowledgeTo00() APIs. + * - Naming of APIs modified: from XMC_I2C_CH_EnableSlaveAcknowledgeTo00() to XMC_I2C_CH_EnableAcknowledgeAddress0() + * and from XMC_I2C_CH_DisableSlaveAcknowledgeTo00() to XMC_I2C_CH_DisableAcknowledgeAddress0(). + * + * 2016-05-20: + * - Added XMC_I2C_CH_EnableDataTransmission() and XMC_I2C_CH_DisableDataTransmission() + * + * 2016-08-17: + * - Improved documentation of slave address passing + * + * @endcond + * + */ + +#ifndef XMC_I2C_H +#define XMC_I2C_H + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_usic.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup I2C + * @brief Inter Integrated Circuit(IIC) driver for the XMC microcontroller family. + * + * USIC IIC Features:
+ * * Two-wire interface, with one line for shift clock transfer and synchronization (shift clock SCL), the other one for the data transfer (shift data SDA)
+ * * Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
+ * * Support of 7-bit addressing, as well as 10-bit addressing
+ * * Master mode operation, where the IIC controls the bus transactions and provides the clock signal.
+ * * Slave mode operation, where an external master controls the bus transactions and provides the clock signal.
+ * * Multi-master mode operation, where several masters can be connected to the bus and bus arbitration can take place, i.e. the IIC module can be master or slave.
+ The master/slave operation of an IIC bus participant can change from frame to frame.
+ * * Efficient frame handling (low software effort), also allowing DMA transfers
+ * * Powerful interrupt handling due to multitude of indication flags
+ * @{ + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#if defined(USIC0) +#define XMC_I2C0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */ +#define XMC_I2C0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */ +#endif + +#if defined(USIC1) +#define XMC_I2C1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */ +#define XMC_I2C1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */ +#endif + +#if defined(USIC2) +#define XMC_I2C2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */ +#define XMC_I2C2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */ +#endif + +#define XMC_I2C_10BIT_ADDR_GROUP (0x7800U) /**< Value to verify the address is 10-bit or not */ + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * @brief I2C Status + */ +typedef enum XMC_I2C_CH_STATUS +{ + XMC_I2C_CH_STATUS_OK, /**< Status OK */ + XMC_I2C_CH_STATUS_ERROR, /**< Status ERROR */ + XMC_I2C_CH_STATUS_BUSY /**< Status BUSY */ +} XMC_I2C_CH_STATUS_t; + +/** + * @brief I2C status + */ +typedef enum XMC_I2C_CH_STATUS_FLAG +{ + XMC_I2C_CH_STATUS_FLAG_SLAVE_SELECT = USIC_CH_PSR_IICMode_SLSEL_Msk, /**< Slave select status */ + XMC_I2C_CH_STATUS_FLAG_WRONG_TDF_CODE_FOUND = USIC_CH_PSR_IICMode_WTDF_Msk, /**< Wrong TDF status */ + XMC_I2C_CH_STATUS_FLAG_START_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_SCR_Msk, /**< Start condition received status */ + XMC_I2C_CH_STATUS_FLAG_REPEATED_START_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_RSCR_Msk, /**< Repeated start condition received status */ + XMC_I2C_CH_STATUS_FLAG_STOP_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_PCR_Msk, /**< Stop condition received status */ + XMC_I2C_CH_STATUS_FLAG_NACK_RECEIVED = USIC_CH_PSR_IICMode_NACK_Msk, /**< NACK received status */ + XMC_I2C_CH_STATUS_FLAG_ARBITRATION_LOST = USIC_CH_PSR_IICMode_ARL_Msk, /**< Arbitration lost status */ + XMC_I2C_CH_STATUS_FLAG_SLAVE_READ_REQUESTED = USIC_CH_PSR_IICMode_SRR_Msk, /**< Slave read requested status */ + XMC_I2C_CH_STATUS_FLAG_ERROR = USIC_CH_PSR_IICMode_ERR_Msk, /**< Error status */ + XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED = USIC_CH_PSR_IICMode_ACK_Msk, /**< ACK received status */ + XMC_I2C_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_IICMode_RSIF_Msk, /**< Receive start indication status */ + XMC_I2C_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_IICMode_DLIF_Msk, /**< Data lost indication status */ + XMC_I2C_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_IICMode_TSIF_Msk, /**< Transmit shift indication status */ + XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_IICMode_TBIF_Msk, /**< Transmit buffer indication status */ + XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_IICMode_RIF_Msk, /**< Receive indication status */ + XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_IICMode_AIF_Msk, /**< Alternate receive indication status */ + XMC_I2C_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_IICMode_BRGIF_Msk /**< Baud rate generator indication status */ +} XMC_I2C_CH_STATUS_FLAG_t; + +/** + * @brief I2C receiver status. The received data byte is available at the bit + * positions RBUF[7:0], whereas the additional information is monitored at the bit positions +* RBUF[12:8]. + */ +typedef enum XMC_I2C_CH_RECEIVER_STATUS_FLAG +{ + XMC_I2C_CH_RECEIVER_STATUS_FLAG_ACK = 0x1U, /**< Bit 8: Value of Received Acknowledgement bit */ + XMC_I2C_CH_RECEIVER_STATUS_FLAG_FIN = 0x2U, /**< Bit 9: A 1 at this bit position indicates that after a (repeated) start condition + followed by the address reception the first data byte of a new frame has + been received. A 0 at this bit position indicates further data bytes */ + XMC_I2C_CH_RECEIVER_STATUS_FLAG_MODE = 0x4U, /**< Bit 10: A 0 at this bit position indicates that the data byte has been received + when the device has been in slave mode, whereas a 1 indicates a reception in master mode */ + XMC_I2C_CH_RECEIVER_STATUS_FLAG_ERR = 0x8U, /**< Bit 11: A 1 at this bit position indicates an incomplete/erroneous + data byte in the receive buffer */ + XMC_I2C_CH_RECEIVER_STATUS_FLAG_ADR = 0x10 /**< Bit 12: A 0 at this bit position indicates that the programmed address + has been received. A 1 indicates a general call address. */ +} XMC_I2C_CH_RECEIVER_STATUS_FLAG_t; + +/** + * @brief I2C commands + */ +typedef enum XMC_I2C_CH_CMD +{ + XMC_I2C_CH_CMD_WRITE, /**< I2C Command Write */ + XMC_I2C_CH_CMD_READ /**< I2C Command Read */ +} XMC_I2C_CH_CMD_t; + +/** + * @brief I2C events + */ +typedef enum XMC_I2C_CH_EVENT +{ + XMC_I2C_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */ + XMC_I2C_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */ + XMC_I2C_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */ + XMC_I2C_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */ + XMC_I2C_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */ + XMC_I2C_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */ + XMC_I2C_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */ + + XMC_I2C_CH_EVENT_START_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_SCRIEN_Msk, /**< Start condition received event */ + XMC_I2C_CH_EVENT_REPEATED_START_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_RSCRIEN_Msk, /**< Repeated start condition received event */ + XMC_I2C_CH_EVENT_STOP_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_PCRIEN_Msk, /**< Stop condition received event */ + XMC_I2C_CH_EVENT_NACK = USIC_CH_PCR_IICMode_NACKIEN_Msk, /**< NACK received event */ + XMC_I2C_CH_EVENT_ARBITRATION_LOST = USIC_CH_PCR_IICMode_ARLIEN_Msk, /**< Arbitration lost event */ + XMC_I2C_CH_EVENT_SLAVE_READ_REQUEST = USIC_CH_PCR_IICMode_SRRIEN_Msk, /**< Slave read request event */ + XMC_I2C_CH_EVENT_ERROR = USIC_CH_PCR_IICMode_ERRIEN_Msk, /**< Error condition event */ + XMC_I2C_CH_EVENT_ACK = USIC_CH_PCR_IICMode_ACKIEN_Msk /**< ACK received event */ +} XMC_I2C_CH_EVENT_t; + +/** + * @brief I2C input stage selection + */ +typedef enum XMC_I2C_CH_INPUT +{ + XMC_I2C_CH_INPUT_SDA = 0U, /**< selection of sda input stage */ +#if UC_FAMILY == XMC1 + XMC_I2C_CH_INPUT_SDA1 = 3U, + XMC_I2C_CH_INPUT_SDA2 = 5U, +#endif + XMC_I2C_CH_INPUT_SCL = 1U, /**< selection of scl input stage */ +#if UC_FAMILY == XMC1 + XMC_I2C_CH_INPUT_SCL1 = 4U +#endif +} XMC_I2C_CH_INPUT_t; + +/** + * I2C channel interrupt node pointers + */ +typedef enum XMC_I2C_CH_INTERRUPT_NODE_POINTER +{ + XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */ + XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */ + XMC_I2C_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */ + XMC_I2C_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */ + XMC_I2C_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */ +} XMC_I2C_CH_INTERRUPT_NODE_POINTER_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ +/** + * @brief I2C_CH configuration structure + */ +typedef struct XMC_I2C_CH_CONFIG +{ + uint32_t baudrate; /**< baud rate configuration upto max of 400KHz */ + uint16_t address; /**< slave address + A 7-bit address needs to be left shifted it by 1. + A 10-bit address needs to be ORed with XMC_I2C_10BIT_ADDR_GROUP. */ +} XMC_I2C_CH_CONFIG_t; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param config Constant pointer to I2C channel config structure of type @ref XMC_I2C_CH_CONFIG_t + * + * @return None
+ * + * \parDescription:
+ * Initializes the I2C \a channel.
+ * + * \par + * Configures the data format in SCTR register. Sets the slave address, baud rate. Enables transmit data valid, clears status flags + * and disables parity generation.
+ * + * \parRelated APIs:
+ * XMC_USIC_CH_Enable()\n\n + */ + +void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param rate baud rate of I2C channel + * + * @return None
+ * + * \parDescription:
+ * Sets the rate of I2C \a channel. + * + * \parNote:
+ * Standard over sampling is considered if rate <= 100KHz and fast over sampling is considered if rate > 100KHz.
+ * + * \parRelated APIs:
+ * XMC_USIC_CH_SetBaudrate()\n\n + */ +XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * + * @return None
+ * + * \parDescription:
+ * Starts the I2C \a channel. + * + * \par + * Sets the USIC input operation mode to I2C mode using CCR register. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetMode()\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_Start(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_I2C); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * + * @return @ref XMC_I2C_CH_STATUS_t
+ * + * \parDescription:
+ * Stops the I2C \a channel.
+ * + * \par + * Sets the USIC input operation to IDLE mode using CCR register. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetMode()\n\n + */ +XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param service_request Service request number in the range of 0-5 + * @return None
+ * + * \parDescription:
+ * Sets the interrupt node for protocol interrupt.
+ * + * \par + * To generate interrupt for an event, node pointer should be configured with service request number(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * + * \parNote:
+ * NVIC node should be separately enabled to generate the interrupt. After setting the node pointer, desired event must be enabled. + * + * \parRelated APIs:
+ * XMC_I2C_CH_EnableEvent(), NVIC_SetPriority(), NVIC_EnableIRQ(), XMC_I2C_CH_SetInputSource()
+ */ +__STATIC_INLINE void XMC_I2C_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const uint8_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, service_request); +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection + * @param interrupt_node Interrupt node pointer to be configured. \n + * \b Range: @ref XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, + * @ref XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc. + * @param service_request Service request number.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for USIC channel events. \n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_I2C_CH_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_I2C_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, + (uint32_t)service_request); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection + * @param service_request_line service request number of the event to be triggered. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Trigger a I2C interrupt service request.\n\n + * When the I2C service request is triggered, the NVIC interrupt associated with it will be + * generated if enabled. + * + * \parRelated APIs:
+ * XMC_I2C_CH_SelectInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line) +{ + XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param input I2C channel input stage of type @ref XMC_I2C_CH_INPUT_t + * @param source Input source select for the input stage(0->DX0A, 1->DX1A, .. 7->DX7G) + * @return None
+ * + * \parDescription:
+ * Sets the input source for I2C \a channel.
+ * Defines the input stage for the corresponding input line. + * + * @note After configuring the input source for corresponding channel, interrupt node pointer is set. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetInptSource(), XMC_USIC_CH_SetInterruptNodePointer() + * + */ +__STATIC_INLINE void XMC_I2C_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_INPUT_t input, const uint8_t source) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_INSW_Msk)) | USIC_CH_DX0CR_DSEN_Msk; + XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param address I2C slave address + * @return None
+ * + * \parDescription:
+ * Sets the I2C \a channel slave address.
+ * + * \par + * Address is set in PCR_IICMode register by checking if it is in 10-bit address group or 7-bit address group. + * (If first five bits of address are assigned with 0xF0, then address mode is 10-bit mode otherwise it is 7-bit mode)\n + * @note A 7-bit address should include an additional bit at the LSB for read/write indication. For example, address 0x05 should + * be provided as 0x0a. A 10-bit address should be provided with the identifier 0b11110xx at the most significant bits. For example, + * address 0x305 should be provided as 0x7b05(bitwise OR with 0x7800). + * + * \parRelated APIs:
+ * XMC_I2C_CH_GetSlaveAddress()\n\n + */ +void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t address); + +/** + * @param channel Constant pointer to USIC channel handler of type @ref XMC_USIC_CH_t + * @return uint16_t Slave address
+ * + * \parDescription:
+ * Gets the I2C \a channel slave address.
+ * + * \par + * Returns the address using PCR_IICMode register by checking if it is in 10-bit address group or 7-bit address group.
+ * (If first five bits of address are assigned with 0xF0, then address mode is considered as 10-bit mode otherwise it is 7-bit mode)\n + * @note A 7-bit address will include an additional bit at the LSB. For example, address 0x05 will be returned as 0x0a. + * 10-bit address will not include the 10-bit address identifier 0b11110xx at the most signifcant bits. + * + * \parRelated APIs:
+ * XMC_I2C_CH_SetSlaveAddress()\n\n + */ +uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param addr I2C master address + * @param command read/write command + * @return None
+ * + * \parDescription:
+ * Starts the I2C master \a channel.
+ * + * \par + * Sends the Start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.\n + * @note Address(addr) should reserve an additional bit at the LSB for read/write indication. For example, address 0x05 should + * be provided as 0x0a. If the address is 10-bit, only most significant bits with the 10-bit identifier should be sent using this function. + * For example, if the 10-bit address is 0x305, the address should be provided as 0xf6(prepend with 0b11110, upper two bits of address 0b11, + * followed by 1-bit field for read/write). + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n + */ +void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param addr I2C master address + * @param command read/write command + * @return None
+ * + * \parDescription:
+ * Sends the repeated start condition from I2C master \a channel.
+ * + * \par + * Sends the repeated start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.\n + * @note Address(addr) should reserve an additional bit at the LSB for read/write indication. For example, address 0x05 should + * be provided as 0x0a. If the address is 10-bit, only most significant bits with the 10-bit identifier should be sent using this function. + * For example, if the 10-bit address is 0x305, the address should be provided as 0xf6(prepend with 0b11110, upper two bits of address 0b11, + * followed by 1-bit field for read/write). + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n + */ +void XMC_I2C_CH_MasterRepeatedStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return None
+ * + * \parDescription:
+ * Stops the I2C master \a channel.
+ * + * \par + * Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Stop command. + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n + */ +void XMC_I2C_CH_MasterStop(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param data data to transmit from I2C \a channel + * @return None
+ * + * \parDescription:
+ * Transmit the data from the I2C master \a channel.
+ * + * \par + * Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Send command. + * + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus()\n\n + */ +void XMC_I2C_CH_MasterTransmit(XMC_USIC_CH_t *const channel, const uint8_t data); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param data data to transmit from I2C \a channel + * @return None
+ * + * \parDescription:
+ * Transmit the data from the I2C slave \a channel.
+ * + * \par + * Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Slave Send command. + * + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus(),XMC_I2C_CH_ClearStatusFlag()\n\n + */ +void XMC_I2C_CH_SlaveTransmit(XMC_USIC_CH_t *const channel, const uint8_t data); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return None
+ * + * \parDescription:
+ * Sends the Ack request from I2C master \a channel.
+ * + * \par +* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Receive Ack command. + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit()\n\n + */ +void XMC_I2C_CH_MasterReceiveAck(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return None
+ * + * \parDescription:
+ * Sends the Nack request from I2C master \a channel.
+ * + * \par + * Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Receive Nack command. + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit()\n\n + */ +void XMC_I2C_CH_MasterReceiveNack(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return uint8_t OUTR/RBUF register data
+ * + * \parDescription:
+ * Reads the data from I2C \a channel.
+ * + * \par + * Data is read by using OUTR/RBUF register based on FIFO/non-FIFO modes. + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit()\n\n + */ +uint8_t XMC_I2C_CH_GetReceivedData(const XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return uint8_t Receiver status flag
+ * + * \parDescription:
+ * Gets the receiver status of I2C \a channel using RBUF register of bits 8-12 which gives information about receiver status. + * + * \parRelated APIs:
+ * XMC_I2C_CH_MasterTransmit()\n\n + */ +__STATIC_INLINE uint8_t XMC_I2C_CH_GetReceiverStatusFlag(XMC_USIC_CH_t *const channel) +{ + return((uint8_t)((channel->RBUF) >> 8U)); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param event ORed values of @ref XMC_I2C_CH_EVENT_t enum + * @return None
+ * + * \parDescription:
+ * Enables the input parameter @ref XMC_I2C_CH_EVENT_t event using PCR_IICMode register. + * + * \parRelated APIs:
+ * XMC_I2C_CH_DisableEvent()\n\n + */ +void XMC_I2C_CH_EnableEvent(XMC_USIC_CH_t *const channel, uint32_t event); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param event ORed values of @ref XMC_I2C_CH_EVENT_t enum + * @return None
+ * + * \parDescription:
+ * Disables the input parameter @ref XMC_I2C_CH_EVENT_t event using PCR_IICMode register. + * + * \parRelated APIs:
+ * XMC_I2C_CH_EnableEvent()\n\n + */ +void XMC_I2C_CH_DisableEvent(XMC_USIC_CH_t *const channel, uint32_t event); + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return uint32_t Status byte
+ * + * \parDescription:
+ * Retrieves the status byte of I2C \a channel using PSR_IICMode register.\n + * + * \parRelated APIs:
+ * XMC_I2C_CH_ClearStatusFlag()\n\n + */ +__STATIC_INLINE uint32_t XMC_I2C_CH_GetStatusFlag(XMC_USIC_CH_t *const channel) +{ + return (channel->PSR_IICMode); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param flag Status flag + * @return None
+ * + * \parDescription:
+ * Clears the status flag of I2C \a channel by setting the input parameter \a flag in PSCR register. + * + * \parRelated APIs:
+ * XMC_I2C_CH_GetStatusFlag()\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, uint32_t flag) +{ + channel->PSCR |= flag; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection + * @param pdiv Desired divider for the external frequency input. \b Range: minimum value = 1, maximum value = 1024 \n + * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n + * This can be related to the number of samples for each logic state of the data signal. \n + * \b Range: 1 to 32. Value should be chosen based on the protocol used. + * @param combination_mode USIC channel input combination mode \n + * + * @return None + * + * \parDescription
+ * Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and + * the combination mode of the USIC channel. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, + const uint16_t pdiv, + const uint32_t oversampling, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) +{ + XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel,pdiv,oversampling,combination_mode); +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return None + * + * \parDescription:
+ * Retrieves the status byte of I2C \a channel using PSR_IICMode register.\n + * + * \parRelated APIs:
+ * XMC_I2C_CH_DisableAcknowledgeAddress0()\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_EnableAcknowledgeAddress0(XMC_USIC_CH_t *const channel) +{ + channel->PCR_IICMode |= USIC_CH_PCR_IICMode_ACK00_Msk; +} + +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @return None + * + * \parDescription:
+ * This bit defines that slave device should not be sensitive to the slave address 00H.\n + * + * \parRelated APIs:
+ * XMC_I2C_CH_EnableAcknowledgeAddress0()\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_DisableAcknowledgeAddress0(XMC_USIC_CH_t *const channel) +{ + channel->PCR_IICMode &= ~USIC_CH_PCR_IICMode_ACK00_Msk; +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection + * @return None + * + * \parDescription
+ * Enable data transmission.\n\n + * Use this function in combination with XMC_I2C_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode() + * + * \parRelated APIs:
+ * XMC_I2C_CH_DisableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection + * @return None + * + * \parDescription
+ * Disable data transmission.\n\n + * Use this function in combination with XMC_I2C_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * + * \parRelated APIs:
+ * XMC_I2C_CH_EnableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_i2s.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_i2s.h new file mode 100644 index 00000000..60808167 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_i2s.h @@ -0,0 +1,837 @@ +/** + * @file xmc_i2s.h + * @date 2016-06-30 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-08-21: + * - Initial
+ * + * 2015-08-24: + * - Added APIs for enabling/disabling delay compensation XMC_I2S_CH_DisableDelayCompensation() and + * XMC_I2S_CH_EnableDelayCompensation()
+ * + * 2015-09-01: + * - Modified XMC_I2S_CH_SetInputSource() for avoiding complete DXCR register overwriting.
+ * - Modified XMC_I2S_CH_EVENT_t enum for supporting XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent()
+ * for supporting multiple events configuration
+ * + * 2015-09-14: + * - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length
+ * + * 2016-05-20: + * - Added XMC_I2S_CH_EnableDataTransmission() and XMC_I2S_CH_DisableDataTransmission() + * + * 2016-06-30: + * - Documentation updates. + * + * @endcond + * + */ + +#ifndef XMC_I2S_H_ +#define XMC_I2S_H_ + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ +#include "xmc_usic.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup I2S + * @brief (IIS) driver for the XMC microcontroller family. + * + * USIC IIS Features:
+ * @{ + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#if defined(USIC0) +#define XMC_I2S0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */ +#define XMC_I2S0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */ +#endif + +#if defined(USIC1) +#define XMC_I2S1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */ +#define XMC_I2S1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */ +#endif + +#if defined(USIC2) +#define XMC_I2S2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */ +#define XMC_I2S2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */ +#endif +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * @brief I2S Status + */ +typedef enum XMC_I2S_CH_STATUS +{ + XMC_I2S_CH_STATUS_OK, /**< Status OK */ + XMC_I2S_CH_STATUS_ERROR, /**< Status ERROR */ + XMC_I2S_CH_STATUS_BUSY /**< Status BUSY */ +} XMC_I2S_CH_STATUS_t; + +/** + * @brief I2S status flag + */ +typedef enum XMC_I2S_CH_STATUS_FLAG +{ + XMC_I2S_CH_STATUS_FLAG_WORD_ADDRESS = USIC_CH_PSR_IISMode_WA_Msk, /**< Word Address status */ + XMC_I2S_CH_STATUS_FLAG_DX2S = USIC_CH_PSR_IISMode_DX2S_Msk, /**< Status of WA input(DX2) signal*/ + XMC_I2S_CH_STATUS_FLAG_DX2T_EVENT_DETECTED = USIC_CH_PSR_IISMode_DX2TEV_Msk, /**< Status for WA input signal transition */ + XMC_I2S_CH_STATUS_FLAG_WA_FALLING_EDGE_EVENT = USIC_CH_PSR_IISMode_WAFE_Msk, /**< Falling edge of the WA output + signal has been generated */ + XMC_I2S_CH_STATUS_FLAG_WA_RISING_EDGE_EVENT = USIC_CH_PSR_IISMode_WARE_Msk, /**< Rising edge of the WA output + signal has been generated */ + XMC_I2S_CH_STATUS_FLAG_WA_GENERATION_END = USIC_CH_PSR_IISMode_END_Msk, /**< The WA generation has ended */ + XMC_I2S_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_IISMode_RSIF_Msk, /**< Receive start indication status */ + XMC_I2S_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_IISMode_DLIF_Msk, /**< Data lost indication status */ + XMC_I2S_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_IISMode_TSIF_Msk, /**< Transmit shift indication status */ + XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_IISMode_TBIF_Msk, /**< Transmit buffer indication status */ + XMC_I2S_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_IISMode_RIF_Msk, /**< Receive indication status */ + XMC_I2S_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_IISMode_AIF_Msk, /**< Alternate receive indication status */ + XMC_I2S_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_IISMode_BRGIF_Msk /**< Baud rate generator indication status */ +} XMC_I2S_CH_STATUS_FLAG_t; + +/** + * @brief I2S Baudrate Generator shift clock output +*/ +typedef enum XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT +{ + XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK, /**< Baudrate Generator shift clock output: SCLK*/ + XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 /**< Clock obtained as input from master: DX1*/ +} XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t; + +/** + * @brief I2S channel interrupt node pointers + */ +typedef enum XMC_I2S_CH_INTERRUPT_NODE_POINTER +{ + XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */ + XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */ + XMC_I2S_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */ + XMC_I2S_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */ + XMC_I2S_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */ +} XMC_I2S_CH_INTERRUPT_NODE_POINTER_t; + +/** + * @brief I2S events + */ +typedef enum XMC_I2S_CH_EVENT +{ + XMC_I2S_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */ + XMC_I2S_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */ + XMC_I2S_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */ + XMC_I2S_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */ + XMC_I2S_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */ + XMC_I2S_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */ + XMC_I2S_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */ + + XMC_I2S_CH_EVENT_WA_FALLING_EDGE = USIC_CH_PCR_IISMode_WAFEIEN_Msk << 2U, /**< WA falling edge event */ + XMC_I2S_CH_EVENT_WA_RISING_EDGE = USIC_CH_PCR_IISMode_WAREIEN_Msk << 2U, /**< WA rising edge event */ + XMC_I2S_CH_EVENT_WA_GENERATION_END = USIC_CH_PCR_IISMode_ENDIEN_Msk << 2U, /**< END event */ + XMC_I2S_CH_EVENT_DX2TIEN_ACTIVATED = USIC_CH_PCR_IISMode_DX2TIEN_Msk << 2U /**< WA input signal transition event*/ +} XMC_I2S_CH_EVENT_t; + +/** + * @brief Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal. + */ +typedef enum XMC_I2S_CH_WA_POLARITY +{ + XMC_I2S_CH_WA_POLARITY_DIRECT = 0x0UL, /**< The SELO outputs have the same polarity + as the WA signal (active high) */ + XMC_I2S_CH_WA_POLARITY_INVERTED = 0x1UL << USIC_CH_PCR_IISMode_SELINV_Pos /**< The SELO outputs have the inverted + polarity to the WA signal (active low)*/ +} XMC_I2S_CH_WA_POLARITY_t; + +/** + * @brief Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal. + */ +typedef enum XMC_I2S_CH_CHANNEL +{ + XMC_I2S_CH_CHANNEL_1_LEFT = 0U, /**< Channel 1 (left) */ + XMC_I2S_CH_CHANNEL_2_RIGHT = 1U /**< Channel 2 (right) */ +} XMC_I2S_CH_CHANNEL_t; + +/** + * @brief I2S input stage selection + */ +typedef enum XMC_I2S_CH_INPUT +{ + XMC_I2S_CH_INPUT_DIN0 = 0UL, /**< Data input stage 0 */ + XMC_I2S_CH_INPUT_SLAVE_SCLKIN = 1UL, /**< Clock input stage */ + XMC_I2S_CH_INPUT_SLAVE_WA = 2UL, /**< WA input stage */ +#if UC_FAMILY == XMC1 + XMC_I2S_CH_INPUT_DIN1 = 3UL, /**< Data input stage 1 */ + XMC_I2S_CH_INPUT_DIN2 = 4UL, /**< Data input stage 2 */ + XMC_I2S_CH_INPUT_DIN3 = 5UL /**< Data input stage 3 */ +#endif +} XMC_I2S_CH_INPUT_t; + +/** + * @brief Defines the I2S bus mode + */ +typedef enum XMC_I2S_CH_BUS_MODE +{ + XMC_I2S_CH_BUS_MODE_MASTER, /**< I2S Master */ + XMC_I2S_CH_BUS_MODE_SLAVE /**< I2S Slave */ +} XMC_I2S_CH_BUS_MODE_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ +/** + * @brief I2S_CH configuration structure + */ +typedef struct XMC_I2S_CH_CONFIG +{ + uint32_t baudrate; /**< Module baud rate for communication */ + uint8_t data_bits; /**< Data word length. A data frame can consists of several data words. \n + Value configured as USIC channel word length. \n + \b Range: minimum= 1, maximum= 16*/ + uint8_t frame_length; /**< Number of data bits transferred after a change of signal WA (data frame). \n + Configured as USIC channel frame length. \n + \b Range: minimum= 1, maximum= 63*/ + uint8_t data_delayed_sclk_periods; /**< Data delay defined in sclk periods */ + XMC_I2S_CH_WA_POLARITY_t wa_inversion; /**< Enable inversion of Slave select signal relative to the internal WA */ + XMC_I2S_CH_BUS_MODE_t bus_mode; /**< Bus mode MASTER/SLAVE */ +} XMC_I2S_CH_CONFIG_t; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0, XMC_I2S1_CH1,XMC_I2S2_CH0, XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @param config Constant pointer to I2S configuration structure of type @ref XMC_I2S_CH_CONFIG_t. + * @return XMC_I2S_CH_STATUS_t Status of initializing the USIC channel for I2S protocol.\n + * \b Range: @ref XMC_I2S_CH_STATUS_OK if initialization is successful.\n + * @ref XMC_I2S_CH_STATUS_ERROR if configuration of baudrate failed. + * + * \parDescription
+ * Initializes the USIC channel for I2S protocol.\n\n + * During the initialization, USIC channel is enabled and baudrate is configured. + * After each change of the WA signal, a complete data frame is intended to be transferred (frame length <= system word length). + * The number of data bits transferred after a change of signal WA is defined by config->frame_length. + * A data frame can consist of several data words with a data word length defined by config->data_bits. + * The changes of signal WA define the system word length as the number of SCLK cycles between two changes of WA. + * The system word length is set by default to the frame length defined by config->frame_length. + * + * XMC_I2S_CH_Start() should be invoked after the initialization to enable the channel. + * + * \parRelated APIs:
+ * XMC_I2S_CH_Start(), XMC_I2S_CH_Stop(), XMC_I2S_CH_Transmit(), XMC_I2S_CH_SetSystemWordLength()\n\n\n + */ +void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the selected USIC channel to operate in I2S mode, by setting CCR.MODE bits.\n\n + * It should be executed after XMC_I2S_CH_Init() during initialization. By invoking XMC_I2S_CH_Stop(), the MODE is set + * to IDLE state. Call XMC_I2S_CH_Start() to set the I2S mode again, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_I2S_CH_Init(), XMC_I2S_CH_Stop() + */ +__STATIC_INLINE void XMC_I2S_CH_Start(XMC_USIC_CH_t *const channel) +{ + /* USIC channel in I2S mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_I2S); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for stopping is processed. \n + * XMC_I2S_CH_STATUS_OK- If the USIC channel is successfully put to IDLE mode. \n + * XMC_I2S_CH_STATUS_BUSY- If the USIC channel is busy transmitting data. + * + * \parDescription:
+ * Set the selected I2S channel to IDLE mode, by clearing CCR.MODE bits.\n\n + * After calling XMC_I2S_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_I2S_CH_Start() has to be + * invoked to start the communication again. + * + * \parRelated APIs:
+ * XMC_I2S_CH_Start() + */ +XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param rate Bus speed in bits per second + * + * @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for setting baudrate is processed. \n + * XMC_I2S_CH_STATUS_OK- If the baudrate is successfully changed. \n + * XMC_I2S_CH_STATUS_ERROR- If the new baudrate value is out of range. + * + * \parDescription:
+ * Sets the bus speed in bits per second + * + * \parRelated APIs:
+ * XMC_I2S_CH_Init(), XMC_I2S_CH_Stop() + */ +XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param sclk_cycles_system_word_length system word length in terms of sclk clock cycles. + * + * @return None + * + * \parDescription:
+ * Configures the system word length by setting BRG.DCTQ bit field.\n\n + * This value has to be always higher than 1U and lower than the data with (SCTR.FLE) + * + */ +void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param data Data to be transmitted + * @param channel_number Communication output channel of the I2S, based on this channel selection TCI(Transmit control information)is updated.\n + * Refer @ref XMC_I2S_CH_CHANNEL_t for valid values. + * + * @return None + * + * \parDescription:
+ * Puts the data into FIFO, if FIFO mode is enabled or else into standard buffer, by setting the proper mode.\n\n + * TCI(Transmit Control Information) allows dynamic control of output channel during data transfers. To support this auto + * update, TCSR.WAMD(Automatic WA mode) will be enabled during the initialization using XMC_I2S_CH_Init() for all modes. + * + * + * \parRelated APIs:
+ * XMC_I2S_CH_Receive() + */ +void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNEL_t channel_number); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param channel_number Communication output channel of the I2S, based on this mode TCI(Transmit control information)is updated.\n + * Refer @ref XMC_I2S_CH_CHANNEL_t for valid values. + * + * @return None + * + * \parDescription:
+ * Transmits a dummy data(FFFFH) to provide clock for slave and receives the data from the slave.\n\n + * XMC_I2S_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data + * XMC_I2S_CH_GetReceivedData() can be invoked to read the data from the buffers. + * + * \parRelated APIs:
+ * XMC_I2S_CH_GetReceivedData() + */ +__STATIC_INLINE void XMC_I2S_CH_Receive(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CHANNEL_t channel_number) +{ + /* Transmit dummy data */ + XMC_I2S_CH_Transmit(channel, (uint16_t)0xffffU , channel_number); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return uint16_t Data read from the receive buffer. + * + * \parDescription:
+ * Reads data from the receive buffer based on the FIFO selection.\n\n + * Invocation of XMC_I2S_CH_Receive() receives the data and place it into receive buffer. After receiving the data + * XMC_I2S_CH_GetReceivedData() can be used to read the data from the buffer. + * + * \parRelated APIs:
+ * XMC_I2S_CH_Receive() + */ +uint16_t XMC_I2S_CH_GetReceivedData(XMC_USIC_CH_t *const channel); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the order of data transfer from LSB to MSB, by clearing SCTR.SDIR bit.\n\n + * This is typically based on the slave settings. Invoke XMC_I2S_CH_SetBitOrderLsbFirst() to set direction as needed in + * the program. + * + * \parRelated APIs:
+ * XMC_I2S_CH_SetBitOrderMsbFirst() + */ +__STATIC_INLINE void XMC_I2S_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t *const channel) +{ + channel->SCTR &= (uint32_t)~USIC_CH_SCTR_SDIR_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.\n\n + * This is typically based on the slave settings. This is not set during XMC_I2S_CH_Init(). + * Invoke XMC_I2S_CH_SetBitOrderMsbFirst() to set direction as needed in the program. + * + * \parRelated APIs:
+ * XMC_I2S_CH_SetBitOrderLsbFirst() + */ +__STATIC_INLINE void XMC_I2S_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t *const channel) +{ + channel->SCTR |= (uint32_t)USIC_CH_SCTR_SDIR_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param event Protocol events which have to be enabled. + * Refer @ XMC_I2S_CH_EVENT_t for valid values. OR combinations of these enum items can be used + * as input. + * + * @return None + * + * \parDescription:
+ * Enables the I2S protocol specific events, by configuring PCR register.\n\n + * Events can be enabled as needed using XMC_I2S_CH_EnableEvent(). + * XMC_I2S_CH_DisableEvent() can be used to disable the events. + * + * \parRelated APIs:
+ * XMC_I2S_CH_DisableEvent() + */ +void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param event Protocol events which have to be disabled. + * Refer @ XMC_I2S_CH_EVENT_t for valid values. OR combinations of these enum item can be used + * as input. + * + * @return None + * + * \parDescription:
+ * Disables the I2S protocol specific events, by configuring PCR register.\n\n + * After disabling the events, XMC_I2S_CH_EnableEvent() has to be invoked to re-enable the events. + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableEvent() + */ +void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return uint32_t Status of I2S protocol events. + * + * \parDescription:
+ * Returns the status of the events, by reading PSR register.\n\n + * This indicates the status of the all the events, for I2S communication. + * + * \parRelated APIs:
+ * XMC_I2S_CH_ClearStatusFlag() + */ +__STATIC_INLINE uint32_t XMC_I2S_CH_GetStatusFlag(XMC_USIC_CH_t *const channel) +{ + return channel->PSR_IISMode; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param flag Protocol event status to be cleared for detection of next occurence. + * Refer @ XMC_I2S_CH_STATUS_FLAG_t for valid values. OR combinations of these enum item can be used + * as input. + * @return None + * + * \parDescription:
+ * Clears the events specified, by setting PSCR register.\n\n + * During communication the events occurred have to be cleared to detect their next occurence.\n + * e.g: During transmission Transmit buffer event occurs to indicating data word transfer has started. This + * event has to be cleared after transmission of each data word. Otherwise next event cannot be recognized. + * + * \parRelated APIs:
+ * XMC_I2S_CH_GetStatusFlag() + */ +__STATIC_INLINE void XMC_I2S_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag) +{ + channel->PSCR |= flag; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Enables the generation of Master clock by setting PCR.MCLK bit.\n\n + * This clock can be used as a clock reference for external devices. This is not enabled during initialization in + * XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by + * XMC_I2S_CH_DisableMasterClock(). + * + * \parRelated APIs:
+ * XMC_I2S_CH_DisableMasterClock() + */ +__STATIC_INLINE void XMC_I2S_CH_EnableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_IISMode |= (uint32_t)USIC_CH_PCR_IISMode_MCLK_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Disables the generation of Master clock by clearing PCR.MCLK bit.\n\n + * This clock can be enabled by invoking XMC_I2S_CH_EnableMasterClock() as needed in the program. + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableMasterClock() + */ +__STATIC_INLINE void XMC_I2S_CH_DisableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_IISMode &= (uint32_t)~USIC_CH_PCR_IISMode_MCLK_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param clock_output shift clock source.\n + * Refer @ref XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t for valid inputs. + * + * @return None + * + * \parDescription:
+ * Configures the shift clock source by setting BRG.SCLKOSEL.\n\n + * In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available + * for external slave devices by SCLKOUT signal.\n + * In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.\n + */ +__STATIC_INLINE void XMC_I2S_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) +{ + XMC_USIC_CH_ConfigureShiftClockOutput(channel, (XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t)0U, + (XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param word_length Number of bits to be configured for a data word. \n + * \b Range: 1 to 16. + * + * @return None + * + * \parDescription
+ * Defines the data word length.\n\n + * Sets the number of bits to represent a data word. Frame length should be a multiple of word length. + * + * \parRelated APIs:
+ * XMC_I2S_CH_SetFrameLength() + */ +__STATIC_INLINE void XMC_I2S_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length) +{ + XMC_USIC_CH_SetWordLength(channel, word_length); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param frame_length Number of bits in a frame. \n + * \b Range: 1 to 64. + * + * @return None + * + * \parDescription
+ * Define the data frame length.\n\n + * Set the number of bits to be serially transmitted in a frame. + * The frame length should be multiples of word length. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetWordLength() + */ +__STATIC_INLINE void XMC_I2S_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length) +{ + XMC_USIC_CH_SetFrameLength(channel, frame_length); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input I2S channel input stage.\n + * Refer @ref XMC_I2S_CH_INPUT_t for valid values + * @param source Input source select for the input stage. + * Range : [0 to 7] + * + * @return None + * + * \parDescription
+ * Selects the data source for I2S input stage, by configuring DXCR.DSEL bits.\n\n + * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the + * input stages like DX0CR, DX1CR etc. This is not done during initialization. This has to be configured before starting + * the I2S communication. + */ +__STATIC_INLINE void XMC_I2S_CH_SetInputSource(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_INPUT_t input, + const uint8_t source) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_DSEN_Msk)) | USIC_CH_DX0CR_INSW_Msk; + XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param wa_inversion Polarity of the word address signal.\n + * Refer @ref XMC_I2S_CH_WA_POLARITY_t for valid values + * + * @return None + * + * \parDescription
+ * Set the polarity of the word address signal, by configuring PCR.SELINV bit.\n\n + * Normally WA signal is active low level signal. This is configured + * in XMC_I2S_CH_Init() during initialization. Invoke XMC_I2S_CH_WordAddressSignalPolarity() with desired settings as + * needed later in the program. + */ +__STATIC_INLINE void XMC_I2S_CH_WordAddressSignalPolarity(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_WA_POLARITY_t wa_inversion) +{ + /* Configuration of Protocol Control Register */ + channel->PCR_IISMode = (uint32_t)((channel->PCR_IISMode & (~USIC_CH_PCR_IISMode_SELINV_Msk)) | (uint32_t)wa_inversion); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input I2S channel input stage.\n + * Refer @ref XMC_I2S_CH_INPUT_t for valid inputs. + * + * @return None + * + * \parDescription
+ * Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y = \a input).\n\n + * This is not set in XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableInputInversion() as needed later in the program. To + * disable the inversion XMC_I2S_CH_DisableInputInversion() can be invoked. + * + * \parRelated APIs:
+ * XMC_I2S_CH_DisableInputInversion() + */ +__STATIC_INLINE void XMC_I2S_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_INPUT_t input) +{ + XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input I2S channel input stage.\n + * Refer @ref XMC_I2S_CH_INPUT_t for valid inputs. + * + * @return None + * + * \parDescription
+ * Disables the polarity inversion of input data signal, by clearing DXyCR.DPOL(where y = \a input).\n\n + * Resets the input data polarity. Invoke XMC_I2S_CH_EnableInputInversion() to apply inversion. + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableInputInversion() + */ +__STATIC_INLINE void XMC_I2S_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_INPUT_t input) +{ + XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param service_request Service request number. + Range: [0 to 5] + * + * @return None + * + * \parDescription
+ * Sets the interrupt node for I2S channel events.\n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so. This is not configured in XMC_I2S_CH_Init() during + * initialization. + * + * \parNote::
+ * 1. NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableEvent() + */ +__STATIC_INLINE void XMC_I2S_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const uint8_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, (uint32_t)service_request); +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @param interrupt_node Interrupt node pointer to be configured. \n + * \b Range: @ref XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, + * @ref XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc. + * @param service_request Service request number.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for USIC channel events. \n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_I2S_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, + (uint32_t)service_request); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @param service_request_line service request number of the event to be triggered. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Trigger a I2S interrupt service request.\n\n + * When the I2S service request is triggered, the NVIC interrupt associated with it will be + * generated if enabled. + * + * \parRelated APIs:
+ * XMC_I2S_CH_SelectInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line) +{ + XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @return None + * + * \parDescription
+ * Enables delay compensation. \n\n + * + * Delay compensation can be applied to the receive path. + * \parRelated APIs:
+ * XMC_I2S_CH_DisableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_EnableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_EnableDelayCompensation(channel); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @return None + * + * \parDescription
+ * Disables delay compensation.. \n\n + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_DisableDelayCompensation(channel); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @return None + * + * \parDescription
+ * Enable data transmission.\n\n + * Use this function in combination with XMC_I2S_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode() + * + * \parRelated APIs:
+ * XMC_I2S_CH_DisableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @return None + * + * \parDescription
+ * Disable data transmission.\n\n + * Use this function in combination with XMC_I2S_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * + * \parRelated APIs:
+ * XMC_I2S_CH_EnableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ +#endif /* XMC_I2S_H_ */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ledts.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ledts.h new file mode 100644 index 00000000..0934eda6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_ledts.h @@ -0,0 +1,1052 @@ +/** + * @file xmc_ledts.h + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * - Documentation improved
+ * - New API added: XMC_LEDTS_SetActivePADNo()
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * @endcond + * + */ + +#ifndef XMC_LEDTS_H +#define XMC_LEDTS_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +#if defined(LEDTS0) +#include "xmc_scu.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup LEDTS + * @brief LED and Touch-Sense control(LEDTS) driver for the XMC controller family. + * + * The LED and Touch-Sense (LEDTS) drives LEDs and controls touch pads used as human-machine interface (HMI) in an + * application. The LEDTS can measure the capacitance of up to 8 touch pads, can also drive up to 64 LEDs in an LED matrix. + * Touch pads and LEDs can share pins to minimize the number of pins needed for such applications, this is realized by + * the module controlling the touch pads and driving the LEDs in a time-division multiplexed manner. + * + * This device contains LEDTS kernel that has an LED driving function and a touch-sensing function. + * + * It is recommended to set up all configurations for the LEDTS in all Special Function Registers(SFR) before + * enabling and starting LED and/or touch-sense function(s). + * + * This Low Level Driver(LLD) provides APIs to configure and control LED functionality, Touch-Sense functionality and + * features common to both functionalities. + * + * LED features: + * -# Configuration structure to configure LED functionality (XMC_LEDTS_LED_CONFIG_t) and initialization funtion + * (XMC_LEDTS_InitLED()). + * -# Selection of number of LED columns, active column level and enabling LED funtionality (XMC_LEDTS_InitLED()). + * -# Setting line pattern to be displayed on LED column (XMC_LEDTS_SetLEDLinePattern()). + * -# Brightness control of LED column (XMC_LEDTS_SetColumnBrightness()). + * -# Setting number of columns to be activated (XMC_LEDTS_SetNumOfLEDColumns()). + * + * Touch-Sense features: + * -# Configuration structure to perform basic Touch-Sense functionality (XMC_LEDTS_TS_CONFIG_BASIC_t) settings and + * initialization funtion (XMC_LEDTS_InitTSBasic()). + * -# Configuration structure to perform advanced Touch-Sense functionality (XMC_LEDTS_TS_CONFIG_ADVANCED_t) settings + * and initialization function (XMC_LEDTS_InitTSAdvanced()). + * -# Setting number of touch inputs and acculumate count on touch input (XMC_LEDTS_InitTSBasic()). + * -# Enabling/disabling of common compare, Touch-Sense counter auto reset and Touch-Sense funtionality. + * (XMC_LEDTS_InitTSBasic()). + * -# Set number of mask bits for time frame validation and first touch input to be active. (XMC_LEDTS_InitTSAdvanced()). + * -# Enable/disable time frame interrupt, external pull-up on touch pin and hardware or software control of + * pad turn (XMC_LEDTS_InitTSAdvanced()). + * -# Setting size of common oscillation window for all touch-sense inputs (XMC_LEDTS_SetCommonOscillationWindow()). + * -# Setting size of oscillation window for a touch-sense input (XMC_LEDTS_SetOscillationWindow()). + * + * Common features: + * -# Global configuration structure XMC_LEDTS_GLOBAL_CONFIG_t and initialization function XMC_LEDTS_InitGlobal(). + * -# Selection of Clock source for LEDTS module (XMC_LEDTS_InitGlobal()). + * -# Kick-start and stop of LEDTS module (XMC_LEDTS_StartCounter() / XMC_LEDTS_StopCounter()). + * -# Read and clear of interrupt status flags (XMC_LEDTS_ReadInterruptFlag() / XMC_LEDTS_ClearInterruptFlag()). + * -# Reading of previous active column number (XMC_LEDTS_ReadFNCOL()). + * -# Enable/Disable Interrupts(XMC_LEDTS_EnableInterrupt() / XMC_LEDTS_DisableInterrupt()). + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#if defined(LEDTS0) +#define XMC_LEDTS0 ((XMC_LEDTS_GLOBAL_t *) LEDTS0) /**< Typedef for LEDTS kernel0*/ +#define XMC_LEDTS_CHECK_LEDTS0(PTR) (PTR == XMC_LEDTS0) +#else +#define XMC_LEDTS_CHECK_LEDTS0(PTR) 0 +#endif + +#if defined(LEDTS1) +#define XMC_LEDTS1 ((XMC_LEDTS_GLOBAL_t *) LEDTS1) /**< Typedef for LEDTS kernel1*/ +#define XMC_LEDTS_CHECK_LEDTS1(PTR) (PTR == XMC_LEDTS1) +#else +#define XMC_LEDTS_CHECK_LEDTS1(PTR) 0 +#endif + +#if defined(LEDTS2) +#define XMC_LEDTS2 ((XMC_LEDTS_GLOBAL_t *) LEDTS2) /**< Typedef for LEDTS kernel2*/ +#define XMC_LEDTS_CHECK_LEDTS2(PTR) (PTR == XMC_LEDTS2) +#else +#define XMC_LEDTS_CHECK_LEDTS2(PTR) 0 +#endif + +#define XMC_LEDTS_CHECK_KERNEL_PTR(PTR) (XMC_LEDTS_CHECK_LEDTS0(PTR) || \ + XMC_LEDTS_CHECK_LEDTS1(PTR) || \ + XMC_LEDTS_CHECK_LEDTS2(PTR)) + +/** + * Defines LEDTS module structure. This holds data and configuration registers of LEDTS modules. Use type + * XMC_LEDTS_GLOBAL_t for this data structure.\n + */ +typedef struct XMC_LEDTS_GLOBAL{ /*!< (@ 0x50020000) LEDTS Structure */ + __I uint32_t ID; /*!< (@ 0x50020000) Module Identification Register */ + __IO uint32_t GLOBCTL; /*!< (@ 0x50020004) Global Control Register */ + __IO uint32_t FNCTL; /*!< (@ 0x50020008) Function Control Register */ + __O uint32_t EVFR; /*!< (@ 0x5002000C) Event Flag Register */ + __IO uint32_t TSVAL; /*!< (@ 0x50020010) Touch-sense TS-Counter Value */ + __IO uint32_t LINE[2]; /*!< (@ 0x50020014) Line Pattern Register 0 */ + __IO uint32_t LDCMP[2]; /*!< (@ 0x5002001C) LED Compare Register 0 */ + __IO uint32_t TSCMP[2]; /*!< (@ 0x50020024) Touch-sense Compare Register 0 */ + } XMC_LEDTS_GLOBAL_t; + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +/** + * Defines typedef for LEDTS Global data structure. Use type XMC_LEDTS_t for this data structure.\n + */ +typedef XMC_LEDTS_GLOBAL_t XMC_LEDTS_t; + +#if defined(LEDTS0) +#define XMC_LEDTS0 ((XMC_LEDTS_GLOBAL_t *) LEDTS0) /**< Typedef for LEDTS kernel0*/ +#endif + +#if defined(LEDTS1) +#define XMC_LEDTS1 ((XMC_LEDTS_GLOBAL_t *) LEDTS1) /**< Typedef for LEDTS kernel1*/ +#endif + + +/** + * Defines return value of an API. Use type XMC_LEDTS_STATUS_t for this enum. + */ +typedef enum XMC_LEDTS_STATUS +{ + XMC_LEDTS_STATUS_SUCCESS = 0, /**< API fulfills request */ + XMC_LEDTS_STATUS_RUNNING = 1, /**< The kernel-counter is currently running */ + XMC_LEDTS_STATUS_ERROR = 2, /**< API cannot fulfill request */ + XMC_LEDTS_STATUS_IDLE = 3 /**< The kernel-counter is currently idle */ +} XMC_LEDTS_STATUS_t; + +/** + * Defines return value for checking interrupt flag. Use type XMC_LEDTS_FLAG_STATUS_t for this enum. + */ +typedef enum XMC_LEDTS_FLAG_STATUS +{ + XMC_LEDTS_FLAG_STATUS_NO = 0, /**< Flag not raised */ + XMC_LEDTS_FLAG_STATUS_YES = 1 /**< Flag is raised */ +} XMC_LEDTS_FLAG_STATUS_t; + +/** + * Defines Touch-Sense function enable/disable. Use type XMC_LEDTS_TS_FUNC_t for this enum. + */ +typedef enum XMC_LEDTS_TS_FUNC +{ + XMC_LEDTS_TS_FUNC_DISABLE = 0, /**< Disable touch-sense function */ + XMC_LEDTS_TS_FUNC_ENABLE = 1 /**< Enable touch-sense function */ +} XMC_LEDTS_TS_FUNC_t; + +/** + * Defines LED function enable/disable. Use type XMC_LEDTS_LED_FUNC_t for this enum. + */ +typedef enum XMC_LEDTS_LED_FUNC +{ + XMC_LEDTS_LED_FUNC_DISABLE = 0, /**< Disable LED function */ + XMC_LEDTS_LED_FUNC_ENABLE = 1 /**< Enable LED function */ +} XMC_LEDTS_LED_FUNC_t; + +/** + * Defines Clock master enable/disable. Use type for XMC_LEDTS_CLOCK_TYPE_t for this enum. + */ +typedef enum XMC_LEDTS_CLOCK_TYPE +{ + XMC_LEDTS_CLOCK_TYPE_MASTER = 0, /**< Kernel generates its own clock */ + XMC_LEDTS_CLOCK_TYPE_SLAVE = 1 /**< Clock is taken from another master kernel */ +} XMC_LEDTS_CLOCK_TYPE_t; + +/** + * Defines enable/disable of autoscan time period synchronization. Use type XMC_LEDTS_TP_SYNC_t for this enum. + */ +typedef enum XMC_LEDTS_TP_SYNC +{ + XMC_LEDTS_TP_SYNC_DISABLE = 0, /**< Synchronization is disabled */ + XMC_LEDTS_TP_SYNC_ENABLE = 1 /**< Synchronization enabled on Kernel0 autoscan time period */ +} XMC_LEDTS_TP_SYNC_t; + +/** + * Defines Suspend request configuration. Use type XMC_LEDTS_SUSPEND_t for this enum. + */ +typedef enum XMC_LEDTS_SUSPEND +{ + XMC_LEDTS_SUSPEND_DISABLE = 0, /**< Ignore suspend request */ + XMC_LEDTS_SUSPEND_ENABLE = 1 /**< Enable suspend according to request */ +} XMC_LEDTS_SUSPEND_t; + +/** + * Defines number of bits to mask for time frame event validation. Use type XMC_LEDTS_TS_COUNTER_MASK_t for this enum. + */ +typedef enum XMC_LEDTS_TS_COUNTER_MASK +{ + XMC_LEDTS_TS_COUNTER_MASK_1_LSB = 0, /**< Mask LSB bit only */ + XMC_LEDTS_TS_COUNTER_MASK_2_LSB = 1, /**< Mask 2 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_3_LSB = 2, /**< Mask 3 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_4_LSB = 3, /**< Mask 4 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_5_LSB = 4, /**< Mask 5 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_6_LSB = 5, /**< Mask 6 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_7_LSB = 6, /**< Mask 7 LSB bits */ + XMC_LEDTS_TS_COUNTER_MASK_8_LSB = 7 /**< Mask 8 LSB bits */ +} XMC_LEDTS_TS_COUNTER_MASK_t; + +/** + * Defines Enable/disable of (extended) time frame validation. Use type XMC_LEDTS_TF_VALIDATION_t for this enum. + */ +typedef enum XMC_LEDTS_TF_VALIDATION +{ + XMC_LEDTS_TF_VALIDATION_DISABLE = 0, /**< Disable time frame validation */ + XMC_LEDTS_TF_VALIDATION_ENABLE = 1 /**< Enable time frame validation */ +} XMC_LEDTS_TF_VALIDATION_t; + +/** + * Defines Enable or disable interrupts. Use type XMC_LEDTS_INTERRUPT_t for this enum. + */ +typedef enum XMC_LEDTS_INTERRUPT +{ + XMC_LEDTS_INTERRUPT_TIMESLICE = LEDTS_GLOBCTL_ITS_EN_Msk, /**< Enable or Disable time slice interrupt */ + XMC_LEDTS_INTERRUPT_TIMEFRAME = LEDTS_GLOBCTL_ITF_EN_Msk, /**< Enable or Disable time frame interrupt */ + XMC_LEDTS_INTERRUPT_TIMEPERIOD = LEDTS_GLOBCTL_ITP_EN_Msk /**< Enable or Disable autoscan time period interrupt */ +} XMC_LEDTS_INTERRUPT_t; + +/** + * Defines Touch-Sense TSIN pad turn. Use type XMC_LEDTS_PAD_TURN_t for this enum. + */ +typedef enum XMC_LEDTS_PAD_TURN +{ + XMC_LEDTS_PAD_TURN_0 = 0, /**< TSIN0 is next or currently active */ + XMC_LEDTS_PAD_TURN_1 = 1, /**< TSIN1 is next or currently active */ + XMC_LEDTS_PAD_TURN_2 = 2, /**< TSIN2 is next or currently active */ + XMC_LEDTS_PAD_TURN_3 = 3, /**< TSIN3 is next or currently active */ + XMC_LEDTS_PAD_TURN_4 = 4, /**< TSIN4 is next or currently active */ + XMC_LEDTS_PAD_TURN_5 = 5, /**< TSIN5 is next or currently active */ + XMC_LEDTS_PAD_TURN_6 = 6, /**< TSIN6 is next or currently active */ + XMC_LEDTS_PAD_TURN_7 = 7 /**< TSIN7 is next or currently active */ +} XMC_LEDTS_PAD_TURN_t; + +/** + * Defines software control for Touch-Sense pad turn. Use type XMC_LEDTS_PAD_TURN_SW_CONTROL_t for this enum. + */ +typedef enum XMC_LEDTS_PAD_TURN_SW_CONTROL +{ + XMC_LEDTS_SW_CONTROL_DISABLE = 0, /**< Disable software control. Auto hardware control */ + XMC_LEDTS_SW_CONTROL_ENABLE = 1 /**< Enable software control for pad turn */ +} XMC_LEDTS_PAD_TURN_SW_CONTROL_t; + +/** + * Defines External pull-up on touch-sense pin. Use type XMC_LEDTS_EXT_PULLUP_COLA_t for this enum. + */ +typedef enum XMC_LEDTS_EXT_PULLUP_COLA +{ + XMC_LEDTS_EXT_PULLUP_COLA_DISABLE = 0, /**< Disable external pull-up. Internal pull-up is active */ + XMC_LEDTS_EXT_PULLUP_COLA_ENABLE = 1 /**< Enable external pull-up */ +} XMC_LEDTS_EXT_PULLUP_COLA_t; + +/** + * Defines number of accumulation counts on Touch-Sense input. Use type XMC_LEDTS_ACCUMULATION_COUNT_t for this enum. + */ +typedef enum XMC_LEDTS_ACCUMULATION_COUNT +{ + XMC_LEDTS_ACCUMULATION_COUNT_1_TIME = 0, /**< Accumulate once */ + XMC_LEDTS_ACCUMULATION_COUNT_2_TIMES = 1, /**< Accumulate twice */ + XMC_LEDTS_ACCUMULATION_COUNT_3_TIMES = 2, /**< Accumulate thrice */ + XMC_LEDTS_ACCUMULATION_COUNT_4_TIMES = 3, /**< Accumulate 4 times */ + XMC_LEDTS_ACCUMULATION_COUNT_5_TIMES = 4, /**< Accumulate 5 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_6_TIMES = 5, /**< Accumulate 6 times */ + XMC_LEDTS_ACCUMULATION_COUNT_7_TIMES = 6, /**< Accumulate 7 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_8_TIMES = 7, /**< Accumulate 8 times */ + XMC_LEDTS_ACCUMULATION_COUNT_9_TIMES = 8, /**< Accumulate 9 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_10_TIMES = 9, /**< Accumulate 10 times */ + XMC_LEDTS_ACCUMULATION_COUNT_11_TIMES = 10, /**< Accumulate 11 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_12_TIMES = 11, /**< Accumulate 12 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_13_TIMES = 12, /**< Accumulate 13 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_14_TIMES = 13, /**< Accumulate 14 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_15_TIMES = 14, /**< Accumulate 15 times*/ + XMC_LEDTS_ACCUMULATION_COUNT_16_TIMES = 15 /**< Accumulate 16 times*/ +} XMC_LEDTS_ACCUMULATION_COUNT_t; + +/** + * Defines enable/disable of common compare configuration for Touch-Sense. Use type XMC_LEDTS_COMMON_COMPARE_t + * for this enum. + */ +typedef enum XMC_LEDTS_COMMON_COMPARE +{ + XMC_LEDTS_COMMON_COMPARE_DISABLE = 0, /**< Disable common compare for touch-sense */ + XMC_LEDTS_COMMON_COMPARE_ENABLE = 1 /**< Enable common compare for touch-sense */ +} XMC_LEDTS_COMMON_COMPARE_t; + +/** + * Defines extended Touch-Sense output for pin-low-level. Use type XMC_LEDTS_EXTEND_TS_OUTPUT_t for this enum. + */ +typedef enum XMC_LEDTS_EXTEND_TS_OUTPUT +{ + XMC_LEDTS_EXTEND_TS_OUTPUT_BY_1_CLK = 0, /**< Extend Touch-Sense output for pin-low-level by 1 ledts_clk */ + XMC_LEDTS_EXTEND_TS_OUTPUT_BY_4_CLK = 1, /**< Extend Touch-Sense output for pin-low-level by 4 ledts_clk */ + XMC_LEDTS_EXTEND_TS_OUTPUT_BY_8_CLK = 2, /**< Extend Touch-Sense output for pin-low-level by 8 ledts_clk */ + XMC_LEDTS_EXTEND_TS_OUTPUT_BY_16_CLK = 3 /**< Extend Touch-Sense output for pin-low-level by 16 ledts_clk */ +} XMC_LEDTS_EXTEND_TS_OUTPUT_t; + +/** + * Defines enable/disable of Touch-Sense counter auto reset configuration. Use type XMC_LEDTS_TS_COUNTER_AUTO_RESET_t + * for this enum. + */ +typedef enum XMC_LEDTS_TS_COUNTER_AUTO_RESET +{ + XMC_LEDTS_TS_COUNTER_AUTO_RESET_DISABLE = 0, /**< Disable Touch-Sense counter automatic reset */ + XMC_LEDTS_TS_COUNTER_AUTO_RESET_ENABLE = 1 /**< Enable Touch-Sense counter automatic reset to 0x00 */ +} XMC_LEDTS_TS_COUNTER_AUTO_RESET_t; + +/** + * Defines enable/disable of Touch-Sense counter saturation configuration. Use type XMC_LEDTS_TS_COUNTER_SATURATION_t + * for this enum. + */ +typedef enum XMC_LEDTS_TS_COUNTER_SATURATION +{ + XMC_LEDTS_TS_COUNTER_SATURATION_DISABLE = 0, /**< Disabled. Touch-Sense counter overflows when it reaches 0xFF */ + XMC_LEDTS_TS_COUNTER_SATURATION_ENABLE = 1 /**< Enabled. Touch-Sense counter stops counting when it reaches 0xFF */ +} XMC_LEDTS_TS_COUNTER_SATURATION_t; + +/** + * Defines number of Touch-Sense Input (for HW pad turn control). Use type XMC_LEDTS_NUMBER_TS_INPUT_t for this enum. + */ +typedef enum XMC_LEDTS_NUMBER_TS_INPUT +{ + XMC_LEDTS_NUMBER_TS_INPUT_1 = 0, /**< Only TSIN0 is used */ + XMC_LEDTS_NUMBER_TS_INPUT_2 = 1, /**< TSIN0 & TSIN1 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_3 = 2, /**< TSIN0-TSIN2 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_4 = 3, /**< TSIN0-TSIN3 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_5 = 4, /**< TSIN0-TSIN4 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_6 = 5, /**< TSIN0-TSIN5 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_7 = 6, /**< TSIN0-TSIN6 are used */ + XMC_LEDTS_NUMBER_TS_INPUT_8 = 7 /**< TSIN0-TSIN7 are used */ +} XMC_LEDTS_NUMBER_TS_INPUT_t; + +/** + * Defines level of LED column when active. Use type XMC_LEDTS_ACTIVE_LEVEL_LED_COL_t for this enum. + */ +typedef enum XMC_LEDTS_ACTIVE_LEVEL_LED_COL +{ + XMC_LEDTS_ACTIVE_LEVEL_LED_COL_LOW = 0, /**< LED column pins output low when active */ + XMC_LEDTS_ACTIVE_LEVEL_LED_COL_HIGH = 1 /**< LED column pins output high when active */ +} XMC_LEDTS_ACTIVE_LEVEL_LED_COL_t; + +/** + * Defines Number of LED columns. Use type XMC_LEDTS_NUMBER_LED_COLUMNS_t for this enum. + */ +typedef enum XMC_LEDTS_NUMBER_LED_COLUMNS +{ + XMC_LEDTS_NUMBER_LED_COLUMNS_1 = 0, /**< COLA only if TS is enabled, else COL0 only */ + XMC_LEDTS_NUMBER_LED_COLUMNS_2 = 1, /**< COLA,COL0 if TS is enabled, else COL0-1 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_3 = 2, /**< COLA,COL0-1 if TS is enabled, else COL0-2 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_4 = 3, /**< COLA,COL0-2 if TS is enabled, else COL0-3 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_5 = 4, /**< COLA,COL0-3 if TS is enabled, else COL0-4 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_6 = 5, /**< COLA,COL0-4 if TS is enabled, else COL0-5 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_7 = 6, /**< COLA,COL0-5 if TS is enabled, else COL0-6 */ + XMC_LEDTS_NUMBER_LED_COLUMNS_8 = 7 /**< Only possible if TS is disabled; COLA,COL0-6 used */ +} XMC_LEDTS_NUMBER_LED_COLUMNS_t; + +/** + * Defines Interrupt flag status. Use type XMC_LEDTS_TS_INTERRUPT_FLAG_t for this enum. + */ +typedef enum XMC_LEDTS_INTERRUPT_FLAG +{ + XMC_LEDTS_INTERRUPT_FLAG_TIMESLICE = LEDTS_EVFR_TSF_Msk, /**< Time slice interrupt flag status */ + XMC_LEDTS_INTERRUPT_FLAG_TIMEFRAME = LEDTS_EVFR_TFF_Msk, /**< Time frame interrupt flag status */ + XMC_LEDTS_INTERRUPT_FLAG_TIMEPERIOD = LEDTS_EVFR_TPF_Msk, /**< Time period interrupt flag status */ + XMC_LEDTS_INTERRUPT_FLAG_TSCOUNTER_OVERFLOW = LEDTS_EVFR_TSCTROVF_Msk, /**< TS counter overflow flag status */ +} XMC_LEDTS_TS_INTERRUPT_FLAG_t; + +/** + * Defines (Extended) Time frame interrupt flag status. Use type XMC_LEDTS_TF_INTERRUPT_FLAG_t for this enum. + */ +typedef enum XMC_LEDTS_TF_INTERRUPT_FLAG +{ + XMC_LEDTS_TF_INTERRUPT_FLAG_INACTIVE = 0, /**< (Extended) Time frame interrupt not active */ + XMC_LEDTS_TF_INTERRUPT_FLAG_ACTIVE = 1 /**< (Extended) Time frame interrupt active */ +} XMC_LEDTS_TF_INTERRUPT_FLAG_t; + +/** + * Defines Autoscan time period interrupt flag status. Use type XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_t for this enum. + */ +typedef enum XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG +{ + XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_INACTIVE = 0, /**< Autoscan time period interrupt not active */ + XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_ACTIVE = 1 /**< Autoscan time period interrupt active */ +} XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_t; + +/** + * Defines Touch-Sense counter overflow indication. Use type XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_t for this enum. + */ +typedef enum XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG +{ + XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_NO = 0, /**< Touch-sense counter has not overflowed */ + XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_YES = 1 /**< Touch-sense counter has overflowed at least once */ +} XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_t; + +/** + * Defines available LED columns. Use type XMC_LEDTS_LED_COLUMN_t for this enum. + */ +typedef enum XMC_LEDTS_LED_COLUMN +{ + XMC_LEDTS_LED_COLUMN_0 = 0, /**< Denotes LED Column 0 */ + XMC_LEDTS_LED_COLUMN_1 = 1, /**< Denotes LED Column 1 */ + XMC_LEDTS_LED_COLUMN_2 = 2, /**< Denotes LED Column 2 */ + XMC_LEDTS_LED_COLUMN_3 = 3, /**< Denotes LED Column 3 */ + XMC_LEDTS_LED_COLUMN_4 = 4, /**< Denotes LED Column 4 */ + XMC_LEDTS_LED_COLUMN_5 = 5, /**< Denotes LED Column 5 */ + XMC_LEDTS_LED_COLUMN_6 = 6, /**< Denotes LED Column 6 */ + XMC_LEDTS_LED_COLUMN_A = 7 /**< Denotes LED Column A */ +} XMC_LEDTS_LED_COLUMN_t; + +/** + * Defines available Touch-Sense inputs. Use type XMC_LEDTS_TS_INPUT_t for this enum. + */ +typedef enum XMC_LEDTS_TS_INPUT +{ + XMC_LEDTS_TS_INPUT_0 = 0, /**< TSIN0 - Denotes touch-sense line 1 */ + XMC_LEDTS_TS_INPUT_1 = 1, /**< TSIN1 - Denotes touch-sense line 2 */ + XMC_LEDTS_TS_INPUT_2 = 2, /**< TSIN2 - Denotes touch-sense line 3*/ + XMC_LEDTS_TS_INPUT_3 = 3, /**< TSIN3 - Denotes touch-sense line 4*/ + XMC_LEDTS_TS_INPUT_4 = 4, /**< TSIN4 - Denotes touch-sense line 5*/ + XMC_LEDTS_TS_INPUT_5 = 5, /**< TSIN5 - Denotes touch-sense line 6*/ + XMC_LEDTS_TS_INPUT_6 = 6, /**< TSIN6 - Denotes touch-sense line 7*/ + XMC_LEDTS_TS_INPUT_7 = 7 /**< TSIN7 - Denotes touch-sense line 8*/ +} XMC_LEDTS_TS_INPUT_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + /*Anonymous structure/union guard start*/ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Data structure for initialization of global features common to LED and touch-sense function. Use + * type XMC_LEDTS_GLOBAL_CONFIG_t for this structure. + */ +typedef struct XMC_LEDTS_GLOBAL_CONFIG +{ + union + { + struct + { + uint32_t : 2; + uint32_t clock_generation:1; /**< When this bit is set LEDTS counter takes its clock from another master + kernel. Kernel generates its own clock when this bit is not set (CMTR). + Refer @ref XMC_LEDTS_CLOCK_TYPE_t enum for possible values. */ + + uint32_t autoscan_synchronization:1; /**< Set this bit to synchronize start of autoscan time period with master + kernel(ENSYNC). Refer @ref XMC_LEDTS_TP_SYNC_t enum for possible values. */ + uint32_t : 4; + uint32_t suspend_response:1; /**< Suspend request configuration(SUSCFG). + Refer @ref XMC_LEDTS_SUSPEND_t enum for possible values.*/ + }; + uint32_t globctl; + }; +}XMC_LEDTS_GLOBAL_CONFIG_t; + +/** + * Data structure for LED function initialization. Use type XMC_LEDTS_LED_CONFIG_t for this structure. + */ +typedef struct XMC_LEDTS_LED_CONFIG +{ + union + { + struct + { + uint32_t : 28; + uint32_t column_active_level:1; /**< When this bit is set LED column level is active high, otherwise column + level is active low(COLLEV). Refer @ref XMC_LEDTS_ACTIVE_LEVEL_LED_COL_t + enum for possible values.*/ + + uint32_t no_of_led_columns:3; /**< Defines number of LED columns(NR_LEDCOL). Range 0 - 7. + Refer @ref XMC_LEDTS_NUMBER_LED_COLUMNS_t enum for possible values. */ + }; + uint32_t fnctl; + }; +}XMC_LEDTS_LED_CONFIG_t; + +/** + * Data structure for basic Touch-Sense function initialization. Use type XMC_LEDTS_TS_CONFIG_BASIC_t for + * this structure. + */ +typedef struct XMC_LEDTS_TS_CONFIG_BASIC +{ + union + { + struct + { + uint32_t : 16; + uint32_t no_of_accumulation:4; /**< Defines number of times touch-sense input pin is enabled in touch-sense + time slice of consecutive frames(ACCCNT). Range 0 - 15. + Refer @ref XMC_LEDTS_ACCUMULATION_COUNT_t enum type for possible values. */ + + uint32_t common_compare:1; /**< When this bit is set it enables common compare for all touch sense inputs. + Disables common compare when not set(TSCCMP). + Refer @ref XMC_LEDTS_COMMON_COMPARE_t enum for possible values.*/ + uint32_t : 2; + uint32_t counter_auto_reset:1; /**< When this bit is set TS-counter is automatically reset to 00H on first pad + turn of a new touch-sense pin(TSCTRR). + Refer @ref XMC_LEDTS_TS_COUNTER_AUTO_RESET_t enum for possible values.*/ + + uint32_t counter_saturation:1; /**< When this bit is set TS-counter stops counting in the touch-sense time slice + of the same frame when it reaches FFH (TSCTRSAT). + Refer @ref XMC_LEDTS_TS_COUNTER_SATURATION_t enum for possible values. */ + + uint32_t no_of_touch_inputs:3; /**< Defines number of touch-sense inputs (NR_TSIN). Range 0 - 7. + Refer @ref XMC_LEDTS_NUMBER_TS_INPUT_t enum for possible values. */ + }; + uint32_t fnctl; + }; +}XMC_LEDTS_TS_CONFIG_BASIC_t; + +/** + * Data structure for advanced Touch-Sense function initialization. Use type XMC_LEDTS_TS_CONFIG_ADVANCED_t + * for this structure. + */ +typedef struct XMC_LEDTS_TS_CONFIG_ADVANCED +{ + union + { + struct + { + uint32_t : 9; + uint32_t validation_mask:3; /**< This bit-field defines number of LSB bits to mask for TS counter and shadow + TS counter comparison when Time Frame validation is enabled(MASKVAL). + Refer @ref XMC_LEDTS_TS_COUNTER_MASK_t enum for possible values.*/ + + uint32_t time_frame_validation:1; /**< Disable or enable (extended) time frame validation(FENVAL). + when validation fails time frame interrupt is not triggered. + Refer @ref XMC_LEDTS_TF_VALIDATION_t enum for possible values.*/ + uint32_t : 1; + uint32_t : 1; + }; + uint32_t globctl; + }; + union + { + struct + { + uint32_t first_pad_turn:3; /**< This bit-field denotes TSIN[x] pin on which oscillations are measured + currently/next(PADT). Refer @ref XMC_LEDTS_PAD_TURN_t enum for possible + values.*/ + + uint32_t pad_turn_control:1; /**< Control pad turn via HW or SW(PADTSW). + Refer @ref XMC_LEDTS_PAD_TURN_SW_CONTROL_t enum for possible values. */ + + uint32_t external_pullup:1; /**< Disable or enable external pull-up on touch pin(EPULL). + Refer @ref XMC_LEDTS_EXT_PULLUP_COLA_t enum for possible values. */ + uint32_t : 16; + uint32_t pin_low_extend:2; /**< This bit extends touch-sense output for pin-low-level configuration for + adjustment of oscillation per user system. + Refer @ref XMC_LEDTS_EXTEND_TS_OUTPUT_t enum for possible values. */ + }; + uint32_t fnctl; + }; +}XMC_LEDTS_TS_CONFIG_ADVANCED_t; + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +#ifdef __cplusplus +extern "C" { +#endif +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param config Pointer to constant LEDTS Global configuration structure. Refer @ref XMC_LEDTS_GLOBAL_CONFIG_t + * data structure.
+ * + * @return + * XMC_LEDTS_STATUS_SUCCESS - on success.
+ * XMC_LEDTS_STATUS_RUNNING - LEDTS module currently active. Refer @ref XMC_LEDTS_STATUS_t enum type.
+ * + * \parDescription
+ * Initializes and configures GLOBCTL register of \a ledts with configuration data pointed by \a config. + * \par + * This API selects clock source (GLOBCTL.CMTR), enables/disables auto scan sync(GLOBCTL.ENSYNC) & + * suspend config(GLOBCTL.SUSCFG).
+ * Call this API to initialize global register fields common to both LED and touch-sense(TS).\n + * + * \parNote
+ * LEDTS should be stopped by using XMC_LEDTS_StopCounter()before calling this API.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter()\n + * + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitGlobal(XMC_LEDTS_t *const ledts, const XMC_LEDTS_GLOBAL_CONFIG_t *config); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param config Pointer to constant LEDTS LED configuration structure. Refer @ref XMC_LEDTS_LED_CONFIG_t + * data structure.
+ * + * @return + * XMC_LEDTS_STATUS_SUCCESS - on success.
+ * XMC_LEDTS_STATUS_RUNNING - LEDTS module currently active/running. Refer @ref XMC_LEDTS_STATUS_t enum type.
+ * + * \parDescription
+ * Configures FNCTL register of \a ledts with configuration data pointed by \a config and enables LED functionality. + * \par + * This API sets number of LED columns(FNCTL.NR_LEDCOL), column level(FNCTL.COLLEV) and enables LED + * functionality(GLOBCTL.LD_EN). + * \par + * Call this API to Configure \a FNCTL & \a GLOBCTL registers for LED-driving function. Global initialization of + * LEDTS module should be done by calling XMC_LEDTS_InitGlobal() prior to calling this API.\n + * + * \parNote
+ * LEDTS should be stopped by using XMC_LEDTS_StopCounter() before calling this API.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter() XMC_LEDTS_InitGlobal()\n + * + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitLED(XMC_LEDTS_t *const ledts, const XMC_LEDTS_LED_CONFIG_t *config); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param config Pointer to constant LEDTS TS basic configuration structure. Refer @ref XMC_LEDTS_TS_CONFIG_BASIC_t + * data structure.
+ * + * @return + * XMC_LEDTS_STATUS_SUCCESS - on success.
+ * XMC_LEDTS_STATUS_RUNNING - LEDTS module currently active/running. Refer @ref XMC_LEDTS_STATUS_t enum type.
+ * + * \parDescription
+ * Configures FNCTL register of \a ledts for basic touch sense functionality with configuration data pointed by \a config + * and enables TS functionality. + * \par + * This API sets number of touch inputs(FNCTL.NR_TSIN), accumulate count on touch input(FNCTL.ACCCNT). + * \par + * This API Enables/disables common compare(FNCTL.TSCCMP), TS counter auto reset(FNCTL.TSCTRR), counter + * saturation(FNCTL.TSCTRSAT) and enables TS functionality(GLOBCTL.TS_EN). + * \par + * Call this API to configure \a FNCTL & \a GLOBCTL registers for basic touch sense function. Global initialization + * of LEDTS module should be done by calling XMC_LEDTS_InitGlobal() prior to calling this API.\n + * + * \parNote
+ * LEDTS should be stopped by using XMC_LEDTS_StopCounter() before calling this API.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter() XMC_LEDTS_InitGlobal()\n + * + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSBasic(XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_BASIC_t *config); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param config Pointer to constant LEDTS TS advanced configuration structure. + * Refer @ref XMC_LEDTS_TS_CONFIG_ADVANCED_t data structure.
+ * + * @return + * XMC_LEDTS_STATUS_SUCCESS - on success.
+ * XMC_LEDTS_STATUS_RUNNING - LEDTS module currently active/running. Refer @ref XMC_LEDTS_STATUS_t enum type.
+ * + * \parDescription
+ * Configures FNCTL register of \a ledts for advanced touch sense functionality with configuration data pointed by + * \a config. + * \par + * This API sets number of mask-bits for time frame validation(GLOBCTL.MASKVAL) & first touch input to be active(if + * pad turn control is set to S/W)(FNCTL.PADT). + * \par + * Enables/disables time frame interrupt(GLOBCTL.ITF_EN), external pull up on touch pin(FNCTL.EPULL) & H/W or S/W + * control of pad turn(if set to H/W, touch input activation is done in round-robin sequence, starting from TSIN0) + * (FNCTL.PADTSW). + * \par + * Call this API to initialize registers for advanced touch sense function. Before calling this API Call + * XMC_LEDTS_InitGlobal() to do Global initialization and XMC_LEDTS_InitTSBasic() to do basic init of touch-sense.\n + * + * \parNote
+ * LEDTS should be stopped by using XMC_LEDTS_StopCounter() before calling this API.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter(), XMC_LEDTS_InitTSBasic().\n + * + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSAdvanced (XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_ADVANCED_t *config); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param prescaler Constant prescaler value. Range: 0H to FFFFH.
+ * + * @return + * None.
+ * + * \parDescription
+ * Kick-starts the LEDTS module by programming CLK_PS bit field of GLOBCTL register with \a prescaler value to start + * the LEDTS-counter. + * \par + * To set LEDTS counter at least one of the touch-sense or LED function should be enabled. + * Call this API to start LEDTS counter.\n + * + * \parNote
+ * This should be called after all used modules have been initialized.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter(), XMC_LEDTS_InitLED(), XMC_LEDTS_InitTSBasic(), XMC_LEDTS_InitTSAdvanced().\n + * + */ +void XMC_LEDTS_StartCounter(XMC_LEDTS_t *const ledts, const uint16_t prescaler); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * + * @return + * None.
+ * + * \parDescription
+ * Stops the LEDTS module by programming the CLK_PS bit field(with value = 0) of GLOBCTL register.
+ * This could be done when it is required to change some module configuration which requires the LEDTS-counter + * to be stopped before the register bit/bit field can be programmed.
Call this API to stop LEDTS counter.\n + * + * \parRelated API's
+ * XMC_LEDTS_StartCounter(), XMC_LEDTS_InitLED(), XMC_LEDTS_InitTSBasic(), XMC_LEDTS_InitTSAdvanced().\n + * + */ +void XMC_LEDTS_StopCounter(XMC_LEDTS_t *const ledts); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param interrupt_mask mask value of @ref XMC_LEDTS_INTERRUPT_t enum type.
+ * + * @return + * None.
+ * + * \parDescription
+ * Enables requested interrupt type by configuring GLOBCTL register with masked value \a interrupt_mask.
+ * \par + * This API can be used to enable time slice(GLOBCTL.ITS_EN) or time frame(GLOBCTL.ITF_EN )or time period + * (GLOBCTL.ITP_EN)interrupt or any combination of these interrupts by passing appropriate bitwise ORed mask value.\n + * + * \parRelated API's
+ * XMC_LEDTS_DisableInterrupt().\n + * + */ +__STATIC_INLINE void XMC_LEDTS_EnableInterrupt(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask) +{ + XMC_ASSERT("XMC_LEDTS_EnableInterrupt:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->GLOBCTL |= interrupt_mask; +} + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param interrupt_mask mask value of @ref XMC_LEDTS_INTERRUPT_t enum type.
+ * + * @return + * None.
+ * + * \parDescription
+ * Disables requested interrupt type by configuring GLOBCTL register with masked value \a interrupt_mask.
+ * \par + * This API can be used to disable time slice(GLOBCTL.ITS_EN) or time frame(GLOBCTL.ITF_EN )or time period + * (GLOBCTL.ITP_EN)interrupt or any combination of these interrupts by passing appropriate bitwise ORed mask value.\n + * + * \parRelated API's
+ * XMC_LEDTS_EnableInterrupt().\n + * + */ +__STATIC_INLINE void XMC_LEDTS_DisableInterrupt(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask) +{ + XMC_ASSERT("XMC_LEDTS_DisableInterrupt:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->GLOBCTL &= ~interrupt_mask; +} + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * + * @return + * Status flags for events. Possible event flags are 0x01(time slice), 0x02(time frame), + 0x04(time period), 0x08(TS counter overflow).
+ * + * \parDescription
+ * Returns interrupt status flag by reading TSF(time slice), TFF(time frame), TPF(time period), TSCTROVF + * (touch sense counter overflow) fields of EVFR register.
+ * Typically used in interrupt handler to find out which event has triggered the interrupt.\n + * + * \parNote
+ * These flags are set on event regardless of corresponding interrupt is enabled or not.\n + * + * \parRelated API's
+ * XMC_LEDTS_ClearInterruptFlag().\n + * + */ +uint32_t XMC_LEDTS_ReadInterruptFlag(XMC_LEDTS_t *const ledts); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param interrupt_mask mask value of @ref XMC_LEDTS_INTERRUPT_t enum type.
+ * + * @return + * None.
+ * + * \parDescription
+ * Clears interrupt status flags in EVFR register as indicated by mask value \a interrupt_mask.
+ * This API sets EVFR.CTSF, EVFR.CTFF, EVFR.CTPF bit fields to clear time slice, time frame or time period interrupts + * respectively. + * \par + * Typically used along with XMC_LEDTS_ReadInterruptFlag() to figure out which event triggered the interrupt.\n + * + * \parNote
+ * Calling this API moves interrupt from pending/active state to inactive state. If the interrupt is pulsed, + * failing to clear the event bit might cause CPU to immediately re-enter the interrupt service routine(ISR).\n + * + * \parRelated API's
+ * XMC_LEDTS_ReadInterruptFlag().\n + * + */ +void XMC_LEDTS_ClearInterruptFlag(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param pad_num Pad number. Range refer @ref XMC_LEDTS_NUMBER_TS_INPUT_t enum type.
+ * + * @return + * None.
+ * + * \parDescription
+ * Sets TSIN[x] (where x corresponds to \a active pad number to be set) field of TSIN[x](x = 0-7) .
+ * This is the TSIN[x] pin that is next or currently active in pad turn.
+ * Call this API to set the active pad turn. + * \par + * Touch sense functionality should be initialized and configured before calling this API.\n + * + */ +void XMC_LEDTS_SetActivePADNo(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t pad_num); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param column Column number. Range refer @ref XMC_LEDTS_LED_COLUMN_t enum type.
+ * @param pattern Pattern to be displayed. Range: 0H to FFH.
+ * + * @return + * None.
+ * + * \parDescription
+ * Sets LINE_x (where x corresponds to \a column number) field of LINEx(x = 0-1) register to \a pattern value.
+ * This value is output on LINE_x when LED \a column x is active.
Call this API to set desired LED pattern. + * \par + * LED functionality should be initialized and configured before calling this API.\n + * + */ +void XMC_LEDTS_SetLEDLinePattern(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t pattern); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param column Column number. Range refer @ref XMC_LEDTS_LED_COLUMN_t enum type.
+ * @param brightness LED brightness level. Range: 0H(min brightness) to FFH(max brightness).
+ * + * @return + * None.
+ * + * \parDescription
+ * Programs CMP_LDx (where x denotes \a column number) field of LDCMPx(x = 0-1)register to the requested \a brightness + * level. + * \par + * The LDCMPx registers hold the COMPARE values for their respective LED columns. These values are used for LED + * brightness control. Call this API to control brightness level of the LED. + * \par + * LED functionality should be initialized and configured before calling this API.\n + * + */ +void XMC_LEDTS_SetColumnBrightness(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t brightness); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param common_size Requested common oscillation window width. Range: FFH(min) to 00H.(max)
+ * + * @return + * None.
+ * + * \parDescription
+ * Programs the respective LDCMP1 register bit field CMP_LDA_TSCOM with \a common_size. + * \par + * Call this API to adjust the size of the common oscillation window to increase/decrease the number of recorded + * number of oscillation counts for all touch-sense inputs.\n + * + */ +void XMC_LEDTS_SetCommonOscillationWindow(XMC_LEDTS_t *const ledts, const uint8_t common_size); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * + * @return + * uint32_t Previous active LED column number. Range: 0 to 7.
+ * + * \parDescription
+ * Returns active LED column number in previous time-slice by reading FNCOL bit field of FNCTL register. + * Call this API to figure out active column during previous time slice.\n + * + */ +uint32_t XMC_LEDTS_ReadFNCOL(XMC_LEDTS_t *const ledts); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure
+ * @param count Number of LED columns to be enabled. Range: 0 to 7.
+ * + * @return + * None.
+ * + * \parDescription
+ * Sets \a count number of LED columns active by programming NR_LEDCOL bit field of FNCTL register.
+ * \par + * Call this API to set desired number of LED columns active.\n + * + * \parNote
+ * NR_LEDCOL bit field can only be modified when LEDTS counter is not running, use XMC_LEDTS_StopCounter() + * to stop LEDTS module before calling this API.\n + * + * \parRelated API's
+ * XMC_LEDTS_StopCounter().\n + */ +void XMC_LEDTS_SetNumOfLEDColumns(XMC_LEDTS_t *const ledts, uint8_t count); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * + * @return + * uint16_t Shadow touch sense counter value. Range: 0H to FFFFH.
+ * + * \parDescription
+ * Returns latched touch sense counter value by reading the TSCTRVALR field of TSVAL register.
+ * \par + * This API is typically called in time frame(TF) event handler to get oscillation count of the touch-sense input + * active in previous time frame.\n + * + * \parNote
+ * This is the latched value of the TS-counter(on every extended time frame event).\n + * + * \parRelated API's
+ * XMC_LEDTS_ReadInterruptFlag().\n + */ +uint16_t XMC_LEDTS_ReadTSVAL(XMC_LEDTS_t *const ledts); + +/** + * + * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
+ * @param touchpad Touch-sense input pad number. Range refer @ref XMC_LEDTS_NUMBER_TS_INPUT_t enum type.
+ * @param size Requested oscillation window width. Range: 0H(max) to FFH(min).
+ * + * @return + * None.
+ * + * \parDescription
+ * Sets the size of \a touchpad touch sense oscillation window to \a size. + * \par + * This API programs the respective CMP_TSx(where x is \a touchpad number) bit fields of TSCMPx(x = 0-1) register. + * \a size value determines the size of the pad oscillation window for each pad input lines during their pad turn. + * \par + * Call this API to increase/decrease recorded number of oscillation counts for the requested touch-sense input.\n + * + */ +void XMC_LEDTS_SetOscillationWindow(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t touchpad, const uint8_t size); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LEDTS0 */ + +#endif /* XMC_LEDTS_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_posif.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_posif.h new file mode 100644 index 00000000..2cbab878 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_posif.h @@ -0,0 +1,1046 @@ +/** + * @file xmc_posif.h + * @date 2016-03-09 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Initial version + * + * 2015-02-20: + * - Driver description added
+ * + * 2015-06-19: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-07-02: + * - Updated XMC_POSIF_QD_GetDirection API + * + * 2016-03-09: + * - Optimization of write only registers + * + * @endcond + * + */ + + +#ifndef XMC_POSIF_H +#define XMC_POSIF_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +#if defined(POSIF0) +#include + +/** + * @addtogroup XMClib + * @{ + */ + +/** + * @addtogroup POSIF + * @{ + * @brief Position Interface Unit (POSIF) driver for the XMC microcontroller family
+ * + * The POSIF unit is a flexible and powerful component for motor control systems that use + * rotary encoders or hall sensors as feedback loop. It provides interface for motor position and velocity measurement. + * POSIF unit works with CCU4 and CCU8 to enable position and velocity measurement and to control PWM outputs using multi channel pattern.
+ * + * Driver is divided in three POSIF functional blocks - Hall Sensor Control (POSIF_HSC), Quadrature Decoder (POSIF_QD) and + * MultiChannel Mode (POSIF_MCM).
+ * + * POSIF driver features: + * -# Configuration structure XMC_POSIF_CONFIG_t and initialization function XMC_POSIF_Init() to configure global settings + * -# Allows to change the operating mode using XMC_POSIF_SetMode() + * -# Allows the selection of one of the four inputs (A, B, C or D) using XMC_POSIF_SelectInputSource(). In hall sensor control, inputs are + * hall0, hall1 and hall2 signals. For quadrature decoder mode, inputs are phase A, phase B and index signals. + * -# Hall Sensor Control (APIs prefixed with XMC_POSIF_HSC_)
+ * - Configuration structure XMC_POSIF_HSC_CONFIG_t and initialization function XMC_POSIF_HSC_Init() + * - Update current and expected hall pattern in shadow register using XMC_POSIF_HSC_SetHallPatterns() + * - Allows immediate shadow transfer using XMC_POSIF_HSC_UpdateHallPattern() + * -# Quadrature Decoder (APIs prefixed with XMC_POSIF_QD_)
+ * - Configuration structure XMC_POSIF_QD_CONFIG_t and initialization function XMC_POSIF_QD_Init() + * - Get direction of rotation using XMC_POSIF_QD_GetDirection() + * -# MultiChannel Mode (APIs prefixed with XMC_POSIF_MCM_)
+ * - Configuration structure XMC_POSIF_MCM_CONFIG_t and initialization function XMC_POSIF_MCM_Init() + * - Update multichannel pattern in shadow register using XMC_POSIF_MCM_SetMultiChannelPattern() + * - Allows immediate shadow transfer using XMC_POSIF_MCM_UpdateMultiChannelPattern() + * -# User need to call respective init functions to configure POSIF operating mode. e.g to configure POSIF in hall sensor control with multichannel mode + * call both XMC_POSIF_HSC_Init() and XMC_POSIF_MCM_Init(). + * -# Allows to enable and disable interrupt sources and assign to service request node using XMC_POSIF_EnableEvent(), XMC_POSIF_DisableEvent() and XMC_POSIF_SetInterruptNode() + + */ +/* POSIF is not available on XMC11 and XMC12 devices */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_POSIF_PCONF_INSEL_Msk (0x3fUL << POSIF_PCONF_INSEL0_Pos) /*< Mask for input pins selection */ +#define XMC_POSIF_INSEL_MAX (4U) /*< Maximum possible input selector */ +#define XMC_POSIF_HALPS_HALLPAT_Msk (0x3FUL) + +#if ((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || (UC_SERIES == XMC14)) +#define XMC_POSIF_CHECK_MODULE_PTR(PTR) ( ((PTR)== POSIF0) || ((PTR)== POSIF1) ) /*< Check for valid module pointer */ +#else +#define XMC_POSIF_CHECK_MODULE_PTR(PTR) ( ((PTR)== POSIF0)) /*< Check for valid module pointer */ +#endif + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +/** + * Defines the return status, to verify the POSIF related API calls. Use type @ref XMC_POSIF_STATUS_t for this enum. + */ +typedef enum XMC_POSIF_STATUS +{ + XMC_POSIF_STATUS_OK = 0U, /**< API fulfills request */ + XMC_POSIF_STATUS_ERROR /**< API cannot fulfill request */ +} XMC_POSIF_STATUS_t; + +/** + * Defines POSIF configurable modes.Use type @ref XMC_POSIF_MODE_t for this enum. + * The members defines the function selector(FSEL) bitfields of \a PCONF register. + */ +typedef enum XMC_POSIF_MODE +{ + XMC_POSIF_MODE_HALL_SENSOR = 0U, /**< Hall sensor mode */ + XMC_POSIF_MODE_QD , /**< Quadrature Decoder mode */ + XMC_POSIF_MODE_MCM , /**< Standalone Multichannel mode */ + XMC_POSIF_MODE_MCM_QD /**< Quadrature Decoder + Standalone Multichannel mode */ +} XMC_POSIF_MODE_t; + +/** + * Defines POSIF configurable input ports.Use type @ref XMC_POSIF_INPUT_PORT_t for this enum. + * The member defines the respective input selector(INSELX) bitfields of \a PCONF register. + * It selects, which input is used for the phase or Hall input function (depending on the module is set for + * Quadrature Decoder or Hall Sensor Mode). Same enum can be used to configure pattern update signal select by configuring + * \a PCONF register's \a MSETS bit field. + */ +typedef enum XMC_POSIF_INPUT_PORT +{ + XMC_POSIF_INPUT_PORT_A = 0U, /**< INPUT-A */ + XMC_POSIF_INPUT_PORT_B , /**< INPUT-B */ + XMC_POSIF_INPUT_PORT_C , /**< INPUT-C */ + XMC_POSIF_INPUT_PORT_D , /**< INPUT-D */ + XMC_POSIF_INPUT_PORT_E , /**< INPUT-E */ + XMC_POSIF_INPUT_PORT_F , /**< INPUT-F */ + XMC_POSIF_INPUT_PORT_G , /**< INPUT-G */ + XMC_POSIF_INPUT_PORT_H /**< INPUT-H */ +} XMC_POSIF_INPUT_PORT_t; + +/** + * Defines active level of an input signal.Use type @ref XMC_POSIF_INPUT_ACTIVE_LEVEL_t for this enum. + */ +typedef enum XMC_POSIF_INPUT_ACTIVE_LEVEL +{ + XMC_POSIF_INPUT_ACTIVE_LEVEL_HIGH = 0U, /**< Input - Active High */ + XMC_POSIF_INPUT_ACTIVE_LEVEL_LOW /**< Input - Active Low */ +} XMC_POSIF_INPUT_ACTIVE_LEVEL_t; + +/** + * Defines POSIF input debounce filter configuration.POSIF inputs are connected to low pass filter and + * this enum is used to configure low pass filters cut off frequency. + * Use type @ref XMC_POSIF_FILTER_t for this enum. + * The member defines the low pass filter configuration(LPC) bitfield of \a PCONF register. + */ +typedef enum XMC_POSIF_FILTER +{ + XMC_POSIF_FILTER_DISABLED = 0U, /**< No filtering */ + XMC_POSIF_FILTER_1_CLOCK_CYCLE , /**< Filter of 1 Clock Cycle */ + XMC_POSIF_FILTER_2_CLOCK_CYCLE , /**< Filter of 2 Clock Cycles */ + XMC_POSIF_FILTER_4_CLOCK_CYCLE , /**< Filter of 4 Clock Cycles */ + XMC_POSIF_FILTER_8_CLOCK_CYCLE , /**< Filter of 8 Clock Cycles */ + XMC_POSIF_FILTER_16_CLOCK_CYCLE , /**< Filter of 16 Clock Cycles */ + XMC_POSIF_FILTER_32_CLOCK_CYCLE , /**< Filter of 32 Clock Cycles */ + XMC_POSIF_FILTER_64_CLOCK_CYCLE /**< Filter of 64 Clock Cycles */ +} XMC_POSIF_FILTER_t; + +/** + * Defines POSIF events.Use type @ref XMC_POSIF_IRQ_EVENT_t for this enum. + * The member defines available event sources.It is used to configure which event to be used for + * interrupt generation using \a PFLGE register. [ PFLG,SPFLG,RPFLG] + */ +typedef enum XMC_POSIF_IRQ_EVENT +{ + XMC_POSIF_IRQ_EVENT_CHE = 0U, /**< Hall Mode : Correct Hall Event */ + XMC_POSIF_IRQ_EVENT_WHE = 1U, /**< Hall Mode : Wrong Hall Event */ + XMC_POSIF_IRQ_EVENT_HALL_INPUT = 2U, /**< Hall Mode : Hall Input update */ + XMC_POSIF_IRQ_EVENT_MCP_SHADOW_TRANSFER = 4U, /**< Hall Mode + MCM Mode : MC Pattern shadow transfer */ + XMC_POSIF_IRQ_EVENT_INDX = 8U, /**< Quadrature Mode : Index event detection */ + XMC_POSIF_IRQ_EVENT_ERR = 9U, /**< Quadrature Mode : Quadrature Phase Error */ + XMC_POSIF_IRQ_EVENT_CNT = 10U, /**< Quadrature Mode : Quadrature Clock event */ + XMC_POSIF_IRQ_EVENT_DIR = 11U, /**< Quadrature Mode : Quadrature Direction change event */ + XMC_POSIF_IRQ_EVENT_PCLK = 12U /**< Quadrature Mode : Quadrature period clock generation event */ +} XMC_POSIF_IRQ_EVENT_t; + +/** + * Defines POSIF service request lines.Use type @ref XMC_POSIF_SR_ID_t for this enum. + * It used to connect POSIF event to required service request line. + * in \a PFLGE register for interrupt generation. + */ +typedef enum XMC_POSIF_SR_ID +{ + XMC_POSIF_SR_ID_0 = 0U, /**< SR-0 */ + XMC_POSIF_SR_ID_1 /**< SR-1 */ +} XMC_POSIF_SR_ID_t; + +/** + * Defines position decoder mode selection.Use type @ref XMC_POSIF_QD_MODE_t for this enum. + * The member defines configuration for the operation of the quadrature decoder mode. + * It used to configure \a QDC register. + */ +typedef enum XMC_POSIF_QD_MODE +{ + XMC_POSIF_QD_MODE_QUADRATURE = 0U, /**< Standard Quadrature Mode */ + XMC_POSIF_QD_MODE_DIRECTION_COUNT /**< Direction Count Mode */ +} XMC_POSIF_QD_MODE_t; + +/** + * Defines motor rotation direction.Use type @ref XMC_POSIF_QD_DIR_t for this enum. + * The member defines the direction in quadrature mode. + */ +typedef enum XMC_POSIF_QD_DIR +{ + XMC_POSIF_QD_DIR_COUNTERCLOCKWISE = 0U, /**< Counter Clockwise */ + XMC_POSIF_QD_DIR_CLOCKWISE /**< Clockwise */ +} XMC_POSIF_QD_DIR_t; + +/** + * Defines frequency of index signal generation.Use type @ref XMC_POSIF_QD_INDEX_GENERATION_t for this enum. + * Member represents available configuration for index marker generation using \a ICM bit field in \a QDC register. + */ +typedef enum XMC_POSIF_QD_INDEX_GENERATION +{ + XMC_POSIF_QD_INDEX_GENERATION_NEVER = 0U, /**< Never generate the index marker signal */ + XMC_POSIF_QD_INDEX_GENERATION_ONCE , /**< Generate only once after the first revolution */ + XMC_POSIF_QD_INDEX_GENERATION_ALWAYS /**< Index marker generated upon every revolution */ +} XMC_POSIF_QD_INDEX_GENERATION_t; + +/** + * Defines trigger edge in hall sensor mode.Use type @ref XMC_POSIF_HSC_TRIGGER_EDGE_t for this enum. + * It can be used to configure \a PCONF register's \a SPES and \a MSES bit fields. + */ +typedef enum XMC_POSIF_HSC_TRIGGER_EDGE +{ + XMC_POSIF_HSC_TRIGGER_EDGE_RISING = 0U, /**< Rising edge */ + XMC_POSIF_HSC_TRIGGER_EDGE_FALLING /**< Falling edge */ +} XMC_POSIF_HSC_TRIGGER_EDGE_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * + * Defines POSIF peripheral register structure.Use type @ref XMC_POSIF_t for this data structure. + */ +typedef POSIF_GLOBAL_TypeDef XMC_POSIF_t; + +/** + * Defines POSIF quadrature decoder initialization data structure. + * Use type @ref XMC_POSIF_QD_CONFIG_t for this data structure. + * It used to configure Quadrature mode using \a QDC register. + */ +typedef struct XMC_POSIF_QD_CONFIG +{ + XMC_POSIF_QD_MODE_t mode; /**< Operational Mode of the quadrature encoder and decoder */ + union + { + struct + { + uint32_t phase_a: 1; /**< Phase-A active level configuration */ + uint32_t phase_b: 1; /**< Phase-B active level configuration */ + uint32_t phase_leader: 1; /**< Which of the two phase signals[Phase A or Phase B] leads the other? */ + uint32_t : 1; + uint32_t index: 2; /**< Index signal generation control. Use @ref XMC_POSIF_QD_INDEX_GENERATION_t to configure this field.*/ + uint32_t : 26; + }; + uint32_t qdc; + }; +} XMC_POSIF_QD_CONFIG_t; + +/** + * Defines POSIF hall sensor control initialization data structure. + * Use type @ref XMC_POSIF_HSC_CONFIG_t for this data structure. + * It used to initialize hall sensor mode configuration using \a PCONF register. + */ +typedef struct XMC_POSIF_HSC_CONFIG +{ + union + { + struct + { + uint32_t : 4; + uint32_t disable_idle_signal: 1; /**< Should idle signal be disabled upon wrong hall event? */ + uint32_t : 11; + uint32_t sampling_trigger: 1; /**< Of HSDA and HSDB, which one is to be used to trigger POSIF to sample hall pattern? */ + uint32_t sampling_trigger_edge: 1; /**< Which edge of the sampling trigger signal is to be considered? */ + uint32_t : 6; + uint32_t external_error_port: 2; /**< Of the 4 external error ports, which one is to be considered? */ + uint32_t external_error_enable: 1; /**< Should external errors lead to Wrong Hall event? */ + uint32_t external_error_level: 1; /**< What should be the active level of external error signal? */ + uint32_t: 4; + }; + uint32_t hall_config; + }; +} XMC_POSIF_HSC_CONFIG_t; + +/** + * Defines POSIF multi-channel mode initialization data structure. + * Use type @ref XMC_POSIF_MCM_CONFIG_t for this data structure. + * It used to initialize multi channel mode configuration using \a PCONF register. + */ +typedef struct XMC_POSIF_MCM_CONFIG +{ + union + { + struct + { + uint32_t : 5; + uint32_t pattern_sw_update: 1; /**< should multi channel pattern updated by SW ? */ + uint32_t : 12; + uint32_t pattern_update_trigger: 3; /**< Of the 8 update triggers, which one is to be considered? */ + uint32_t pattern_trigger_edge: 1; /**< Which edge of the pattern update trigger is to be considered? */ + uint32_t pwm_sync: 2; /**< Of the 4 pwm sync inputs, which one is to be considered? */ + uint32_t : 8; + }; + uint32_t mcm_config; + }; +}XMC_POSIF_MCM_CONFIG_t; + +/** + * Defines POSIF module initialization data structure. + * Use type @ref XMC_POSIF_CONFIG_t for this data structure. + * It is used to initialize POSIF module using \a PCONF register. + */ +typedef struct XMC_POSIF_CONFIG +{ + union + { + struct + { + uint32_t mode: 2; /**< POSIF Operational mode. Use @ref XMC_POSIF_MODE_t to configure */ + uint32_t :6; + uint32_t input0: 2; /**< Choice of input for Input-1 */ + uint32_t input1: 2; /**< Choice of input for Input-2 */ + uint32_t input2: 2; /**< Choice of input for Input-3 */ + uint32_t :14; + uint32_t filter: 3; /**< Input filter configuration */ + uint32_t: 1; + }; + uint32_t pconf; + }; +} XMC_POSIF_CONFIG_t; + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param peripheral Pointer to an instance of POSIF module of type @ref XMC_POSIF_t + * @retval None + * + * \parDescription
+ * De-asserts the POSIF module from reset and enables the clock.\n + * Configures \a PRCLR0 register's \a POSIF0RS or \a POSIF1RS bit field depends upon \a peripheral. + * If running on other than XMC45 device then it will ungate the peripheral clock. + * + * \parNote
+ * This is the first API which application must invoke to configure POSIF. + * It is internally called by XMC_POSIF_Init(). + * + * \parRelated APIs:
+ * XMC_POSIF_Disable(),XMC_POSIF_Init() \n\n\n + */ +void XMC_POSIF_Enable(XMC_POSIF_t *const peripheral); + +/** + * @param peripheral Pointer to an instance of POSIF module of type @ref XMC_POSIF_t + * @retval None + * + * \parDescription
+ * Asserts the POSIF module into reset and disables the clock.\n + * If running on other than XMC45 device then in addition it will gate the peripheral clock. + * Configures \a PRCLR0 register's \a POSIF0RS or \a POSIF1RS bitfield depends upon \a peripheral. + * + * \parRelated APIs:
+ * XMC_POSIF_Enable()\n\n\n + */ +void XMC_POSIF_Disable(XMC_POSIF_t *const peripheral); + +/** + * @param peripheral Pointer to an instance of POSIF module of type @ref XMC_POSIF_t + * @param config Pointer to POSIF configuration data(operation mode,input selection and filter configuration) + * @retval None + * + * \parDescription
+ * Initialize POSIF module with \a config.\n + * Configures POSIF global registers.This is the first API which application must invoke to configure POSIF. + * It sets up parameters common to all the POSIF modes - hall sensor,quadrature decoder and multi-channel modes of operation. + * Configures \a PCONF register with mode of operation,input selection and filter configuration. + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_Init(),XMC_POSIF_QD_Init(),XMC_POSIF_MCM_Init() \n\n\n +*/ +void XMC_POSIF_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_CONFIG_t * const config); + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param config Pointer to hall sensor control initialization data of type @ref XMC_POSIF_HSC_CONFIG_t + * @retval XMC_POSIF_STATUS_t Returns @ref XMC_POSIF_STATUS_OK if configured in Hall Sensor Mode + * else return @ref XMC_POSIF_STATUS_ERROR. + * + * \parDescription
+ * Initializes hall sensor control mode.\n + * Configures \a PCONF register with which POSIF input trigger to be used for + * sampling hall pattern.Configures \a PCONF register for idle signal generation for wrong hall event. + * + * \parNote
+ * It is necessary to have called XMC_POSIF_Init first with Hall sensor mode before invocation of this API. + * + * \parRelated APIs:
+ * XMC_POSIF_Init() \n\n\n + */ +XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_HSC_CONFIG_t * const config); + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param config Pointer to quadrature decoder initialization data + * @retval XMC_POSIF_STATUS_t Returns quadrature mode initialization status of type @ref XMC_POSIF_STATUS_t + * + * \parDescription
+ * Initializes quadrature decoder control mode.\n + * Configures \a PCONF register with quadrature mode using @ref XMC_POSIF_QD_MODE_t data structure. + * Initializes \a QDC register with quadrature mode configuration using @ref XMC_POSIF_QD_CONFIG_t structure. + * + * \parNote
+ * It is necessary to have called XMC_POSIF_Init first with Quadrature decoder mode before invocation of this API. + * + * \parRelated APIs:
+ * XMC_POSIF_Init() \n\n\n + */ +XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_QD_CONFIG_t * const config); + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param config Pointer to quadrature decoder initialization data + * @retval XMC_POSIF_STATUS_t Returns multi channel pattern initialization status of type @ref XMC_POSIF_STATUS_t + * + * \parDescription
+ * Initializes multi channel mode in Hall mode, standalone multi-channel mode and quadrature with multi-channel mode.\n + * Configures \a PCONF register with multi channel mode using @ref XMC_POSIF_MCM_CONFIG_t data structure. + * + * \parNote
+ * It is necessary to call XMC_POSIF_Init first before invocation of this API. + * For XMC_POSIF_MODE_HALL_SENSOR, it is necessary to have called XMC_POSIF_HSC_Init before invocation of this API. + * For XMC_POSIF_MODE_MCM_QD, it is necessary to have called XMC_POSIF_QD_Init before invocation of this API. + * + * \parRelated APIs:
+ * XMC_POSIF_Init(),XMC_POSIF_HSC_Init(),XMC_POSIF_QD_Init() \n\n\n + */ +XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_MCM_CONFIG_t * const config); + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param mode POSIF operating mode of type @ref XMC_POSIF_MODE_t + * @retval None + * + * \parDescription
+ * Configures POSIF module for \a mode.\n + * Configures \a PCONF register's a\ FSEL bitfield with \a mode. + * Refer @ref XMC_POSIF_MODE_t for available options. + * + * \parNote
+ * POSIF module should be in stopped state while changing the operating mode. + * + * \parRelated APIs:
+ * XMC_POSIF_Stop() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_SetMode(XMC_POSIF_t *const peripheral, const XMC_POSIF_MODE_t mode) +{ + peripheral->PCONF = ((peripheral->PCONF & ~(uint32_t)(POSIF_PCONF_FSEL_Msk)) | + (((uint32_t)mode << POSIF_PCONF_FSEL_Pos) & (uint32_t)POSIF_PCONF_FSEL_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param input0 Choice of input for input 0 [0-3] + * @param input1 Choice of input for input 1 [0-3] + * @param input2 Choice of input for input 2 [0-3] + * @retval None + * + * \parDescription
+ * Configures which input to be connected to POSIF module. \n + * Configures \a PCONF register's INSEL0,INSEL1,INSEL2 bit fields with source for the input connection for \a input0 + * \a input1, \a input2 respectively. + * + * \parNote
+ * Configures which input is used for the Phase X or Hall input X function depending upon the module is + * set for Quadrature Decoder or Hall Sensor Mode. + * + * \parRelated APIs:
+ * XMC_POSIF_Init() \n\n\n + */ +void XMC_POSIF_SelectInputSource(XMC_POSIF_t *const peripheral, const XMC_POSIF_INPUT_PORT_t input0, + const XMC_POSIF_INPUT_PORT_t input1, const XMC_POSIF_INPUT_PORT_t input2); + + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval None + * + * \parDescription
+ * Starts POSIF \a peripheral functional state machine.\n + * Starts POSIF state machine for \a peripheral.Configures \a PRUNS register's \a SRB bit field with 1. + * + * \parNote
+ * Global properties of POSIF along with mode specific properties should have been initialized before starting of POSIF + * FSM. + * + * \parRelated APIs:
+ * XMC_POSIF_Stop(),XMC_POSIF_IsRunning() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_Start(XMC_POSIF_t *const peripheral) +{ + peripheral->PRUNS = (uint32_t)POSIF_PRUNS_SRB_Msk; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval None + * + * \parDescription
+ * Stops POSIF \a peripheral functional state machine.\n + * Stop POSIF functional state machine and clears current internal status of the \a peripheral. + * Configures \a PRUNC register's \a CRB bit field with 1. + * + * \parRelated APIs:
+ * XMC_POSIF_Start(),XMC_POSIF_IsRunning() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_Stop(XMC_POSIF_t *const peripheral) +{ + peripheral->PRUNC = (uint32_t)(POSIF_PRUNC_CRB_Msk | POSIF_PRUNC_CSM_Msk); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval bool Returns false: IDLE, true:RUNNING + * + * \parDescription
+ * Returns the status of POSIF module - Running or IDLE.\n + * Retrieves the status from \a PRUN register's \a SRB bit. + * + * \parRelated APIs:
+ * XMC_POSIF_Start(),XMC_POSIF_Stop() \n\n\n + */ +__STATIC_INLINE bool XMC_POSIF_IsRunning(XMC_POSIF_t *const peripheral) +{ + return ((bool)peripheral->PRUN); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns last sampled hall sensor pattern. Range : [0-7] + * + * \parDescription
+ * Returns last sampled hall sensor pattern of \a peripheral.\n + * Retrieves the last sampled hall sensor pattern from \a PDBG register's \a HSP bit field of \a peripheral. + * Applications can at any point in time retrieve the last sampled hall sensor pattern by invoking this API. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation. + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_GetCurrentPattern(),XMC_POSIF_HSC_GetExpectedPattern() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_HSC_GetLastSampledPattern(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->PDBG) & POSIF_PDBG_HSP_Msk) >> POSIF_PDBG_HSP_Pos); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns current hall sensor pattern. Range : [0-7] + * + * \parDescription
+ * Returns current sampled hall sensor pattern of \a peripheral.\n + * Retrieves the current hall sensor pattern from \a HALP register's \a HCP bit field of \a peripheral. + * Applications can at any point in time retrieve the current hall sensor pattern by invoking this API. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation. + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_GetLastSampledPattern(),XMC_POSIF_HSC_GetExpectedPattern() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_HSC_GetCurrentPattern(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->HALP & POSIF_HALP_HCP_Msk) >> POSIF_HALP_HCP_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns expected hall sensor pattern. Range : [0-7] + * + * \parDescription
+ * Returns expected hall sensor pattern of \a peripheral.\n + * Retrieves the expected hall sensor pattern from \a HALP register's \a HEP bit field of \a peripheral. + * Applications can at any point in time retrieve the expected hall sensor pattern by invoking this API. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation. + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_GetLastSampledPattern(),XMC_POSIF_HSC_GetCurrentPattern() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_HSC_GetExpectedPattern(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->HALP & POSIF_HALP_HEP_Msk) >> POSIF_HALP_HEP_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param pattern The hall sensor pattern to be programmed into current pattern [0-7] + * @retval None + * + * \parDescription
+ * Configures current Hall sensor \a pattern of \a peripheral.\n + * Configures the Current hall sensor pattern on \a HALPS shadow register's \a HCPS bit field of \a peripheral. + * Applications can set at any point in time program the current hall sensor pattern by invoking this API. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation. It may be noted that the pattern is merely + * written to the shadow register. Transfer from the shadow register is based on a hardware transfer trigger + * or software trigger through API @ref XMC_POSIF_HSC_UpdateHallPattern(). + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_GetCurrentPattern(),XMC_POSIF_HSC_SetExpectedPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_HSC_SetCurrentPattern(XMC_POSIF_t *const peripheral, const uint8_t pattern) +{ + peripheral->HALPS = ((peripheral->HALPS & ~(uint32_t)(POSIF_HALPS_HCPS_Msk)) | + (((uint32_t)pattern << POSIF_HALPS_HCPS_Pos) & (uint32_t)POSIF_HALPS_HCPS_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param pattern The hall sensor pattern to be programmed into expected pattern [0-7] + * @retval None + * + * \parDescription
+ * Configures the expected hall sensor \a pattern of \a peripheral.\n + * Applications can set at any point in time program the hall sensor expected patterns by invoking this API. + * Configures the expected hall sensor pattern on \a HALPS shadow register's \a HEPS bit field of \a peripheral. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation.It may be noted that the pattern is merely + * written to the shadow register. Transfer from the shadow register is based on a hardware transfer trigger + * or software trigger through API @ref XMC_POSIF_HSC_UpdateHallPattern(). + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_GetExpectedPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_HSC_SetExpectedPattern(XMC_POSIF_t *const peripheral, const uint8_t pattern) +{ + peripheral->HALPS = ((peripheral->HALPS & ~(uint32_t)(POSIF_HALPS_HEPS_Msk)) | + (((uint32_t)pattern << POSIF_HALPS_HEPS_Pos) & (uint32_t)POSIF_HALPS_HEPS_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param pattern_mask The hall sensor pattern mask [0-63] Format of mask: (expected_pattern << 3) | (current_pattern) + * @retval None + * + * \parDescription
+ * Configures current and expected hall pattern of \a peripheral. \n + * Configures \a HALPS register with the Current and Expected hall sensor patterns in one operation. + * Applications can at any point in time program the current and expected hall sensor pattern by invoking this API. + * + * \parNote
+ * This is applicable only to the hall sensor mode of operation. It may be noted that the pattern is merely + * written to the shadow register. Transfer from the shadow register is based on a hardware transfer trigger + * or software trigger through API @ref XMC_POSIF_HSC_UpdateHallPattern(). + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_SetExpectedPattern(),XMC_POSIF_HSC_SetCurrentPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_HSC_SetHallPatterns(XMC_POSIF_t *const peripheral, const uint8_t pattern_mask) +{ + peripheral->HALPS = (uint32_t)(pattern_mask & (POSIF_HALPS_HCPS_Msk | POSIF_HALPS_HEPS_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval None + * + * \parDescription
+ * Manually performs shadow transfer of hall sensor patterns.\n + * Configures \a MCMS register's \a STHR bit field with 1. + * Setting this bit to 1 leads to an immediate update of the fields \a HALP.HCP(Current pattern) and \a HALP.HEP(Expected pattern). + * + * \parNote
+ * The transfer of hall sensor pattern shadow registers content to the sensor pattern register happens under two + * conditions. A hardware trigger starts the shadow transfer. Alternatively, the shadow transfer can be initiated + * by application software by means of invocation of this API. + * + * \parRelated APIs:
+ * XMC_POSIF_HSC_SetHallPatterns() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_HSC_UpdateHallPattern(XMC_POSIF_t *const peripheral) +{ + peripheral->MCMS = (uint32_t)POSIF_MCMS_STHR_Msk; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param pattern The 16b multi-channel pattern [0-65535] + * @retval None + * + * \parDescription
+ * Configures \a MCSM register with Multi-Channel Pattern.\n + * This 16b multi-channel pattern which controls the 16 outputs of all slices of a CCU8 module. + * Transfer from the shadow register is based on a hardware transfer trigger + * or software trigger through API @ref XMC_POSIF_MCM_UpdateMultiChannelPattern(). + * Every time that a Multi-Channel pattern transfer is triggered, this value is passed into the field \a MCM.MCMP of \a peripheral + * + * \parNote
+ * It may be noted that the pattern is merely written to the shadow register. + * + * \parRelated APIs:
+ * XMC_POSIF_MCM_GetMultiChannelPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_MCM_SetMultiChannelPattern(XMC_POSIF_t *const peripheral, const uint16_t pattern) +{ + peripheral->MCSM = pattern; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint16_t Returns configured multi channel pattern + * + * \parDescription
+ * Returns configured multi channel pattern of \a peripheral. \n + * Retrieves the Multi-Channel Pattern from \a MCM register's MCMP bit field of \a peripheral + * Applications can at any point in time retrieve the multi-channel pattern by invoking this API. + * + * \parRelated APIs:
+ * XMC_POSIF_MCM_SetMultiChannelPattern() \n\n\n + */ +__STATIC_INLINE uint16_t XMC_POSIF_MCM_GetMultiChannelPattern(XMC_POSIF_t *const peripheral) +{ + return ((uint16_t)(peripheral->MCM & (uint32_t)POSIF_MCM_MCMP_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint16_t Returns configured multi channel pattern present in shadow transfer register + * + * \parDescription
+ * Returns configured multi channel pattern in shadow register of \a peripheral. \n + * Retrieves the Multi-Channel Pattern from \a MCSM shadow register's \a MCMPS bit field. + * Applications can at any point in time retrieve the multi-channel pattern by invoking this API. + * + * It can be used when MCM is enabled. + * + * \parRelated APIs:
+ * XMC_POSIF_MCM_SetMultiChannelPattern() \n\n\n + */ +__STATIC_INLINE uint16_t XMC_POSIF_MCM_GetShadowMultiChannelPattern(XMC_POSIF_t *const peripheral) +{ + return ((uint16_t)(peripheral->MCSM & (uint32_t)POSIF_MCSM_MCMPS_Msk)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval None + * + * \parDescription
+ * Performs shadow transfer of the Multi-Channel Pattern register by configuring \a MCMS register's \a STMR bit field. + * + * \parNote
+ * Transfer multi-channel pattern shadow registers content to the actual pattern register of \a peripheral. \n + * The transfer of multi-channel pattern shadow registers content to the actual pattern register happens under two + * conditions. A hardware trigger starts the shadow transfer. Alternatively, the shadow transfer can be initiated + * by application software by means of invocation of this API. + * + * \parRelated APIs:
+ * XMC_POSIF_MCM_SetMultiChannelPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_MCM_UpdateMultiChannelPattern(XMC_POSIF_t *const peripheral) +{ + peripheral->MCMS |= (uint32_t)POSIF_MCMS_STMR_Msk; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval None + * + * \parDescription
+ * Enables update of the Multi-Channel Pattern by software in standalone multi-channel mode.\n + * Enabling update of multi-channel pattern happens under two conditions. A hardware trigger enables this update. + * Alternatively, this can be enabled by software by means of invocation of this API. + * + * \parNote
+ * The update is not done immediately due to the fact that the trigger that synchronizes the update with the PWM is + * still needed. + * + * \parRelated APIs:
+ * XMC_POSIF_MCM_UpdateMultiChannelPattern() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_MCM_EnableMultiChannelPatternUpdate(XMC_POSIF_t *const peripheral) +{ + peripheral->MCMS |= (uint32_t)POSIF_MCMS_MNPS_Msk; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval XMC_POSIF_QD_DIR_t Return direction of revolution of the motor of type @ref XMC_POSIF_QD_DIR_t + * + * \parDescription
+ * Returns the direction of revolution of the motor.\n + * Retrieves direction from \a QDC register's \a DVAL bit field in quadrature mode. + * Applications can at any point in time retrieve the direction of rotation by invoking this API. + * + * \parNote
+ * This is applicable only to the quadrature decoder mode of operation. + * + */ +__STATIC_INLINE XMC_POSIF_QD_DIR_t XMC_POSIF_QD_GetDirection(XMC_POSIF_t *const peripheral) +{ + return ((XMC_POSIF_QD_DIR_t)((peripheral->QDC & POSIF_QDC_DVAL_Msk) >> POSIF_QDC_DVAL_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns current state of quadrature decoder[Phase B,Phase A] + * + * \parDescription
+ * Returns the current state of phase signals in quadrature decoder mode of \a peripheral. \n + * Retrieves current state of the quadrature decoder from \a PDBG register's \a QCSV bit fields. + * Applications can at any point in time retrieve the current state of Phase A and Phase B signals + * by invoking this API. + * + * \parNote
+ * This is applicable only to the quadrature decoder mode of operation. + * + * \parRelated APIs:
+ * XMC_POSIF_QD_GetPreviousState() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_QD_GetCurrentState(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->PDBG & POSIF_PDBG_QCSV_Msk) >> POSIF_PDBG_QCSV_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns previous state of quadrature decoder[Phase B,Phase A] + * + * \parDescription
+ * Returns the previous state of phase signals in quadrature decoder mode of \a peripheral. \n + * Retrieves previous state of the quadrature decoder from \a PDBG register's \a QPSV bit fields. + * Applications can at any point in time retrieve the previous state of Phase A and Phase B signals + * by invoking this API. + * + * \parNote
+ * This is applicable only to the quadrature decoder mode of operation. + * + * \parRelated APIs:
+ * XMC_POSIF_QD_GetCurrentState() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_QD_GetPreviousState(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->PDBG & POSIF_PDBG_QPSV_Msk) >> POSIF_PDBG_QPSV_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @retval uint8_t Returns the index value.[1 - New rotation started, 0 - In-between] + * + * \parDescription
+ * Returns the current index value in quadrature decoder mode of \a peripheral. \n + * Retrieves current index signal value of the quadrature decoder from \a PDBG register's \a IVAL bit field. + * Applications can at any point in time retrieve the current index signal value of the quadrature decoder by + * invoking this API. + * + * \parNote
+ * This is applicable only to the quadrature decoder mode of operation. + * + */ +__STATIC_INLINE uint8_t XMC_POSIF_QD_GetCurrentIndexValue(XMC_POSIF_t *const peripheral) +{ + return ((uint8_t)((peripheral->PDBG & POSIF_PDBG_IVAL_Msk) >> POSIF_PDBG_IVAL_Pos)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param event Event to be enabled + * @retval None + * + * \parDescription
+ * Enables \a event generation of \a peripheral. \n + * Enables an IRQ generation capable \a event by configuring 1 to \a PFLGE register's \a event bit field. + * + * \parRelated APIs:
+ * XMC_POSIF_DisableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_EnableEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) +{ + peripheral->PFLGE |= (uint32_t)1 << (uint8_t)event; +} + +/** + * @brief Disables an IRQ generation capable event + * @param peripheral Pointer to an instance of POSIF module + * @param event Event to be disabled + * @retval None + * + * \parDescription
+ * Disables \a event generation of \a peripheral.\n + * Disables an IRQ generation capable \a event by configuring 0 to \a PFLGE register's \a event bit field. + * + * \parRelated APIs:
+ * XMC_POSIF_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_DisableEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) +{ + peripheral->PFLGE &= ~((uint32_t)1 << (uint8_t)event); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param event Event to be manually asserted + * @retval None + * + * \parDescription
+ * Manually generates \a event of \a peripheral. \n + * Manually asserts an IRQ generation capable event by configuring 1 to \a SPFLG register's \a event bit field. + * + * \parRelated APIs:
+ * XMC_POSIF_ClearEvent() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_SetEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) +{ + peripheral->SPFLG = (uint32_t)1 << (uint8_t)event; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param event Event to be acknowledged + * @retval None + * + * \parDescription
+ * Clears \a event by acknowledgment of \a peripheral. \n + * Acknowledges an IRQ event by configuring 1 to \a RPFLG register's \a event bit field. + * + * \parRelated APIs:
+ * XMC_POSIF_SetEvent() \n\n\n + */ +__STATIC_INLINE void XMC_POSIF_ClearEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) +{ + peripheral->RPFLG = (uint32_t)1 << (uint8_t)event; +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param event Event ID to be checked for status + * @retval uint8_t Returns event status + * + * \parDescription
+ * Returns \a event status of \a peripheral. \n + * Determines if IRQ event is asserted by retrieving data from \a PFLG register's \a event bit field. + * + * \parRelated APIs:
+ * XMC_POSIF_SetEvent(),XMC_POSIF_ClearEvent() \n\n\n + */ +__STATIC_INLINE uint8_t XMC_POSIF_GetEventStatus(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) +{ + return ((uint8_t)((peripheral->PFLG >> (uint8_t)event) & 1U)); +} + +/** + * @param peripheral Pointer to an instance of POSIF module + * @param event Event to be acknowledged of type @ref XMC_POSIF_IRQ_EVENT_t + * @param sr Service request line of type @ref XMC_POSIF_SR_ID_t + * @retval None + * + * \parDescription
+ * Configures \a event to generate \a sr (service request) of \a peripheral. \n + * Binds an IRQ event to a service request line by configuring \a PFLGE register's \a event bit field. + */ +void XMC_POSIF_SetInterruptNode(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event, const XMC_POSIF_SR_ID_t sr); + +#ifdef __cplusplus +} +#endif /* #if defined(POSIF0) */ + +/** + * @} + */ + +/** + * @} + */ + +#endif + +#endif /* XMC_POSIF_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_rtc.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_rtc.h new file mode 100644 index 00000000..f0b7d3a5 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_rtc.h @@ -0,0 +1,683 @@ +/** + * @file xmc_rtc.h + * @date 2016-05-19 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial + * + * 2015-05-20: + * - Documentation updates
+ * - In xmc1_rtc file XMC_RTC_Init function + * is modified by adding the RTC running condition check + * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2016-05-19: + * - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat() + * + * @endcond + * + */ + +#ifndef XMC_RTC_H +#define XMC_RTC_H + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ + +#include +#include + +/** + * + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup RTC + * @brief RTC driver for XMC microcontroller family. + * + * Real-time clock (RTC) is a clock that keeps track of the current time. Precise + * real time keeping is with a 32.768 KHz external crystal clock or a 32.768 KHz + * high precision internal clock. It provides a periodic time based interrupt and + * a programmable alarm interrupt on time match. It also supports wakeup from + * hibernate. + * + * The RTC low level driver provides functions to configure and initialize the RTC + * hardware peripheral. + * + * @{ + */ + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ + +/********************************************************************************************************************* + * ENUMS + *********************************************************************************************************************/ + +/** + * Status return values for RTC low level driver + */ +typedef enum XMC_RTC_STATUS +{ + XMC_RTC_STATUS_OK = 0U, /**< Operation successful */ + XMC_RTC_STATUS_ERROR = 1U, /**< Operation unsuccessful */ + XMC_RTC_STATUS_BUSY = 2U /**< Busy with a previous request */ +} XMC_RTC_STATUS_t; + +/** + * Events which enables interrupt request generation + */ +typedef enum XMC_RTC_EVENT +{ + XMC_RTC_EVENT_PERIODIC_SECONDS = RTC_MSKSR_MPSE_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_PERIODIC_MINUTES = RTC_MSKSR_MPMI_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_PERIODIC_HOURS = RTC_MSKSR_MPHO_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_PERIODIC_DAYS = RTC_MSKSR_MPDA_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_PERIODIC_MONTHS = RTC_MSKSR_MPMO_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_PERIODIC_YEARS = RTC_MSKSR_MPYE_Msk, /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_ALARM = RTC_MSKSR_MAI_Msk /**< Mask value to enable an event on periodic seconds */ +} XMC_RTC_EVENT_t; + +/** + * Months used to program the date + */ +typedef enum XMC_RTC_MONTH +{ + XMC_RTC_MONTH_JANUARY = 0U, + XMC_RTC_MONTH_FEBRUARY = 1U, + XMC_RTC_MONTH_MARCH = 2U, + XMC_RTC_MONTH_APRIL = 3U, + XMC_RTC_MONTH_MAY = 4U, + XMC_RTC_MONTH_JUNE = 5U, + XMC_RTC_MONTH_JULY = 6U, + XMC_RTC_MONTH_AUGUST = 7U, + XMC_RTC_MONTH_SEPTEMBER = 8U, + XMC_RTC_MONTH_OCTOBER = 9U, + XMC_RTC_MONTH_NOVEMBER = 10U, + XMC_RTC_MONTH_DECEMBER = 11U +} XMC_RTC_MONTH_t; + +/** + * Week days used program the date + */ +typedef enum XMC_RTC_WEEKDAY +{ + XMC_RTC_WEEKDAY_SUNDAY = 0U, + XMC_RTC_WEEKDAY_MONDAY = 1U, + XMC_RTC_WEEKDAY_TUESDAY = 2U, + XMC_RTC_WEEKDAY_WEDNESDAY = 3U, + XMC_RTC_WEEKDAY_THURSDAY = 4U, + XMC_RTC_WEEKDAY_FRIDAY = 5U, + XMC_RTC_WEEKDAY_SATURDAY = 6U +} XMC_RTC_WEEKDAY_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + *********************************************************************************************************************/ +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + + +/** + * Alarm time values of RTC
+ * + * The structure presents a convenient way to set/obtain the + * alarm time values for seconds, minutes, hours, days, month and year of RTC. + * The XMC_RTC_SetAlarm() and XMC_RTC_GetAlarm() can be + * used to populate the structure with the alarm time value of + * RTC + */ +typedef struct XMC_RTC_ALARM +{ + union + { + uint32_t raw0; + struct + { + uint32_t seconds : 6; /**< Alarm seconds compare value (0-59: Above this causes this bitfield to be set with 0)*/ + uint32_t : 2; + uint32_t minutes : 6; /**< Alarm minutes compare value (0-59: Above this causes this bitfield to be set with 0)*/ + uint32_t : 2; + uint32_t hours : 5; /**< Alarm hours compare value (0-23: Above this causes this bitfield to be set with 0)*/ + uint32_t : 3; + uint32_t days : 5; /**< Alarm days compare value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/ + uint32_t : 3; + }; + }; + + union + { + uint32_t raw1; + struct + { + uint32_t : 8; + uint32_t month : 4; /**< Alarm month compare value (0-11: Above this causes this bitfield to be set with 0) */ + uint32_t : 4; + uint32_t year : 16; /**< Alarm year compare value */ + }; + }; +} XMC_RTC_ALARM_t; + +/** + * Time values of RTC
+ * + * The structure presents a convenient way to set/obtain the + * time values for seconds, minutes, hours, days, month and year of RTC. + * The XMC_RTC_SetTime() and XMC_RTC_GetTime() can be + * used to populate the structure with the time value of + * RTC + */ +typedef struct XMC_RTC_TIME +{ + union + { + uint32_t raw0; + struct + { + uint32_t seconds : 6; /**< Seconds time value (0-59: Above this causes this bitfield to be set with 0) */ + uint32_t : 2; + uint32_t minutes : 6; /**< Minutes time value (0-59: Above this causes this bitfield to be set with 0) */ + uint32_t : 2; + uint32_t hours : 5; /**< Hours time value (0-23: Above this causes this bitfield to be set with 0) */ + uint32_t : 3; + uint32_t days : 5; /**< Days time value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/ + uint32_t : 3; + }; + }; + + union + { + uint32_t raw1; + struct + { + uint32_t daysofweek : 3; /**< Days of week time value (0-6: Above this causes this bitfield to be set with 0) */ + uint32_t : 5; + uint32_t month : 4; /**< Month time value (0-11: Above this causes this bitfield to be set with 0) */ + uint32_t : 4; + uint32_t year : 16; /**< Year time value */ + }; + }; +} XMC_RTC_TIME_t; +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +/** + * RTC initialization with time, alarm and clock divider(prescaler) configurations
+ * + * The structure presents a convenient way to set/obtain the time and alarm configurations + * for RTC. The XMC_RTC_Init() can be used to populate the structure with the time and alarm + * values of RTC. + */ +typedef struct XMC_RTC_CONFIG +{ + XMC_RTC_TIME_t time; + XMC_RTC_ALARM_t alarm; + uint16_t prescaler; +} XMC_RTC_CONFIG_t; + +/******************************************************************************* + * EXTENSIONS + *******************************************************************************/ + +#if UC_FAMILY == XMC1 +#include "xmc1_rtc.h" +#endif + +#if UC_FAMILY == XMC4 +#include "xmc4_rtc.h" +#endif + +/******************************************************************************* + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param config Constant pointer to a constant ::XMC_RTC_CONFIG_t structure containing the + * time, alarm time and clock divider(prescaler) configuration. + * @return XMC_RTC_STATUS_t Always returns XMC_RTC_STATUS_OK (It contains only register assignment statements) + * + * \parDescription:
+ * Initialize the RTC peripheral
+ * + * \par \if XMC4 + * The function enables the hibernate domain for accessing RTC peripheral registers, configures + * internal clock divider, time and alarm values by writing to the CTR.DIV, TIM0, TIM1, ATIM0 and + * ATIM1 registers. + * \endif + * + * \if XMC1 + * The function ungates the peripheral clock for RTC, configures + * internal clock divider, time and alarm values by writing to the CTR.DIV, TIM0, TIM1, ATIM0 and + * ATIM1 registers. + * \endif + */ +XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config); + +/** + * @return None + * + * \parDescription
+ * Enables RTC peripheral for programming its registers
+ * + * \par \if XMC4 + * Enables the hibernate domain for accessing RTC peripheral registers. + * \endif + * + * \if XMC1 + * Ungates the peripheral clock. + * \endif + * + * \parRelated APIs:
+ * XMC_RTC_Disable(), XMC_SCU_RESET_DeassertPeripheralReset() + */ +void XMC_RTC_Enable(void); + +/** + * @return None + * + * \parDescription
+ * Disables RTC peripheral for programming its registers
+ * + * \par \if XMC4 + * Empty function (Hibernate domain is not disabled). + * \endif + * + * \if XMC1 + * Gates the peripheral clock. + * \endif + * + * \parRelated APIs:
+ * XMC_RTC_Enable(), XMC_SCU_RESET_AssertPeripheralReset() + */ +void XMC_RTC_Disable(void); + +/** + * @return None + * + * \parDescription
+ * Checks RTC peripheral is enabled for programming its registers
+ * + * \par \if XMC4 + * Checks the hibernate domain is enabled or not. + * \endif + * + * \if XMC1 + * Checks peripheral clock is ungated or not. + * \endif + * + * \parRelated APIs:
+ * XMC_RTC_Enable(), XMC_RTC_Disable(), XMC_SCU_RESET_DeassertPeripheralReset(), + * XMC_SCU_RESET_AssertPeripheralReset() + */ +bool XMC_RTC_IsEnabled(void); + +/** + * @return None + * + * \parDescription
+ * Enables RTC peripheral to start counting time
+ * + * \par + * The function starts the RTC for counting time by setting + * CTR.ENB bit. Before starting the RTC, it should not be in + * running mode and also hibernate domain should be enabled. + * + * \parRelated APIs:
+ * XMC_RTC_Enable(), XMC_RTC_Stop(), XMC_SCU_RESET_DeassertPeripheralReset() + */ +void XMC_RTC_Start(void); + +/** + * @return None + * + * \parDescription
+ * Disables RTC peripheral to start counting time
+ * + * \par + * The function stops the RTC for counting time by resetting + * CTR.ENB. Before stopping the RTC, hibernate domain should be enabled. + * + * \parRelated APIs:
+ * XMC_RTC_Enable(), XMC_RTC_Start(), XMC_SCU_RESET_AssertPeripheralReset() + */ +void XMC_RTC_Stop(void); + +/** + * @param prescaler Prescaler value to be set + * @return None + * + * \parDescription:
+ * Sets the RTC module prescaler value
+ * + * \par + * The function sets the CTR.DIV bitfield to configure the prescalar value. + * The default value for the prescalar with the 32.768kHz crystal (or the internal clock) + * is 7FFFH for a time interval of 1 sec. Before setting the prescaler value RTC should be + * in stop mode and hibernate domain should be enabled. + * + * \parRelated APIs:
+ * XMC_RTC_Stop(), XMC_RTC_Enable(), XMC_RTC_GetPrescaler() + */ +void XMC_RTC_SetPrescaler(uint16_t prescaler); + +/** + * @return None + * + * \parDescription:
+ * Gets the RTC module prescaler value
+ * + * \par + * The function reads the CTR.DIV bitfield to get the prescalar value. The default value + * for the prescalar with the 32.768kHz crystal (or the internal clock) is 7FFFH for a + * time interval of 1 sec. + * + * \parRelated APIs:
+ * XMC_RTC_SetPrescaler() + */ +__STATIC_INLINE uint32_t XMC_RTC_GetPrescaler(void) +{ + return (uint32_t)(((uint32_t)RTC->CTR & (uint32_t)RTC_CTR_DIV_Msk) >> (uint32_t)RTC_CTR_DIV_Pos); +} + +/** + * @param timeval Contstant pointer to a constant ::XMC_RTC_TIME_t structure containing the + * time parameters seconds, minutes, hours, days, daysofweek, month and year. + * @return None + * + * \parDescription:
+ * Sets the RTC module time values
+ * + * \par + * The function sets the TIM0, TIM1 registers with time values. + * The values can only be written when RTC is disabled. + * See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters.
+ * + * \parRelated APIs:
+ * XMC_RTC_GetTime(), XMC_RTC_Stop() + */ +void XMC_RTC_SetTime(const XMC_RTC_TIME_t *const timeval); + +/** + * @param time Pointer to a constant ::XMC_RTC_TIME_t structure containing the time parameters + * seconds, minutes, hours, days, daysofweek, month and year. + * @return None + * + * \parDescription:
+ * Gets the RTC module time value
+ * + * \par + * The function gets the time values from TIM0, TIM1 registers. + * See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters.
+ * + * \parRelated APIs:
+ * XMC_RTC_SetTime() + */ +void XMC_RTC_GetTime(XMC_RTC_TIME_t *const time); + +/** + * @param stdtime Pointer to a ::tm structure containing the time parameters seconds, + * minutes, hours, days, daysofweek, month, year(since 1900) and days in a + * year in standard format. + * @return None + * + * \parDescription:
+ * Sets the RTC module time value in standard format
+ * + * \par + * The function sets the time values from TIM0, TIM1 registers. + * + * \parRelated APIs:
+ * XMC_RTC_SetTime(), XMC_RTC_GetTime() + */ +void XMC_RTC_SetTimeStdFormat(const struct tm *const stdtime); + +/** + * @param stdtime Pointer to a constant ::tm structure containing the time parameters seconds, + * minutes, hours, days, daysofweek, month, year(since 1900) and days in a + * year in standard format. + * @return None + * + * \parDescription:
+ * Gets the RTC module time value in standard format
+ * + * \par + * The function gets the time values from TIM0, TIM1 registers. + * See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters.
+ * For days the valid range is (1 - Actual days of month), year (since 1900) and + * daysinyear (0 -365). + * + * \parRelated APIs:
+ * XMC_RTC_SetTime(), XMC_RTC_GetTime() + */ +void XMC_RTC_GetTimeStdFormat(struct tm *const stdtime); + +/** + * @param alarm Constant pointer to a constant ::XMC_RTC_ALARM_t structure containing the + * alarm time parameters alarm seconds, alarm minutes, alarm hours, alarm days, + * alarm daysofweek, alarm month and alarm year. + * @return None + * + * \parDescription:
+ * Sets the RTC module alarm time value
+ * + * \par + * The function sets the ATIM0, ATIM1 registers with alarm time values. + * See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters.
+ * + * \parRelated APIs:
+ * XMC_RTC_GetAlarm() + */ +void XMC_RTC_SetAlarm(const XMC_RTC_ALARM_t *const alarm); + +/** + * @param alarm Pointer to a constant ::XMC_RTC_ALARM_t structure containing the + * time parameters alarm seconds, alarm minutes, alarm hours, alarm days, + * alarm daysofweek, alarm month and alarm year. + * @return None + * + * \parDescription:
+ * Gets the RTC module alarm time value
+ * + * \par + * The function gets the alarm time values from ATIM0, ATIM1 registers. + * See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters.
+ * + * \parRelated APIs:
+ * XMC_RTC_SetAlarm() + */ +void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm); + +/** + * @param stdtime Pointer to a ::tm structure containing the time parameters alarm seconds, + * alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month, + * alarm year(since 1900) and alarm days in a year in standard format. + * @return None + * + * \parDescription:
+ * Sets the RTC module alarm time value in standard format
+ * + * \par + * The function sets the alarm time values from ATIM0, ATIM1 registers. + * + * \parRelated APIs:
+ * XMC_RTC_SetAlarm(), XMC_RTC_GetAlarm() + */ +void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime); + +/** + * @param stdtime Pointer to a constant ::tm structure containing the time parameters alarm seconds, + * alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month, + * alarm year(since 1900) and alarm days in a year in standard format. + * @return None + * + * \parDescription:
+ * Gets the RTC module alarm time value in standard format
+ * + * \par + * The function gets the alarm time values from ATIM0, ATIM1 registers. + * See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters.
+ * For days the valid range is (1 - Actual days of month), year (since 1900) and + * daysinyear (0 -365). + * + * \parRelated APIs:
+ * XMC_RTC_SetAlarm(), XMC_RTC_GetAlarm() + */ +void XMC_RTC_GetAlarmStdFormat(struct tm *const stdtime); + +/** + * @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Enable RTC periodic and alarm event(s)
+ * + * \par + * The function sets the bitfields of MSKSR register to enable interrupt generation + * for requested RTC event(s). + * Setting the masking value for the event(s) containing in the ::XMC_RTC_EVENT_t leads + * to a generation of the interrupt. + * + * \parRelated APIs:
+ * XMC_RTC_DisableEvent() + */ +void XMC_RTC_EnableEvent(const uint32_t event); + +/** + * @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Disable RTC periodic and alarm event(s)
+ * + * \par + * The function resets the bitfields of MSKSR register to disable interrupt generation + * for requested RTC event(s). + * Resetting the masking value for the the event(s) containing in the ::XMC_RTC_EVENT_t blocks + * the generation of the interrupt. + * + * \parRelated APIs:
+ * XMC_RTC_EnableEvent() + */ +void XMC_RTC_DisableEvent(const uint32_t event); + +/** + * @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Clears periodic and alarm event(s) status
+ * + * \par + * The function sets the bitfields of CLRSR register to clear status bits in RAWSTAT and STSSR registers. + * Setting the value for the the RTC event(s) containing in the ::XMC_RTC_EVENT_t clears the + * corresponding status bits in RAWSTAT and STSSR registers. + * + * \parRelated APIs:
+ * XMC_RTC_GetEventStatus() + */ +void XMC_RTC_ClearEvent(const uint32_t event); + +/** + * @return None + * + * \parDescription:
+ * Gets the RTC periodic and alarm event(s) status
+ * + * \par + * The function reads the bitfields of STSSR register + * to get the status of RTC events. + * Reading the value of the register STSSR gives the status of the event(s) containing in the ::XMC_RTC_EVENT_t. + * + * \parRelated APIs:
+ * XMC_RTC_ClearEvent() + */ +uint32_t XMC_RTC_GetEventStatus(void); + +/** + * @return bool true if RTC is running + * false if RTC is not running + * + * \parDescription:
+ * Checks the running status of the RTC
+ * + * \par + * The function reads the bitfield ENB of CTR register + * to get the running status of RTC. + * + * \parRelated APIs:
+ * XMC_RTC_Start(), XMC_RTC_Stop() + */ +__STATIC_INLINE bool XMC_RTC_IsRunning(void) +{ + return (bool)(RTC->CTR & RTC_CTR_ENB_Msk); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XMC_RTC_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_scu.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_scu.h new file mode 100644 index 00000000..cacb0cf2 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_scu.h @@ -0,0 +1,598 @@ +/** + * @file xmc_scu.h + * @date 2016-03-09 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - Documentation improved
+ * - XMC_ASSERT() hanging issues have fixed for XMC4 devices.
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * - Removed STATIC_INLINE property for the below APIs and declared as void + * XMC_SCU_INTERRUPT_EnableEvent, XMC_SCU_INTERRUPT_DisableEvent, + * XMC_SCU_INTERRUPT_TriggerEvent, XMC_SCU_INTERUPT_GetEventStatus, + * XMC_SCU_INTERUPT_ClearEventStatus + * + * 2015-11-30: + * - Documentation improved
+ * + * 2016-03-09: + * - Optimization of write only registers + * + * @endcond + * + */ +#ifndef XMC_SCU_H +#define XMC_SCU_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup SCU + * @brief System Control Unit(SCU) driver for XMC microcontroller family. + * + * System control unit is the SoC power, reset and a clock manager with additional responsibility of + * providing system stability protection and other auxiliary functions.
+ * SCU provides the following features, + * -# Power control + \if XMC4 + * -# Hibernate control + \endif + * -# Reset control + * -# Clock control + * -# Miscellaneous control(boot mode, system interrupts etc.)

+ * + * The SCU driver is divided in to clock control logic, reset control logic, system interrupt control logic + \if XMC4 + * , hibernate control logic, trap control logic, parity control logic + \endif + * and miscellaneous control logic.
+ * + * Clock driver features: + * -# Allows clock configuration using the structure XMC_SCU_CLOCK_CONFIG_t and API XMC_SCU_CLOCK_Init() + \if XMC4 + * -# Provides structure XMC_SCU_CLOCK_SYSPLL_CONFIG_t for configuring the system PLL + * -# Allows selection of clock source for system PLL, XMC_SCU_CLOCK_GetSystemPllClockSource() + * -# Provides APIs for configuring different module clock frequencies XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetUsbClockDivider() + * -# Allows selection of clock source for external output, XMC_SCU_CLOCK_SetExternalOutputClockSource() + * -# Provides APIs for enabling external high power oscillator and ultra low power oscillator, XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_EnableLowPowerOscillator() + * -# Provides APIs for getting various clock frequencies XMC_SCU_CLOCK_GetPeripheralClockFrequency(), + XMC_SCU_CLOCK_GetCpuClockFrequency(), XMC_SCU_CLOCK_GetSystemClockFrequency()
+ \endif + \if XMC1 + * -# Allows selection of peripheral clock frequency, XMC_SCU_CLOCK_SetFastPeripheralClockSource() + * -# Provides API to get the peripheral clock frequency, XMC_SCU_CLOCK_GetFastPeripheralClockFrequency() + \endif + * + * Reset driver features: + \if XMC4 + * -# Allows to handle peripheral reset XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset() + * -# Allows configuration of NMI generation for selected events, XMC_SCU_INTERRUPT_EnableNmiRequest() + \endif + \if XMC1 + * -# Allows to trigger device reset XMC_SCU_RESET_AssertMasterReset() + * -# Allows to configure multiple sources for reset, XMC_SCU_RESET_EnableResetRequest() + \endif
+ * + * Interrupt driver features: + * -# Provides APIs for enabling/ disabling interrupt event generation XMC_SCU_INTERRUPT_EnableEvent(), + XMC_SCU_INTERRUPT_DisableEvent() + * -# Provides API for registering callback function for events XMC_SCU_INTERRUPT_SetEventHandler()
+ * + \if XMC4 + * Hibernate driver features: + * -# Allows configuration of hibernate domain XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain() + * -# Allows selection of standby clock source, XMC_SCU_HIB_SetStandbyClockSource() + * -# Allows selection of RTC clock source, XMC_SCU_HIB_SetRtcClockSource() + * -# Provides API for enabling slow internal clock used for backup clock, XMC_SCU_HIB_EnableInternalSlowClock()
+ * + * Trap driver features: + * -# Allows handling of trap XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_GetStatus(), XMC_SCU_TRAP_Trigger()
+ * + * Parity driver features: + * -# Parity error generated by on-chip RAM can be monitored, XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_GetStatus() + * -# Allows configuration of trap generation on detection of parity error, XMC_SCU_PARITY_EnableTrapGeneration() + * + * Power driver features: + * -# Allows to power the USB module XMC_SCU_POWER_EnableUsb(), XMC_SCU_POWER_DisableUsb() + \endif + * + * Miscellaneous features: + * -# Allows to trigger multiple capture compare unit(CCU) channels to be started together XMC_SCU_SetCcuTriggerHigh() + \if XMC4 + * -# Enables configuration of out of range comparator (ORC) XMC_SCU_EnableOutOfRangeComparator() + * -# Enables configuration of die temperature sensor XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor() + * -# Enables configuration of device boot mode XMC_SCU_SetBootMode()
+ \endif + \if XMC1 + * -# Enables configuration of die temperature sensor XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits() + * -# Allows configuring supply monitor unit using the structure XMC_SCU_SUPPLYMONITOR_t and API XMC_SCU_SupplyMonitorInit() + * -# Allows handling of protected bits XMC_SCU_LockProtectedBits(), XMC_SCU_UnlockProtectedBits()
+ \endif + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +/** + * Defines the status of SCU API execution, used to verify the SCU related API calls. + */ +typedef enum XMC_SCU_STATUS +{ + XMC_SCU_STATUS_OK = 0UL, /**< SCU related operation successfully completed.*/ + XMC_SCU_STATUS_ERROR, /**< SCU related operation failed. When API cannot fulfill request, this value is returned. */ + XMC_SCU_STATUS_BUSY, /**< Cannot execute the SCU related operation request because + another operation is in progress. \a XMC_SCU_STATUS_BUSY is returned when API is busy + processing another request. */ +} XMC_SCU_STATUS_t; + + +/********************************************************************************************************************* + * DATA TYPES + ********************************************************************************************************************/ + +/** + * Function pointer type used for registering callback functions on SCU event occurrence. + */ +typedef void (*XMC_SCU_INTERRUPT_EVENT_HANDLER_t)(void); + +/********************************************************************************************************************* + * DEVICE EXTENSIONS + ********************************************************************************************************************/ + +#if (UC_FAMILY == XMC1) +#include +#elif (UC_FAMILY == XMC4) +#include +#else +#error "Unspecified chipset" +#endif + +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * + * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits + * in the register CCUCON.
+ * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be + * combined using \a OR operation. + * + * @return None + * + * \parDescription
+ * Generates active edge(low to high) trigger for multiple CCU units at the same time.\n\n + * Before executing this API, all the required CCU timers should configure external start. + * The edge of the start signal should be selected as active edge. + * The input signal for the CCU slice should be selected as SCU input. + * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). + * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering + * the timer using this API.
+ * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerLow()\n\n\n + */ +__STATIC_INLINE void XMC_SCU_SetCcuTriggerHigh(const uint32_t trigger) +{ + SCU_GENERAL->CCUCON |= (uint32_t)trigger; +} + +/** + * + * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits + * in the register CCUCON.
+ * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be + * combined using \a OR operation. + * + * @return None + * + * \parDescription
+ * Generates passive edge(high to low) trigger for multiple CCU units at the same time.\n\n + * Before executing this API, all the required CCU timers should configure external start. + * The edge of the start signal should be selected as passive edge. + * The input signal for the CCU slice should be selected as SCU input. + * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). + * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering + * the timer using this API.
+ * \parRelated APIs:
+ * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerHigh()\n\n\n + */ +__STATIC_INLINE void XMC_SCU_SetCcuTriggerLow(const uint32_t trigger) +{ + SCU_GENERAL->CCUCON &= (uint32_t)~trigger; +} + +/** + * + * @param config Pointer to structure holding the clock prescaler values and divider values for + * configuring clock generators and clock tree.\n + * \b Range: Configure the members of structure @ref XMC_SCU_CLOCK_CONFIG_t for various + * parameters of clock setup. + * + * @return None + * + * \parDescription
+ * Initializes clock generators and clock tree.\n\n + * \if XMC1 + * Peripheral clock and system clock are configured based on the input configuration \a config. + * The system clock frequency is tuned by configuring the FDIV and IDIV values of CLKCR register. + * The values of FDIV and IDIV can be provided as part of input configuration. + * The PCLK divider determines the ratio of peripheral clock to the system clock. + * The source of RTC clock is set based on the input configuration. + * \a SystemCoreClock variable will be updated with the value of + * system clock frequency. Access to protected bit fields are handled internally. + * \endif + * \if XMC4 + * Enables the high precision oscillator(fOHP) input and configures the system and peripheral clock frequencies. + * Based on the system clock source selected in \a config, either fPLL or fOFI will be chosen as system clock. + * Based on PLL mode(normal or prescaler mode) used, PLL ramps up in steps to achieve target frequency. + * The clock dividers for CPU, CCU and peripheral clocks will be set based on the input configuration. + * The \a SystemCoreClock variable is set with the value of system clock frequency. + * \endif + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency() \n\n\n + */ +void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config); + +/** + * + * @param event Bit mask of the event to enable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t + * for providing the input value. Multiple events can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Enables the generation of interrupt for the input events.\n\n + * The events are enabled by setting the respective bit fields in the SRMSK register. \n + * Note: User should separately enable the NVIC node responsible for handling the SCU interrupt. + * The interrupt will be generated when the respective event occurs. + * \parRelated APIs:
+ * NVIC_EnableIRQ(), XMC_SCU_INTERRUPT_DisableEvent()\n\n\n + */ +void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event); + + +/** + * + * @param event Bit mask of the event to disable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t + * for providing the input value. Multiple events can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Disables generation of interrupt on occurrence of the input event.\n\n + * The events are disabled by resetting the respective bit fields in the SRMSK register. \n + * \parRelated APIs:
+ * NVIC_DisableIRQ(), XMC_SCU_INTERRUPT_EnableEvent()\n\n\n + */ +void XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event); + +/** + * + * @param event Bit mask of the event to be triggered. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t + * for providing the input value. Multiple events can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Triggers the event as if the hardware raised it.\n\n + * Event will be triggered by setting the respective bitfield in the SRSET register.\n + * Note: User should enable the NVIC node that handles the respective event for interrupt generation. + * \parRelated APIs:
+ * NVIC_EnableIRQ(), XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_ClearEventStatus() \n\n\n + */ +void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event); + +/** + * @return uint32_t Status of the SCU events. + * + * \parDescription
+ * Provides the status of all SCU events.\n\n + * The status is read from the SRRAW register. To check the status of a particular + * event, the returned value should be masked with the bit mask of the event. The bitmask + * of events can be obtained using the type @ref XMC_SCU_INTERRUPT_EVENT_t. Multiple events' + * status can be checked by combining the bit masks using \a OR operation. + * After detecting the event, the event status should be cleared using software to detect the event again. + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_ClearEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n + */ +XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus(void); + +/** + * + * @param event Bit mask of the events to clear. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t + * for providing the input value. Multiple events can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
+ * Clears the event status bit in SRRAW register.\n\n + * The events are cleared by writing value 1 to their bit positions in the SRCLR register. + * The API can be used when polling method is used. After detecting the event, the event status + * should be cleared using software to detect the event again. + * + * \parRelated APIs:
+ * XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent() \n\n\n + */ +void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event); + +/** + * + * @return uint32_t Status representing the reason for device reset. + * + * \parDescription
+ * Provides the value representing the reason for device reset.\n\n + * The return value is an encoded word, which can indicate multiple reasons for the last reset. Each bit position of the + * returned word is representative of a last reset cause. The returned value should be appropriately masked to check + * the cause of reset. + * The cause of the last reset gets automatically stored in + * the \a SCU_RSTSTAT register. The reset status shall be reset after each + * startup in order to ensure consistent source indication after the next reset. + * \b Range: The type @ref XMC_SCU_RESET_REASON_t can be used to get the bit masks of the reset cause. + * + * \parRelated APIs:
+ * XMC_SCU_RESET_ClearDeviceResetReason() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_RESET_GetDeviceResetReason(void) +{ + return ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_RSTSTAT_Msk); +} +/** + * @return None + * + * \parDescription
+ * Clears the reset reason bits in the reset status register. \n\n + * Clearing of the reset status information in the \a SCU_RSTSTAT register via register bit \a RSTCLR.RSCLR is strongly + * recommended to ensure a clear indication of the cause of next reset. + * + * \parRelated APIs:
+ * XMC_SCU_RESET_GetDeviceResetReason() \n\n\n + */ +__STATIC_INLINE void XMC_SCU_RESET_ClearDeviceResetReason(void) +{ + /* Clear RSTSTAT.RSTSTAT bitfield */ + SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk; +} + +/** + * @return uint32_t Value of CPU clock frequency. + * + * \parDescription
+ * Provides the vlaue of CPU clock frequency.\n\n + * The value is stored in a global variable \a \b SystemCoreClock. + * It is updated when the clock configuration is done using the SCU LLD APIs. + * The value represents the frequency of clock used for CPU operation. + * \b Range: Value is of type uint32_t, and gives the value of frequency in Hertz. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockFrequency(void) +{ + return SystemCoreClock; +} + +/** + * @return uint32_t Value of peripheral clock frequency in Hertz. + * + * \parDescription
+ * Provides the vlaue of clock frequency at which the peripherals are working.\n\n + * The value is derived from the CPU frequency. \b Range: Value is of type uint32_t. It is represented in Hertz. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_GetCpuClockFrequency(),XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n + */ +uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void); + +#if(UC_SERIES != XMC45) + +/** + * + * @param peripheral The peripheral for which the clock has to be gated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t + * to identify the peripheral clock to be gated. + * + * @return None + * + * \parDescription
+ * Blocks the supply of clock to the selected peripheral.\n\n + * Clock gating helps in reducing the power consumption. User can selectively gate the clocks of unused peripherals. + * \if XMC1 + * fPCLK is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks + * the clock supply for the selected peripheral. + * Software can request for individual gating of such peripheral clocks by enabling the \a SCU_CGATSET0 + * register bit field. Every bit in \a SCU_CGATSET0 register is protected by the bit protection scheme. Access to protected + * bit fields are handled internally. + * \endif + * \if XMC4 + * fPERI is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks + * the clock supply for the selected peripheral. + * Software can request for individual gating of such peripheral clocks by enabling one of the \a + * SCU_CGATSET0, \a SCU_CGATSET1 or \a SCU_CGATSET2 register bitfields. + * + * \endif + * Note: Clock gating shall not be activated unless the module is in reset state. So use \a + * XMC_SCU_CLOCK_IsPeripheralClockGated() API before enabling the gating of any peripheral. + * \parRelated APIs:
+ * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_UngatePeripheralClock() \n\n\n + */ +void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral); + +/** + * + * @param peripheral The peripheral for which the clock has to be ungated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t + * to identify the peripheral. + * + * @return None + * + * \parDescription
+ * Enables the supply of clock to the selected peripheral.\n\n + * By default when the device powers on, the peripheral clock will be gated for the + * peripherals that support clock gating. + * The peripheral clock should be enabled before using it for any functionality. + * \if XMC1 + * fPCLK is the source of clock to various peripherals. Some peripherals support clock gate. + * Software can request for individual ungating of such peripheral clocks by setting respective bits + * in the \a SCU_CGATCLR0 register. + * \endif + * \if XMC4 + * fPERI is the source of clock to various peripherals. Some peripherals support clock gate. + * Software can request for individual ungating of such peripheral clocks by setting the respective bits in one of \a + * SCU_CGATCLR0, \a SCU_CGATCLR1 or \a SCU_CGATCLR2 registers. + * \endif + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n + */ +void XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral); + +/** + * + * @param peripheral The peripheral for which the check for clock gating has to be done. + * \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral. + * + * @return bool Status of the peripheral clock gating. \b Range: true if the peripheral clock is gated. + * false if the peripheral clock ungated(gate de-asserted). + * + * \parDescription
+ * Gives the status of peripheral clock gating.\n\n + * \if XMC1 + * Checks the status of peripheral clock gating using the register CGATSTAT0. + * \endif + * \if XMC4 + * Checks the status of peripheral clock gating using one of CGATSTAT0, CGATSTAT1 or CGATSTAT2 registers. + * \endif + * It is recommended to use this API before + * enabling the gating of any peripherals through \a XMC_SCU_CLOCK_GatePeripheralClock() API. + * + * \parRelated APIs:
+ * XMC_SCU_CLOCK_UngatePeripheralClock(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n + */ +bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral); +#endif + + +/** + * @return uint32_t Status of the register mirror update.\n + * \b Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register for the mirror update event of + * interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple update events can be combined + * using \a OR operation. + * + * \parDescription
+ * Provides the status of hibernate domain register update, when the respective mirror registers are changed. \n\n + * The hibernate domain is connected to the core domain via SPI serial communication. MIRRSTS is a status register + * representing the communication of changed value of a mirror register to its corresponding register in the + * hibernate domain. The bit fields of the register indicate + * that a corresponding register of the hibernate domain is ready to accept a write or that the communication interface + * is busy with executing the previous operation.\n + * Note: There is no hibernate domain in XMC1x devices. This register is retained for legacy purpose. + */ +__STATIC_INLINE uint32_t XMC_SCU_GetMirrorStatus(void) +{ + return(SCU_GENERAL->MIRRSTS); +} + +/** + * @param event The event for which the interrupt handler is to be configured. \n + * \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t for identifying the event. + * @param handler Name of the function to be executed when the event if detected. \n + * \b Range: The function accepts no arguments and returns no value. + * @return XMC_SCU_STATUS_t Status of configuring the event handler function for the selected event.\n + * \b Range: \a XMC_SCU_STATUS_OK if the event handler is successfully configured.\n + * \a XMC_SCU_STATUS_ERROR if the input event is invalid.\n + * \parDescription
+ * Assigns the event handler function to be executed on occurrence of the selected event.\n\n + * If the input event is valid, the handler function will be assigned to a table to be executed + * when the interrupt is generated and the event status is set in the event status register. By using this API, + * polling for a particular event can be avoided. This way the CPU utilization will be optimized. Multiple SCU events + * can generate a common interrupt. When the interrupt is generated, a common interrupt service routine is executed. + * It checks for status flags of events which can generate the interrupt. The handler function will be executed if the + * event flag is set. + * + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERUPT_GetEventStatus() \n\n\n + */ +XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t event, const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler); + +/** + * @param sr_num Service request number identifying the SCU interrupt generated.\n + * \b Range: 0 to 2. XMC4x devices have one common SCU interrupt, so the value should be 0.\n + * But XMC1x devices support 3 interrupt nodes. + * @return None + * \parDescription
+ * A common function to execute callback functions for multiple events.\n\n + * It checks for the status of events which can generate the interrupt with the selected service request. + * If the event is set, the corresponding callback function will be executed. It also clears the event status bit.\n + * \b Note: This is an internal function. It should not be called by the user application. + * + * \parRelated APIs:
+ * XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n + */ +void XMC_SCU_IRQHandler(uint32_t sr_num); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* SCU_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_sdmmc.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_sdmmc.h new file mode 100644 index 00000000..0881a2f3 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_sdmmc.h @@ -0,0 +1,1656 @@ + +/** + * @file xmc_sdmmc.h + * @date 2017-02-14 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial version + * - Documentation updates + * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2016-01-16: + * - Added the following APIs to the XMC_SDMMC low level driver
+ * 1) XMC_SDMMC_EnableDelayCmdDatLines
+ * 2) XMC_SDMMC_DisableDelayCmdDatLines
+ * 3) XMC_SDMMC_SetDelay
+ * 4) XMC_SDMMC_EnableHighSpeed
+ * 5) XMC_SDMMC_DisableHighSpeed
+ * + * 2016-04-07: + * - Added XMC_SDMMC_COMMAND_RESPONSE_t
+ * + * 2016-07-11: + * - Adjust masks for the following functions:
+ * 1) XMC_SDMMC_SetBusVoltage
+ * 2) XMC_SDMMC_SetDataLineTimeout
+ * 3) XMC_SDMMC_SDClockFreqSelect
+ * + * 2017-02-14: + * - Added:
+ * 1) XMC_SDMMC_SetCardDetectionStatus()
+ * 2) XMC_SDMMC_SetCardDetectionSource()
+ + * @endcond + */ + +#ifndef XMC_SDMMC_H +#define XMC_SDMMC_H + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_common.h" + +#if defined (SDMMC) + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup SDMMC + * @brief Secure Digital/Multi Media Card (SDMMC) driver for the XMC4500 microcontroller + * + * The SDMMC peripheral provides an interface between SD/SDIO/MMC cards and the AHB. It handles + * the SD/SDIO protocol at transmission level. It automatically packs data and checks for CRC, + * start/end bits and format correctness. For SD cards, a maximum transfer rate of 24MB/sec is + * supported and for MMC cards, 48MB/sec. + * + * The peripheral can be used for applications that require large storage memory; e.g. Data logging, + * firmware updates or an embedded database. + * + * The SDMMC low level driver provides functions to configure and initialize the SDMMC hardware + * peripheral. + * @{ + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/** + * A convenient symbol for the SDMMC peripheral base address + */ +#if defined (SDMMC) +# define XMC_SDMMC ((XMC_SDMMC_t *)SDMMC_BASE) +#else +# error 'SDMMC' base peripheral pointer not defined +#endif + +/* + * Check for valid ACMD errors
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_MODULE_PTR(p) ((p) == XMC_SDMMC) + +/* + * Check for valid ACMD errors
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_ACMD_ERR(v)\ + ((v == XMC_SDMMC_ACMD12_NOT_EXEC_ERR) ||\ + (v == XMC_SDMMC_ACMD_TIMEOUT_ERR) ||\ + (v == XMC_SDMMC_ACMD_CRC_ERR) ||\ + (v == XMC_SDMMC_ACMD_END_BIT_ERR) ||\ + (v == XMC_SDMMC_ACMD_IND_ERR) ||\ + (v == XMC_SDMMC_CMD_NOT_ISSUED_BY_ACMD12_ERR)) + +/* + * Check for valid SDCLK divider frequency
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_SDCLK_FREQ(f)\ + ((f == XMC_SDMMC_CLK_DIV_1) ||\ + (f == XMC_SDMMC_CLK_DIV_2) ||\ + (f == XMC_SDMMC_CLK_DIV_4) ||\ + (f == XMC_SDMMC_CLK_DIV_8) ||\ + (f == XMC_SDMMC_CLK_DIV_16) ||\ + (f == XMC_SDMMC_CLK_DIV_32) ||\ + (f == XMC_SDMMC_CLK_DIV_64) ||\ + (f == XMC_SDMMC_CLK_DIV_128) ||\ + (f == XMC_SDMMC_CLK_DIV_256)) + +/* + * Check for valid bus voltage levels
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_BUS_VOLTAGE(v)\ + (v == XMC_SDMMC_BUS_VOLTAGE_3_3_VOLTS) + +/* + * Check for valid data timeout counter values
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_DAT_TIMEOUT_COUNTER(c)\ + ((c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_13) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_14) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_15) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_16) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_17) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_18) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_19) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_20) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_21) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_22) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_23) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_24) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_25) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_26) ||\ + (c == XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_27)) + +/* + * Valid number of data lines
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_DATA_LINES(l)\ + ((l == XMC_SDMMC_DATA_LINES_1) ||\ + (l == XMC_SDMMC_DATA_LINES_4) ||\ + (l == XMC_SDMMC_DATA_LINES_8)) + +/* + * Check data transfer dir: Host to card and vice-versa
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_DATA_TRANSFER_DIR(d)\ + ((d == XMC_SDMMC_DATA_TRANSFER_HOST_TO_CARD) ||\ + (d == XMC_SDMMC_DATA_TRANSFER_CARD_TO_HOST)) + +/* + * Min and max number of delay elements
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_MIN_DELAY_ELEMENTS (0U) +#define XMC_SDMMC_MAX_DELAY_ELEMENTS (15U) + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * Number of data lines for SDMMC data transfer + */ +typedef enum +{ + XMC_SDMMC_DATA_LINES_1 = 0x00U, /**< Single data line mode */ + XMC_SDMMC_DATA_LINES_4 = 0x02U, /**< 4-bit mode */ + XMC_SDMMC_DATA_LINES_8 = 0x20U /**< SD 8-bit mode */ +} XMC_SDMMC_DATA_LINES_t; + +/** + * Valid SD clock frequency divider selection + */ +typedef enum +{ + XMC_SDMMC_CLK_DIV_1 = 0x00U, /**< Base clock (10 Mhz -> 63 Mhz) */ + XMC_SDMMC_CLK_DIV_2 = 0x01U, /**< Base clock divided by 2 */ + XMC_SDMMC_CLK_DIV_4 = 0x02U, /**< Base clock divided by 4 */ + XMC_SDMMC_CLK_DIV_8 = 0x04U, /**< Base clock divided by 8 */ + XMC_SDMMC_CLK_DIV_16 = 0x08U, /**< Base clock divided by 16 */ + XMC_SDMMC_CLK_DIV_32 = 0x10U, /**< Base clock divided by 32 */ + XMC_SDMMC_CLK_DIV_64 = 0x20U, /**< Base clock divided by 64 */ + XMC_SDMMC_CLK_DIV_128 = 0x40U, /**< Base clock divided by 128 */ + XMC_SDMMC_CLK_DIV_256 = 0x80U /**< Base clock divided by 256 */ +} XMC_SDMMC_SDCLK_FREQ_SEL_t; + +/** + * Status return values for the SDMMC low level driver + */ +typedef enum +{ + XMC_SDMMC_STATUS_SUCCESS = 0U, /**< Operation successful */ + XMC_SDMMC_STATUS_CMD_LINE_BUSY, /**< Command line busy */ + XMC_SDMMC_STATUS_DAT_LINE_BUSY /**< Data line busy */ +} XMC_SDMMC_STATUS_t; + +/** + * SDMMC events (Normal and error events) + */ +typedef enum +{ + XMC_SDMMC_CMD_COMPLETE = 0x01U, /**< Command complete event */ + XMC_SDMMC_TX_COMPLETE = 0x02U, /**< Transmit complete event */ + XMC_SDMMC_BLOCK_GAP_EVENT = 0x04U, /**< Block gap event */ + XMC_SDMMC_BUFFER_WRITE_READY = 0x10U, /**< Buffer write ready event */ + XMC_SDMMC_BUFFER_READ_READY = 0x20U, /**< Buffer read ready event */ + XMC_SDMMC_CARD_INS = 0x40U, /**< Card insert event */ + XMC_SDMMC_CARD_REMOVAL = 0x80U, /**< Card removal event */ + XMC_SDMMC_CARD_INT = 0x100U, /**< Card INT event */ + XMC_SDMMC_CARD_ERR = 0x8000U, /**< Card error interrupt */ + XMC_SDMMC_CMD_TIMEOUT_ERR = ((uint32_t)0x01 << 16U), /**< Command time-out error */ + XMC_SDMMC_CMD_CRC_ERR = ((uint32_t)0x02U << 16U), /**< Command CRC error */ + XMC_SDMMC_CMD_END_BIT_ERR = ((uint32_t)0x04U << 16U), /**< Command end bit error */ + XMC_SDMMC_CMD_IND_ERR = ((uint32_t)0x08U << 16U), /**< Command index error */ + XMC_SDMMC_DATA_TIMEOUT_ERR = ((uint32_t)0x10U << 16U), /**< Data time-out error */ + XMC_SDMMC_DATA_CRC_ERR = ((uint32_t)0x20U << 16U), /**< Data CRC error */ + XMC_SDMMC_DATA_END_BIT_ERR = ((uint32_t)0x40U << 16U), /**< Data end bit error */ + XMC_SDMMC_CURRENT_LIMIT_ERR = ((uint32_t)0x80U << 16U), /**< Current limit error */ + XMC_SDMMC_ACMD_ERR = ((uint32_t)0x100U << 16U), /**< ACMD error */ + XMC_SDMMC_TARGET_RESP_ERR = ((uint32_t)0x1000U << 16U) /**< Target response error */ +} XMC_SDMMC_EVENT_t; + +/** + * SDMMC wakeup events + */ +typedef enum +{ + XMC_SDMMC_WAKEUP_EN_CARD_INT = SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Msk, /**< Wakeup on card interrupt */ + XMC_SDMMC_WAKEUP_EN_CARD_INS = SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Msk, /**< Wakeup on SD card insertion */ + XMC_SDMMC_WAKEUP_EN_CARD_REM = SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Msk /**< Wakeup SD card removal */ +} XMC_SDMMC_WAKEUP_EVENT_t; + +/** + * SDMMC software reset modes + */ +typedef enum +{ + XMC_SDMMC_SW_RESET_ALL = SDMMC_SW_RESET_SW_RST_ALL_Msk, /**< Software reset all */ + XMC_SDMMC_SW_RST_CMD_LINE = SDMMC_SW_RESET_SW_RST_CMD_LINE_Msk, /**< Software reset command line */ + XMC_SDMMC_SW_RST_DAT_LINE = SDMMC_SW_RESET_SW_RST_DAT_LINE_Msk /**< Software reset data line */ +} XMC_SDMMC_SW_RESET_t; + +/** + * CMD12 response errors of Auto CMD12 + */ +typedef enum +{ + XMC_SDMMC_ACMD12_NOT_EXEC_ERR = SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Msk, /**< ACMD12 not executed error */ + XMC_SDMMC_ACMD_TIMEOUT_ERR = SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Msk, /**< ACMD timeout error */ + XMC_SDMMC_ACMD_CRC_ERR = SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Msk, /**< ACMD CRC error */ + XMC_SDMMC_ACMD_END_BIT_ERR = SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Msk, /**< ACMD end bit error */ + XMC_SDMMC_ACMD_IND_ERR = SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Msk, /**< ACMD IND error */ + XMC_SDMMC_CMD_NOT_ISSUED_BY_ACMD12_ERR = SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Msk /**< CMD not issued by ACMD12 */ +} XMC_SDMMC_ACMD_ERR_t; + +/** + * SDMMC response types + */ +typedef enum +{ + XMC_SDMMC_RESPONSE_TYPE_NO_RESPONSE = 0U, /**< No response */ + XMC_SDMMC_RESPONSE_TYPE_R1, /**< Response type: R1 */ + XMC_SDMMC_RESPONSE_TYPE_R1b, /**< Response type: R1b */ + XMC_SDMMC_RESPONSE_TYPE_R2, /**< Response type: R2 */ + XMC_SDMMC_RESPONSE_TYPE_R3, /**< Response type: R3 */ + XMC_SDMMC_RESPONSE_TYPE_R6, /**< Response type: R6 */ + XMC_SDMMC_RESPONSE_TYPE_R7 /**< Response type: R7 */ +} XMC_SDMMC_RESPONSE_TYPE_t; + +/** +* Command response selection +*/ +typedef enum XMC_SDMMC_COMMAND_RESPONSE +{ + XMC_SDMMC_COMMAND_RESPONSE_NONE = 0, /**< No Response */ + XMC_SDMMC_COMMAND_RESPONSE_LONG = 1, /**< Response length 136 */ + XMC_SDMMC_COMMAND_RESPONSE_SHORT = 2, /**< Response length 48 */ + XMC_SDMMC_COMMAND_RESPONSE_SHORT_BUSY = 3, /**< Response length 48 check Busy after response */ +} XMC_SDMMC_COMMAND_RESPONSE_t; + +/** + * Types of SDMMC commands + */ +typedef enum +{ + XMC_SDMMC_COMMAND_TYPE_NORMAL = 0U, /**< Command normal */ + XMC_SDMMC_COMMAND_TYPE_SUSPEND, /**< Command suspend */ + XMC_SDMMC_COMMAND_TYPE_RESUME, /**< Command resume */ + XMC_SDMMC_COMMAND_TYPE_ABORT /**< Command abort */ +} XMC_SDMMC_COMMAND_TYPE_t; + +/** + * SDMMC transfer modes + */ +typedef enum +{ + XMC_SDMMC_TRANSFER_MODE_TYPE_SINGLE = 0x00U, /**< Transfer mode type: single */ + XMC_SDMMC_TRANSFER_MODE_TYPE_INFINITE = 0x20U, /**< Transfer mode type: infinite */ + XMC_SDMMC_TRANSFER_MODE_TYPE_MULTIPLE = 0x22U, /**< Transfer mode type: multiple */ + XMC_SDMMC_TRANSFER_MODE_TYPE_STOP_MULTIPLE = 0x22U /**< Transfer mode type: multiple stop */ +} XMC_SDMMC_TRANSFER_MODE_TYPE_t; + +/** + * Auto command transfer modes + */ +typedef enum +{ + XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_DISABLED = 0x00U, /**< ACMD mode disabled */ + XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_12 /**< ACMD12 mode */ +} XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_t; + +/** + * SDMMC bus voltage level + */ +typedef enum +{ + XMC_SDMMC_BUS_VOLTAGE_3_3_VOLTS = 0x07U +} XMC_SDMMC_BUS_VOLTAGE_t; + +/** + * Data line timeout counter values + */ +typedef enum +{ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_13 = 0U, /** SDCLK * (2 ^ 13) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_14 = 1U, /** SDCLK * (2 ^ 14) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_15 = 2U, /** SDCLK * (2 ^ 15) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_16 = 3U, /** SDCLK * (2 ^ 16) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_17 = 4U, /** SDCLK * (2 ^ 17) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_18 = 5U, /** SDCLK * (2 ^ 18) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_19 = 6U, /** SDCLK * (2 ^ 19) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_20 = 7U, /** SDCLK * (2 ^ 20) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_21 = 8U, /** SDCLK * (2 ^ 21) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_22 = 9U, /** SDCLK * (2 ^ 22) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_23 = 10U, /** SDCLK * (2 ^ 23) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_24 = 11U, /** SDCLK * (2 ^ 24) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_25 = 12U, /** SDCLK * (2 ^ 25) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_26 = 13U, /** SDCLK * (2 ^ 26) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_27 = 14U, /** SDCLK * (2 ^ 27) */ +} XMC_SDMMC_DAT_TIMEOUT_COUNTER_t; + +/** + * SDMMC data transfer direction + */ +typedef enum +{ + XMC_SDMMC_DATA_TRANSFER_HOST_TO_CARD = 0U, /** Host to card */ + XMC_SDMMC_DATA_TRANSFER_CARD_TO_HOST /** Card to host */ +} XMC_SDMMC_DATA_TRANSFER_DIR_t; + +/** + * SDMMC card detection signal source + */ +typedef enum XMC_SDMMC_CD_SOURCE +{ + XMC_SDMMC_CD_SOURCE_PIN = 0, + XMC_SDMMC_CD_SOURCE_SW = 1 << SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos +} XMC_SDMMC_CD_SOURCE_t; + +/** + * SDMMC card detection status + */ +typedef enum XMC_SDMMC_CD_STATUS +{ + XMC_SDMMC_CD_STATUS_NO_CARD = 0, + XMC_SDMMC_CD_STATUS_INSERTED = 1 << SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos +} XMC_SDMMC_CD_STATUS_t; + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ + +/** + * SDMMC device structure
+ * + * The structure represents a collection of all hardware registers used + * to configure the SDMMC peripheral on the XMC4500 microcontroller. The + * registers can be accessed with ::XMC_SDMMC. + */ +typedef struct +{ + __I uint32_t RESERVED0; + __IO uint16_t BLOCK_SIZE; + __IO uint16_t BLOCK_COUNT; + __IO uint32_t ARGUMENT1; + __IO uint16_t TRANSFER_MODE; + __IO uint16_t COMMAND; + __I uint32_t RESPONSE[4]; + __IO uint32_t DATA_BUFFER; + __I uint32_t PRESENT_STATE; + __IO uint8_t HOST_CTRL; + __IO uint8_t POWER_CTRL; + __IO uint8_t BLOCK_GAP_CTRL; + __IO uint8_t WAKEUP_CTRL; + __IO uint16_t CLOCK_CTRL; + __IO uint8_t TIMEOUT_CTRL; + __IO uint8_t SW_RESET; + __IO uint16_t INT_STATUS_NORM; + __IO uint16_t INT_STATUS_ERR; + __IO uint16_t EN_INT_STATUS_NORM; + __IO uint16_t EN_INT_STATUS_ERR; + __IO uint16_t EN_INT_SIGNAL_NORM; + __IO uint16_t EN_INT_SIGNAL_ERR; + __I uint16_t ACMD_ERR_STATUS; + __I uint16_t RESERVED1[9]; + __O uint16_t FORCE_EVENT_ACMD_ERR_STATUS; + __O uint16_t FORCE_EVENT_ERR_STATUS; + __I uint32_t RESERVED2[8]; + __O uint32_t DEBUG_SEL; + __I uint32_t RESERVED3[30]; + __IO uint32_t SPI; + __I uint32_t RESERVED4[2]; + __I uint16_t SLOT_INT_STATUS; +} XMC_SDMMC_t; + +/* Anonymous structure/union guard start */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__TASKING__) + #pragma warning 586 +#endif + +/** + * Present state of the SDMMC host controller
+ * + * The structure presents a convenient way to obtain the SDMMC peripheral's + * present state information (for example, the write protect pin level). The + * XMC_SDMMC_GetPresentState() API can be used to populate the structure + * with the state of the SD host controller. + */ +typedef union +{ + struct + { + uint32_t command_inihibit_cmd : 1; /**< Command: Inhibit command */ + uint32_t command_inihibit_dat : 1; /**< Command: Inhibit data */ + uint32_t dat_line_active : 1; /**< Data line active */ + uint32_t : 5; + uint32_t write_transfer_active : 1; /**< Write transfer active */ + uint32_t read_transfer_active : 1; /**< Read transfer active */ + uint32_t buffer_write_enable : 1; /**< Buffer write enable */ + uint32_t buffer_read_enable : 1; /**< Buffer read enable */ + uint32_t : 4; + uint32_t card_inserted : 1; /**< Card inserted */ + uint32_t card_state_stable : 1; /**< Card state stable */ + uint32_t card_detect_pin_level : 1; /**< Card detect pin level */ + uint32_t write_protect_pin_level : 1; /**< Write protect pin level */ + uint32_t dat_3_0_pin_level : 4; /**< Data 3_0 pin level */ + uint32_t cmd_line_level : 1; /**< Command line level */ + uint32_t dat7_4_pin_level : 4; /**< Data 7_4 pin level */ + uint32_t : 3; + }; + uint32_t b32; +} XMC_SDMMC_PRESENT_STATE_t; + +/** + * SDMMC transfer mode configuration + */ +typedef struct +{ + uint32_t block_size; + uint32_t num_blocks; + XMC_SDMMC_TRANSFER_MODE_TYPE_t type; + XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_t auto_cmd; + XMC_SDMMC_DATA_TRANSFER_DIR_t direction; +} XMC_SDMMC_TRANSFER_MODE_t; + +/** + * Represent an SDMMC command
+ * + * The structure holds the configuration for an SDMMC command. The SDMMC + * COMMAND register is a 16-bit register which is responsible for enabling + * configuration parameters like command type, response type, index check + * enable (and a few more). Once SDMMC.COMMAND is configured, the + * XMC_SDMMC_SendCommand() function can be used to send the command. + */ +typedef union +{ + struct + { + uint16_t response_type_sel : 2; /**< Response type select ::XMC_SDMMC_COMMAND_RESPONSE_t */ + uint16_t : 1; + uint16_t crc_check_en : 1; /**< Command CRC check enable */ + uint16_t index_check_en : 1; /**< Command index check enable */ + uint16_t dat_present_sel : 1; /**< Data present select */ + uint16_t cmd_type : 2; /**< Command type ::XMC_SDMMC_COMMAND_TYPE_t */ + uint16_t cmd_index : 6; /**< Command index */ + uint16_t : 2; + }; + uint16_t cmd; +} XMC_SDMMC_COMMAND_t; + +/* Anonymous structure/union guard end */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__TASKING__) + #pragma warning restore +#endif + +/** + * Card response structure + */ +typedef struct +{ + uint32_t response_0; + uint32_t response_2; + uint32_t response_4; + uint32_t response_6; +} XMC_SDMMC_RESPONSE_t; + +/** + * SDMMC configuration data structure
+ * + * The structure is used to configure the bus width and the clock divider. + */ +typedef struct +{ + uint8_t bus_width; /**< SDMMC bus width */ + XMC_SDMMC_SDCLK_FREQ_SEL_t clock_divider; /**< SDMMC clock divider */ +} XMC_SDMMC_CONFIG_t; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool + * + * \parDescription:
+ * Get power status of the SDMMC peripheral
+ * + * \par + * The function checks the SD_BUS_POWER bit-field of the POWER_CTRL register and returns + * a boolean value - "on" or "off". + */ +bool XMC_SDMMC_GetPowerStatus(XMC_SDMMC_t *const sdmmc); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Enable SDMMC peripheral
+ * + * \par + * The function de-asserts the peripheral reset. The peripheral needs to be initialized. + */ +void XMC_SDMMC_Enable(XMC_SDMMC_t *const sdmmc); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Disable SDMMC peripheral
+ * + * \par + * The function asserts the peripheral reset. + */ +void XMC_SDMMC_Disable(XMC_SDMMC_t *const sdmmc); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param config A pointer to a constant XMC_SDMMC_CONFIG_t structure containing the + * bus width and clock divider configuration + * @return ::XMC_SDMMC_STATUS_SUCCESS + * + * \parDescription:
+ * Initialize the SDMMC peripheral
+ * + * \par + * The function enables the SDMMC peripheral, sets the internal clock divider register + * and sets the bus width. + */ +XMC_SDMMC_STATUS_t XMC_SDMMC_Init(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_CONFIG_t *config); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Enable SDMMC normal and error event(s)
+ * + * \par + * The function first sets the bit-fields of EN_INT_STATUS_NORM and EN_INT_STATUS_ERR + * registers to enable interrupt status for requested normal/error SDMMC events. It then + * sets the bit-fields of EN_INT_SIGNAL_NORM and EN_INT_SIGNAL_ERR to enable the + * interrupt generation for the requested events. + */ +void XMC_SDMMC_EnableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Disable normal and error SDMMC event(s)
+ * + * \par + * The function disables the interrupt generation for the requested events by clearing + * the bit-fields of EN_INT_SIGNAL_NORM and EN_INT_SIGNAL_ERR registers. + * + * \parNote:
+ * The XMC_SDMMC_DisableEvent() function doesn't reset the the interrupt status. One + * may still use XMC_SDMMC_GetEvent() to check the status of requested events even if + * the interrupt generation is already disabled. + */ +void XMC_SDMMC_DisableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Clear SDMMC event(s)
+ * + * \par + * The function clears requested normal/error events by settings the bit-fields of + * the INT_STATUS register. Please check SDMMC_INT_STATUS_NORM in the XMC45000 + * manual for more details. + */ +void XMC_SDMMC_ClearEvent(XMC_SDMMC_t *const sdmmc, uint32_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) + * @return bool + * + * \parDescription:
+ * Get SDMMC event status
+ * + * \par + * The function returns the status of a single requested (normal/error) event by + * reading the appropriate bit-fields of the INT_STATUS register. + */ +bool XMC_SDMMC_GetEvent(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_EVENT_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Enable event status
+ * + * \par + * The function sets the bit-fields of EN_INT_STATUS_NORM and EN_INT_STATUS_ERR + * registers to enable interrupt status for requested normal/error SDMMC events. + */ +void XMC_SDMMC_EnableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Disable event status
+ * + * \par + * The function resets the bit-fields of EN_INT_STATUS_NORM and EN_INT_STATUS_ERR + * registers to disable interrupt status for requested normal/error SDMMC events. + */ +void XMC_SDMMC_DisableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC event (::XMC_SDMMC_EVENT_t) or a valid combination of + * logically OR'd events + * @return None + * + * \parDescription:
+ * Trigger SDMMC error events
+ * + * \par + * The SDMMC peripheral supports triggering of following error events:
+ * + * ::XMC_SDMMC_CMD_TIMEOUT_ERR, ::XMC_SDMMC_CMD_CRC_ERR, ::XMC_SDMMC_CMD_END_BIT_ERR, + * ::XMC_SDMMC_CMD_IND_ERR, ::XMC_SDMMC_DATA_TIMEOUT_ERR, ::XMC_SDMMC_DATA_CRC_ERR, + * ::XMC_SDMMC_DATA_END_BIT_ERR, ::XMC_SDMMC_CURRENT_LIMIT_ERR, ::XMC_SDMMC_ACMD_ERR, + * ::XMC_SDMMC_TARGET_RESP_ERR + * + * For triggering Auto CMD12 error, see XMC_SDMMC_TriggerACMDErr() + */ +__STATIC_INLINE void XMC_SDMMC_TriggerEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_TriggerEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->FORCE_EVENT_ERR_STATUS |= (uint16_t)(event >> 16U); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param source A valid SDMMC card detection signal source (::XMC_SDMMC_CD_SOURCE_t) + * @return None + * + * \parDescription:
+ * Selects source for card detection + */ +__STATIC_INLINE void XMC_SDMMC_SetCardDetectionSource(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_CD_SOURCE_t source) +{ + XMC_ASSERT("XMC_SDMMC_TriggerEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->HOST_CTRL |= (sdmmc->HOST_CTRL & (uint32_t)~SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Msk) | source; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param status A valid SDMMC card detection status (::XMC_SDMMC_CD_STATUS_t) + * @return None + * + * \parDescription:
+ * Sets the card detection status indicating whether card is inserted or not. + * Generates (card ins or card removal) interrupt when the normal interrupt is enabled. + * @note Only valid if SDMMC card detection signal source is set to XMC_SDMMC_CD_SOURCE_SW
+ * + */ +__STATIC_INLINE void XMC_SDMMC_SetCardDetectionStatus(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_CD_STATUS_t status) +{ + XMC_ASSERT("XMC_SDMMC_TriggerEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->HOST_CTRL |= (sdmmc->HOST_CTRL & (uint32_t)~SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Msk) | status; +} + + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool + * + * \parDescription:
+ * Check if any error event has occured
+ * + * \par + * The function can typically be used for writing an error interrupt recovery routine. + * Should any error be indicated (If XMC_SDMMC_IsAnyErrorEvent() returns true), the + * routine may then clear the event after indicating the error event and reset the + * SDMMC command and data lines. + */ +__STATIC_INLINE bool XMC_SDMMC_IsAnyErrorEvent(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_IsAnyErrorEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (bool)(sdmmc->INT_STATUS_ERR); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC wakeup event (::XMC_SDMMC_WAKEUP_EVENT_t) or a valid combination + * of logically OR'd wakeup events + * @return None + * + * \parDescription:
+ * Enable wakeup event(s)
+ * + * \par + * The function enables SDMMC wakeup events by setting appropriate bit-fields of the WAKEUP_CTRL + * register.
+ * + * List of supported wakeup events -> Wakeup on:
+ * 1) Card interrupt
+ * 2) SD card insertion
+ * 3) SD card removal
+ */ +__STATIC_INLINE void XMC_SDMMC_EnableWakeupEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_EnableWakeupEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->WAKEUP_CTRL |= (uint8_t)event; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param event A valid SDMMC wakeup event (::XMC_SDMMC_WAKEUP_EVENT_t) or a valid combination + * of logically OR'd wakeup events + * @return None + * + * \parDescription:
+ * Disable wakeup event(s)
+ * + * \par + * The function disables SDMMC wakeup events by clearing appropriate bit-fields of the WAKEUP_CTRL + * register.
+ * + * List of supported wakeup events -> Wakeup on:
+ * 1) Card interrupt
+ * 2) SD card insertion
+ * 3) SD card removal
+ */ +__STATIC_INLINE void XMC_SDMMC_DisableWakeupEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_DisableWakeupEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->WAKEUP_CTRL &= (uint8_t)~event; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param error A valid SDMMC ACMD error (::XMC_SDMMC_ACMD_ERR_t) + * @return bool + * + * \parDescription:
+ * Get status of Auto CMD12 errors
+ * + * \par + * The function detects the presence of an Auto CMD12 error. A boolean is returned to + * indicate if an error is detected. + */ +__STATIC_INLINE bool XMC_SDMMC_GetACMDErrStatus(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_ACMD_ERR_t error) +{ + XMC_ASSERT("XMC_SDMMC_GetACMDErrStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_GetACMDErrStatus: Invalid ACMD response error", XMC_SDMMC_CHECK_ACMD_ERR(error)); + + return (bool)(sdmmc->ACMD_ERR_STATUS & (uint16_t)error); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param error A valid SDMMC ACMD error (::XMC_SDMMC_ACMD_ERR_t) or a valid combination + * of logically OR'd ACMD error events + * @return None + * + * \parDescription:
+ * Triggers Auto CMD12 error(s)
+ * + * \par + * This function triggers Auto CMD12 error(s) by setting appropriate bit-fields of the + * FORCE_EVENT_ACMD_ERR_STATUS register. + * + * \parRelated APIs:
+ * XMC_SDMMC_TriggerEvent() + */ +__STATIC_INLINE void XMC_SDMMC_TriggerACMDErr(XMC_SDMMC_t *const sdmmc, uint32_t error) +{ + XMC_ASSERT("XMC_SDMMC_TriggerACMDErr: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->FORCE_EVENT_ACMD_ERR_STATUS |= (uint16_t)error; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return uint32_t The value held in the SDMMC FIFO + * + * \parDescription:
+ * Use this function to read a single word (32 bits) from the SDMMC FIFO.
+ */ +__STATIC_INLINE uint32_t XMC_SDMMC_ReadFIFO(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_ReadFIFO: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (sdmmc->DATA_BUFFER); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param data Pointer to a data word (32 bits) that needs to be written to the FIFO + * @return None + * + * \parDescription:
+ * Use this function to write a single word (32 bits) to the SDMMC FIFO.
+ */ +__STATIC_INLINE void XMC_SDMMC_WriteFIFO(XMC_SDMMC_t *const sdmmc, uint32_t *data) +{ + XMC_ASSERT("XMC_SDMMC_WriteFIFO: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->DATA_BUFFER = *data; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Enable SDMMC bus power
+ * + * \par + * The function sets the SD_BUS_POWER bit-field in the POWER_CTRL register, enabling the + * bus power. It may be invoked after enabling the SD clock (XMC_SDMMC_SDClockEnable()). + */ +__STATIC_INLINE void XMC_SDMMC_BusPowerOn(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_BusPowerOn: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->POWER_CTRL |= (uint8_t)(SDMMC_POWER_CTRL_SD_BUS_POWER_Msk); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Disable SDMMC bus power
+ * + * \par + * The function resets the SD_BUS_POWER bit-field in the POWER_CTRL register, disabling the + * bus power. + */ +__STATIC_INLINE void XMC_SDMMC_BusPowerOff(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_BusPowerOff: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->POWER_CTRL &= (uint8_t)~SDMMC_POWER_CTRL_SD_BUS_POWER_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Enable the internal SDMMC clock
+ * + * \par + * The function enables the internal clock of the SDMMC peripheral. To check if the + * clock is stable, use XMC_SDMMC_GetClockStability(). + * + * \parNote:
+ * Invoke XMC_SDMMC_Init() before using this function. + */ +__STATIC_INLINE void XMC_SDMMC_Start(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_Start: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + /* Enable internal clock */ + sdmmc->CLOCK_CTRL |= (uint16_t)SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool + * + * \parDescription:
+ * Check internal clock stability
+ * + * \par + * Use this function to check the internal SDMMC clock stability. The function returns a + * boolean value indicating internal clock stability (true = stable) + */ +__STATIC_INLINE bool XMC_SDMMC_GetClockStability(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetClockStability: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + /* Return clock stability */ + return (bool)(sdmmc->CLOCK_CTRL & SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Msk); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Disable internal SDMMC clock
+ * + * \par + * The function disables the internal clock of the SDMMC peripheral. The SDMMC registers + * can still be read and written even if the internal clock is disabled. + */ +__STATIC_INLINE void XMC_SDMMC_Stop(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_Stop: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->CLOCK_CTRL &= (uint16_t)~SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Enable the SD clock
+ * + * \par + * The function sets the SDCLOCK_EN bit-field of the CLOCK_CTRL register, enabling the + * SD clock. It can be invoked after the internal clock has achieved stability. SD card + * initialization process may then follow. + */ +__STATIC_INLINE void XMC_SDMMC_SDClockEnable(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_SDClockEnable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->CLOCK_CTRL |= (uint16_t)SDMMC_CLOCK_CTRL_SDCLOCK_EN_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return None + * + * \parDescription:
+ * Disable the SD clock
+ * + * \par + * The function resets the SDCLOCK_EN bit-field of the CLOCK_CTRL register, disabling the + * SD clock. It can be used alongside a SD card information reset routine (if required). + */ +__STATIC_INLINE void XMC_SDMMC_SDClockDisable(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_SDClockDisable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->CLOCK_CTRL &= (uint16_t)~SDMMC_CLOCK_CTRL_SDCLOCK_EN_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param reset_mode Reset mode or a bitwise combination of modes + * @return None + * + * \parDescription:
+ * Set SDMMC software reset request
+ * + * \par + * The function sets in the SDMMC SW_RESET register:
+ * 1) bit 0 to reset all
+ * 2) bit 1 to reset CMD line
+ * 3) bit 2 reset DAT line
+ * + * It is typically used to reset the SD HOST controller's registers. + */ +__STATIC_INLINE void XMC_SDMMC_SetSWReset(XMC_SDMMC_t *const sdmmc, uint32_t reset_mode) +{ + XMC_ASSERT("XMC_SDMMC_SetSWReset: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->SW_RESET |= (uint8_t)reset_mode; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return Software reset status + * + * \parDescription:
+ * Get SDMMC software reset status
+ * + * \par + * The SD host takes some time to reset its registers after invoking XMC_SDMMC_SetSWReset(). + * Since XMC_SDMMC_SetSWReset() is a non-blocking function, XMC_SDMMC_GetSWResetStatus() has + * been provided to check the software reset status. The return value needs to be masked + * with the reset mode (XMC_SDMMC_SW_RESET_t) to get a specific software reset status value. + */ +__STATIC_INLINE uint32_t XMC_SDMMC_GetSWResetStatus(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetSWResetStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (uint32_t)(sdmmc->SW_RESET); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return XMC_SDMMC_PRESENT_STATE_t A structure storing the present state of the host controller + * + * \parDescription:
+ * Get the present state of the SDMMC host controller
+ * + * \par + * Get the values of each bit-field in SDMMC_PRESENT_STATE register + * The function call populates an instance of the XMC_SDMMC_PRESENT_STATE_t structure with + * the state of the SD host controller and returns it to the caller. + */ +__STATIC_INLINE XMC_SDMMC_PRESENT_STATE_t XMC_SDMMC_GetPresentState(const XMC_SDMMC_t *const sdmmc) +{ + XMC_SDMMC_PRESENT_STATE_t result; + + XMC_ASSERT("XMC_SDMMC_GetPresentState: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + result.b32 = (uint32_t)sdmmc->PRESENT_STATE; + + return result; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool SDMMC command line status + * + * \parDescription:
+ * Check if the command line is busy
+ * + * \par + * The function reads the SDMMC PRESENT_STATE register and returns "true" if the command + * line is busy ("false" otherwise). The command line must be free before sending an SDMMC + * command with XMC_SDMMC_SendCommand(). + */ +__STATIC_INLINE bool XMC_SDMMC_IsCommandLineBusy(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_IsCommandLineBusy: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (bool)(sdmmc->PRESENT_STATE & SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Msk); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool SDMMC data line status + * + * \parDescription:
+ * Check if the data line is busy
+ * + * \par + * The function reads the SDMMC PRESENT_STATE register and returns "true" if the data + * line is busy ("false" otherwise). The data line must be free before sending an SDMMC + * command with XMC_SDMMC_SendCommand(). + */ +__STATIC_INLINE bool XMC_SDMMC_IsDataLineBusy(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_IsDataLineBusy: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (bool)(sdmmc->PRESENT_STATE & SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Msk); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool Status of all data lines + * + * \parDescription:
+ * Check if all data line are high
+ * + * \par + * The function reads the SDMMC PRESENT_STATE register and returns "true" if all data + * lines are high. It can be used to handle SDMMC error conditions. For example, if an + * error event (XMC_SDMMC_IsAnyErrorEvent()) is detected and all data lines are high, + * the user code can conclude that the error is of a "recoverable" type. + */ +__STATIC_INLINE bool XMC_SDMMC_IsAllDataLinesHigh(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_IsAllDataLinesHigh: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return ((((sdmmc->PRESENT_STATE & SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Msk) >> + SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos) == 0x0FU) ? true : false); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param command A pointer to a constant of type XMC_SDMMC_COMMAND_t, pointing to the command configuration + * @param arg Command argument + * @return ::XMC_SDMMC_STATUS_SUCCESS + * + * \parDescription:
+ * Send normal SDMMC command
+ * + * \par + * Use this function to send a normal SDMMC command. This non-blocking function sets the + * ARGUMENT1 and COMMAND registers. It is the user's responsibility to check if the command + * and data lines are busy (XMC_SDMMC_IsDataLineBusy(), XMC_SDMMC_IsCommandLineBusy()). + */ +XMC_SDMMC_STATUS_t XMC_SDMMC_SendCommand(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_COMMAND_t *command, uint32_t arg); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return uint32_t SDMMC command response + * + * \parDescription:
+ * Get card response (no Auto command)
+ * + * \par + * This function returns [39:8] bits of the card response. The others are checked automatically + * by the peripheral. This function can be used with response type R1, R1b, R3, R4, R5, R5b, R6 + * but it doesn't support the retrieving of R1 of Auto CMD 23 and R1b of Auto CMD 12. To get + * these responses, use XMC_SDMMC_GetAutoCommandResponse(). + */ +__STATIC_INLINE uint32_t XMC_SDMMC_GetCommandResponse(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetCommandResponse: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (sdmmc->RESPONSE[0]); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return uint32_t Auto command response value + * + * \parDescription:
+ * Get card response of Auto commands
+ * + * \par + * This function returns card response [39:8] bits of auto commands: R1 of Auto CMD 23 and + * R1b of Auto CMD 12. + */ +__STATIC_INLINE uint32_t XMC_SDMMC_GetAutoCommandResponse(const XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetAutoCommandResponse: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (sdmmc->RESPONSE[3]); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param response Pointer to structure type XMC_SDMMC_RESPONSE_t to store the full response + * @return None + * + * \parDescription:
+ * Get card R2 response
+ * + * \par + * The R2 response is 120 bits wide. The function reads all peripheral registers and store in + * the response data structure. + */ +void XMC_SDMMC_GetR2Response(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_RESPONSE_t *const response); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param transfer_mode Transfer mode configuration + * @return None + * + * \parDescription:
+ * Configure data transfer mode
+ * + * \par + * The function configures block size, block count, type of data transfer, response type + * and sets the auto command configuration. Use this function to configure a multi-block + * SDMMC transfer. + */ +void XMC_SDMMC_SetDataTransferMode(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_TRANSFER_MODE_t *const transfer_mode); + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return uint32_t Number of blocks that need to be transferred + * + * \parDescription:
+ * Get the number of blocks that need to be transferred
+ * + * \par + * This function is valid only for multiple block transfers. The host controller + * decrements the block count after each block transfer and stops when the count reaches + * zero. It can only be accessed when no transaction is happening (i.e after a transaction + * has stopped). This function returns an invalid value during the transfer.
+ * + * When saving transfer context as a result of the suspend command, the number of blocks + * yet to be transferred can be determined by using this function. + */ +__STATIC_INLINE uint32_t XMC_SDMMC_GetTransferBlocksNum(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetTransferBlocksNum: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (uint32_t)(sdmmc->BLOCK_COUNT); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param enabled "true" to enable read wait control, "false" to disable read wait control. + * @return None + * + * \parDescription:
+ * Configure read wait control
+ * + * \par + * The read wait function is optional for SDIO cards. If the card supports read wait and + * XMC_SDMMC_GetTransferBlocksNum() is executed, the SDMMC peripheral will stop read data + * using DAT[2] line. If this feature is not enabled the peripheral has to stop the SD + * clock to hold read data, restricting commands generation.
+ * + * When the host driver detects an SD card insertion, it sets this bit according to the + * CCCR of the SDIO card. If the card does not support read wait, this feature shall + * never be enabled otherwise a DAT line conflict may occur. If this feature is disabled, + * Suspend/Resume cannot be supported. + */ +__STATIC_INLINE void XMC_SDMMC_SetReadWaitControl(XMC_SDMMC_t *const sdmmc, bool enabled) +{ + XMC_ASSERT("XMC_SDMMC_SetReadWaitControl: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->BLOCK_GAP_CTRL = (uint8_t)((sdmmc->BLOCK_GAP_CTRL & (uint8_t)~SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Msk) | + (uint8_t)((uint8_t)enabled << SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param enabled "true" to set stop at block gap, "false" for transfer + * @return None + * + * \parDescription:
+ * Stop at block gap request
+ * + * \par + * The function is used to terminate a transaction execution at the next block gap for + * non-DMA transfers. + */ +__STATIC_INLINE void XMC_SDMMC_SetStopAtBlockGap(XMC_SDMMC_t *const sdmmc, bool enabled) +{ + XMC_ASSERT("XMC_SDMMC_SetStopAtBlockGap: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->BLOCK_GAP_CTRL = (uint8_t)((sdmmc->BLOCK_GAP_CTRL & (uint8_t)~SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Msk) | + (uint8_t)((uint8_t)enabled << SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param enabled "true" to restart transaction, "false" is ignored + * @return None + * + * \parDescription:
+ * Issue a continue request
+ * + * \par + * The function is used to restart a transaction which was stopped using the "Stop at + * block gap" request. (XMC_SDMMC_SetStopAtBlockGap()) + */ +__STATIC_INLINE void XMC_SDMMC_SetContinueRequest(XMC_SDMMC_t *const sdmmc, bool enabled) +{ + XMC_ASSERT("XMC_SDMMC_SetContinueRequest: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->BLOCK_GAP_CTRL = ((sdmmc->BLOCK_GAP_CTRL & (uint8_t)~SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Msk) | + (uint8_t)((uint8_t)enabled << SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @return bool + * + * \parDescription:
+ * Get continue request
+ * + * \par + * The function returns the status of the BLOCK_GAP_CTRL.CONTINUE_REQ bit-field. It + * returns "true" if the transaction is restarted after a "stop at block gap" request. + */ +__STATIC_INLINE bool XMC_SDMMC_GetContinueRequest(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetContinueRequest: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (bool)(sdmmc->BLOCK_GAP_CTRL & (uint8_t)(1U << SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param config A pointer to the SDMMC configuration structure (::XMC_SDMMC_CONFIG_t) + * @return None + * + * \parDescription:
+ * Enable interrupt at block gap
+ * + * \par + * The function sets the BLOCK_GAP_CTRL.INT_AT_BLOCK_GAP bit-field to enable interrupt + * at block gap for a multi-block transfer. This bit is only valid in a 4-bit mode of + * the SDIO card. + */ +__STATIC_INLINE void XMC_SDMMC_EnableInterruptAtBlockGap(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_CONFIG_t *config) +{ + XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: This operation is only valid in 4-bit mode", + (config->bus_width == XMC_SDMMC_DATA_LINES_1)); + + sdmmc->BLOCK_GAP_CTRL |= (uint8_t)SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param config A pointer to the SDMMC configuration structure (::XMC_SDMMC_CONFIG_t) + * @return None + * + * \parDescription:
+ * Disable interrupt at block gap
+ * + * \par + * The function resets the BLOCK_GAP_CTRL.INT_AT_BLOCK_GAP bit-field to disable interrupt + * at block gap. This bit is only valid in a 4-bit mode of the SDIO card. + */ +__STATIC_INLINE void XMC_SDMMC_DisableInterruptAtBlockGap(XMC_SDMMC_t *const sdmmc, + const XMC_SDMMC_CONFIG_t *config) + +{ + XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: This operation is only valid in 4-bit mode", + (config->bus_width == XMC_SDMMC_DATA_LINES_1)); + + sdmmc->BLOCK_GAP_CTRL &= (uint8_t)~SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param clk Desired clock frequency (::XMC_SDMMC_SDCLK_FREQ_SEL_t) + * @return None + * + * \parDescription:
+ * Set SD clock frequency
+ * + * \par + * The function sets the CLOCK_CTRL register to configure the frequency of the SD clock + * pin. The register is programmed with the divisor of the base clock frequency (clk). + * + * The following settings are permitted (8-bit divided clock mode):
+ * 00H: base clock (10MHz->63MHz)
+ * 01H: base clock divided by 2
+ * 10H: base clock divided by 32
+ * 02H: base clock divided by 4
+ * 04H: base clock divided by 8
+ * 08H: base clock divided by 16
+ * 20H: base clock divided by 64
+ * 40H: base clock divided by 128
+ * 80H: base clock divided by 256
+ * + * \parNote:
+ * The internal clock should be disabled before updating frequency clock select. Please + * see section 2.2.14 -> "Clock Control Register" in the SD HOST specification for more + * information. + */ +__STATIC_INLINE void XMC_SDMMC_SDClockFreqSelect(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_SDCLK_FREQ_SEL_t clk) +{ + XMC_ASSERT("XMC_SDMMC_SDClockFreqSelect: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SDClockFreqSelect: Invalid clock frequency selection", XMC_SDMMC_CHECK_SDCLK_FREQ(clk)); + + sdmmc->CLOCK_CTRL = (uint16_t)((sdmmc->CLOCK_CTRL & (uint32_t)~SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Msk) | + (uint32_t)(clk << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param bus_voltage Desired bus voltage (::XMC_SDMMC_BUS_VOLTAGE_t) + * @return None + * + * \parDescription:
+ * Set SDMMC bus voltage
+ * + * \par + * The function sets the CLOCK_CTRL register to configure the bus voltage. Currently, + * 3.3 volts is the supported voltage level. This function is relevant within the host + * controller initialization routine. + */ +__STATIC_INLINE void XMC_SDMMC_SetBusVoltage(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_BUS_VOLTAGE_t bus_voltage) +{ + XMC_ASSERT("XMC_SDMMC_SetBusVoltage: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetBusVoltage: Invalid bus voltage", XMC_SDMMC_CHECK_BUS_VOLTAGE(bus_voltage)); + + sdmmc->POWER_CTRL = (uint8_t)((sdmmc->POWER_CTRL & (uint32_t)~SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Msk) | + (uint32_t)(bus_voltage << SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param timeout Data line timeout value + * @return None + * + * \parDescription:
+ * Set data line timeout
+ * + * \par + * Use the function to set the interval by which the data line timeouts are detected. The + * timeout clock frequency is generated by dividing the SD clock (TMCLK) by the timeout argument. + * This function must be called before setting the bus voltage (XMC_SDMMC_SetBusVoltage()). + */ +__STATIC_INLINE void XMC_SDMMC_SetDataLineTimeout(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_DAT_TIMEOUT_COUNTER_t timeout) +{ + XMC_ASSERT("XMC_SDMMC_SetDataLineTimeout: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetDataLineTimeout: Invalid timeout", XMC_SDMMC_CHECK_DAT_TIMEOUT_COUNTER(timeout)); + + sdmmc->TIMEOUT_CTRL = (uint8_t)((sdmmc->TIMEOUT_CTRL & (uint32_t)~SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Msk) | + (uint32_t)(timeout << SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos)); +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param lines Number of data lines to use (::XMC_SDMMC_DATA_LINES_t) + * @return None + * + * \parDescription:
+ * Set data transfer width
+ * + * \par + * Use the function to set the data transfer width. Before using this function, an ACMD6 + * command (with R1 response type) must be sent to switch the bus width. + */ +__STATIC_INLINE void XMC_SDMMC_SetDataTransferWidth(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_DATA_LINES_t lines) +{ + XMC_ASSERT("XMC_SDMMC_SetDataTransferWidth: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetDataTransferWidth: Invalid no. of data lines", XMC_SDMMC_CHECK_DATA_LINES(lines)); + + sdmmc->HOST_CTRL &= (uint8_t)~(XMC_SDMMC_DATA_LINES_1 | XMC_SDMMC_DATA_LINES_4 | XMC_SDMMC_DATA_LINES_8); + sdmmc->HOST_CTRL |= (uint8_t)lines; +} + +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param dir Transfer direction (::XMC_SDMMC_DATA_TRANSFER_DIR_t) + * @return None + * + * \parDescription:
+ * Set data transfer direction
+ * + * \par + * Use the function to set the data transfer direction: host to card OR card to host. It + * is typically used to configure block operations (read/write) on the SD card. For + * example, XMC_SDMMC_DATA_TRANSFER_HOST_TO_CARD must be used for a write block operation. + */ +__STATIC_INLINE void XMC_SDMMC_SetDataTransferDirection(XMC_SDMMC_t *const sdmmc, + XMC_SDMMC_DATA_TRANSFER_DIR_t dir) +{ + XMC_ASSERT("XMC_SDMMC_SetDataTransferDirection: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetDataTransferDirection: Invalid direction", XMC_SDMMC_CHECK_DATA_TRANSFER_DIR(dir)); + + sdmmc->TRANSFER_MODE = (uint16_t)((sdmmc->TRANSFER_MODE & (uint16_t)~SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Msk) | + (uint16_t)((uint16_t)dir << SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos)); +} + +/** + * @param None + * @return None + * + * \parDescription:
+ * Enable delay on the command/data out lines
+ * + * \par + * Use the function to enable delay on the command/data out lines. Invoke this function + * before selecting the number of delay elements. + */ +__STATIC_INLINE void XMC_SDMMC_EnableDelayCmdDatLines(void) +{ + SCU_GENERAL->SDMMCDEL |= (uint32_t)SCU_GENERAL_SDMMCDEL_TAPEN_Msk; +} + +/** + * @param None + * @return None + * + * \parDescription:
+ * Disable delay on the command/data out lines
+ * + * \par + * Use the function to disable delay on the command/data out lines. + */ +__STATIC_INLINE void XMC_SDMMC_DisableDelayCmdDatLines(void) +{ + SCU_GENERAL->SDMMCDEL &= (uint32_t)~SCU_GENERAL_SDMMCDEL_TAPEN_Msk; +} + +/** + * @param tapdel Number of delay elements to select + * @return None + * + * \parDescription:
+ * Set number of delay elements on the command/data out lines
+ * + * \par + * Use the function to set the number of delay elements on the command/data out lines. + * The function writes the delay value to the SDMMC delay control register (SDMMCDEL) + * within the realm of the SCU peripheral. A delay of tapdel + 1 is considered as the + * final selected number of delay elements. + */ +__STATIC_INLINE void XMC_SDMMC_SetDelay(uint8_t tapdel) +{ + SCU_GENERAL->SDMMCDEL = (uint32_t)((SCU_GENERAL->SDMMCDEL & (uint32_t)~SCU_GENERAL_SDMMCDEL_TAPDEL_Msk) | + (uint32_t)(tapdel << SCU_GENERAL_SDMMCDEL_TAPDEL_Pos)); +} + +/** + * @param None + * @return None + * + * \parDescription:
+ * High speed enable
+ * + * \par + * Use the function to enable high speed operation. The default is a normal speed operation. + * Once enabled, the host controller outputs command and data lines at the rising edge of the + * SD clock (up to 50 MHz for SD). + */ +__STATIC_INLINE void XMC_SDMMC_EnableHighSpeed(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_EnableHighSpeed: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->HOST_CTRL |= (uint8_t)SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk; +} + +/** + * @param None + * @return None + * + * \parDescription:
+ * High speed disable
+ * + * \par + * Use the function to disable high speed operation. The host controller will switch back + * to a normal speed mode. In this mode, the host controller outputs command and data lines + * at 25 MHz for SD. + */ +__STATIC_INLINE void XMC_SDMMC_DisableHighSpeed(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_DisableHighSpeed: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->HOST_CTRL &= (uint8_t)~SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* #if defined (SDMMC) */ + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_spi.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_spi.h new file mode 100644 index 00000000..ec1de7e8 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_spi.h @@ -0,0 +1,1279 @@ +/** + * @file xmc_spi.h + * @date 2016-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial + * + * 2015-05-20: + * - Documentation improved
+ * - Added XMC_SPI_CH_SetSlaveSelectDelay(), XMC_SPI_CH_TriggerServiceRequest() and + * XMC_SPI_CH_SelectInterruptNodePointer()
+ * - Added XMC_SPI_CH_SetInterwordDelaySCLK()
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-08-24: + * - Added APIs for enabling/disabling delay compensation XMC_SPI_CH_DisableDelayCompensation() and + * XMC_SPI_CH_EnableDelayCompensation()
+ * + * 2015-08-27: + * - Added APIs for external input for BRG configuration:XMC_SPI_CH_ConfigExternalInputSignalToBRG()
+ * + * 2015-09-01: + * - Modified XMC_SPI_CH_SetInputSource() for avoiding complete DXCR register overwriting.
+ * - Modified XMC_SPI_CH_EVENT_t enum for supporting XMC_SPI_CH_EnableEvent() and XMC_SPI_CH_DisableEvent() + * for supporting multiple events configuration
+ * + * 2015-09-08: + * - Adding API for configuring the receiving clock phase in the slave:XMC_SPI_CH_DataLatchedInTrailingEdge() and XMC_SPI_CH_DataLatchedInLeadingEdge()
+ * + * 2016-04-10: + * - Added an API for configuring the transmit mode:XMC_SPI_CH_SetTransmitMode()
+ * + * 2016-05-20: + * - Added XMC_SPI_CH_EnableDataTransmission() and XMC_SPI_CH_DisableDataTransmission() + * + * @endcond + * + */ + +#ifndef XMC_SPI_H +#define XMC_SPI_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ +#include "xmc_usic.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup SPI + * @brief Synchronous serial channel driver for SPI-like communication. + * + * The SPI driver uses Universal Serial Interface Channel(USIC) module. + * The USIC module supports multiple data lines for SPI communication. \n + * -# Full duplex communication with 2 separate lines for transmission and reception. + * -# Half duplex communication with 1 common line shared for transmission and reception. + * -# Dual mode communication with 2 common lines shared for transmission and reception. + * -# Quad mode communication with 4 common lines shared for transmission and reception.

+ * + * SPI driver provides structures, enumerations and APIs for configuring the USIC channel for SPI communication + * and also for data transaction.
+ * SPI driver features: + * -# Configuration structure XMC_SPI_CH_CONFIG_t and SPI initialization function XMC_SPI_CH_Init() + * -# Allows configuration of protocol word and frame length using XMC_SPI_CH_SetWordLength(), XMC_SPI_CH_SetFrameLength() + * -# Allows manipulation of data frame at runtime using XMC_SPI_CH_EnableSOF(), XMC_SPI_CH_EnableEOF(), + XMC_SPI_CH_EnableSlaveSelect(), XMC_SPI_CH_DisableSlaveSelect() + * -# Provides APIs for transmitting data and receiving data using XMC_SPI_CH_Transmit(), XMC_SPI_CH_Receive(), XMC_SPI_CH_GetReceivedData() + * -# Allows configuration of shift clock using XMC_SPI_CH_ConfigureShiftClockOutput() + * -# Provides enumeration of SPI protocol events using @ref XMC_SPI_CH_STATUS_FLAG_t + * @{ + */ + +/*********************************************************************************************************************** + * MACROS + **********************************************************************************************************************/ + +#if defined(USIC0) +#define XMC_SPI0_CH0 XMC_USIC0_CH0 /**< SPI0 channel 0 base address */ +#define XMC_SPI0_CH1 XMC_USIC0_CH1 /**< SPI0 channel 1 base address */ +#endif + +#if defined(USIC1) +#define XMC_SPI1_CH0 XMC_USIC1_CH0 /**< SPI1 channel 0 base address */ +#define XMC_SPI1_CH1 XMC_USIC1_CH1 /**< SPI1 channel 1 base address */ +#endif + +#if defined(USIC2) +#define XMC_SPI2_CH0 XMC_USIC2_CH0 /**< SPI2 channel 0 base address */ +#define XMC_SPI2_CH1 XMC_USIC2_CH1 /**< SPI2 channel 1 base address */ +#endif + +/*********************************************************************************************************************** + * ENUMS + ***********************************************************************************************************************/ + +/** + * Defines return status of SPI driver APIs + */ +typedef enum XMC_SPI_CH_STATUS +{ + XMC_SPI_CH_STATUS_OK, /**< Status of the Module: OK */ + XMC_SPI_CH_STATUS_ERROR, /**< Status of the Module: ERROR */ + XMC_SPI_CH_STATUS_BUSY /**< The Module is busy */ +} XMC_SPI_CH_STATUS_t; +/** + * Defines the SPI bus mode + */ +typedef enum XMC_SPI_CH_BUS_MODE +{ + XMC_SPI_CH_BUS_MODE_MASTER, /**< SPI Master */ + XMC_SPI_CH_BUS_MODE_SLAVE /**< SPI Slave */ +} XMC_SPI_CH_BUS_MODE_t; + +/** + * Defines the Polarity of the slave select signals SELO[7:0] in relation to the master slave select signal MSLS. + */ +typedef enum XMC_SPI_CH_SLAVE_SEL_MSLS_INV +{ + XMC_SPI_CH_SLAVE_SEL_SAME_AS_MSLS = 0x0UL, /**< The SELO outputs have the same polarity as the MSLS signal + (active high) */ + XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS = 0x1UL << USIC_CH_PCR_SSCMode_SELINV_Pos /**< The SELO outputs have the inverted + polarity to the MSLS signal + (active low)*/ +} XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t; + +/** + * Defines the Polarity of the data inputs. + */ +typedef enum XMC_SPI_CH_DATA_POLARITY +{ + XMC_SPI_CH_DATA_POLARITY_DIRECT = 0x0UL, /**< The polarity of the data line is not inverted */ + XMC_SPI_CH_DATA_POLARITY_INVERT = 0x1UL << USIC_CH_DX2CR_DPOL_Pos /**< The polarity of the data line is inverted */ +} XMC_SPI_CH_DATA_POLARITY_t; + +/** + * Defines Slave Select lines + */ +typedef enum XMC_SPI_CH_SLAVE_SELECT +{ + XMC_SPI_CH_SLAVE_SELECT_0 = 1UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 0 */ + XMC_SPI_CH_SLAVE_SELECT_1 = 2UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 1 */ + XMC_SPI_CH_SLAVE_SELECT_2 = 4UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 2 */ + XMC_SPI_CH_SLAVE_SELECT_3 = 8UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 3 */ + XMC_SPI_CH_SLAVE_SELECT_4 = 16UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 4 */ + XMC_SPI_CH_SLAVE_SELECT_5 = 32UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 5 */ + XMC_SPI_CH_SLAVE_SELECT_6 = 64UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select line 6 */ + XMC_SPI_CH_SLAVE_SELECT_7 = 128UL << USIC_CH_PCR_SSCMode_SELO_Pos /**< Slave Select line 7 */ +} XMC_SPI_CH_SLAVE_SELECT_t; + +/** + * Defines SPI specific events + */ +typedef enum XMC_SPI_CH_EVENT +{ + XMC_SPI_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */ + XMC_SPI_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */ + XMC_SPI_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */ + XMC_SPI_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */ + XMC_SPI_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */ + XMC_SPI_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */ + XMC_SPI_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */ + + XMC_SPI_CH_EVENT_PARITY_ERROR = USIC_CH_PCR_SSCMode_PARIEN_Msk >> 13U, /**< Parity error event */ + XMC_SPI_CH_EVENT_MSLS_CHANGE = USIC_CH_PCR_SSCMode_MSLSIEN_Msk >> 13U, /**< Master slave select(MSLS) output transition event*/ + XMC_SPI_CH_EVENT_DX2TIEN_ACTIVATED = USIC_CH_PCR_SSCMode_DX2TIEN_Msk >> 13U /**< Slave select input signal transition event*/ +} XMC_SPI_CH_EVENT_t; + +/** + * Defines SPI event status + */ +typedef enum XMC_SPI_CH_STATUS_FLAG +{ + XMC_SPI_CH_STATUS_FLAG_MSLS = USIC_CH_PSR_SSCMode_MSLS_Msk, /**< Status of Master slave + select(MSLS) signal */ + XMC_SPI_CH_STATUS_FLAG_DX2S = USIC_CH_PSR_SSCMode_DX2S_Msk, /**< Status of slave select + input(DX2) signal*/ + XMC_SPI_CH_STATUS_FLAG_MSLS_EVENT_DETECTED = USIC_CH_PSR_SSCMode_MSLSEV_Msk, /**< Status for master slave select + output signal transition*/ + XMC_SPI_CH_STATUS_FLAG_DX2T_EVENT_DETECTED = USIC_CH_PSR_SSCMode_DX2TEV_Msk, /**< Status for slave select + input signal transition */ + XMC_SPI_CH_STATUS_FLAG_PARITY_ERROR_EVENT_DETECTED = USIC_CH_PSR_SSCMode_PARERR_Msk, /**< Indicates status of the + parity error */ + XMC_SPI_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_SSCMode_RSIF_Msk, /**< Status for receive start + event */ + XMC_SPI_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_SSCMode_DLIF_Msk, /**< Status for data lost event*/ + XMC_SPI_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_SSCMode_TSIF_Msk, /**< Status for transmit shift + event */ + XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_SSCMode_TBIF_Msk, /**< Status for transmit buffer + event */ + XMC_SPI_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_SSCMode_RIF_Msk, /**< Status for receive event */ + XMC_SPI_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_SSCMode_AIF_Msk, /**< Status for alternative + receive event */ + XMC_SPI_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_SSCMode_BRGIF_Msk/**< Status for baud rate + generation error event */ +} XMC_SPI_CH_STATUS_FLAG_t; + +/** + * Defines input frequency sources for slave select signal delay configuration. + */ +typedef enum XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY +{ + XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPDIV = 0x0UL, /**< Output of PDIV divider: FPDIV */ + XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPPP = 0x1UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos, /**< Peripheral clock: FPPP */ + XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FSCLK = 0x2UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos, /**< Shift clock: FSCLK */ + XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FMCLK = 0x3UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos /**< Master clock: FMCLK */ +} XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_t; + +/** + * Define data and clock input stages + */ +typedef enum XMC_SPI_CH_INPUT +{ + XMC_SPI_CH_INPUT_DIN0 = 0UL, /**< Data input stage 0 */ + XMC_SPI_CH_INPUT_SLAVE_SCLKIN = 1UL, /**< Clock input stage */ + XMC_SPI_CH_INPUT_SLAVE_SELIN = 2UL, /**< Slave select input stage */ + XMC_SPI_CH_INPUT_DIN1 = 3UL, /**< Data input stage 1 */ + XMC_SPI_CH_INPUT_DIN2 = 4UL, /**< Data input stage 2 */ + XMC_SPI_CH_INPUT_DIN3 = 5UL /**< Data input stage 3 */ +} XMC_SPI_CH_INPUT_t; + +/** + * Define SPI data transfer mode + */ +typedef enum XMC_SPI_CH_MODE +{ + XMC_SPI_CH_MODE_STANDARD = 0UL, /**< SPI standard full duplex mode */ + XMC_SPI_CH_MODE_STANDARD_HALFDUPLEX = 4UL, /**< SPI standard half duplex mode */ + XMC_SPI_CH_MODE_DUAL= 6UL, /**< SPI half duplex mode with dual data lines */ + XMC_SPI_CH_MODE_QUAD= 7UL /**< SPI half duplex mode with quad data lines */ +} XMC_SPI_CH_MODE_t; + + +/** + * SPI Baudrate Generator shift clock passive level + */ +typedef enum XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL +{ + /**< Passive clock level 0, delay disabled */ + XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED, + /**< Passive clock level 1, delay disabled */ + XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED, + /**< Passive clock level 0, delay enabled */ + XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED, + /**< Passive clock level 1, delay enabled */ + XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED +} XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t; + +/** + * SPI Baudrate Generator shift clock output +*/ +typedef enum XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT +{ + XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK, /**< Baudrate Generator shift clock output: SCLK*/ + XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 /**< Clock obtained as input from master: DX1*/ +} XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t; + +/** + * SPI channel interrupt node pointers + */ +typedef enum XMC_SPI_CH_INTERRUPT_NODE_POINTER +{ + XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */ + XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */ + XMC_SPI_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */ + XMC_SPI_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */ + XMC_SPI_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */ +} XMC_SPI_CH_INTERRUPT_NODE_POINTER_t; + +/********************************************************************************************************************** + * DATA STRUCTURES +**********************************************************************************************************************/ + +/** + * Structure for initializing SPI channel. + */ +typedef struct XMC_SPI_CH_CONFIG +{ + uint32_t baudrate; /**< Module baud rate for communication */ + XMC_SPI_CH_BUS_MODE_t bus_mode; /**< Bus mode: Master/Slave */ + XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion; /**< Enable inversion of Slave select signal relative to the internal + MSLS signal */ + XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Enable parity check for transmit and received data */ +} XMC_SPI_CH_CONFIG_t; + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param config pointer to constant SPI channel configuration data structure.\n + * Refer data structure @ref XMC_SPI_CH_CONFIG_t for detail. + * + * @return None + * + * \parDescription:
+ * Initializes the selected SPI \a channel with the \a config structure.\n\n + * Enable SPI channel by calling XMC_USIC_CH_Enable() and then configures + *
    + *
  • Baudrate,
    • + *
  • Passive data level as active high,
    • + *
  • Shift control signal as active high,
    • + *
  • Frame length as 64U,
    • + *
  • Word length as 8U,
    • + *
  • Enable Hardware port control mode,
    • + *
  • Enable transmission of data TDV(Transmit data valid) bit is set to 1,
    • + *
  • Enable invalidation of data in TBUF once loaded into shift register,
    • + *
  • Parity mode settings
    • + *
+ * And if master mode is selected, + *
    + *
  • Enables MSLS signal generation,
    • + *
  • configures slave selection as normal mode,
    • + *
  • Set polarity for the Slave signal,
    • + *
  • Enable Frame end mode(MSLS signal is kept active after transmission of a frame)
    • + *
+ */ +void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the selected USIC channel to operate in SPI mode, by setting CCR.MODE bits.\n\n + * It should be executed after XMC_SPI_CH_Init() during initialization. By invoking XMC_SPI_CH_Stop(), the MODE is set + * to IDLE state. Call XMC_SPI_CH_Start() to set the SPI mode again, as needed later in the program. + * + * \parRelated APIs:
+ * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop() + */ +__STATIC_INLINE void XMC_SPI_CH_Start(XMC_USIC_CH_t *const channel) +{ + /* USIC channel in SPI mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_SPI); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for stopping is processed. \n + * XMC_SPI_CH_STATUS_OK- If the USIC channel is successfully put to IDLE mode. \n + * XMC_SPI_CH_STATUS_BUSY- If the USIC channel is busy transmitting data. + * + * \parDescription:
+ * Set the selected SPI channel to IDLE mode, by clearing CCR.MODE bits.\n\n + * After calling XMC_SPI_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_SPI_CH_Start() has to be + * invoked to start the communication again. + * + * \parRelated APIs:
+ * XMC_SPI_CH_Start() + */ +XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param rate Bus speed in bits per second + * + * @return XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for setting baudrate is processed. \n + * XMC_SPI_CH_STATUS_OK- If the baudrate is successfully changed. \n + * XMC_SPI_CH_STATUS_ERROR- If the new baudrate value is out of range. + * + * \parDescription:
+ * Sets the bus speed in bits per second + * + * \parRelated APIs:
+ * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop() + */ +XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param slave Slave select signal.\n + * Refer @ref XMC_SPI_CH_SLAVE_SELECT_t for valid values. + * + * @return None + * + * \parDescription:
+ * Enable the selected slave signal by setting PCR.SELO bits.\n\n + * Each slave is connected with one slave select signal. This is not configured in XMC_SPI_CH_Init(). Invoke + * XMC_SPI_CH_EnableSlaveSelect() with required \a slave to to start the communication. After finishing the + * communication XMC_SPI_CH_DisableSlaveSelect() can be invoked to disable the slaves. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableSlaveSelect() + */ +void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SELECT_t slave); + +/** + * @param channel A constant ponter to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Disable all the slave signals by clearing PCR.SELO bits.\n\n + * XMC_SPI_CH_EnableSlaveSelect() has to be invoked to start the communication with the desired slave again. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableSlaveSelect() + */ +void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated.\n + * Refer @ref XMC_SPI_CH_MODE_t for valid values. + * + * @return None + * + * \parDescription:
+ * In Dual and Quad modes, hardware port control(CCR.HPCEN) mode is enabled. \n\n + * By enabling this the direction of the data pin is updated by hardware itself. Before transmitting the data set the + * mode to ensure the proper communication. + * + * \parRelated APIs:
+ * XMC_SPI_CH_Transmit() + */ +__STATIC_INLINE void XMC_SPI_CH_SetTransmitMode(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_MODE_t mode) +{ + channel->CCR = (channel->CCR & (uint32_t)(~USIC_CH_CCR_HPCEN_Msk)) | + (((uint32_t) mode << USIC_CH_CCR_HPCEN_Pos) & (uint32_t)USIC_CH_CCR_HPCEN_Msk); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param data Data to be transmitted + * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated.\n + * Refer @ref XMC_SPI_CH_MODE_t for valid values. + * + * @return None + * + * \parDescription:
+ * Puts the data into FIFO, if FIFO mode is enabled or else into standard buffer, by setting the proper mode.\n\n + * In Dual and Quad modes, hardware port control(CCR.HPCEN) mode is enabled. By enabling this the direction of the data + * pin is updated by hardware itself. TCI(Transmit Control Information) allows dynamic control of both the data shift mode + * and pin direction during data transfers by writing to SCTR.DSM and SCTR.HPCDIR bit fields. To support this auto + * update, TCSR.HPCMD(Hardware Port control) will be enabled during the initialization using XMC_SPI_CH_Init() for all modes. + * + * + * \parRelated APIs:
+ * XMC_SPI_CH_Receive() + */ +void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_SPI_CH_MODE_t mode); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated.\n + * Refer @ref XMC_SPI_CH_MODE_t for valid values. + * + * @return None + * + * \parDescription:
+ * Transmits a dummy data(FFFFH) to provide clock for slave and receives the data from the slave.\n\n + * XMC_SPI_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data + * XMC_SPI_CH_GetReceivedData() can be invoked to read the data from the buffers. + * + * \parRelated APIs:
+ * XMC_SPI_CH_GetReceivedDaa() + */ +__STATIC_INLINE void XMC_SPI_CH_Receive(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_MODE_t mode) +{ + /* Transmit dummy data */ + XMC_SPI_CH_Transmit(channel, (uint16_t)0xffffU, (XMC_SPI_CH_MODE_t)((uint16_t)mode & 0xfffbU)); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return uint16_t Data read from the receive buffer. + * + * \parDescription:
+ * Reads data from the receive buffer based on the FIFO selection.\n\n + * Invocation of XMC_SPI_CH_Receive() receives the data and place it into receive buffer. After receiving the data + * XMC_SPI_CH_GetReceivedData() can be used to read the data from the buffer. + * + * \parRelated APIs:
+ * XMC_SPI_CH_Receive() + */ +uint16_t XMC_SPI_CH_GetReceivedData(XMC_USIC_CH_t *const channel); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the order of data transfer from LSB to MSB, by clearing SCTR.SDIR bit.\n\n + * This is typically based on the slave settings. Invoke XMC_SPI_CH_SetBitOrderLsbFirst() to set direction as needed in + * the program. + * + * \parRelated APIs:
+ * XMC_SPI_CH_SetBitOrderMsbFirst() + */ +__STATIC_INLINE void XMC_SPI_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t *const channel) +{ + channel->SCTR &= (uint32_t)~USIC_CH_SCTR_SDIR_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.\n\n + * This is typically based on the slave settings. This is not set during XMC_SPI_CH_Init(). + * Invoke XMC_SPI_CH_SetBitOrderMsbFirst() to set direction as needed in the program. + * + * \parRelated APIs:
+ * XMC_SPI_CH_SetBitOrderLsbFirst() + */ +__STATIC_INLINE void XMC_SPI_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t *const channel) +{ + channel->SCTR |= (uint32_t)USIC_CH_SCTR_SDIR_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param event Protocol events which have to be enabled. + * Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations of these enum items can be used + * as input. + * + * @return None + * + * \parDescription:
+ * Enables the SPI protocol specific events, by configuring PCR register.\n\n + * Events can be enabled as needed using XMC_SPI_CH_EnableEvent(). + * XMC_SPI_CH_DisableEvent() can be used to disable the events. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableEvent() + */ +void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param event Protocol events which have to be disabled. + * Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations of these enum item can be used + * as input. + * + * @return None + * + * \parDescription:
+ * Disables the SPI protocol specific events, by configuring PCR register.\n\n + * After disabling the events, XMC_SPI_CH_EnableEvent() has to be invoked to re-enable the events. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableEvent() + */ +void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return uint32_t Status of SPI protocol events. + * + * \parDescription:
+ * Returns the status of the events, by reading PSR register.\n\n + * This indicates the status of the all the events, for SPI communication. + * + * \parRelated APIs:
+ * XMC_SPI_CH_ClearStatusFlag() + */ +__STATIC_INLINE uint32_t XMC_SPI_CH_GetStatusFlag(XMC_USIC_CH_t *const channel) +{ + return channel->PSR_SSCMode; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param flag Protocol event status to be cleared for detection of next occurence. + * Refer @ XMC_SPI_CH_STATUS_FLAG_t for valid values. OR combinations of these enum item can be used + * as input. + * @return None + * + * \parDescription:
+ * Clears the events specified, by setting PSCR register.\n\n + * During communication the events occurred have to be cleared to detect their next occurence.\n + * e.g: During transmission Transmit buffer event occurs to indicating data word transfer has started. This + * event has to be cleared after transmission of each data word. Otherwise next event cannot be recognized. + * + * \parRelated APIs:
+ * XMC_SPI_CH_GetStatusFlag() + */ +__STATIC_INLINE void XMC_SPI_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag) +{ + channel->PSCR |= flag; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Enables the generation of Master clock by setting PCR.MCLK bit.\n\n + * This clock can be used as a clock reference for external devices. This is not enabled during initialization in + * XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by + * XMC_SPI_CH_DisableMasterClock(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableMasterClock() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_MCLK_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Disables the generation of Master clock by clearing PCR.MCLK bit.\n\n + * This clock can be enabled by invoking XMC_SPI_CH_EnableMasterClock() as needed in the program. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableMasterClock() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_MCLK_Msk; +} +#ifdef USIC_CH_PCR_SSCMode_SLPHSEL_Msk +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DataLatchedInLeadingEdge() + */ +__STATIC_INLINE void XMC_SPI_CH_DataLatchedInTrailingEdge(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SLPHSEL_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 + * stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are + * always latched in with the leading edge. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DataLatchedInTrailingEdge() + */ +__STATIC_INLINE void XMC_SPI_CH_DataLatchedInLeadingEdge(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode |= USIC_CH_PCR_SSCMode_SLPHSEL_Msk; +} +#endif +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Enables the delay after each word, by setting PCR.TIWEN bit.\n\n + * The inter word delay starts at the end of last SCLK cycle of data word. During this time no clock pulses are + * generated and MSLS signal stays active. If inter word delay is not enabled, last data bit of a data word is directly + * followed by the first data bit of the next data word. This is not enabled in XMC_SPI_CH_Init(). To enable + * XMC_SPI_CH_EnableInterwordDelay() has to be invoked as needed in the program. And can be disabled by invoking + * XMC_SPI_CH_DisableInterwordDelay(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableInterwordDelay() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableInterwordDelay(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_TIWEN_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Disables the delay after after each word, by clearing PCR.TIWEN bit.\n\n + * So the last data bit of a data word is directly followed by the first data bit of the next data word. If needed can + * be enabled by invoking XMC_SPI_CH_EnableInterwordDelay(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableInterwordDelay() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableInterwordDelay(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_TIWEN_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param tinterword_delay_ns delay in terms of nano seconds. + * + * @return None + * + * \parDescription:
+ * Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields.\n\n + * The inter word delay is dependent on the peripheral clock. The maximum possible value is calculated by using the + * below formula\n + * Maximum inter word delay = ((1 + PCTQ1_max)(1 + DCTQ1_max)) / peripheral clock\n + * where PCTQ1_max = 3 and DCTQ1_max = 31\n + * After configuring the inter word delay, this has to be enabled by invoking XMC_SPI_CH_EnableInterwordDelay(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_SetInterwordDelaySCLK() + */ +void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterword_delay_ns); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param sclk_period in terms of clk cycles. + * + * @return None + * + * \parDescription:
+ * Configures the inter word delay by setting PCR.DCTQ1 bit fields.\n\n + * This delay is dependent on the peripheral clock. The maximum possible value supported by this API + * is 32 clock cycles. + * After configuring the inter word delay, this has to be enabled by invoking XMC_SPI_CH_EnableInterwordDelay(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_EnableInterwordDelay() + */ +__STATIC_INLINE void XMC_SPI_CH_SetInterwordDelaySCLK(XMC_USIC_CH_t *const channel,uint32_t sclk_period) +{ + channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode) & (~(USIC_CH_PCR_SSCMode_DCTQ1_Msk | + USIC_CH_PCR_SSCMode_PCTQ1_Msk | + USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) | + (((sclk_period - 1U) << USIC_CH_PCR_SSCMode_DCTQ1_Pos) | + (0x02U << USIC_CH_PCR_SSCMode_CTQSEL1_Pos)); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param sclk_period delay in terms of sclk clock cycles. + * + * @return None + * + * \parDescription:
+ * Configures the leading/trailing delay by setting BRG.DCTQ bit field.\n\n + * This delay is dependent on the peripheral clock. The maximum possible value supported by this API + * is 30 clock cycles. + * + */ +__STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectDelay(XMC_USIC_CH_t *const channel,uint32_t sclk_period) +{ + + channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk | + USIC_CH_BRG_PCTQ_Msk)) | + (((sclk_period - 1U) << USIC_CH_BRG_DCTQ_Pos) | (0x01U << USIC_CH_BRG_PCTQ_Pos)); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * + * Configure to keep MSLS(Slave select signal) active even after finishing the current data frame, + * by setting PCR.FEM bit.\n\n + * This is typically used during the transmission of multi-data word frames, where there is possibility of delay in + * delivering the data. Frame end mode is enabled in XMC_SPI_CH_Init() during initialization. To disable + * XMC_SPI_CH_DisableFEM() can be invoked as needed in the program. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableFEM() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableFEM(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_FEM_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
+ * Configure to disable the MSLS(Slave select signal) if the current data frame is considered as finished, + * by setting PCR.FEM bit.\n\n + * + * When the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data, is + * considered as frame is ended and MSLS(Slave select signal) is disabled. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableFEM() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableFEM(XMC_USIC_CH_t *const channel) +{ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_FEM_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param passive_level polarity and delay of the selected shift clock.\n + * Refer @ref XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t for valid inputs. + * @param clock_output shift clock source.\n + * Refer @ref XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t for valid inputs. + * + * @return None + * + * \parDescription:
+ * Configures the shift clock source with the selected polarity and delay by setting BRG.SCLKOSEL and BRG.SCLKCFG.\n\n + * In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available + * for external slave devices by SCLKOUT signal.\n + * In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.\n + * The shift clock output(SCLKOUT) signal polarity can be set relative to SCLK, with the delay of half the shift clock + * period. These settings are applicable only in master mode. + */ +__STATIC_INLINE void XMC_SPI_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level, + const XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) +{ + XMC_USIC_CH_ConfigureShiftClockOutput(channel, (XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t)passive_level, + (XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param word_length Number of bits to be configured for a data word. \n + * \b Range: 1 to 16. + * + * @return None + * + * \parDescription
+ * Defines the data word length.\n\n + * Sets the number of bits to represent a data word. Frame length should be a multiple of word length. + * + * \parRelated APIs:
+ * XMC_SPI_CH_SetFrameLength() + */ +__STATIC_INLINE void XMC_SPI_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length) +{ + XMC_USIC_CH_SetWordLength(channel, word_length); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param frame_length Number of bits in a frame. \n + * \b Range: 1 to 64. If the value 64 is configured, then the frame does not + * automatically end. User should explicitly end the frame. + * + * @return None + * + * \parDescription
+ * Define the data frame length.\n\n + * Set the number of bits to be serially transmitted in a frame. + * The frame length should be multiples of word length. If the value is set to 64, the frame does not + * automatically end. Use XMC_SPI_CH_DisableSlaveSelect() to end the frame after all the data + * is transmitted. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetWordLength(), XMC_USIC_CH_EnableFrameLengthControl(), XMC_SPI_CH_DisableSlaveSelect() + */ +__STATIC_INLINE void XMC_SPI_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length) +{ + XMC_USIC_CH_SetFrameLength(channel, frame_length); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * Configure the handling of start of frame through software, by setting TCSR.SOF bit.\n\n + * This can be used if the software handles the TBUF data without FIFO. If SOF is set, a valid content of the TBUF is + * considered as first word of a new frame by finishing the currently running frame. For software handling of SOF bit, + * it is recommended to configure TCSR.WLEMD as 0. This is not configured during initialization. XMC_SPI_CH_EnableSOF() + * can be called as needed in the program and can be disabled by XMC_SPI_CH_DisableSOF(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableSOF() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableSOF(XMC_USIC_CH_t *const channel) +{ + channel->TCSR |= (uint32_t)USIC_CH_TCSR_SOF_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * Set the control of the handling start of frame through hardware, by clearing TCSR.SOF bit.\n\n + * Typically this can be disabled, where the transmission control is done by the hardware. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableSOF() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableSOF(XMC_USIC_CH_t *const channel) +{ + channel->TCSR &= (uint32_t)~USIC_CH_TCSR_SOF_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * Configure the handling of end of frame through software, by setting TCSR.EOF bit.\n\n + * This can be used if the software handles the TBUF data without FIFO. If EOF is set, a valid content of the TBUF is + * considered as last word of a frame. After transfer of the last word, MSLS signal becomes inactive. For software + * handling of EOF bit, it is recommended to configure TCSR.WLEMD as 0. \n + * \b Note: The API should be called before putting the last data word of the frame to TBUF. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableEOF() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableEOF(XMC_USIC_CH_t *const channel) +{ + channel->TCSR |= (uint32_t)USIC_CH_TCSR_EOF_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * Configure the handling of end of frame through hardware, by clearing TCSR.EOF bit.\n\n + * Typically this can be disabled, where the transmission control is done by the hardware. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableEOF() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableEOF(XMC_USIC_CH_t *const channel) +{ + channel->TCSR &= (uint32_t)~USIC_CH_TCSR_EOF_Msk; +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input SPI channel input stage.\n + * Refer @ref XMC_SPI_CH_INPUT_t for valid values + * @param source Input source select for the input stage. + * Range : [0 to 7] + * + * @return None + * + * \parDescription
+ * Selects the data source for SPI input stage, by configuring DXCR.DSEL bits.\n\n + * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the + * input stages like DX0CR, DX1CR etc. This is not done during initialization. This has to be configured before starting + * the SPI communication. + */ +__STATIC_INLINE void XMC_SPI_CH_SetInputSource(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_INPUT_t input, + const uint8_t source) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_DSEN_Msk)) | USIC_CH_DX0CR_INSW_Msk; + XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param selo_inversion Polarity of the slave select signal relative to the MSLS signal.\n + * Refer @ref XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t for valid values + * + * @return None + * + * \parDescription
+ * Set the polarity of the slave select signal, by configuring PCR.SELINV bit.\n\n + * Normally MSLS signal is active low level signal. SO based on the slave inversion has to be applied. This is configured + * in XMC_SPI_CH_Init() during initialization. Invoke XMC_SPI_CH_SetSlaveSelectPolarity() with desired settings as + * needed later in the program. + */ +__STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectPolarity(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion) +{ + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode & (~USIC_CH_PCR_SSCMode_SELINV_Msk)) | (uint32_t)selo_inversion); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input SPI channel input stage.\n + * Refer @ref XMC_SPI_CH_INPUT_t for valid inputs. + * + * @return None + * + * \parDescription
+ * Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y = \a input).\n\n + * This is not set in XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableInputInversion() as needed later in the program. To + * disable the inversion XMC_SPI_CH_DisableInputInversion() can be invoked. + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableInputInversion() + */ +__STATIC_INLINE void XMC_SPI_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_INPUT_t input) +{ + XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param input SPI channel input stage.\n + * Refer @ref XMC_SPI_CH_INPUT_t for valid inputs. + * + * @return None + * + * \parDescription
+ * Disables the polarity inversion of input data signal, by clearing DXyCR.DPOL(where y = \a input).\n\n + * Resets the input data polarity. Invoke XMC_SPI_CH_EnableInputInversion() to apply inversion. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableInputInversion() + */ +__STATIC_INLINE void XMC_SPI_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_INPUT_t input) +{ + XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param service_request Service request number. + Range: [0 to 5] + * + * @return None + * + * \parDescription
+ * Sets the interrupt node for SPI channel events.\n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so. This is not configured in XMC_SPI_CH_Init() during + * initialization. + * + * \parNote::
+ * 1. NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableEvent() + */ +__STATIC_INLINE void XMC_SPI_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const uint8_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, (uint32_t)service_request); +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @param interrupt_node Interrupt node pointer to be configured. \n + * \b Range: @ref XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, + * @ref XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc. + * @param service_request Service request number.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for USIC channel events. \n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_SPI_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, + (uint32_t)service_request); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @param service_request_line service request number of the event to be triggered. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Trigger a SPI interrupt service request.\n\n + * When the SPI service request is triggered, the NVIC interrupt associated with it will be + * generated if enabled. + * + * \parRelated APIs:
+ * XMC_SPI_CH_SelectInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line) +{ + XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @return None + * + * \parDescription
+ * Enables delay compensation. \n\n + * + * Delay compensation can be applied to the receive path. + * \parRelated APIs:
+ * XMC_SPI_CH_DisableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_EnableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_EnableDelayCompensation(channel); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @return None + * + * \parDescription
+ * Disables delay compensation.. \n\n + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_DisableDelayCompensation(channel); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @param pdiv Desired divider for the external frequency input. \b Range: minimum value = 1, maximum value = 1024 \n + * @param combination_mode USIC channel input combination mode \n + * + * @return None + * + * \parDescription
+ * Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and + * the combination mode of the USIC channel. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, + const uint16_t pdiv, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) +{ + XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel,pdiv,2U,combination_mode); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * The SELOx lines (with x = 1-7) can be used as addresses for an external address + * decoder to increase the number of external slave devices. + */ +__STATIC_INLINE void XMC_SPI_CH_EnableSlaveSelectCodedMode(XMC_USIC_CH_t *const channel) +{ + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode = (uint32_t)(channel->PCR_SSCMode & (~USIC_CH_PCR_SSCMode_SELCTR_Msk)); +} + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription
+ * Each SELOx line (with x = 0-7) can be directly connected to an external slave device. + */ +__STATIC_INLINE void XMC_SPI_CH_DisableSlaveSelectCodedMode(XMC_USIC_CH_t *const channel) +{ + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_SELCTR_Msk; +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @return None + * + * \parDescription
+ * Enable data transmission.\n\n + * Use this function in combination with XMC_SPI_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode() + * + * \parRelated APIs:
+ * XMC_SPI_CH_DisableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection + * @return None + * + * \parDescription
+ * Disable data transmission.\n\n + * Use this function in combination with XMC_SPI_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * + * \parRelated APIs:
+ * XMC_SPI_CH_EnableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_SPI_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_uart.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_uart.h new file mode 100644 index 00000000..387be642 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_uart.h @@ -0,0 +1,810 @@ + /** + * @file xmc_uart.h + * @date 2016-05-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial + * + * 2015-05-20: + * - Description updated
+ * - Added XMC_UART_CH_TriggerServiceRequest() and XMC_UART_CH_SelectInterruptNodePointer
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-09-01: + * - Modified XMC_UART_CH_SetInputSource() for avoiding complete DXCR register overwriting.
+ * - Modified XMC_UART_CH_EVENT_t enum for supporting XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent() + * for supporting multiple events configuration
+ * + * 2016-05-20: + * - Added XMC_UART_CH_EnableDataTransmission() and XMC_UART_CH_DisableDataTransmission() + * + * @endcond + * + */ + +#ifndef XMC_UART_H +#define XMC_UART_H + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_usic.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup UART + * @brief Universal Asynchronous Receiver/Transmitter (UART) driver for XMC microcontroller family. + * + * The UART driver uses Universal Serial Interface Channel(USIC) module to implement UART protocol. + * It provides APIs to configure USIC channel for UART communication. The driver enables the user + * in getting the status of UART protocol events, configuring interrupt service requests, protocol + * related parameter configuration etc. + * + * UART driver features: + * -# Configuration structure XMC_UART_CH_CONFIG_t and initialization function XMC_UART_CH_Init() + * -# Enumeration of events with their bit masks @ref XMC_UART_CH_EVENT_t, @ref XMC_UART_CH_STATUS_FLAG_t + * -# Allows the selection of input source for the DX0 input stage using the API XMC_UART_CH_SetInputSource() + * -# Allows configuration of baudrate using XMC_UART_CH_SetBaudrate() and configuration of data length using + XMC_UART_CH_SetWordLength() and XMC_UART_CH_SetFrameLength() + * -# Provides the status of UART protocol events, XMC_UART_CH_GetStatusFlag() + * -# Allows transmission of data using XMC_UART_CH_Transmit() and gets received data using XMC_UART_CH_GetReceivedData() + * + * @{ + */ + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ + +#if defined(USIC0) +#define XMC_UART0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */ +#define XMC_UART0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */ +#endif + +#if defined(USIC1) +#define XMC_UART1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */ +#define XMC_UART1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */ +#endif + +#if defined(USIC2) +#define XMC_UART2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */ +#define XMC_UART2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */ +#endif + +/********************************************************************************************************************* + * ENUMS + *********************************************************************************************************************/ + +/** + * UART driver status + */ +typedef enum XMC_UART_CH_STATUS +{ + XMC_UART_CH_STATUS_OK, /**< UART driver status : OK*/ + XMC_UART_CH_STATUS_ERROR, /**< UART driver status : ERROR */ + XMC_UART_CH_STATUS_BUSY /**< UART driver status : BUSY */ +} XMC_UART_CH_STATUS_t; + +/** +* UART portocol status. The enum values can be used for getting the status of UART channel. +* +*/ +typedef enum XMC_UART_CH_STATUS_FLAG +{ + XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE = USIC_CH_PSR_ASCMode_TXIDLE_Msk, /**< UART Protocol Status transmit IDLE*/ + XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE = USIC_CH_PSR_ASCMode_RXIDLE_Msk, /**< UART Protocol Status receive IDLE*/ + XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED = USIC_CH_PSR_ASCMode_SBD_Msk, /**< UART Protocol Status synchronization break detected*/ + XMC_UART_CH_STATUS_FLAG_COLLISION_DETECTED = USIC_CH_PSR_ASCMode_COL_Msk, /**< UART Protocol Status collision detected*/ + XMC_UART_CH_STATUS_FLAG_RECEIVER_NOISE_DETECTED = USIC_CH_PSR_ASCMode_RNS_Msk, /**< UART Protocol Status receiver noise detected */ + XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_0 = USIC_CH_PSR_ASCMode_FER0_Msk, /**< UART Protocol Status format error in stop bit 0 */ + XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_1 = USIC_CH_PSR_ASCMode_FER1_Msk, /**< UART Protocol Status format error in stop bit 1 */ + XMC_UART_CH_STATUS_FLAG_RECEIVE_FRAME_FINISHED = USIC_CH_PSR_ASCMode_RFF_Msk, /**< UART Protocol Status receive frame finished */ + XMC_UART_CH_STATUS_FLAG_TRANSMITTER_FRAME_FINISHED = USIC_CH_PSR_ASCMode_TFF_Msk, /**< UART Protocol Status transmit frame finished */ + XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY = USIC_CH_PSR_ASCMode_BUSY_Msk, /**< UART Protocol Status transfer status busy */ + XMC_UART_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_ASCMode_RSIF_Msk, /**< UART Protocol Status receive start indication flag*/ + XMC_UART_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_ASCMode_DLIF_Msk, /**< UART Protocol Status data lost indication flag*/ + XMC_UART_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_ASCMode_TSIF_Msk, /**< UART Protocol Status transmit shift indication flag*/ + XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_ASCMode_TBIF_Msk, /**< UART Protocol Status transmit buffer indication flag*/ + XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_RIF_Msk, /**< UART Protocol Status receive indication flag*/ + XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_AIF_Msk, /**< UART Protocol Status alternative receive indication flag*/ + XMC_UART_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_ASCMode_BRGIF_Msk /**< UART Protocol Status baudrate generator indication flag*/ +} XMC_UART_CH_STATUS_FLAG_t; + +/** +* UART configuration events. The enums can be used for configuring events using the CCR register. +*/ +typedef enum XMC_CH_UART_EVENT +{ + XMC_UART_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */ + XMC_UART_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */ + XMC_UART_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */ + XMC_UART_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */ + XMC_UART_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */ + XMC_UART_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */ + XMC_UART_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */ + + XMC_UART_CH_EVENT_SYNCHRONIZATION_BREAK = USIC_CH_PCR_ASCMode_SBIEN_Msk, /**< Event synchronization break */ + XMC_UART_CH_EVENT_COLLISION = USIC_CH_PCR_ASCMode_CDEN_Msk, /**< Event collision */ + XMC_UART_CH_EVENT_RECEIVER_NOISE = USIC_CH_PCR_ASCMode_RNIEN_Msk, /**< Event receiver noise */ + XMC_UART_CH_EVENT_FORMAT_ERROR = USIC_CH_PCR_ASCMode_FEIEN_Msk, /**< Event format error */ + XMC_UART_CH_EVENT_FRAME_FINISHED = USIC_CH_PCR_ASCMode_FFIEN_Msk /**< Event frame finished */ +} XMC_UART_CH_EVENT_t; + +/** + * UART Input sampling frequency options + */ +typedef enum XMC_UART_CH_INPUT_SAMPLING_FREQ +{ + XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH = XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH, /**< Sampling frequency input fperiph*/ + XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER = XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER /**< Sampling frequency input fractional divider*/ +} XMC_UART_CH_INPUT_SAMPLING_FREQ_t; + +/** + * UART input stages + */ +typedef enum XMC_UART_CH_INPUT +{ + XMC_UART_CH_INPUT_RXD = 0UL /**< UART input stage DX0*/ +#if UC_FAMILY == XMC1 + , + XMC_UART_CH_INPUT_RXD1 = 3UL, /**< UART input stage DX3*/ + XMC_UART_CH_INPUT_RXD2 = 5UL /**< UART input stage DX5*/ +#endif +} XMC_UART_CH_INPUT_t; + + +/** + * UART channel interrupt node pointers + */ +typedef enum XMC_UART_CH_INTERRUPT_NODE_POINTER +{ + XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */ + XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */ + XMC_UART_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */ + XMC_UART_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */ + XMC_UART_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */ +} XMC_UART_CH_INTERRUPT_NODE_POINTER_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + *********************************************************************************************************************/ + +/** + * UART initialization structure +*/ +typedef struct XMC_UART_CH_CONFIG +{ + uint32_t baudrate; /**< Desired baudrate. \b Range: minimum= 100, maximum= (fPERIPH * 1023)/(1024 * oversampling) */ + uint8_t data_bits; /**< Number of bits for the data field. Value configured as USIC channel word length. \n + \b Range: minimum= 1, maximum= 16*/ + uint8_t frame_length; /**< Indicates nmber of bits in a frame. Configured as USIC channel frame length. \n + \b Range: minimum= 1, maximum= 63*/ + uint8_t stop_bits; /**< Number of stop bits. \b Range: minimum= 1, maximum= 2 */ + uint8_t oversampling; /**< Number of samples for a symbol(DCTQ).\b Range: minimum= 1, maximum= 32*/ + XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Parity mode. \b Range: @ref XMC_USIC_CH_PARITY_MODE_NONE, @ref XMC_USIC_CH_PARITY_MODE_EVEN, \n + @ref XMC_USIC_CH_PARITY_MODE_ODD*/ +} XMC_UART_CH_CONFIG_t; + +/********************************************************************************************************************* + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1,XMC_UART1_CH0, XMC_UART1_CH1,XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param config Constant pointer to UART configuration structure of type @ref XMC_UART_CH_CONFIG_t. + * @return XMC_UART_CH_STATUS_t Status of initializing the USIC channel for UART protocol.\n + * \b Range: @ref XMC_UART_CH_STATUS_OK if initialization is successful.\n + * @ref XMC_UART_CH_STATUS_ERROR if configuration of baudrate failed. + * + * \parDescription
+ * Initializes the USIC channel for UART protocol.\n\n + * During the initialization, USIC channel is enabled, baudrate is configured with the defined oversampling value + * in the intialization structure. If the oversampling value is set to 0 in the structure, the default oversampling of 16 + * is considered. Sampling point for each symbol is configured at the half of sampling period. Symbol value is decided by the + * majority decision among 3 samples. + * Word length is configured with the number of data bits. If the value of \a frame_length is 0, then USIC channel frame length + * is set to the same value as word length. If \a frame_length is greater than 0, it is set as the USIC channel frame length. + * Parity mode is set to the value configured for \a parity_mode. + * The USIC channel should be set to UART mode by calling the XMC_UART_CH_Start() API after the initialization. + * + * \parRelated APIs:
+ * XMC_UART_CH_Start(), XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n + */ +void XMC_UART_CH_Init(XMC_USIC_CH_t *const channel, const XMC_UART_CH_CONFIG_t *const config); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return None + * + * \parDescription
+ * Sets the USIC channel operation mode to UART mode.\n\n + * CCR register bitfield \a Mode is set to 2(UART mode). This API should be called after configuring + * the USIC channel. Transmission and reception can happen only when the UART mode is set. + * This is an inline function. + * + * \parRelated APIs:
+ * XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_Start(XMC_USIC_CH_t *const channel) +{ + channel->CCR = (uint32_t)(((channel->CCR) & (~USIC_CH_CCR_MODE_Msk)) | (uint32_t)XMC_USIC_CH_OPERATING_MODE_UART); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return XMC_UART_CH_STATUS_t Status to indicate if the communication channel is stopped successfully.\n + * @ref XMC_UART_CH_STATUS_OK if the communication channel is stopped. + * @ref XMC_UART_CH_STATUS_BUSY if the communication channel is busy. + * + * \parDescription
+ * Stops the UART communication.\n\n + * CCR register bitfield \a Mode is reset. This disables the communication. + * Before starting the communication again, the channel has to be reconfigured. + * + * \parRelated APIs:
+ * XMC_UART_CH_Init() \n\n\n + */ +XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1 ,XMC_UART1_CH0, XMC_UART1_CH1, XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param rate Desired baudrate. \n + * \b Range: minimum value = 100, maximum value depends on the peripheral clock frequency\n + * and \a oversampling. Maximum baudrate can be derived using the formula: (fperiph * 1023)/(1024 * oversampling) + * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data.\n + * This can be related to the number of samples for each logic state of the data signal.\n + * \b Range: 4 to 32. Value should be chosen based on the protocol used. + * @return XMC_UART_CH_STATUS_t Status indicating the baudrate configuration.\n + * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured, + * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid. + * + * \parDescription:
+ * Sets the bus speed in bits per second.\n\n + * Derives the values of \a STEP and PDIV to arrive at the optimum realistic speed possible. + * \a oversampling is the number of samples to be taken for each symbol of UART protocol. + * Default \a oversampling of 16 is considered if the input \a oversampling is less than 4. It is recommended to keep + * a minimum oversampling of 4 for UART. + * + * \parRelated APIs:
+ * XMC_UART_CH_Init(), XMC_UART_CH_Stop() + */ +XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param data Data to be transmitted. \n + * \b Range: 16 bit unsigned data within the range 0 to 65535. Actual size of + * data transmitted depends on the configured number of bits for the UART protocol in the register SCTR. + * @return None + * + * \parDescription
+ * Transmits data over serial communication channel using UART protocol.\n\n + * Based on the channel configuration, data is either put to the transmit FIFO or to TBUF register. + * Before putting data to TBUF, the API waits for TBUF to finish shifting its contents to shift register. + * So user can continuously execute the API without checking for TBUF busy status. Based on the number of + * data bits configured, the lower significant bits will be extracted for transmission. + * + * Note: When FIFO is not configured, the API waits for the TBUF to be available. + * This makes the execution a blocking call. + * + * \parRelated APIs:
+ * XMC_UART_CH_GetReceivedData() \n\n\n + */ +void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return uint16_t Received data over UART communication channel. + * \parDescription
+ * Provides one word of data received over UART communication channel.\n\n + * Based on the channel configuration, data is either read from the receive FIFO or RBUF register. + * Before returning the value, there is no check for data validity. User should check the appropriate + * data receive flags(standard receive/alternative receive/FIFO standard receive/FIFO alternative receive) + * before executing the API. Reading from an empty receive FIFO can generate a receive error event. + * + * \parRelated APIs:
+ * XMC_UART_CH_GetStatusFlag(), XMC_UART_CH_Transmit() \n\n\n + */ +uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param word_length Data word length. \n + * \b Range: minimum= 1, maximum= 16. + * @return None + * + * \parDescription
+ * Sets the data word length in number of bits.\n\n + * Word length can range from 1 to 16. It indicates the number of data bits in a data word. + * The value of \a word_length will be decremented by 1 before setting the value to \a SCTR register. + * If the UART data bits is more than 16, then the frame length should be set to the actual number of bits and + * word length should be configured with the number of bits expected in each transaction. For example, if number of data bits + * for UART communication is 20 bits, then the frame length should be set as 20. Word length can be set based on the + * transmit and receive handling. If data is stored as 8bit array, then the word length can be set to 8. In this case, + * a full message of UART data should be transmitted/ received as 3 data words. + * + * \parRelated APIs:
+ * XMC_UART_CH_SetFrameLength() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length) +{ + XMC_USIC_CH_SetWordLength(channel, word_length); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param frame_length Number of data bits in each UART frame. \n + * \b Range: minimum= 1, maximum= 64. + * @return None + * + * \parDescription
+ * Sets the number of data bits for UART communication.\n\n + * The frame length is configured by setting the input value to \a SCTR register. + * The value of \a frame_length will be decremented by 1, before setting it to the register. + * Frame length should not be set to 64 for UART communication. + * + * \parRelated APIs:
+ * XMC_UART_CH_SetWordLength() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length) +{ + XMC_USIC_CH_SetFrameLength(channel, frame_length); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param event Event bitmasks to enable. Use the type @ref XMC_UART_CH_EVENT_t for naming events. \n + * \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref XMC_UART_CH_EVENT_DATA_LOST, + * @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref XMC_UART_CH_EVENT_TRANSMIT_BUFFER, + * etc. + * @return None + * + * \parDescription
+ * Enables interrupt events for UART communication.\n\n + * Multiple events can be combined using the bitwise OR operation and configured in one function call. + * @ref XMC_UART_CH_EVENT_t enumerates multiple event bitmasks. These enumerations can be used as input to the API. + * Events are configured by setting bits in the CCR register. + * \parRelated APIs:
+ * XMC_UART_CH_DisableEvent(), XMC_UART_CH_SetInterruptNodePointer(), XMC_UART_CH_GetStatusFlag() \n\n\n + */ +void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param event Bitmask of events to disable. Use the type @ref XMC_UART_CH_EVENT_t for naming events.\n + * \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref XMC_UART_CH_EVENT_DATA_LOST, + * @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref XMC_UART_CH_EVENT_TRANSMIT_BUFFER, + * etc. + * @return None + * + * \parDescription
+ * Disables the interrupt events by clearing the bits in CCR register.\n\n + * Multiple events can be combined using the bitwise OR operation and configured in one function call. + * XMC_UART_CH_EVENT_FLAG_t enumerates multiple event bitmasks. These enumerations can be used as input to the API. + * + * \parRelated APIs:
+ * XMC_UART_CH_ClearStatusFlag(), XMC_UART_CH_EnableEvent() \n\n\n + */ +void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param service_request Service request number for generating protocol interrupts.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for UART channel protocol events.\n\n + * For all the protocol events enlisted in the enumeration XMC_UART_CH_EVENT_t, one common + * interrupt gets generated. The service request connects the interrupt node to the UART + * protocol events. + * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const uint8_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, + (uint32_t)service_request); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param interrupt_node Interrupt node pointer to be configured. \n + * \b Range: @ref XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, + * @ref XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc. + * @param service_request Service request number.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for USIC channel events. \n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_UART_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, + (uint32_t)service_request); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param service_request_line service request number of the event to be triggered. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Trigger a UART interrupt service request.\n\n + * When the UART service request is triggered, the NVIC interrupt associated with it will be + * generated if enabled. + * + * \parRelated APIs:
+ * XMC_UART_CH_SelectInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line) +{ + XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return Status of UART channel events. \n + * \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for + * event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE, @ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE, + * @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc. + * + * \parDescription
+ * Provides the status of UART channel events.\n\n + * Status provided by the API represents the status of multiple events at their bit positions. The bitmasks can be + * obtained using the enumeration XMC_UART_CH_STATUS_FLAG_t. Event status is obtained by reading + * the register PSR_ASCMode. + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableEvent(), XMC_UART_CH_ClearStatusFlag()\n\n\n + */ +__STATIC_INLINE uint32_t XMC_UART_CH_GetStatusFlag(XMC_USIC_CH_t *const channel) +{ + return channel->PSR_ASCMode; +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param flag UART events to be cleared. \n + * \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for + * event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE, @ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE, + * @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc. + * @return None + * + * \parDescription
+ * Clears the status of UART channel events.\n\n + * Multiple events can be combined using the bitwise OR operation and configured in one function call. + * XMC_UART_CH_STATUS_FLAG_t enumerates multiple event bitmasks. These enumerations can be used as input to the API. + * Events are cleared by setting the bitmask to the PSCR register. + * + * \parRelated APIs:
+ * XMC_UART_CH_DisableEvent(), XMC_UART_CH_GetStatusFlag()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag) +{ + channel->PSCR = flag; +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @param source Input source select for the input stage. The table provided below maps the decimal value with the input source. + * + * + *
0DXnA
1DXnB
2DXnC
3DXnD
4DXnE
5DXnF
6DXnG
7Always 1
+ * @return None + * + * \parDescription
+ * Sets input soource for the UART communication.\n\n + * It is used for configuring the input stage for data reception. + * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. + * The API can be used for the input stages DX0, DX3 and DX5. + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputInversion() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input, const uint8_t source) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~(USIC_CH_DX0CR_INSW_Msk|USIC_CH_DX0CR_DSEN_Msk))); + XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param pulse_length Length of the zero pulse in number of time quanta. \n + * \b Range: 0 to 7. + * @return None + * + * \parDescription
+ * Sets the length of zero pulse in number of time quanta. Value 0 indicates one time quanta.\n\n + * Maximum possible is 8 time quanta with the value configured as 7.\n + * The value is set to PCR_ASCMode register. + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n + * +*/ +__STATIC_INLINE void XMC_UART_CH_SetPulseLength(XMC_USIC_CH_t *const channel, const uint8_t pulse_length) +{ + channel->PCR_ASCMode = (uint32_t)(channel->PCR_ASCMode & (~USIC_CH_PCR_ASCMode_PL_Msk)) | + ((uint32_t)pulse_length << USIC_CH_PCR_ASCMode_PL_Pos); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param sample_point Sample point among the number of samples. \n + * \b Range: minimum= 0, maximum= \a oversampling (DCTQ). + * @return None + * + * \parDescription
+ * Sets the sample point among the multiple samples for each UART symbol.\n\n + * The sample point is the one sample among number of samples set as oversampling. The value should be less than + * the oversampling value. XMC_UART_CH_Init() sets the sample point to the sample at the centre. For + * example if the oversampling is 16, then the sample point is set to 9. + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetSamplePoint(XMC_USIC_CH_t *const channel, const uint32_t sample_point) +{ + channel->PCR_ASCMode = (uint32_t)((channel->PCR_ASCMode & (uint32_t)(~USIC_CH_PCR_ASCMode_SP_Msk)) | + (sample_point << USIC_CH_PCR_ASCMode_SP_Pos)); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * + * \parDescription
+ * Enables input inversion for UART input data signal.\n\n + * Polarity of the input source can be changed to provide inverted data input. + * \parRelated APIs:
+ * XMC_UART_CH_DisableInputInversion()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * + * \parDescription
+ * Disables input inversion for UART input data signal.\n\n + * Resets the input data polarity for the UART input data signal. + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputInversion()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); +} +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * + * \parDescription
+ * Enables the digital filter for UART input stage.\n\n + * + * \parRelated APIs:
+ * XMC_UART_CH_DisableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_EnableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input); +} +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * + * \parDescription
+ * Disables the digital filter for UART input stage.\n\n + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_DisableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input); +} +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * \parDescription
+ * Enables synchronous input for the UART input stage.\n\n + * + * \parRelated APIs:
+ * XMC_UART_CH_DisableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_EnableInputSync(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_EnableInputSync(channel, (XMC_USIC_CH_INPUT_t)input); +} +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @return None + * + * \parDescription
+ * Disables synchronous input for the UART input stage.\n\n + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_DisableInputSync(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input) +{ + XMC_USIC_CH_DisableInputSync(channel, (XMC_USIC_CH_INPUT_t)input); +} +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), + * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). + * @param sampling_freq Input sampling frequency. \n + * \b Range: @ref XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH, @ref XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER. + * @return None + * + * \parDescription
+ * Sets the sampling frequency for the UART input stage.\n\n + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel, + const XMC_UART_CH_INPUT_t input, + const XMC_UART_CH_INPUT_SAMPLING_FREQ_t sampling_freq) +{ + XMC_USIC_CH_SetInputSamplingFreq(channel, (XMC_USIC_CH_INPUT_t)input, (XMC_USIC_CH_INPUT_SAMPLING_FREQ_t)sampling_freq); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return None + * + * \parDescription
+ * Enable data transmission.\n\n + * Use this function in combination with XMC_UART_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode() + * + * \parRelated APIs:
+ * XMC_UART_CH_DisableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV); +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return None + * + * \parDescription
+ * Disable data transmission.\n\n + * Use this function in combination with XMC_UART_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. + * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). + * + * \parRelated APIs:
+ * XMC_UART_CH_EnableDataTransmission()\n\n\n + */ +__STATIC_INLINE void XMC_UART_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) +{ + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usbd.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usbd.h new file mode 100644 index 00000000..5e94b5af --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usbd.h @@ -0,0 +1,989 @@ +/** + * @file xmc_usbd.h + * @date 2015-06-20 + * + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-16: + * - Initial Version.
+ * 2015-03-18: + * - Updated the doxygen comments for documentation.
+ * - Updated the XMC_USBD_PATCH_VERSION to 4.
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API.
+ * - Updated the doxygen comments for API XMC_USBD_IsEnumDone().
+ * - Updated the copy right in the file header.
+ * + * @endcond + * + */ + +#ifndef XMC_USBD_H +#define XMC_USBD_H + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ +#include "xmc_common.h" + +#if defined(USB0) + +#include +#include +#include "xmc_usbd_regs.h" +#include "xmc_scu.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup USBD + * @brief Universal Serial Bus Device (USBD) driver for the XMC4000 microcontroller family. + * + * The USBD is the device driver for the USB0 hardware module on XMC4000 family of microcontrollers. + * The USB0 module can be used to establish a USB interface between outside world and XMC4000 family of controllers. + * The USB module includes the following features in device mode: + * -# Complies with the USB 2.0 Specification. + * -# Support for the Full-Speed (12-Mbps) mode. + * -# Supports up to 7 bidirectional endpoints, including control endpoint 0. + * -# Supports SOFs in Full-Speed modes. + * -# Supports clock gating for power saving. + * -# Supports USB suspend/resume. + * -# Supports USB soft disconnect. + * -# Supports DMA mode. + * -# Supports FIFO mode. + * + * The below figure shows the overview of USB0 module in XMC4 microntroller. + * @image html USB_module_overview.png + * @image latex ../images/USB_module_overview.png + * + * The below figure shows the USB device connection of USB0 module. + * @image html USB_device_connection.png + * @image latex ../images/USB_device_connection.png + * + * The USBD device driver supports the following features:\n + * -# Initialize/Uninitialize the USB0 module on XMC4000 device. + * -# Connect the USB device to host. + * -# Get USB device state. + * -# Set the USB device address. + * -# Configure/Unconfigure the USB endpoints. + * -# Stall/Abort the USB endpoints. + * -# USB IN transfers on EP0 and non EP0 endpoints. + * -# USB OUT transfers on EP0 and non EP0 endpoints. + * + * The USBD device driver provides the configuration structure ::XMC_USBD_t which user need to configure before initializing the USB.\n + * The following elements of configuration structure need to be initialized before calling the ::XMC_USBD_Init API: + * -# cb_xmc_device_event of type ::XMC_USBD_SignalDeviceEvent_t. + * -# cb_endpoint_event of type ::XMC_USBD_SignalEndpointEvent_t. + * -# usbd_max_num_eps of type ::XMC_USBD_MAX_NUM_EPS_t. + * -# usbd_transfer_mode of type ::XMC_USBD_TRANSFER_MODE_t. + * + * @{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ + +#define XMC_USBD_NUM_TX_FIFOS (7U) /**< Number of hardware transmission endpoint fifos */ + +#define XMC_USBD_MAX_FIFO_SIZE (2048U) /**< Maximum USBD endpoint fifo size */ + +#define XMC_USBD_NUM_EPS (7U) /**< Number of hardware endpoints */ + +#define XMC_USBD_MAX_PACKET_SIZE (64U) /**< Maximum packet size for all endpoints + (including ep0) */ + +/**< Maximum transfer size for endpoints. + * + * It's based on the maximum payload, due to the fact, + * that we only can transfer 2^10 - 1 packets and this is less than the + * transfer size field can hold. + */ +#define XMC_USBD_MAX_TRANSFER_SIZE (((uint32_t)((uint32_t)1U << (uint32_t)10U) - 1U) * (uint32_t)XMC_USBD_MAX_PACKET_SIZE) + +#define XMC_USBD_MAX_TRANSFER_SIZE_EP0 (64U) /**< Maximum transfer size for endpoint 0*/ + +#define XMC_USBD_SETUP_COUNT (3U) /**< The number of USB setup packets */ + +#define XMC_USBD_SETUP_SIZE (8U) /**< The size of USB setup data */ + +#define XMC_USBD_EP_NUM_MASK (0x0FU) /**< USB Endpoint number mask. */ + +#define XMC_USBD_EP_DIR_MASK (0x80U) /**< USB Endpoint direction mask */ + +#define XMC_USBD_DCFG_DEVSPD_FS (0x3U) /*USB Full Speed device flag in DCFG register */ + +#define XMC_USBD_TX_FIFO_REG_OFFSET (0x1000U)/* First endpoint fifo register offset from base address */ + +#define XMC_USBD_TX_FIFO_OFFSET (0x1000U)/* Offset for each fifo register */ + +#define XMC_USBD_ENDPOINT_NUMBER_MASK (0x0FU) /**< USB Endpoint number mask to get the EP number from address. */ + +#define XMC_USBD_ENDPOINT_DIRECTION_MASK (0x80U) /**< USB Endpoint direction mask to get the EP direction from address. */ + +#define XMC_USBD_ENDPOINT_MAX_PACKET_SIZE_MASK (0x07FFU)/**< USB Endpoint Maximum Packet Size mask */ + +#define XMC_USBD_ENDPOINT_MFRAME_TR_MASK (0x1800U)/* USB Endpoint micro frame TR mask */ +#define XMC_USBD_ENDPOINT_MFRAME_TR_1 (0x0000U)/* Selects USB Endpoint micro frame TR1 */ +#define XMC_USBD_ENDPOINT_MFRAME_TR_2 (0x0800U)/* Selects USB Endpoint micro frame TR2 */ +#define XMC_USBD_ENDPOINT_MFRAME_TR_3 (0x1000U)/* Selects USB Endpoint micro frame TR3 */ + + +#define XMC_USBD_SPEED_FULL (1U) /**< Speed Mode. Full Speed */ + +#define XMC_USBD_EP0_BUFFER_SIZE (64U) /* Endpoint 0 buffer size */ + +#define XMC_USBD_EP1_BUFFER_SIZE (64U) /* Endpoint 1 buffer size */ + +#define XMC_USBD_EP2_BUFFER_SIZE (64U) /* Endpoint 2 buffer size */ + +#define XMC_USBD_EP3_BUFFER_SIZE (64U) /* Endpoint 3 buffer size */ + +#define XMC_USBD_EP4_BUFFER_SIZE (64U) /* Endpoint 4 buffer size */ + +#define XMC_USBD_EP5_BUFFER_SIZE (64U) /* Endpoint 5 buffer size */ + +#define XMC_USBD_EP6_BUFFER_SIZE (64U) /* Endpoint 6 buffer size */ + + +/********************************************************************************************************************** + * ENUMS + *********************************************************************************************************************/ + +/** + * Defines the options for the global receive fifo packet status. + * Use type ::XMC_USBD_GRXSTS_PKTSTS_t for this enum. + * */ +typedef enum XMC_USBD_GRXSTS_PKTSTS { + XMC_USBD_GRXSTS_PKTSTS_GOUTNAK = 0x1U, /**< Global out nack send ( triggers an interrupt ) */ + XMC_USBD_GRXSTS_PKTSTS_OUTDATA = 0x2U, /**< OUT data packet received */ + XMC_USBD_GRXSTS_PKTSTS_OUTCMPL = 0x3U, /**< OUT transfer completed (triggers an interrupt) */ + XMC_USBD_GRXSTS_PKTSTS_SETUPCMPL = 0x4U, /**< SETUP transaction completed (triggers an interrupt) */ + XMC_USBD_GRXSTS_PKTSTS_SETUP = 0x6U /**< SETUP data packet received */ +} XMC_USBD_GRXSTS_PKTSTS_t; + +/** +* Defines the options for the USB endpoint type. The values are from the USB 2.0 specification. +* Use type ::XMC_USBD_ENDPOINT_TYPE_t for this enum. +*/ +typedef enum XMC_USBD_ENDPOINT_TYPE { + XMC_USBD_ENDPOINT_TYPE_CONTROL = 0x0U, /**< Control endpoint */ + XMC_USBD_ENDPOINT_TYPE_ISOCHRONOUS = 0x01U, /**< Isochronous endpoint */ + XMC_USBD_ENDPOINT_TYPE_BULK = 0x02U, /**< Bulk endpoint */ + XMC_USBD_ENDPOINT_TYPE_INTERRUPT = 0x03U /**< Interrupt endpoint */ +} XMC_USBD_ENDPOINT_TYPE_t; + + +/** +* Defines the options for USB device state while setting the address. +* Use type ::XMC_USBD_SET_ADDRESS_STAGE_t for this enum. +*/ +typedef enum XMC_USBD_SET_ADDRESS_STAGE { + XMC_USBD_SET_ADDRESS_STAGE_SETUP, /**< Setup address */ + XMC_USBD_SET_ADDRESS_STAGE_STATUS /**< Status address */ +} XMC_USBD_SET_ADDRESS_STAGE_t; + + +/** +* Defines the USB Device Status of executed operation. +* Use type ::XMC_USBD_STATUS_t for this enum. +*/ +typedef enum XMC_USBD_STATUS { + XMC_USBD_STATUS_OK = 0U, /**< USBD Status: Operation succeeded*/ + XMC_USBD_STATUS_BUSY = 2U, /**< Driver is busy and cannot handle request */ + XMC_USBD_STATUS_ERROR = 1U /**< USBD Status: Unspecified error*/ +} XMC_USBD_STATUS_t; + + +/** +* Defines the USB Device events. +* Use type ::XMC_USBD_EVENT_t for this enum. +*/ +typedef enum XMC_USBD_EVENT { + XMC_USBD_EVENT_POWER_ON, /**< USB Device Power On */ + XMC_USBD_EVENT_POWER_OFF, /**< USB Device Power Off */ + XMC_USBD_EVENT_CONNECT, /**< USB Device connected */ + XMC_USBD_EVENT_DISCONNECT, /**< USB Device disconnected */ + XMC_USBD_EVENT_RESET, /**< USB Reset occurred */ + XMC_USBD_EVENT_HIGH_SPEED, /**< USB switch to High Speed occurred */ + XMC_USBD_EVENT_SUSPEND, /**< USB Suspend occurred */ + XMC_USBD_EVENT_RESUME, /**< USB Resume occurred */ + XMC_USBD_EVENT_REMOTE_WAKEUP, /**< USB Remote wakeup */ + XMC_USBD_EVENT_SOF, /**< USB Start of frame event */ + XMC_USBD_EVENT_EARLYSUSPEND, /**< USB Early suspend */ + XMC_USBD_EVENT_ENUMDONE, /**< USB enumeration done */ + XMC_USBD_EVENT_ENUMNOTDONE, /**< USB enumeration not done */ + XMC_USBD_EVENT_OUTEP, /**< USB OUT endpoint */ + XMC_USBD_EVENT_INEP /**< USB IN endpoint */ +} XMC_USBD_EVENT_t; + +/** +* Defines the USB IN endpoint events. +* Use type ::XMC_USBD_EVENT_IN_EP_t for this enum. +*/ +typedef enum XMC_USBD_EVENT_IN_EP { + XMC_USBD_EVENT_IN_EP_TX_COMPLET = 1U, /**< USB IN ep transmission complete */ + XMC_USBD_EVENT_IN_EP_DISABLED = 2U, /**< USB IN ep disabled */ + XMC_USBD_EVENT_IN_EP_AHB_ERROR = 4U, /**< USB IN ep AHB error */ + XMC_USBD_EVENT_IN_EP_TIMEOUT = 8U, /**< USB IN ep timeout */ +} XMC_USBD_EVENT_IN_EP_t; + +/** +* Defines the USB OUT endpoint events. +* Use type ::XMC_USBD_EVENT_OUT_EP_t for this enum. +*/ +typedef enum XMC_USBD_EVENT_OUT_EP { + XMC_USBD_EVENT_OUT_EP_TX_COMPLET = 1U, /**< USB OUT ep transmission complete */ + XMC_USBD_EVENT_OUT_EP_DISABLED = 2U, /**< USB OUT ep disabled */ + XMC_USBD_EVENT_OUT_EP_AHB_ERROR = 4U, /**< USB OUT ep AHB error */ + XMC_USBD_EVENT_OUT_EP_SETUP = 8U, /**< USB OUT ep setup */ +} XMC_USBD_EVENT_OUT_EP_t; + + +/** +* Defines the generic USB endpoint events. +* Use type ::XMC_USBD_EP_EVENT_t for this enum. +*/ +typedef enum XMC_USBD_EP_EVENT { + XMC_USBD_EP_EVENT_SETUP, /**< SETUP packet*/ + XMC_USBD_EP_EVENT_OUT, /**< OUT packet*/ + XMC_USBD_EP_EVENT_IN /**< IN packet*/ +} XMC_USBD_EP_EVENT_t; + +/** +* Defines the options for the USB data transfer modes. +* Use type ::XMC_USBD_TRANSFER_MODE_t for this enum. +*/ +typedef enum XMC_USBD_TRANSFER_MODE { + XMC_USBD_USE_DMA, /**< Transfer by DMA*/ + XMC_USBD_USE_FIFO /**< Transfer by FIFO*/ +} XMC_USBD_TRANSFER_MODE_t; + +/** +* Defines the options for the maximum number of endpoints used. +* Use type ::XMC_USBD_MAX_NUM_EPS_t for this enum. +*/ +typedef enum XMC_USBD_MAX_NUM_EPS { + XMC_USBD_MAX_NUM_EPS_1 = 1U, /**< Maximum 1 endpoint used*/ + XMC_USBD_MAX_NUM_EPS_2 = 2U, /**< Maximum 2 endpoints used*/ + XMC_USBD_MAX_NUM_EPS_3 = 3U, /**< Maximum 3 endpoints used*/ + XMC_USBD_MAX_NUM_EPS_4 = 4U, /**< Maximum 4 endpoints used*/ + XMC_USBD_MAX_NUM_EPS_5 = 5U, /**< Maximum 5 endpoints used*/ + XMC_USBD_MAX_NUM_EPS_6 = 6U, /**< Maximum 6 endpoints used*/ + XMC_USBD_MAX_NUM_EPS_7 = 7U /**< Maximum 2 endpoints used*/ +} XMC_USBD_MAX_NUM_EPS_t; + +/** +* USB device/endpoint event function pointers +*/ +typedef void (*XMC_USBD_SignalDeviceEvent_t) (XMC_USBD_EVENT_t event);/**< Pointer to USB device event call back. + Uses type ::XMC_USBD_EVENT_t as the argument of callback.*/ +typedef void (*XMC_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, XMC_USBD_EP_EVENT_t ep_event);/**< Pointer to USB endpoint event call back. + Uses type ::XMC_USBD_EP_EVENT_t and EP address as the argument of callback.*/ + +/********************************************************************************************************************** + * DATA STRUCTURES + *********************************************************************************************************************/ + +/** + * Describes the USB Device Driver Capabilities. + */ +typedef struct XMC_USBD_CAPABILITIES { + uint32_t event_power_on : 1; /**< Signal Power On event*/ + uint32_t event_power_off : 1; /**< Signal Power Off event*/ + uint32_t event_connect : 1; /**< Signal Connect event*/ + uint32_t event_disconnect : 1; /**< Signal Disconnect event*/ + uint32_t event_reset : 1; /**< Signal Reset event*/ + uint32_t event_high_speed : 1; /**< Signal switch to High-speed event*/ + uint32_t event_suspend : 1; /**< Signal Suspend event*/ + uint32_t event_resume : 1; /**< Signal Resume event*/ + uint32_t event_remote_wakeup : 1; /**< Signal Remote Wake up event*/ + uint32_t reserved : 23; /**< Reserved for future use*/ +} XMC_USBD_CAPABILITIES_t; + +/** + * Describes the current USB Device State. + */ +typedef struct XMC_USBD_STATE { + uint32_t powered : 1; /**< USB Device powered flag*/ + uint32_t connected : 1; /**< USB Device connected flag*/ + uint32_t active : 1; /**< USB Device active lag*/ + uint32_t speed : 2; /**< USB Device speed */ +} XMC_USBD_STATE_t; + +/** + * Describes a USB endpoint
+ * + * All information to control an endpoint is stored in this structure. + * It contains information about the endpoints and the status of the device. + */ +typedef struct { + union { + uint32_t address : 8; /**< The endpoint address including the direction */ + struct { + uint32_t number : 4; /**< The endpoint number.It can be from 0 to 6 */ + uint32_t pading : 3; /**< Padding between number and direction */ + uint32_t direction : 1; /**< The endpoint direction */ + } address_st; + } address_u; + uint32_t type : 2; /**< The endpoint type */ + uint32_t isConfigured : 1; /**< The flag showing, if the endpoint is configured */ + volatile uint32_t inInUse : 1; /**< Sets if the selected USB IN endpoint is currently in use */ + volatile uint32_t outInUse : 1; /**< Sets if the selected USB OUT endpoint is currently in use */ + uint32_t isStalled : 1; /**< Sets if the selected USB endpoint is stalled. */ + uint32_t txFifoNum : 4; /**< Endpoint transmit Fifo Number */ + uint32_t sendZeroLengthPacket : 1; /**< If set, a zero length packet will be send at the end of the transfer */ + uint32_t maxPacketSize : 7; /**< The maximum size of packet for USB endpoint ( due to FS Speed device only 64 Byte )*/ + uint32_t maxTransferSize : 19; /**< The maximum amount of data the core can send at once.*/ + uint8_t *outBuffer; /**< The buffer for operation as OUT endpoint */ + uint32_t outBytesAvailable; /**< The number of bytes available in the EP OUT buffer */ + uint32_t outBufferSize; /**< The size of the EP OUT buffer */ + uint32_t outOffset; /**< The read offset of the EP OUT buffer */ + uint8_t *inBuffer; /**< The buffer for operation as IN endpoint */ + uint32_t inBufferSize; /**< The size of the EP IN buffer */ + uint8_t *xferBuffer; /**< The buffer of the current transfer */ + uint32_t xferLength; /**< The length of the current transfer */ + uint32_t xferCount; /**< Bytes transfered of the current USB data transfer */ + uint32_t xferTotal; /**< The length of total data in buffer */ +} XMC_USBD_EP_t; + +/** + * Describes the XMC USB device
+ * + * All information to control an XMC USB device is stored in + * this structure. It contains register, callbacks, information + * about the endpoints and the status of the device. + */ +typedef struct XMC_USBD_DEVICE { + XMC_USBD_EP_t ep[8]; /**< Endpoints of the USB device. It is of type ::XMC_USBD_EP_t */ + dwc_otg_core_global_regs_t *global_register; /**< Global register interface */ + dwc_otg_device_global_regs_t *device_register; /**< Device register interface */ + dwc_otg_dev_in_ep_regs_t *endpoint_in_register[(uint8_t)XMC_USBD_NUM_EPS];/**< IN Endpoint register interface */ + dwc_otg_dev_out_ep_regs_t *endpoint_out_register[(uint8_t)XMC_USBD_NUM_EPS];/**< OUT Endpoint register interface */ + volatile uint32_t *fifo[(uint8_t)XMC_USBD_NUM_TX_FIFOS]; /**< Transmit fifo interface */ + uint16_t txfifomsk; /**< Mask of used TX fifos */ + uint32_t IsConnected : 1; /**< Sets if device is connected */ + uint32_t IsActive : 1; /**< Sets if device is currently active */ + uint32_t IsPowered : 1; /**< Sets if device is powered by Vbus */ + XMC_USBD_SignalDeviceEvent_t DeviceEvent_cb; /**< The USB device event callback. */ + XMC_USBD_SignalEndpointEvent_t EndpointEvent_cb; /**< The USB endpoint event callback. */ +} XMC_USBD_DEVICE_t; + + +/** + * USB device initialization structure + */ +typedef struct XMC_USBD_OBJ +{ + USB0_GLOBAL_TypeDef *const usbd; /**< USB Module Pointer. The USB0 module base address. */ + XMC_USBD_SignalDeviceEvent_t cb_xmc_device_event; /**< USB device event callback. Use ::XMC_USBD_SignalDeviceEvent_t type of function pointer. */ + XMC_USBD_SignalEndpointEvent_t cb_endpoint_event; /**< USB endpoint event callback. Use ::XMC_USBD_SignalEndpointEvent_t type of function pointer.*/ + XMC_USBD_MAX_NUM_EPS_t usbd_max_num_eps; /**< Maximum number of end points used. The maximum range can be 7.*/ + XMC_USBD_TRANSFER_MODE_t usbd_transfer_mode; /**< USB data transfer mode.Use ::XMC_USBD_TRANSFER_MODE_t type to specify the transfer mode. */ +} XMC_USBD_t; + +/** + * Defines the access structure of the USB Device Driver. + */ +typedef struct XMC_USBD_DRIVER { + + + XMC_USBD_CAPABILITIES_t (*GetCapabilities) (void); /**< Pointer to @ref XMC_USBD_GetCapabilities : Get driver capabilities.*/ + + + XMC_USBD_STATUS_t (*Initialize) (XMC_USBD_t *obj); /**< Pointer to @ref XMC_USBD_Init : Initialize USB Device Interface.*/ + + + XMC_USBD_STATUS_t (*Uninitialize) (void); /**< Pointer to @ref XMC_USBD_Uninitialize : De-initialize USB Device Interface.*/ + + + XMC_USBD_STATUS_t (*DeviceConnect) (void); /**< Pointer to @ref XMC_USBD_DeviceConnect : Connect USB Device.*/ + + + XMC_USBD_STATUS_t (*DeviceDisconnect) (void); /**< Pointer to @ref XMC_USBD_DeviceDisconnect : Disconnect USB Device.*/ + + + XMC_USBD_STATE_t (*DeviceGetState) (const XMC_USBD_t *const obj); /**< Pointer to @ref XMC_USBD_DeviceGetState : Get current USB Device State.*/ + + + XMC_USBD_STATUS_t (*DeviceSetAddress) (uint8_t dev_addr, XMC_USBD_SET_ADDRESS_STAGE_t stage);/**< Pointer to @ref XMC_USBD_DeviceSetAddress : Set USB Device Address.*/ + + + XMC_USBD_STATUS_t (*EndpointConfigure) (uint8_t ep_addr,XMC_USBD_ENDPOINT_TYPE_t ep_type, uint16_t ep_max_packet_size);/**< Pointer to @ref XMC_USBD_EndpointConfigure : Configure USB Endpoint.*/ + + + XMC_USBD_STATUS_t (*EndpointUnconfigure)(uint8_t ep_addr); /**< Pointer to @ref XMC_USBD_EndpointUnconfigure : Unconfigure USB Endpoint.*/ + + + XMC_USBD_STATUS_t (*EndpointStall) (uint8_t ep_addr, bool stall); /**< Pointer to @ref XMC_USBD_EndpointStall : Set/Clear Stall for USB Endpoint.*/ + + + XMC_USBD_STATUS_t (*EndpointReadStart) (uint8_t ep_addr, uint32_t len); /**< Pointer to @ref XMC_USBD_EndpointReadStart : Start USB Endpoint Read operation.*/ + + + int32_t (*EndpointRead) (uint8_t ep_addr, uint8_t *buf, uint32_t len);/**< Pointer to @ref XMC_USBD_EndpointRead : Read data from USB Endpoint.*/ + + + int32_t (*EndpointWrite) (uint8_t ep_addr, const uint8_t *buf, uint32_t len); /**< Pointer to @ref XMC_USBD_EndpointWrite : Write data to USB Endpoint.*/ + + + XMC_USBD_STATUS_t (*EndpointAbort) (uint8_t ep_addr); /**< Pointer to @ref XMC_USBD_EndpointAbort : Abort current USB Endpoint transfer.*/ + + + uint16_t (*GetFrameNumber) (void); /**< Pointer to @ref XMC_USBD_GetFrameNumber : Get current USB Frame Number.*/ + + + uint32_t (*IsEnumDone) (void); /**< Pointer to @ref XMC_USBD_IsEnumDone : Is enumeration done in Host?.*/ +} const XMC_USBD_DRIVER_t; + +/** + * Defines the driver interface function table. + * To access the XMC device controller driver interface use this table of functions. + **/ +extern const XMC_USBD_DRIVER_t Driver_USBD0; + + +/** + * Defines the XMC USB device data + * The instance of ::XMC_USBD_DEVICE_t structure describing the XMC device. + **/ +extern XMC_USBD_DEVICE_t xmc_device; + +/********************************************************************************************************************** + * API PROTOTYPES + *********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param None. + * + * @return None. + * + * \parDescription:
+ * Enables the USB module in the XMC controller.
+ * It de-asserts the peripheral reset on USB0 module and enables the USB power. + * + * \parNote:
+ * This API is called inside the XMC_USBD_Init().\n + * + * \parRelated APIs:
+ * XMC_USBD_Disable()\n + **/ +void XMC_USBD_Enable(void); + +/** + * @param None. + * + * @return None. + * + * \parDescription:
+ * Disables the USB module in the XMC controller.
+ * It asserts the peripheral reset on USB0 module and disables the USB power. + * + * \parRelated APIs:
+ * XMC_USBD_Enable()\n + **/ +void XMC_USBD_Disable(void); + +/** + * @param event The single event that needs to be cleared. Use ::XMC_USBD_EVENT_t as argument.\n + * + * @return None. + * + * \parDescription:
+ * Clears the selected USBD \a event.
+ * It clears the event by writing to the GINTSTS register. + * + * \parNote:
+ * This API is called inside the USB interrupt handler to clear the event XMC_USBD_EVENT_t + * and maintain the device state machine.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_ClearEventOUTEP(),::XMC_USBD_ClearEventINEP()\n + **/ +void XMC_USBD_ClearEvent(XMC_USBD_EVENT_t event); + + +/** + * @param event The single event or multiple events that need to be cleared. + * + * @param ep_num The IN endpoint number on which the events to be cleared. + * + * @return None. + * + * \parDescription:
+ * Clears the single event or multiple events of the selected IN endpoint.
+ * The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_IN_EP_t elements.\n + * It clears the event by programming DIEPINT register.\n + * + * \parNote:
+ * This API is called inside the USB IN EP interrupt handler to clear the ::XMC_USBD_EVENT_IN_EP_t event + * and maintain the device state machine.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_ClearEventOUTEP()\n + **/ +void XMC_USBD_ClearEventINEP(uint32_t event,uint8_t ep_num); + + +/** + * @param event The single event or multiple events that need to be cleared. + * + * @param ep_num The OUT endpoint number on which the events to be cleared. + * + * @return None. + * + * \parDescription:
+ * Clears the single \a event or multiple events of the selected OUT endpoint.
+ * The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_OUT_EP_t elements. + * It clears the event by writing to DOEPINT register. + * + * \parNote:
+ * This API is called inside the USB OUT EP interrupt handler to clear the ::XMC_USBD_EVENT_OUT_EP_t event + * and maintain the device state machine.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_ClearEventINEP()\n + **/ +void XMC_USBD_ClearEventOUTEP(uint32_t event,uint8_t ep_num); + +/** + * @param event The single event or multiple events that need to be enabled. + * + * @return None. + * + * \parDescription:
+ * Enables the event or multiple events of the OUT endpoints.
+ * The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_OUT_EP_t elements. + * It enables the event by programming DOEPMSK register. + * + * \parNote:
+ * This API is called inside the ::XMC_USBD_Init() to enable the OUT EP interrupts.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_EnableEventINEP()\n + **/ +void XMC_USBD_EnableEventOUTEP(uint32_t event); + +/** + * @param event The single event or multiple events that need to be enabled. + * + * @return None. + * + * \parDescription:
+ * Enables the \a event or multiple events of the USB IN endpoints.
+ * The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_IN_EP_t elements. + * It enables the event by programming DIEPMSK register. + * + * \parNote:
+ * This API is called inside the ::XMC_USBD_Init() to enable the IN EP interrupts.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_EnableEventOUTEP()\n + **/ +void XMC_USBD_EnableEventINEP(uint32_t event); + +/** + * @param None. + * + * @return ::XMC_USBD_CAPABILITIES_t. + * + * \parDescription:
+ * Retrieves the USB device capabilities of type \a XMC_USBD_CAPABILITIES_t
+ * The USB device capabilities supported by the USBD driver, like power on/off, connect/disconnect, + * reset,suspend/resume,USB speed etc are retrieved. + * + * It can be called after initializing the USB device to get the information on the USBD capabilities. + * + **/ +XMC_USBD_CAPABILITIES_t XMC_USBD_GetCapabilities(void); + + +/** + * @param obj The pointer to the USB device handle ::XMC_USBD_t. + * + * @return XMC_USBD_STATUS_t The USB device status of type ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Initializes the USB device to get ready for connect to USB host.
+ * Enables the USB module,sets the EP buffer sizes,registers the device and EP event call backs. + * Initializes the global,device and FIFO register base addresses. + * Configures the global AHB,enables the global interrupt and DMA by programming GAHBCFG register. + * Configures the USB in to device mode and enables the session request protocol by programming GUSBCFG register. + * Configures the USB device speed to full speed by programming DCFG register. + * Disconnects the USB device by programming DCTL register. + * Enables the USB common and device interrupts by programming GINTMSK register. + * + * \parNote:
+ * This API makes the USB device ready to connect to host.The user has to explicitly call + * the ::XMC_USBD_DeviceConnect() after the USB initialization to connect to USB host.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_DeviceConnect()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_Init(XMC_USBD_t *obj); + +/** + * @param None. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Uninitialises the USB device.
+ * Disconnects the USB device by programming DCTL register and resets the XMC USB device data. + * + * \parNote:
+ * Once this API is called, USB device will not be accessible from host.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_Init()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_Uninitialize(void); + +/** + * @param None. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Connects the USB device to host and triggers the USB enumeration.
+ * Connects the USB device to host by programming DCTL register.\n + * It resets the soft disconnect bit, which activates the speed pull up at d+ line of USB. + * ::XMC_USBD_Init() should be called before calling this API. + * + * \parNote:
+ * Once this API is called, USB host starts the enumeration process and the device should + * handle the descriptor requests.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_Init()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceConnect(void); + +/** + * @param None. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Disconnects the USB device from host.
+ * By programming DCTL register, it sets the soft disconnect bit, which deactivates\n + * the speed pull up at d+ line of USB. + * + * \parNote:
+ * Once this API is called, USB device will not be accessible from host.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_DeviceConnect()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceDisconnect(void); + +/** + * @param obj The pointer to the USB device handle structure \a XMC_USBD_t. + * + * @return ::XMC_USBD_STATE_t. + * + * \parDescription:
+ * Retrieves the current USB device state.
+ * Power,active,speed and connection status data are retrieved.\n + * + * \parNote:
+ * Before calling this API, USB should be initialized with ::XMC_USBD_Init.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_Init()\n + **/ +XMC_USBD_STATE_t XMC_USBD_DeviceGetState(const XMC_USBD_t *const obj); + + +/** + * @param address The address to be set for the USB device . + * @param stage The device request stage-setup or status ::XMC_USBD_SET_ADDRESS_STAGE_t. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Sets the USB device address.
+ * The device address is programmed in the DCFG register.
+ * + * The address should be more than 0; as 0 is the default USB device address at the starting of enumeration. + * As part of enumeration, host sends the control request to the device to set the USB address; and in turn,\n + * in the USB device event call back handler, user has to set the address using this API for the set address request.
+ * + * The stage parameter should be XMC_USBD_SET_ADDRESS_STAGE_SETUP from the enum ::XMC_USBD_SET_ADDRESS_STAGE_t. + * + * \parNote:
+ * Before calling this API, USB should be initialized with ::XMC_USBD_Init () and connected to + * USB host using ::XMC_USBD_DeviceConnect() \n + * + * \parRelated APIs:
+ * ::XMC_USBD_Init(), ::XMC_USBD_DeviceConnect()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceSetAddress(uint8_t address,XMC_USBD_SET_ADDRESS_STAGE_t stage); + +/** + * @param ep_addr The address of the USB endpoint, which needs to be configured. + * @param ep_type The ::XMC_USBD_ENDPOINT_TYPE_t. + * @param ep_max_packet_size The maximum packet size of endpoint in USB full speed. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Configures the USB endpoint.
+ * The endpoint is configured by programming the DAINT,DIEPCTL and DOEPCTL registers.
+ * + * Configures the EP type, FIFO number,maximum packet size, enables endpoint and sets the DATA0 PID. + * This function also initializes the internal buffer handling for the specified endpoint, + * but does not start any transfers.
+ * + * As part of enumeration, host sends the control request to the device to set the configuration; and in turn,\n + * in the USB device event call back handler, user has to set the configuration and configure the endpoints \n + * required for the device.\n + * + * \parNote:
+ * This API should only be used as part of enumeration.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_Init(),::XMC_USBD_DeviceConnect(),::XMC_USBD_EndpointUnconfigure()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointConfigure(uint8_t ep_addr, + XMC_USBD_ENDPOINT_TYPE_t ep_type, + uint16_t ep_max_packet_size); + +/** + * @param ep_addr The address of the USB endpoint, which needs to be unconfigured. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Unconfigures the USB endpoint.
+ * The endpoint is unconfigured by programming the DAINT,DIEPCTL and DOEPCTL registers.\n + * Disables the endpoint, unassign the fifo, deactivate it and only send nacks.\n + * Waits until the endpoint has finished operation and disables it. All (eventuallly) allocated buffers gets freed. + * Forces the endpoint to stop immediately, any pending transfers are killed(Can cause device reset). + * + * \parRelated APIs:
+ * ::XMC_USBD_EndpointConfigure()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointUnconfigure(uint8_t ep_addr); + +/** + * @param ep_addr The address of the USB endpoint, on which stall needs to be set or cleared. + * @param stall The boolean variable to decide on set or clear of stall on EP. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Set or Clear stall on the USB endpoint \a ep_addr, based on \a stall parameter.
+ * + * By programming stall bit in the doepctl and diepctl, it sets or clears the stall on the endpoint. + * The endpoint can be stalled when a non supported request comes from the USB host. + * The XMC_USBD_EndpointStall() should be called with \a stall set to 0, in the clear feature standard request + * in the USB device event call back handler. * + * + * \parNote:
+ * The host should clear the stall set on the endpoint by sending the clear feature standard + * request on the non EP0 endpoints. On EP0, the stall will automatically gets cleared on the next control request.\n + * + * \parRelated APIs:
+ * ::XMC_USBD_EndpointAbort()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointStall(uint8_t ep_addr, bool stall); + + +/** + * @param ep_addr The address of the USB endpoint, from which data need to be read. + * @param size The number of bytes to be read. + * + * @return ::XMC_USBD_STATUS_t. + * + * \parDescription:
+ * Prepares an endpoint to receive OUT tokens from the USB host.
+ * The selected endpoint gets configured, so that it receives the specified amount of data from the host. + * As part of streaming of OUT data, after reading the current OUT buffer using ::XMC_USBD_EndpointRead(),\n + * user can prepare endpoint for the next OUT packet by using ::XMC_USBD_EndpointReadStart(). + * + * The registers DOEPDMA,DOEPTSIZ and DOEPCTL are programmed to start a new read request. + * + * \parNote:
+ * For the data received on OUT EP buffer, use ::XMC_USBD_EndpointRead().\n + * + * \parRelated APIs:
+ * XMC_USBD_EndpointRead()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointReadStart(const uint8_t ep_addr, uint32_t size); + + +/** + * @param ep_addr The address of the USB OUT endpoint, from which data need to be read. + * @param buffer The pointer to the user buffer,in which data need to be received. + * @param length The number of bytes to be read from OUT EP. + * + * @return
+ * The actual number of bytes received. + * + * \parDescription:
+ * Read \a length number of bytes from an OUT endpoint \a ep_addr.
+ * If data has been received for this endpoint, it gets copied into the user buffer until its full + * or no data is left in the driver buffer. + * + * \parNote:
+ * For preparing the next OUT token, use ::XMC_USBD_EndpointReadStart() after ::XMC_USBD_EndpointRead().\n + * + * + * \parRelated APIs:
+ * ::XMC_USBD_EndpointReadStart()\n + **/ +int32_t XMC_USBD_EndpointRead(const uint8_t ep_addr,uint8_t * buffer, uint32_t length); + + +/** + * @param ep_addr The address of the USB IN endpoint, on which data should be sent. + * @param buffer The pointer to the data buffer, to write to the endpoint. + * @param length The number of bytes to be written to IN EP. + * + * @return
+ * The actual amount of data written to the endpoint buffer. + * + * \parDescription:
+ * Write the \a length bytes of data to an IN endpoint \a ep_addr.
+ * The User data gets copied into the driver buffer or will be send directly based on the buffer concept + * selected in the ::XMC_USBD_TRANSFER_MODE_t configuration. + * + * Then the endpoint is set up to transfer the data to the host.\n + * DIEPDMA,DIEPTSIZ and DIEPCTL registers are programmed to start the IN transfer. + * + * + * \parRelated APIs:
+ * ::XMC_USBD_EndpointRead()\n + **/ +int32_t XMC_USBD_EndpointWrite(const uint8_t ep_addr,const uint8_t * buffer,uint32_t length); + + +/** + * @param ep_addr The address of the USB endpoint, on which the data need to be aborted. + * + * @return ::XMC_USBD_STATUS_t + * + * \parDescription:
+ * Abort the transfer on endpoint \a ep_addr.
+ * On any failure with the USB transmission user can reset the endpoint into default state and clear all + * assigned buffers, to start from a clean point. The endpoint will not be unconfigured or disabled. + * + * \parRelated APIs:
+ * ::XMC_USBD_EndpointUnconfigure()\n + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointAbort(uint8_t ep_addr); + +/** + * @param None. + * + * @return The 16 bit current USB frame number. + * + * \parDescription:
+ * Read the current USB frame number.
* + * Reads the device status register (DSTS) and returns the SOFFN field. + * + **/ +uint16_t XMC_USBD_GetFrameNumber(void); + +/** + * @param None. + * + * @return Returns 1, if the speed enumeration is done and 0 otherwise. + * + * \parDescription:
+ * Gets the speed enumeration completion status of the USB device.
+ * + * \parNote:
+ * This should not be used for the actual USB enumeration completion status. For the actual USB enumeration status, + * the application layer should check for the completion of USB standard request 'Set configuration'.\n + * + **/ +uint32_t XMC_USBD_IsEnumDone(void); + + +/** + * @param obj The pointer to the USB device handle structure. + * + * @return None. + * + * \parDescription:
+ * USB device default IRQ handler.
+ * USBD Peripheral LLD provides default implementation of ISR. + * The user needs to explicitly either use our default implementation or use its own one using the LLD APIs. + * + * For example: + * XMC_USBD_t *obj; + * void USB0_0_IRQHandler(void) + * { + * XMC_USBD_IRQHandler(obj); + * } + * + * \parNote:
+ * The user should initialize the XMC USB device configuration structure before calling + * ::XMC_USBD_IRQHandler() in the actual USB0 IRQ handler. + * + **/ +void XMC_USBD_IRQHandler(const XMC_USBD_t *const obj); + +#ifdef __cplusplus +} +#endif + +/** + * MISRA C 2004 Deviations + * + * 1. Function like macro- defined- MISRA Advisory Rule 19.7 + * 2. usage of unions - MISRA Required Rule 18.4 + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(USB0) */ + +#endif /* XMC_USBD_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usbd_regs.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usbd_regs.h new file mode 100644 index 00000000..df31cb45 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usbd_regs.h @@ -0,0 +1,2595 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ + * $Revision: #91 $ + * $Date: 2010/11/29 $ + * $Change: 1636033 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +/* + * @file xmc_usbd_regs.h + * @date 2015-02-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial version + * + * @endcond + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + + +/** + * @file + * + * This file contains the data structures for accessing the DWC_otg core registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/** Register Definitions */ +/** Maximum endpoint channel */ +#define MAX_EPS_CHANNELS ( 7U ) +/** Maximum periodic fifos in usb core */ +#define MAX_PERIO_FIFOS ( 1U ) +/** Maximum tx fifos */ +#define MAX_TX_FIFOS ( 14U ) +/* dwc_dma_t type definition and register header file inclusion */ +typedef void* dwc_dma_t; + +/****************************************************************************/ +/** DWC_otg Core registers . + * The dwc_otg_core_global_regs structure defines the size + * and relative field offsets for the Core Global registers. + */ +typedef struct dwc_otg_core_global_regs { + /** OTG Control and Status Register. Offset: 000h */ + volatile uint32_t gotgctl; + /** OTG Interrupt Register. Offset: 004h */ + volatile uint32_t gotgint; + /**Core AHB Configuration Register. Offset: 008h */ + volatile uint32_t gahbcfg; + +#define DWC_GLBINTRMASK 0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 +#define DWC_PTXEMPTYLVL_EMPTY 0x0100 +#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 + + /**Core USB Configuration Register. Offset: 00Ch */ + volatile uint32_t gusbcfg; + /**Core Reset Register. Offset: 010h */ + volatile uint32_t grstctl; + /**Core Interrupt Register. Offset: 014h */ + volatile uint32_t gintsts; + /**Core Interrupt Mask Register. Offset: 018h */ + volatile uint32_t gintmsk; + /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ + volatile uint32_t grxstsr; + /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ + volatile uint32_t grxstsp; + /**Receive FIFO Size Register. Offset: 024h */ + volatile uint32_t grxfsiz; + /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ + volatile uint32_t gnptxfsiz; + /**Non Periodic Transmit FIFO/Queue Status Register (Read + * Only). Offset: 02Ch */ + volatile uint32_t gnptxsts; + /**I2C Access Register. Offset: 030h */ + volatile uint32_t gi2cctl; + /**PHY Vendor Control Register. Offset: 034h */ + volatile uint32_t gpvndctl; + /**General Purpose Input/Output Register. Offset: 038h */ + volatile uint32_t ggpio; + /**User ID Register. Offset: 03Ch */ + volatile uint32_t guid; + /**Synopsys ID Register (Read Only). Offset: 040h */ + volatile uint32_t gsnpsid; + /**User HW Config1 Register (Read Only). Offset: 044h */ + volatile uint32_t ghwcfg1; + /**User HW Config2 Register (Read Only). Offset: 048h */ + volatile uint32_t ghwcfg2; +#define DWC_SLAVE_ONLY_ARCH 0 +#define DWC_EXT_DMA_ARCH 1 +#define DWC_INT_DMA_ARCH 2 + +#define DWC_MODE_HNP_SRP_CAPABLE 0 +#define DWC_MODE_SRP_ONLY_CAPABLE 1 +#define DWC_MODE_NO_HNP_SRP_CAPABLE 2 +#define DWC_MODE_SRP_CAPABLE_DEVICE 3 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 +#define DWC_MODE_SRP_CAPABLE_HOST 5 +#define DWC_MODE_NO_SRP_CAPABLE_HOST 6 + + /**User HW Config3 Register (Read Only). Offset: 04Ch */ + volatile uint32_t ghwcfg3; + /**User HW Config4 Register (Read Only). Offset: 050h*/ + volatile uint32_t ghwcfg4; + /** Core LPM Configuration register Offset: 054h*/ + volatile uint32_t glpmcfg; + /** Global PowerDn Register Offset: 058h */ + volatile uint32_t gpwrdn; + /** Global DFIFO SW Config Register Offset: 05Ch */ + volatile uint32_t gdfifocfg; + /** ADP Control Register Offset: 060h */ + volatile uint32_t adpctl; + /** Reserved Offset: 064h-0FFh */ + volatile uint32_t reserved39[39]; + /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ + volatile uint32_t hptxfsiz; + /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, + otherwise Device Transmit FIFO#n Register. + * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ + volatile uint32_t dtxfsiz[15]; +} dwc_otg_core_global_regs_t; + +/** + * This union represents the bit fields of the Core OTG Control + * and Status Register (GOTGCTL). Set the bits using the bit + * fields then write the d32 value to the register. + */ +typedef union gotgctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned sesreqscs:1; + unsigned sesreq:1; + unsigned vbvalidoven:1; + unsigned vbvalidovval:1; + unsigned avalidoven:1; + unsigned avalidovval:1; + unsigned bvalidoven:1; + unsigned bvalidovval:1; + unsigned hstnegscs:1; + unsigned hnpreq:1; + unsigned hstsethnpen:1; + unsigned devhnpen:1; + unsigned reserved12_15:4; + unsigned conidsts:1; + unsigned dbnctime:1; + unsigned asesvld:1; + unsigned bsesvld:1; + unsigned otgver:1; + unsigned reserved1:1; + unsigned multvalidbc:5; + unsigned chirpen:1; + unsigned reserved28_31:4; + } b; +} gotgctl_data_t; + +/** + * This union represents the bit fields of the Core OTG Interrupt Register + * (GOTGINT). Set/clear the bits using the bit fields then write the d32 + * value to the register. + */ +typedef union gotgint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Current Mode */ + unsigned reserved0_1:2; + + /** Session End Detected */ + unsigned sesenddet:1; + + unsigned reserved3_7:5; + + /** Session Request Success Status Change */ + unsigned sesreqsucstschng:1; + /** Host Negotiation Success Status Change */ + unsigned hstnegsucstschng:1; + + unsigned reserved10_16:7; + + /** Host Negotiation Detected */ + unsigned hstnegdet:1; + /** A-Device Timeout Change */ + unsigned adevtoutchng:1; + /** Debounce Done */ + unsigned debdone:1; + /** Multi-Valued input changed */ + unsigned mvic:1; + + + unsigned reserved31_21:11; + + } b; +} gotgint_data_t; + +/** + * This union represents the bit fields of the Core AHB Configuration + * Register (GAHBCFG). Set/clear the bits using the bit fields then + * write the d32 value to the register. + */ +typedef union gahbcfg_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned glblintrmsk:1; +#define DWC_GAHBCFG_GLBINT_ENABLE 1 + + unsigned hburstlen:4; +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 + + unsigned dmaenable:1; +#define DWC_GAHBCFG_DMAENABLE 1 + unsigned reserved:1; + unsigned nptxfemplvl_txfemplvl:1; + unsigned ptxfemplvl:1; +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 + unsigned reserved9_20:12; + unsigned remmemsupp:1; + unsigned notialldmawrit:1; + unsigned reserved23_31:9; + } b; +} gahbcfg_data_t; + +/** + * This union represents the bit fields of the Core USB Configuration + * Register (GUSBCFG). Set the bits using the bit fields then write + * the d32 value to the register. + */ +typedef union gusbcfg_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned toutcal:3; + unsigned phyif:1; + unsigned ulpi_utmi_sel:1; + unsigned fsintf:1; + unsigned physel:1; + unsigned ddrsel:1; + unsigned srpcap:1; + unsigned hnpcap:1; + unsigned usbtrdtim:4; + unsigned reserved1:1; + unsigned phylpwrclksel:1; + unsigned otgutmifssel:1; + unsigned ulpi_fsls:1; + unsigned ulpi_auto_res:1; + unsigned ulpi_clk_sus_m:1; + unsigned ulpi_ext_vbus_drv:1; + unsigned ulpi_int_vbus_indicator:1; + unsigned term_sel_dl_pulse:1; + unsigned indicator_complement:1; + unsigned indicator_pass_through:1; + unsigned ulpi_int_prot_dis:1; + unsigned ic_usb_cap:1; + unsigned ic_traffic_pull_remove:1; + unsigned tx_end_delay:1; + unsigned force_host_mode:1; + unsigned force_dev_mode:1; + unsigned reserved31:1; + } b; +} gusbcfg_data_t; + +/** + * This union represents the bit fields of the Core Reset Register + * (GRSTCTL). Set/clear the bits using the bit fields then write the + * d32 value to the register. + */ +typedef union grstctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Core Soft Reset (CSftRst) (Device and Host) + * + * The application can flush the control logic in the + * entire core using this bit. This bit resets the + * pipelines in the AHB Clock domain as well as the + * PHY Clock domain. + * + * The state machines are reset to an IDLE state, the + * control bits in the CSRs are cleared, all the + * transmit FIFOs and the receive FIFO are flushed. + * + * The status mask bits that control the generation of + * the interrupt, are cleared, to clear the + * interrupt. The interrupt status bits are not + * cleared, so the application can get the status of + * any events that occurred in the core after it has + * set this bit. + * + * Any transactions on the AHB are terminated as soon + * as possible following the protocol. Any + * transactions on the USB are terminated immediately. + * + * The configuration settings in the CSRs are + * unchanged, so the software doesn't have to + * reprogram these registers (Device + * Configuration/Host Configuration/Core System + * Configuration/Core PHY Configuration). + * + * The application can write to this bit, any time it + * wants to reset the core. This is a self clearing + * bit and the core clears this bit after all the + * necessary logic is reset in the core, which may + * take several clocks, depending on the current state + * of the core. + */ + unsigned csftrst:1; + /** Hclk Soft Reset + * + * The application uses this bit to reset the control logic in + * the AHB clock domain. Only AHB clock domain pipelines are + * reset. + */ + unsigned hsftrst:1; + /** Host Frame Counter Reset (Host Only)
+ * + * The application can reset the (micro)frame number + * counter inside the core, using this bit. When the + * (micro)frame counter is reset, the subsequent SOF + * sent out by the core, will have a (micro)frame + * number of 0. + */ + unsigned hstfrm:1; + /** In Token Sequence Learning Queue Flush + * (INTknQFlsh) (Device Only) + */ + unsigned intknqflsh:1; + /** RxFIFO Flush (RxFFlsh) (Device and Host) + * + * The application can flush the entire Receive FIFO + * using this bit. The application must first + * ensure that the core is not in the middle of a + * transaction. The application should write into + * this bit, only after making sure that neither the + * DMA engine is reading from the RxFIFO nor the MAC + * is writing the data in to the FIFO. The + * application should wait until the bit is cleared + * before performing any other operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) + * to clear. + */ + unsigned rxfflsh:1; + /** TxFIFO Flush (TxFFlsh) (Device and Host). + * + * This bit is used to selectively flush a single or + * all transmit FIFOs. The application must first + * ensure that the core is not in the middle of a + * transaction. The application should write into + * this bit, only after making sure that neither the + * DMA engine is writing into the TxFIFO nor the MAC + * is reading the data out of the FIFO. The + * application should wait until the core clears this + * bit, before performing any operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) + * to clear. + */ + unsigned txfflsh:1; + + /** TxFIFO Number (TxFNum) (Device and Host). + * + * This is the FIFO number which needs to be flushed, + * using the TxFIFO Flush bit. This field should not + * be changed until the TxFIFO Flush bit is cleared by + * the core. + * - 0x0 : Non Periodic TxFIFO Flush + * - 0x1 : Periodic TxFIFO #1 Flush in device mode + * or Periodic TxFIFO in host mode + * - 0x2 : Periodic TxFIFO #2 Flush in device mode. + * - ... + * - 0xF : Periodic TxFIFO #15 Flush in device mode + * - 0x10: Flush all the Transmit NonPeriodic and + * Transmit Periodic FIFOs in the core + */ + unsigned txfnum:5; + /** Reserved */ + unsigned reserved11_29:19; + /** DMA Request Signal. Indicated DMA request is in + * probress. Used for debug purpose. */ + unsigned dmareq:1; + /** AHB Master Idle. Indicates the AHB Master State + * Machine is in IDLE condition. */ + unsigned ahbidle:1; + } b; +} grstctl_t; + +/** + * This union represents the bit fields of the Core Interrupt Mask + * Register (GINTMSK). Set/clear the bits using the bit fields then + * write the d32 value to the register. + */ +typedef union gintmsk_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved0:1; + unsigned modemismatch:1; + unsigned otgintr:1; + unsigned sofintr:1; + unsigned rxstsqlvl:1; + unsigned nptxfempty:1; + unsigned ginnakeff:1; + unsigned goutnakeff:1; + unsigned ulpickint:1; + unsigned i2cintr:1; + unsigned erlysuspend:1; + unsigned usbsuspend:1; + unsigned usbreset:1; + unsigned enumdone:1; + unsigned isooutdrop:1; + unsigned eopframe:1; + unsigned restoredone:1; + unsigned epmismatch:1; + unsigned inepintr:1; + unsigned outepintr:1; + unsigned incomplisoin:1; + unsigned incomplisoout:1; + unsigned fetsusp:1; + unsigned resetdet:1; + unsigned portintr:1; + unsigned hcintr:1; + unsigned ptxfempty:1; + unsigned lpmtranrcvd:1; + unsigned conidstschng:1; + unsigned disconnect:1; + unsigned sessreqintr:1; + unsigned wkupintr:1; + } b; +} gintmsk_data_t; +/** + * This union represents the bit fields of the Core Interrupt Register + * (GINTSTS). Set/clear the bits using the bit fields then write the + * d32 value to the register. + */ +typedef union gintsts_data { + /** raw register data */ + uint32_t d32; +#define DWC_SOF_INTR_MASK 0x0008 + /** register bits */ + struct { +#define DWC_HOST_MODE 1 + unsigned curmode:1; + unsigned modemismatch:1; + unsigned otgintr:1; + unsigned sofintr:1; + unsigned rxstsqlvl:1; + unsigned nptxfempty:1; + unsigned ginnakeff:1; + unsigned goutnakeff:1; + unsigned ulpickint:1; + unsigned i2cintr:1; + unsigned erlysuspend:1; + unsigned usbsuspend:1; + unsigned usbreset:1; + unsigned enumdone:1; + unsigned isooutdrop:1; + unsigned eopframe:1; + unsigned restoredone:1; + unsigned epmismatch:1; + unsigned inepint:1; + unsigned outepintr:1; + unsigned incomplisoin:1; + unsigned incomplisoout:1; + unsigned fetsusp:1; + unsigned resetdet:1; + unsigned portintr:1; + unsigned hcintr:1; + unsigned ptxfempty:1; + unsigned lpmtranrcvd:1; + unsigned conidstschng:1; + unsigned disconnect:1; + unsigned sessreqintr:1; + unsigned wkupintr:1; + } b; +} gintsts_data_t; + +/** + * This union represents the bit fields in the Device Receive Status Read and + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 + * element then read out the bits using the bit elements. + */ +typedef union device_grxsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned epnum:4; + unsigned bcnt:11; + unsigned dpid:2; + +#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet +#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete + +#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK +#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete +#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet + unsigned pktsts:4; + unsigned fn:4; + unsigned reserved25_31:7; + } b; +} device_grxsts_data_t; + +/** + * This union represents the bit fields in the Host Receive Status Read and + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 + * element then read out the bits using the bit elements. + */ +typedef union host_grxsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned chnum:4; + unsigned bcnt:11; + unsigned dpid:2; + + unsigned pktsts:4; +#define DWC_GRXSTS_PKTSTS_IN 0x2 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 +#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 + + unsigned reserved21_31:11; + } b; +} host_grxsts_data_t; + +/** + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, + * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the d32 element then + * read out the bits using the bit elements. + */ +typedef union fifosize_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned startaddr:16; + unsigned depth:16; + } b; +} fifosize_data_t; + +/** + * This union represents the bit fields in the Non-Periodic Transmit + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the + * d32 element then read out the bits using the bit + * elements. + */ +typedef union gnptxsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned nptxfspcavail:16; + unsigned nptxqspcavail:8; + /** Top of the Non-Periodic Transmit Request Queue + * - bit 24 - Terminate (Last entry for the selected + * channel/EP) + * - bits 26:25 - Token Type + * - 2'b00 - IN/OUT + * - 2'b01 - Zero Length OUT + * - 2'b10 - PING/Complete Split + * - 2'b11 - Channel Halt + * - bits 30:27 - Channel/EP Number + */ + unsigned nptxqtop_terminate:1; + unsigned nptxqtop_token:2; + unsigned nptxqtop_chnep:4; + unsigned reserved:1; + } b; +} gnptxsts_data_t; + +/** + * This union represents the bit fields in the Transmit + * FIFO Status Register (DTXFSTS). Read the register into the + * d32 element then read out the bits using the bit + * elements. + */ +typedef union dtxfsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned txfspcavail:16; + unsigned reserved:16; + } b; +} dtxfsts_data_t; + +/** + * This union represents the bit fields in the I2C Control Register + * (I2CCTL). Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union gi2cctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned rwdata:8; + unsigned regaddr:8; + unsigned addr:7; + unsigned i2cen:1; + unsigned ack:1; + unsigned i2csuspctl:1; + unsigned i2cdevaddr:2; + unsigned i2cdatse0:1; + unsigned reserved:1; + unsigned rw:1; + unsigned bsydne:1; + } b; +} gi2cctl_data_t; + +/** + * This union represents the bit fields in the PHY Vendor Control Register + * (GPVNDCTL). Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union gpvndctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned regdata:8; + unsigned vctrl:8; + unsigned regaddr16_21:6; + unsigned regwr:1; + unsigned reserved23_24:2; + unsigned newregreq:1; + unsigned vstsbsy:1; + unsigned vstsdone:1; + unsigned reserved28_30:3; + unsigned disulpidrvr:1; + } b; +} gpvndctl_data_t; + +/** + * This union represents the bit fields in the General Purpose + * Input/Output Register (GGPIO). + * Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union ggpio_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned gpi:16; + unsigned gpo:16; + } b; +} ggpio_data_t; + +/** + * This union represents the bit fields in the User ID Register + * (GUID). Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union guid_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned rwdata:32; + } b; +} guid_data_t; + +/** + * This union represents the bit fields in the Synopsys ID Register + * (GSNPSID). Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union gsnpsid_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned rwdata:32; + } b; +} gsnpsid_data_t; + +/** + * This union represents the bit fields in the User HW Config1 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg1_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned ep_dir0:2; + unsigned ep_dir1:2; + unsigned ep_dir2:2; + unsigned ep_dir3:2; + unsigned ep_dir4:2; + unsigned ep_dir5:2; + unsigned ep_dir6:2; + unsigned ep_dir7:2; + unsigned ep_dir8:2; + unsigned ep_dir9:2; + unsigned ep_dir10:2; + unsigned ep_dir11:2; + unsigned ep_dir12:2; + unsigned ep_dir13:2; + unsigned ep_dir14:2; + unsigned ep_dir15:2; + } b; +} hwcfg1_data_t; + +/** + * This union represents the bit fields in the User HW Config2 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg2_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /* GHWCFG2 */ + unsigned op_mode:3; +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 + + unsigned architecture:2; + unsigned point2point:1; + unsigned hs_phy_type:2; +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 + + unsigned fs_phy_type:2; + unsigned num_dev_ep:4; + unsigned num_host_chan:4; + unsigned perio_ep_supported:1; + unsigned dynamic_fifo:1; + unsigned multi_proc_int:1; + unsigned reserved21:1; + unsigned nonperio_tx_q_depth:2; + unsigned host_perio_tx_q_depth:2; + unsigned dev_token_q_depth:5; + unsigned otg_enable_ic_usb:1; + } b; +} hwcfg2_data_t; + +/** + * This union represents the bit fields in the User HW Config3 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg3_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /* GHWCFG3 */ + unsigned xfer_size_cntr_width:4; + unsigned packet_size_cntr_width:3; + unsigned otg_func:1; + unsigned i2c:1; + unsigned vendor_ctrl_if:1; + unsigned optional_features:1; + unsigned synch_reset_type:1; + unsigned adp_supp:1; + unsigned otg_enable_hsic:1; + unsigned otg_ver_support:1; + unsigned otg_lpm_en:1; + unsigned dfifo_depth:16; + } b; +} hwcfg3_data_t; + +/** + * This union represents the bit fields in the User HW Config4 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg4_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned num_dev_perio_in_ep:4; + unsigned power_optimiz:1; + unsigned min_ahb_freq:1; + unsigned part_power_down:1; + unsigned reserved:7; + unsigned utmi_phy_data_width:2; + unsigned num_dev_mode_ctrl_ep:4; + unsigned iddig_filt_en:1; + unsigned vbus_valid_filt_en:1; + unsigned a_valid_filt_en:1; + unsigned b_valid_filt_en:1; + unsigned session_end_filt_en:1; + unsigned ded_fifo_en:1; + unsigned num_in_eps:4; + unsigned desc_dma:1; + unsigned desc_dma_dyn:1; + } b; +} hwcfg4_data_t; + +/** + * This union represents the bit fields of the Core LPM Configuration + * Register (GLPMCFG). Set the bits using bit fields then write + * the d32 value to the register. + */ +typedef union glpmctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** LPM-Capable (LPMCap) (Device and Host) + * The application uses this bit to control + * the DWC_otg core LPM capabilities. + */ + unsigned lpm_cap_en:1; + /** LPM response programmed by application (AppL1Res) (Device) + * Handshake response to LPM token pre-programmed + * by device application software. + */ + unsigned appl_resp:1; + /** Host Initiated Resume Duration (HIRD) (Device and Host) + * In Host mode this field indicates the value of HIRD + * to be sent in an LPM transaction. + * In Device mode this field is updated with the + * Received LPM Token HIRD bmAttribute + * when an ACK/NYET/STALL response is sent + * to an LPM transaction. + */ + unsigned hird:4; + /** RemoteWakeEnable (bRemoteWake) (Device and Host) + * In Host mode this bit indicates the value of remote + * wake up to be sent in wIndex field of LPM transaction. + * In Device mode this field is updated with the + * Received LPM Token bRemoteWake bmAttribute + * when an ACK/NYET/STALL response is sent + * to an LPM transaction. + */ + unsigned rem_wkup_en:1; + /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) + * The application uses this bit to control + * the utmi_sleep_n assertion to the PHY when in L1 state. + */ + unsigned en_utmi_sleep:1; + /** HIRD Threshold (HIRD_Thres) (Device and Host) + */ + unsigned hird_thres:5; + /** LPM Response (CoreL1Res) (Device and Host) + * In Host mode this bit contains handsake response to + * LPM transaction. + * In Device mode the response of the core to + * LPM transaction received is reflected in these two bits. + - 0x0 : ERROR (No handshake response) + - 0x1 : STALL + - 0x2 : NYET + - 0x3 : ACK + */ + unsigned lpm_resp:2; + /** Port Sleep Status (SlpSts) (Device and Host) + * This bit is set as long as a Sleep condition + * is present on the USB bus. + */ + unsigned prt_sleep_sts:1; + /** Sleep State Resume OK (L1ResumeOK) (Device and Host) + * Indicates that the application or host + * can start resume from Sleep state. + */ + unsigned sleep_state_resumeok:1; + /** LPM channel Index (LPM_Chnl_Indx) (Host) + * The channel number on which the LPM transaction + * has to be applied while sending + * an LPM transaction to the local device. + */ + unsigned lpm_chan_index:4; + /** LPM Retry Count (LPM_Retry_Cnt) (Host) + * Number host retries that would be performed + * if the device response was not valid response. + */ + unsigned retry_count:3; + /** Send LPM Transaction (SndLPM) (Host) + * When set by application software, + * an LPM transaction containing two tokens + * is sent. + */ + unsigned send_lpm:1; + /** LPM Retry status (LPM_RetryCnt_Sts) (Host) + * Number of LPM Host Retries still remaining + * to be transmitted for the current LPM sequence + */ + unsigned retry_count_sts:3; + unsigned reserved28_29:2; + /** In host mode once this bit is set, the host + * configures to drive the HSIC Idle state on the bus. + * It then waits for the device to initiate the Connect sequence. + * In device mode once this bit is set, the device waits for + * the HSIC Idle line state on the bus. Upon receving the Idle + * line state, it initiates the HSIC Connect sequence. + */ + unsigned hsic_connect:1; + /** This bit overrides and functionally inverts + * the if_select_hsic input port signal. + */ + unsigned inv_sel_hsic:1; + } b; +} glpmcfg_data_t; + +/** + * This union represents the bit fields of the Core ADP Timer, Control and + * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write + * the d32 value to the register. + */ +typedef union adpctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Probe Discharge (PRB_DSCHG) + * These bits set the times for TADP_DSCHG. + * These bits are defined as follows: + * 2'b00 - 4 msec + * 2'b01 - 8 msec + * 2'b10 - 16 msec + * 2'b11 - 32 msec + */ + unsigned prb_dschg:2; + /** Probe Delta (PRB_DELTA) + * These bits set the resolution for RTIM value. + * The bits are defined in units of 32 kHz clock cycles as follows: + * 2'b00 - 1 cycles + * 2'b01 - 2 cycles + * 2'b10 - 3 cycles + * 2'b11 - 4 cycles + * For example if this value is chosen to 2'b01, it means that RTIM + * increments for every 3(three) 32Khz clock cycles. + */ + unsigned prb_delta:2; + /** Probe Period (PRB_PER) + * These bits sets the TADP_PRD as shown in Figure 4 as follows: + * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) + * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) + * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) + * 2'b11 - Reserved + */ + unsigned prb_per:2; + /** These bits capture the latest time it took for VBUS to ramp from VADP_SINK + * to VADP_PRB. The bits are defined in units of 32 kHz clock cycles as follows: + * 0x000 - 1 cycles + * 0x001 - 2 cycles + * 0x002 - 3 cycles + * etc + * 0x7FF - 2048 cycles + * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. + */ + unsigned rtim:11; + /** Enable Probe (EnaPrb) + * When programmed to 1'b1, the core performs a probe operation. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned enaprb:1; + /** Enable Sense (EnaSns) + * When programmed to 1'b1, the core performs a Sense operation. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned enasns:1; + /** ADP Reset (ADPRes) + * When set, ADP controller is reset. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adpres:1; + /** ADP Enable (ADPEn) + * When set, the core performs either ADP probing or sensing + * based on EnaPrb or EnaSns. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adpen:1; + /** ADP Probe Interrupt (ADP_PRB_INT) + * When this bit is set, it means that the VBUS + * voltage is greater than VADP_PRB or VADP_PRB is reached. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_prb_int:1; + /** + * ADP Sense Interrupt (ADP_SNS_INT) + * When this bit is set, it means that the VBUS voltage is greater than + * VADP_SNS value or VADP_SNS is reached. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_sns_int:1; + /** ADP Tomeout Interrupt (ADP_TMOUT_INT) + * This bit is relevant only for an ADP probe. + * When this bit is set, it means that the ramp time has + * completed ie ADPCTL.RTIM has reached its terminal value + * of 0x7FF. This is a debug feature that allows software + * to read the ramp time after each cycle. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_tmout_int:1; + /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) + * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_prb_int_msk:1; + /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) + * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_sns_int_msk:1; + /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) + * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_tmout_int_msk:1; + /** Access Request + * 2'b00 - Read/Write Valid (updated by the core) + * 2'b01 - Read + * 2'b00 - Write + * 2'b00 - Reserved + */ + unsigned ar:2; + /** Reserved */ + unsigned reserved29_31:3; + } b; +} adpctl_data_t; + +//////////////////////////////////////////// +// Device Registers +/** + * Device Global Registers. Offsets 800h-BFFh + * + * The following structures define the size and relative field offsets + * for the Device Mode Registers. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_global_regs { + /** Device Configuration Register. Offset 800h */ + volatile uint32_t dcfg; + /** Device Control Register. Offset: 804h */ + volatile uint32_t dctl; + /** Device Status Register (Read Only). Offset: 808h */ + volatile uint32_t dsts; + /** Reserved. Offset: 80Ch */ + uint32_t unused; + /** Device IN Endpoint Common Interrupt Mask + * Register. Offset: 810h */ + volatile uint32_t diepmsk; + /** Device OUT Endpoint Common Interrupt Mask + * Register. Offset: 814h */ + volatile uint32_t doepmsk; + /** Device All Endpoints Interrupt Register. Offset: 818h */ + volatile uint32_t daint; + /** Device All Endpoints Interrupt Mask Register. Offset: + * 81Ch */ + volatile uint32_t daintmsk; + /** Device IN Token Queue Read Register-1 (Read Only). + * Offset: 820h */ + volatile uint32_t dtknqr1; + /** Device IN Token Queue Read Register-2 (Read Only). + * Offset: 824h */ + volatile uint32_t dtknqr2; + /** Device VBUS discharge Register. Offset: 828h */ + volatile uint32_t dvbusdis; + /** Device VBUS Pulse Register. Offset: 82Ch */ + volatile uint32_t dvbuspulse; + /** Device IN Token Queue Read Register-3 (Read Only). / + * Device Thresholding control register (Read/Write) + * Offset: 830h */ + volatile uint32_t dtknqr3_dthrctl; + /** Device IN Token Queue Read Register-4 (Read Only). / + * Device IN EPs empty Inr. Mask Register (Read/Write) + * Offset: 834h */ + volatile uint32_t dtknqr4_fifoemptymsk; + /** Device Each Endpoint Interrupt Register (Read Only). / + * Offset: 838h */ + volatile uint32_t deachint; + /** Device Each Endpoint Interrupt mask Register (Read/Write). / + * Offset: 83Ch */ + volatile uint32_t deachintmsk; + /** Device Each In Endpoint Interrupt mask Register (Read/Write). / + * Offset: 840h */ + volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; + /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / + * Offset: 880h */ + volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; +} dwc_otg_device_global_regs_t; + +/** + * This union represents the bit fields in the Device Configuration + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. Write the + * d32 member to the dcfg register. + */ +typedef union dcfg_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Device Speed */ + unsigned devspd:2; + /** Non Zero Length Status OUT Handshake */ + unsigned nzstsouthshk:1; +#define DWC_DCFG_SEND_STALL 1 + + unsigned ena32khzs:1; + /** Device Addresses */ + unsigned devaddr:7; + /** Periodic Frame Interval */ + unsigned perfrint:2; +#define DWC_DCFG_FRAME_INTERVAL_80 0 +#define DWC_DCFG_FRAME_INTERVAL_85 1 +#define DWC_DCFG_FRAME_INTERVAL_90 2 +#define DWC_DCFG_FRAME_INTERVAL_95 3 + + unsigned reserved13_17:5; + /** In Endpoint Mis-match count */ + unsigned epmscnt:5; + /** Enable Descriptor DMA in Device mode */ + unsigned descdma:1; + unsigned perschintvl:2; + unsigned resvalid:6; + } b; +} dcfg_data_t; + +/** + * This union represents the bit fields in the Device Control + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union dctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Remote Wakeup */ + unsigned rmtwkupsig:1; + /** Soft Disconnect */ + unsigned sftdiscon:1; + /** Global Non-Periodic IN NAK Status */ + unsigned gnpinnaksts:1; + /** Global OUT NAK Status */ + unsigned goutnaksts:1; + /** Test Control */ + unsigned tstctl:3; + /** Set Global Non-Periodic IN NAK */ + unsigned sgnpinnak:1; + /** Clear Global Non-Periodic IN NAK */ + unsigned cgnpinnak:1; + /** Set Global OUT NAK */ + unsigned sgoutnak:1; + /** Clear Global OUT NAK */ + unsigned cgoutnak:1; + + /** Power-On Programming Done */ + unsigned pwronprgdone:1; + /** Reserved */ + unsigned reserved:1; + /** Global Multi Count */ + unsigned gmc:2; + /** Ignore Frame Number for ISOC EPs */ + unsigned ifrmnum:1; + /** NAK on Babble */ + unsigned nakonbble:1; + + unsigned reserved17_31:15; + } b; +} dctl_data_t; + +/** + * This union represents the bit fields in the Device Status + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union dsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Suspend Status */ + unsigned suspsts:1; + /** Enumerated Speed */ + unsigned enumspd:2; +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 + /** Erratic Error */ + unsigned errticerr:1; + unsigned reserved4_7:4; + /** Frame or Microframe Number of the received SOF */ + unsigned soffn:14; + unsigned reserved22_31:10; + } b; +} dsts_data_t; + +/** + * This union represents the bit fields in the Device IN EP Interrupt + * Register and the Device IN EP Common Mask Register. + * + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union diepint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer complete mask */ + unsigned xfercompl:1; + /** Endpoint disable mask */ + unsigned epdisabled:1; + /** AHB Error mask */ + unsigned ahberr:1; + /** TimeOUT Handshake mask (non-ISOC EPs) */ + unsigned timeout:1; + /** IN Token received with TxF Empty mask */ + unsigned intktxfemp:1; + /** IN Token Received with EP mismatch mask */ + unsigned intknepmis:1; + /** IN Endpoint NAK Effective mask */ + unsigned inepnakeff:1; + /** Reserved */ + unsigned emptyintr:1; + + unsigned txfifoundrn:1; + + /** BNA Interrupt mask */ + unsigned bna:1; + + unsigned reserved10_12:3; + /** BNA Interrupt mask */ + unsigned nak:1; + + unsigned reserved14_31:18; + } b; +} diepint_data_t; + +/** + * This union represents the bit fields in the Device IN EP + * Common/Dedicated Interrupt Mask Register. + */ +typedef union diepint_data diepmsk_data_t; + +/** + * This union represents the bit fields in the Device OUT EP Interrupt + * Registerand Device OUT EP Common Interrupt Mask Register. + * + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union doepint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer complete */ + unsigned xfercompl:1; + /** Endpoint disable */ + unsigned epdisabled:1; + /** AHB Error */ + unsigned ahberr:1; + /** Setup Phase Done (contorl EPs) */ + unsigned setup:1; + /** OUT Token Received when Endpoint Disabled */ + unsigned outtknepdis:1; + + unsigned stsphsercvd:1; + /** Back-to-Back SETUP Packets Received */ + unsigned back2backsetup:1; + + unsigned reserved7:1; + /** OUT packet Error */ + unsigned outpkterr:1; + /** BNA Interrupt */ + unsigned bna:1; + + unsigned reserved10:1; + /** Packet Drop Status */ + unsigned pktdrpsts:1; + /** Babble Interrupt */ + unsigned babble:1; + /** NAK Interrupt */ + unsigned nak:1; + /** NYET Interrupt */ + unsigned nyet:1; + + unsigned reserved15_31:17; + } b; +} doepint_data_t; + +/** + * This union represents the bit fields in the Device OUT EP + * Common/Dedicated Interrupt Mask Register. + */ +typedef union doepint_data doepmsk_data_t; + +/** + * This union represents the bit fields in the Device All EP Interrupt + * and Mask Registers. + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union daint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** IN Endpoint bits */ + unsigned in:16; + /** OUT Endpoint bits */ + unsigned out:16; + } ep; + struct { + /** IN Endpoint bits */ + unsigned inep0:1; + unsigned inep1:1; + unsigned inep2:1; + unsigned inep3:1; + unsigned inep4:1; + unsigned inep5:1; + unsigned inep6:1; + unsigned inep7:1; + unsigned inep8:1; + unsigned inep9:1; + unsigned inep10:1; + unsigned inep11:1; + unsigned inep12:1; + unsigned inep13:1; + unsigned inep14:1; + unsigned inep15:1; + /** OUT Endpoint bits */ + unsigned outep0:1; + unsigned outep1:1; + unsigned outep2:1; + unsigned outep3:1; + unsigned outep4:1; + unsigned outep5:1; + unsigned outep6:1; + unsigned outep7:1; + unsigned outep8:1; + unsigned outep9:1; + unsigned outep10:1; + unsigned outep11:1; + unsigned outep12:1; + unsigned outep13:1; + unsigned outep14:1; + unsigned outep15:1; + } b; +} daint_data_t; + +/** + * This union represents the bit fields in the Device IN Token Queue + * Read Registers. + * - Read the register into the d32 member. + * - READ-ONLY Register + */ +typedef union dtknq1_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** In Token Queue Write Pointer */ + unsigned intknwptr:5; + /** Reserved */ + unsigned reserved05_06:2; + /** write pointer has wrapped. */ + unsigned wrap_bit:1; + /** EP Numbers of IN Tokens 0 ... 4 */ + unsigned epnums0_5:24; + } b; +} dtknq1_data_t; + +/** + * This union represents Threshold control Register + * - Read and write the register into the d32 member. + * - READ-WRITABLE Register + */ +typedef union dthrctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** non ISO Tx Thr. Enable */ + unsigned non_iso_thr_en:1; + /** ISO Tx Thr. Enable */ + unsigned iso_thr_en:1; + /** Tx Thr. Length */ + unsigned tx_thr_len:9; + /** AHB Threshold ratio */ + unsigned ahb_thr_ratio:2; + /** Reserved */ + unsigned reserved13_15:3; + /** Rx Thr. Enable */ + unsigned rx_thr_en:1; + /** Rx Thr. Length */ + unsigned rx_thr_len:9; + unsigned reserved26:1; + /** Arbiter Parking Enable*/ + unsigned arbprken:1; + /** Reserved */ + unsigned reserved28_31:4; + } b; +} dthrctl_data_t; + +/** + * Device Logical IN Endpoint-Specific Registers. Offsets + * 900h-AFCh + * + * There will be one set of endpoint registers per logical endpoint + * implemented. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_in_ep_regs { + /** Device IN Endpoint Control Register. Offset:900h + + * (ep_num * 20h) + 00h */ + volatile uint32_t diepctl; + /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ + uint32_t reserved04; + /** Device IN Endpoint Interrupt Register. Offset:900h + + * (ep_num * 20h) + 08h */ + volatile uint32_t diepint; + /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ + uint32_t reserved0C; + /** Device IN Endpoint Transfer Size + * Register. Offset:900h + (ep_num * 20h) + 10h */ + volatile uint32_t dieptsiz; + /** Device IN Endpoint DMA Address Register. Offset:900h + + * (ep_num * 20h) + 14h */ + volatile uint32_t diepdma; + /** Device IN Endpoint Transmit FIFO Status Register. Offset:900h + + * (ep_num * 20h) + 18h */ + volatile uint32_t dtxfsts; + /** Device IN Endpoint DMA Buffer Register. Offset:900h + + * (ep_num * 20h) + 1Ch */ + volatile uint32_t diepdmab; +} dwc_otg_dev_in_ep_regs_t; + +/** + * Device Logical OUT Endpoint-Specific Registers. Offsets: + * B00h-CFCh + * + * There will be one set of endpoint registers per logical endpoint + * implemented. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_out_ep_regs { + /** Device OUT Endpoint Control Register. Offset:B00h + + * (ep_num * 20h) + 00h */ + volatile uint32_t doepctl; + /** Device OUT Endpoint Frame number Register. Offset: + * B00h + (ep_num * 20h) + 04h */ + volatile uint32_t doepfn; + /** Device OUT Endpoint Interrupt Register. Offset:B00h + + * (ep_num * 20h) + 08h */ + volatile uint32_t doepint; + /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ + uint32_t reserved0C; + /** Device OUT Endpoint Transfer Size Register. Offset: + * B00h + (ep_num * 20h) + 10h */ + volatile uint32_t doeptsiz; + /** Device OUT Endpoint DMA Address Register. Offset:B00h + * + (ep_num * 20h) + 14h */ + volatile uint32_t doepdma; + /** Reserved. Offset:B00h + * (ep_num * 20h) + 18h */ + uint32_t unused; + /** Device OUT Endpoint DMA Buffer Register. Offset:B00h + * + (ep_num * 20h) + 1Ch */ + uint32_t doepdmab; +} dwc_otg_dev_out_ep_regs_t; + +/** + * This union represents the bit fields in the Device EP Control + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union depctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Maximum Packet Size + * IN/OUT EPn + * IN/OUT EP0 - 2 bits + * 2'b00: 64 Bytes + * 2'b01: 32 + * 2'b10: 16 + * 2'b11: 8 */ + unsigned mps:11; +#define DWC_DEP0CTL_MPS_64 0 +#define DWC_DEP0CTL_MPS_32 1 +#define DWC_DEP0CTL_MPS_16 2 +#define DWC_DEP0CTL_MPS_8 3 + + /** Next Endpoint + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned nextep:4; + + /** USB Active Endpoint */ + unsigned usbactep:1; + + /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) + * This field contains the PID of the packet going to + * be received or transmitted on this endpoint. The + * application should program the PID of the first + * packet going to be received or transmitted on this + * endpoint , after the endpoint is + * activated. Application use the SetD1PID and + * SetD0PID fields of this register to program either + * D0 or D1 PID. + * + * The encoding for this field is + * - 0: D0 + * - 1: D1 + */ + unsigned dpid:1; + + /** NAK Status */ + unsigned naksts:1; + + /** Endpoint Type + * 2'b00: Control + * 2'b01: Isochronous + * 2'b10: Bulk + * 2'b11: Interrupt */ + unsigned eptype:2; + + /** Snoop Mode + * OUT EPn/OUT EP0 + * IN EPn/IN EP0 - reserved */ + unsigned snp:1; + + /** Stall Handshake */ + unsigned stall:1; + + /** Tx Fifo Number + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned txfnum:4; + + /** Clear NAK */ + unsigned cnak:1; + /** Set NAK */ + unsigned snak:1; + /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA0. Set Even + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) + * frame. + */ + unsigned setd0pid:1; + /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA1 Set Odd + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to odd (micro) frame. + */ + unsigned setd1pid:1; + + /** Endpoint Disable */ + unsigned epdis:1; + /** Endpoint Enable */ + unsigned epena:1; + } b; +} depctl_data_t; + +/** + * This union represents the bit fields in the Device EP Transfer + * Size Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union deptsiz_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer size */ + unsigned xfersize:19; + /** Packet Count */ + unsigned pktcnt:10; + /** Multi Count - Periodic IN endpoints */ + unsigned mc:2; + unsigned reserved:1; + } b; +} deptsiz_data_t; + +/** + * This union represents the bit fields in the Device EP 0 Transfer + * Size Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union deptsiz0_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer size */ + unsigned xfersize:7; + /** Reserved */ + unsigned reserved7_18:12; + /** Packet Count */ + unsigned pktcnt:2; + /** Reserved */ + unsigned reserved21_28:8; + /**Setup Packet Count (DOEPTSIZ0 Only) */ + unsigned supcnt:2; + unsigned reserved31; + } b; +} +#if __GNUC__ /*GCC*/ +__attribute__((__may_alias__)) deptsiz0_data_t; +#else + deptsiz0_data_t; +#endif +///////////////////////////////////////////////// +// DMA Descriptor Specific Structures +// + +/** Buffer status definitions */ + +#define BS_HOST_READY 0x0 +#define BS_DMA_BUSY 0x1 +#define BS_DMA_DONE 0x2 +#define BS_HOST_BUSY 0x3 + +/** Receive/Transmit status definitions */ + +#define RTS_SUCCESS 0x0 +#define RTS_BUFFLUSH 0x1 +#define RTS_RESERVED 0x2 +#define RTS_BUFERR 0x3 + +/** + * This union represents the bit fields in the DMA Descriptor + * status quadlet. Read the quadlet into the d32 member then + * set/clear the bits using the bit, b_iso_out and + * b_iso_in elements. + */ +typedef union dev_dma_desc_sts { + /** raw register data */ + uint32_t d32; + /** quadlet bits */ + struct { + /** Received number of bytes */ + unsigned bytes:16; + + unsigned reserved16_22:7; + /** Multiple Transfer - only for OUT EPs */ + unsigned mtrf:1; + /** Setup Packet received - only for OUT EPs */ + unsigned sr:1; + /** Interrupt On Complete */ + unsigned ioc:1; + /** Short Packet */ + unsigned sp:1; + /** Last */ + unsigned l:1; + /** Receive Status */ + unsigned sts:2; + /** Buffer Status */ + unsigned bs:2; + } b; + +//#ifdef DWC_EN_ISOC + /** iso out quadlet bits */ + struct { + /** Received number of bytes */ + unsigned rxbytes:11; + + unsigned reserved11:1; + /** Frame Number */ + unsigned framenum:11; + /** Received ISO Data PID */ + unsigned pid:2; + /** Interrupt On Complete */ + unsigned ioc:1; + /** Short Packet */ + unsigned sp:1; + /** Last */ + unsigned l:1; + /** Receive Status */ + unsigned rxsts:2; + /** Buffer Status */ + unsigned bs:2; + } b_iso_out; + + /** iso in quadlet bits */ + struct { + /** Transmited number of bytes */ + unsigned txbytes:12; + /** Frame Number */ + unsigned framenum:11; + /** Transmited ISO Data PID */ + unsigned pid:2; + /** Interrupt On Complete */ + unsigned ioc:1; + /** Short Packet */ + unsigned sp:1; + /** Last */ + unsigned l:1; + /** Transmit Status */ + unsigned txsts:2; + /** Buffer Status */ + unsigned bs:2; + } b_iso_in; +//#endif /* DWC_EN_ISOC */ +} dev_dma_desc_sts_t; + +/** + * DMA Descriptor structure + * + * DMA Descriptor structure contains two quadlets: + * Status quadlet and Data buffer pointer. + */ +typedef struct dwc_otg_dev_dma_desc { + /** DMA Descriptor status quadlet */ + dev_dma_desc_sts_t status; + /** DMA Descriptor data buffer pointer */ + uint32_t buf; +} dwc_otg_dev_dma_desc_t; + +/** + * The dwc_otg_dev_if structure contains information needed to manage + * the DWC_otg controller acting in device mode. It represents the + * programming view of the device-specific aspects of the controller. + */ +typedef struct dwc_otg_dev_if { + /** Pointer to device Global registers. + * Device Global Registers starting at offset 800h + */ + dwc_otg_device_global_regs_t *dev_global_regs; +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800 + + /** + * Device Logical IN Endpoint-Specific Registers 900h-AFCh + */ + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; +#define DWC_DEV_IN_EP_REG_OFFSET 0x900 +#define DWC_EP_REG_OFFSET 0x20 + + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ + dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 + + /* Device configuration information */ + uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ + uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ + uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ + + /** Size of periodic FIFOs (Bytes) */ + uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; + + /** Size of Tx FIFOs (Bytes) */ + uint16_t tx_fifo_size[MAX_TX_FIFOS]; + + /** Thresholding enable flags and length varaiables **/ + uint16_t rx_thr_en; + uint16_t iso_tx_thr_en; + uint16_t non_iso_tx_thr_en; + + uint16_t rx_thr_length; + uint16_t tx_thr_length; + + /** + * Pointers to the DMA Descriptors for EP0 Control + * transfers (virtual and physical) + */ + + /** 2 descriptors for SETUP packets */ + dwc_dma_t dma_setup_desc_addr[2]; + dwc_otg_dev_dma_desc_t *setup_desc_addr[2]; + + /** Pointer to Descriptor with latest SETUP packet */ + dwc_otg_dev_dma_desc_t *psetup; + + /** Index of current SETUP handler descriptor */ + uint32_t setup_desc_index; + + /** Descriptor for Data In or Status In phases */ + dwc_dma_t dma_in_desc_addr; + dwc_otg_dev_dma_desc_t *in_desc_addr; + + /** Descriptor for Data Out or Status Out phases */ + dwc_dma_t dma_out_desc_addr; + dwc_otg_dev_dma_desc_t *out_desc_addr; + + /** Setup Packet Detected - if set clear NAK when queueing */ + uint32_t spd; + +} dwc_otg_dev_if_t; + +///////////////////////////////////////////////// +// Host Mode Register Structures +// +/** + * The Host Global Registers structure defines the size and relative + * field offsets for the Host Mode Global Registers. Host Global + * Registers offsets 400h-7FFh. +*/ +typedef struct dwc_otg_host_global_regs { + /** Host Configuration Register. Offset: 400h */ + volatile uint32_t hcfg; + /** Host Frame Interval Register. Offset: 404h */ + volatile uint32_t hfir; + /** Host Frame Number / Frame Remaining Register. Offset: 408h */ + volatile uint32_t hfnum; + /** Reserved. Offset: 40Ch */ + uint32_t reserved40C; + /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ + volatile uint32_t hptxsts; + /** Host All Channels Interrupt Register. Offset: 414h */ + volatile uint32_t haint; + /** Host All Channels Interrupt Mask Register. Offset: 418h */ + volatile uint32_t haintmsk; + /** Host Frame List Base Address Register . Offset: 41Ch */ + volatile uint32_t hflbaddr; +} dwc_otg_host_global_regs_t; + +/** + * This union represents the bit fields in the Host Configuration Register. + * Read the register into the d32 member then set/clear the bits using + * the bit elements. Write the d32 member to the hcfg register. + */ +typedef union hcfg_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** FS/LS Phy Clock Select */ + unsigned fslspclksel:2; +#define DWC_HCFG_30_60_MHZ 0 +#define DWC_HCFG_48_MHZ 1 +#define DWC_HCFG_6_MHZ 2 + + /** FS/LS Only Support */ + unsigned fslssupp:1; + unsigned reserved3_6:4; + /** Enable 32-KHz Suspend Mode */ + unsigned ena32khzs:1; + /** Resume Validation Periiod */ + unsigned resvalid:8; + unsigned reserved16_22:7; + /** Enable Scatter/gather DMA in Host mode */ + unsigned descdma:1; + /** Frame List Entries */ + unsigned frlisten:2; + /** Enable Periodic Scheduling */ + unsigned perschedena:1; + unsigned reserved27_30:4; + unsigned modechtimen:1; + } b; +} hcfg_data_t; + +/** + * This union represents the bit fields in the Host Frame Remaing/Number + * Register. + */ +typedef union hfir_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned frint:16; + unsigned hfirrldctrl:1; + unsigned reserved:15; + } b; +} hfir_data_t; + +/** + * This union represents the bit fields in the Host Frame Remaing/Number + * Register. + */ +typedef union hfnum_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned frnum:16; +#define DWC_HFNUM_MAX_FRNUM 0x3FFF + unsigned frrem:16; + } b; +} hfnum_data_t; + +typedef union hptxsts_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned ptxfspcavail:16; + unsigned ptxqspcavail:8; + /** Top of the Periodic Transmit Request Queue + * - bit 24 - Terminate (last entry for the selected channel) + * - bits 26:25 - Token Type + * - 2'b00 - Zero length + * - 2'b01 - Ping + * - 2'b10 - Disable + * - bits 30:27 - Channel Number + * - bit 31 - Odd/even microframe + */ + unsigned ptxqtop_terminate:1; + unsigned ptxqtop_token:2; + unsigned ptxqtop_chnum:4; + unsigned ptxqtop_odd:1; + } b; +} hptxsts_data_t; + +/** + * This union represents the bit fields in the Host Port Control and Status + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hprt0 register. + */ +typedef union hprt0_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned prtconnsts:1; + unsigned prtconndet:1; + unsigned prtena:1; + unsigned prtenchng:1; + unsigned prtovrcurract:1; + unsigned prtovrcurrchng:1; + unsigned prtres:1; + unsigned prtsusp:1; + unsigned prtrst:1; + unsigned reserved9:1; + unsigned prtlnsts:2; + unsigned prtpwr:1; + unsigned prttstctl:4; + unsigned prtspd:2; +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1 +#define DWC_HPRT0_PRTSPD_LOW_SPEED 2 + unsigned reserved19_31:13; + } b; +} hprt0_data_t; + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union haint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned ch0:1; + unsigned ch1:1; + unsigned ch2:1; + unsigned ch3:1; + unsigned ch4:1; + unsigned ch5:1; + unsigned ch6:1; + unsigned ch7:1; + unsigned ch8:1; + unsigned ch9:1; + unsigned ch10:1; + unsigned ch11:1; + unsigned ch12:1; + unsigned ch13:1; + unsigned ch14:1; + unsigned ch15:1; + unsigned reserved:16; + } b; + + struct { + unsigned chint:16; + unsigned reserved:16; + } b2; +} haint_data_t; + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union haintmsk_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned ch0:1; + unsigned ch1:1; + unsigned ch2:1; + unsigned ch3:1; + unsigned ch4:1; + unsigned ch5:1; + unsigned ch6:1; + unsigned ch7:1; + unsigned ch8:1; + unsigned ch9:1; + unsigned ch10:1; + unsigned ch11:1; + unsigned ch12:1; + unsigned ch13:1; + unsigned ch14:1; + unsigned ch15:1; + unsigned reserved:16; + } b; + + struct { + unsigned chint:16; + unsigned reserved:16; + } b2; +} haintmsk_data_t; + +/** + * Host Channel Specific Registers. 500h-5FCh + */ +typedef struct dwc_otg_hc_regs { + /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ + volatile uint32_t hcchar; + /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ + volatile uint32_t hcsplt; + /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ + volatile uint32_t hcint; + /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ + volatile uint32_t hcintmsk; + /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ + volatile uint32_t hctsiz; + /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ + volatile uint32_t hcdma; + volatile uint32_t reserved; + /** Host Channel 0 DMA Buffer Address Register. Offset: 500h + (chan_num * 20h) + 1Ch */ + volatile uint32_t hcdmab; +} dwc_otg_hc_regs_t; + +/** + * This union represents the bit fields in the Host Channel Characteristics + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcchar register. + */ +typedef union hcchar_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Maximum packet size in bytes */ + unsigned mps:11; + + /** Endpoint number */ + unsigned epnum:4; + + /** 0: OUT, 1: IN */ + unsigned epdir:1; + + unsigned reserved:1; + + /** 0: Full/high speed device, 1: Low speed device */ + unsigned lspddev:1; + + /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ + unsigned eptype:2; + + /** Packets per frame for periodic transfers. 0 is reserved. */ + unsigned multicnt:2; + + /** Device address */ + unsigned devaddr:7; + + /** + * Frame to transmit periodic transaction. + * 0: even, 1: odd + */ + unsigned oddfrm:1; + + /** Channel disable */ + unsigned chdis:1; + + /** Channel enable */ + unsigned chen:1; + } b; +} hcchar_data_t; + +typedef union hcsplt_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Port Address */ + unsigned prtaddr:7; + + /** Hub Address */ + unsigned hubaddr:7; + + /** Transaction Position */ + unsigned xactpos:2; +#define DWC_HCSPLIT_XACTPOS_MID 0 +#define DWC_HCSPLIT_XACTPOS_END 1 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2 +#define DWC_HCSPLIT_XACTPOS_ALL 3 + + /** Do Complete Split */ + unsigned compsplt:1; + + /** Reserved */ + unsigned reserved:14; + + /** Split Enble */ + unsigned spltena:1; + } b; +} hcsplt_data_t; + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union hcint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Transfer Complete */ + unsigned xfercomp:1; + /** Channel Halted */ + unsigned chhltd:1; + /** AHB Error */ + unsigned ahberr:1; + /** STALL Response Received */ + unsigned stall:1; + /** NAK Response Received */ + unsigned nak:1; + /** ACK Response Received */ + unsigned ack:1; + /** NYET Response Received */ + unsigned nyet:1; + /** Transaction Err */ + unsigned xacterr:1; + /** Babble Error */ + unsigned bblerr:1; + /** Frame Overrun */ + unsigned frmovrun:1; + /** Data Toggle Error */ + unsigned datatglerr:1; + /** Buffer Not Available (only for DDMA mode) */ + unsigned bna:1; + /** Exessive transaction error (only for DDMA mode) */ + unsigned xcs_xact:1; + /** Frame List Rollover interrupt */ + unsigned frm_list_roll:1; + /** Reserved */ + unsigned reserved14_31:18; + } b; +} hcint_data_t; + +/** + * This union represents the bit fields in the Host Channel Interrupt Mask + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcintmsk register. + */ +typedef union hcintmsk_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned xfercompl:1; + unsigned chhltd:1; + unsigned ahberr:1; + unsigned stall:1; + unsigned nak:1; + unsigned ack:1; + unsigned nyet:1; + unsigned xacterr:1; + unsigned bblerr:1; + unsigned frmovrun:1; + unsigned datatglerr:1; + unsigned bna:1; + unsigned xcs_xact:1; + unsigned frm_list_roll:1; + unsigned reserved14_31:18; + } b; +} hcintmsk_data_t; + +/** + * This union represents the bit fields in the Host Channel Transfer Size + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcchar register. + */ + +typedef union hctsiz_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Total transfer size in bytes */ + unsigned xfersize:19; + + /** Data packets to transfer */ + unsigned pktcnt:10; + + /** + * Packet ID for next data packet + * 0: DATA0 + * 1: DATA2 + * 2: DATA1 + * 3: MDATA (non-Control), SETUP (Control) + */ + unsigned pid:2; +#define DWC_HCTSIZ_DATA0 0 +#define DWC_HCTSIZ_DATA1 2 +#define DWC_HCTSIZ_DATA2 1 +#define DWC_HCTSIZ_MDATA 3 +#define DWC_HCTSIZ_SETUP 3 + + /** Do PING protocol when 1 */ + unsigned dopng:1; + } b; + + /** register bits */ + struct { + /** Scheduling information */ + unsigned schinfo:8; + + /** Number of transfer descriptors. + * Max value: + * 64 in general, + * 256 only for HS isochronous endpoint. + */ + unsigned ntd:8; + + /** Data packets to transfer */ + unsigned reserved16_28:13; + + /** + * Packet ID for next data packet + * 0: DATA0 + * 1: DATA2 + * 2: DATA1 + * 3: MDATA (non-Control) + */ + unsigned pid:2; + + /** Do PING protocol when 1 */ + unsigned dopng:1; + } b_ddma; +} hctsiz_data_t; + +/** + * This union represents the bit fields in the Host DMA Address + * Register used in Descriptor DMA mode. + */ +typedef union hcdma_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved0_2:3; + /** Current Transfer Descriptor. Not used for ISOC */ + unsigned ctd:8; + /** Start Address of Descriptor List */ + unsigned dma_addr:21; + } b; +} hcdma_data_t; + +/** + * This union represents the bit fields in the DMA Descriptor + * status quadlet for host mode. Read the quadlet into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union host_dma_desc_sts { + /** raw register data */ + uint32_t d32; + /** quadlet bits */ + + /* for non-isochronous */ + struct { + /** Number of bytes */ + unsigned n_bytes:17; + /** QTD offset to jump when Short Packet received - only for IN EPs */ + unsigned qtd_offset:6; + /** + * Set to request the core to jump to alternate QTD if + * Short Packet received - only for IN EPs + */ + unsigned a_qtd:1; + /** + * Setup Packet bit. When set indicates that buffer contains + * setup packet. + */ + unsigned sup:1; + /** Interrupt On Complete */ + unsigned ioc:1; + /** End of List */ + unsigned eol:1; + unsigned reserved27:1; + /** Rx/Tx Status */ + unsigned sts:2; +#define DMA_DESC_STS_PKTERR 1 + unsigned reserved30:1; + /** Active Bit */ + unsigned a:1; + } b; + /* for isochronous */ + struct { + /** Number of bytes */ + unsigned n_bytes:12; + unsigned reserved12_24:13; + /** Interrupt On Complete */ + unsigned ioc:1; + unsigned reserved26_27:2; + /** Rx/Tx Status */ + unsigned sts:2; + unsigned reserved30:1; + /** Active Bit */ + unsigned a:1; + } b_isoc; +} host_dma_desc_sts_t; + +#define MAX_DMA_DESC_SIZE 131071 +#define MAX_DMA_DESC_NUM_GENERIC 64 +#define MAX_DMA_DESC_NUM_HS_ISOC 256 +#define MAX_FRLIST_EN_NUM 64 +/** + * Host-mode DMA Descriptor structure + * + * DMA Descriptor structure contains two quadlets: + * Status quadlet and Data buffer pointer. + */ +typedef struct dwc_otg_host_dma_desc { + /** DMA Descriptor status quadlet */ + host_dma_desc_sts_t status; + /** DMA Descriptor data buffer pointer */ + uint32_t buf; +} dwc_otg_host_dma_desc_t; + +/** OTG Host Interface Structure. + * + * The OTG Host Interface Structure structure contains information + * needed to manage the DWC_otg controller acting in host mode. It + * represents the programming view of the host-specific aspects of the + * controller. + */ +typedef struct dwc_otg_host_if { + /** Host Global Registers starting at offset 400h.*/ + dwc_otg_host_global_regs_t *host_global_regs; +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 + + /** Host Port 0 Control and Status Register */ + volatile uint32_t *hprt0; +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 + + /** Host Channel Specific Registers at offsets 500h-5FCh. */ + dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20 + + /* Host configuration information */ + /** Number of Host Channels (range: 1-16) */ + uint8_t num_host_channels; + /** Periodic EPs supported (0: no, 1: yes) */ + uint8_t perio_eps_supported; + /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ + uint16_t perio_tx_fifo_size; + +} dwc_otg_host_if_t; + +/** + * This union represents the bit fields in the Power and Clock Gating Control + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union pcgcctl_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Stop Pclk */ + unsigned stoppclk:1; + /** Gate Hclk */ + unsigned gatehclk:1; + /** Power Clamp */ + unsigned pwrclmp:1; + /** Reset Power Down Modules */ + unsigned rstpdwnmodule:1; + /** Reserved */ + unsigned reserved:1; + /** Enable Sleep Clock Gating (Enbl_L1Gating) */ + unsigned enbl_sleep_gating:1; + /** PHY In Sleep (PhySleep) */ + unsigned phy_in_sleep:1; + /** Deep Sleep*/ + unsigned deep_sleep:1; + unsigned resetaftsusp:1; + unsigned restoremode:1; + unsigned reserved10_12:3; + unsigned ess_reg_restored:1; + unsigned prt_clk_sel:2; + unsigned port_power:1; + unsigned max_xcvrselect:2; + unsigned max_termsel:1; + unsigned mac_dev_addr:7; + unsigned p2hd_dev_enum_spd:2; + unsigned p2hd_prt_spd:2; + unsigned if_dev_mode:1; + } b; +} pcgcctl_data_t; + +/** + * This union represents the bit fields in the Global Data FIFO Software Configuration Register. + * Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union gdfifocfg_data { + /* raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** OTG Data FIFO depth */ + unsigned gdfifocfg:16; + /** Start address of EP info controller */ + unsigned epinfobase:16; + } b; +} gdfifocfg_data_t; + +/** + * This union represents the bit fields in the Global Power Down Register + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union gpwrdn_data { + /* raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** PMU Interrupt Select */ + unsigned pmuintsel:1; + /** PMU Active */ + unsigned pmuactv:1; + /** Restore */ + unsigned restore:1; + /** Power Down Clamp */ + unsigned pwrdnclmp:1; + /** Power Down Reset */ + unsigned pwrdnrstn:1; + /** Power Down Switch */ + unsigned pwrdnswtch:1; + /** Disable VBUS */ + unsigned dis_vbus:1; + /** Line State Change */ + unsigned lnstschng:1; + /** Line state change mask */ + unsigned lnstchng_msk:1; + /** Reset Detected */ + unsigned rst_det:1; + /** Reset Detect mask */ + unsigned rst_det_msk:1; + /** Disconnect Detected */ + unsigned disconn_det:1; + /** Disconnect Detect mask */ + unsigned disconn_det_msk:1; + /** Connect Detected*/ + unsigned connect_det:1; + /** Connect Detected Mask*/ + unsigned connect_det_msk:1; + /** SRP Detected */ + unsigned srp_det:1; + /** SRP Detect mask */ + unsigned srp_det_msk:1; + /** Status Change Interrupt */ + unsigned sts_chngint:1; + /** Status Change Interrupt Mask */ + unsigned sts_chngint_msk:1; + /** Line State */ + unsigned linestate:2; + /** Indicates current mode(status of IDDIG signal) */ + unsigned idsts:1; + /** B Session Valid signal status*/ + unsigned bsessvld:1; + /** ADP Event Detected */ + unsigned adp_int:1; + /** Multi Valued ID pin */ + unsigned mult_val_id_bc:5; + /** Reserved 24_31 */ + unsigned reserved29_31:3; + } b; +} gpwrdn_data_t; + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usbh.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usbh.h new file mode 100644 index 00000000..06641fe4 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usbh.h @@ -0,0 +1,416 @@ +/** + * @file xmc_usbh.h + * @date 2016-06-30 + * + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2016-06-30: + * - Initial Version.
+ * 2016-09-01: + * - Removed Keil specific inclusions and macros
+ * + * @endcond + * + */ + +#ifndef XMC_USBH_H +#define XMC_USBH_H + +#include +#include "xmc_common.h" +#include "xmc_scu.h" +#include "xmc_gpio.h" + +#if((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC43) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || defined(DOXYGEN)) +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup USBH + * @brief Universal Serial Bus Host (USBH) driver for the XMC4000 microcontroller family. + * + * The USBH is the host mode device driver for the USB0 hardware module on XMC4000 family of microcontrollers. + * The USB0 module can be used to establish a USB interface between outside world and XMC4000 family of controllers. + * The USB module includes the following features in host mode: + * -# Complies with the USB 2.0 Specification. + * -# Supports up to 14 bidirectional pipes, including control pipe 0. + * -# Supports SOFs in Full-Speed modes. + * -# Supports clock gating for power saving. + * -# Supports FIFO mode data transaction. + * + * The below figure shows the overview of USB0 module in XMC4 microntroller. + * @image html USB_module_overview.png + * @image latex ../images/USB_module_overview.png + * + * + * The USBH device driver supports the following features:\n + * -# Initialize/Uninitialize the USB0 module on XMC4000 device. + * -# Control VBUS state. + * -# Reset USB port. + * -# Set the USB device address. + * -# Allocate pipe for new endpoint communication. + * -# Modify an existing pipe. + * -# Transfer data on selected pipe. + * -# Abort ongoing data transaction. + * -# Handle multi packet data transaction by updating toggle information. + * + * The USBH device driver expects registration of callback functions ::XMC_USBH_SignalPortEvent_t and ::XMC_USBH_SignalPipeEvent_t to be executed + * when there is port event interrupt and pipe event interrupt respectively.\n + * The USBH driver is CMSIS API compatible. Please use Driver_USBH0 to access the USBH API.\n + * For example, to initialize the USB host controller, use Driver_USBH0.Initialize().\n + * + * @{ + */ + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ +/*Drive VBUS*/ +#define XMC_USB_DRIVE_PORT1 P3_2 /**< Default port(PORT3, pin 2) used to enable VBUS voltage regulator on the board */ +#define XMC_USB_DRIVE_PORT2 P0_1 /**< Alternate port that can be used to enable VBUS voltage regulator(PORT0, pin 1) */ + +#ifndef USBH0_MAX_PIPE_NUM +#define USBH0_MAX_PIPE_NUM (14U) /**< Representation of number of pipes available */ +#endif +#if (USBH0_MAX_PIPE_NUM > 14U) +#error Too many Pipes, maximum Pipes that this driver supports is 14 !!! +#endif + +#define XMC_USBH_CLOCK_GATING_ENABLE 1 /**< Used to enable clock gating when the driver is powered down*/ +#define XMC_USBH_CLOCK_GATING_DISABLE 0 /**< Used to disable clock gating when the driver is fully powered*/ + +#define USB_CH_HCCHARx_MPS(x) (((uint32_t) x ) & (uint32_t)USB_CH_HCCHAR_MPS_Msk) /**< Masks maximum packet size information from the HCCHAR register value provided as input */ +#define USB_CH_HCCHARx_EPNUM(x) (((uint32_t) x << USB_CH_HCCHAR_EPNum_Pos) & (uint32_t)USB_CH_HCCHAR_EPNum_Msk) /**< Shifts the value to the position of endpoint number(EPNum) in the HCCHAR register*/ +#define USB_CH_HCCHARx_EPTYPE(x) (((uint32_t) x << USB_CH_HCCHAR_EPType_Pos) & (uint32_t)USB_CH_HCCHAR_EPType_Msk) /**< Shifts the value to the position of endpoint type(EPType) in the HCCHAR register*/ +#define USB_CH_HCCHARx_MCEC(x) (((uint32_t) x << USB_CH_HCCHAR_MC_EC_Pos) & (uint32_t)USB_CH_HCCHAR_MC_EC_Msk) /**< Shifts the value to the position of multi-count(MC_EC) field in the HCCHAR register*/ +#define USB_CH_HCCHARx_DEVADDR(x) (((uint32_t) x << USB_CH_HCCHAR_DevAddr_Pos) & (uint32_t)USB_CH_HCCHAR_DevAddr_Msk) /**< Shifts the value to the position of endpoint type(EPType) in the HCCHAR register*/ +#define USB_CH_HCCHARx_EPDIR(x) (((uint32_t) x << USB_CH_HCCHAR_EPDir_Pos) & (uint32_t)USB_CH_HCCHAR_EPDir_Msk) /**< Shifts the value to the position of endpoint direction(EPDir) in the HCCHAR register*/ +#define USB_CH_HCCHAR_LSDEV_Msk (((uint32_t) 0x1 << 15U) & 0x1U) +#define USB_CH_HCTSIZx_DPID(x) (((uint32_t) x << USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos) & (uint32_t)USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk) /**< Shifts the value to the position of packet ID (PID) in the HCTSIZ register*/ +#define USB_CH_HCTSIZx_DPID_DATA0 (USB_CH_HCTSIZx_DPID(0U)) /**< Represents DATA toggle DATA0 as in HCTSIZ register*/ +#define USB_CH_HCTSIZx_DPID_DATA2 (USB_CH_HCTSIZx_DPID(1U)) /**< Represents DATA toggle DATA2 as in HCTSIZ register*/ +#define USB_CH_HCTSIZx_DPID_DATA1 (USB_CH_HCTSIZx_DPID(2U)) /**< Represents DATA toggle DATA1 as in HCTSIZ register*/ +#define USB_CH_HCTSIZx_DPID_MDATA (USB_CH_HCTSIZx_DPID(3U)) /**< Represents DATA toggle MDATA as in HCTSIZ register*/ +#define USB_CH_HCTSIZx_DPID_SETUP (USB_CH_HCTSIZx_DPID(3U)) /**< Represents SETUP token as in HCTSIZ register*/ +#define USB_GRXSTSR_HOSTMODE_PktSts_IN_DATA_PKT 0x2 /**< Represents IN data token as in receive status pop register(GRXSTSP)*/ +#define USB_GRXSTSR_HOSTMODE_PktSts_IN_TRSF_CPL 0x3 /**< Represents paket status information as in receive status pop register(GRXSTSP)*/ + + +#define USB_CH_HCFG_FSLSSUP(x) (((uint32_t) x << USB_HCFG_FSLSSupp_Pos) & USB_HCFG_FSLSSupp_Msk) /**< Provides register value to update USB full speed related mask FLSSupp of register HCFG*/ +#define USB_CH_HCFG_FSLSPCS(x) (((uint32_t) x ) & USB_HCFG_FSLSPclkSel_Msk) /**< Provides register value to update PHY clock selection in register HCFG*/ + +#define USB_CH_HCINTx_ALL (USB_CH_HCINTMSK_XferComplMsk_Msk | \ + USB_CH_HCINTMSK_ChHltdMsk_Msk | \ + USB_CH_HCINTMSK_StallMsk_Msk | \ + USB_CH_HCINTMSK_NakMsk_Msk | \ + USB_CH_HCINTMSK_AckMsk_Msk | \ + USB_CH_HCINTMSK_XactErrMsk_Msk | \ + USB_CH_HCINTMSK_BblErrMsk_Msk | \ + USB_CH_HCINTMSK_FrmOvrunMsk_Msk | \ + USB_CH_HCINTMSK_DataTglErrMsk_Msk) /**< Mask for selecting all channel related events*/ + +#define USB_CH_HCINTx_ERRORS (USB_CH_HCINTMSK_XactErrMsk_Msk | \ + USB_CH_HCINTMSK_BblErrMsk_Msk | \ + USB_CH_HCINTMSK_FrmOvrunMsk_Msk | \ + USB_CH_HCINTMSK_DataTglErrMsk_Msk) /**< Mask for selecting all channel error related events*/ +/*Macro to find pipe index using handle*/ +#define USBH_PIPE_GET_INDEX(handle) (((uint32_t)handle - (uint32_t)USB0_CH0_BASE)/(0x20U)) /**< Macro provides index of the USB channel based on its base address*/ + +#define XMC_USBH_API_VERSION ((uint16_t)((uint16_t)XMC_LIB_MAJOR_VERSION << 8U) |XMC_LIB_MINOR_VERSION) /**< USBH low level driver API version */ + +/* General return codes */ +#define XMC_USBH_DRIVER_OK 0 /**< Operation succeeded */ +#define XMC_USBH_DRIVER_ERROR -1 /**< Unspecified error */ +#define XMC_USBH_DRIVER_ERROR_BUSY -2 /**< Driver is busy*/ +#define XMC_USBH_DRIVER_ERROR_TIMEOUT -3 /**< Timeout occurred */ +#define XMC_USBH_DRIVER_ERROR_UNSUPPORTED -4 /**< Operation not supported*/ +#define XMC_USBH_DRIVER_ERROR_PARAMETER -5 /**< Parameter error*/ +#define XMC_USBH_DRIVER_ERROR_SPECIFIC -6 /**< Start of driver specific errors*/ + +/* USB Speed */ +#define XMC_USBH_SPEED_LOW 0U /**< Low-speed USB*/ +#define XMC_USBH_SPEED_FULL 1U /**< Full-speed USB*/ +#define XMC_USBH_SPEED_HIGH 2U /**< High-speed USB*/ + +/* USB Endpoint Type */ +#define XMC_USBH_ENDPOINT_CONTROL 0 /**< Control Endpoint*/ +#define XMC_USBH_ENDPOINT_ISOCHRONOUS 1 /**< Isochronous Endpoint*/ +#define XMC_USBH_ENDPOINT_BULK 2 /**< Bulk Endpoint*/ +#define XMC_USBH_ENDPOINT_INTERRUPT 3 /**< Interrupt Endpoint*/ + +#define XMC_USBH_SignalEndpointEvent_t XMC_USBH_SignalPipeEvent_t /**< Legacy name for the pipe event handler*/ + +/****** USB Host Packet Information *****/ +#define XMC_USBH_PACKET_TOKEN_Pos 0 /**< Packet token position*/ +#define XMC_USBH_PACKET_TOKEN_Msk (0x0FUL << XMC_USBH_PACKET_TOKEN_Pos) /**< Packet token mask*/ +#define XMC_USBH_PACKET_SETUP (0x01UL << XMC_USBH_PACKET_TOKEN_Pos) /**< SETUP Packet*/ +#define XMC_USBH_PACKET_OUT (0x02UL << XMC_USBH_PACKET_TOKEN_Pos) /**< OUT Packet*/ +#define XMC_USBH_PACKET_IN (0x03UL << XMC_USBH_PACKET_TOKEN_Pos) /**< IN Packet*/ +#define XMC_USBH_PACKET_PING (0x04UL << XMC_USBH_PACKET_TOKEN_Pos) /**< PING Packet*/ + +#define XMC_USBH_PACKET_DATA_Pos 4 /**< Packet data PID position*/ +#define XMC_USBH_PACKET_DATA_Msk (0x0FUL << XMC_USBH_PACKET_DATA_Pos) /**< Packet data PID mask*/ +#define XMC_USBH_PACKET_DATA0 (0x01UL << XMC_USBH_PACKET_DATA_Pos) /**< DATA0 PID */ +#define XMC_USBH_PACKET_DATA1 (0x02UL << XMC_USBH_PACKET_DATA_Pos) /**< DATA1 PID */ + +#define XMC_USBH_PACKET_SPLIT_Pos 8 +#define XMC_USBH_PACKET_SPLIT_Msk (0x0FUL << XMC_USBH_PACKET_SPLIT_Pos) +#define XMC_USBH_PACKET_SSPLIT (0x08UL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet */ +#define XMC_USBH_PACKET_SSPLIT_S (0x09UL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet: Data Start */ +#define XMC_USBH_PACKET_SSPLIT_E (0x0AUL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet: Data End */ +#define XMC_USBH_PACKET_SSPLIT_S_E (0x0BUL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet: Data All */ +#define XMC_USBH_PACKET_CSPLIT (0x0CUL << XMC_USBH_PACKET_SPLIT_Pos) /**< CSPLIT Packet */ + +#define XMC_USBH_PACKET_PRE (1UL << 12) /**< PRE Token */ + + +/****** USB Host Port Event *****/ +#define XMC_USBH_EVENT_CONNECT (1UL << 0) /**< USB Device Connected to Port */ +#define XMC_USBH_EVENT_DISCONNECT (1UL << 1) /**< USB Device Disconnected from Port */ +#define XMC_USBH_EVENT_OVERCURRENT (1UL << 2) /**< USB Device caused Overcurrent */ +#define XMC_USBH_EVENT_RESET (1UL << 3) /**< USB Reset completed */ +#define XMC_USBH_EVENT_SUSPEND (1UL << 4) /**< USB Suspend occurred */ +#define XMC_USBH_EVENT_RESUME (1UL << 5) /**< USB Resume occurred */ +#define XMC_USBH_EVENT_REMOTE_WAKEUP (1UL << 6) /**< USB Device activated Remote Wakeup */ + +/****** USB Host Pipe Event *****/ +#define XMC_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0) /**< Transfer completed */ +#define XMC_USBH_EVENT_HANDSHAKE_NAK (1UL << 1) /**< NAK Handshake received */ +#define XMC_USBH_EVENT_HANDSHAKE_NYET (1UL << 2) /**< NYET Handshake received */ +#define XMC_USBH_EVENT_HANDSHAKE_MDATA (1UL << 3) /**< MDATA Handshake received */ +#define XMC_USBH_EVENT_HANDSHAKE_STALL (1UL << 4) /**< STALL Handshake received */ +#define XMC_USBH_EVENT_HANDSHAKE_ERR (1UL << 5) /**< ERR Handshake received */ +#define XMC_USBH_EVENT_BUS_ERROR (1UL << 6) /**< Bus Error detected */ +/******************************************************************************* + * ENUMS + *******************************************************************************/ +/** + * @brief General power states of USB peripheral driver +*/ +typedef enum XMC_USBH_POWER_STATE { + XMC_USBH_POWER_OFF, /**< Power off: no operation possible */ + XMC_USBH_POWER_LOW, /**< Low Power mode: retain state, detect and signal wake-up events */ + XMC_USBH_POWER_FULL /**< Power on: full operation at maximum performance */ +} XMC_USBH_POWER_STATE_t; +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ +/** + * @brief USB host Driver Version +*/ +typedef struct XMC_USBH_DRIVER_VERSION { + uint16_t api; /**< API version */ + uint16_t drv; /**< Driver version */ +} XMC_USBH_DRIVER_VERSION_t; + + +/** + * @brief USB Host Port State +*/ +typedef struct XMC_USBH_PORT_STATE { + uint32_t connected : 1; /**< USB Host Port connected flag */ + uint32_t overcurrent : 1; /**< USB Host Port overcurrent flag */ + uint32_t speed : 2; /**< USB Host Port speed setting (ARM_USB_SPEED_xxx) */ +} XMC_USBH_PORT_STATE_t; + +/** + * @brief USB Host Pipe Handle. It represents the physical address of a USB channel +*/ +typedef uint32_t XMC_USBH_PIPE_HANDLE; +#define XMC_USBH_EP_HANDLE XMC_USBH_PIPE_HANDLE /**< Legacy name for pipe handle used by CMSIS*/ + +/** + * @brief USB Host Driver Capabilities. +*/ +typedef struct XMC_USBH_CAPABILITIES { + uint32_t port_mask : 15; /**< Root HUB available Ports Mask */ + uint32_t auto_split : 1; /**< Automatic SPLIT packet handling */ + uint32_t event_connect : 1; /**< Signal Connect event */ + uint32_t event_disconnect : 1; /**< Signal Disconnect event */ + uint32_t event_overcurrent : 1; /**< Signal Overcurrent event */ +} XMC_USBH_CAPABILITIES_t; + + +typedef void (*XMC_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event); /**< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event. */ +typedef void (*XMC_USBH_SignalPipeEvent_t) (XMC_USBH_PIPE_HANDLE pipe_hndl, uint32_t event); /**< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event. */ + +/** + * @brief Access structure of USB Host Driver. +*/ +typedef struct XMC_USBH_DRIVER { + XMC_USBH_DRIVER_VERSION_t (*GetVersion) (void); /**< Pointer to \ref ARM_USBH_GetVersion : Get driver version. */ + XMC_USBH_CAPABILITIES_t (*GetCapabilities) (void); /**< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities. */ + int32_t (*Initialize) (XMC_USBH_SignalPortEvent_t cb_port_event, + XMC_USBH_SignalPipeEvent_t cb_pipe_event); /**< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface. */ + int32_t (*Uninitialize) (void); /**< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface. */ + int32_t (*PowerControl) (XMC_USBH_POWER_STATE_t state); /**< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power. */ + int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); /**< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off. */ + int32_t (*PortReset) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset. */ + int32_t (*PortSuspend) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs). */ + int32_t (*PortResume) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs). */ + XMC_USBH_PORT_STATE_t (*PortGetState) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State. */ + XMC_USBH_PIPE_HANDLE (*PipeCreate) (uint8_t dev_addr, + uint8_t dev_speed, + uint8_t hub_addr, + uint8_t hub_port, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_max_packet_size, + uint8_t ep_interval); /**< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System. */ + int32_t (*PipeModify) (XMC_USBH_PIPE_HANDLE pipe_hndl, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t hub_addr, + uint8_t hub_port, + uint16_t ep_max_packet_size); /**< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System. */ + int32_t (*PipeDelete) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System. */ + int32_t (*PipeReset) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe. */ + int32_t (*PipeTransfer) (XMC_USBH_PIPE_HANDLE pipe_hndl, + uint32_t packet, + uint8_t *data, + uint32_t num); /**< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe. */ + uint32_t (*PipeTransferGetResult) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer. */ + int32_t (*PipeTransferAbort) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer. */ + uint16_t (*GetFrameNumber) (void); /**< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number. */ +} const XMC_USBH_DRIVER_t; + + +/** + * @brief Structure to handle various states of USB host driver. An instance exists for each USB channel + */ +typedef struct XMC_USBH0_pipe { + uint32_t packet; /**< Holds packet token and PID information of ongoing data packet transaction*/ + uint8_t *data; /**< Holds address of data buffer. It represents source buffer for OUT or SETUP transfer and + destination address for IN transfer*/ + uint32_t num; /**< Number of bytes of data to be transmitted*/ + uint32_t num_transferred_total; /**< Number of bytes transmitted or received at the moment*/ + uint32_t num_transferring; /**< Number of bytes being transmitted currently*/ + uint16_t ep_max_packet_size; /**< Maximum packet size for the selected pipe*/ + uint16_t interval_reload; /**< For INTERRUPT or ISOCHRONOUS pipe, it represents the period for repeated transfer*/ + uint16_t interval; /**< For INTERRUPT or ISOCHRONOUS pipe, it represents the decrementing count to reach 0 for initiating retransmission*/ + uint8_t ep_type; /**< Endpoint type for selected pipe*/ + uint8_t in_use; /**< Set to true when transfer is in progress and reset only after the /ref num of bytes is transferred*/ + uint8_t transfer_active; /**< Set to true when a transfer has been initiated and reset when event for transfer complete occurs*/ + uint8_t interrupt_triggered; /**< For INTERRUPT or ISOCHRONOUS pipe, indicates if retransmit timeout has occurred*/ + uint8_t event; /**< Holds pipe specific event flags*/ +} XMC_USBH0_pipe_t; + + +typedef struct xmc_usb_host_device { + USB0_GLOBAL_TypeDef *global_register; /**< Global register interface */ + USB0_CH_TypeDef *host_channel_registers; /**< Host channel interface */ + XMC_USBH_SignalPortEvent_t SignalPortEvent_cb; /**< Port event callback; set during init */ + XMC_USBH_SignalPipeEvent_t SignalPipeEvent_cb; /**< Pipe event callback; set during init */ + bool init_done; /**< init status */ + XMC_USBH_POWER_STATE_t power_state; /**< USB Power status */ + bool port_reset_active; /**< Port reset state */ +} XMC_USBH0_DEVICE_t; + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param gintsts USB global interrupt status. + * @return None. + * + * \parDescription:
+ * Updates logical state of the USB host driver based on the input status value. It handles port interrupt + * and channel interrupt. It responsible for updating data toggle information for multi-packet data transmission. + * It executes the callback function on transfer completion and reception of data. It also does error management and + * calls the relevant callback functions to indicate it to the application. + */ +void XMC_USBH_HandleIrq (uint32_t gintsts); +/** + * @param ms Delay in milliseconds. + * @return uint8_t Value has no significance for the low level driver. + * + * \parDescription:
+ * Function implements time delay logic. The USB host low level driver provides a weak definition + * for delay which has to re-implemented with time delay logic. The low level driver expects blocking + * implementation of the delay. + */ + uint8_t XMC_USBH_osDelay(uint32_t ms); + +/** + * @param port Address of the port which has the pin used to enable VBUS charge pump. + * @param pin Pin number in the port selected in previous argument using which the VBUS charge pump has to be enabled. + * @return None + * + * \parDescription:
+ * Configures the port pin with alternate output function 1. VBUS enabling pins work with alternate output function 1. \n + * Note:The input port pin should support USB VBUS as an alternate function. \n + * Typical ports that support VBUS enable are: P3_2 and P0_1. + * + */ +void XMC_USBH_Select_VBUS(XMC_GPIO_PORT_t* port, uint32_t pin); + +/** + * @return USB host mode interrupt status. Bit field USB0_BASE->GINTSTS_HOSTMODE + * + * \parDescription:
+ * Provides USB host global interrupt status. \n + * This value can be used to provide interrupt status to the IRQ handler function XMC_USBH_HandleIrq(). + * + */ +uint32_t XMC_USBH_GetInterruptStatus(void); + +/** + * @return None + * + * \parDescription:
+ * De-asserts resume bit. \n + * The function shall be called 20ms after detecting port remote wakeup event. \n + * + */ +void XMC_USBH_TurnOffResumeBit(void); +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +/** + * @} + */ +#endif +#endif /* XMC_USBH_H */ + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usic.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usic.h new file mode 100644 index 00000000..6eeb2daa --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_usic.h @@ -0,0 +1,2089 @@ +/** + * @file xmc_usic.h + * @date 2017-02-10 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * - Documentation improved
+ * + * 2015-05-08: + * - Added XMC_USIC_CH_SetInputTriggerCombinationMode() and XMC_USIC_CH_SetTransmitBufferStatus()
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-08-17: + * - Bug fixed in XMC_USIC_CH_SetTransmitBufferStatus API. OR operator removed. + * + * 2015-08-24: + * - Added APIs for enabling/disabling delay compensation XMC_USIC_CH_DisableDelayCompensation() and + * XMC_USIC_CH_DisableDelayCompensation() + * + * 2015-08-25: + * - Added APIs for defining if the data shift unit input is derived + * from the input data path DXn or from the selected protocol pre-processors: XMC_USIC_CH_ConnectInputDataShiftToPPP() + * and XMC_USIC_CH_ConnectInputDataShiftToDataInput() + * + * 2015-08-27: + * - Fixed bug in XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T value. + * - Added APIs for direct TBUF access: XMC_USIC_CH_WriteToTBUF() and XMC_USIC_CH_WriteToTBUFTCI() + * - Added APIs for external input for BRG configuration:XMC_USIC_CH_ConfigExternalInputSignalToBRG() and XMC_USIC_CH_SetBRGInputClockSource() + * + * 2015-08-28: + * - Added API for enabling the transfer trigger unit to set bit TCSR.TE if the trigger signal DX2T becomes active. Feature used for RS-232 + * Clear to Send (CTS) signal: XMC_USIC_CH_EnableTBUFDataValidTrigger() and XMC_USIC_CH_DisableTBUFDataValidTrigger(). + * + * 2016-03-09: + * - Optimization of write only registers + * + * 2016-04-10: + * - Added an API to put the data into FIFO when hardware port control is enabled: XMC_USIC_CH_TXFIFO_PutDataHPCMode()
+ * + * 2017-02-10: + * - Added XMC_USIC_CH_SetShiftDirection() to allow selection of shift direction of the data words for transmision and reception + * - Added XMC_USIC_CH_GetCaptureTimerValue() and XMC_USIC_CH_SetFractionalDivider() + * + * @endcond + * + */ + +#ifndef XMC_USIC_H +#define XMC_USIC_H +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_common.h" + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup USIC + * @brief Universal Serial Interface Channel(USIC) driver for serial communication. + * + * The Universal Serial Interface Channel(USIC) module is a flexible interface module + * covering several serial communication protocols. A USIC module contains two + * independent communication channels named USICx_CH0 and USICx_CH1, with x + * being the number of the USIC module. The user can program, during run-time, which protocol will be handled + * by each communication channel and which pins are used. + * The driver provides APIs, configuration structures and enumerations to configure common features of multiple serial + * communication protocols. + * + * USIC driver features: + * -# Allows configuration of FIFO for transmit and receive functions. + * -# Provides a structure type XMC_USIC_CH_t to represent the USIC channel registers in a programmer + friendly format. + * -# Allows configuration of automatic update for frame length, word length, slave select or slave address. + * -# Allows transmission of data to FIFO using XMC_USIC_CH_TXFIFO_PutData() and XMC_USIC_CH_TXFIFO_PutDataFLEMode() + * -# Allows reading of received data in FIFO using XMC_USIC_CH_RXFIFO_GetData() + * -# Allows configuration of baudrate using XMC_USIC_CH_SetBaudrate() + * -# Provides API to trigger interrupts using XMC_USIC_CH_TriggerServiceRequest() + * @{ + */ + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define XMC_USIC0 ((XMC_USIC_t *)USIC0_BASE) /**< USIC0 module base address */ +#define XMC_USIC0_CH0 ((XMC_USIC_CH_t *)USIC0_CH0_BASE) /**< USIC0 channel 0 base address */ +#define XMC_USIC0_CH1 ((XMC_USIC_CH_t *)USIC0_CH1_BASE) /**< USIC0 channel 1 base address */ + +#if defined(USIC1) +#define XMC_USIC1 ((XMC_USIC_t *)USIC1_BASE) /**< USIC1 module base address */ +#define XMC_USIC1_CH0 ((XMC_USIC_CH_t *)USIC1_CH0_BASE) /**< USIC1 channel 0 base address */ +#define XMC_USIC1_CH1 ((XMC_USIC_CH_t *)USIC1_CH1_BASE) /**< USIC1 channel 1 base address */ +#endif + +#if defined(USIC2) +#define XMC_USIC2 ((XMC_USIC_t *)USIC2_BASE) /**< USIC2 module base address */ +#define XMC_USIC2_CH0 ((XMC_USIC_CH_t *)USIC2_CH0_BASE) /**< USIC2 channel 0 base address */ +#define XMC_USIC2_CH1 ((XMC_USIC_CH_t *)USIC2_CH1_BASE) /**< USIC2 channel 1 base address */ +#endif + +#define USIC_CH_DXCR_DSEL_Msk USIC_CH_DX0CR_DSEL_Msk /**< Common mask for DSEL bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_DSEL_Pos USIC_CH_DX0CR_DSEL_Pos /**< Common mask for DSEL bitfield position in DXnCR register */ +#define USIC_CH_DXCR_SFSEL_Pos USIC_CH_DX0CR_SFSEL_Pos /**< Common mask for SFSEL bitfield position in DXnCR register */ +#define USIC_CH_DXCR_SFSEL_Msk USIC_CH_DX0CR_SFSEL_Msk /**< Common mask for SFSEL bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_DPOL_Msk USIC_CH_DX0CR_DPOL_Msk /**< Common mask for DPOL bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_DFEN_Msk USIC_CH_DX0CR_DFEN_Msk /**< Common mask for DFEN bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_DSEN_Msk USIC_CH_DX0CR_DSEN_Msk /**< Common mask for DSEN bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_CM_Pos USIC_CH_DX0CR_CM_Pos /**< Common mask for CM bitfield position in DXnCR register */ +#define USIC_CH_DXCR_CM_Msk USIC_CH_DX0CR_CM_Msk /**< Common mask for CM bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_INSW_Msk USIC_CH_DX0CR_INSW_Msk /**< Common mask for INSW bitfield mask in DXnCR register */ +#define USIC_CH_DXCR_INSW_pos USIC_CH_DX0CR_INSW_Pos /**< Common mask for INSW bitfield position in DXnCR register */ + +#if UC_FAMILY == XMC1 + #include "xmc1_usic_map.h" +#endif + +#if UC_FAMILY == XMC4 + #include "xmc4_usic_map.h" +#endif + +/******************************************************************************* + * ENUMS + *******************************************************************************/ + +/** + * USIC channel driver status + */ +typedef enum XMC_USIC_CH_STATUS +{ + XMC_USIC_CH_STATUS_OK, /**< USIC driver status : OK */ + XMC_USIC_CH_STATUS_ERROR, /**< USIC driver status : ERROR */ + XMC_USIC_CH_STATUS_BUSY /**< USIC driver status : BUSY */ +} XMC_USIC_CH_STATUS_t; + +/** +* USIC channel kernel mode +*/ +typedef enum XMC_USIC_CH_KERNEL_MODE +{ + XMC_USIC_CH_KERNEL_MODE_RUN_0 = 0x0UL, /**< Run mode 0 (transmission and reception possible)*/ + XMC_USIC_CH_KERNEL_MODE_RUN_1 = 0x1UL << USIC_CH_KSCFG_NOMCFG_Pos, /**< Run mode 1 (transmission and reception possible)*/ + XMC_USIC_CH_KERNEL_MODE_STOP_0 = 0x2UL << USIC_CH_KSCFG_NOMCFG_Pos, /**< Stop mode 0 (no transmission, but reception possible)*/ + XMC_USIC_CH_KERNEL_MODE_STOP_1 = 0x3UL << USIC_CH_KSCFG_NOMCFG_Pos /**< Stop mode 1 (both transmission and reception not possible)*/ +} XMC_USIC_CH_KERNEL_MODE_t; + +/** + * USIC channel operating mode + */ +typedef enum XMC_USIC_CH_OPERATING_MODE +{ + XMC_USIC_CH_OPERATING_MODE_IDLE = 0x0UL, /**< USIC channel idle */ + XMC_USIC_CH_OPERATING_MODE_SPI = 0x1UL << USIC_CH_CCR_MODE_Pos, /**< SPI mode */ + XMC_USIC_CH_OPERATING_MODE_UART = 0x2UL << USIC_CH_CCR_MODE_Pos, /**< UART mode */ + XMC_USIC_CH_OPERATING_MODE_I2S = 0x3UL << USIC_CH_CCR_MODE_Pos, /**< I2S mode */ + XMC_USIC_CH_OPERATING_MODE_I2C = 0x4UL << USIC_CH_CCR_MODE_Pos /**< I2C mode */ +} XMC_USIC_CH_OPERATING_MODE_t; + +/** + * USIC channel inputs + */ +typedef enum XMC_USIC_CH_INPUT +{ + XMC_USIC_CH_INPUT_DX0, /**< DX0 input */ + XMC_USIC_CH_INPUT_DX1, /**< DX1 input */ + XMC_USIC_CH_INPUT_DX2, /**< DX2 input */ + XMC_USIC_CH_INPUT_DX3, /**< DX3 input */ + XMC_USIC_CH_INPUT_DX4, /**< DX4 input */ + XMC_USIC_CH_INPUT_DX5 /**< DX5 input */ +} XMC_USIC_CH_INPUT_t; + +/** + * USIC channel input source sampling frequency + */ +typedef enum XMC_USIC_CH_INPUT_SAMPLING_FREQ +{ + XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH = 0x0UL, /**< Use fperiph frequency for input source sampling*/ + XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER = 0x1UL << USIC_CH_DXCR_SFSEL_Pos /**< Use fFD(fractional divider) frequency for input source sampling*/ +} XMC_USIC_CH_INPUT_SAMPLING_FREQ_t; + +/** + * USIC channel input combination mode + */ +typedef enum XMC_USIC_CH_INPUT_COMBINATION_MODE +{ + XMC_USIC_CH_INPUT_COMBINATION_MODE_TRIGGER_DISABLED = 0x0UL, /**< The trigger activation is disabled.*/ + XMC_USIC_CH_INPUT_COMBINATION_MODE_RISING_EDGE = 0x1UL, /**< A rising edge activates DXnT*/ + XMC_USIC_CH_INPUT_COMBINATION_MODE_FALLING_EDGE = 0x2UL, /**< A falling edge activates DXnT*/ + XMC_USIC_CH_INPUT_COMBINATION_MODE_BOTH_EDGES = 0x3UL, /**< Both edges activate DXnT*/ +} XMC_USIC_CH_INPUT_COMBINATION_MODE_t; + +/** + * USIC channel data transmission start modes. + * Data shifted out of the transmit pin depends on the value configured for the + * TDEN bitfield of the TCSR register. Following enum values are used for configuring + * the TCSR->TDEN bitfield. + */ +typedef enum XMC_USIC_CH_START_TRANSMISION_MODE +{ + XMC_USIC_CH_START_TRANSMISION_DISABLED = 0x0U, /**< Passive data level is sent out on transmission. */ + XMC_USIC_CH_START_TRANSMISION_ON_TDV = 0x1UL << USIC_CH_TCSR_TDEN_Pos, /**< Transmission of the data word in TBUF can be started if TDV = 1 */ + XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0 = 0x2UL << USIC_CH_TCSR_TDEN_Pos, /**< Transmission of the data word in TBUF can be started if TDV = 1 while DX2S_0 */ + XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1 = 0x3UL << USIC_CH_TCSR_TDEN_Pos /**< Transmission of the data word in TBUF can be started if TDV = 1 while DX2S_1 */ +} XMC_USIC_CH_START_TRANSMISION_MODE_t; + +/** + * USIC channel interrupt node pointers + */ +typedef enum XMC_USIC_CH_INTERRUPT_NODE_POINTER +{ + XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = USIC_CH_INPR_TSINP_Pos, /**< Node pointer for transmit shift interrupt */ + XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = USIC_CH_INPR_TBINP_Pos, /**< Node pointer for transmit buffer interrupt */ + XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE = USIC_CH_INPR_RINP_Pos, /**< Node pointer for receive interrupt */ + XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = USIC_CH_INPR_AINP_Pos, /**< Node pointer for alternate receive interrupt */ + XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL = USIC_CH_INPR_PINP_Pos /**< Node pointer for protocol related interrupts */ +} XMC_USIC_CH_INTERRUPT_NODE_POINTER_t; + +/** + * USIC channel events + */ +typedef enum XMC_USIC_CH_EVENT +{ + XMC_USIC_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */ + XMC_USIC_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */ + XMC_USIC_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */ + XMC_USIC_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */ + XMC_USIC_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */ + XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */ + XMC_USIC_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk /**< Baudrate generator event */ +} XMC_USIC_CH_EVENT_t; + +/** +* USIC channel parity mode +*/ +typedef enum XMC_USIC_CH_PARITY_MODE +{ + XMC_USIC_CH_PARITY_MODE_NONE = 0x0UL, /**< Disable parity mode */ + XMC_USIC_CH_PARITY_MODE_EVEN = 0x2UL << USIC_CH_CCR_PM_Pos, /**< Enable even parity mode */ + XMC_USIC_CH_PARITY_MODE_ODD = 0x3UL << USIC_CH_CCR_PM_Pos /**< Enable odd parity mode */ +} XMC_USIC_CH_PARITY_MODE_t; + +/** +* USIC channel data output mode +*/ +typedef enum XMC_USIC_CH_DATA_OUTPUT_MODE +{ + XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL = 0x0UL, /**< Data output normal mode */ + XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED = 0x1UL << USIC_CH_SCTR_DOCFG_Pos /**< Data output inverted mode */ +} XMC_USIC_CH_DATA_OUTPUT_MODE_t; + +/** +* USIC channel data transmit buffer status +*/ +typedef enum XMC_USIC_CH_TBUF_STATUS +{ + XMC_USIC_CH_TBUF_STATUS_IDLE = 0x0UL, /**< Transfer buffer is currently idle*/ + XMC_USIC_CH_TBUF_STATUS_BUSY = USIC_CH_TCSR_TDV_Msk /**< Transfer buffer is currently busy*/ +} XMC_USIC_CH_TBUF_STATUS_t; + + + +/** +* USIC channel data transmit buffer status modification +*/ +typedef enum XMC_USIC_CH_TBUF_STATUS_SET +{ + XMC_USIC_CH_TBUF_STATUS_SET_BUSY = 0x1UL, /**< Set Transfer buffer status to busy*/ + XMC_USIC_CH_TBUF_STATUS_SET_IDLE = 0x2UL /**< Set Transfer buffer status to idle*/ +} XMC_USIC_CH_TBUF_STATUS_SET_t; + +/** +* USIC channel receive buffer status +*/ +typedef enum XMC_USIC_CH_RBUF_STATUS +{ + XMC_USIC_CH_RBUF_STATUS_DATA_VALID0 = USIC_CH_RBUFSR_RDV0_Msk, /**< RBUF0 data has not yet been read out*/ + XMC_USIC_CH_RBUF_STATUS_DATA_VALID1 = USIC_CH_RBUFSR_RDV1_Msk /**< RBUF1 data has not yet been read out*/ +} XMC_USIC_CH_RBUF_STATUS_t; + +/** + * USIC channel output signal passive data level +*/ +typedef enum XMC_USCI_CH_PASSIVE_DATA_LEVEL +{ + XMC_USIC_CH_PASSIVE_DATA_LEVEL0 = 0x0UL, /**< Passive level(idle mode signal level) 0 */ + XMC_USIC_CH_PASSIVE_DATA_LEVEL1 = 0x1UL << USIC_CH_SCTR_PDL_Pos /**< Passive level(idle mode signal level) 1 */ +} XMC_USIC_CH_PASSIVE_DATA_LEVEL_t; + +/** +* USIC channel receive FIFO size +*/ +typedef enum XMC_USIC_CH_FIFO_SIZE +{ + XMC_USIC_CH_FIFO_DISABLED = 0x0U, /**< FIFO Disabled */ + XMC_USIC_CH_FIFO_SIZE_2WORDS = 0x1U, /**< FIFO size: 2 words */ + XMC_USIC_CH_FIFO_SIZE_4WORDS = 0x2U, /**< FIFO size: 4 words */ + XMC_USIC_CH_FIFO_SIZE_8WORDS = 0x3U, /**< FIFO size: 8 words */ + XMC_USIC_CH_FIFO_SIZE_16WORDS = 0x4U, /**< FIFO size: 16 words */ + XMC_USIC_CH_FIFO_SIZE_32WORDS = 0x5U, /**< FIFO size: 32 words */ + XMC_USIC_CH_FIFO_SIZE_64WORDS = 0x6U /**< FIFO size: 64 words */ +} XMC_USIC_CH_FIFO_SIZE_t; + +/** +* USIC channel transmit FIFO interrupt node pointers +*/ +typedef enum XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER +{ + XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD = USIC_CH_TBCTR_STBINP_Pos, /**< Node pointer for FIFO standard transmit interrupt */ + XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE = USIC_CH_TBCTR_ATBINP_Pos /**< Node pointer for transmit FIFO error interrupt */ +} XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t; + +/** +* USIC channel transmit FIFO event configuration +*/ +typedef enum XMC_USIC_CH_TXFIFO_EVENT_CONF +{ + XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD = USIC_CH_TBCTR_STBIEN_Msk, /**< Enable FIFO standard transmit interrupt */ + XMC_USIC_CH_TXFIFO_EVENT_CONF_ERROR = (int32_t)USIC_CH_TBCTR_TBERIEN_Msk /**< Enable transmit FIFO error interrupt */ +} XMC_USIC_CH_TXFIFO_EVENT_CONF_t; + +/** +* USIC channel transmit FIFO status +*/ +typedef enum XMC_USIC_CH_TXFIFO_EVENT +{ + XMC_USIC_CH_TXFIFO_EVENT_STANDARD = USIC_CH_TRBSR_STBI_Msk, /**< Transmit FIFO status: Standard event */ + XMC_USIC_CH_TXFIFO_EVENT_ERROR = USIC_CH_TRBSR_TBERI_Msk /**< Transmit FIFO status: Error event */ +} XMC_USIC_CH_TXFIFO_EVENT_t; + +/** +* USIC channel receive FIFO interrupt node pointers +*/ +typedef enum XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER +{ + XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD = USIC_CH_RBCTR_SRBINP_Pos, /**< Node pointer for FIFO standard receive interrupt */ + XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE = USIC_CH_RBCTR_ARBINP_Pos /**< Node pointer for FIFO alternative receive interrupt */ +} XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t; + +/** +* USIC channel receive FIFO event configuration +*/ +typedef enum XMC_USIC_CH_RXFIFO_EVENT_CONF +{ + XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD = USIC_CH_RBCTR_SRBIEN_Msk, /**< Enable FIFO standard receive interrupt */ + XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR = (int32_t)USIC_CH_RBCTR_RBERIEN_Msk, /**< Enable receive FIFO error interrupt */ + XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE = USIC_CH_RBCTR_ARBIEN_Msk /**< Enable FIFO alternative receive interrupt */ +} XMC_USIC_CH_RXFIFO_EVENT_CONF_t; + +/** +* USIC channel receive FIFO status +*/ +typedef enum XMC_USIC_CH_RXFIFO_EVENT +{ + XMC_USIC_CH_RXFIFO_EVENT_STANDARD = USIC_CH_TRBSR_SRBI_Msk, /**< Receive FIFO status: Standard event */ + XMC_USIC_CH_RXFIFO_EVENT_ERROR = USIC_CH_TRBSR_RBERI_Msk, /**< Receive FIFO status: Error event */ + XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE = USIC_CH_TRBSR_ARBI_Msk /**< Receive FIFO status: Alternative event */ +} XMC_USIC_CH_RXFIFO_EVENT_t; + +/** +* USIC channel baudrate generator clock source +*/ +typedef enum XMC_USIC_CH_BRG_CLOCK_SOURCE +{ + XMC_USIC_CH_BRG_CLOCK_SOURCE_DIVIDER = 0x0UL, /**< Baudrate generator clock source : Source divider. (Internal clock source)*/ + XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T = 0x2UL << USIC_CH_BRG_CLKSEL_Pos /**< Baudrate generator clock source : DX1T. (External clock source) */ +} XMC_USIC_CH_BRG_CLOCK_SOURCE_t; + +/** +* USIC channel baudrate generator divider mode +*/ +typedef enum XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE +{ + XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_DISABLED = 0x0UL, /**< Baudrate generator clock divider: Disabled */ + XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL = 0x1UL << USIC_CH_FDR_DM_Pos, /**< Baudrate generator clock divider: Normal mode */ + XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL = 0x2UL << USIC_CH_FDR_DM_Pos /**< Baudrate generator clock divider: Fractional mode */ +} XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t; + +/** +* USIC channel baudrate generator master clock passive level +*/ +typedef enum XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL +{ + XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0 = 0x0UL, /**< Baudrate generator master clock passive level(idle mode signal level) 0*/ + XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1 = 0x1UL << USIC_CH_BRG_MCLKCFG_Pos /**< Baudrate generator master clock passive level((idle mode signal level)) 1*/ +} XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t; + +/** +* USIC channel baudrate generator shift clock passive level +*/ +typedef enum XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL +{ + XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED = 0x0UL, /**< Shift clock passive level 0, delay disabled */ + XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED = 0x1UL << USIC_CH_BRG_SCLKCFG_Pos, /**< Shift clock passive level 1, delay disabled */ + XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED = (int32_t)(0x2UL << USIC_CH_BRG_SCLKCFG_Pos), /**< Shift clock passive level 0, delay enabled */ + XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED = (int32_t)(0x3UL << USIC_CH_BRG_SCLKCFG_Pos) /**< Shift clock passive level 1, delay enabled */ +} XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t; + +/** +* USIC channel baudrate generator shift clock output +*/ +typedef enum XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT +{ + XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = 0x0UL, /**< Baudrate generator shift clock output: SCL.(Internally generated shift clock)*/ + XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = 0x1UL << USIC_CH_BRG_SCLKOSEL_Pos /**< Baudrate generator shift clock output: DX1. (External input shift clock)*/ +} XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t; + +/** +* USIC channel shift direction. +* Defines the shift direction of the data words for transmission and reception +*/ +typedef enum XMC_USIC_CH_SHIFT_DIRECTION +{ + XMC_USIC_CH_SHIFT_DIRECTION_LSB_FIRST = 0x0UL, /**< Shift LSB first. The first data bit of a data word is located at bit position 0. */ + XMC_USIC_CH_SHIFT_DIRECTION_MSB_FIRST = 0x1UL << USIC_CH_SCTR_SDIR_Msk /**< Shift MSB first. The first data bit of a data word is located at the bit position given by the configured word length. */ +} XMC_USIC_CH_SHIFT_DIRECTION_t; + + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ + +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * USIC module structure + */ +typedef USIC_GLOBAL_TypeDef XMC_USIC_t; + +/** + * USIC channel structure.
The members of the structure are same as in the device header file, + * except for some registers. + * DX0CR, DX1CR, DX2CR, DX3CR, DX4CR and DX5CR are replaced with the array DXCR[6]. + * TBUF0 to TBUF31 are replaced with TBUF[32]. + * IN0 to IN31 are replaced with IN[32]. + */ +typedef struct XMC_USIC_CH +{ + __I uint32_t RESERVED0; + __I uint32_t CCFG; /**< Channel configuration register*/ + __I uint32_t RESERVED1; + __IO uint32_t KSCFG; /**< Kernel state configuration register*/ + __IO uint32_t FDR; /**< Fractional divider configuration register*/ + __IO uint32_t BRG; /**< Baud rate generator register*/ + __IO uint32_t INPR; /**< Interrupt node pointer register*/ + __IO uint32_t DXCR[6]; /**< Input control registers DX0 to DX5.*/ + __IO uint32_t SCTR; /**< Shift control register*/ + __IO uint32_t TCSR; + + union { + __IO uint32_t PCR_IICMode; /**< I2C protocol configuration register*/ + __IO uint32_t PCR_IISMode; /**< I2S protocol configuration register*/ + __IO uint32_t PCR_SSCMode; /**< SPI protocol configuration register*/ + __IO uint32_t PCR; /**< Protocol configuration register*/ + __IO uint32_t PCR_ASCMode; /**< UART protocol configuration register*/ + }; + __IO uint32_t CCR; /**< Channel control register*/ + __IO uint32_t CMTR; /**< Capture mode timer register*/ + + union { + __IO uint32_t PSR_IICMode; /**< I2C protocol status register*/ + __IO uint32_t PSR_IISMode; /**< I2S protocol status register*/ + __IO uint32_t PSR_SSCMode; /**< SPI protocol status register*/ + __IO uint32_t PSR; /**< Protocol status register*/ + __IO uint32_t PSR_ASCMode; /**< UART protocol status register*/ + }; + __O uint32_t PSCR; /**< Protocol status clear register*/ + __I uint32_t RBUFSR; /**< Receive buffer status register*/ + __I uint32_t RBUF; /**< Receive buffer register*/ + __I uint32_t RBUFD; /**< Debug mode receive buffer register*/ + __I uint32_t RBUF0; /**< Receive buffer 0*/ + __I uint32_t RBUF1; /**< Receive buffer 1*/ + __I uint32_t RBUF01SR; /**< Receive buffer status register*/ + __O uint32_t FMR; /**< Flag modification register*/ + __I uint32_t RESERVED2[5]; + __IO uint32_t TBUF[32]; /**< Tranmsit buffer registers*/ + __IO uint32_t BYP; /**< FIFO bypass register*/ + __IO uint32_t BYPCR; /**< FIFO bypass control register*/ + __IO uint32_t TBCTR; /**< Transmit FIFO control register*/ + __IO uint32_t RBCTR; /**< Receive FIFO control register*/ + __I uint32_t TRBPTR; /**< Transmit/recive buffer pointer register*/ + __IO uint32_t TRBSR; /**< Transmit/receive buffer status register*/ + __O uint32_t TRBSCR; /**< Transmit/receive buffer status clear register*/ + __I uint32_t OUTR; /**< Receive FIFO output register*/ + __I uint32_t OUTDR; /**< Receive FIFO debug output register*/ + __I uint32_t RESERVED3[23]; + __O uint32_t IN[32]; /**< Transmit FIFO input register*/ +} XMC_USIC_CH_t; + + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif + +/******************************************************************************* + * API PROTOTYPES + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +__STATIC_INLINE bool XMC_USIC_IsModuleValid(const XMC_USIC_t *const module) +{ + bool tmp; + + tmp = (module == XMC_USIC0); +#if defined(XMC_USIC1) + tmp = tmp || (module == XMC_USIC1); +#endif +#if defined(XMC_USIC2) + tmp = tmp || (module == XMC_USIC2); +#endif + + return tmp; +} + +__STATIC_INLINE bool XMC_USIC_IsChannelValid(const XMC_USIC_CH_t *const channel) +{ + bool tmp; + + tmp = ((channel == XMC_USIC0_CH0) || (channel == XMC_USIC0_CH1)); +#if defined(XMC_USIC1) + tmp = tmp || ((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1)); +#endif +#if defined(XMC_USIC2) + tmp = tmp || ((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1)); +#endif + + return tmp; +} + +/* Common APIs */ + +/** + * @param usic Pointer to USIC module handler of type @ref XMC_USIC_t.\n + * \b Range: @ref XMC_USIC0 to @ref XMC_USIC2 based on device support. + * @return None + * + * \parDescription
+ * Enables the USIC module.\n\n + * Enables the clock for the USIC module by following the + * clock enabling sequence for the selected device. + * + * \parRelated APIs:
+ * XMC_USIC_CH_Enable(), XMC_USIC_Disable() \n\n\n + */ +void XMC_USIC_Enable(XMC_USIC_t *const usic); +/** + * @param usic Pointer to USIC module handler of type @ref XMC_USIC_t.\n + * \b Range: @ref XMC_USIC0 to @ref XMC_USIC2 based on device support. + * @return None + * + * \parDescription
+ * Disables the USIC module.\n\n + * Disables the clock for the USIC module by following the clock + * disabling sequence for the selected device. + * + * \parRelated APIs:
+ * XMC_USIC_CH_Disable(), XMC_USIC_Enable() \n\n\n + */ +void XMC_USIC_Disable(XMC_USIC_t *const usic); +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Enables the USIC channel. \n\n + * USIC channel is enabled by setting the module enable bit in KSCFG register bitfield MODEN. + * On enabling, the channel is set to idle mode. + * + * \parRelated APIs:
+ * XMC_USIC_CH_Disable(), XMC_USIC_Enable() \n\n\n + */ +void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel); +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Disables the USIC channel.\n\n + * USIC channel is disabled by setting the module enable bit(MDEN) to 0 in the register KSCFG. + * + * \parRelated APIs:
+ * XMC_USIC_CH_Enable(), XMC_USIC_Disable() \n\n\n + */ +void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param rate Desired baudrate. \b Range: minimum value = 100, maximum value depends on the peripheral clock frequency \n + * and \a oversampling. Maximum baudrate can be derived using the formula: (fperiph * 1023)/(1024 * oversampling) + * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n + * This can be related to the number of samples for each logic state of the data signal. \n + * \b Range: 1 to 32. Value should be chosen based on the protocol used. + * @return Status indicating the baudrate configuration.\n + * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured, + * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid. + * + * \parDescription
+ * Configures the baudrate of the USIC channel. \n\n + * Baudrate is configured by considering the peripheral frequency and the desired baudrate. + * Optimum values of FDR->STEP and BRG->PDIV are calulated and used for generating the desired + * baudrate. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetStartTransmisionMode(), XMC_USIC_CH_SetInputSource() \n\n\n + */ +XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param pdiv Desired divider for the external frequency input. \b Range: minimum value = 1, maximum value = 1024 \n + * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n + * This can be related to the number of samples for each logic state of the data signal. \n + * \b Range: 1 to 32. Value should be chosen based on the protocol used. + * @param combination_mode Selects which edge of the synchronized(and optionally filtered) signal DXnS actives the trigger + * output DXnT of the input stage. + * + * @return None + * + * \parDescription
+ * Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and + * the combination mode of the USIC channel. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n + */ +void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, + const uint16_t pdiv, + const uint32_t oversampling, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @param source Input source select for the input stage. The table below maps the enum value with the input channel. + * + * + *
0DXnA
1DXnB
2DXnC
3DXnD
4DXnE
5DXnF
6DXnG
7Always 1
+ * @return None + * + * \parDescription
+ * Selects the data source for USIC input stage.\n\n + * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the input stages + * like DX0CR, DX1CR etc. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableInputInversion(), XMC_USIC_CH_EnableInputDigitalFilter(), XMC_USIC_CH_EnableInputSync(), + * XMC_USIC_CH_SetInputSamplingFreq()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input, const uint8_t source) +{ + channel->DXCR[input] = (uint32_t)((channel->DXCR[input] & (uint32_t)(~USIC_CH_DXCR_DSEL_Msk)) | + ((uint32_t)source << USIC_CH_DXCR_DSEL_Pos)); +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * The input of the data shift unit is controlled by the + * protocol pre-processor. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_ConnectInputDataShiftToDataInput()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_ConnectInputDataShiftToPPP(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_INSW_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * The input of the data shift unit is connected to + * the selected data input line. \n\n + * + * This setting is used + * if the signals are directly derived from an input + * pin without treatment by the protocol preprocessor. + * \parRelated APIs:
+ * XMC_USIC_CH_ConnectInputDataShiftToPPP()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_ConnectInputDataShiftToDataInput(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] |= USIC_CH_DXCR_INSW_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Enables input inversion for USIC channel input data signal. \n\n + * + * Polarity of the input source can be changed to provide inverted data input. + * \parRelated APIs:
+ * XMC_USIC_CH_DisableInputInversion()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] |= USIC_CH_DXCR_DPOL_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Disables input inversion for USIC channel. \n\n + * + * Resets the input data polarity for the USIC channel input data signal. + * \parRelated APIs:
+ * XMC_USIC_CH_EnableInputInversion()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DPOL_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Enables delay compensation. \n\n + * + * Delay compensation can be applied to the receive path. + * \parRelated APIs:
+ * XMC_USIC_CH_DisableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + channel->DXCR[1U] |= USIC_CH_DX1CR_DCEN_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Disables delay compensation.. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableDelayCompensation()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel) +{ + channel->DXCR[1U] &=(uint32_t)~USIC_CH_DX1CR_DCEN_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Enables the input digital filter for USIC channel input data signal. \n\n + * Input data signal from the selected multiplexer will be digitally filtered. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] |= (uint32_t)USIC_CH_DXCR_DFEN_Msk; +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Disables the input digital filter for USIC channel input data signal. \n\n + * Input data signal from the selected multiplexer will not be digitally filtered. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DFEN_Msk; +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Enables input synchronization for the USIC channel input data signal. \n\n + * Input data signal from the selected multiplexer will be synchronized with fPERIPH. + * A noisy signal can be synchronized and filtered by enabling the digital filter. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableInputSync(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] |=(uint32_t)USIC_CH_DXCR_DSEN_Msk; +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @return None + * + * \parDescription
+ * Disables input synchronization for the USIC channel input data signal. \n\n + * Input data signal from the selected multiplexer will not be synchronized. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_DisableInputDigitalFilter() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableInputSync(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) +{ + channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DSEN_Msk; +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @param sampling_freq Sampling frequency value of type \a XMC_USIC_CH_INPUT_SAMPLING_FREQ_t. + * @return None + * + * \parDescription
+ * Sets sampling frequency for USIC channel input data signal. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_INPUT_t input, + const XMC_USIC_CH_INPUT_SAMPLING_FREQ_t sampling_freq) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DXCR_SFSEL_Msk)) | + ((uint32_t)sampling_freq); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.. + * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n + * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5 + * @param combination_mode Combination mode value of type \a XMC_USIC_CH_INPUT_COMBINATION_MODE_t. + * @return None + * + * \parDescription
+ * Selects which edge of the synchronized signal DXnS activates the trigger output DXnT of the input stage. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetInputTriggerCombinationMode(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_INPUT_t input, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) +{ + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DXCR_CM_Msk)) | + ((uint32_t)combination_mode << USIC_CH_DXCR_CM_Pos); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param clock_source clock source for the BRG. + * @return None + * + * \parDescription
+ * Sets the clock source for the BRG. \n\n + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetInputTriggerCombinationMode(), XMC_USIC_CH_SetExternalClockBRGDivider()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetBRGInputClockSource(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_BRG_CLOCK_SOURCE_t clock_source) +{ + channel->BRG = (uint32_t)(channel->BRG & (~USIC_CH_BRG_CLKSEL_Msk)) | (uint32_t)(clock_source); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data Data to be transmitted. \n + * \b Range: 16bit unsigned data. minimum= 0, maximum= 65535 + * @return None + * + * \parDescription
+ * Writes data into the transmit buffer. \n\n + * The data provided is placed in TBUF[0U]. + * + * + * \parRelated APIs:
+ * XMC_USIC_CH_WriteToTBUFTCI() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_WriteToTBUF(XMC_USIC_CH_t *const channel, const uint16_t data) +{ + channel->TBUF[0U] = data; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data Data to be transmitted. + * @param transmit_control_information transmit control information to be configured while transmitting the data. \n + * \b Range: minimum= 0, maximum= 31. + * @return None + * + * \parDescription
+ * Writes data to the transmit buffer in a control mode. \n\n + * When the respective control mode is enabled , this API can be used. + * + * + * \parRelated APIs:
+ * XMC_USIC_CH_WriteToTBUF() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_WriteToTBUFTCI(XMC_USIC_CH_t *const channel, + const uint16_t data, + const uint32_t transmit_control_information) +{ + channel->TBUF[transmit_control_information] = data; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param word_length Number of bits to be configured for a data word. \n + * \b Range: minimum= 1, maximum= 16. \n + * e.g: For word length of 8, \a word_length should be provided as 8. + * @return None + * + * \parDescription
+ * Sets the data word length in number of bits. \n\n + * Sets the number of bits to represent a data word. Frame length should be a multiple of word length. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetFrameLength()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length) +{ + channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_WLE_Msk)) | + (uint32_t)(((uint32_t)word_length - 1UL) << USIC_CH_SCTR_WLE_Pos); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param word_length Number of bits to be configured for a data word. \n + * \b Range: minimum= 1, maximum= 16. \n + * e.g: For word length of 8, \a word_length should be provided as 8. + * @return None + * + * \parDescription
+ * Sets the data word length in number of bits. \n\n + * Sets the number of bits to represent a data word. Frame length should be a multiple of word length. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetFrameLength()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetShiftDirection(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_SHIFT_DIRECTION_t shift_direction) +{ + channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_SDIR_Msk)) | (uint32_t)shift_direction; +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Captured counter value + * + * + * \parDescription
+ * The value of the counter is captured if one of the trigger signals DX0T or DX1T are activated by the corresponding input stage. + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_GetCaptureTimerValue(const XMC_USIC_CH_t *const channel) +{ + return channel->CMTR; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param mode divider mode ::XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t \n + * @param step divider \n + * \b XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL resulting divider = 1023 - step \n + * \b XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL resulting divider = 1023 / step \n + * + * @return None + * + * \parDescription
+ * The fractional divider generates its output frequency fFD by either dividing the input frequency fPERIPH by an integer factor n or by multiplication of n/1024. + * + */ +__STATIC_INLINE void XMC_USIC_CH_SetFractionalDivider(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t mode, const uint16_t step) +{ + channel->FDR = mode | step; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param frame_length Number of bits in a frame. \n + * \b Range: minimum= 1, maximum= 0x3f. The maximum value for fixed frame size is 0x3f. \n + * e.g: For a frame length of 16, \a frame_length should be provided as 16. + * @return None + * + * \parDescription
+ * Define the data frame length.\n\n + * Set the number of bits to be serially transmitted in a frame. + * The frame length should be multiples of word length. If the value is set to 0x40, the frame length + * has to be controlled explicitly. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetWordLength(), XMC_USIC_CH_EnableFrameLengthControl() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length) +{ + channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_FLE_Msk)) | + (((uint32_t)frame_length - 0x1U) << USIC_CH_SCTR_FLE_Pos); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Bit mask of the channel events to be enabled. Use @ref XMC_USIC_CH_EVENT_t for the bit masks. \n + * \b Range: @ref XMC_USIC_CH_EVENT_RECEIVE_START, @ref XMC_USIC_CH_EVENT_DATA_LOST etc. Multiple events + * can be combined using \a OR operation. + * @return None + * + * \parDescription
+ * Enable the channel interrupt events.\n\n + * Common channel events related to serial communication can be configured using this API. + * Multiple events can be combined using the bitwise OR operation and configured in one function call. + * XMC_USIC_CH_EVENT_t enumerates multiple protocol event bitmasks. These enumerations can be used as input to the API. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableEvent(), XMC_USIC_CH_SetInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR |= event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Bit mask of the channel events to be disabled. Use @ref XMC_USIC_CH_EVENT_t for the bit masks. \n + * \b Range: @ref XMC_USIC_CH_EVENT_RECEIVE_START, @ref XMC_USIC_CH_EVENT_DATA_LOST etc. Multiple events + * can be combined using \a OR operation. + * @return None + * + * \parDescription
+ * Disable the channel interrupt events. \n\n + * Multiple events can be combined using the bitwise OR operation and configured in one function call. + * XMC_USIC_CH_EVENT_t enumerates multiple protocol event bitmasks. These enumerations can be used as input to the API. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableEvent(), XMC_USIC_CH_SetInterruptNodePointer() \n\n\n +*/ +__STATIC_INLINE void XMC_USIC_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR &= (uint32_t)~event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param interrupt_node Interrupt node pointer to be configured. \n + * \b Range: @ref XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, + * @ref XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc. + * @param service_request Service request number.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets the interrupt node for USIC channel events. \n\n + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * The NVIC node gets linked to the interrupt event by doing so.
+ * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableEvent() \n\n\n + */ +void XMC_USIC_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Stataus @ref XMC_USIC_CH_TBUF_STATUS_IDLE if transmit buffer is free, + * @ref XMC_USIC_CH_TBUF_STATUS_BUSY if transmit buffer is busy. + * + * \parDescription
+ * Gets transmit buffer status. \n\n + * Status indicates whether the transmit buffer is free, or busy transmitting data. + * The status depends on the value of TDV flag in TCSR register. + * This status can be used while transmitting data. Transmit data when the transmit buffer + * status is @ref XMC_USIC_CH_TBUF_STATUS_IDLE. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetDataOutputMode() \n\n\n + */ +__STATIC_INLINE XMC_USIC_CH_TBUF_STATUS_t XMC_USIC_CH_GetTransmitBufferStatus(XMC_USIC_CH_t *const channel) +{ + return (XMC_USIC_CH_TBUF_STATUS_t)(channel->TCSR & USIC_CH_TCSR_TDV_Msk); +} + +/** + * @brief API to get receive buffer status + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status of data validity check for RBUF0 and RBUF1. \n + * Returned value should be masked with RDV0 and RDV1 bits to know the status. \n + * \b Range: @ref XMC_USIC_CH_RBUF_STATUS_DATA_VALID0, @ref XMC_USIC_CH_RBUF_STATUS_DATA_VALID1. + * + * \parDescription
+ * Checks if RBUF0 and RBUF1 have valid unread data. \n\n + * It checks the bits RDV0 and RDV1 of the RBUFSR register. + * Returns the value of RBUFSR masked with bitmasks of RDV0 and RDV1. + * It can be used to decide whether 2bytes has to be read from RBUF or 1 byte. + * If both bitmasks XMC_USIC_CH_RBUF_STATUS_DATA_VALID0 and XMC_USIC_CH_RBUF_STATUS_DATA_VALID1 + * are set, then 2 bytes can be read from RBUF. If only either of them is set, then only one byte + * can be read from RBUF. + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_GetReceiveBufferStatus(XMC_USIC_CH_t *const channel) +{ + return ((uint32_t) (channel->RBUFSR & (USIC_CH_RBUFSR_RDV0_Msk | USIC_CH_RBUFSR_RDV1_Msk))); +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param start_transmision_mode Transmission mode to be enabled. \n + * \b Range: @ref XMC_USIC_CH_START_TRANSMISION_DISABLED, + * @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV, @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0, + * @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1 + * + * @return None + * + * \parDescription
+ * Configures data transmission. \n\n + * The configuration affects the data shifted on the DOUT0 pin. + * + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetDataOutputMode() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetStartTransmisionMode(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_START_TRANSMISION_MODE_t start_transmision_mode) +{ + channel->TCSR = (uint32_t)(channel->TCSR & (~USIC_CH_TCSR_TDEN_Msk)) | (uint32_t)start_transmision_mode; +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data_output_mode Data output mode. \n + * \b Range: @ref XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL, @ref XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED + * @return None + * + * \parDescription
+ * Configures the mode for data output. \n\n + * USIC channel can be configured to shift inverted data or direct data based on the input to the API. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetStartTransmisionMode() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetDataOutputMode(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_DATA_OUTPUT_MODE_t data_output_mode) +{ + channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_DOCFG_Msk)) | (uint32_t)data_output_mode; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Enables automatic update of frame length. \n\n + * When the automatic update of frame length is enabled, frame length is configured based on the + * index of the TBUF[]/IN[] register array. When the data is written to TBUF[x], frame length is configured + * with the mask value of \a x at the last 5 bit positions. Same logic is applicable if data is written to + * IN[x] register. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_TXFIFO_PutDataFLEMode() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableFrameLengthControl(XMC_USIC_CH_t *const channel) +{ + channel->TCSR = (uint32_t)(channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk | + USIC_CH_TCSR_SELMD_Msk | + USIC_CH_TCSR_WAMD_Msk | + USIC_CH_TCSR_HPCMD_Msk))) | + (uint32_t)USIC_CH_TCSR_FLEMD_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Disables automatic update of frame length. \n\n + * When automatic update of frame length is disabled, frame length has to configured explicitly. + * Frame length remains fixed until it is changed again. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_SetFrameLength() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableFrameLengthControl(XMC_USIC_CH_t *const channel) +{ + channel->TCSR &= (uint32_t)~USIC_CH_TCSR_FLEMD_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Bit TCSR.TE is set if DX2T becomes active while TDV = 1. \n\n + * Enables the transfer trigger unit to set bit TCSR.TE if the trigger signal DX2T becomes active + * for event driven transfer starts. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableTBUFDataValidTrigger()\n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableTBUFDataValidTrigger(XMC_USIC_CH_t *const channel) +{ + channel->TCSR |= (uint32_t)USIC_CH_TCSR_TDVTR_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Disables the trigger of TDV depending on DX2T signal. \n\n + * Bit TCSR.TE is permanently set. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableTBUFDataValidTrigger() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableTBUFDataValidTrigger(XMC_USIC_CH_t *const channel) +{ + channel->TCSR &= (uint32_t)~USIC_CH_TCSR_TDVTR_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param service_request_line service request number of the event to be triggered. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Trigger a USIC interrupt service request.\n\n + * When the USIC service request is triggered, the NVIC interrupt associated with it will be + * generated if enabled. + * + * \parRelated APIs:
+ * XMC_USIC_CH_SetInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line) +{ + channel->FMR = (uint32_t)(USIC_CH_FMR_SIO0_Msk << service_request_line); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param transmit_buffer_status clearing or setting the TDV flag. \n + * + * @return None + * + * \parDescription
+ * Modify TCSR.TDV and TCSR.TE to control the start of a data word transmission by software. + * + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetTransmitBufferStatus(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_TBUF_STATUS_SET_t transmit_buffer_status) +{ + channel->FMR = (uint32_t)transmit_buffer_status; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param passive_level Value of passive level for the channel. \n + * \b Range: @ref XMC_USIC_CH_PASSIVE_DATA_LEVEL0, @ref XMC_USIC_CH_PASSIVE_DATA_LEVEL1 + * @return None + * + * \parDescription
+ * Set the passive data level of the output signal. \n\n + * When the USIC channel transmit stage is idle, the output signal level stays at the + * configured passive level. + * + * \parRelated APIs:
+ * XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetStartTransmisionMode() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetPassiveDataLevel(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_PASSIVE_DATA_LEVEL_t passive_level) +{ + channel->SCTR &= (~USIC_CH_SCTR_PDL_Msk); + channel->SCTR |= (uint32_t)passive_level; +} + +/* TX FIFO APIs */ +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data_pointer Start position inside the FIFO buffer. \n + * \b Range: 0 to 63. + * @param size Required size of the transmit FIFO. \n + * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS + * @param limit Threshold of transmit FIFO filling level to be considered for generating events. \n + * \b Range: 0 to \a size -1. + * @return None + * + * \parDescription
+ * Initializes the transmit FIFO. \n\n + * Transmit FIFO is a subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module. + * Each channel can share the FIFO for transmission and reception. \a data_pointer represents the start index in the common FIFO, + * from where transmit data can be put, for the selected USIC channel. \a size represents the size of transmit FIFO as a multiple of + * 2. Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully selected. A FIFO standard transmit buffer + * event is generated when the FIFO filling level falls below the \a limit value. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_EnableEvent(), XMC_USIC_CH_TXFIFO_SetInterruptNodePointer() \n\n\n + */ +void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel, + const uint32_t data_pointer, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param size Required size of the transmit FIFO. \n + * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS + * @param limit Threshold for transmit FIFO filling level to be considered for generating events. \n + * \b Range: 0 to \a size -1. + * @return None + * + * \parDescription
+ * Sets the size and trigger limit for the transmit FIFO. \n\n + * The API is not to be called for initializing the transmit FIFO. The API shall be used for the + * runtime change of transmit FIFO trigger limit. FIFO start position will not be affected on execution. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit() \n\n\n + */ +void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit); + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Events to be enabled. Multiple events can be bitwise OR combined. @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t \n + * @return None + * + * \parDescription
+ * Enables the interrupt events related to transmit FIFO. \n\n + * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t. + * Multiple events can be enabled by providing multiple events in a single call. For providing + * multiple events, combine the events using bitwise OR operation. Events are configured in the TBCTR register.
+ * + * Note: API only enables the events. For interrupt generation, interrupt node must be configured and NVIC node + * must be enabled. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_SetInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->TBCTR |= event; +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Events to be disabled. @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t \n + * @return None + * + * \parDescription
+ * Disables the interrupt events related to transmit FIFO. \n\n + * By disabling the interrupt events, generation of interrupt is stopped. User can poll the event + * flags from the status register using the API XMC_USIC_CH_TXFIFO_GetEvent(). + * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t. For providing + * multiple events, combine the events using bitwise OR operation. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_GetEvent(), XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->TBCTR &= (uint32_t)~event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param interrupt_node Node pointer representing the transmit FIFO events. \n + * \b Range: @ref XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD, + * @ref XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE + * @param service_request The service request to be used for interrupt generation. \n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets an interrupt node for the transmit FIFO events.\n\n + * A node pointer represents one or more interrupt events. Service request represents the interrupt node to be used + * among the 6 interrupt nodes available for USIC module. + * API configures the service request to be used for interrupt generation for the events selected. + * A transmit FIFO event can generate an interrupt only if the interrupt node is configured for the event and + * the interrupt generation is enabled for the event. For example, transmit FIFO standard transmit buffer + * interrupt is generated if the interrupt node for the same is set and interrupt is enabled.
+ * + * Note: NVIC node should be explicitly enabled for the interrupt generation. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n + */ +void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data Data to be transmitted. \n + * \b Range: 16bit unsigned data. minimum= 0, maximum= 65535 + * @return None + * + * \parDescription
+ * Writes data into the transmit FIFO. \n\n + * The data provided is placed in the transmit FIFO. + * The transmit FIFO should be configured before calling this API. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutData(XMC_USIC_CH_t *const channel, const uint16_t data) +{ + channel->IN[0] = data; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data Data to be transmitted. + * @param frame_length Frame length to be configured while transmitting the data. \n + * \b Range: minimum= 0, maximum= 31. e.g: For a frame length of 16, set \a frame_length as 15. + * @return None + * + * \parDescription
+ * Writes data to the transmit FIFO in frame length control mode. \n\n + * When frame length control is enabled for dynamic update of frame length, this API can be used. + * \a frame_length represents the frame length to be updated by the peripheral. + * \a frame_length is used as index for the IN[] register array. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableFrameLengthControl() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_USIC_CH_t *const channel, + const uint16_t data, + const uint32_t frame_length) +{ + channel->IN[frame_length] = data; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data Data to be transmitted. + * @param frame_length Frame length to be configured while transmitting the data. \n + * \b Range: minimum= 0, maximum= 31. e.g: For a frame length of 16, set \a frame_length as 15. + * @return None + * + * \parDescription
+ * Writes data to the transmit FIFO in hardware port control mode. \n\n + * When hardware port control is enabled for dynamic update of frame length, this API can be used. + * \a frame_length represents the frame length to be updated by the peripheral. + * \a frame_length is used as index for the IN[] register array. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableFrameLengthControl() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataHPCMode(XMC_USIC_CH_t *const channel, + const uint16_t data, + const uint32_t frame_length) +{ + channel->IN[frame_length] = data; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Clears the contents of transmit FIFO. \n\n + * Transmit FIFO contents will be cleared and the filling level will be reset to 0. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_GetLevel() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_Flush(XMC_USIC_CH_t *const channel) +{ + channel->TRBSCR = (uint32_t)USIC_CH_TRBSCR_FLUSHTB_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status \a true if transmit FIFO is full + * \a false if transmit FIFO is not full. + * + * \parDescription
+ * Checks if transmit FIFO is full. \n\n + * When the transmit FIFO filling level reaches the configured size, FIFO full flag is set. + * User should not write to the FIFO when the transmit FIFO is full. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_IsEmpty(), XMC_USIC_CH_TXFIFO_Flush() \n\n\n + */ +__STATIC_INLINE bool XMC_USIC_CH_TXFIFO_IsFull(XMC_USIC_CH_t *const channel) +{ + return (bool)(channel->TRBSR & USIC_CH_TRBSR_TFULL_Msk); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status \a true if transmit FIFO is empty + * \a false if transmit FIFO has some data. + * + * \parDescription
+ * Checks if transmit FIFO is empty. \n\n + * When the transmit FIFO is empty, data can be written to FIFO. + * When the last written word to the transmit FIFO is transmitted out of the FIFO, + * FIFO empty flag is set. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData() \n\n\n + */ +__STATIC_INLINE bool XMC_USIC_CH_TXFIFO_IsEmpty(XMC_USIC_CH_t *const channel) +{ + return (bool)(channel->TRBSR & USIC_CH_TRBSR_TEMPTY_Msk); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Transmit FIFO filling level. \n + * \b Range: minimum= 0(FIFO empty), maximum= transmit FIFO size. + * + * \parDescription
+ * Gets the transmit FIFO filling level. \n\n + * For every word written to the FIFO, filling level is updated. The API gives the value + * of this filling level. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetLevel(XMC_USIC_CH_t *const channel) +{ + return ((uint32_t)(channel->TRBSR & USIC_CH_TRBSR_TBFLVL_Msk) >> USIC_CH_TRBSR_TBFLVL_Pos); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status of standard transmit and transmit buffer error events. @ref XMC_USIC_CH_TXFIFO_EVENT_t \n + * + * \parDescription
+ * Gets the transmit FIFO event status. \n\n + * Gives the status of transmit FIFO standard transmit buffer event and transmit buffer error event. + * The status bits are located at their bit positions in the TRBSR register in the returned value. + * User can make use of the @ref XMC_USIC_CH_TXFIFO_EVENT_t enumeration for checking the status of return value. + * The status can be found by using the bitwise AND operation on the returned value with the enumerated value.
+ * + * Note: Event status flags should be cleared by the user explicitly. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_ClearEvent() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetEvent(XMC_USIC_CH_t *const channel) +{ + return (uint32_t)((channel->TRBSR) & (USIC_CH_TRBSR_STBI_Msk | + USIC_CH_TRBSR_TBERI_Msk)); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Transmit FIFO events to be cleared. \n + * \b Range: @ref XMC_USIC_CH_TXFIFO_EVENT_STANDARD, @ref XMC_USIC_CH_TXFIFO_EVENT_ERROR. + * @return None + * + * \parDescription
+ * Clears the transmit FIFO event flags in the status register. \n\n + * USIC channel peripheral does not clear the event flags after they are read. + * This API clears the events provided in the \a mask value. + * XMC_USIC_CH_TXFIFO_EVENT enumeration can be used as input. Multiple events + * can be cleared by providing a mask value obtained by bitwise OR operation of + * multiple event enumerations. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_GetEvent() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_ClearEvent(XMC_USIC_CH_t *const channel, + const uint32_t event) +{ + channel->TRBSCR = event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data_pointer Start position inside the FIFO buffer. \n + * \b Range: 0 to 63. + * @param size Required size of the receive FIFO. \n + * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS + * @param limit Threshold of receive FIFO filling level to be considered for generating events. \n + * \b Range: 0 to \a size -1. + * @return None + * + * \parDescription
+ * Configures the receive FIFO. \n\n + * Receive FIFO is the subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module. + * Each channel can share the FIFO for transmission and reception. \a data_pointer represents the start index in the common FIFO, + * from where received data can be put. \a size represents the size of receive FIFO as a multiple of 2. + * Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully selected. A FIFO standard receive buffer + * event or alternative receive buffer event is generated when the FIFO filling level exceeds the \a limit value. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_EnableEvent(), XMC_USIC_CH_RXFIFO_SetInterruptNodePointer() \n\n\n +*/ +void XMC_USIC_CH_RXFIFO_Configure(XMC_USIC_CH_t *const channel, + const uint32_t data_pointer, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param size Required size of the receive FIFO. \n + * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS + * @param limit Threshold for receive FIFO filling level to be considered for generating events. \n + * \b Range: 0 to \a size -1. + * @return None + * + * \parDescription
+ * Sets the size and trigger limit for the receive FIFO. \n\n + * The API is not to be called for initializing the receive FIFO. The API shall be used for the + * runtime change of receive FIFO trigger limit. FIFO start position will not be affected on execution. + * + * \parRelated APIs:
+ * XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit()\ n\n\n + */ +void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Events to be enabled. Multiple events can be bitwise OR combined. @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_t\n + * @return None + * + * \parDescription
+ * Enables the interrupt events related to transmit FIFO. \n\n + * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_t. + * Multiple events can be enabled by providing multiple events in a single call. For providing + * multiple events, combine the events using bitwise OR operation.
+ * + * Note: API only enables the events. For interrupt generation, interrupt node must be configured and NVIC node + * must be enabled. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_SetInterruptNodePointer() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_RXFIFO_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->RBCTR |= event; +} + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Events to be disabled. \n + * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD, @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR, + * @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE. + * @return None + * + * \parDescription
+ * Disables the selected interrupt events related to receive FIFO. \n\n + * By disabling the interrupt events, generation of interrupt is stopped. User can poll the event + * flags from the status register using the API XMC_USIC_CH_RXFIFO_GetEvent(). + * Event bitmasks can be constructed using the enumeration \a XMC_USIC_CH_RXFIFO_EVENT_CONF. For providing + * multiple events, combine the events using bitwise OR operation. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_GetEvent(), XMC_USIC_CH_RXFIFO_EnableEvent() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_RXFIFO_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->RBCTR &= (uint32_t)~event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param interrupt_node Node pointer representing the receive FIFO events. \n + * \b Range: @ref XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD, + * @ref XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE + * @param service_request The service request to be used for interrupt generation.\n + * \b Range: 0 to 5. + * @return None + * + * \parDescription
+ * Sets an interrupt node for the receive FIFO events. \n\n + * A node pointer represents one or more interrupt events. Service request represents the interrupt node to be used + * among the 6 interrupt nodes available for USIC module. + * API configures the service request to be used for interrupt generation for the events selected. + * A receive FIFO event can generate an interrupt only if the interrupt node is configured for the event and + * the interrupt generation is enabled for the event. For example, transmit FIFO standard transmit buffer + * interrupt is generated if the interrupt node for the same is set and interrupt is enabled.
+ * + * Note: NVIC node should be explicitly enabled for the interrupt generation. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_EnableEvent() \n\n\n + */ +void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Value read from the receive FIFO. \n + * \b Range: 16bit data. Length of data depends on the word length configuration. + * + * \parDescription
+ * Gets data from the receive FIFO. \n\n + * Receive FIFO should be read only if data is availble in the FIFO. This can be checked using + * the API XMC_USIC_CH_RXFIFO_IsEmpty(). Receive FIFO error flag will be set if an attempt is made + * to read from an empty receive FIFO. To read all the received data, user should keep reading data + * until receive FIFO is empty. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_ClearEvent() \n\n\n + */ +__STATIC_INLINE uint16_t XMC_USIC_CH_RXFIFO_GetData(XMC_USIC_CH_t *const channel) +{ + return (uint16_t)(channel->OUTR); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Clears the contents of receive FIFO. \n\n + * Receive FIFO contents will be cleared and the filling level will be reset to 0. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_GetLevel() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_RXFIFO_Flush(XMC_USIC_CH_t *const channel) +{ + channel->TRBSCR = (uint32_t)USIC_CH_TRBSCR_FLUSHRB_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status \a true if receive FIFO is full + * \a false if receive FIFO is not full. + * + * \parDescription
+ * Checks if receive FIFO is full. \n\n + * When the receive FIFO filling level reaches the configured size, FIFO full flag is set. + * Any data received when the receive FIFO is full, is lost. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_IsEmpty(), XMC_USIC_CH_RXFIFO_Flush() \n\n\n + */ +__STATIC_INLINE bool XMC_USIC_CH_RXFIFO_IsFull(XMC_USIC_CH_t *const channel) +{ + return (bool)(channel->TRBSR & USIC_CH_TRBSR_RFULL_Msk); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status \a true if receive FIFO is empty, + * \a false if receive FIFO has some data. + * + * \parDescription
+ * Checks if receive FIFO is empty. \n\n + * When the receive FIFO is empty, received data will be put in receive FIFO. + * When the last received word in the FIFO is read, FIFO empty flag is set. Any attempt + * to read from an empty receive FIFO will set the receive FIFO error flag. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData() \n\n\n + */ +__STATIC_INLINE bool XMC_USIC_CH_RXFIFO_IsEmpty(XMC_USIC_CH_t *const channel) +{ + return (bool)(channel->TRBSR & USIC_CH_TRBSR_REMPTY_Msk); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return uint32_t Receive FIFO filling level. \n + * \b Range: minimum= 0(FIFO empty), maximum= receive FIFO size. + * + * \parDescription
+ * Gets the receive FIFO filling level. \n\n + * For every word received, the filling level is incremented. The API gives the value + * of this filling level. The filling level is decremented when the data is read out of the + * receive FIFO. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData() \n\n\n + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetLevel(XMC_USIC_CH_t *const channel) +{ + return ((uint32_t)(channel->TRBSR & USIC_CH_TRBSR_RBFLVL_Msk) >> USIC_CH_TRBSR_RBFLVL_Pos); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return Status of standard receive buffer, alternative receive buffer and receive buffer error events. \n + * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_STANDARD, @ref XMC_USIC_CH_RXFIFO_EVENT_ERROR, + * @ref XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE. + * + * \parDescription
+ * Gets the receive FIFO events' status. \n\n + * Gives the status of receive FIFO standard receive buffer event, alternative receive buffer event and receive buffer error event. + * The status bits are located at their bitpositions in the TRBSR register in the returned value. + * User can make use of the XMC_USIC_CH_RXFIFO_EVENT enumeration for checking the status of return value. + * The status can be found by using the bitwise AND operation on the returned value with the enumerated value.
+ * + * Note: Event status flags should be cleared by the user explicitly. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_ClearEvent()\n\n\n + */ +__STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetEvent(XMC_USIC_CH_t *const channel) +{ + return (uint32_t)((channel->TRBSR) & (USIC_CH_TRBSR_SRBI_Msk | + USIC_CH_TRBSR_RBERI_Msk | + USIC_CH_TRBSR_ARBI_Msk)); +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param event Receive FIFO events to be cleared. \n + * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_STANDARD, @ref XMC_USIC_CH_RXFIFO_EVENT_ERROR, + * @ref XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE. + * @return None + * + * \parDescription
+ * Clears the receive FIFO event flags in the status register. \n\n + * USIC channel peripheral does not clear the event flags after they are read. + * This API clears the events provided in the \a mask value. + * XMC_USIC_CH_RXFIFO_EVENT enumeration can be used as input. Multiple events + * can be cleared by providing a mask value obtained by bitwise OR operation of + * multiple event enumerations. + * + * \parRelated APIs:
+ * XMC_USIC_CH_RXFIFO_GetEvent() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_RXFIFO_ClearEvent(XMC_USIC_CH_t *const channel, + const uint32_t event) +{ + channel->TRBSCR = event; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Enables time measurement using the capture mode timer. \n\n + * Time measurement is enabled by setting the timer enable flag in BRG register. + * + * \parRelated APIs:
+ * XMC_USIC_CH_DisableTimeMeasurement() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableTimeMeasurement(XMC_USIC_CH_t *const channel) +{ + channel->BRG |= (uint32_t)USIC_CH_BRG_TMEN_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
+ * Disables time measurement using the capture mode timer. \n\n + * Time measurement is disabled by clearing the timer enable flag in BRG register. + * + * \parRelated APIs:
+ * XMC_USIC_CH_EnableTimeMeasurement() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableTimeMeasurement(XMC_USIC_CH_t *const channel) +{ + channel->BRG &= (uint32_t)~USIC_CH_BRG_TMEN_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param passive_level Passive level for the master clock output. \n + * \b Range: @ref XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0, @ref XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1. + * @return None + * + * \parDescription
+ * Sets the idle mode pin level for the master clock output. \n + */ +__STATIC_INLINE void XMC_USIC_CH_SetMclkOutputPassiveLevel(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t passive_level) +{ + channel->BRG = (uint32_t)(channel->BRG & (~USIC_CH_BRG_MCLKCFG_Msk)) | (uint32_t)passive_level; +} +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param passive_level Passive level for the clock output. \n + * \b Range: @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED, + * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED, + * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED, + * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED, + * @param clock_output Shift clock source selection. \n + * \b Range: Use @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK, + * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 + * @return None + * + * \parDescription
+ * Sets the idle mode shift clock output level and selects the shift clock source. \n\n + * Shift clock idle mode output level can be set to logic high or low. Shift clock output can be configured to have a + * delay of half shift clock period. Both the configurations are available as enumeration values defined with type + * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t. + * This value should be configured based on the slave device requirement. + * Shift clock source can be selected between internal clock(master) and external input(slave). + * + */ +__STATIC_INLINE void XMC_USIC_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level, + const XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) +{ + channel->BRG = (uint32_t)(channel->BRG & (~(USIC_CH_BRG_SCLKCFG_Msk | + USIC_CH_BRG_SCLKOSEL_Msk))) | + (uint32_t)passive_level | + (uint32_t)clock_output; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param mode USIC channel operation mode. \n + * \b Range: @ref XMC_USIC_CH_OPERATING_MODE_IDLE, @ref XMC_USIC_CH_OPERATING_MODE_SPI, + * @ref XMC_USIC_CH_OPERATING_MODE_UART, @ref XMC_USIC_CH_OPERATING_MODE_I2S, + * @ref XMC_USIC_CH_OPERATING_MODE_I2C. + * @return None + * + * \parDescription
+ * Sets the USIC channel operation mode.\n\n + * A USIC channel can support multiple serial communication protocols like UART, SPI, I2C and I2S. + * The API sets the input operation mode to the USIC channel. + * + * \parRelated APIs:
+ * XMC_USIC_Enable(), XMC_USIC_CH_Enable() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_SetMode(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_OPERATING_MODE_t mode) +{ + channel->CCR = (uint32_t)(channel->CCR & (~(USIC_CH_CCR_MODE_Msk))) | (uint32_t)mode; +} +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_vadc.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_vadc.h new file mode 100644 index 00000000..dc963068 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_vadc.h @@ -0,0 +1,4962 @@ +/** + * @file xmc_vadc.h + * @date 2017-02-06 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-15: + * - Initial
+ * + * 2015-02-20: + * - Revised for XMC1201 device.
+ * + * 2015-04-27: + * - Added new APIs for SHS.
+ * - Added New APIs for trigger edge selection.
+ * - Added new APIs for Queue flush entries, boundary selection, Boundary node pointer.
+ * - Revised GatingMode APIs and EMUX Control Init API.
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * 2015-06-25: + * - BFL configuration in channel initialization fixed. + * + * 2015-07-28: + * - CLOCK_GATING_SUPPORTED and PERIPHERAL_RESET_SUPPORTED macros used + * - Clubbed the macro definitions for XMC13 XMC12 and XMC14 + * - Clubbed the macro definitions for XMC44 XMC47 and XMC48 + * - New APIs Created. + * - XMC_VADC_GLOBAL_SetIndividualBoundary + * - XMC_VADC_GROUP_SetIndividualBoundary + * - XMC_VADC_GROUP_GetAlias + * - XMC_VADC_GROUP_GetInputClass + * - XMC_VADC_GROUP_ChannelSetIclass + * - XMC_VADC_GROUP_ChannelGetResultAlignment + * - XMC_VADC_GROUP_ChannelGetInputClass + * - XMC_VADC_GROUP_SetResultSubtractionValue + * + * 2015-12-01: + * - Added: + * - XMC4300 device supported + * + * - Fixed: + * - XMC_VADC_GLOBAL_TriggerEvent API updated. OR operation removed. + * - XMC_VADC_GLOBAL_ClearEvent API updated. Multiple events triggering on clearing the event is fixed. + * - Wrong MACRO name defined in xmc_vadc_map.h file corrected for XMC4200/4100 devices. + * XMC_VADC_G3_SAMPLE renamed to XMC_VADC_G1_SAMPLE + * + * 2015-12-01: + * - New APIs Created. + * - XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled + * - XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled + * - Fixed the analog calibration voltage for XMC1100 to external reference upper supply range. + * - Fixed the XMC_VADC_GLOBAL_StartupCalibration() for XMC1100. + * + * 2016-03-09: + * - Optimization of write only registers + * + * 2016-03-18: + * - Fixed XMC_VADC_GLOBAL_SHS_IsConverterReady(): API checks the STEPCFG register for the ready bit instead of + * SHSCFG SFR. + * + * 2016-06-17: + * - New macros added XMC_VADC_SHS_FULL_SET_REG, XMC_VADC_RESULT_PRIORITY_AVAILABLE + * - New Enum added XMC_VADC_SHS_GAIN_LEVEL_t and XMC_VADC_SYNCTR_EVAL_t + * - New APIs added are: + * - XMC_VADC_GROUP_SetSyncSlaveReadySignal + * - XMC_VADC_GROUP_ChannelGetAssertedEvents + * - XMC_VADC_GROUP_GetAssertedResultEvents + * - XMC_VADC_GROUP_SetResultRegPriority + * - XMC_VADC_GROUP_SetSyncReadySignal + * - XMC_VADC_GROUP_GetSyncReadySignal + * - XMC_VADC_GROUP_GetResultRegPriority + * + * 2017-02-06: + * - Added new functions to remove channels from background request source, XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence() and XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels() + * + * @endcond + * + */ + +#ifndef XMC_VADC_H +#define XMC_VADC_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include +#include +#include + +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup VADC + * @brief Versatile Analog to Digital Converter (VADC) driver for XMC microcontroller family. + * + * The XMC microcontroller provides a series of analog input channels connected to a cluster of Analog/Digital + * Converters using the Successive Approximation Register (SAR) principle to convert analog input values (voltages) + * to discrete digital values. + * \if XMC1 + * The XMC1x is based on Sample & Hold converters, where a cluster contains 2 Sample&Hold units which share a common + * converter. + * \endif + * + * Each converter of the ADC cluster can operate independent of the others, controlled by a dedicated set of + * registers and triggered by a dedicated group request source. The results of each channel can be stored in a + * dedicated channel-specific result register or in a group-specific result register.
+ * + * The Versatile Analog to Digital Converter module (VADC) of the XMC comprises a set of converter blocks that + * can be operated either independently or via a common request source that emulates a background converter. + * Each converter block is equipped with a dedicated input multiplexer and dedicated request sources, + * which together build separate groups. + * + * \if XMC4 + * @image html "vadc_overview_xmc4x.png" + * \else + * @image html "vadc_overview_xmc1x.png" + * \endif + * + * The VADC LLD is split into GLOBAL and GROUP related APIs.
+ * GLOBAL:
+ *
    + *
  • Global APIs act on the entire ADC module. Configures global configuration registers
    • + *
  • Allows configuration of the background request source of the VADC.
    • + *
  • The clock related configurations for the VADC module are configured in the Global APIs/
    • + *
  • The Global API names are prefixed by the \b XMC_VADC_GLOBAL_ and they accept ::XMC_VADC_GLOBAL_t as + * one of its arguments.
    • + *
  • Configures the background request source of the VADC. The APIs which act on the background related registers + * are prefixed by \b XMC_VADC_GLOBAL_Background
    • + *
  • Configures the sample and hold unit of the VADC. The APIs which act on the SHS related registers + * are prefixed by \b XMC_VADC_GLOBAL_SHS_
    • + *

+ * + * GROUP:
+ *
    + *
  • Group APIs act on a VADC group. Configures the group configuration registers
    • + *
  • Configures the queue request source of the VADC. The APIs which act on the queue related registers + * are prefixed by \b XMC_VADC_GROUP_Queue
    • + *
  • Configures the scan request source of the VADC. The APIs which act on the scan related registers + * are prefixed by \b XMC_VADC_GROUP_Scan
    • + *
  • Configuration of the channels of each group are done by the API which have a prefix as + * \b XMC_VADC_GROUP_Channel.
    • + *
  • The Group API names are prefixed by the \b XMC_VADC_GROUP_ and they accept ::XMC_VADC_GROUP_t as + * one of its arguments.
    • + *

+ * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#if ((UC_SERIES == XMC42)||(UC_SERIES == XMC41) || (UC_SERIES == XMC43)) +#define XMC_VADC_GROUP_AVAILABLE (1U) /* Defines the availability of group resource in a device*/ +#define XMC_VADC_GSCAN_AVAILABLE (1U) /* Defines the availability of scan request resource in a device*/ +#define XMC_VADC_QUEUE_AVAILABLE (1U) /* Defines the availability of queue request resource in a device*/ +#define XMC_VADC_EMUX_AVAILABLE (1U) /* Defines the availability of external multiplexer support in a + device*/ +#define XMC_VADC_BOUNDARY_AVAILABLE (1U) /* Defines the availability of boundary check support in a device*/ +#define XMC_VADC_MULTIPLE_SLAVEGROUPS (1U) /* Defines the availability of synchronous request source in device*/ +#define XMC_VADC_MAXIMUM_NUM_GROUPS (2U) /* Defines the maximum number of groups available in a device*/ +#define XMC_VADC_BOUNDARY_FLAG_SELECT (1U) /* Defines the availability of boundary flags in a device*/ +#define XMC_VADC_EMUX_CH_SEL_STYLE (1U) /* Defines the external multiplexer channel selection mode of + operation for a particular device*/ +#define XMC_VADC_SHS_AVAILABLE (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_SHS_FULL_SET_REG (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_GROUP_SRCREG_AVAILABLE (1U) /* Define the availability of a source specific result register */ +#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */ +#endif + +#if (UC_SERIES == XMC44 || UC_SERIES == XMC47 || UC_SERIES == XMC48) +#define XMC_VADC_GROUP_AVAILABLE (1U) /* Defines the availability of group resource in a device*/ +#define XMC_VADC_GSCAN_AVAILABLE (1U) /* Defines the availability of scan request resource in a device*/ +#define XMC_VADC_QUEUE_AVAILABLE (1U) /* Defines the availability of queue request resource in a device*/ +#define XMC_VADC_EMUX_AVAILABLE (1U) /* Defines the availability of external multiplexer support in a + device*/ +#define XMC_VADC_BOUNDARY_AVAILABLE (1U) /* Defines the availability of boundary check support in a device*/ +#define XMC_VADC_MULTIPLE_SLAVEGROUPS (1U) /* Defines the availability of synchronous request source in device*/ +#define XMC_VADC_MAXIMUM_NUM_GROUPS (4U) /* Defines the maximum number of groups available in a device*/ +#define XMC_VADC_BOUNDARY_FLAG_SELECT (1U) /* Defines the availability of boundary flags in a device*/ +#define XMC_VADC_EMUX_CH_SEL_STYLE (1U) /* Defines the external multiplexer channel selection mode of + operation for a particular device*/ +#define XMC_VADC_SHS_AVAILABLE (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_SHS_FULL_SET_REG (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_GROUP_SRCREG_AVAILABLE (1U) /* Define the availability of a source specific result register */ +#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */ +#endif + +#if (UC_SERIES == XMC45) +#define XMC_VADC_GROUP_AVAILABLE (1U) /* Defines the availability of group resource in a device*/ +#define XMC_VADC_GSCAN_AVAILABLE (1U) /* Defines the availability of scan request resource in a device*/ +#define XMC_VADC_QUEUE_AVAILABLE (1U) /* Defines the availability of queue request resource in a device*/ +#define XMC_VADC_EMUX_AVAILABLE (1U) /* Defines the availability of external multiplexer support in a + device*/ +#define XMC_VADC_BOUNDARY_AVAILABLE (1U) /* Defines the availability of boundary check support in a device*/ +#define XMC_VADC_MULTIPLE_SLAVEGROUPS (1U) /* Defines the availability of synchronous request source in device*/ +#define XMC_VADC_MAXIMUM_NUM_GROUPS (4U) /* Defines the maximum number of groups available in a device*/ +#define XMC_VADC_BOUNDARY_FLAG_SELECT (0U) /* Defines the availability of boundary flags in a device*/ +#define XMC_VADC_EMUX_CH_SEL_STYLE (0U) /* Defines the external multiplexer channel selection mode of + operation for a particular device*/ +#define XMC_VADC_SHS_AVAILABLE (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_SHS_FULL_SET_REG (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_GROUP_SRCREG_AVAILABLE (0U) /* Define the availability of a source specific result register */ +#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */ +#endif + +#if (UC_SERIES == XMC14 || UC_SERIES == XMC13 || UC_SERIES == XMC12) +#define XMC_VADC_GROUP_AVAILABLE (1U) /* Defines the availability of group resource in a device*/ +#define XMC_VADC_GSCAN_AVAILABLE (1U) /* Defines the availability of scan request resource in a device*/ +#define XMC_VADC_QUEUE_AVAILABLE (1U) /* Defines the availability of queue request resource in a device*/ +#define XMC_VADC_EMUX_AVAILABLE (1U) /* Defines the availability of external multiplexer support in a + device*/ +#define XMC_VADC_BOUNDARY_AVAILABLE (1U) /* Defines the availability of boundary check support in a device*/ +#define XMC_VADC_MULTIPLE_SLAVEGROUPS (1U) /* Defines the availability of synchronous request source in device*/ +#define XMC_VADC_MAXIMUM_NUM_GROUPS (2U) /* Defines the maximum number of groups available in a device*/ +#define XMC_VADC_BOUNDARY_FLAG_SELECT (1U) /* Defines the availability of boundary flags in a device*/ +#define XMC_VADC_EMUX_CH_SEL_STYLE (1U) /* Defines the external multiplexer channel selection mode of + operation for a particular device*/ +#define XMC_VADC_SHS_AVAILABLE (1U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_SHS_FULL_SET_REG (1U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_GROUP_SRCREG_AVAILABLE (1U) /* Define the availability of a source specific result register */ +#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (1U) /* Define the availability of a priority for result register */ +#endif + +#if (UC_SERIES == XMC11) +#define XMC_VADC_GROUP_AVAILABLE (0U) /* Defines the availability of group resource in a device*/ +#define XMC_VADC_GSCAN_AVAILABLE (0U) /* Defines the availability of scan request resource in a device*/ +#define XMC_VADC_QUEUE_AVAILABLE (0U) /* Defines the availability of queue request resource in a device*/ +#define XMC_VADC_EMUX_AVAILABLE (0U) /* Defines the availability of external multiplexer support in a + device*/ +#define XMC_VADC_BOUNDARY_AVAILABLE (0U) /* Defines the availability of boundary check support in a device*/ +#define XMC_VADC_MULTIPLE_SLAVEGROUPS (0U) /* Defines the availability of synchronous request source in device*/ +#define XMC_VADC_MAXIMUM_NUM_GROUPS (2U) /* Defines the maximum number of groups available in a device*/ +#define XMC_VADC_BOUNDARY_FLAG_SELECT (0U) /* Defines the availability of boundary flags in a device*/ +#define XMC_VADC_SHS_START_UP_CAL_ACTIVE (3U) /* Defines the need for SHS startup calibration activation for + XMC1100 devices */ +#define XMC_VADC_CONV_ENABLE_FOR_XMC11 (*(uint32_t*) 0x40010500UL) /* Defines the additional errata setting for + XMC1100 device for effective working*/ +#define XMC_VADC_EMUX_CH_SEL_STYLE (0U) /* Defines the external multiplexer channel selection mode of + operation for a particular device*/ +#define XMC_VADC_SHS_AVAILABLE (1U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_SHS_FULL_SET_REG (0U) /* Defines the availability of sample and hold module*/ +#define XMC_VADC_GROUP_SRCREG_AVAILABLE (0U) /* Define the availability of a source specific result register */ +#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */ +#endif + +#define XMC_VADC_NUM_PORTS (16U) /* Defines the number of hardware ports that can be configured + as triggers and gating signals */ + +#define XMC_VADC_NUM_RESULT_REGISTERS (16U) /* Defines the number of result holding registers per ADC group */ + +#define XMC_VADC_NUM_CHANNELS_PER_GROUP (8U) /**< Defines the number of ADC channels per group */ + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ +typedef uint16_t XMC_VADC_RESULT_SIZE_t; /**< Type defined the converted result size to unsigned 16 bit integer */ +typedef VADC_GLOBAL_TypeDef XMC_VADC_GLOBAL_t; /**< Type defined the device header file vadc global register structure + type to VADC type*/ + +#if(XMC_VADC_GROUP_AVAILABLE == 1U) +typedef VADC_G_TypeDef XMC_VADC_GROUP_t; /**< Type defined the device header file vadc group register structure + type to VADC Group type*/ +#endif + +#if(XMC_VADC_SHS_AVAILABLE == 1U) +typedef SHS_Type XMC_VADC_GLOBAL_SHS_t; /**< Type defined the sample and hold register structure*/ +#endif +/** + * Defines the return status after execution of VADC specific API's. Use @ref XMC_VADC_STATUS_t for this enumeration. + */ +typedef enum XMC_VADC_STATUS +{ + XMC_VADC_STATUS_SUCCESS = 0, /**< Returned when the API has been able to fulfill the callers request */ + XMC_VADC_STATUS_ERROR /**< Returned when the API cannot fulfill the request */ +} XMC_VADC_STATUS_t; + +/** + * Defines the various service requests lines. Each group can raise up to 4 service requests independently. While + * all groups together have the possibility of raising 4 module wide service requests. Use @ref XMC_VADC_SR_t for this + * enumeration. + */ +typedef enum XMC_VADC_SR +{ + XMC_VADC_SR_GROUP_SR0 = 0, /**< Group specific Service Request-0 */ + XMC_VADC_SR_GROUP_SR1, /**< Group specific Service Request-1 */ + XMC_VADC_SR_GROUP_SR2, /**< Group specific Service Request-2 */ + XMC_VADC_SR_GROUP_SR3, /**< Group specific Service Request-3 */ + XMC_VADC_SR_SHARED_SR0, /**< Module Wide Common Service Request-0 */ + XMC_VADC_SR_SHARED_SR1, /**< Module Wide Common Service Request-1 */ + XMC_VADC_SR_SHARED_SR2, /**< Module Wide Common Service Request-2 */ + XMC_VADC_SR_SHARED_SR3 /**< Module Wide Common Service Request-3 */ +} XMC_VADC_SR_t; + +/** + * Defines the mode of operation of a channel, when an ongoing conversion gets interrupted in between. + * Use @ref XMC_VADC_STARTMODE_t for this enumeration. + */ +typedef enum XMC_VADC_STARTMODE +{ + XMC_VADC_STARTMODE_WFS = 0, /**< An ongoing conversion completes without interruption */ + XMC_VADC_STARTMODE_CIR, /**< An ongoing conversion can be interrupted and resumed later*/ + XMC_VADC_STARTMODE_CNR /**< An ongoing conversion can be interrupted and never resumed */ +} XMC_VADC_STARTMODE_t; + +/** + * Defines the edge sensitivity of the trigger signal which can assert a conversion. + * Use @ref XMC_VADC_TRIGGER_EDGE_t for this enumeration. + */ +typedef enum XMC_VADC_TRIGGER_EDGE +{ + XMC_VADC_TRIGGER_EDGE_NONE = 0, /**< No external trigger. Conversion request can be asserted by software */ + XMC_VADC_TRIGGER_EDGE_FALLING, /**< The falling edge of the external trigger can assert conversion request */ + XMC_VADC_TRIGGER_EDGE_RISING, /**< The rising edge of the external trigger can assert conversion request */ + XMC_VADC_TRIGGER_EDGE_ANY /**< Both the edges can assert conversion request */ +} XMC_VADC_TRIGGER_EDGE_t; + +/** + * Defines the external trigger input selection possibilities, to assert a conversion. Refer the VADC interconnects + * section of the reference manual for details of peripherals which can be used. Also refer xmc_vadc_map.h file for + * detailed definitions of the peripherals which can take the control of these enumeration items. + * Use @ref XMC_VADC_TRIGGER_INPUT_SELECT_t for this enumeration. + */ +typedef enum XMC_VADC_TRIGGER_INPUT_SELECT +{ + XMC_VADC_REQ_TR_A = 0, /**< Trigger select signal A */ + XMC_VADC_REQ_TR_B, /**< Trigger select signal B */ + XMC_VADC_REQ_TR_C, /**< Trigger select signal C */ + XMC_VADC_REQ_TR_D, /**< Trigger select signal D */ + XMC_VADC_REQ_TR_E, /**< Trigger select signal E */ + XMC_VADC_REQ_TR_F, /**< Trigger select signal F */ + XMC_VADC_REQ_TR_G, /**< Trigger select signal G */ + XMC_VADC_REQ_TR_H, /**< Trigger select signal H */ + XMC_VADC_REQ_TR_I, /**< Trigger select signal I */ + XMC_VADC_REQ_TR_J, /**< Trigger select signal J */ + XMC_VADC_REQ_TR_K, /**< Trigger select signal K */ + XMC_VADC_REQ_TR_L, /**< Trigger select signal L */ + XMC_VADC_REQ_TR_M, /**< Trigger select signal M */ + XMC_VADC_REQ_TR_N, /**< Trigger select signal N */ + XMC_VADC_REQ_TR_O, /**< Trigger select signal O */ + XMC_VADC_REQ_TR_P /**< Trigger select signal P */ + +} XMC_VADC_TRIGGER_INPUT_SELECT_t; + +/** + * Defines the external gating input selection possibilities, to gate the conversion requests. Refer the VADC + * interconnects section of the reference manual for details of peripherals which can be used. Also refer + * xmc_vadc_map.h file for detailed definitions of the peripherals which can take the control of these enumeration + * items. Use @ref XMC_VADC_GATE_INPUT_SELECT_t for this enumeration. + */ +typedef enum XMC_VADC_GATE_INPUT_SELECT +{ + XMC_VADC_REQ_GT_A = 0, /**< Gating select signal A */ + XMC_VADC_REQ_GT_B, /**< Gating select signal B */ + XMC_VADC_REQ_GT_C, /**< Gating select signal C */ + XMC_VADC_REQ_GT_D, /**< Gating select signal D */ + XMC_VADC_REQ_GT_E, /**< Gating select signal E */ + XMC_VADC_REQ_GT_F, /**< Gating select signal F */ + XMC_VADC_REQ_GT_G, /**< Gating select signal G */ + XMC_VADC_REQ_GT_H, /**< Gating select signal H */ + XMC_VADC_REQ_GT_I, /**< Gating select signal I */ + XMC_VADC_REQ_GT_J, /**< Gating select signal J */ + XMC_VADC_REQ_GT_K, /**< Gating select signal K */ + XMC_VADC_REQ_GT_L, /**< Gating select signal L */ + XMC_VADC_REQ_GT_M, /**< Gating select signal M */ + XMC_VADC_REQ_GT_N, /**< Gating select signal N */ + XMC_VADC_REQ_GT_O, /**< Gating select signal O */ + XMC_VADC_REQ_GT_P /**< Gating select signal P */ + +} XMC_VADC_GATE_INPUT_SELECT_t; + +/** + * Defines the condition for gating the conversion requests. It can be used to set the ENGT field + * of ASMR/BSMR/QMR register respectively for auto_scan/background_scan/queue request sources. + * Use @ref XMC_VADC_GATEMODE_t for this enumeration. + */ +typedef enum XMC_VADC_GATEMODE +{ + XMC_VADC_GATEMODE_BLOCK = 0, /**< External triggers are permanently blocked */ + XMC_VADC_GATEMODE_IGNORE, /**< External triggers are unconditionally passed */ + XMC_VADC_GATEMODE_ACTIVEHIGH, /**< External trigger is passed only if the gate signal is high */ + XMC_VADC_GATEMODE_ACTIVELOW /**< External trigger is passed only if the gate signal is low */ +} XMC_VADC_GATEMODE_t; + +/** + * Defines the conversion result handling mode. Use @ref XMC_VADC_DMM_t for this enumeration. + */ +typedef enum XMC_VADC_DMM +{ + XMC_VADC_DMM_REDUCTION_MODE = 0, /**< Standard Data reduction mode*/ + XMC_VADC_DMM_FILTERING_MODE, /**< Provide option to select Finite Impulse Response Filter (FIR) or + Infinite Impulse Response Filter (IIR)*/ + XMC_VADC_DMM_DIFFERENCE_MODE, /**< Difference mode is selected*/ +} XMC_VADC_DMM_t; + +/** + * Defines the conversion mode. It defines the resolution of conversion. Use XMC_VADC_CONVMODE_t for this enumeration. + */ +typedef enum XMC_VADC_CONVMODE +{ + XMC_VADC_CONVMODE_12BIT = 0, /**< Results of conversion are 12bits wide */ + XMC_VADC_CONVMODE_10BIT = 1, /**< Results of conversion are 10bits wide */ + XMC_VADC_CONVMODE_8BIT = 2, /**< Results of conversion are 8bits wide */ + XMC_VADC_CONVMODE_FASTCOMPARE = 5 /**< Input signal compared with a preset range */ +} XMC_VADC_CONVMODE_t; + +/** + * Defines the output of a fast compare mode. Use @ref XMC_VADC_FAST_COMPARE_t for + * this enumeration. + */ +typedef enum XMC_VADC_FAST_COMPARE +{ + XMC_VADC_FAST_COMPARE_LOW = 0, /**< Input lower than than programmed reference */ + XMC_VADC_FAST_COMPARE_HIGH , /**< Input higher than than programmed reference */ + XMC_VADC_FAST_COMPARE_UNKNOWN /**< Unknown, Conversion probably still ongoing */ +} XMC_VADC_FAST_COMPARE_t; + +/** + * Defines the type of scan request source to be used. It can choose between auto scan and background scan request + * source methods. Use @ref XMC_VADC_SCAN_TYPE_t for this enumeration. + */ +typedef enum XMC_VADC_SCAN_TYPE +{ + XMC_VADC_SCAN_TYPE_GROUPSCAN = 0, /**< Auto scan mode of operation selected. Also called as Group scan*/ + XMC_VADC_SCAN_TYPE_BACKGROUND /**< Background scan mode of operation selected. Also called as Global scan*/ +} XMC_VADC_SCAN_TYPE_t; + +/** + * Defines the behavior of load event for the scan request source. Use @ref XMC_VADC_SCAN_LOAD_t for this enumeration. + */ +typedef enum XMC_VADC_SCAN_LOAD +{ + XMC_VADC_SCAN_LOAD_OVERWRITE = 0, /**< The old set of channels is discarded in favor of the new set + awaiting conversion */ + XMC_VADC_SCAN_LOAD_COMBINE /**< The new set of channels are combined with the pending channels from + previous set */ +} XMC_VADC_SCAN_LOAD_t; + +/** + * Defines the conversion classes that can be selected for each channel. The enumeration members holds the group or + * global classes. The conversion classes decides the properties of conversion, like resolution, sampling time etc + * Use @ref XMC_VADC_CHANNEL_CONV_t for this enumeration. + */ + +typedef enum XMC_VADC_CHANNEL_CONV +{ + XMC_VADC_CHANNEL_CONV_GROUP_CLASS0 = 0, /**< Conversion property set-0 specific to the group */ + XMC_VADC_CHANNEL_CONV_GROUP_CLASS1, /**< Conversion property set-1 specific to the group */ + XMC_VADC_CHANNEL_CONV_GLOBAL_CLASS0, /**< Conversion property set-0, Module wide */ + XMC_VADC_CHANNEL_CONV_GLOBAL_CLASS1 /**< Conversion property set-1, Module wide */ +} XMC_VADC_CHANNEL_CONV_t; + +/** + * Defines the references to boundary values used for limit checking feature. Each of these can be assigned as + * either an upper bound or a lower bound. Use @ref XMC_VADC_CHANNEL_BOUNDARY_t for this enumeration. + */ + +typedef enum XMC_VADC_CHANNEL_BOUNDARY +{ + XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0 = 0, /**< Group specific Boundary-0 value */ + XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND1, /**< Group specific Boundary-1 value */ + XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND0, /**< Module wide Boundary-0 value */ + XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND1 /**< Module wide Boundary-1 value */ +} XMC_VADC_CHANNEL_BOUNDARY_t; + +/** + * Defines the voltage which the capacitor is charged to. Used in Broken wire detection feature. Use + * @ref XMC_VADC_CHANNEL_BWDCH_t for this enumeration. + */ +typedef enum XMC_VADC_CHANNEL_BWDCH +{ + XMC_VADC_CHANNEL_BWDCH_VAGND = 0, /**< Capacitor pre-charged to ground*/ + XMC_VADC_CHANNEL_BWDCH_VAREF /**< Capacitor pre-charged to reference voltage*/ +} XMC_VADC_CHANNEL_BWDCH_t; + +/** + * Defines the criteria for event generation by the channel. Use @ref XMC_VADC_CHANNEL_EVGEN_t for this enumeration. + */ +typedef enum XMC_VADC_CHANNEL_EVGEN +{ + XMC_VADC_CHANNEL_EVGEN_NEVER = 0, /**< No event generated */ + XMC_VADC_CHANNEL_EVGEN_INBOUND = 1U, /**< Event generated when the result is within the normal range */ + XMC_VADC_CHANNEL_EVGEN_COMPHIGH = 1U, /**< Event generated when the result of fast compare operation is high */ + XMC_VADC_CHANNEL_EVGEN_OUTBOUND = 2U, /**< Event generated when the result is outside the normal range */ + XMC_VADC_CHANNEL_EVGEN_COMPLOW = 2U, /**< Event generated when the result result of fast compare operation is low */ + XMC_VADC_CHANNEL_EVGEN_ALWAYS = 3U /**< Event generated always after conversion - unconditionally */ +} XMC_VADC_CHANNEL_EVGEN_t; + +/** + * Defines the reference voltage selection for conversion. Use @ref XMC_VADC_CHANNEL_REF_t for this enumeration. + */ +typedef enum XMC_VADC_CHANNEL_REF +{ + XMC_VADC_CHANNEL_REF_INTREF = 0, /**< Internal VARef */ + XMC_VADC_CHANNEL_REF_ALT_CH0 /**< External voltage available on Channel-0 of the perticular group */ +} XMC_VADC_CHANNEL_REF_t; + +/** + * Defines the criteria for boundary flag assertion. Use @ref XMC_VADC_CHANNEL_BOUNDARY_CONDITION_t for this + * enumeration. + */ +typedef enum XMC_VADC_CHANNEL_BOUNDARY_CONDITION +{ + XMC_VADC_CHANNEL_BOUNDARY_CONDITION_ABOVE_BAND = 0, /**< Set Boundary condition criteria to assert above the band */ + XMC_VADC_CHANNEL_BOUNDARY_CONDITION_BELOW_BAND /**< Set Boundary condition criteria to assert below the band */ +} XMC_VADC_CHANNEL_BOUNDARY_CONDITION_t; + +/** + * Defines the event which can lead to a global service request assertion. Use @ref XMC_VADC_GLOBAL_EVENT_t for this + * enumeration. + */ +typedef enum XMC_VADC_GLOBAL_EVENT +{ + XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE = VADC_GLOBEFLAG_SEVGLB_Msk, /**< Background scan request source event */ + XMC_VADC_GLOBAL_EVENT_RESULT = VADC_GLOBEFLAG_REVGLB_Msk /**< Global result event */ +} XMC_VADC_GLOBAL_EVENT_t; + +/** + * Defines the power modes of a VADC Group. Use @ref XMC_VADC_GROUP_POWERMODE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_POWERMODE +{ + XMC_VADC_GROUP_POWERMODE_OFF = 0, /**< Group is powered down */ + XMC_VADC_GROUP_POWERMODE_RESERVED1, /**< Reserved */ + XMC_VADC_GROUP_POWERMODE_RESERVED2, /**< Reserved */ + XMC_VADC_GROUP_POWERMODE_NORMAL /**< Group is powered up */ +} XMC_VADC_GROUP_POWERMODE_t; + +/** + * Defines the status of a VADC group (also known as kernel). Use @ref XMC_VADC_GROUP_STATE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_STATE +{ + XMC_VADC_GROUP_STATE_IDLE = 0, /**< Idle and can convert if requested */ + XMC_VADC_GROUP_STATE_BUSY /**< Busy with an ongoing conversion */ +} XMC_VADC_GROUP_STATE_t; + +/** + * Defines the reference to sample time and conversion mode settings. Use @ref XMC_VADC_GROUP_CONV_t for this + * enumeration. + */ +typedef enum XMC_VADC_GROUP_CONV +{ + XMC_VADC_GROUP_CONV_STD = 0, /**< Settings pertaining to channels directly attached to VADC module */ + XMC_VADC_GROUP_CONV_EMUX /**< Settings pertaining to channels connected to VADC via EMUX */ +} XMC_VADC_GROUP_CONV_t; + +/** + * Defines the request source arbiter behavior. Use @ref XMC_VADC_GROUP_ARBMODE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_ARBMODE +{ + XMC_VADC_GROUP_ARBMODE_ALWAYS = 0, /**< Arbiter runs all the time */ + XMC_VADC_GROUP_ARBMODE_ONDEMAND /**< Arbiter runs only if a conversion request is asserted by any of the + request sources */ +} XMC_VADC_GROUP_ARBMODE_t; + +/** + * Defines the EMUX mode of operation. Use @ref XMC_VADC_GROUP_EMUXMODE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_EMUXMODE +{ + XMC_VADC_GROUP_EMUXMODE_SWCTRL = 0, /**< Perform EMUX in Software control mode*/ + XMC_VADC_GROUP_EMUXMODE_STEADYMODE, /**< Perform EMUX in Steady mode (Use EMUX set value)*/ + XMC_VADC_GROUP_EMUXMODE_SINGLEMODE, /**< Perform EMUX in Single step mode*/ + XMC_VADC_GROUP_EMUXMODE_SEQUENCEMODE, /**< Perform EMUX in Sequence mode*/ +} XMC_VADC_GROUP_EMUXMODE_t; + +/** + * Defines the EMUX channel selection encoding scheme. Use @ref XMC_VADC_GROUP_EMUXCODE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_EMUXCODE +{ + XMC_VADC_GROUP_EMUXCODE_BINARY = 0, /**< A linearly incrementing code serves are MUX-SEL */ + XMC_VADC_GROUP_EMUXCODE_GRAY /**< The MUX-SEL is gray encoded */ +} XMC_VADC_GROUP_EMUXCODE_t; + +/** + * Defines the service request set used. Use @ref XMC_VADC_GROUP_IRQ_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_IRQ +{ + XMC_VADC_GROUP_IRQ_KERNEL = 0, /**< Refers to Group specific service request */ + XMC_VADC_GROUP_IRQ_SHARED /**< Refers to Module wide service request */ +} XMC_VADC_GROUP_IRQ_t; + +/** + * Defines the alignment of the converted result. Use @ref XMC_VADC_RESULT_ALIGN_t for this enumeration. + */ +typedef enum XMC_VADC_RESULT_ALIGN +{ + XMC_VADC_RESULT_ALIGN_LEFT = 0, /**< Always align result to left */ + XMC_VADC_RESULT_ALIGN_RIGHT /**< Always align result to right */ +} XMC_VADC_RESULT_ALIGN_t; + +typedef enum XMC_VADC_RESULT_SUBTRATION +{ + XMC_VADC_RESULT_SUBTRATION_12BIT_LEFT_ALIGN = 0U, /**< Always align result to left */ + XMC_VADC_RESULT_SUBTRATION_12BIT_RIGHT_ALIGN = 0U, /**< Always align result to right */ + XMC_VADC_RESULT_SUBTRATION_10BIT_LEFT_ALIGN = 2U, /**< Always align result to left */ + XMC_VADC_RESULT_SUBTRATION_10BIT_RIGHT_ALIGN = 0U, /**< Always align result to right */ + XMC_VADC_RESULT_SUBTRATION_8BIT_LEFT_ALIGN = 4U, /**< Always align result to left */ + XMC_VADC_RESULT_SUBTRATION_8BIT_RIGHT_ALIGN = 0U, /**< Always align result to right */ +} XMC_VADC_RESULT_SUBTRATION_t; + +/** + * Defines the request source arbitration priority. Use @ref XMC_VADC_GROUP_RS_PRIORITY_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_RS_PRIORITY +{ + XMC_VADC_GROUP_RS_PRIORITY_0 = 0, /**< Lowest priority for the request source*/ + XMC_VADC_GROUP_RS_PRIORITY_1, /**< Second lowest priority for the request source*/ + XMC_VADC_GROUP_RS_PRIORITY_2, /**< Second highest priority for the request source*/ + XMC_VADC_GROUP_RS_PRIORITY_3, /**< Highest priority for the request source*/ +}XMC_VADC_GROUP_RS_PRIORITY_t; + +/** + * Defines the various modes for the boundary flag. Use @ref XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_BOUNDARY_FLAG_MODE +{ + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_DISABLED = 0, /**< Disable boundary flag*/ + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED, /**< Always enable boundary*/ + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_LOW, /**< Enable boundary flag when gate level is 0*/ + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_HIGH /**< Enable boundary flag when gate level is 1*/ +}XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_t; + + +/** + * Defines the boundary select for Channel. Use @ref XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_t for this enumeration. + */ +typedef enum XMC_VADC_BOUNDARY_SELECT +{ + XMC_VADC_BOUNDARY_SELECT_LOWER_BOUND = 0U, /**< Select the lower boundary*/ + XMC_VADC_BOUNDARY_SELECT_UPPER_BOUND = 2U /**< Selects the upper boundary*/ +}XMC_VADC_BOUNDARY_SELECT_t; + + +/** + * Defines the group indices. Use @ref XMC_VADC_GROUP_INDEX_t for this enumeration. + */ +typedef enum XMC_VADC_GROUP_INDEX +{ + XMC_VADC_GROUP_INDEX_0 = 0, + XMC_VADC_GROUP_INDEX_1, +#if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2U) + XMC_VADC_GROUP_INDEX_2, + XMC_VADC_GROUP_INDEX_3 +#endif +}XMC_VADC_GROUP_INDEX_t; + +/** +* Defines channel alias. +* All enum items are available for channels 0 and 1. Other Channels can accept only XMC_VADC_CHANNEL_ALIAS_DISABLED. +*/ +typedef enum XMC_VADC_CHANNEL_ALIAS +{ + XMC_VADC_CHANNEL_ALIAS_DISABLED = -1, + XMC_VADC_CHANNEL_ALIAS_CH0 = 0, + XMC_VADC_CHANNEL_ALIAS_CH1 = 1, + XMC_VADC_CHANNEL_ALIAS_CH2 = 2, + XMC_VADC_CHANNEL_ALIAS_CH3 = 3, + XMC_VADC_CHANNEL_ALIAS_CH4 = 4, + XMC_VADC_CHANNEL_ALIAS_CH5 = 5, + XMC_VADC_CHANNEL_ALIAS_CH6 = 6, + XMC_VADC_CHANNEL_ALIAS_CH7 = 7 +} XMC_VADC_CHANNEL_ALIAS_t; + +#if(XMC_VADC_SHS_AVAILABLE == 1U) + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/** + * Defines the gain calibration selection. + */ +typedef enum XMC_VADC_SHS_GAIN_LEVEL +{ + XMC_VADC_SHS_GAIN_LEVEL_0 = SHS_CALOC0_CALOFFVAL0_Pos, /**< Select the calibration value for gain level 0 */ + XMC_VADC_SHS_GAIN_LEVEL_1 = SHS_CALOC0_CALOFFVAL1_Pos, /**< Select the calibration value for gain level 1 */ + XMC_VADC_SHS_GAIN_LEVEL_2 = SHS_CALOC0_CALOFFVAL2_Pos, /**< Select the calibration value for gain level 2 */ + XMC_VADC_SHS_GAIN_LEVEL_3 = SHS_CALOC0_CALOFFVAL3_Pos /**< Select the calibration value for gain level 3 */ +}XMC_VADC_SHS_GAIN_LEVEL_t; +#endif + +/** + * Defines the Delta sigma loop. + */ +typedef enum XMC_VADC_SHS_LOOP_CH +{ + XMC_VADC_SHS_LOOP_CH_0 = SHS_LOOP_LPCH0_Pos, /**< Select Delta-sigma loop 0*/ + XMC_VADC_SHS_LOOP_CH_1 = SHS_LOOP_LPCH1_Pos /**< Select Delta-sigma loop 1*/ +}XMC_VADC_SHS_LOOP_CH_t; + +/** + * Provides the order in which the SHS should do the calibration + */ +typedef enum XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER +{ + XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_POST_CONV = 0, /**< Calibration occur after conversion takes place */ + XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_PRE_CONV /**< Calibration occur before conversion takes place */ +}XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_t; +#endif + +#if (XMC_VADC_BOUNDARY_FLAG_SELECT == 1U) +/** + * Provides possible routing values for the boundary flag. + */ +typedef enum XMC_VADC_BOUNDARY_NODE +{ + XMC_VADC_BOUNDARY_NODE_COMMON_BOUNDARY_FLAG_0 = 0U, /** 2U) + XMC_VADC_SYNCTR_EVAL_2 = VADC_G_SYNCTR_EVALR2_Msk, /**Range:[0x0 to 0x7] */ + uint32_t refill_needed : 1; /**< Conversion completed channel gets inserted back into the queue */ + uint32_t generate_interrupt : 1; /**< Generates a queue request source event */ + uint32_t external_trigger : 1; /**< Conversion requests are raised on an external trigger. */ + uint32_t : 24; + + }; + uint32_t qinr0; + }; +} XMC_VADC_QUEUE_ENTRY_t; + +/** + * Structure initializing a VADC queue request source. Use type @ref XMC_VADC_QUEUE_CONFIG_t. + */ +typedef struct XMC_VADC_QUEUE_CONFIG +{ + uint32_t conv_start_mode : 2; /**< One converter is shared between the queue and scan request sources of the same + group. This field determines how queue request source would request for + conversion. Uses @ref XMC_VADC_STARTMODE_t */ + uint32_t req_src_priority : 2; /**< Request source priority for the arbiter.Uses @ref XMC_VADC_GROUP_RS_PRIORITY_t */ + union + { + struct + { +#if(XMC_VADC_GROUP_SRCREG_AVAILABLE == (1U)) + uint32_t src_specific_result_reg : 4; /**< Uses any one Group related result register as the destination + for all conversions results. To use the individual result register + from each channel configuration, configure this field with 0x0 */ +#else + uint32_t : 4; +#endif + uint32_t : 4; + uint32_t trigger_signal : 4; /**< Select one of the 16 possibilities for trigger. + Uses @ref XMC_VADC_TRIGGER_INPUT_SELECT_t */ + uint32_t : 1; + uint32_t trigger_edge : 2; /**< Edge selection for trigger signal. + Uses @ref XMC_VADC_TRIGGER_EDGE_t */ + uint32_t : 1; + uint32_t gate_signal : 4; /**< Select one of the 16 possibilities for gating. + Uses @ref XMC_VADC_GATE_INPUT_SELECT_t */ + uint32_t : 8; + uint32_t timer_mode : 1; /**< Timer mode for equi-distant sampling shall be activated or not? */ + uint32_t : 3; + }; + uint32_t qctrl0; + }; + union + { + struct + { + uint32_t : 2; + uint32_t external_trigger : 1; /**< Are external triggers supported? */ + uint32_t : 29; + }; + uint32_t qmr0; + }; +} XMC_VADC_QUEUE_CONFIG_t; + + +/** + * Structure to initialize the global input class configuration. Configured parameters are sample time and + * conversion Mode. + */ +typedef struct XMC_VADC_GLOBAL_CLASS +{ + union + { + struct + { + uint32_t sample_time_std_conv : 5; /**< Sample time for channels directly connected to VADC +
Range: [0x0 to 0x1F] */ + uint32_t : 3; + uint32_t conversion_mode_standard : 3; /**< Conversion mode for channels directly connected to VADC. + Uses @ref XMC_VADC_CONVMODE_t */ + uint32_t : 5; +#if(XMC_VADC_EMUX_AVAILABLE == 1U) + uint32_t sampling_phase_emux_channel : 5; /**< Sample time for channels connected via EMUX +
Range: [0x0 to 0x1F] */ + uint32_t : 3; + uint32_t conversion_mode_emux : 3; /**< Conversion mode for channels connected via EMUX to VADC. + Uses @ref XMC_VADC_CONVMODE_t */ + uint32_t : 5; +#else + uint32_t : 16; +#endif + }; + uint32_t globiclass; + }; +} XMC_VADC_GLOBAL_CLASS_t; + +#if (XMC_VADC_GROUP_AVAILABLE != 0U) +/** + * Structure to initialize converter and arbiter clock configuration + */ +typedef struct XMC_VADC_GLOBAL_CLOCK +{ + union + { + struct + { + + uint32_t analog_clock_divider : 5; /**< Clock for the converter.
Range: [0x0 to 0x1F] */ + uint32_t : 2; + uint32_t msb_conversion_clock : 1; /**< Additional clock cycle for analog converter */ + uint32_t arbiter_clock_divider : 2; /**< Request source arbiter clock divider.
Range: [0x0 to 0x3] */ + uint32_t : 5; + uint32_t : 17; + }; + uint32_t globcfg; + }; +} XMC_VADC_GLOBAL_CLOCK_t; +#endif + + +/** + * Structure to initialize the VADC Global functions + */ +typedef struct XMC_VADC_GLOBAL_CONFIG +{ + union + { + struct + { + uint32_t boundary0 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; + uint32_t boundary1 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; + }; + uint32_t globbound; + }; +#if (XMC_VADC_GROUP_AVAILABLE != 0U) + XMC_VADC_GLOBAL_CLOCK_t clock_config; /**< ADC clock configurations*/ +#endif + XMC_VADC_GLOBAL_CLASS_t class0; /**< ADC input conversion configurations for GLOBICLASS[0]*/ + XMC_VADC_GLOBAL_CLASS_t class1; /**< ADC input conversion configurations for GLOBICLASS[1]*/ + union + { + struct + { + uint32_t : 16; + uint32_t data_reduction_control : 4; /**< Data reduction stages */ + uint32_t : 4; + uint32_t wait_for_read_mode : 1; /**< Results of the next conversion will not be overwritten in the + result register until the previous value is read*/ + uint32_t : 6; + uint32_t event_gen_enable : 1; /**< Generates an event on availability of new result. */ + }; + uint32_t globrcr; + }; + union + { + struct + { + uint32_t module_disable : 1; /**< Disables the module clock.*/ + uint32_t : 2; + uint32_t disable_sleep_mode_control : 1; /**< Set it to true in order to disable the Sleep mode */ + uint32_t : 28; + }; + uint32_t clc; + }; +} XMC_VADC_GLOBAL_CONFIG_t; + + +/** + * Structure to initialize the group input class configuration. Configured parameters are sample time and + * conversion Mode. + */ +typedef struct XMC_VADC_GROUP_CLASS +{ + union + { + struct + { + uint32_t sample_time_std_conv : 5; /**< Sample time for channels directly connected to VADC +
Range: [0x0 to 0x1F] */ + uint32_t : 3; + uint32_t conversion_mode_standard : 3; /**< Conversion mode for channels directly connected to VADC. + Uses @ref XMC_VADC_CONVMODE_t */ + uint32_t : 5; + uint32_t sampling_phase_emux_channel : 5; /**< Sample time for channels connected via EMUX +
Range: [0x0 to 0x1F] */ + uint32_t : 3; + uint32_t conversion_mode_emux : 3; /**< Conversion mode for channels connected via EMUX to VADC. + Uses @ref XMC_VADC_CONVMODE_t */ + uint32_t : 5; + }; + uint32_t g_iclass0; + }; +} XMC_VADC_GROUP_CLASS_t; + + +/** + * EMUX related configuration structure. + */ +typedef struct XMC_VADC_GROUP_EMUXCFG +{ + union + { + struct + { + uint32_t starting_external_channel : 3; /**< External channel number to which the VADC will + generate a control signal (needed to select the analog input in + the analog multiplexer)*/ + uint32_t : 13; +#if (XMC_VADC_EMUX_CH_SEL_STYLE == 1U) + uint32_t connected_channel : 10; /**< The Channel to which the EMUX is connected. */ +#else + uint32_t connected_channel : 5; /**< The Channel to which the EMUX is connected. */ + uint32_t : 5; +#endif + uint32_t emux_mode : 2; /**< Selects the external multiplexer modes: Steady, Single Mode, step etc + Uses @ref XMC_VADC_GROUP_EMUXMODE_t*/ + uint32_t emux_coding : 1; /**< Select Binary or Gray coding. Uses @ref XMC_VADC_GROUP_EMUXCODE_t*/ + uint32_t stce_usage : 1; /**< Use STCE for each conversion of an external channel */ +#if (XMC_VADC_EMUX_CH_SEL_STYLE == 1U) + uint32_t emux_channel_select_style : 1; /**< Selects the style of configuring the \b connected_channel + (Each bit represents the channel or entire field represents the channel number ) */ + uint32_t : 1; +#else + uint32_t : 2; +#endif + }; + uint32_t g_emuxctr; + }; +} XMC_VADC_GROUP_EMUXCFG_t; + + +/** + * Group Configuration Data Structures + */ + +typedef struct XMC_VADC_GROUP_CONFIG +{ + XMC_VADC_GROUP_EMUXCFG_t emux_config; /**< External multiplexer related configurations */ + XMC_VADC_GROUP_CLASS_t class0; /**< ADC input conversion configurations for GxICLASS[0]*/ + XMC_VADC_GROUP_CLASS_t class1; /**< ADC input conversion configurations for GxICLASS[1]*/ + union + { + struct + { + uint32_t boundary0 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; + uint32_t boundary1 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; + }; + uint32_t g_bound; + }; + union + { + struct + { + uint32_t : 4; + uint32_t arbitration_round_length : 2; /**< Number of arbiter slots to be considered */ + uint32_t : 1; + uint32_t arbiter_mode : 1; /**< Arbiter mode - Select either Continuous mode or Demand based. + Uses @ref XMC_VADC_GROUP_ARBMODE_t */ + uint32_t : 24; + }; + uint32_t g_arbcfg; + }; +} XMC_VADC_GROUP_CONFIG_t; + +/** + * Structure to initialize VADC Group result register. + */ + +typedef struct XMC_VADC_RESULT_CONFIG +{ + union + { + struct + { + uint32_t : 16; + uint32_t data_reduction_control : 4; /**< Configures the data reduction stages */ + uint32_t post_processing_mode : 2; /**< Result data processing mode. Uses @ref XMC_VADC_DMM_t + For normal operation select + XMC_VADC_DMM_t::XMC_VADC_DMM_REDUCTION_MODE + and data_reduction_control as 0*/ + uint32_t : 2; + uint32_t wait_for_read_mode : 1; /**< Allow the conversion only after previous results are read*/ + uint32_t part_of_fifo : 2; /**< Make the result register a part of Result FIFO? */ + uint32_t : 4; + uint32_t event_gen_enable : 1; /**< Generates an event on availability of new result. */ + }; + uint32_t g_rcr; + }; +} XMC_VADC_RESULT_CONFIG_t; + +#if(XMC_VADC_SHS_AVAILABLE == 1U) +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/** + * Structure to initialize the Stepper configurations + */ +typedef struct XMC_VADC_GLOBAL_SHS_STEP_CONFIG +{ + union + { + struct + { + uint32_t sh_unit_step0 :3; /**< Select a Sample and hold unit for the stepper's step number 0. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step0 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step1 :3; /**< Select a Sample and hold unit for the stepper's step number 1. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step1 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step2 :3; /**< Select a Sample and hold unit for the stepper's step number 2. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step2 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step3 :3; /**< Select a Sample and hold unit for the stepper's step number 3. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step3 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step4 :3; /**< Select a Sample and hold unit for the stepper's step number 4. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step4 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step5 :3; /**< Select a Sample and hold unit for the stepper's step number 5. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step5 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step6 :3; /**< Select a Sample and hold unit for the stepper's step number 6. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step6 :1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step7 :3; /**< Select a Sample and hold unit for the stepper's step number 7. + Uses @ref XMC_VADC_GROUP_INDEX_t*/ + uint32_t enable_step7 :1; /**< Should the step be added to the sequence */ + + }; + uint32_t stepcfg; + }; +}XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t; +#endif +/** + * Sample and hold Initialization structure + */ +typedef struct XMC_VADC_GLOBAL_SHS_CONFIG +{ + union + { + struct + { + uint32_t shs_clock_divider :4; /**< The divider value for the SHS clock. Range: [0x0 to 0xF]*/ + uint32_t :6; + uint32_t analog_reference_select :2; /**< It is possible to different reference voltage for the SHS module + */ + uint32_t :20; + }; + uint32_t shscfg; + }; +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) + XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_t calibration_order; /**< order in which the calibration should be taken up*/ +#endif +}XMC_VADC_GLOBAL_SHS_CONFIG_t; + +#endif +/** + * Detailed result structure + */ + typedef struct XMC_VADC_DETAILED_RESULT +{ + union + { + struct + { + uint32_t result :16; /**< Result of the Analog to digital conversion*/ + uint32_t data_reduction_counter :4; /**< Results reduction counter value*/ + uint32_t channel_number :5; /**< Converted channel number*/ + uint32_t emux_channel_number :3; /**< Converted external multiplexer channel number. + Only applicable for GxRES[0] result register*/ + uint32_t converted_request_source :2; /**< Converted request source*/ + uint32_t fast_compare_result :1; /**< Fast compare result if conversion mode is fast compare mode.*/ + uint32_t vaild_result :1; /**< Valid flag is set when a new result is available*/ + }; + uint32_t res; + }; +}XMC_VADC_DETAILED_RESULT_t; + + +/*Anonymous structure/union guard end*/ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * static inline functions + ********************************************************************************************************************/ + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +__STATIC_INLINE bool XMC_VADC_CHECK_GROUP_PTR(XMC_VADC_GROUP_t *const group_ptr) +{ +#if (XMC_VADC_MAXIMUM_NUM_GROUPS == 4U) + return((group_ptr == VADC_G0) || (group_ptr == VADC_G1) || (group_ptr == VADC_G2) || (group_ptr == VADC_G3)); +#else + return((group_ptr == VADC_G0) || (group_ptr == VADC_G1)); +#endif +} +#endif +/********************************************************************************************************************* + * API Prototypes + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Enables the VADC module.
\n + * This API would ungate the clock to the VADC module (if applicable). Also this API would bring + * the VADC module out of reset state(if applicable), by asserting the appropriate registers. + * This API would invoke XMC_SCU_CLOCK_UngatePeripheralClock() and XMC_SCU_RESET_DeassertPeripheralReset() + * if needed. Directly accessed register is COMPARATOR.ORCCTRL (Refer to the errata for XMC1100). + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_DisableModule(). + */ +void XMC_VADC_GLOBAL_EnableModule(void); + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Disables the VADC module.
\n + * This API would gate the clock to the VADC module (if applicable). Also this API would put + * the VADC module into the reset state(if applicable) by asserting the appropriate registers. + * This API would invoke XMC_SCU_CLOCK_GatePeripheralClock() and XMC_SCU_RESET_AssertPeripheralReset() if needed. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_EnableModule(). + */ +void XMC_VADC_GLOBAL_DisableModule(void); + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * @param config Pointer to initialization data structure + * + * @return None + * + * \parDescription:
+ * Initializes the VADC global module with the associated configuration structure pointed by \a config.\n\n It + * enables the global access to registers by configuring reset and clock un-gating for selected devices. It + * initializes global class, boundary , result resources by setting GLOBICLASS,GLOBBOUND,GLOBRCR registers. It also + * configures the global analog and digital clock dividers by setting GLOBCFG register. Refer related API's to change + * the configurations later in the program. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_ClockInit()
+ */ +void XMC_VADC_GLOBAL_Init(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CONFIG_t *config); + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Enables the VADC module clock.\n\n Call this API before any further configuration of VADC. It sets the DISR bit of CLC + * register to enable. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_Init() + * + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_EnableModuleClock(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_Enable:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->CLC &= ~((uint32_t)VADC_CLC_DISR_Msk); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Disables the VADC module clock.\n\n After this API call, no conversion will occur. Call + * XMC_VADC_GLOBAL_EnableModuleClock() to enable the VADC module later in the program. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_Init() + * + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_DisableModuleClock(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_Disable:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->CLC |= (uint32_t) ((uint32_t)1 << VADC_CLC_DISR_Pos); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Enables VADC module to sleep if a sleep request comes.\n\n + * It resets the EDIS bit of CLC register for enabling the sleep mode. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_DisableSleepMode(). + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_EnableSleepMode(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_EnableSleepMode:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->CLC &= ~((uint32_t)VADC_CLC_EDIS_Msk); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Ignores the sleep mode request for the VADC.\n\n + * With the sleep feature enabled, the module will respond to sleep + * requests by going into a low power mode. It resets the EDIS bit of CLC register for enabling the sleep mode. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_EnableSleepMode(). + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_DisableSleepMode(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_DisableSleepMode:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->CLC |= (uint32_t) ((uint32_t)1 << VADC_CLC_EDIS_Pos); +} + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +/** + * + * @param global_ptr Constant pointer to the VADC module. + * @param config Pointer to the data structure containing clock configuration data + * + * @return None + * + * \parDescription:
+ * Configures the VADC clock.
\n + * Sets up the clock configuration of the VADC module using the config structure pointed by \a config. + * The clock to the analog converter and to the request source arbiter is configured by setting the GLOBCFG register. + * + * \parRelated APIs:
+ * None + * + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_ClockInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CLOCK_t *config) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_ClockInit:Wrong Module Pointer", (global_ptr == VADC)) + + /* Write the Clock configuration into the GLOBCFG register */ + global_ptr->GLOBCFG = (uint32_t)(config->globcfg | (VADC_GLOBCFG_DIVWC_Msk)); +} +#endif + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * @param config Conversion class parameter structure + * @param conv_type configure the input call for either standard conversion or EMUX related conversion. + * @param set_num Conversion class set
+ * Range: [0x0, 0x1] + * + * \parDescription:
+ * Configures the ADC conversion settings like sample time and resolution.
\n + * Sets up the conversion settings for vadc global resource associated with \a config structure. It configures the + * conversion class properties like sampling time and resolution for selected \a conv_type channels. It initializes + * the GLOBALICLASS register specified by \a set_num with the required settings. + * + * + * \parRelated APIs:
+ * None + * + */ + +void XMC_VADC_GLOBAL_InputClassInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CLASS_t config, + const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num); + +/** + * + * @param global_ptr Constant pointer to the VADC global module + * @param config Pointer to result configuration data structure + * + * @return None + * + * \parDescription:
+ * Initializes global result register.
\n + * Initializes Global Result Register with specified settings configured in the \a config structure.\n\n This API + * results in configuration of GLOBRCR register. This helps in configuring the Data reduction mode, global result event + * , wait for read mode on the GLOBRES register. + * + * + * \parRelated APIs:
+ * None + * + */ + + __STATIC_INLINE void XMC_VADC_GLOBAL_ResultInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_RESULT_CONFIG_t *config) + { + XMC_ASSERT("XMC_VADC_GLOBAL_ResultInit:Wrong Module Pointer", (global_ptr == VADC)) + + /* Configure GLOBRCR*/ + global_ptr->GLOBRCR = config->g_rcr; + } + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Enables the startup calibration feature of the VADC module.\n\n It configures the SUCAL bit of GLOBCFG register to + * enable the startup calibration feature. After turning it on, it loops until all active groups finish calibration. + * Call XMC_VADC_GLOBAL_Enable() and XMC_VADC_GLOBAL_ClockInit() before calling this API in sequence. Calling the API + * XMC_VADC_GLOBAL_DisableStartupCalibration() can disable the calibration feature at runtime. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_Enable()
+ * XMC_VADC_GLOBAL_ClockInit()
+ * None + */ +void XMC_VADC_GLOBAL_StartupCalibration(XMC_VADC_GLOBAL_t *const global_ptr); + + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return None + * + * \parDescription:
+ * Disables the startup calibration feature of the VADC module.\n\n It configures the SUCAL bit of GLOBCFG register to + * disable the startup calibration feature. Calling the API XMC_VADC_GLOBAL_EnsableStartupCalibration() can enable the + * calibration feature at runtime. + * + * \parRelated APIs:
+ * None + */ + +__STATIC_INLINE void XMC_VADC_GLOBAL_DisableStartupCalibration(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_DisableStartupCalibration:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->GLOBCFG &= ~((uint32_t)VADC_GLOBCFG_SUCAL_Msk); +} + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param group_number group number whose post calibration feature is to be disabled.
+ * Range[0x0 to 0x3] Accepts the enum ::XMC_VADC_GROUP_INDEX_t + * + * @return None + * + * \parDescription:
+ * Disables the post calibration for a particular group specified as \a group_number.\n\n It configures the DPCAL0 bit + * of GLOBCFG register to disable the post calibration feature. Call XMC_VADC_GLOBAL_Enable() and + * XMC_VADC_GLOBAL_ClockInit() before calling this API in sequence. Calling the API + * XMC_VADC_GLOBAL_EnablePostCalibration() can enable back the calibration feature at runtime. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_Enable()
+ * XMC_VADC_GLOBAL_ClockInit()
+ * XMC_VADC_GLOBAL_DisablePostCalibration()
+ * None + */ + +__STATIC_INLINE void XMC_VADC_GLOBAL_DisablePostCalibration(XMC_VADC_GLOBAL_t *const global_ptr, uint32_t group_number) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_DisablePostCalibration:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->GLOBCFG |= (uint32_t)((uint32_t)1 << ((uint32_t)VADC_GLOBCFG_DPCAL0_Pos + group_number)); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param group_number group number whose post calibration feature is to be enabled.
+ * Range[0x0 to 0x3] Accepts the enum ::XMC_VADC_GROUP_INDEX_t + * + * @return None + * + * \parDescription:
+ * Enables the post calibration for a particular group specified as \a group_number.\n\n It configures the DPCAL0 bit + * of GLOBCFG register to enable the post calibration feature. Calling the API XMC_VADC_GLOBAL_DisablePostCalibration() + * can disable the calibration feature at runtime. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_DisablePostCalibration()
+ * None + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_EnablePostCalibration(XMC_VADC_GLOBAL_t *const global_ptr, uint32_t group_number) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_EnablePostCalibration:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->GLOBCFG &= (~ (uint32_t)((uint32_t)1 << ((uint32_t)VADC_GLOBCFG_DPCAL0_Pos + group_number))); +} +#endif + +#if (XMC_VADC_BOUNDARY_AVAILABLE == 1U) +/** + * + * @param global_ptr Constant pointer to the VADC module. + * @param boundary0 Boundary-0 Value
Range[0 - 4095] + * @param boundary1 Boundary-1 Value
Range[0 - 4095] + * + * @return None + * + * \parDescription:
+ * Programs the boundaries with \a boundary0 and boundary1 for result comparison.\n\n These two boundaries can serve as + * absolute boundaries. They define a range against which the result of a conversion can be compared. In the + * fast compare mode, the two boundaries provide hysteresis capability to a compare value. In any case, these boundary + * values entered here form a boundary pallete. There are dedicated upper and lower boundary registers GLOBBOUND0 and + * GLOBBOUND1 who will derive their values from this palette. + * + * \parRelated APIs:
+ * None + * + */ +void XMC_VADC_GLOBAL_SetBoundaries(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t boundary0, const uint32_t boundary1); + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * @param selection The boundary value selected for \b boundary_value. + * @param boundary_value Boundary Value
Range[0 - 4095] + * + * @return None + * + * \parDescription:
+ * Programs either the boundary 0 or boundary 1 for result comparison.\n\n This defines a range against which + * the result of a conversion can be compared. In the fast compare mode, the two boundaries provide hysteresis + * capability to a compare value. + * + * \parRelated APIs:
+ * None + * + */ +void XMC_VADC_GLOBAL_SetIndividualBoundary(XMC_VADC_GLOBAL_t *const global_ptr, + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value); +#endif + +#if (XMC_VADC_EMUX_AVAILABLE== 1U) +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param emuxif The EMUX interface
Range[0x0 - 0x1] + * @param group The VADC group which must be bound to the desired emux + * + * @return None + * + * \parDescription:
+ * Binds a VADC \a group to an EMUX interface specified in \a emuxif.
\n + * Selects which group's scan request source will control the EMUX interface (set of control select lines for the EMUX). + * By passing \b group it would configure that group's scan request source to control the EMUX select lines of the set + * \b emuxif. + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GLOBAL_BindGroupToEMux(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t emuxif, const uint32_t group); +#endif + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return uint32_t Complete global result register value GLOBRES + * + * \parDescription:
+ * Retrieves the complete result from the global result register associated with the \a global_ptr.\n\n This API audits + * the result register GLOBRES for the validity of the data. If the validity is assured, data is first read + * the global result register, cached locally next and subsequently returned to the caller. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_GetResult() + */ +__STATIC_INLINE uint32_t XMC_VADC_GLOBAL_GetDetailedResult(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_GetDetailedResult:Wrong Module Pointer", (global_ptr == VADC)) + + return(global_ptr->GLOBRES); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module. + * + * @return XMC_VADC_RESULT_SIZE_t 16 bit result register value.
+ * Range[0x0 - 0X0FFF] + * + * \parDescription:
+ * Retrieves the conversion result from the global result register associated with the \a global_ptr.\n\n This is a + * lightweight version of XMC_VADC_GLOBAL_GetDetailedResult(). The behavior is exactly the same, just that it is + * only the 16 bit numeric result returned back to the application instead of the complete GLOBRES register value. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_GetDetailedResult() + */ +__STATIC_INLINE XMC_VADC_RESULT_SIZE_t XMC_VADC_GLOBAL_GetResult(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_GetResult:Wrong Module Pointer", (global_ptr == VADC)) + + return ((XMC_VADC_RESULT_SIZE_t)global_ptr->GLOBRES); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param compare_val Compare value which the result of a conversion will be compared against. + *
Range[0x0 - 0X0FFF] + * + * @return None + * + * \parDescription:
+ * Set compare value in the global result register for fast compare mode.\n\n The result of a conversion will directly + * be compared to the compare value entered as part of \a compare_val. The prerequisite is that the channel associated + * with this global register must select an ICLASS which has the conversion mode configured as fast compare mode. Call + * @ref XMC_VADC_GLOBAL_GetCompareResult() after this API to + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GLOBAL_SetCompareValue(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_RESULT_SIZE_t compare_val); + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @return compare high or low. Refer @ref XMC_VADC_FAST_COMPARE_t enum + * + * @return None + * + * \parDescription:
+ * Determines the result of fast compare operation.\n\n This API returns the result of fast compare operation provided + * the valid flag in the global result register GLOBRES is set. + * + * \parRelated APIs:
+ * None + */ +XMC_VADC_FAST_COMPARE_t XMC_VADC_GLOBAL_GetCompareResult(XMC_VADC_GLOBAL_t *const global_ptr); + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param event_type Desired event that must be manually asserted + * Use the enum ::XMC_VADC_GLOBAL_EVENT_t to create a mask to be used with this argument + * @return None + * + * \parDescription:
+ * Manually asserts an event that can lead to an interrupt.\n\n This API manually asserts the requested event + * (Background request source event or a global result event) by setting the GLOBEVFLAG register with the specified + * \a event_type. + * + * \parRelated APIs:
+ * None + */ + +__STATIC_INLINE void XMC_VADC_GLOBAL_TriggerEvent(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t event_type) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_TriggerEvent:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_TriggerEvent:Wrong Global Event", + ((XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE == event_type) || (XMC_VADC_GLOBAL_EVENT_RESULT == event_type))) + + global_ptr->GLOBEFLAG = event_type; +} + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param event_type Event that must be acknowledged + * Use the enum ::XMC_VADC_GLOBAL_EVENT_t to create a mask to be used with this argument + * + * @return None + * + * \parDescription:
+ * Acknowledges an event that has been asserted manually or automatically.\n\n This API acknowledges the requested event + * by clearing GLOBEFLAG sticky flag. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_ClearEvent(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t event_type) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_ClearEvent:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_ClearEvent:Wrong Global Event", + ((XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE == event_type) || (XMC_VADC_GLOBAL_EVENT_RESULT == event_type))) + + global_ptr->GLOBEFLAG = ((uint32_t)(event_type << (uint32_t)16)); +} + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param sr The service request to which the global result event is connected. Refer @ref XMC_VADC_SR_t enum + * + * @return None + * + * \parDescription:
+ * Binds the global result event to one of the 4 shared service requests.\n\n This API binds the global result event + * to one of the 4 module wide shared service requests .Sets GLOBEVNP register with the corresponding \a sr line. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode() + */ +void XMC_VADC_GLOBAL_SetResultEventInterruptNode(XMC_VADC_GLOBAL_t *const global_ptr, XMC_VADC_SR_t sr); + +/** + * + * @param global_ptr Constant pointer to the VADC module + * @param sr The service request to which the global request source event is connected. Refer @ref XMC_VADC_SR_t enum + * + * @return None + * + * \parDescription:
+ * Binds the background request source event to one of the 4 shared service requests.\n\n This API binds the background + * request source event to one of the 4 module wide shared service requests. Sets GLOBEVNP register with the + * corresponding \a sr line. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SetResultEventInterruptNode() + */ +void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *const global_ptr, XMC_VADC_SR_t sr); + +#if(XMC_VADC_SHS_AVAILABLE == 1U) +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param config Struct consisting of various SHS related configurations. + * + * @return None + * + * \parDescription:
+ * Configure the basic SHS parameters.
\n + * API would initialize the clock divider configuration, the analog reference selection and + * the calibration order for the Sample and Hold unit. + * + * \parRelated APIs:
+ * None. + */ + void XMC_VADC_GLOBAL_SHS_Init(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, const XMC_VADC_GLOBAL_SHS_CONFIG_t *config); + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) + /** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param config Struct consisting of various step configurations. + * + * @return None + * + * \parDescription:
+ * Configures the stepper sequence for the converter.
\n + * Stepper of the SHS can be configured to take up a specific sequence of groups for conversion. + * The stepper sequence is configured using this API. + * + * \parRelated APIs:
+ * None. + */ + __STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetStepperSequence(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + const XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t *config) + { + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_StepperInit:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_StepperInit:Wrong config pointer", + (config == (XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t*)NULL)) + + shs_ptr->STEPCFG = (uint32_t) config->stepcfg; + } +#endif + + /** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * + * @return bool returns true if the analog converter is operable + * returns false if the analog converter is powered down + * + * \parDescription:
+ * Returns the converter status.
\n + * Returns the ANRDY bit field of the SHSCFG register. + * + * \parRelated APIs:
+ * None. + */ + __STATIC_INLINE bool XMC_VADC_GLOBAL_SHS_IsConverterReady(XMC_VADC_GLOBAL_SHS_t *const shs_ptr) + { + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_IsConverterReady:Wrong SHS Pointer",(shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + + return((bool)((shs_ptr->SHSCFG >> (uint32_t)SHS_SHSCFG_ANRDY_Pos) & (uint32_t)0x1)); + } + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num group number for which the accelerated mode needs to be enabled.
Range: [0x0 to 0x1] + * + * @return None + * + * \parDescription:
+ * Enables the Accelerated timing mode.
\n + * This API is needed when a switch from compatible mode to accelerated mode of conversion is needed. In + * this mode the ADC module will convert the input depending on the value stored in the SST bit of the SHS0_TIMCFGx. + * This API would configure the accelerated mode in the SHS0_TIMCFG0 and SHS0_TIMCFG1 registers. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr,XMC_VADC_GROUP_INDEX_t group_num); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num group number for which the accelerated mode needs to be disabled.
Range: [0x0 to 0x1] + * + * @return None + * + * \parDescription:
+ * Enables the Accelerated timing mode.
\n + * This API is needed when a switch from accelerated mode to compatible mode of conversion is needed. + * This API would clear the accelerated mode in the SHS0_TIMCFG0 and SHS0_TIMCFG1 registers. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr,XMC_VADC_GROUP_INDEX_t group_num); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num group number for which the accelerated mode needs to be enabled.
Range: [0x0 to 0x1] + * @param sst_value Value of short sample time that needs to be configured.
+ * Range: [0x0 to 0x3F] + * + * @return None + * + * \parDescription:
+ * Configures the Accelerated timing mode sample time.
\n + * This API is needed when a switch from compatible mode to accelerated mode of conversion is needed. In + * Accelerated mode the ADC module will convert the input depending on the value stored in the SST bit of the + * SHS0_TIMCFGx. This API would configure the shot sample time either in SHS0_TIMCFG0.SST or SHS0_TIMCFG1.SST . + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GLOBAL_SHS_SetShortSampleTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + uint8_t sst_value); + +#endif +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param divs_value The clock divider value that is possible + *
Range:[0x0 to 0xF] + * @return None + * + * \parDescription:
+ * Configure Sample and hold clock divider value.
\n + * API would initialize the clock divider configuration. This determines the frequency of conversion + * of the Sample and hold converter. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetClockDivider(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, uint8_t divs_value) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetClockDivider:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetClockDivider:Wrong divide factor selected", + (divs_value < (uint32_t)0x10)) + + shs_ptr->SHSCFG = (shs_ptr->SHSCFG & (~(uint32_t)SHS_SHSCFG_DIVS_Msk)) | (uint32_t)SHS_SHSCFG_SCWC_Msk; + shs_ptr->SHSCFG |= ((uint32_t)divs_value << SHS_SHSCFG_DIVS_Pos) | (uint32_t)SHS_SHSCFG_SCWC_Msk; +} + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param gain_value gain value possible + * Range:[0x0 to 0x3] + * @param group_num The Group number for which the configurations applies + * @param ch_num The channel number for which the gain has to be configured + * @return None + * + * \parDescription:
+ * Configure the gain value for SHS.
\n + * API would set the gain factor for a selected channel. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GLOBAL_SHS_SetGainFactor(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + uint8_t gain_value, + XMC_VADC_GROUP_INDEX_t group_num, + uint8_t ch_num); + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param max_calibration_time calibration time + * Range:[0x0 to 0x3F] + * @return None + * + * \parDescription:
+ * Configure the Maximum calibration timing.
\n + * API would initialize the Maximum time after which the calibration should occur. If no adc conversion + * occur during this duration then the calibration would run irrespective of conversions. The max time the + * converter can go without a calibration is set in this API. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetMaxCalTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + uint32_t max_calibration_time) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetMaxCalTime:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + + shs_ptr->CALCTR &= ~((uint32_t)SHS_CALCTR_CALMAX_Msk); + shs_ptr->CALCTR |= ((uint32_t)max_calibration_time << SHS_CALCTR_CALMAX_Pos); +} + + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num The Group number for which the configurations applies + * @return None + * + * \parDescription:
+ * Enable the Gain and offset calibration.
\n + * Enable the gain and offset calibration for all the Sample and hold units. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations()
. + */ +void XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num The Group number for which the configurations applies + * @return None + * + * \parDescription:
+ * Disable the Gain and offset calibration.
\n + * Disable the gain and offset calibration for all the Sample and hold units. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations()
. + */ +void XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num The Group number for which the configurations applies + * @param gain_level The gain level whose calibration value has to read. + * @return None + * + * \parDescription:
+ * Read the calibration value for the selected gain level.
\n + * Each gain value has a offset calibration value, this API would return the offset calibration value of the + * selected gain level. This is applicable for all the channels in the group that use the particular gain level. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue()
. + */ +uint8_t XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num The Group number for which the configurations applies + * @param gain_level The gain level whose calibration value has to read. + * @param offset_calibration_value The offset calibration value to be set. + * @return None + * + * \parDescription:
+ * Set the calibration value for the selected gain level.
\n + * Each gain value has a offset calibration value, this API would set the offset value of the selected gain level. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue()
. + */ +void XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level, + uint8_t offset_calibration_value); +#endif + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param group_num The Group number for which the configurations applies + * @param loop_select The delta sigma loop number for which the configurations applies + * @param ch_num Channel number for which the configurations applies + * @return None + * + * \parDescription:
+ * Configures the delta sigma loop of the SHS.
\n + * There are 2 Delta-Sigma loops that can be configured. This API would configure the loop (loop_select) + * with the appropriate group_num and channel_num. + * Configures the SHS_LOOP bit fields. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop()
. + */ +void XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_LOOP_CH_t loop_select, + uint8_t ch_num); + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param loop_select The delta sigma loop number for which the configurations applies + * @return None + * + * \parDescription:
+ * Enable the selected Delta-Sigma loop.
\n + * Configures the SHS_LOOP.LPENx bit field. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop()
. + * XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations()
. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_SHS_LOOP_CH_t loop_select) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop:Wrong Delta sigma loop selected", + (loop_select == XMC_VADC_SHS_LOOP_CH_0)||(loop_select == XMC_VADC_SHS_LOOP_CH_1)) + + shs_ptr->LOOP |= (uint32_t)SHS_LOOP_LPEN0_Msk << (uint32_t)loop_select; +} + +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param loop_select The delta sigma loop number for which the configurations applies + * @return None + * + * \parDescription:
+ * Disable the selected delta sigma loop.
\n + * Configures the SHS_LOOP.LPENx bit field. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop()
. + * XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations()
. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_SHS_DisableSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_SHS_LOOP_CH_t loop_select) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableSigmaDeltaLoop:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableSigmaDeltaLoop:Wrong Delta sigma loop selected", + (loop_select == XMC_VADC_SHS_LOOP_CH_0)||(loop_select == XMC_VADC_SHS_LOOP_CH_1)) + + shs_ptr->LOOP &= ~((uint32_t)SHS_LOOP_LPEN0_Msk << (uint32_t)loop_select); + +} + +#endif +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +/** + * + * @param group_ptr Constant pointer to the VADC group. + * @param config Pointer to the initialization data structure + * + * @return None + * + * \parDescription:
+ * Initializes the VADC group module with the associated configuration structure pointed by \a config.\n\n It + * initializes the group specified as part of the \a group_ptr. It initializes group conversion class, arbiter + * configuration , boundary configuration by setting GxICLASS,GxARBCFG,GxBOUND, registers. It also + * configures the EMUX control register if applicable. Refer related API's to change the configurations later in the + * program. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_InputClassInit()
+ * XMC_VADC_GROUP_SetPowerMode()
+ * XMC_VADC_GROUP_SetBoundaries()
+ * XMC_VADC_GROUP_ExternalMuxControlInit()
+ */ +void XMC_VADC_GROUP_Init(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_CONFIG_t *config); + +/** + * + * @param group_ptr Constant pointer to the VADC group. + * @param config group related conversion class parameter structure + * @param conv_type Use direct channels or EMUX channels. Refer @ref XMC_VADC_GROUP_CONV_t enum + * @param set_num Conversion class set
+ * Range[0x0, 0x1] + * + * @return None + * + * \parDescription:
+ * Sets up the conversion settings for vadc group resource associated with \a config structure. It configures the + * conversion class properties like sampling time and resolution for selected \a conv_type channels. It initializes + * the G_ICLASS register specified by \a set_num with the required settings. + * + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_Init() + * + */ +void XMC_VADC_GROUP_InputClassInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_CLASS_t config, + const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num); + +/** + * + * @param group_ptr Constant pointer to the VADC Group which must be set as a slave + * @param master_grp The master group number
+ * Range: [0x0 - 0x3] + * @param slave_group The slave group number
+ * Range: [0x0 - 0x3] + * + * @return None + * + * \parDescription:
+ * Configures a VADC Group as a slave group.\n\n Conversion of identically numbered channels across groups can be + * synchronized. For example, when the trigger to convert CH-1 of Group-2 is received, it is possible to + * simultaneously request conversion of CH-1 of Group-0 and Group-3. Group-2 in this example is therefore the + * master group while Groups-0 and 3 are the slave groups. It uses the SYNCCTR register for the configuration settings. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_SetSyncMaster()
+ * XMC_VADC_GROUP_CheckSlaveReadiness()
+ * XMC_VADC_GROUP_EnableChannelSyncRequest()
+ * + */ +void XMC_VADC_GROUP_SetSyncSlave(XMC_VADC_GROUP_t *const group_ptr, uint32_t master_grp, uint32_t slave_group); + +/** + * + * @param group_ptr Constant pointer to the VADC Group. + * @param power_mode Desired power mode + * + * @return None + * + * \parDescription:
+ * Configures the power mode of a VADC group.\n\n For a VADC group to actually convert an analog signal, its analog + * converter must be turned on. + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GROUP_SetPowerMode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_POWERMODE_t power_mode); + +/** + * + * @param group_ptr Constant pointer to the VADC group. + * + * @return None + * + * \parDescription:
+ * Configures a VADC Group as a master group.
\n + * Conversion of identically numbered channels across groups can be + * synchronized. For example, when the trigger to convert CH-1 of Group-2 is received, it is possible to simultaneously + * request conversion of CH-1 of Group-0 and Group-3. Group-2 in this example is therefore the master group while + * Groups-0 and 3 are the slave groups. + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GROUP_SetSyncMaster(XMC_VADC_GROUP_t *const group_ptr); + +/** + + * @param group_ptr Pointer to the master VADC Group + * @param slave_group The slave VADC Group number + *
Range: [0x0 to 0x3] + * @return None + * + * \parDescription:
+ * Configures the ready signal for master group.
\n + * This API would read the \b slave_group number and determine which EVAL configuration to apply for the given master + * slave set. Checks the readiness of slaves in synchronized conversions. Conversion of identically numbered channels + * across groups can be synchronized. For example, when the trigger to convert CH-1 of Group-2 is received, it is + * possible to simultaneously request conversion of CH-1 of Group-0 and Group-3. Group-2 in this example is + * therefore the master group while Groups-0 and 3 are the slave groups. Before the master can request its slaves + * for synchronized conversion, it has the option of checking the readiness of the slaves. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_IgnoreSlaveReadiness()
XMC_VADC_GROUP_SetSyncMaster() + */ +void XMC_VADC_GROUP_CheckSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group); + +/** + * + * @param group_ptr Constant Pointer to the master VADC Group + * @param slave_group The slave VADC Group number + * @return None + * + * \parDescription:
+ * Clears the ready signal for master group.
\n + * Ignores the readiness of slaves in synchronized conversions.This API would read the \b slave_group number and + * determine which EVAL configuration to apply for the given master slave set. Then clears the configuration if present. + * This API is called when the master should issue the conversion request without waiting for the slave to + * assert a ready signal. The ready signal is asserted by the slave group(s) when the conversion is completed + * in these channels. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_CheckSlaveReadiness()
XMC_VADC_GROUP_SetSyncMaster()
+ */ +void XMC_VADC_GROUP_IgnoreSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group); + +/** + * + * @param group_ptr Constant Pointer to the VADC Group waiting for ready signal + * @param eval_waiting_group The VADC Group which expects a ready signal to start it's conversion. + * @param eval_origin_group The VADC Group from which the eval_waiting_group will expect a ready signal + * @return None + * + * \parDescription:
+ * Sets the ready signal in the eval_waiting_group .
\n + * For Synchronized conversion all the slaves participating need to configure the ready signal. + * A slave group will also need to configure the ready signals coming from the other slave groups. + * A call to this API would configure the Sync.slave's EVAL Bits (GxSYNCTR.EVALy). + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_CheckSlaveReadiness()
XMC_VADC_GROUP_IgnoreSlaveReadiness()
+ */ +void XMC_VADC_GROUP_SetSyncSlaveReadySignal(XMC_VADC_GROUP_t *const group_ptr, + uint32_t eval_waiting_group, + uint32_t eval_origin_group); + +/** + * + * @param group_ptr Constant Pointer to the VADC Group + * @return + * uint32_t EVAL bits for the group + * + * \parDescription:
+ * Get the Eval bits of the group.
\n + * For Synchronized conversion the master's ready signal configuration must be copied onto the slaves. + * A call to this API would return the Sync EVAL Bits (GxSYNCTR.EVALy) which can be used to set in the slaves. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_CheckSlaveReadiness()
XMC_VADC_GROUP_IgnoreSlaveReadiness()
+ */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetSyncReadySignal(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t eval_mask; + XMC_ASSERT("XMC_VADC_GROUP_GetSyncReadySignal:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + +#if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2U) + eval_mask = VADC_G_SYNCTR_EVALR1_Msk | VADC_G_SYNCTR_EVALR2_Msk | VADC_G_SYNCTR_EVALR3_Msk; +#else + eval_mask = VADC_G_SYNCTR_EVALR1_Msk; +#endif + return( group_ptr->SYNCTR & eval_mask); +} + +/** + * @param group_ptr Constant Pointer to the VADC Group + * @param eval_mask mask to configure the eval bits + * Use XMC_VADC_SYNCTR_EVAL_t to create the mask. + * @return None + * + * \parDescription:
+ * Set the Eval bits of the group.
\n + * For Synchronized conversion the master's ready signal configuration must be copied onto the slaves. + * A call to this API would configure the Sync EVAL Bits (GxSYNCTR.EVALy). + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_CheckSlaveReadiness()
XMC_VADC_GROUP_IgnoreSlaveReadiness()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_SetSyncReadySignal(XMC_VADC_GROUP_t *const group_ptr, uint32_t mask) +{ + uint32_t eval_mask; + XMC_ASSERT("XMC_VADC_GROUP_SetSyncReadySignal:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + +#if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2U) + eval_mask = VADC_G_SYNCTR_EVALR1_Msk | VADC_G_SYNCTR_EVALR2_Msk | VADC_G_SYNCTR_EVALR3_Msk; +#else + eval_mask = VADC_G_SYNCTR_EVALR1_Msk; +#endif + group_ptr->SYNCTR &= ~(eval_mask); + group_ptr->SYNCTR |= mask; +} + +/** + * + * @param group_ptr Constant pointer to the master VADC Group + * @param ch_num Channel whose conversion triggers conversion in slave groups + * @return None + * + * \parDescription:
+ * Sets up a channel for synchronized conversion.\n\n Conversion of identically numbered channels across groups + * can be synchronized. For example, when the trigger to + * convert CH-1 of Group-2 is received, it is possible to simultaneously request conversion of CH-1 of Group-0 and + * Group-3. Group-2 in this example is therefore the master group while Groups-0 and 3 are the slave groups.
+ * Before the master can request its slaves for synchronized conversion, it has the option of checking the readiness + * of the slaves. + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GROUP_EnableChannelSyncRequest(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num); + +/** + * + * @param group_ptr Pointer to the master VADC Group + * @param ch_num Channel whose conversion triggers conversion in slave groups + * @return None + * + * \parDescription:
+ * Disable the synchronization request for the particular channel specified as ch_num. To enable the synchronization + * call the API @ref XMC_VADC_GROUP_EnableChannelSyncRequest(). + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GROUP_DisableChannelSyncRequest(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num); + +/** + * + * @param group_ptr Constant pointer to the VADC group. + * + * @return retuns IDLE if converter is free else returns busy. Refer @ref XMC_VADC_GROUP_STATE_t enum + * + * \parDescription:
+ * Checks the live status of the analog to digital converter. The converter can either idle doing nothing or busy + * sampling + converting. + * + * \parRelated APIs:
+ * None + */ +XMC_VADC_GROUP_STATE_t XMC_VADC_GROUP_IsConverterBusy(XMC_VADC_GROUP_t *const group_ptr); + +/** + * + * @param group_ptr Constant pointer to the VADC group whose global boundary registers are to be programmed + * @param boundary0 Boundary-0 Value
+ * Range: [0x0 - 0x0FFF] + * @param boundary1 Boundary-1 Value
+ * Range: [0x0 - 0x0FFF] + * + * @return None + * + * \parDescription:
+ * Programs the boundaries with \a boundary0 and boundary1 for result comparison.\n\n These two boundaries can serve as + * absolute boundaries. They defines a range against which the result of a conversion can be compared. In the + * fast compare mode, the two boundaries provide hysteresis capability to a compare value. In any case, these boundary + * values entered here form a boundary pallete. There are dedicated upper and lower boundary registers G_BOUND0 and + * G_BOUND1 who will derive their values from this palette. + * + * \parRelated APIs:
+ * None + * + */ +void XMC_VADC_GROUP_SetBoundaries(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t boundary0, + const uint32_t boundary1); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param selection The boundary value selected for \b boundary_value. + * @param boundary_value Select the boundary value. + * @return + * None + * + * \parDescription:
+ * Programs the boundary with \a boundary_value for result comparison.\n\n This defines a range against which + * the result of a conversion can be compared. In the fast compare mode, the two boundaries provide hysteresis + * capability to a compare value. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_SetIndividualBoundary(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param sr_num The service request number (0 through 3) + * @param type IRQ type (Kernel specific interrupt vs Module wide shared interrupt ) + * @return None + * + * \parDescription:
+ * Activates a Service Request line(manually trigger).
\n + * VADC provides few SR lines for each group and a few more which is shared across all the groups. + * These SR lines can be connected to an NVIC node which in-turn would generate an interrupt. + * This API would manually trigger the given SR line. Could be used for evaluation and testing purposes. + * + * \parRelated APIs:
+ * None + */ +void XMC_VADC_GROUP_TriggerServiceRequest(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t sr_num, + const XMC_VADC_GROUP_IRQ_t type); + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param emux_cfg EMUX configuration structure + * @return None + * + * \parDescription:
+ * Configures group EMUX parameters associated with the \a emux_cfg configuration structure.\n\n An external emux + * interface allows additional channels to be connected to a VADC group. The conversion properties + * of such channels can be different from the standard channels which are directly connected to the VADC group. + * This API configures conversion properties of channels connected via EMUX interface. + * + * \parRelated APIs:
+ * None + */ +__STATIC_INLINE void XMC_VADC_GROUP_ExternalMuxControlInit(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_GROUP_EMUXCFG_t emux_cfg) +{ + uint32_t emux_config; + + XMC_ASSERT("XMC_VADC_GROUP_ExternalMuxControlInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + emux_config = ((uint32_t)emux_cfg.starting_external_channel << (uint32_t)VADC_G_EMUXCTR_EMUXSET_Pos) | + ((uint32_t)emux_cfg.connected_channel << (uint32_t)VADC_G_EMUXCTR_EMUXCH_Pos); + + group_ptr->EMUXCTR = emux_config; + emux_config = ((uint32_t)emux_cfg.emux_coding << (uint32_t)VADC_G_EMUXCTR_EMXCOD_Pos) | + ((uint32_t)emux_cfg.emux_mode << (uint32_t)VADC_G_EMUXCTR_EMUXMODE_Pos)| + ((uint32_t)emux_cfg.stce_usage << (uint32_t)VADC_G_EMUXCTR_EMXST_Pos); + +#if (XMC_VADC_EMUX_CH_SEL_STYLE == 1U) + emux_config |= ((uint32_t)emux_cfg.emux_channel_select_style << (uint32_t)VADC_G_EMUXCTR_EMXCSS_Pos); +#endif + group_ptr->EMUXCTR |= (emux_config | ((uint32_t)VADC_G_EMUXCTR_EMXWC_Msk)) ; +} + +#if XMC_VADC_BOUNDARY_FLAG_SELECT == 1U + +/** + * @param group_ptr Constant pointer to the VADC group + * @param boundary_flag_num The Boundary flag for which the interrupt node needs to be configured. + * Range: [0x0 to 0x3] + * @param node Service Request node Id + * @return + * None + * + * \parDescription:
+ * Connects the boundary event to the SR line of VADC or to a common boundary flag.
\n + * This API will connect a Service Request line(SR) to a boundary event. Hence to get a interrupt on this + * Service request line one has to enable the required NVIC node. A call to this API would configure the register bit + * field GxBFLNP.BFLxNP. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_SetBoundaryEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint8_t boundary_flag_num, + const XMC_VADC_BOUNDARY_NODE_t node); +#endif + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * uint32_t The complete GxALIAS register + * + * \parDescription:
+ * Returns the ALIAS values.\n The ALIAS value that is configured for Channel-0 and channel-1 are returned. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetAlias(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_GetAliasWrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return (group_ptr->ALIAS); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param conv_class conversion property to be extracted + * @return + * XMC_VADC_GROUP_CLASS_t The complete GxICLASSy register + * + * \parDescription:
+ * Returns the input class configuration values.\n + * This returns the sampling time configuration and resolution configured in the appropriate group input class + * \b conv_class. A call to this API would return the register GxICLASSy. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_VADC_GROUP_CLASS_t XMC_VADC_GROUP_GetInputClass(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_CHANNEL_CONV_t conv_class) +{ + XMC_VADC_GROUP_CLASS_t input_value; + XMC_ASSERT("XMC_VADC_GROUP_GetInputClass:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetInputClass:Wrong conv_class selected", + (XMC_VADC_CHANNEL_CONV_GROUP_CLASS0 == conv_class) || (XMC_VADC_CHANNEL_CONV_GROUP_CLASS1 == conv_class)) + + input_value.g_iclass0 = (uint32_t) 0xFFFFFFFF; + if ((XMC_VADC_CHANNEL_CONV_GROUP_CLASS0 == conv_class) || (XMC_VADC_CHANNEL_CONV_GROUP_CLASS1 == conv_class)) + { + input_value.g_iclass0 = group_ptr->ICLASS[(uint32_t)conv_class]; + } + + return (input_value); +} +#endif + +#if (XMC_VADC_GSCAN_AVAILABLE == 1U) +/** + * @param group_ptr Pointer to the VADC group + * @param config Pointer to Scan configuration + * @return None + * + * \parDescription:
+ * Initializes the VADC SCAN functional block.
\n + * The GROUP SCAN request source functional block converts channels sequentially starting with the highest numbered + * channel to the lowest. Channels must register themselves as being part of the the scan sequence. + * A call to this API will first disable the arbitration slot for queue (XMC_VADC_GROUP_ScanEnableArbitrationSlot()) + * and then it would configure all the related registers with the required configuration values. + * The arbitration slot is re-enabled at the end of init by invoking XMC_VADC_GROUP_ScanDisableArbitrationSlot(). + * A call to this API would configure the registers GxARBPR, GxASCTRL, GxASMR needed scan request source. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableArbitrationSlot()
XMC_VADC_GROUP_ScanDisableArbitrationSlot()
+ * XMC_VADC_GROUP_ScanSelectTrigger()
XMC_VADC_GROUP_ScanSelectGating()
+ */ +void XMC_VADC_GROUP_ScanInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SCAN_CONFIG_t *config); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables arbitration slot of the scan request source.
\n + * If the scan request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the scan channel can only be converted when the arbiter comes + * to the scan slot. Thus this must be enabled if any conversion need to take place. + * A call to this API would configure the register bit field GxARBPR.ASEN1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanDisableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanEnableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanEnableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ARBPR |= (uint32_t)VADC_G_ARBPR_ASEN1_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables arbitration slot of the scan request source.
\n + * If the scan request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the scan channel can only be converted when the arbiter comes + * to the scan slot.A call to this API will lead to all conversions request by scan to be blocked. + * A call to this API would configure the register bit field GxARBPR.ASEN1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanDisableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanDisableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ARBPR &= ~((uint32_t)VADC_G_ARBPR_ASEN1_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * bool returns true if the arbitration is enabled else returns false. + * + * \parDescription:
+ * Returns the arbitration status of the scan request source.
\n + * If the scan request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the scan channel can only be converted when the arbiter comes + * to the scan slot. A call to this API would return the status of the arbitration slot of scan. + * A call to this API would read the register bit field GxARBPR.ASEN1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableArbitrationSlot(),
XMC_VADC_GROUP_ScanDisableArbitrationSlot()
+ */ +__STATIC_INLINE bool XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + return ((group_ptr->ARBPR & (uint32_t)VADC_G_ARBPR_ASEN1_Msk) >> VADC_G_ARBPR_ASEN1_Pos); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param trigger_input Choice of the input earmarked as a trigger line + * @return + * None + * + * \parDescription:
+ * Select Trigger signal for scan request source.
\n + * A scan request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 16 input lines as a trigger line. This is + * needed when a hardware trigger is needed for the conversion of the scan request source. + * Refer to the reference manual to determine the signal that needs to be connected. + * A call to this API would configure the register bit field GxASCTRL.XTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanSelectGating()
XMC_VADC_GROUP_ScanEnableExternalTrigger()
+ */ +void XMC_VADC_GROUP_ScanSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_TRIGGER_INPUT_SELECT_t trigger_input); + + +/** + * @param group_ptr Constant pointer to the VADC group + * @param trigger_edge Trigger edge selection + * @return + * None + * + * \parDescription:
+ * Selects the trigger edge for scan request source.
\n + * A scan request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 4 possible trigger edges. This is + * needed when a hardware trigger is needed for the conversion of the scan request source. + * A call to this API would configure the register bit field GxASCTRL.XTMODE. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanSelectTrigger()
+ */ +void XMC_VADC_GROUP_ScanSelectTriggerEdge(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_TRIGGER_EDGE_t trigger_edge); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param gating_input Module input signal meant to be selected as gating input + * @return + * None + * + * \parDescription:
+ * Select Gating signal for scan request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. Any one of the 16 input + * lines can be chosen as a gating signal. Trigger signal can be given to the scan request source only + * when the gating signal's active level is detected. Additionally the GxASMR.ENGT has to be configured for + * the gating signal's active level. A call to this API would configure the register bit field GxASCTRL.GTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanSelectTrigger()
+ */ +void XMC_VADC_GROUP_ScanSelectGating(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_GATE_INPUT_SELECT_t gating_input); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param mode_sel Select how the gating is applied to the scan request source + * @return + * None + * + * \parDescription:
+ * Selects the gating mode of scan request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. + * This API determines how the gating signal behaves, either active low or active high. + * If gating signal needs to ignored XMC_VADC_GATEMODE_IGNORE should be used as the \a mode_sel. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanSelectGating(); + */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanSetGatingMode(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_GATEMODE_t mode_sel) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanSetGatingMode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSetGatingMode:Wrong mode selected", (mode_sel <= XMC_VADC_GATEMODE_ACTIVELOW)) + + /* Clear the existing gate configuration */ + group_ptr->ASMR &= (uint32_t) (~((uint32_t)VADC_G_ASMR_ENGT_Msk)); + /* Set the new gating mode */ + group_ptr->ASMR |= (uint32_t)((uint32_t)mode_sel << VADC_G_ASMR_ENGT_Pos); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables continuous conversion mode.
\n + * Typically for a scan request source to generate conversion request, either a hardware trigger or a software + * request is a pre-requisite. Using autoscan feature it is possible to start the conversion once and allow the + * sequence to repeat without any further triggers. Once all channels belonging to a scan request source have + * been converted, a request source completion event is generated. Generation of this event can restart the scan + * sequence. Every request source event will cause a load event to occur. A call to this API would configure + * the register bit field GxASMR.SCAN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanDisableContinuousMode()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanEnableContinuousMode(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanEnableContinuousMode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_SCAN_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables continuous conversion mode.
\n + * Typically for a scan request source to generate conversion request, either a hardware trigger or a software + * request is a pre-requisite. Using autoscan feature it is possible to start the conversion once and allow the + * sequence to repeat without any further triggers. Once all channels belonging to a scan request source have + * been converted, a request source completion event is generated. Generation of this event can restart the scan + * sequence. By invoking this feature the Autoscan mode of operations is disabled. A call to this API would configure + * the register bit field GxASMR.SCAN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableContinuousMode()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanDisableContinuousMode(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanDisableContinuousMode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_SCAN_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Generates conversion request (Software initiated conversion).
\n + * A conversion request can be raised either upon detection of a hardware trigger, or by software. This API forces + * the scan unit to generate a conversion request to the analog converter. It is assumed that the scan has already + * been filled up with entries. A call to this API would configure the register bit field GxASMR.LDEV. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanTriggerConversion(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanTriggerConversion:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_LDEV_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Aborts an ongoing scan sequence conversion.
\n + * An ongoing sequence can be aborted at any time. The scan unit picks the pending channels one by one from a + * pending register and requests for their conversion. This API essentially clears the channel pending register thus + * creating an illusion that there are no more channels left in the sequence. + * A call to this API would configure the registers GxASMR, GxASCTRL, GxARBPR to achieve the sequence abort. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ScanSequenceAbort(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num The channel meant to be added to scan sequence + *
Range: [0x0 to 0x7] + * @return + * None + * + * \parDescription:
+ * Adds a channel to the scan sequence.
\n + * Call this API to insert a new single channel into the scan request source. This will be added to the scan + * sequence. The added channel will be part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of GxASSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanAddMultipleChannels()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanAddChannelToSequence(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + XMC_ASSERT("VADC_GSCAN_AddSingleChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanAddChannelToSequence:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + group_ptr->ASSEL |= (uint32_t)((uint32_t)1 << ch_num); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_mask Mask word indicating channels which form part of scan conversion sequence + * Bit location 0/1/2/3/4/5/6/7 represents channels-0/1/2/3/4/5/6/7 respectively. + * To Add the channel to the scan sequence enable the respective bit. + * Passing a 0x0 will clear all the selected channels + *
Range: [0x0 to 0xFF] + * @return + * None + * + * \parDescription:
+ * Adds multiple channels to the scan sequence.
\n + * Call this API to insert a multiple channels into the scan request source. This will be added to a scan + * sequence. The added channels will be a part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of GxASSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanAddChannelToSequence()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanAddMultipleChannels(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_mask) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanAddMultipleChannels:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ASSEL = ch_mask; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num The channel being audited for completion of conversion + *
Range: [0x0 to 0x7] + * @return + * bool returns true if the channel is pending conversion else returns false + * + * \parDescription:
+ * Determine if the channel is pending for conversion.
\n + * This API will check if the Channel in question is awaiting conversion in the current arbitration round. + * When a load event occurs the scan sequence is pushed to a pending conversion register. + * From the pending register the channels are taken up by the converter. This API would return true + * if the channel is found in the pending register (GxASPND). + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanGetNumChannelsPending()
+ */ +__STATIC_INLINE bool XMC_VADC_GROUP_ScanIsChannelPending(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + + XMC_ASSERT("XMC_VADC_GROUP_ScanIsChannelPending:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanIsChannelPending:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + return( (bool)((uint32_t)(group_ptr->ASPND >> ch_num) & 1U)); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return
+ * uint32_t Returns the total channels pending for conversion. + *
Range: [0x0 to 0x8] + * + * \parDescription:
+ * Returns the total number of pending channels.
\n + * This API will read the pending channels register and will return the number of channels that are awaiting conversion. + * When a load event occurs the scan sequence is pushed to a pending conversion register. + * From the pending register the channels are taken up by the converter. When the API is called it would + * return the total number of channels pending (GxASPND). + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanIsChannelPending()
+ */ +uint32_t XMC_VADC_GROUP_ScanGetNumChannelsPending(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Manually asserts the conversion complete request source event.
\n + * This API will set the request source event for scan. This will trigger a interrupt if the + * service node pointer for the scan has been configured. + * A call to this API would configure the register bit field GxSEFLAG.SEV1. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanTriggerReqSrcEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanTriggerReqSrcEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->SEFLAG |= (uint32_t)VADC_G_SEFLAG_SEV1_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Acknowledges the scan conversion complete request source event.
\n + * This API will clear the request source event that occurred. This will clear a interrupt if it was raised. + * A call to this API would configure the register bit field GxSEFLAG.SEV1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanTriggerReqSrcEvent()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanClearReqSrcEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanClearReqSrcEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->SEFCLR |= (uint32_t)VADC_G_SEFCLR_SEV1_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * bool returns true if the service request event is raised. + * returns false if the service request event was not raised. + * + * \parDescription:
+ * Determines if the request source event is asserted.
+ * This API will get the status of the scan request source event. Will return a true + * if the event has occurred for scan. A call to this API would access the register bit field GxSEFLAG.SEV1. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE bool XMC_VADC_GROUP_ScanGetReqSrcEventStatus(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GSCAN_GetRSEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return( (bool)(group_ptr->SEFLAG & (uint32_t)VADC_G_SEFLAG_SEV1_Msk)); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param sr Service Request Id + * @return + * None + * + * \parDescription:
+ * Connects the scan request source event to the SR line of VADC.
\n + * This API will connect a Service Request line(SR) to a scan request source event. Hence to get a interrupt on this + * Service request line one has to enable the required NVIC node. A call to this API would configure the register bit + * field GxSEVNP.SEV1NP . + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SR_t sr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables the trigger for scan request source.
\n + * By using this API, the trigger signal will be activated for the scan request source. The trigger signal and trigger + * edge will be selected from the ASCTRL register. The Selection of a input will be done by + * XMC_VADC_GROUP_ScanSelectTrigger(). A call to this API would configure the register bit field GxASMR.ENTR. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanSelectTrigger()
XMC_VADC_GROUP_ScanDisableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanEnableExternalTrigger(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanEnableExternalTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_ENTR_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables the trigger for scan request source.
+ * By using this API the trigger will be deactivated for the scan request source. + * This will just deactivate the H/W trigger for the scan request source. If any configuration were done + * to select the trigger input in GxASCTRL, it will be not be effected by this API. + * A call to this API would configure the register bit field GxASMR.ENTR. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanDisableExternalTrigger(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanDisableExternalTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_ENTR_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param channel_num channel number to be removed from the scan sequence. + * @return + * None + * + * \parDescription:
+ * Removes a channel from the scan sequence.
+ * By using this API the it is possible to remove a single channel from the conversion sequence. + * The remaining channels will continue however they are. + * A call to this API would configure the register GxASSEL. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ScanRemoveChannel(XMC_VADC_GROUP_t *const group_ptr, const uint32_t channel_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables the scan request source event .
+ * By using this API the request source event will be activated for the scan request source. + * Other configurations w.r.t service node pointer are not done in this API. + * A call to this API would configure the register bit field GxASMR.ENSI. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanDisableEvent(),
XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanEnableEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanEnableEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->ASMR |= ((uint32_t)VADC_G_ASMR_ENSI_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables the scan request source event .
+ * By using this API the request source event will be deactivated for the scan request source. + * Other configurations w.r.t service node pointer are not done in this API. + * A call to this API would configure the register bit field GxASMR.ENSI. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ScanEnableEvent(),
XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ScanDisableEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ScanDisableEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_ENSI_Msk); +} +#endif + +/** + * @param global_ptr Pointer to the VADC module + * @param config Pointer to initialization data structure + * + * \parDescription:
+ * Initializes the Background scan functional block.
\n + * The BACKGROUND SCAN request source functional block converts channels of all VADC groups that have not + * been assigned as a priority channel (priority channels can be converted only by queue and scan). Background Scan + * request source converts the unprioritized channels. Unprioritized channels however can also be used with queue + * and scan. But a channel which is prioritized can not be used with background request source. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_BackgroundEnableArbitrationSlot()
XMC_VADC_GROUP_BackgroundDisableArbitrationSlot()
+ * XMC_VADC_GLOBAL_BackgroundSelectTrigger()
XMC_VADC_GLOBAL_BackgroundSelectGating()
+ */ +void XMC_VADC_GLOBAL_BackgroundInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_BACKGROUND_CONFIG_t *config); + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +/** + * @param group_ptr Constant pointer to the VADC group which may receive a + * conversion request from background request source + * + * @return + * None + * + * \parDescription:
+ * Enables arbitration slot of the Background request source.
\n + * If the Background request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the Background channel can only be converted when the arbiter + * comes to the Background slot. Thus this must be enabled if any conversion need to take place. + * A call to this API would configure the register bit field GxARBPR.ASEN2. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_BackgroundDisableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_BackgroundEnableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_BackgroundEnableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ARBPR |= (uint32_t)VADC_G_ARBPR_ASEN2_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group which may receive a conversion request + * from background request source + * @return + * None + * + * \parDescription:
+ * Disables arbitration slot of the Background request source.
\n + * If the Background request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the Background channel can only be converted when the arbiter + * comes to the Background slot.A call to this API will lead to all conversions request by Background to be blocked. + * A call to this API would configure the register bit field GxARBPR.ASEN2 + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_BackgroundEnableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_BackgroundDisableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_BackgroundDisableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->ARBPR &= ~((uint32_t)VADC_G_ARBPR_ASEN2_Msk); +} +#endif + +/** + * @param global_ptr Pointer to the VADC module + * @param input_num Choice of the input earmarked as a trigger line + * Accepts enum ::XMC_VADC_TRIGGER_INPUT_SELECT_t + * @return + * None + * + * \parDescription:
+ * Select Trigger signal for Background request source.
\n + * A Background request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 16 input lines as a trigger line. This is + * needed when a hardware trigger is needed for the conversion of the Background request source. + * Refer to the reference manual to determine the signal that needs to be connected. + * A call to this API would configure the register bit field BRSCTRL.XTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSelectGating()
XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger()
+ */ +void XMC_VADC_GLOBAL_BackgroundSelectTrigger(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t input_num); + + +/** + * @param global_ptr Pointer to the VADC module + * @param trigger_edge Select the trigger edge + * @return + * None + * + * \parDescription:
+ * Select Trigger edge for Background request source.
\n + * A Background request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 4 possible values for the trigger edge. This is + * needed when a hardware trigger is needed for the conversion of the Background request source. + * A call to this API would configure the register bit field BRSCTRL.XTMODE. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSelectGating()
XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger()
+ */ +void XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_TRIGGER_EDGE_t trigger_edge); + +/** + * @param global_ptr Pointer to the VADC module + * @param input_num Module input signal meant to be selected as gating input + * Accepts enum ::XMC_VADC_GATE_INPUT_SELECT_t + * @return + * None + * + * \parDescription:
+ * Select Gating signal for Background request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. Any one of the 16 input + * lines can be chosen as a gating signal. Trigger signal can be given to the Background request source only + * when the gating signal's active level is detected. Additionally the GxBRSMR.ENGT has to be configured for + * the gating signal's active level. A call to this API would configure the register bit field BRSCTRL.GTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSelectTrigger()
+ */ +void XMC_VADC_GLOBAL_BackgroundSelectGating(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t input_num); + +/** + * @param global_ptr Pointer to the VADC module + * @param mode_sel Select how the gating is applied to the background scan request source + * @return + * None + * + * Details of function
+ * Selects the gating mode of background request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. + * This API determines how the gating signal behaves, either active low or active high. + * If gating signal needs to ignored XMC_VADC_GATEMODE_IGNORE should be used as the \a mode_sel. + * A call to this API would configure the register bit field BRSMR.ENGT. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSelectGating(); + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundSetGatingMode(XMC_VADC_GLOBAL_t *const global_ptr, + XMC_VADC_GATEMODE_t mode_sel) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSetGatingMode:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSetGatingMode:Wrong mode selected", (mode_sel <= XMC_VADC_GATEMODE_ACTIVELOW)) + + /* Clear the existing gate configuration */ + global_ptr->BRSMR &= (uint32_t)(~((uint32_t)VADC_BRSMR_ENGT_Msk)); + /* Configure the new gating mode*/ + global_ptr->BRSMR |= (uint32_t)((uint32_t)mode_sel << VADC_BRSMR_ENGT_Pos); +} + + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Enables continuous conversion mode.
\n + * Typically for a Background request source to generate conversion request, either a hardware trigger or a software + * request is needed. Using autoscan (continuous conversion)feature it is possible to start the conversion + * once and allow the sequence to repeat without any further triggers. Once all channels belonging to a Background + * request source have been converted, a request source completion event is generated. Generation of this event + * can restart the Background configure sequence. Every request source event will cause a load event to occur. + * A call to this API would access the register bit field BRSMR.SCAN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_BackgroundDisableContinuousMode()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundEnableContinuousMode(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundEnableContinuousMode:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_SCAN_Msk; +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Disables continuous conversion mode.
\n + * Typically for a Background request source to generate conversion request, either a hardware trigger or a software + * request is a pre-requisite. Using autoscan feature it is possible to start the conversion once and allow the + * sequence to repeat without any further triggers. Once all channels belonging to a Background request source have + * been converted, a request source completion event is generated. Generation of this event can restart the Background + * sequence. By invoking this API the Autoscan mode of operations is disabled. A call to this API would configure the + * register bit field BRSMR.SCAN. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundEnableContinuousMode()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundDisableContinuousMode(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundDisableContinuousMode:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->BRSMR &= ~((uint32_t)VADC_BRSMR_SCAN_Msk); +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Generates conversion request (Software initiated conversion).
\n + * A conversion request can be raised either upon detection of a hardware trigger, or by software. This API forces + * the scan unit to generate a conversion request to the analog converter. It is assumed that the background scan + * has already been filled up with entries. A call to this API would set the register bit field BRSMR.LDEV. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundTriggerConversion(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundTriggerConversion:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_LDEV_Msk; +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Aborts an ongoing background scan conversion(sequence).
\n + * An ongoing sequence can be aborted at any time. The scan unit picks the pending channels one by one from a + * pending register and requests for their conversion. This API essentially clears the channel pending register thus + * creating an illusion that there are no more channels left in the sequence. + * A call to this API would configure the registers BRSMR, BRSCTRL, GxARBPR(if group is available) to abort the + * current scan sequence. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GLOBAL_BackgroundAbortSequence(XMC_VADC_GLOBAL_t *const global_ptr); + +/** + * @param global_ptr Pointer to the VADC module + * @param grp_num ID of the VADC group whose unprioritized channels have been assigned to background scan + * Request source + * @param ch_num The unprioritized channel meant to be added to the scan sequence + *
Range: [0x0 to 0x7] + * @return + * None + * + * \parDescription:
+ * Adds a channel to the background scan sequence.
\n + * Call this API to insert a new single channel into the background scan request source. This will be added to the scan + * sequence. The added channel will be part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of BRSSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundAddMultipleChannels()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundAddChannelToSequence(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t grp_num, + const uint32_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Group Number",((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + global_ptr->BRSSEL[grp_num] |= (uint32_t)((uint32_t)1 << ch_num); +} + +/** + * @param global_ptr Pointer to the VADC module + * @param grp_num ID of the VADC group whose unprioritized channels have been assigned to background scan + * @param ch_mask Mask word indicating channels which form part of scan conversion sequence + * Bit location 0/1/2/3/4/5/6/7 represents channels-0/1/2/3/4/5/6/7 respectively. + * To Add the channel to the scan sequence enable the respective bit. + * Passing a 0x0 will clear all the previously selected channels + *
Range: [0x0 to 0xFF] + * @return + * None + * + * \parDescription:
+ * Adds multiple channels to the scan sequence.
\n + * Call this API to insert a multiple channels into the scan request source. This will be added to a scan + * sequence. The added channels will be a part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of BRSSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgndAddMultipleChannels(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t grp_num, + const uint32_t ch_mask) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Group Number", ((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + global_ptr->BRSSEL[grp_num] |= ch_mask; +} + +/** + * @param global_ptr Pointer to the VADC module + * @param grp_num ID of the VADC group whose unprioritized channels have been assigned to background scan + * Request source + * @param ch_num The unprioritized channel meant to be added to the scan sequence + *
Range: [0x0 to 0x7] + * @return + * None + * + * \parDescription:
+ * Removes a channel to the background scan sequence.
\n + * Call this API to insert a new single channel into the background scan request source. This will be added to the scan + * sequence. The added channel will be part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of BRSSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t grp_num, + const uint32_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Group Number",((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + global_ptr->BRSSEL[grp_num] &= (uint32_t)~((uint32_t)1 << ch_num); +} + +/** + * @param global_ptr Pointer to the VADC module + * @param grp_num ID of the VADC group whose unprioritized channels have been assigned to background scan + * @param ch_mask Mask word indicating channels which form part of scan conversion sequence + * Bit location 0/1/2/3/4/5/6/7 represents channels-0/1/2/3/4/5/6/7 respectively. + * To Add the channel to the scan sequence enable the respective bit. + * Passing a 0x0 will clear all the previously selected channels + *
Range: [0x0 to 0xFF] + * @return + * None + * + * \parDescription:
+ * Removes multiple channels to the scan sequence.
\n + * Call this API to insert a multiple channels into the scan request source. This will be added to a scan + * sequence. The added channels will be a part of the conversion sequence when the next load event occurs. + * A call to this API would configure the register bit fields of BRSSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t grp_num, + const uint32_t ch_mask) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Group Number", ((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + global_ptr->BRSSEL[grp_num] &= (uint32_t)~ch_mask; +} + +/** + * @param global_ptr Pointer to the VADC module + * @param grp_num ID of the VADC group whose unprioritized channels have been assigned to background scan RS + * @param ch_num The channel being audited for completion of conversion + *
Range: [0x0 to 0x7] + * @return + * bool returns true if the channel is pending conversion else returns false + * + * \parDescription:
+ * Determine if the channel is pending.
\n + * This API will check if the Channel in question is awaiting conversion in the current arbitration round. + * When a load event occurs the scan sequence is pushed to a pending conversion register. + * From the pending register the channels are taken up by the converter. This API would return true + * if the channel is found in the pending register (BRSPND[\b grp_num]). + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending()
+ */ +__STATIC_INLINE bool XMC_VADC_GLOBAL_BackgroundIsChannelPending(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t grp_num, + const uint32_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundIsChannelPending:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundIsChannelPending:Wrong Group Number", ((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundIsChannelPending:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + return( (bool)(global_ptr->BRSPND[grp_num] & (uint32_t)((uint32_t)1 << ch_num))); +} + +/** + * @param global_ptr Pointer to the VADC module + * @return
+ * uint32_t Returns the total channels pending for conversion. + *
Range: [0x0 to (0x8*number of groups)] + * + * \parDescription:
+ * Returns the number of pending channels.
\n + * This API will read the pending channels register and will return the number of channels that are awaiting conversion. + * When a load event occurs the scan sequence is pushed to a pending conversion register. + * From the pending register the channels are taken up by the converter. When the API is called it would + * return the total number of channels pending (BRSPND[\b grp_num]). + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundIsChannelPending()
+ */ +uint32_t XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending(XMC_VADC_GLOBAL_t *const global_ptr); + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Manually asserts the conversion complete request source event.
\n + * This API will set the request source event for background scan. This will trigger a interrupt if the + * service node pointer for the scan has been configured. + * A call to this API would configure the register bit field GLOBEFLAG.SEVGLB. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundTriggerReqSrcEvent(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundTriggerReqSrcEvent:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->GLOBEFLAG |= (uint32_t)VADC_GLOBEFLAG_SEVGLB_Msk; +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Acknowledges the background scan conversion complete request source event.
\n + * This API will clear the request source event that occurred. This will clear a interrupt if it was raised. + * A call to this API would configure the register bit field GLOBEFLAG.SEVGLB + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundTriggerReqSrcEvent()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundClearReqSrcEvent(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundClearReqSrcEvent:Wrong Module Pointer", (global_ptr == VADC)) + global_ptr->GLOBEFLAG |= (uint32_t)VADC_GLOBEFLAG_SEVGLBCLR_Msk; +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * bool returns true if the service request event is raised. + * returns false if the service request event was not raised. + * + * \parDescription:
+ * Determines if the request source event is asserted.
+ * This API will get the status of the background scan request source event. Will return a true + * if the event has occurred for background scan. A call to this API would configure the register + * bit field GLOBEFLAG.SEVGLB. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE bool XMC_VADC_GLOBAL_BackgroundGetReqSrcEventStatus(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundGetReqSrcEventStatus:Wrong Module Pointer", (global_ptr == VADC)) + return((bool)(global_ptr->GLOBEFLAG & (uint32_t)VADC_GLOBEFLAG_SEVGLB_Msk)); +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Enables the trigger for background scan request source.
\n + * By using this API the trigger will be activated for the scan request source. The trigger signal and trigger + * edge will be selected from the BRSCTRL register. The Selection of a input will be done by + * XMC_VADC_GLOBAL_BackgroundSelectTrigger(). A call to this API would configure the register bit field BRSMR.ENTR. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundSelectTrigger()
XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_ENTR_Msk; +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Disables the trigger for background scan request source.
+ * By using this API the trigger will be deactivated for the background scan request source. + * This will just deactivate the H/W trigger for the background scan request source. If any configuration was done + * to select the trigger input in BRSCTRL will be not be effected. A call to this API would configure the register + * bit field BRSMR.ENTR. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->BRSMR &= ~((uint32_t)VADC_BRSMR_ENTR_Msk); +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Enables the background scan request source event .
+ * By using this API the request source event will be activated for the background scan request source. + * Other configurations w.r.t service node pointer are not done in this API. + * A call to this API would configure the register bit field BRSMR.ENSI. + * + * \parRelated APIs:
+ * XMC_VADC_GLOBAL_BackgroundEnableEvent(),
XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundEnableEvent(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundEnableEvent:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->BRSMR |= ((uint32_t)VADC_BRSMR_ENSI_Msk); +} + +/** + * @param global_ptr Pointer to the VADC module + * @return + * None + * + * \parDescription:
+ * Disables the background scan request source event .
+ * By using this API the request source event will be deactivated for the background scan request source. + * Other configurations w.r.t service node pointer are not done in this API. + * A call to this API would configure the register bit field BRSMR.ENSI. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_BackgroundEnableEvent(),
XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode()
+ */ +__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundDisableEvent(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundDisableEvent:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->BRSMR &= ~((uint32_t)VADC_BRSMR_ENSI_Msk); +} + +#if (XMC_VADC_QUEUE_AVAILABLE == 1U) +/** + * @param group_ptr Pointer to the VADC group + * @param config Pointer to initialization data structure + * @return + * None + * + * \parDescription:
+ * Initializes VADC QUEUE functional block.
\n + * The QUEUE request source functional block converts channels stored in a queue. The first channel entered into the + * queue is converted first. A channel once converted, can be placed back into the queue if desired(refill). + * A call to this API will first disable the arbitration slot for queue (XMC_VADC_GROUP_QueueEnableArbitrationSlot()) + * and then it would configure all the related registers with the required configuration values. + * The arbitration slot is re-enabled at the end of init by invoking XMC_VADC_GROUP_QueueDisableArbitrationSlot(). + * A call to this API would configure the registers GxARBPR, GxQCTRL0, GxQMR0 to configure the queue request + * source. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueEnableArbitrationSlot()
XMC_VADC_GROUP_QueueDisableArbitrationSlot()
+ * XMC_VADC_GROUP_QueueSelectTrigger()
XMC_VADC_GROUP_QueueSelectGating()
+ */ +void XMC_VADC_GROUP_QueueInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_QUEUE_CONFIG_t *config); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables arbitration slot of the queue request source.
\n + * If the QUEUE request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the queue channel can only be converted when the arbiter comes + * to the queue slot. Thus this must be enabled if any conversion need to take place. + * A call to this API would configure the register bit field GxARBPR.ASEN0. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueDisableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueEnableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueEnableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)); + group_ptr->ARBPR |= (uint32_t)((uint32_t)1 << VADC_G_ARBPR_ASEN0_Pos); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables arbitration slot of the queue request source.
\n + * If the QUEUE request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the queue channel can only be converted when the arbiter comes + * to the queue slot.A call to this API will lead to all conversions request by queue to be blocked. + * A call to this API would configure the register bit field GxARBPR.ASEN0. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueEnableArbitrationSlot()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueDisableArbitrationSlot(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueDisableArbitrationSlot:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)); + group_ptr->ARBPR &= ~((uint32_t)VADC_G_ARBPR_ASEN0_Msk); +} + + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * bool returns true if the arbitration is enabled else returns false. + * + * \parDescription:
+ * Returns the arbitration status of the queue request source.
\n + * If the queue request source must have its conversion request considered by the arbiter, it must participate in + * the arbitration rounds. Even if a load event occurs the queue channel can only be converted when the arbiter comes + * to the queue slot. A call to this API would return the status of the arbitration slot of queue. + * A call to this API would read the register bit field GxARBPR.ASEN1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueEnableArbitrationSlot(),
XMC_VADC_GROUP_QueueDisableArbitrationSlot()
+ */ +__STATIC_INLINE bool XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + return ((group_ptr->ARBPR & (uint32_t)VADC_G_ARBPR_ASEN0_Msk) >> VADC_G_ARBPR_ASEN0_Pos); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param input_num Choice of the input earmarked as a trigger line + * @return + * None + * + * \parDescription:
+ * Select Trigger signal for queue request source.
\n + * A queue request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 16 input lines as a trigger line. This is + * needed when a hardware trigger is needed for the conversion of the queue request source. + * Refer to the reference manual to determine the signal that needs to be connected. + * A call to this API would configure the register bit field GxQCTRL0.XTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueSelectGating()
XMC_VADC_GROUP_QueueEnableExternalTrigger()
+ */ +void XMC_VADC_GROUP_QueueSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_TRIGGER_INPUT_SELECT_t input_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param trigger_edge Choice of the trigger edge + * @return + * None + * + * \parDescription:
+ * Select Trigger signal edge for queue request source.
\n + * A queue request source will raise conversion request only if there were either a request from application or + * occurrence of a hardware trigger. This API selects one of the 4 trigger edges. This is + * needed when a hardware trigger is needed for the conversion of the queue request source. + * Refer to the reference manual to determine the signal that needs to be connected. + * A call to this API would configure the register bit field GxQCTRL0.XTMODE. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueSelectGating()
XMC_VADC_GROUP_QueueEnableExternalTrigger()
+ */ +void XMC_VADC_GROUP_QueueSelectTriggerEdge(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_TRIGGER_EDGE_t trigger_edge); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param input_num Choice of the input earmarked as the gating line + * @return + * None + * + * \parDescription:
+ * Select Gating signal for queue request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. Any one of the 16 input + * lines can be chosen as a gating signal. Trigger signal can be given to the queue request source only + * when the gating signal's active level is detected. Additionally the GxQMR0.ENGT has to be configured for + * the gating signal's active level. A call to this API would configure the register bit field GxQCTRL0.GTSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueSelectTrigger()
+ */ +void XMC_VADC_GROUP_QueueSelectGating(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GATE_INPUT_SELECT_t input_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param mode_sel Select how the gating is applied to the queue request source + * @return + * None + * + * Details of function
+ * Selects the gating mode of queue request source.
\n + * Passage of the trigger input to the request source can be controlled via a gating signal. + * This API determines how the gating signal behaves, either active low or active high. + * If gating signal needs to ignored XMC_VADC_GATEMODE_IGNORE should be used as the \a mode_sel. + * A call to this API would configure the register bit field GxQMR0.ENGT. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueSelectGating(); + */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueSetGatingMode(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_GATEMODE_t mode_sel) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueSetGatingMode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSetGatingMode:Wrong mode selected", (mode_sel <= XMC_VADC_GATEMODE_ACTIVELOW)) + + /* Clear the existing gate configuration */ + group_ptr->QMR0 &= (uint32_t)(~((uint32_t) VADC_G_QMR0_ENGT_Msk)); + /* Set the new gating mode */ + group_ptr->QMR0 |= (uint32_t)((uint32_t)mode_sel << VADC_G_QMR0_ENGT_Pos); +} + + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Generates conversion request (Software initiated conversion).
+ * A conversion request can be raised either upon detection of a hardware trigger, or by software. This API forces + * the queue unit to generate a conversion request to the analog converter. It is assumed that the queue has already + * been filled up with entries. A call to this API would configure the register bit field GxQMR0.TREV. + * + * \parNote:
+ * The conversion of queue entry will start immediately after the entry has been loaded into GxQINR0. + * This happens only if the queue entry has been loaded into the register without the need for the H/W trigger.\n + * If a H/W Trigger is selected while loading the entry, the conversion will occur in one of the 2 ways: + *
    + *
  • The H/W generates a trigger needed for the queue request source. + *
  • The Conversion is triggered manually by calling this API. + *
+ * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueInsertChannel()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueTriggerConversion(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueTriggerConversion:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->QMR0 |= (uint32_t)((uint32_t)1 << VADC_G_QMR0_TREV_Pos); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * uint32_t returns the total number of channels. + *
Range: [0x0 to 0x8] + * + * \parDescription:
+ * Returns the number of channels present in the queue.
\n + * This API will return the queue buffer size. This buffer will be consisting of valid queue entries which + * will be converted when a trigger event occurs. All the entries that are loaded onto the GxQINR0 will + * be added to the queue buffer. Hence if an application needs to get the number of valid queue entries + * this API would provide the interface. A call to this API would access the registers GxQBUR0, GxQSR0 in order + * to determine the queue length. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueInsertChannel()
+ */ +uint32_t XMC_VADC_GROUP_QueueGetLength(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Aborts an ongoing conversion by flushing the queue.
\n + * This API will flush the queue buffer. Ongoing conversion of the Queue request source will + * not be effected by this API. This would clear all the contents that are present in the queue buffer. + * A call to this API would configure the registers GxQCTRL0, GxQMR0, GxARBPR in order to abort + * the queue sequence. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueRemoveChannel()
XMC_VADC_GROUP_QueueFlushEntries()
+ */ +void XMC_VADC_GROUP_QueueAbortSequence(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Flushing the queue Entry.
\n + * This API will flush one entry in the queue buffer. Ongoing conversion of the Queue request source will + * not be effected by this API. This would clear all the contents that are present in the queue buffer. + * A call to this API would configure the registers GxQMR0. This is a Blocking API, i.e will only exit when + * all the entries are removed from the queue. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueRemoveChannel()
XMC_VADC_GROUP_QueueAbortSequence(0
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueFlushEntries(XMC_VADC_GROUP_t *const group_ptr) +{ + /* Initiate flushing of the queue */ + group_ptr->QMR0 |= (uint32_t)VADC_G_QMR0_FLUSH_Msk; + + while( !((group_ptr->QSR0)& (uint32_t)VADC_G_QSR0_EMPTY_Msk)) + { + /* Wait until the queue is indeed flushed */ + } +} + + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Clears the next valid channel in the queue buffer.
\n + * A queue entry lined up for conversion can be removed and replaced by its successor. The call to this API will + * first check if a valid queue entry is present in the queue backup register if present would clear its valid flag. + * If no valid queue entries are present in the backup then the first channel + * present in the queue buffer would be cleared. + * A call to this API would configure the registers GxQCTRL0, GxQMR0, GxARBPR in order to clear a + * channel from the queue. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueInsertChannel()
+ */ +void XMC_VADC_GROUP_QueueRemoveChannel(XMC_VADC_GROUP_t *const group_ptr); + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param entry Details of the node being added + * @return + * None + * + * \parDescription:
+ * Inserts a queue entry to the tail of the queue buffer.
\n + * This API will insert a new channel into the queue buffer. The Queue will start conversion of + * the channels from the head of the buffer. This Insert will place the entry after the last valid entry. + * If no valid entries are present then this API will place the Queue entry at the head of the buffer. + * Then the successive call to the insert will place the new entry after the last entry. + * A call to this API would configure the register GxQINR0 for a single queue entry. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueRemoveChannel()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueInsertChannel(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_QUEUE_ENTRY_t entry) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueInsertChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + /* Insert the channel physically and get the length of the queue*/ + group_ptr->QINR0 = entry.qinr0; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * int32_t Returns -1 if there are no channels for conversion + * Else would return the next valid channel for conversion. + *
Range: [0x0 to 0x8] + * + * \parDescription:
+ * Returns the next entry in the queue request source for conversion.
\n + * Identifies the channel in the queue lined up for conversion next. + * API will return a valid queue entry from the queue buffer. First checks for the valid channel entry + * in the backup register and returns if present. If the valid entry has not been found in the backup register + * then the queue buffer is searched for a valid entry. A call to this API would access the registers GxQ0R0, + * GxQBUR0 to determine the next channel. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueRemoveChannel()
XMC_VADC_GROUP_QueueInsertChannel()
+ */ +int32_t XMC_VADC_GROUP_QueueGetNextChannel(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * int32_t Returns -1 if there is no channel that have been interrupted. + * Else would return the channel that is interrupted. + *
Range: [0x0 to 0x8] + * + * \parDescription:
+ * Identifies the channel whose conversion was suspended.
\n + * When using cancel inject repeat mode the canceled conversion will be placed in the backup register. + * This API will return the valid queue channel number from the backup register. This happens when ever + * there is a high priority conversion interrupts the conversion of queue request source. This forces the channel + * to goto the backup register. A call to this API would access the register GxQBUR0 to determine the + * interrupted channel. + * + * \parRelated APIs:
+ * None. + */ +int32_t XMC_VADC_GROUP_QueueGetInterruptedChannel(XMC_VADC_GROUP_t *const group_ptr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Manually asserts the conversion complete request source event.
\n + * This API will set the request source event for queue. This will trigger a interrupt if the + * service node pointer for the scan has been configured. + * A call to this API would configure the register bit field GxSEFLAG.SEV0. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueClearReqSrcEvent()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueTriggerReqSrcEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueTriggerReqSrcEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->SEFLAG |= 1U; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Acknowledges the conversion complete request source event.
\n + * This API will clear the request source event that occurred. This will clear a interrupt if it was raised. + * A call to this API would configure the register bit field GxSEFCLR.SEV0. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueTriggerReqSrcEvent()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueClearReqSrcEvent(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueClearReqSrcEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->SEFCLR = (uint32_t)VADC_G_SEFCLR_SEV0_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * bool returns true if the service request event is raised. + * returns false if the service request event was not raised. + * + * \parDescription:
+ * Determines if the request source event is asserted.
+ * This API will get the status of the queue request source event. Will return a true + * if the event has occurred for queue. A call to this API would acces the register bit field GxSEFLAG.SEV0. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE bool XMC_VADC_GROUP_QueueGetReqSrcEventStatus(XMC_VADC_GROUP_t *const group_ptr) +{ + + XMC_ASSERT("XMC_VADC_GROUP_QueueGetReqSrcEventStatus:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return(group_ptr->SEFLAG & (uint32_t)VADC_G_SEFLAG_SEV0_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param sr The service request line (Common SR lines, Group specific SR lines) + * @return + * None + * + * \parDescription:
+ * Connects the event to the SR line of VADC.
\n + * This API will connect a Service Request line(SR) to a queue request source event. Hence to get a interrupt on this + * Service request line one has to enable the required NVIC node. A call to this API would configure the register + * bit field GxSEVNP.SEVNP0. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SR_t sr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Enables the trigger for queue request source.
\n + * By using this API the trigger will be activated for the queue request source. The trigger signal and trigger + * edge will be selected from the QCTRL register. The Selection of a input will be done by + * XMC_VADC_GROUP_QueueSelectTrigger(). A call to this API would configure the register bit field GxQMR0.ENTR + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueSelectTrigger()
XMC_VADC_GROUP_QueueDisableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueEnableExternalTrigger(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueEnableExternalTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->QMR0 |= (uint32_t)VADC_G_QMR0_ENTR_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Disables the trigger for queue request source.
+ * By using this API the trigger will be deactivated for the queue request source. + * This will just deactivate the H/W trigger for the queue request source. If any configuration was done + * to select the trigger input in GxQCTRL0 will be not be effected. A call to this API would configure the + * register bit field GxQMR0.ENTR + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_QueueEnableExternalTrigger()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_QueueDisableExternalTrigger(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_QueueDisableExternalTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + group_ptr->QMR0 &= ~((uint32_t)VADC_G_QMR0_ENTR_Msk); +} +#endif + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num The channel being initialized + *
Range: [0x0 to 0x7] + * @param config Pointer to initialization data + * @return + * None + * + * \parDescription:
+ * Initializes the ADC channel for conversion.
\n + * This API will do the channel related initializations. This includes configuration of the CHCTR settings + * and boundary flag settings. This must be called in the application in order to enable the conversion of + * a channel. After a request source has been initialized this API has to be called for each channel that + * has to be converted. A call to this API would configure the registers GxCHCTR GxBFL GxALIAS GxCHASS + * GxBFLC(depending on device) in order to configure the channel. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ChannelInit(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num, + const XMC_VADC_CHANNEL_CONFIG_t *config); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param src_ch_num Channel which will be converted by \b alias_ch_num, when called by the request source. + *
Range:[0x0 to 0x7] + * @param alias_ch_num This is the alias channel (Ch-0 or Ch-1) + *
Range:[0x0, 0x1] + * @return + * None + * + * \parDescription:
+ * Sets the Alias channel(\b alias_ch_num) to convert from the source channel(\b src_ch_num).
\n + * When a alias configuration takes place the request source(queue/scan/background) will not call channel \b src_ch_num. + * The Request sources will call the channel \b alias_ch_num , this would invoke the conversion of + * the pin associated with \b src_ch_num. The configuration of the alias channel (\b alias_ch_num) will be used + * for the conversion.\n + * When an alias channel (Ch-0 or Ch-1) receives a trigger, it converts the aliased channel (\b src_ch_num). + * The properties of Ch-0 or Ch-1 (as indicated in \b alias_ch_num ) apply when \b src_ch_num is converted. + * A call to this API would configure the register GxALIAS. + * + * \parNote:
+ * Alias Channel (\b alias_ch_num) and the source channel (\b src_ch_num) cannot be the same. + * If they are, that alias feature is not used for the conversion. In order to Reset the alias + * feature that was previously selected this method can be used. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_SetChannelAlias(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t src_ch_num, + const uint32_t alias_ch_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose input was converted + *
Range: [0x0 to 0x7] + * @return + * bool Returns true if there was violation w.r.t the specified boundaries. + * + * \parDescription:
+ * Determines if the result of the channel confines with the specified boundaries.
\n + * An application may not necessarily always need to know the exact value of the converted result, but merely + * an indication if the generated result is within stipulated boundaries. Generation of Channel event can be subject + * to channel event generation criteria (Generate always, Never generate, Generate if result is out of bounds, + * Generate if result is within bounds). When interrupts are not enabled, this API can be used to determine the + * nature of the result. A call to this API would access the registers GxCHCTR and GxCEFLAG in order to determine + * if a violation has occured. + * + * \parRelated APIs:
+ * None + */ +bool XMC_VADC_GROUP_ChannelIsResultOutOfBounds(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose input is to be converted + *
Range: [0x0 to 0x7] + * @param ref Reference voltage + * @return + * None + * + * \parDescription:
+ * Selects the reference voltage for conversion.
\n + * An internal voltage reference (VARef) or an external voltage reference fed to Ch-0 can serve as a voltage reference + * for conversions. A call to this API would configure the register bit field GxCHCTR.REFSEL. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ChannelSetInputReference(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num, + const XMC_VADC_CHANNEL_REF_t ref); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose i/p is to be converted + *
Range: [0x0 to 0x7] + * @param result_reg_num Result Register associated with this channel + * @return + * None + * + * \parDescription:
+ * Selects the target result register.
\n + * There are upto 16 result registers which a channel can choose from to store the results of conversion. + * This selects only the group related result registers. A call to this API would configure the register + * bit field GxCHCTR.RESREG. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ChannelSetResultRegister(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const uint32_t result_reg_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose conversion class is to be configured + *
Range: [0x0 to 0x7] + * @param conversion_class conversion property to be associated with this channel + * @return + * None + * + * \parDescription:
+ * Selects the conversion class registers.
\n + * It configures the channel to have a particular conversion class properties like sampling + * time and resolution. A call to this API would configure the register + * bit field GxCHCTR.ICLSEL. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelGetInputClass(). + */ +void XMC_VADC_GROUP_ChannelSetIclass(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_CHANNEL_CONV_t conversion_class); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose result alignment is to be returned + *
Range: [0x0 to 0x7] + * @return + * XMC_VADC_RESULT_ALIGN_LEFT if the result are aligned to the left + * XMC_VADC_RESULT_ALIGN_RIGHT if the result are aligned to the right + * + * \parDescription:
+ * Returns the channel result alignment.
\n + * The results are aligned either to the left or to the right. A left aligned 10bit resolution has its LSB + * at bit2 where as a left aligned 8bit resolution starts at bit4. A call to this API would return the currently + * configured alignment value. + * A call to this API would read the register bit field GxCHCTR.RESPOS. + * + * \parRelated APIs:
+ * None. + */ +__STATIC_INLINE XMC_VADC_RESULT_ALIGN_t XMC_VADC_GROUP_ChannelGetResultAlignment(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetResultAlignment:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetResultAlignment:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + return ((XMC_VADC_RESULT_ALIGN_t)((group_ptr->CHCTR[ch_num] & (uint32_t)VADC_G_CHCTR_RESPOS_Msk) >> + (uint32_t)VADC_G_CHCTR_RESPOS_Pos) ); +} + + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose result alignment is to be returned + *
Range: [0x0 to 0x7] + * @return + * XMC_VADC_CHANNEL_CONV_t Returns the configured input class for the \b ch_num + * + * \parDescription:
+ * Returns the channel's input class for conversion for the required channel.
\n + * The sampling time and resolution can be taken from any of the 4 possible Input class registers. + * This API would return the input class register that is taken up by \b ch_num for conversion. + * A call to this API would read the register bit field GxCHCTR.RESPOS. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelSetIclass(). + */ +__STATIC_INLINE XMC_VADC_CHANNEL_CONV_t XMC_VADC_GROUP_ChannelGetInputClass(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetInputClass:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetInputClass:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + return ((XMC_VADC_CHANNEL_CONV_t)((group_ptr->CHCTR[ch_num] & (uint32_t)VADC_G_CHCTR_ICLSEL_Msk) >> + (uint32_t)VADC_G_CHCTR_ICLSEL_Pos) ); +} + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose associated result register is to be found + *
Range: [0x0 to 0x7] + * @return + * uint8_t returns the Group result register to which it is linked to. + *
Range: [0x0 to 0xF] + * + * \parDescription:
+ * Returns the result register associated with this channel.
\n + * There are upto 16 result registers which a channel can choose from to store the results of conversion. + * This returns only the group related result registers. A call to this API would access the register + * bit field GxCHCTR.RESREG. + * + * \parRelated APIs:
+ * None. + */ +uint8_t XMC_VADC_GROUP_ChannelGetResultRegister(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose channel event is to be asserted + *
Range: [0x0 to 0x7] + * @return + * None + * + * \parDescription:
+ * Manually asserts a Channel event.
\n + * It is merely the channel event which is asserted. For this asserted event to lead to an interrupt, it must + * have been bound to an SR and that SR must have been enabled. It can potentially lead to an interrupt if the + * SR line is connected to an NVIC node. A call to this API would configure the register bit fields of GxCEFLAG. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelClearEvent(). + */ +void XMC_VADC_GROUP_ChannelTriggerEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num); + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * uint32_t returns the asserted channel events + * + * \parDescription:
+ * Returns the Channel event flag register.
\n + * The return is merely the channel events which are asserted. + * A call to this API would read the register bit fields of GxCEFLAG. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelClearEvent(). + */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_ChannelGetAssertedEvents(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetAssertedEvents:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return(group_ptr->CEFLAG); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose channel event is to be acknowledged + *
Range: [0x0 to 0x7] + * @return + * None + * + * \parDescription:
+ * Acknowledges a Channel event.
\n + * When a channel event is raised after the conversion of that channel, it has to be cleared. This API would clear + * the Channel event of a particular channel if it has occurred. A call to this API would configure the register + * bit fields of GxCEFCLR. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelTriggerEvent(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_ChannelClearEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + + XMC_ASSERT("XMC_VADC_GROUP_ChannelClearEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelClearEvent:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + group_ptr->CEFCLR = (uint32_t)((uint32_t)1 << ch_num); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose channel event is to be connected to a service request line + *
Range: [0x0 to 0x7] + * @param sr The service request line to which the channel event is to be connected + * @return + * None + * + * \parDescription:
+ * Binds a channel event to a requested Service Request line.
\n + * The channel event is connected to a service request line. For an event to result in an interrupt, this service + * request line must be enabled in VADC and the NVIC node which this service request line is connected to must have + * interrupt generation enabled. A call to this API would configure the register bit fields of GxCEVNP0. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelTriggerEvent()
XMC_VADC_GROUP_ChannelClearEvent() + */ +void XMC_VADC_GROUP_ChannelSetEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_SR_t sr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose channel event is being configured + *
Range: [0x0 to 0x7] + * @param criteria The condition under which the channel may assert its channel event + * @return + * None + * + * \parDescription:
+ * Defines the conditions under which a channel may assert its channel event.
\n + * The channel event can be generated under the following conditions - Always, Never, Result Out of bounds and Result + * inside the boundaries. A call to this API would configure the register bit field GxCHCTR.CHEVMODE. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelTriggerEvent()
XMC_VADC_GROUP_ChannelClearEvent()
+ * XMC_VADC_GROUP_ChannelSetEventInterruptNode()
+ */ +void XMC_VADC_GROUP_ChannelTriggerEventGenCriteria(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_CHANNEL_EVGEN_t criteria); + + +/** + * @param group_ptr Constant pointer to the VADC group + * @param ch_num Channel whose channel event is being configured + *
Range: [0x0 to 0x7] + * @param boundary_sel Select the upper/lower boundary configuration . + * @param selection The boundary value selected for \b boundary_sel. + * @return + * None + * + * \parDescription:
+ * Configure the boundary selection for the given channel
\n + * The channel event can be generated under the following conditions - Always, Never, Result Out of bounds and Result + * inside the boundaries. The boundary values to which results are compared can be selected from several sources. + * A call to this API would configure the register bit field GxCHCTR.BNDSELL or GxCHCTR.BNDSELU . + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_ChannelSetBoundarySelection(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + XMC_VADC_BOUNDARY_SELECT_t boundary_sel, + XMC_VADC_CHANNEL_BOUNDARY_t selection); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg_num Result register which is intended to be initialized + *
Range: [0x0 to 0xF] + * @param config Pointer to initialization data + * @return + * None + * + * \parDescription:
+ * Initializes a Group Result Register.
+ * Various options needed for the working of the result result will be configured with this API. + * This would determine the result handling of the group registers. This API must be called after + * the channel Init (XMC_VADC_GROUP_ChannelInit())to initialize the result register that is selected for the channel. + * This API would also determine if the result register that is being configured has to a part of a FIFO buffer. + * In this API one can also configure the various result handling options line FIR/IIR filters and it order. + * Also configures the Data reduction to accumulate 2/3/4 results need to be done. This API will also configure + * the result event generation. A call to this API would configure the register GxRCR with the \b config . + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_AddResultToFifo()
XMC_VADC_GROUP_EnableResultEvent()
XMC_VADC_GROUP_DisableResultEvent()
+ */ +__STATIC_INLINE void XMC_VADC_GROUP_ResultInit(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg_num, + const XMC_VADC_RESULT_CONFIG_t *config) +{ + XMC_ASSERT("XMC_VADC_GROUP_ResultInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->RCR[res_reg_num] = config->g_rcr; + +} + + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Register which is required to be a part of results FIFO + *
Range: [0x0 to 0xF] + * @return + * None + * + * \parDescription:
+ * Adds result register to Result FIFO.
\n + * Sometimes, the rate of consumption of results by application software may not match the rate at which the + * results are produced. A Result FIFO thus helps a slow consumer to read out results without loss of data. + * When a result register is added to fifo, it is in fact chained to its higher numbered neighbor. For example, if + * Result Register-5 is to be added to FIFO, it gets chained to Result Register-6. Results are written to Register-6 + * while the same can be read out of Register-5 leisurely by software. + * A call to this API would configure the register bit field GxRCR.FEN. + * + * \parNote:
+ * The FIFO is always read by the software with the lowest numbered result register. + * The hardware will write the results from the highest numbered result register. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_AddResultToFifo(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which event generation is to be enabled + *
Range: [0x0 to 0xF] + * @return + * None + * + * \parDescription:
+ * Enables result event generation.
\n + * Once the results of conversion are available, the result event (which is being enabled in this function) + * if connected to a service request line(Group or Shared service request) can lead to an interrupt. It is therefore + * not only necessary to enable the event, but also to connect it to a service request line. The + * service request generation capability must also be enabled and so should the corresponding NVIC node. + * A call to this API would configure the register bit field GxRCR.SRGEN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_SetResultInterruptNode(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_EnableResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + + XMC_ASSERT("XMC_VADC_GROUP_EnableResultEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_EnableResultEvent:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + group_ptr->RCR[res_reg] |= (uint32_t)VADC_G_RCR_SRGEN_Msk; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which event generation is to be disabled + *
Range: [0x0 to 0xF] + * @return + * None + * + * \parDescription:
+ * Disable result event generation.
\n + * This would just disable the event. It would not alter anything w.r.t the SR line if it was configured. + * A call to this API would configure the register bit field GxRCR.SRGEN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_EnableResultEvent(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_DisableResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + XMC_ASSERT("XMC_VADC_GROUP_DisableResultEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_DisableResultEvent:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + group_ptr->RCR[res_reg] &= ~((uint32_t)VADC_G_RCR_SRGEN_Msk); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register from which the result of conversion is to be read out + *
Range: [0x0 to 0xF] + * @return + * uint32_t returns the complete result register GxRESy. + * + * \parDescription:
+ * Returns the result register completely (result of conversion as well as other info).
\n + * The Result register will have information regarding the channel that is requesting the conversion, + * if the result is valid, if the fast compare bit, Data Reduction Counter, and the request source information. + * All these information will be returned back. And if the user is polling for the result he can use the + * result if the valid bit is set. A call to this API would return the complete register GxRES. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetResult(). + */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetDetailedResult(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + XMC_ASSERT("XMC_VADC_GROUP_GetDetailedResult:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetDetailedResult:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + return(group_ptr->RES[res_reg]); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register from which the result of conversion is to be read out + *
Range: [0x0 to 0xF] + * @return + * XMC_VADC_RESULT_SIZE_t Result register values. + *
Range:[ 0x0 to 0xFFF] (Result of single conversion. Accumulated results not considered for range) + * + * \parDescription:
+ * Returns the result of the conversion.
\n + * This API will only return the result of the conversion and will strip out the other information that is present + * in the result register. A call to this API would access the register bit field GxRES.RESULT. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetDetailedResult(). + */ +__STATIC_INLINE XMC_VADC_RESULT_SIZE_t XMC_VADC_GROUP_GetResult(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg) +{ + XMC_ASSERT("XMC_VADC_GROUP_GetResult:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetResult:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + return ((XMC_VADC_RESULT_SIZE_t)group_ptr->RES[res_reg]); +} + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which the compare value is being set + *
Range: [0x0 to 0xF] + * @param compare_val The compare value itself + *
Range: [0x0 to 0xFFF] + * @return + * None + * + * \parDescription:
+ * Configures the compare value (relevant to the Fast Compare Mode).
\n + * A channel input can be converted and its value stored in its result register. Alternatively, the channel input can + * be converted and compared against a compare value. This is the fast compare mode typically utilized by applications + * that are not interested in absolute converted value of an analog input, but rather a binary decision on how the + * input fares against a preset compare value. The channel should have had already chosen the correct ICLASS with + * the fast compare mode enabled. \b compare_val would be the compare value on which FCM bit in the result + * register will be set. The FCM bit will be set if the analog voltage is greater than the compare value. + * A call to this API would configure the register bit field GxRES.RESULT. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetFastCompareResult(). + */ +void XMC_VADC_GROUP_SetResultFastCompareValue(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg, + const XMC_VADC_RESULT_SIZE_t compare_val); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which the compare value is being set + *
Range: [0x0 to 0xF] + * @return + * ::XMC_VADC_FAST_COMPARE_t If the input is greater or lower than the compare value returns the appropriate enum. + * if the valid flag was not set then it would return XMC_VADC_FAST_COMPARE_UNKNOWN. + * + * \parDescription:
+ * Determines the input is greater/lower than the compare value.
\n + * This API determines if the input is greater/lower than the preset compare value. + * A call to this API would access the register bit field GxRES.FCM. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_SetResultFastCompareValue(). + */ +XMC_VADC_FAST_COMPARE_t XMC_VADC_GROUP_GetFastCompareResult(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg); + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param subtraction_val 12 bit subtraction value + *
Range: [0x0 to 0xFFF] + * @return + * None + * + * \parDescription:
+ * Configures the subtraction value (relevant to the Difference Mode).
\n + * A channel input can be converted and its value stored in its result register. Alternatively, the channel input can + * be converted and subtracted with the value stored in GxRES[0]. This Difference Mode typically utilized by + * applications that are not interested in absolute converted value of an analog input, but rather a difference of + * converted values. Subtraction value will always be present in the GxRES[0] and thus this API would configure + * that register. + * + * \parRelated APIs:
+ * None. + */ +void XMC_VADC_GROUP_SetResultSubtractionValue(XMC_VADC_GROUP_t *const group_ptr, + const uint16_t subtraction_val); +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which the result event is being asserted + *
Range: [0x0 to 0xF] + * @return + * None + * + * \parDescription:
+ * Manually asserts the result event.
\n + * The result event must necessarily be connected to a SR line. The SR in turn must have been enabled along with the + * corresponding NVIC node. Only then will the assertion of RES event lead to an interrupt. + * A call to this API would access the register bit fieldS OF GxREFLAG. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ClearResultEvent(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_TriggerResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + XMC_ASSERT("XMC_VADC_GROUP_TriggerResultEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_TriggerResultEvent:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + group_ptr->REFLAG = (uint32_t)((uint32_t)1 << res_reg); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * uint32_t returns the asserted result events + * + * \parDescription:
+ * Returns the Result event flag register.
\n + * The return is merely the result events which are asserted. + * A call to this API would read the register bit fields of GxREFLAG. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_TriggerResultEvent(). + */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetAssertedResultEvents(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_GetAssertedResultEvents:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return(group_ptr->REFLAG); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which the result event is being acknowledged + *
Range: [0x0 to 0xF] + * @return + * None + * + * \parDescription:
+ * Acknowledges a Result event.
\n + * When a Result event is raised after the conversion of that associated channel has produced a result and + * it has to be cleared. This API would clear the Channel event of a particular channel if it has occurred. + * A call to this API would access the register bit fields of GxREFCLR. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_ChannelTriggerEvent(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_ClearResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + XMC_ASSERT("XMC_VADC_GROUP_ClearResultEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ClearResultEvent:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + group_ptr->REFCLR = (uint32_t)((uint32_t)1 << res_reg); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register for which the result event is being asserted + *
Range: [0x0 to 0xF] + * @param sr The SR line to which the result event must be connected + * @return + * None + * + * \parDescription:
+ * Binds a result event to a requested Service Request line.
\n + * The result event is connected to a service request line. For an event to result in an interrupt, this service + * request line must be enabled in VADC and the NVIC node which this service request line is connected to must have + * interrupt generation enabled. A call to this API would access the registers GxREVNP0 GxREVNP1. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_TriggerResultEvent()
XMC_VADC_GROUP_ClearResultEvent() + */ +void XMC_VADC_GROUP_SetResultInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg, + const XMC_VADC_SR_t sr); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register which forms a part of FIFO + *
Range: [0x0 to 0xF] + * @return + * uint32_t returns the Result register number which is the tail of the FIFO,\b res_reg is apart of this FIFO. + * + * \parDescription:
+ * Returns the the FIFO tail (register from where to read the results).
\n + * The analog converter writes to the head of the FIFO. It is the head of the FIFO which is bound to the channel. + * Applications read the result from the tail of the FIFO. This API would return the result + * register from where a user can call the API XMC_VADC_GROUP_GetResult() to read the result stored in the FIFO. + * A call to this API would access the register bit field GxRCR.FEN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetResultFifoHead()
+ */ +uint32_t XMC_VADC_GROUP_GetResultFifoTail(XMC_VADC_GROUP_t *const group_ptr, uint32_t res_reg); + +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register which forms a part of fifo + *
Range: [0x0 to 0xF] + * @return + * uint32_t returns the Result register number which is the head of the FIFO,\b res_reg is apart of this FIFO. + * + * \parDescription:
+ * Returns the the FIFO head (register to which the results are written by H/W).
\n + * The analog converter writes to the head of the FIFO. It is the head of the FIFO which is bound to the channel. + * Applications read the result from the tail of the FIFO. This API would just return the head of the FIFO + * from where the results are being added to the FIFO. + * A call to this API would access the register bit field GxRCR.FEN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetResultFifoHead()
+ */ +uint32_t XMC_VADC_GROUP_GetResultFifoHead(XMC_VADC_GROUP_t *const group_ptr,const uint32_t res_reg); + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register in question + *
Range: [0x0 to 0xF] + * @return + * bool returns true if the \b res_reg is the FIFO head. + * + * \parDescription:
+ * Determines if the requested register is the head of a FIFO.
\n + * The analog converter writes to the head of the FIFO. It is the head of the FIFO which is bound to the channel. + * Applications read the result from the tail of the FIFO. + * A call to this API would access the register bit field GxRCR.FEN. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetResultFifoHead()
+ */ +bool XMC_VADC_GROUP_IsResultRegisterFifoHead(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg); + +/** + * + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Register number
+ *
Range: [0x0 to 0xF] + * @return + * bool returns true if the \b res_reg is the FIFO member, else false. + * + * \parDescription:
+ * Determines whether the specified register is a FIFO member or not.
\n + * The analog converter writes to the head of the FIFO. It is the head of the FIFO which is bound to the channel. + * Applications read the result from the tail of the FIFO. + * A call to this API would access the register bit field GxRCR.FEN. + * + */ +__STATIC_INLINE bool XMC_VADC_GROUP_IsResultRegisterInFifo(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg) +{ + + XMC_ASSERT("XMC_VADC_GROUP_IsResultRegisterInFifo:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_IsResultRegisterInFifo:Wrong Result Register", + ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + return( (bool)(group_ptr->RCR[res_reg] & (uint32_t)VADC_G_RCR_FEN_Msk)); +} + +#if XMC_VADC_RESULT_PRIORITY_AVAILABLE == 1U +/** + * @param group_ptr Constant pointer to the VADC group + * @param res_reg Result Registers which need to be set for priority conversions + * Bit location 0..15 represents Result Register-0..15 respectively. + * To add the result register as priority. + * Passing a 0x0 will clear all the selected channels + *
Range: [0x0 to 0xFFFF] + * @return + * None + * + * \parDescription:
+ * Prioritize a Result register for group conversions.
\n + * Applications that need to reserve certain result registers only for Queue and scan request sources should + * use this API. A call to this API would access the register bit fields of GxRRASS. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_GetResultRegPriority(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_SetResultRegPriority(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_mask) +{ + XMC_ASSERT("XMC_VADC_GROUP_SetResultRegPriority:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + group_ptr->RRASS = (uint32_t)res_mask; +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @return + * None + * + * \parDescription:
+ * Get the priority of all Result register.
\n + * A call to this API would access the register bit fields of GxRRASS. + * + * \parRelated APIs:
+ * XMC_VADC_GROUP_SetResultRegPriority(). + */ +__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetResultRegPriority(XMC_VADC_GROUP_t *const group_ptr) +{ + XMC_ASSERT("XMC_VADC_GROUP_GetResultRegPriority:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + return(group_ptr->RRASS); +} +#endif +#endif + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_vadc_map.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_vadc_map.h new file mode 100644 index 00000000..865f6688 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_vadc_map.h @@ -0,0 +1,293 @@ +/** + * @file xmc_vadc_map.h + * @date 2016-11-17 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-15: + * - Initial version + * + * 2015-12-01: + * - Added: + * - XMC4300 device supported + * + * - Fixed: + * - Wrong MACRO name corrected for XMC4200/4100 devices. + * XMC_VADC_G3_SAMPLE renamed to XMC_VADC_G1_SAMPLE + * + * 2016-11-17: + * - Fixed: Add missing support for XMC47000 + * - Fixed: Renamed XMC_CCU_41_ST2 to XMC_CCU_41_ST3 + * - Added: New macros equivalent to th existing ones but with better naming. + * Old macros are kept for backward compatibility but they deprecated. + * - Added: ECAT support for XMC48/43 + * + * @endcond + * + */ + +#ifndef XMC_ADC_MAP_H +#define XMC_ADC_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************************************************************************************** + * MACROS + *********************************************************************************************************************/ +#if ( UC_FAMILY == XMC1 ) + +/* Group request source Gating input connection mappings */ +#define XMC_CCU_40_ST3 XMC_VADC_REQ_GT_A /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */ +#define XMC_CCU_40_ST2 XMC_VADC_REQ_GT_B /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST2 */ +#define XMC_CCU_40_ST1 XMC_VADC_REQ_GT_C /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST1 */ +#define XMC_CCU_40_ST0 XMC_VADC_REQ_GT_D /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST0 */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_CCU_80_ST3_A XMC_VADC_REQ_GT_E /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3A */ +#define XMC_CCU_81_ST3 XMC_VADC_REQ_GT_F /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3 */ +#endif +#if (UC_SERIES != XMC13 && UC_SERIES != XMC11) +#define XMC_LEDTS0_FN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS0_FN */ +#define XMC_LEDTS1_FN XMC_VADC_REQ_GT_J /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS1_FN */ +#endif +#define XMC_ERU_0_PDOUT2 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT2 */ +#define XMC_ERU_0_PDOUT3 XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT3 */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_CCU_80_ST0 XMC_VADC_REQ_GT_M /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST0 */ +#define XMC_CCU_80_ST1 XMC_VADC_REQ_GT_N /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST1 */ +#endif +#define XMC_ERU_0_PDOUT0 XMC_VADC_REQ_GT_O /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT0 */ +#define XMC_ERU_0_PDOUT1 XMC_VADC_REQ_GT_P /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT1 */ + +/* Group request source Trigger input connection mappings */ +#define XMC_CCU_40_SR2 XMC_VADC_REQ_TR_A /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR2 */ +#define XMC_CCU_40_SR3 XMC_VADC_REQ_TR_B /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR3 */ +#if (UC_SERIES != XMC11) +#define XMC_BCCU0_TRIGOUT XMC_VADC_REQ_TR_F /**< @deprecated use instead XMC_VADC_REQ_TR_BCCU0_TRIGOUT0, XMC_VADC_REQ_TR_G0_BCCU0_TRIGOUT0 or XMC_VADC_REQ_TR_G1_BCCU0_TRIGOUT1 */ +#endif +#define XMC_ERU_0_IOUT2 XMC_VADC_REQ_TR_G /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT2 */ +#define XMC_ERU_0_IOUT3 XMC_VADC_REQ_TR_H /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT3 */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_CCU_80_SR2 XMC_VADC_REQ_TR_I /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR2 */ +#define XMC_CCU_80_SR3 XMC_VADC_REQ_TR_J /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR3 */ +#endif +#define XMC_ERU_0_IOUT0 XMC_VADC_REQ_TR_M /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT0 */ +#define XMC_ERU_0_IOUT1 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT1 */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_POSIF_0_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1 */ +#endif +#define XMC_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< @deprecated use instead XMC_VADC_REQ_TR_REQ_GT_SEL */ + +/* Group request source Gating input connection mappings */ +#define XMC_VADC_REQ_GT_CCU40_ST3 XMC_VADC_REQ_GT_A /**< VADC Gating input A */ +#define XMC_VADC_REQ_GT_CCU40_ST2 XMC_VADC_REQ_GT_B /**< VADC Gating input B */ +#define XMC_VADC_REQ_GT_CCU40_ST1 XMC_VADC_REQ_GT_C /**< VADC Gating input C */ +#define XMC_VADC_REQ_GT_CCU40_ST0 XMC_VADC_REQ_GT_D /**< VADC Gating input D */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_VADC_REQ_GT_CCU80_ST3A XMC_VADC_REQ_GT_E /**< VADC Gating input E */ +#define XMC_VADC_REQ_GT_CCU80_ST3 XMC_VADC_REQ_GT_F /**< VADC Gating input F */ +#endif +#if (UC_SERIES != XMC13 && UC_SERIES != XMC11) +#define XMC_VADC_REQ_GT_LEDTS0_FN XMC_VADC_REQ_GT_I /**< VADC Gating input I */ +#define XMC_VADC_REQ_GT_LEDTS1_FN XMC_VADC_REQ_GT_J /**< VADC Gating input J */ +#endif +#define XMC_VADC_REQ_GT_ERU0_PDOUT2 XMC_VADC_REQ_GT_K /**< VADC Gating input K */ +#define XMC_VADC_REQ_GT_ERU0_PDOUT3 XMC_VADC_REQ_GT_L /**< VADC Gating input L */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_VADC_REQ_GT_CCU80_ST0 XMC_VADC_REQ_GT_M /**< VADC Gating input M */ +#define XMC_VADC_REQ_GT_CCU80_ST1 XMC_VADC_REQ_GT_N /**< VADC Gating input N */ +#endif +#define XMC_VADC_REQ_GT_ERU0_PDOUT0 XMC_VADC_REQ_GT_O /**< VADC Gating input O */ +#define XMC_VADC_REQ_GT_ERU0_PDOUT1 XMC_VADC_REQ_GT_P /**< VADC Gating input P */ + +/* Group request source Trigger input connection mappings */ +#define XMC_VADC_REQ_TR_CCU40_SR2 XMC_VADC_REQ_TR_A /**< VADC Trigger input A */ +#define XMC_VADC_REQ_TR_CCU40_SR3 XMC_VADC_REQ_TR_B /**< VADC Trigger input B */ +#if (UC_SERIES != XMC11) +#define XMC_VADC_REQ_TR_BCCU0_TRIGOUT0 XMC_VADC_REQ_TR_F /**< VADC Global Background Source Trigger input F */ +#define XMC_VADC_REQ_TR_G0_BCCU0_TRIGOUT0 XMC_VADC_REQ_TR_F /**< VADC Group 0 Trigger input F */ +#define XMC_VADC_REQ_TR_G1_BCCU0_TRIGOUT1 XMC_VADC_REQ_TR_F /**< VADC Group1 Trigger input F */ +#endif +#define XMC_VADC_REQ_TR_ERU0_IOUT2 XMC_VADC_REQ_TR_G /**< VADC Trigger input G */ +#define XMC_VADC_REQ_TR_ERU0_IOUT3 XMC_VADC_REQ_TR_H /**< VADC Trigger input H */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_VADC_REQ_TR_CCU80_SR2 XMC_VADC_REQ_TR_I /**< VADC Trigger input I */ +#define XMC_VADC_REQ_TR_CCU80_SR3 XMC_VADC_REQ_TR_J /**< VADC Trigger input J */ +#endif +#define XMC_VADC_REQ_TR_ERU0_IOUT0 XMC_VADC_REQ_TR_M /**< VADC Trigger input M */ +#define XMC_VADC_REQ_TR_ERU0_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Trigger input N */ +#if (UC_SERIES != XMC12 && UC_SERIES != XMC11) +#define XMC_VADC_REQ_TR_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Trigger input O */ +#endif +#define XMC_VADC_REQ_TR_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< VADC Trigger input P */ + +#endif + +#if ( UC_FAMILY == XMC4 ) + +/* Group request source Gating input connection mappings */ +#define XMC_CCU_40_ST3 XMC_VADC_REQ_GT_A /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */ +#define XMC_CCU_41_ST3 XMC_VADC_REQ_GT_B /**< @deprecated use instead XMC_VADC_REQ_GT_CCU41_ST3 */ +#define XMC_CCU_40_SR0 XMC_VADC_REQ_GT_C /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_SR0 */ +#define XMC_CCU_41_SR1 XMC_VADC_REQ_GT_D /**< @deprecated use instead XMC_VADC_REQ_GT_CCU41_SR1 */ +#define XMC_CCU_80_ST3_A XMC_VADC_REQ_GT_E /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3A */ +#define XMC_CCU_80_ST3_B XMC_VADC_REQ_GT_F /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3B */ + +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_CCU_81_ST3_A XMC_VADC_REQ_GT_G /**< @deprecated use instead XMC_VADC_REQ_GT_CCU81_ST3A */ +#define XMC_CCU_81_ST3_B XMC_VADC_REQ_GT_H /**< @deprecated use instead XMC_VADC_REQ_GT_CCU81_ST3B */ +#endif + +#define XMC_DAC_0_SGN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_DAC0_SGN, XMC_VADC_REQ_GT_G0_DAC0_SGN or XMC_VADC_REQ_GT_G2_DAC0_SGN */ +#define XMC_DAC_1_SGN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_DAC0_SGN, XMC_VADC_REQ_GT_G1_DAC1_SGN or XMC_VADC_REQ_GT_G3_DAC1_SGN */ +#define XMC_LEDTS_FN XMC_VADC_REQ_GT_J /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS_FN */ +#define XMC_VADC_G0_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G0_VADC_G1BFLOUT0 */ +#define XMC_VADC_G1_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G1_VADC_G0BFLOUT0 */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_G2_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G2_VADC_G3BFLOUT0 */ +#define XMC_VADC_G3_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G3_VADC_G2BFLOUT0 */ +#endif +#define XMC_VADC_G0_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G0_VADC_G3SAMPLE */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_G1_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G1_VADC_G0SAMPLE */ +#define XMC_VADC_G2_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G2_VADC_G1SAMPLE */ +#define XMC_VADC_G3_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G3_VADC_G2SAMPLE */ +#endif +#define XMC_CCU_80_SR0 XMC_VADC_REQ_GT_M /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_SR0 */ +#define XMC_CCU_80_SR1 XMC_VADC_REQ_GT_N /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_SR1 */ +#define XMC_ERU_1_PDOUT0 XMC_VADC_REQ_GT_O /**< @deprecated use instead XMC_VADC_REQ_GT_ERU1_PDOUT0 */ +#define XMC_ERU_1_PDOUT1 XMC_VADC_REQ_GT_P /**< @deprecated use instead XMC_VADC_REQ_GT_ERU1_PDOUT1 */ + +/* Group request source Trigger input connection mappings */ +#define XMC_CCU_40_SR2 XMC_VADC_REQ_TR_A /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR2 */ +#define XMC_CCU_40_SR3 XMC_VADC_REQ_TR_B /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR3 */ +#define XMC_CCU_41_SR2 XMC_VADC_REQ_TR_C /**< @deprecated use instead XMC_VADC_REQ_TR_CCU41_SR2 */ +#define XMC_CCU_41_SR3 XMC_VADC_REQ_TR_D /**< @deprecated use instead XMC_VADC_REQ_TR_CCU41_SR3 */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_CCU_42_SR3 XMC_VADC_REQ_TR_E /**< @deprecated use instead XMC_VADC_REQ_TR_CCU42_SR3 */ +#define XMC_CCU_43_SR3 XMC_VADC_REQ_TR_F /**< @deprecated use instead XMC_VADC_REQ_TR_CCU43_SR3 */ +#endif +#define XMC_CCU_80_SR2 XMC_VADC_REQ_TR_I /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR2 */ +#define XMC_CCU_80_SR3 XMC_VADC_REQ_TR_J /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR3 */ +#define XMC_CCU_81_SR2 XMC_VADC_REQ_TR_K /**< @deprecated use instead XMC_VADC_REQ_TR_CCU81_SR2 */ +#define XMC_CCU_81_SR3 XMC_VADC_REQ_TR_L /**< @deprecated use instead XMC_VADC_REQ_TR_CCU81_SR3 */ +#define XMC_ERU_1_IOUT0 XMC_VADC_REQ_TR_M /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT0 */ +#define XMC_ERU_1_IOUT1 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT1, XMC_VADC_REQ_TR_G0_ERU1_IOUT1 or XMC_VADC_REQ_TR_G1_ERU1_IOUT1 */ +#define XMC_ERU_1_IOUT2 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT1, XMC_VADC_REQ_TR_G2_ERU1_IOUT2 or XMC_VADC_REQ_TR_G3_ERU1_IOUT1 */ +#if ( (UC_SERIES != XMC43) ) +#define XMC_POSIF_0_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1, XMC_VADC_REQ_TR_G0_POSIF0_SR1 or XMC_VADC_REQ_TR_G2_POSIF0_SR1 */ +#endif +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_POSIF_1_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1, XMC_VADC_REQ_TR_G1_POSIF0_SR1 or XMC_VADC_REQ_TR_G3_POSIF0_SR1 */ +#endif +#define XMC_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */ + +/* Group request source Gating input connection mappings */ +#define XMC_VADC_REQ_GT_CCU40_ST3 XMC_VADC_REQ_GT_A /**< VADC Gating input A */ +#define XMC_VADC_REQ_GT_CCU41_ST3 XMC_VADC_REQ_GT_B /**< VADC Gating input B */ +#define XMC_VADC_REQ_GT_CCU40_SR0 XMC_VADC_REQ_GT_C /**< VADC Gating input C */ +#define XMC_VADC_REQ_GT_CCU41_SR1 XMC_VADC_REQ_GT_D /**< VADC Gating input D */ +#define XMC_VADC_REQ_GT_CCU80_ST3A XMC_VADC_REQ_GT_E /**< VADC Gating input E */ +#define XMC_VADC_REQ_GT_CCU80_ST3B XMC_VADC_REQ_GT_F /**< VADC Gating input F */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_REQ_GT_CCU81_ST3A XMC_VADC_REQ_GT_G /**< VADC Gating input G */ +#define XMC_VADC_REQ_GT_CCU81_ST3B XMC_VADC_REQ_GT_H /**< VADC Gating input H */ +#endif +#define XMC_VADC_REQ_GT_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Global Background Source Gating input I */ +#define XMC_VADC_REQ_GT_G0_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Group 0 Gating input I */ +#define XMC_VADC_REQ_GT_G1_DAC1_SGN XMC_VADC_REQ_GT_I /**< VADC Group 1 Gating input I */ +#define XMC_VADC_REQ_GT_G2_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Group 2 Gating input I */ +#define XMC_VADC_REQ_GT_G3_DAC1_SGN XMC_VADC_REQ_GT_I /**< VADC Group 3 Gating input I */ +#define XMC_VADC_REQ_GT_LEDTS_FN XMC_VADC_REQ_GT_J /**< VADC Gating input J */ +#define XMC_VADC_REQ_GT_VADC_G1BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Global Background Source Gating input K */ +#define XMC_VADC_REQ_GT_G0_VADC_G1BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 0 Gating input K */ +#define XMC_VADC_REQ_GT_G1_VADC_G0BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 1 Gating input K */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_REQ_GT_G2_VADC_G3BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 2 Gating input K */ +#define XMC_VADC_REQ_GT_G3_VADC_G2BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 3 Gating input K */ +#endif +#define XMC_VADC_REQ_GT_G0_VADC_G3SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 0 Gating input L */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_REQ_GT_G1_VADC_G0SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 1 Gating input L */ +#define XMC_VADC_REQ_GT_G2_VADC_G1SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 2 Gating input L */ +#define XMC_VADC_REQ_GT_G3_VADC_G2SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 3 Gating input L */ +#endif +#define XMC_VADC_REQ_GT_CCU80_SR0 XMC_VADC_REQ_GT_M /**< VADC Gating input M */ +#define XMC_VADC_REQ_GT_CCU80_SR1 XMC_VADC_REQ_GT_N /**< VADC Gating input N */ +#define XMC_VADC_REQ_GT_ERU1_PDOUT0 XMC_VADC_REQ_GT_O /**< VADC Gating input O */ +#define XMC_VADC_REQ_GT_ERU1_PDOUT1 XMC_VADC_REQ_GT_P /**< VADC Gating input P */ + +/* Group request source Trigger input connection mappings */ +#define XMC_VADC_REQ_TR_CCU40_SR2 XMC_VADC_REQ_TR_A /**< VADC Trigger input A */ +#define XMC_VADC_REQ_TR_CCU40_SR3 XMC_VADC_REQ_TR_B /**< VADC Trigger input B */ +#define XMC_VADC_REQ_TR_CCU41_SR2 XMC_VADC_REQ_TR_C /**< VADC Trigger input C */ +#define XMC_VADC_REQ_TR_CCU41_SR3 XMC_VADC_REQ_TR_D /**< VADC Trigger input D */ +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_REQ_TR_CCU42_SR3 XMC_VADC_REQ_TR_E /**< VADC Trigger input E */ +#define XMC_VADC_REQ_TR_CCU43_SR3 XMC_VADC_REQ_TR_F /**< VADC Trigger input F */ +#endif +#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC43)) +#define XMC_VADC_REQ_TR_ECAT_SYNC0 XMC_VADC_REQ_TR_G /**< VADC Trigger input G */ +#define XMC_VADC_REQ_TR_ECAT_SYNC1 XMC_VADC_REQ_TR_H /**< VADC Trigger input H */ +#endif +#define XMC_VADC_REQ_TR_CCU80_SR2 XMC_VADC_REQ_TR_I /**< VADC Trigger input I */ +#define XMC_VADC_REQ_TR_CCU80_SR3 XMC_VADC_REQ_TR_J /**< VADC Trigger input J */ +#define XMC_VADC_REQ_TR_CCU81_SR2 XMC_VADC_REQ_TR_K /**< VADC Trigger input K */ +#define XMC_VADC_REQ_TR_CCU81_SR3 XMC_VADC_REQ_TR_L /**< VADC Trigger input L */ +#define XMC_VADC_REQ_TR_ERU1_IOUT0 XMC_VADC_REQ_TR_M /**< VADC Trigger input M */ +#define XMC_VADC_REQ_TR_ERU1_IOUT1 XMC_VADC_REQ_TR_M /**< VADC Global Background Source Trigger input N */ +#define XMC_VADC_REQ_TR_G0_ERU1_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Group 0 Trigger input N */ +#define XMC_VADC_REQ_TR_G1_ERU1_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Group 1 Trigger input N */ +#define XMC_VADC_REQ_TR_G2_ERU1_IOUT2 XMC_VADC_REQ_TR_N /**< VADC Group 2 Trigger input N */ +#define XMC_VADC_REQ_TR_G3_ERU1_IOUT2 XMC_VADC_REQ_TR_N /**< VADC Group 3 Trigger input N */ +#if ( (UC_SERIES != XMC43) ) +#define XMC_VADC_REQ_TR_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Global Background Source Trigger input O */ +#define XMC_VADC_REQ_TR_G0_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 0 Trigger input O */ +#define XMC_VADC_REQ_TR_G1_POSIF1_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 1 Trigger input O */ +#endif +#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) +#define XMC_VADC_REQ_TR_G2_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 2 Trigger input O */ +#define XMC_VADC_REQ_TR_G3_POSIF1_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 3 Trigger input O */ +#endif +#define XMC_VADC_REQ_TR_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< VADC Trigger input P */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_wdt.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_wdt.h new file mode 100644 index 00000000..223af6e6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/inc/xmc_wdt.h @@ -0,0 +1,439 @@ +/** + * @file xmc_wdt.h + * @date 2015-08-06 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Documentation updates
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-08-06: + * - Bug fix in XMC_WDT_SetDebugMode() API, Wrong register is being configured.
+ * @endcond + */ + +#ifndef XMC_WDT_H +#define XMC_WDT_H + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_common.h" +#include "xmc_scu.h" +/** + * @addtogroup XMClib XMC Peripheral Library + * @{ + */ + +/** + * @addtogroup WDT + * @brief Watchdog driver for the XMC microcontroller family. + * + * The watchdog unit (WDT) improves the system integrity, by triggering the system reset request to bring the system + * back from the unresponsive state to normal operation. + * + * This LLD provides the Configuration structure XMC_WDT_CONFIG_t and initialization function XMC_WDT_Init().\n + * It can be used to: + * -# Start or Stop the watchdog timer. (XMC_WDT_Start() and XMC_WDT_Stop()) + * -# Service the watchdog timer. (XMC_WDT_Service()) + * -# Configure the service window upper bound and lower bound timing values. (XMC_WDT_SetWindowBounds()) + * -# Enable the generation of the pre-warning event for the first overflow of the timer. (XMC_WDT_SetMode()) + * -# Clear the pre-warning alarm event. It is mandatory to clear the flag during pre-warning alarm ISR, to stop + generating reset request for the second overflow of the timer. (XMC_WDT_ClearAlarm()) + * -# Suspend the watchdog timer during Debug HALT mode. (XMC_WDT_SetDebugMode()) + * -# Configure service indication pulse width.(XMC_WDT_SetServicePulseWidth()) + * + * @{ + */ + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#define XMC_WDT_MAGIC_WORD (0xABADCAFEU) /* Magic word to be written in Service Register (SRV), + to service or feed the watchdog. */ + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/** + * Defines working modes for watchdog. Use type XMC_WDT_MODE_t for this enum. + */ +typedef enum XMC_WDT_MODE +{ + XMC_WDT_MODE_TIMEOUT = (uint32_t)0x0 << WDT_CTR_PRE_Pos, /**< Generates reset request as soon as the timer overflow + occurs. */ + XMC_WDT_MODE_PREWARNING = (uint32_t)0x1 << WDT_CTR_PRE_Pos /**< Generates an alarm event for the first overflow. And + reset request after subsequent overflow, if not + serviced after first overflow. */ +} XMC_WDT_MODE_t; + +/** + * Defines debug behaviour of watchdog when the CPU enters HALT mode. Use type XMC_WDT_DEBUG_MODE_t for this enum. + */ +typedef enum XMC_WDT_DEBUG_MODE +{ + XMC_WDT_DEBUG_MODE_STOP = (uint32_t)0x0 << WDT_CTR_DSP_Pos, /**< Watchdog counter is paused during debug halt. */ + XMC_WDT_DEBUG_MODE_RUN = (uint32_t)0x1 << WDT_CTR_DSP_Pos /**< Watchdog counter is not paused during debug halt. */ +} XMC_WDT_DEBUG_MODE_t; + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + /* Anonymous structure/union guard start */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__TASKING__) + #pragma warning 586 +#endif + +/** + * Structure for initializing watchdog timer. Use type XMC_WDT_CONFIG_t for this structure. + */ +typedef struct XMC_WDT_CONFIG +{ + uint32_t window_upper_bound; /**< Upper bound for service window (WUB). Reset request is generated up on overflow of + timer. ALways upper bound value has to be more than lower bound value. If it is set + lower than WLB, triggers a system reset after timer crossed upper bound value.\n + Range: [0H to FFFFFFFFH] */ + uint32_t window_lower_bound; /**< Lower bound for servicing window (WLB). Setting the lower bound to 0H disables the + window mechanism.\n + Range: [0H to FFFFFFFFH] */ + union + { + struct + { + uint32_t : 1; + uint32_t prewarn_mode : 1; /**< Pre-warning mode (PRE). This accepts boolean values as input. */ + uint32_t : 2; + uint32_t run_in_debug_mode : 1; /**< Watchdog timer behaviour during debug (DSP). This accepts boolean values as input. */ + uint32_t : 3; + uint32_t service_pulse_width : 8; /**< Service Indication Pulse Width (SPW). Generated Pulse width is of (SPW+1), + in fwdt cycles.\n + Range: [0H to FFH] */ + uint32_t : 16; + }; + uint32_t wdt_ctr; /* Value of operation mode control register (CTR). It’s bit fields are represented by above + union members. */ + }; +} XMC_WDT_CONFIG_t; +/* Anonymous structure/union guard end */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__TASKING__) + #pragma warning restore +#endif +/********************************************************************************************************************* + * API PROTOTYPES + ********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * \if XMC4 + * Enables watchdog clock and releases watchdog reset.\n + * \endif + * \if XMC1 + * Enables watchdog clock.\n + * \endif + * \par + * This API is invoked by XMC_WDT_Init() and therefore no need to call it explicitly during watchdog initialization + * sequence. Invoke this API to enable watchdog once again if the watchdog is disabled by invoking XMC_WDT_Disable(). + * + * \parNote:
+ * \if XMC4 + * 1. It is required to configure the watchdog, again after invoking XMC_WDT_Disable(). Since all the registers are + * reset with default values. + * \endif + * \if XMC1 + * 1. Not required to configure the watchdog again after invoking XMC_WDT_Disable(). Since the registers retains with + * the configured values. + * \endif + * \parRelated APIs:
+ * XMC_WDT_Init(), XMC_WDT_Disable() + */ +void XMC_WDT_Enable(void); + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * \if XMC4 + * Disables the clock and resets watchdog timer.\n + * \endif + * \if XMC1 + * Disables the clock to the watchdog timer.\n + * \endif + * + * \parNote:
+ * \if XMC4 + * 1. Resets the registers with default values. So XMC_WDT_Init() has to be invoked again to configure the watchdog. + * \endif + * \if XMC1 + * 1. After invoking XMC_WDT_Disable(), all register values are displayed with 0F in debugger. Once enabled by + calling XMC_WDT_Enable(), previous configured register values are displayed. No need to invoke XMC_WDT_Init() + again. + * \endif + * \parRelated APIs:
+ * XMC_WDT_Enable() + */ +void XMC_WDT_Disable(void); + +/** + * @param config pointer to a constant watchdog configuration data structure. Refer data structure XMC_WDT_CONFIG_t + * for detail. + * + * @return None + * + * \parDescription:
+ * Initializes and configures watchdog with configuration data pointed by \a config.\n + * \par + * It invokes XMC_WDT_Enable() to enable clock and release reset. Then configures the lower and upper window bounds, + * working mode (timeout/pre-warning), debug behaviour and service request indication pulse width. + * + * \parNote:
+ * 1. With out invoking this XMC_WDT_Init() or XMC_WDT_Enable(), invocation of other APIs like XMC_WDT_SetWindowBounds(), + * XMC_WDT_SetMode(), XMC_WDT_SetServicePulseWidth(), XMC_WDT_SetDebugMode(), XMC_WDT_Start(), XMC_WDT_GetCounter(), + * XMC_WDT_Service(), XMC_WDT_ClearAlarm() has no affect. + */ +void XMC_WDT_Init(const XMC_WDT_CONFIG_t *const config); + +/** + * @param lower_bound specifies watchdog window lower bound in terms of watchdog clock (fWDT) cycles. + * Range: [0H to FFFFFFFFH]. + * @param upper_bound specifies watchdog window upper bound in terms of watchdog clock (fWDT) cycles. + * Range: [0H to FFFFFFFFH]. + * + * @return None + * + * \parDescription:
+ * Sets watchdog window lower and upper bounds by updating WLB and WUB registers.\n + * \par + * Window lower and upper bounds are set during initialization in XMC_WDT_Init(). Invoke this API to alter the values as + * needed later in the program. This upper bound and lower bound can be calculated by using the below formula\n + * upper_bound or lower_bound = desired_boundary_time(sec) * fwdt(hz) + * + * \parNote: + * 1. Always ensure that upper_bound is greater than the lower_bound value. If not, whenever timer crosses the + * upper_bound value it triggers the reset(wdt_rst_req) of the controller. + */ +__STATIC_INLINE void XMC_WDT_SetWindowBounds(uint32_t lower_bound, uint32_t upper_bound) +{ + WDT->WLB = lower_bound; + WDT->WUB = upper_bound; +} + +/** + * @param mode is one of the working modes of the watchdog timer, i.e timeout or pre-warning. Refer @ref XMC_WDT_MODE_t + * for valid values. + * + * @return None + * + * \parDescription:
+ * Sets watchdog working mode (timeout or pre-warning) by updating PRE bit of CTR register.\n + * \par + * The working mode is set during initialization in XMC_WDT_Init(). Invoke this API to alter the mode as needed later in + * the program. + */ +__STATIC_INLINE void XMC_WDT_SetMode(XMC_WDT_MODE_t mode) +{ + WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_PRE_Msk) | (uint32_t)mode; +} + +/** + * @param service_pulse_width specifies Service indication pulse width in terms of fwdt. + * Range: [0H – FFH]. + * @return None + * + * \parDescription:
+ * Sets service indication pulse width by updating SPW bit field of CTR register.\n + * \par + * The service indication pulse (with width service_pulse_width + 1 in fwdt cycles) is generated on successful servicing + * or feeding of watchdog. The pulse width is initially set during initialization in XMC_WDT_Init(). Invoke this API to + * alter the width as needed later in the program. + */ +__STATIC_INLINE void XMC_WDT_SetServicePulseWidth(uint8_t service_pulse_width) +{ + WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_SPW_Msk) | ((uint32_t)service_pulse_width << WDT_CTR_SPW_Pos); +} + +/** + * @param debug_mode running state of watchdog during debug halt mode. Refer @ref XMC_WDT_DEBUG_MODE_t for + * valid values. + * + * @return None + * + * \parDescription:
+ * Sets debug behaviour of watchdog by modifying DSP bit of CTR register.\n + * \par + * Depending upon DSP bit, the watchdog timer stops when CPU is in HALT mode. The debug behaviour is initially set as + * XMC_WDT_DEBUG_MODE_STOP during initialization in XMC_WDT_Init(). Invoke this API to change the debug behaviour as + * needed later in the program. + */ +__STATIC_INLINE void XMC_WDT_SetDebugMode(const XMC_WDT_DEBUG_MODE_t debug_mode) +{ + WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_DSP_Msk) | (uint32_t)debug_mode; +} + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Start the watchdog timer by setting ENB bit of CTR register.\n + * \par + * Invoke this API to start the watchdog after initialization, or to resume the watchdog when + * paused by invoking XMC_WDT_Stop(). + * + * \parRelated APIs:
+ * XMC_WDT_Init(), XMC_WDT_Stop() + */ +__STATIC_INLINE void XMC_WDT_Start(void) +{ + WDT->CTR |= (uint32_t)WDT_CTR_ENB_Msk; +} + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Pauses watchdog timer by resetting ENB bit of CTR register.\n + * \par + * Invoke this API to pause the watchdog as needed in the program e.g. debugging through software control. + * + * \parRelated APIs:
+ * XMC_WDT_Init(), XMC_WDT_Stop() + */ +__STATIC_INLINE void XMC_WDT_Stop(void) +{ + WDT->CTR &= (uint32_t)~WDT_CTR_ENB_Msk; +} + +/** + * @param None + * + * @return uint32_t Current count value of watchdog timer register (TIM). + * Range: [0H to FFFFFFFFH] + * + * \parDescription:
+ * Reads current count of timer register (TIM).\n + * \par + * Invoke this API before servicing or feeding the watchdog to check whether count is between lower and upper + * window bounds. + * + * \parRelated APIs:
+ * XMC_WDT_Service() + */ +__STATIC_INLINE uint32_t XMC_WDT_GetCounter(void) +{ + return WDT->TIM; +} + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Services or feeds the watchdog by writing the Magic word in SRV register.\n + * \par + * Service watchdog when count value of watchdog timer is between lower and upper window bounds. Successful servicing + * will reset watchdog timer (TIM register) to 0H and generate service indication pulse. + * + * \parNote:
+ * 1. invoking this API when count value of watchdog timer is less than window lower bound results + * wrong servicing and immediately triggers reset request. + * + * \parRelated APIs:
+ * XMC_WDT_GetCounter(), XMC_WDT_SetWindowBounds(), XMC_WDT_SetServicePulseWidth() + */ +__STATIC_INLINE void XMC_WDT_Service(void) +{ + WDT->SRV = XMC_WDT_MAGIC_WORD; +} + +/** + * @param None + * + * @return None + * + * \parDescription:
+ * Clears pre-warning alarm by setting ALMC bit in WDTCLR register.\n + * \par + * In pre-warning mode, first overflow of the timer upper window bound fires the pre-warning alarm. XMC_WDT_ClearAlarm() + * must be invoked to clear the alarm alarm. After clearing of the alarm, watchdog timer must be serviced within valid + * time window. Otherwise watchdog timer triggers the reset request up on crossing the upper bound value in a subsequent + * cycle. + * + * \parRelated APIs:
+ * XMC_WDT_Service(), XMC_WDT_SetMode() + */ +__STATIC_INLINE void XMC_WDT_ClearAlarm(void) +{ + WDT->WDTCLR = WDT_WDTCLR_ALMC_Msk; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XMC_WDT_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_eru.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_eru.c new file mode 100644 index 00000000..0f316c51 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_eru.c @@ -0,0 +1,84 @@ +/** + * @file xmc4_eru.c + * @date 2015-02-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * @endcond + */ +#include "xmc_eru.h" + +#if UC_FAMILY == XMC4 +#include "xmc_scu.h" + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ +/* Enable the clock and De-assert the ERU module from the reset state. */ +void XMC_ERU_Enable(XMC_ERU_t *const eru) +{ +#if defined(XMC_ERU1) + if (eru == XMC_ERU1) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ERU1); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ERU1); + } +#else + XMC_UNUSED_ARG(eru); + #endif +} + +/* Disable the clock and Reset the ERU module. */ +void XMC_ERU_Disable(XMC_ERU_t *const eru) +{ +#if defined(XMC_ERU1) + if (eru == XMC_ERU1) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ERU1); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ERU1); + #endif + } +#else + XMC_UNUSED_ARG(eru); +#endif +} + +#endif /* if( UC_FAMILY == XMC1 ) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_flash.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_flash.c new file mode 100644 index 00000000..3ad136dc --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_flash.c @@ -0,0 +1,512 @@ +/** + * @file xmc4_flash.c + * @date 2016-01-08 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-10: + * - Initial
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API + * + * 2015-08-17: + * - Added the below API's to the public interface. + * 1. XMC_FLASH_Reset + * 2. XMC_FLASH_ErasePhysicalSector + * 3. XMC_FLASH_EraseUCB + * 4. XMC_FLASH_ResumeProtection + * 5. XMC_FLASH_RepairPhysicalSector + * + * 2016-01-08: + * - Wait until operation is finished for the next functions: + * 1. XMC_FLASH_InstallProtection + * 2. XMC_FLASH_ConfirmProtection + * 3. XMC_FLASH_ProgramPage + * 4. XMC_FLASH_EraseSector + * 5. XMC_FLASH_ErasePhysicalSector + * 6. XMC_FLASH_EraseUCB + * - Fix XMC_FLASH_VerifyReadProtection and XMC_FLASH_VerifyWriteProtection + * + * @endcond + * + */ + +#include "xmc_flash.h" + +#if UC_FAMILY == XMC4 + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#define XMC_FLASH_PROTECTION_CONFIGURATION_WORDS (8UL) /* Used to upadte the assembly buffer during protection + configuration */ +#define XMC_FLASH_PROT_CONFIRM_OFFSET (512UL) /* Offset address for UCB page */ +#define XMC_FLASH_PROT_CONFIRM_WORDS (4UL) +#define XMC_FLASH_PROT_CONFIRM_CODE (0x8AFE15C3UL) + +/********************************************************************************************************************* + * LOCAL FUNCTIONS + ********************************************************************************************************************/ +void XMC_FLASH_lEnterPageModeCommand(void); +void XMC_FLASH_lLoadPageCommand(uint32_t low_word, uint32_t high_word); +void XMC_FLASH_lWritePageCommand(uint32_t *page_start_address); +void XMC_FLASH_lWriteUCBPageCommand(uint32_t *page_start_address); +void XMC_FLASH_lEraseSectorCommand(uint32_t *sector_start_address); +void XMC_FLASH_lDisableSectorWriteProtectionCommand(uint32_t user, uint32_t password_0, uint32_t password_1); +void XMC_FLASH_lDisableReadProtectionCommand(uint32_t password_0, uint32_t password_1); +void XMC_FLASH_lRepairPhysicalSectorCommand(void); +void XMC_FLASH_lErasePhysicalSectorCommand(uint32_t *sector_start_address); +void XMC_FLASH_lClearStatusCommand(void); + +/* + * Command to program the PFLASH in to page mode, so that assembly buffer is used + */ +void XMC_FLASH_lEnterPageModeCommand(void) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = (uint32_t)0x50U; +} + +/* + * Command to load the data into the page assembly buffer + */ +void XMC_FLASH_lLoadPageCommand(uint32_t low_word, uint32_t high_word) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x55f0U); + *address = low_word; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x55f4U); + *address = high_word; +} + +/* + * Command to start the programming of one page with data from the assembly buffer + */ +void XMC_FLASH_lWritePageCommand(uint32_t *page_start_address) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xa0U; + address = page_start_address; + *address = 0xaaU; +} + +/* + * Command to start the programming of UCB page with data from the assembly buffer + */ +void XMC_FLASH_lWriteUCBPageCommand(uint32_t *page_start_address) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xc0U; + address = page_start_address; + *address = 0xaaU; +} + +/* + * Command to erase sector which is starting with the specified address + */ +void XMC_FLASH_lEraseSectorCommand(uint32_t *sector_start_address) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0x80U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = sector_start_address; + *address = 0x30U; +} + + +/* + * Command to temporarily disables the write protection belonging to the the USER specified, when passwords match with their + * configured values + */ +void XMC_FLASH_lDisableSectorWriteProtectionCommand(uint32_t user, uint32_t password_0, uint32_t password_1) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x553cU); + *address = user; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = password_0; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = password_1; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5558U); + *address = 0x05U; +} + +/* + * Command to temporarily disables the read protection along with write protection, when passwords match with their + * configured values + */ +void XMC_FLASH_lDisableReadProtectionCommand(uint32_t password_0, uint32_t password_1) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x553cU); + *address = 0x00U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = password_0; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = password_1; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5558U); + *address = 0x08U; +} + +/* + * Command to clear FSR.PROG and FSR.ERASE and the error flags in FSR such as PFOPER, SQER, PROER, PFDBER, ORIER, VER + */ +void XMC_FLASH_lClearStatusCommand(void) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xf5U; +} + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + + /* + * This API shall clear Program, erase and error flags(PFOPER, SQER, PROER, PFDBER, ORIER, VER) of FSR register. + */ +void XMC_FLASH_ClearStatus(void) +{ + XMC_FLASH_lClearStatusCommand(); +} + +/* + * This API returns the FSR register value + */ +uint32_t XMC_FLASH_GetStatus(void) +{ + return FLASH0->FSR; +} + +/* + * This API enables the events which required to trigger the ISR + */ +void XMC_FLASH_EnableEvent(const uint32_t event_msk) +{ + FLASH0->FCON |= event_msk; +} + +/* + * This API disables the event generation + */ +void XMC_FLASH_DisableEvent(const uint32_t event_msk) +{ + FLASH0->FCON &= ~event_msk; +} + +/* + * This API write the PFLASH page + */ +void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data) +{ + uint32_t idx; + + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lEnterPageModeCommand(); + + for (idx = 0U; idx < XMC_FLASH_WORDS_PER_PAGE; idx += 2U) + { + XMC_FLASH_lLoadPageCommand(data[idx], data[idx + 1U]); + } + + XMC_FLASH_lWritePageCommand(address); + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * This API erase the logical sector + */ +void XMC_FLASH_EraseSector(uint32_t *address) +{ + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lEraseSectorCommand(address); + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * Command to erase physical sector which is starting with the specified address + */ +void XMC_FLASH_lErasePhysicalSectorCommand(uint32_t *sector_start_address) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0x80U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = sector_start_address; + *address = 0x40U; +} + +/* + * Command to erase physical sector-4 which is starting with the specified address + * This command is only available if PROCON1.PRS = 1. + */ +void XMC_FLASH_lRepairPhysicalSectorCommand(void) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0x80U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = XMC_FLASH_PHY_SECTOR_4; + *address = 0x40U; +} + + /* + * This API erase the physical sector + */ +void XMC_FLASH_ErasePhysicalSector(uint32_t *address) +{ + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lErasePhysicalSectorCommand(address); + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * This API repair the physical sector + */ +void XMC_FLASH_RepairPhysicalSector(void) +{ + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lRepairPhysicalSectorCommand(); +} + +/* + * Command to erase UCB sector which is starting with the specified address + */ +void XMC_FLASH_EraseUCB(uint32_t *ucb_sector_start_address) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0x80U; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xaaU; + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U); + *address = 0x55U; + address = ucb_sector_start_address; + *address = 0xc0U; + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * Command to reset the status of the PFLASH + */ +void XMC_FLASH_Reset(void) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0xf0U; +} + +/* + * This API install the global read and sector write protection for the specified user + */ +void XMC_FLASH_InstallProtection(uint8_t user, + uint32_t protection_mask, + uint32_t password_0, + uint32_t password_1) +{ + uint32_t idx; + + XMC_ASSERT(" XMC_FLASH_ConfigureProtection: User level out of range", (user < 3U)) + + XMC_FLASH_lEnterPageModeCommand(); + + XMC_FLASH_lLoadPageCommand(protection_mask, 0UL); + XMC_FLASH_lLoadPageCommand(protection_mask, 0UL); + XMC_FLASH_lLoadPageCommand(password_0, password_1); + XMC_FLASH_lLoadPageCommand(password_0, password_1); + + for (idx = 0U; idx < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_PROTECTION_CONFIGURATION_WORDS); idx += 2U) + { + XMC_FLASH_lLoadPageCommand(0UL, 0UL); + } + + XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB0 + (user * XMC_FLASH_BYTES_PER_UCB))); + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * This API confirm the protection. So that This sectors are locked with the specified protection. + */ +void XMC_FLASH_ConfirmProtection(uint8_t user) +{ + uint32_t idx; + + XMC_ASSERT(" XMC_FLASH_ConfirmProtection: User level out of range", (user < 3U)) + + XMC_FLASH_lEnterPageModeCommand(); + + XMC_FLASH_lLoadPageCommand(XMC_FLASH_PROT_CONFIRM_CODE, 0U); + XMC_FLASH_lLoadPageCommand(XMC_FLASH_PROT_CONFIRM_CODE, 0U); + + /* Fill the rest of page buffer with zeros*/ + for (idx = 0UL; idx < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_PROT_CONFIRM_WORDS); idx += 2U) + { + XMC_FLASH_lLoadPageCommand(0UL, 0UL); + } + + XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB0 + + (user * XMC_FLASH_BYTES_PER_UCB) + XMC_FLASH_PROT_CONFIRM_OFFSET)); + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} +} + +/* + * This API verify read protection configuration. And returns true if passwords are matching. + */ +bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1) +{ + bool status = false; + + /* Check if read protection is installed */ + if ((XMC_FLASH_GetStatus() & (uint32_t)XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED) != 0U) + { + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lDisableReadProtectionCommand(password_0, password_1); + + status = (bool)(XMC_FLASH_GetStatus() & (uint32_t)XMC_FLASH_STATUS_READ_PROTECTION_DISABLED_STATE); + } + + return status; +} + +/* + * This API verify sector write protection configuration. And returns true if passwords are matching for the + * specified user. + */ +bool XMC_FLASH_VerifyWriteProtection(uint32_t user, + uint32_t protection_mask, + uint32_t password_0, + uint32_t password_1) +{ + bool status = false; + uint32_t *flash_procon_ptr = (uint32_t *)(void*)(&(FLASH0->PROCON0) + user); + + XMC_ASSERT(" XMC_FLASH_VerifyWriteProtection: User level out of range", (user < 2U)) + + /* Check if write protection for selected user is installed */ + if ((XMC_FLASH_GetStatus() & (uint32_t)((uint32_t)1U << (uint32_t)((uint32_t)FLASH_FSR_WPROIN0_Pos + user))) != 0U) + { + XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lDisableSectorWriteProtectionCommand(user, password_0, password_1); + + status = (bool)((XMC_FLASH_GetStatus() & (uint32_t)((uint32_t)1U << (uint32_t)((uint32_t)FLASH_FSR_WPRODIS0_Pos + user)))) && + (*flash_procon_ptr == (protection_mask & (uint32_t)(~(uint32_t)XMC_FLASH_PROTECTION_READ_GLOBAL))); + } + + return status; +} + +/* + * Command to enables the protection as it was configured + */ +void XMC_FLASH_ResumeProtection(void) +{ + volatile uint32_t *address; + + address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); + *address = 0x5eU; +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_gpio.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_gpio.c new file mode 100644 index 00000000..4c19ab14 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_gpio.c @@ -0,0 +1,105 @@ +/** + * @file xmc4_gpio.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * @endcond + * + */ + +#include "xmc_gpio.h" + +#if UC_FAMILY == XMC4 + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define PORT_PDR_Msk PORT0_PDR0_PD0_Msk +#define PORT_PDR_Size (4U) +#define PORT_HWSEL_Msk PORT0_HWSEL_HW0_Msk + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_GPIO_Init: Invalid port", XMC_GPIO_CHECK_PORT(port)); + XMC_ASSERT("XMC_GPIO_Init: Invalid mode", XMC_GPIO_IsModeValid(config->mode)); + + /* Switch to input */ + port->IOCR[pin >> 2U] &= (uint32_t)~(PORT_IOCR_PC_Msk << (PORT_IOCR_PC_Size * (pin & 0x3U))); + + /* HW port control is disabled */ + port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U)); + + + /* Enable digital input */ + if (XMC_GPIO_CHECK_ANALOG_PORT(port)) + { + port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin); + } + else + { + /* Set output level */ + port->OMR = (uint32_t)config->output_level << pin; + + /* Set output driver strength */ + port->PDR[pin >> 3U] &= (uint32_t)~(PORT_PDR_Msk << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U))); + port->PDR[pin >> 3U] |= (uint32_t)config->output_strength << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U)); + } + + /* Set mode */ + port->IOCR[pin >> 2U] |= (uint32_t)config->mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U)); +} + +void XMC_GPIO_SetOutputStrength(XMC_GPIO_PORT_t *const port, const uint8_t pin, XMC_GPIO_OUTPUT_STRENGTH_t strength) +{ + XMC_ASSERT("XMC_GPIO_Init: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); + XMC_ASSERT("XMC_GPIO_Init: Invalid output strength", XMC_GPIO_CHECK_OUTPUT_STRENGTH(strength)); + + port->PDR[pin >> 3U] &= (uint32_t)~((uint32_t)PORT_PDR_Msk << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U))); + port->PDR[pin >> 3U] |= (uint32_t)strength << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U)); +} + +#endif /* UC_FAMILY == XMC4 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_rtc.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_rtc.c new file mode 100644 index 00000000..a7b03ad4 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_rtc.c @@ -0,0 +1,170 @@ +/** + * @file xmc4_rtc.c + * @date 2016-03-09 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2016-03-09: + * - Optimize write only registers + * + * @endcond + * + */ + +/** + * @brief RTC driver for XMC microcontroller family. + * + */ + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ +#include + +#if UC_FAMILY == XMC4 +#include + +/********************************************************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ + +/* + * Enables RTC peripheral for programming its registers + */ +void XMC_RTC_Enable(void) +{ + XMC_SCU_HIB_EnableHibernateDomain(); +} + +/* + * Disables RTC peripheral for programming its registers + */ +void XMC_RTC_Disable(void) +{ + /* + * Empty because disabling the hibernate + * domain is not done intentionally. + */ +} + +/* + * Checks RTC peripheral is enabled for programming to its registers + */ +bool XMC_RTC_IsEnabled(void) +{ + return XMC_SCU_HIB_IsHibernateDomainEnabled(); +} + +/* + * Initialize the RTC peripheral + */ +XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config) +{ + if (XMC_RTC_IsRunning() == false) + { + if (XMC_SCU_HIB_IsHibernateDomainEnabled() == false) + { + XMC_SCU_HIB_EnableHibernateDomain(); + } + + XMC_RTC_SetPrescaler(config->prescaler); + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM0 = config->time.raw0; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM1 = config->time.raw1; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM0 = config->alarm.raw0; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM1 = config->alarm.raw1; + } + return XMC_RTC_STATUS_OK; +} + +/* + * Enable RTC periodic and alarm event(s) + */ +void XMC_RTC_EnableEvent(const uint32_t event) +{ + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->MSKSR |= event; +} + +/* + * Disable RTC periodic and alarm event(s) + */ +void XMC_RTC_DisableEvent(const uint32_t event) +{ + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->MSKSR &= ~event; +} + +/* + * Clear RTC periodic and alarm event(s) + */ +void XMC_RTC_ClearEvent(const uint32_t event) +{ + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->CLRSR = event; +} + +#endif /* UC_FAMILY == XMC4 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_scu.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_scu.c new file mode 100644 index 00000000..28dfec1d --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc4_scu.c @@ -0,0 +1,1820 @@ +/** + * @file xmc4_scu.c + * @date 2016-06-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - XMC_ASSERT() hanging issues have fixed.
+ * - Line indentation aligned with 120 characters.
+ * + * 2015-06-20: + * - XMC_SCU_INTERRUPT_EnableEvent,XMC_SCU_INTERRUPT_DisableEvent, + * - XMC_SCU_INTERRUPT_TriggerEvent,XMC_SCU_INTERUPT_GetEventStatus, + * - XMC_SCU_INTERRUPT_ClearEventStatus are added + * - Added Weak implementation for OSCHP_GetFrequency() + * + * 2015-11-30: + * - Documentation improved
+ * - Following API functionalities are improved + * XMC_SCU_CLOCK_GatePeripheralClock, XMC_SCU_CLOCK_UngatePeripheralClock, XMC_SCU_CLOCK_IsPeripheralClockGated + * XMC_SCU_RESET_AssertPeripheralReset, XMC_SCU_RESET_DeassertPeripheralReset, XMC_SCU_RESET_IsPeripheralResetAsserted + * + * 2015-12-08: + * - XMC_SCU_GetTemperature renamed to XMC_SCU_GetTemperatureMeasurement + * + * 2016-03-09: + * - Optimize write only registers + * - Added XMC_SCU_HIB_SetPinMode + * - Added XMC_SCU_HIB_GetHibernateControlStatus, + * XMC_SCU_HIB_GetEventStatus, XMC_SCU_HIB_ClearEventStatus, XMC_SCU_HIB_TriggerEvent, + * XMC_SCU_HIB_EnableEvent, XMC_SCU_HIB_DisableEvent + * - Added XMC_SCU_HIB_SetWakeupTriggerInput, XMC_SCU_HIB_SetPinMode, XMC_SCU_HIB_SetOutputPinLevel, + * XMC_SCU_HIB_SetInput0, XMC_SCU_HIB_EnterHibernateState + * + * 2016-04-06: + * - Fixed XMC_SCU_ReadFromRetentionMemory functionality + * + * 2016-05-19: + * - Changed XMC_SCU_CLOCK_StartSystemPll to avoid using floating point calculation which might have an impact on interrupt latency if ISR uses also the FPU + * - Added XMC_SCU_CLOCK_IsLowPowerOscillatorStable() and XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() + * - Added XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus() + * - Added XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(), + * XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus() + * + * 2016-06-15: + * - Added XMC_SCU_HIB_EnterHibernateStateEx() which allows to select between external or internal hibernate mode. This last mode only available in XMC44, XMC42 and XMC41 series. + * - Extended wakeup hibernate events using LPAC wakeup on events. Only available in XMC44, XMC42 and XMC41 series + * - Added LPAC APIs. Only available in XMC44, XMC42 and XMC41 series. + * + * @endcond + * + */ + +/** + * + * @brief SCU low level driver API prototype definition for XMC4 family of microcontrollers. + * + * Detailed description of file:
+ * APIs provided in this file cover the following functional blocks of SCU:
+ * -- GCU (APIs prefixed with XMC_SCU_GEN_)
+ * ------ Temperature Monitoring, Bootmode selection, CCU Start, Comparator configuration etc
+ * -- CCU (APIs prefixed with XMC_SCU_CLOCK_)
+ * ------ Clock sources init, Clock tree init, Clock gating, Sleep Management etc
+ * -- RCU (APIs prefixed with XMC_SCU_RESET_)
+ * ------ Reset Init, Cause, Manual Reset Assert/Deassert
+ * -- INTERRUPT (APIs prefixed with XMC_SCU_INTERRUPT_)
+ * ------ Init, Manual Assert/Deassert, Acknowledge etc
+ * -- PARITY (APIs prefixed with XMC_SCU_PARITY_)
+ * ------ Init, Acknowledge etc
+ * -- HIBERNATION (APIs prefixed with XMC_SCU_HIB_)
+ * ------ Hibernation entry/exit config, entry/wakeup sequences, LPAC configuration etc
+ * -- TRAP (APIs prefixed with XMC_SCU_TRAP_)
+ * ------ Init, Enable/Disable, Acknowledge etc
+ * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +#if UC_FAMILY == XMC4 + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define FOSCREF (2500000UL) /**< Oscillator reference frequency (fOSCREF) monitored by Oscillator watchdog */ +#define FREQ_1MHZ (1000000UL) /**< Used during calculation. */ + +#ifndef OFI_FREQUENCY +#define OFI_FREQUENCY (24000000UL) /**< Fast internal backup clock source. */ +#endif + +#ifndef OSI_FREQUENCY +#define OSI_FREQUENCY (32768UL) /**< Internal slow clock source. */ +#endif + +#ifndef OSCHP_FREQUENCY +#define OSCHP_FREQUENCY (12000000U) /**< External crystal High Precision Oscillator. */ +#endif + +#define XMC_SCU_PLL_PLLSTAT_OSC_USABLE (SCU_PLL_PLLSTAT_PLLHV_Msk | \ + SCU_PLL_PLLSTAT_PLLLV_Msk | \ + SCU_PLL_PLLSTAT_PLLSP_Msk) /**< Used to verify the OSC frequency is + usable or not.*/ + +#define XMC_SCU_ORC_ADC_START_GROUP (0UL) /**< The ADC group whose channel input is compared by Out of Range + Comparator (ORC) to serves the purpose of overvoltage monitoring + for analog input pins of the chip and ORC start measurements from + this group number. */ +#define XMC_SCU_ORC_ADC_END_GROUP (1UL) /**< The ADC group whose channel input is compared by Out of Range + Comparator (ORC) to serves the purpose of overvoltage monitoring + for analog input pins of the chip and ORC end measurements at + this group number. */ +#define XMC_SCU_ORC_START_ADC_CHANNEL (6UL) /**< The ADC channel whose channel input is compared by Out of Range + Comparator (ORC) to serves the purpose of overvoltage monitoring + for analog input pins of the chip and ORC start measurements from + this channel number. */ +#define XMC_SCU_ORC_END_ADC_CHANNEL (7UL) /**< The ADC channel whose channel input is compared by Out of Range + Comparator (ORC) to serves the purpose of overvoltage monitoring + for analog input pins of the chip and ORC ends measurements at + this channel number. */ + +#define XMC_SCU_CHECK_GRPNUM(GROUP_NUM) (((GROUP_NUM) == XMC_SCU_ORC_ADC_START_GROUP) || \ + ((GROUP_NUM) == XMC_SCU_ORC_ADC_END_GROUP) ) /**< Used to verify whether + provided ADC group number lies + within specified ADC start and + end group number or not. */ + +#define XMC_SCU_CHECK_CHNUM(CH_NUM) (((CH_NUM) == XMC_SCU_ORC_START_ADC_CHANNEL) || \ + ((CH_NUM) == XMC_SCU_ORC_END_ADC_CHANNEL) ) /**< Used to verify whether + provided ADC channel number lies + within specified ADC start and + end channel number or not. */ + +#define XMC_SCU_INTERRUPT_EVENT_MAX (32U) /**< Maximum supported SCU events. */ + +#define SCU_HIBERNATE_HDCR_HIBIOSEL_Size (4U) + +#define SCU_HIBERNATE_OSCULCTRL_MODE_OSC_POWER_DOWN (0x2U) + +#define XMC_SCU_POWER_LSB13V (0.0058F) +#define XMC_SCU_POWER_LSB33V (0.0225F) + +/********************************************************************************************************************* + * LOCAL DATA + ********************************************************************************************************************/ +XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler_list[XMC_SCU_INTERRUPT_EVENT_MAX]; /**< For registering callback + functions on SCU event + occurrence. */ + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ + #if defined(UC_ID) +/* This is a non-weak function, which retrieves high precision external oscillator frequency. */ +__WEAK uint32_t OSCHP_GetFrequency(void) +{ + return (OSCHP_FREQUENCY); +} +#endif + +/* This is a local function used to generate the delay until register get updated with new configured value. */ +static void XMC_SCU_lDelay(uint32_t cycles); + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ +/* This is a local function used to generate the delay until register get updated with new configured value. */ +void XMC_SCU_lDelay(uint32_t delay) +{ + uint32_t i; + + SystemCoreClockUpdate(); + delay = delay * (uint32_t)(SystemCoreClock / FREQ_1MHZ); + + for (i = 0U; i < delay; ++i) + { + __NOP(); + } +} + +/* API to enable the SCU event */ +void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event) +{ + SCU_INTERRUPT->SRMSK |= (uint32_t)event; +} + +/* API to disable the SCU event */ +void XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event) +{ + SCU_INTERRUPT->SRMSK &= (uint32_t)~event; +} + +/* API to trigger the SCU event */ +void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event) +{ + SCU_INTERRUPT->SRSET |= (uint32_t)event; +} + +/* API to retrieve the SCU event status */ +XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus(void) +{ + return (SCU_INTERRUPT->SRRAW); +} + +/* API to clear the SCU event status */ +void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event) +{ + SCU_INTERRUPT->SRCLR = (uint32_t)event; +} + + +/* API to retrieve the currently deployed device bootmode */ +uint32_t XMC_SCU_GetBootMode(void) +{ + return (uint32_t)(SCU_GENERAL->STCON & SCU_GENERAL_STCON_SWCON_Msk); +} + +/* API to program a new device bootmode */ +void XMC_SCU_SetBootMode(const XMC_SCU_BOOTMODE_t bootmode) +{ + SCU_GENERAL->STCON = (uint32_t)bootmode; +} + +/* API to read from General purpose register */ +uint32_t XMC_SCU_ReadGPR(const uint32_t index) +{ + return (SCU_GENERAL->GPR[index]); +} + +/* API to write to GPR */ +void XMC_SCU_WriteGPR(const uint32_t index, const uint32_t data) +{ + SCU_GENERAL->GPR[index] = data; +} + +/* API to enable Out of Range Comparator(ORC) for a desired group and a desired channel input */ +void XMC_SCU_EnableOutOfRangeComparator(const uint32_t group, const uint32_t channel) +{ + XMC_ASSERT("XMC_SCU_EnableOutOfangeComparator:Wrong Group Number",XMC_SCU_CHECK_GRPNUM(group)); + XMC_ASSERT("XMC_SCU_EnableOutOfangeComparator:Wrong Channel Number",XMC_SCU_CHECK_CHNUM(channel)); + + SCU_GENERAL->GORCEN[group] |= (uint32_t)(1UL << channel); +} + +/* API to enable Out of Range Comparator(ORC) for a desired group and a desired channel input */ +void XMC_SCU_DisableOutOfRangeComparator(const uint32_t group, const uint32_t channel) +{ + XMC_ASSERT("XMC_SCU_DisableOutOfRangeComparator:Wrong Group Number",XMC_SCU_CHECK_GRPNUM(group)); + XMC_ASSERT("XMC_SCU_DisableOutOfRangeComparator:Wrong Channel Number",XMC_SCU_CHECK_CHNUM(channel)); + + SCU_GENERAL->GORCEN[group] &= (uint32_t)~(1UL << channel); +} + +/* API to calibrate temperature sensor */ +void XMC_SCU_CalibrateTemperatureSensor(uint32_t offset, uint32_t gain) +{ + SCU_GENERAL->DTSCON = ((uint32_t)(offset << SCU_GENERAL_DTSCON_OFFSET_Pos) | + (uint32_t)(gain << SCU_GENERAL_DTSCON_GAIN_Pos) | + (uint32_t)(0x4UL << SCU_GENERAL_DTSCON_REFTRIM_Pos) | + (uint32_t)(0x8UL << SCU_GENERAL_DTSCON_BGTRIM_Pos)); +} +/* API to enable die temperature measurement by powering the DTS module. */ +void XMC_SCU_EnableTemperatureSensor(void) +{ + SCU_GENERAL->DTSCON &= (uint32_t)~(SCU_GENERAL_DTSCON_PWD_Msk); +} + +/* API to disable die temperature measurement by powering the DTS module off. */ +void XMC_SCU_DisableTemperatureSensor(void) +{ + SCU_GENERAL->DTSCON |= (uint32_t)SCU_GENERAL_DTSCON_PWD_Msk; +} + +/* API to provide the die temperature sensor power status. */ +bool XMC_SCU_IsTemperatureSensorEnabled(void) +{ + return ((SCU_GENERAL->DTSCON & SCU_GENERAL_DTSCON_PWD_Msk) == 0U); +} + +/* API to check if the die temperature sensor is ready to start a measurement. */ +bool XMC_SCU_IsTemperatureSensorReady(void) +{ + return ((SCU_GENERAL->DTSSTAT & SCU_GENERAL_DTSSTAT_RDY_Msk) != 0U); +} +/* API to start device temperature measurements */ +XMC_SCU_STATUS_t XMC_SCU_StartTemperatureMeasurement(void) +{ + XMC_SCU_STATUS_t status = XMC_SCU_STATUS_OK; + + if (XMC_SCU_IsTemperatureSensorEnabled() == false) + { + status = XMC_SCU_STATUS_ERROR; + } + + if (XMC_SCU_IsTemperatureSensorBusy() == true) + { + status = XMC_SCU_STATUS_BUSY; + } + + /* And start the measurement */ + SCU_GENERAL->DTSCON |= (uint32_t)SCU_GENERAL_DTSCON_START_Msk; + + return (status); +} + +/* API to retrieve the temperature measured */ +uint32_t XMC_SCU_GetTemperatureMeasurement(void) +{ + uint32_t temperature; + + if (XMC_SCU_IsTemperatureSensorEnabled() == false) + { + temperature = 0x7FFFFFFFUL; + } + else + { + temperature = (uint32_t)((SCU_GENERAL->DTSSTAT & SCU_GENERAL_DTSSTAT_RESULT_Msk) >> SCU_GENERAL_DTSSTAT_RESULT_Pos); + } + + return ((uint32_t)temperature); +} + +/* API to know whether Die temperature sensor is busy */ +bool XMC_SCU_IsTemperatureSensorBusy(void) +{ + return ((SCU_GENERAL->DTSSTAT & SCU_GENERAL_DTSSTAT_BUSY_Msk) != 0U); +} + + +#if defined(SCU_GENERAL_DTEMPLIM_LOWER_Msk) && defined(SCU_GENERAL_DTEMPLIM_UPPER_Msk) +/* API to determine if device temperature has gone past the ceiling */ +bool XMC_SCU_HighTemperature(void) +{ + bool ret_val; + uint32_t dtscon; + uint32_t dtempalarm; + dtscon = SCU_GENERAL->DTSCON; + dtscon = dtscon & SCU_GENERAL_DTSCON_PWD_Msk; + + ret_val = false; + + /* Any audit makes sense only if the DTS were powered up */ + if(dtscon) + { + /* Powered down - return false */ + ret_val = false; + } + else + { + /* Powered up - Read the overflow bit and decide accordingly*/ + dtempalarm = SCU_GENERAL->DTEMPALARM; + dtempalarm = dtempalarm & SCU_GENERAL_DTEMPALARM_OVERFL_Msk; + + if(dtempalarm) + { + ret_val = true; + } + else + { + ret_val = false; + } + } + return (ret_val); +} + +/* API to program raw values of temperature limits into the DTS */ +void XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp) +{ + /* Power up the DTS module */ + SCU_GENERAL->DTSCON &= (uint32_t)~SCU_GENERAL_DTSCON_PWD_Msk; + SCU_GENERAL->DTEMPLIM = 0; + SCU_GENERAL->DTEMPLIM = (lower_temp & SCU_GENERAL_DTEMPLIM_LOWER_Msk); + SCU_GENERAL->DTEMPLIM |= (uint32_t)((upper_temp & SCU_GENERAL_DTEMPLIM_LOWER_Msk) << SCU_GENERAL_DTEMPLIM_UPPER_Pos); +} + +/* API to determine if device temperature has gone below the stipulated limit */ +bool XMC_SCU_LowTemperature(void) +{ + bool ret_val; + uint32_t dtscon; + uint32_t dtempalarm; + dtscon = SCU_GENERAL->DTSCON; + dtscon = dtscon & SCU_GENERAL_DTSCON_PWD_Msk; + + ret_val = false; + + /* Any audit makes sense only if the DTS were powered up */ + if(dtscon) + { + /* Powered down - return false */ + ret_val = false; + } + else + { + /* Powered up - Read the overflow bit and decide accordingly*/ + dtempalarm = SCU_GENERAL->DTEMPALARM; + dtempalarm = dtempalarm & SCU_GENERAL_DTEMPALARM_UNDERFL_Msk; + + if(dtempalarm) + { + ret_val = true; + } + else + { + ret_val = false; + } + } + + return (ret_val); +} +#endif + +/* API to write into Retention memory in hibernate domain */ +void XMC_SCU_WriteToRetentionMemory(uint32_t address, uint32_t data) +{ + uint32_t rmacr; + + /* Get the address right */ + rmacr = (uint32_t)((address << SCU_GENERAL_RMACR_ADDR_Pos) & (uint32_t)SCU_GENERAL_RMACR_ADDR_Msk); + + /* Transfer from RMDATA to Retention memory */ + rmacr |= (uint32_t)(SCU_GENERAL_RMACR_RDWR_Msk); + + /* Write desired data into RMDATA register */ + SCU_GENERAL->RMDATA = data; + + /* Write address & direction of transfer into RMACR register */ + SCU_GENERAL->RMACR = rmacr; + + /* Wait until the update of RMX register in hibernate domain is completed */ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_RMX_Msk) + { + } +} + +/* API to read from Retention memory in hibernate domain */ +uint32_t XMC_SCU_ReadFromRetentionMemory(uint32_t address) +{ + uint32_t rmacr; + + /* Get the address right */ + rmacr = ((uint32_t)(address << SCU_GENERAL_RMACR_ADDR_Pos) & (uint32_t)SCU_GENERAL_RMACR_ADDR_Msk); + + /* Transfer from RMDATA to Retention memory */ + rmacr &= ~((uint32_t)(SCU_GENERAL_RMACR_RDWR_Msk)); + + /* Writing an adress & direction of transfer into RMACR register */ + SCU_GENERAL->RMACR = rmacr; + + /* Wait until the update of RMX register in hibernate domain is completed */ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_RMX_Msk) + { + } + + return (SCU_GENERAL->RMDATA); +} + +/* API to initialize the clock tree */ +void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config) +{ + XMC_ASSERT("", config->fsys_clkdiv != 0); + XMC_ASSERT("", config->fcpu_clkdiv != 0); + XMC_ASSERT("", config->fccu_clkdiv != 0); + XMC_ASSERT("", config->fperipheral_clkdiv != 0); + XMC_ASSERT("", ((config->syspll_config.p_div != 0) && + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL)) || + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR)); + XMC_ASSERT("", ((config->syspll_config.n_div != 0) && + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL)) || + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR)); + XMC_ASSERT("", (config->syspll_config.k_div != 0) && + ((config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL) || + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR))); + XMC_ASSERT("", ((config->fsys_clksrc == XMC_SCU_CLOCK_SYSCLKSRC_PLL) || + (config->fsys_clksrc == XMC_SCU_CLOCK_SYSCLKSRC_OFI)) && + ((config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL) || + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR))); + XMC_ASSERT("", ((config->fstdby_clksrc == XMC_SCU_HIB_STDBYCLKSRC_OSCULP) && (config->enable_osculp == true)) || + (config->fstdby_clksrc != XMC_SCU_HIB_STDBYCLKSRC_OSCULP)); + XMC_ASSERT("", ((config->syspll_config.clksrc == XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP) && + (config->enable_oschp == true)) || (config->syspll_config.clksrc != XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP)); + + XMC_SCU_CLOCK_SetSystemClockSource(XMC_SCU_CLOCK_SYSCLKSRC_OFI); + + XMC_SCU_HIB_EnableHibernateDomain(); + if (config->enable_osculp == true) + { + XMC_SCU_CLOCK_EnableLowPowerOscillator(); + while(XMC_SCU_CLOCK_IsLowPowerOscillatorStable() == false); + } + XMC_SCU_HIB_SetStandbyClockSource(config->fstdby_clksrc); + + XMC_SCU_CLOCK_SetBackupClockCalibrationMode(config->calibration_mode); + + XMC_SCU_CLOCK_SetSystemClockDivider((uint32_t)config->fsys_clkdiv); + XMC_SCU_CLOCK_SetCpuClockDivider((uint32_t)config->fcpu_clkdiv); + XMC_SCU_CLOCK_SetCcuClockDivider((uint32_t)config->fccu_clkdiv); + XMC_SCU_CLOCK_SetPeripheralClockDivider((uint32_t)config->fperipheral_clkdiv); + + if (config->enable_oschp == true) + { + XMC_SCU_CLOCK_EnableHighPerformanceOscillator(); + while(XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() == false); + } + + if (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_DISABLED) + { + XMC_SCU_CLOCK_DisableSystemPll(); + } + else + { + + XMC_SCU_CLOCK_EnableSystemPll(); + XMC_SCU_CLOCK_StartSystemPll(config->syspll_config.clksrc, + config->syspll_config.mode, + (uint32_t)config->syspll_config.p_div, + (uint32_t)config->syspll_config.n_div, + (uint32_t)config->syspll_config.k_div); + } + + /* use SYSPLL? */ + if (config->fsys_clksrc == XMC_SCU_CLOCK_SYSCLKSRC_PLL) + { + XMC_SCU_CLOCK_SetSystemClockSource(XMC_SCU_CLOCK_SYSCLKSRC_PLL); + } + SystemCoreClockUpdate(); +} + +/* API to enable a trap source */ +void XMC_SCU_TRAP_Enable(const uint32_t trap) +{ + SCU_TRAP->TRAPDIS &= (uint32_t)~trap; +} + +/* API to disable a trap source */ +void XMC_SCU_TRAP_Disable(const uint32_t trap) +{ + SCU_TRAP->TRAPDIS |= (uint32_t)trap; +} + +/* API to determine if a trap source has generated event */ +uint32_t XMC_SCU_TRAP_GetStatus(void) +{ + return (SCU_TRAP->TRAPRAW); +} + +/* API to manually trigger a trap event */ +void XMC_SCU_TRAP_Trigger(const uint32_t trap) +{ + SCU_TRAP->TRAPSET = (uint32_t)trap; +} + +/* API to clear a trap event */ +void XMC_SCU_TRAP_ClearStatus(const uint32_t trap) +{ + SCU_TRAP->TRAPCLR = (uint32_t)trap; +} + +/* API to clear parity error event */ +void XMC_SCU_PARITY_ClearStatus(const uint32_t memory) +{ + SCU_PARITY->PEFLAG |= (uint32_t)memory; +} + +/* API to determine if the specified parity error has occured or not */ +uint32_t XMC_SCU_PARITY_GetStatus(void) +{ + return (SCU_PARITY->PEFLAG); +} + +/* API to enable parity error checking for the selected on-chip RAM type */ +void XMC_SCU_PARITY_Enable(const uint32_t memory) +{ + SCU_PARITY->PEEN |= (uint32_t)memory; +} + +/* API to disable parity error checking for the selected on-chip RAM type */ +void XMC_SCU_PARITY_Disable(const uint32_t memory) +{ + SCU_PARITY->PEEN &= (uint32_t)~memory; +} + +/* API to enable trap assertion for the parity error source */ +void XMC_SCU_PARITY_EnableTrapGeneration(const uint32_t memory) +{ + SCU_PARITY->PETE |= (uint32_t)memory; +} + +/* API to disable the assertion of trap for the parity error source */ +void XMC_SCU_PARITY_DisableTrapGeneration(const uint32_t memory) +{ + SCU_PARITY->PETE &= (uint32_t)~memory; +} + +/* Enables a NMI source */ +void XMC_SCU_INTERRUPT_EnableNmiRequest(const uint32_t request) +{ + SCU_INTERRUPT->NMIREQEN |= (uint32_t)request; +} + +/* Disables a NMI source */ +void XMC_SCU_INTERRUPT_DisableNmiRequest(const uint32_t request) +{ + SCU_INTERRUPT->NMIREQEN &= (uint32_t)~request; +} + +/* API to manually assert a reset request */ +void XMC_SCU_RESET_AssertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peripheral) +{ + uint32_t index = (uint32_t)((((uint32_t)peripheral) & 0xf0000000UL) >> 28UL); + uint32_t mask = (((uint32_t)peripheral) & ((uint32_t)~0xf0000000UL)); + + *(uint32_t *)(&(SCU_RESET->PRSET0) + (index * 3U)) = (uint32_t)mask; +} + +/* API to manually de-assert a reset request */ +void XMC_SCU_RESET_DeassertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peripheral) +{ + uint32_t index = (uint32_t)((((uint32_t)peripheral) & 0xf0000000UL) >> 28UL); + uint32_t mask = (((uint32_t)peripheral) & ((uint32_t)~0xf0000000UL)); + + *(uint32_t *)(&(SCU_RESET->PRCLR0) + (index * 3U)) = (uint32_t)mask; +} + +/* Find out if the peripheral reset is asserted */ +bool XMC_SCU_RESET_IsPeripheralResetAsserted(const XMC_SCU_PERIPHERAL_RESET_t peripheral) +{ + uint32_t index = (uint32_t)((((uint32_t)peripheral) & 0xf0000000UL) >> 28UL); + uint32_t mask = (((uint32_t)peripheral) & ((uint32_t)~0xf0000000UL)); + + return ((*(uint32_t *)(&(SCU_RESET->PRSTAT0) + (index * 3U)) & mask) != 0U); +} + +/* + * API to retrieve frequency of System PLL output clock + */ +uint32_t XMC_SCU_CLOCK_GetSystemPllClockFrequency(void) +{ + uint32_t clock_frequency; + uint32_t p_div; + uint32_t n_div; + uint32_t k2_div; + + clock_frequency = XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency(); + if(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) + { + /* Prescalar mode - fOSC is the parent*/ + clock_frequency = (uint32_t)(clock_frequency / + ((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1UL)); + } + else + { + p_div = (uint32_t)((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1UL); + n_div = (uint32_t)((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1UL); + k2_div = (uint32_t)((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1UL); + + clock_frequency = (clock_frequency * n_div) / (p_div * k2_div); + } + + return (clock_frequency); +} + +/** + * API to retrieve frequency of System PLL VCO input clock + */ +uint32_t XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency(void) +{ + uint32_t clock_frequency; + + /* Prescalar mode - fOSC is the parent*/ + if((SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk) == (uint32_t)XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP) + { + clock_frequency = OSCHP_GetFrequency(); + } + else + { + clock_frequency = OFI_FREQUENCY; + } + + return (clock_frequency); +} + +/* + * API to retrieve frequency of USB PLL output clock + */ +uint32_t XMC_SCU_CLOCK_GetUsbPllClockFrequency(void) +{ + uint32_t clock_frequency; + uint32_t n_div; + uint32_t p_div; + + clock_frequency = OSCHP_GetFrequency(); + if((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOBYST_Msk) == 0U) + { + /* Normal mode - fVCO is the parent*/ + n_div = (uint32_t)((((SCU_PLL->USBPLLCON) & SCU_PLL_USBPLLCON_NDIV_Msk) >> SCU_PLL_USBPLLCON_NDIV_Pos) + 1UL); + p_div = (uint32_t)((((SCU_PLL->USBPLLCON) & SCU_PLL_USBPLLCON_PDIV_Msk) >> SCU_PLL_USBPLLCON_PDIV_Pos) + 1UL); + clock_frequency = (uint32_t)((clock_frequency * n_div)/ (uint32_t)(p_div * 2UL)); + } + return (clock_frequency); +} + +/* + * API to retrieve frequency of CCU clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetCcuClockFrequency(void) +{ + uint32_t frequency = 0UL; + frequency = XMC_SCU_CLOCK_GetSystemClockFrequency(); + + return (uint32_t)(frequency >> ((uint32_t)((SCU_CLK->CCUCLKCR & SCU_CLK_CCUCLKCR_CCUDIV_Msk) >> + SCU_CLK_CCUCLKCR_CCUDIV_Pos))); +} + +/* + * API to retrieve USB and SDMMC clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetUsbClockFrequency(void) +{ + uint32_t frequency = 0UL; + XMC_SCU_CLOCK_USBCLKSRC_t clksrc; + + clksrc = XMC_SCU_CLOCK_GetUsbClockSource(); + + if (clksrc == XMC_SCU_CLOCK_USBCLKSRC_SYSPLL) + { + frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); + } + else if (clksrc == XMC_SCU_CLOCK_USBCLKSRC_USBPLL) + { + frequency = XMC_SCU_CLOCK_GetUsbPllClockFrequency(); + } + else + { + } + + return (uint32_t)(frequency / (((SCU_CLK->USBCLKCR & SCU_CLK_USBCLKCR_USBDIV_Msk) >> + SCU_CLK_USBCLKCR_USBDIV_Pos) + 1UL)); +} + +#if defined(EBU) +/* + * API to retrieve EBU clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetEbuClockFrequency(void) +{ + uint32_t frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); + + return (uint32_t)((frequency /(((SCU_CLK->EBUCLKCR & SCU_CLK_EBUCLKCR_EBUDIV_Msk) >> + SCU_CLK_EBUCLKCR_EBUDIV_Pos) + 1UL))); +} +#endif + +#if defined(ECAT0) +/* + * API to retrieve ECAT clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetECATClockFrequency(void) +{ + uint32_t frequency; + + if ((SCU_CLK->ECATCLKCR & SCU_CLK_ECATCLKCR_ECATSEL_Msk) != 0U) + { + frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); + } + else + { + frequency = XMC_SCU_CLOCK_GetUsbPllClockFrequency(); + } + + return (uint32_t)((frequency / (XMC_SCU_CLOCK_GetECATClockDivider() + 1UL))); +} +#endif + +/* + * API to retrieve WDT clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetWdtClockFrequency(void) +{ + uint32_t frequency = 0UL; + XMC_SCU_CLOCK_WDTCLKSRC_t clksrc; + + clksrc = XMC_SCU_CLOCK_GetWdtClockSource(); + + if (clksrc == XMC_SCU_CLOCK_WDTCLKSRC_PLL) + { + frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); + } + else if (clksrc == XMC_SCU_CLOCK_WDTCLKSRC_OFI) + { + frequency = OFI_FREQUENCY; + } + else if (clksrc == XMC_SCU_CLOCK_WDTCLKSRC_STDBY) + { + frequency = OSI_FREQUENCY; + } + else + { + + } + + return (uint32_t)((frequency / (((SCU_CLK->WDTCLKCR & SCU_CLK_WDTCLKCR_WDTDIV_Msk) >> + SCU_CLK_WDTCLKCR_WDTDIV_Pos) + 1UL))); +} + +/** + * @brief API to retrieve EXTERNAL-OUT clock frequency + * @retval Clock frequency + */ +uint32_t XMC_SCU_CLOCK_GetExternalOutputClockFrequency(void) +{ + uint32_t frequency = 0UL; + XMC_SCU_CLOCK_EXTOUTCLKSRC_t clksrc; + + clksrc = XMC_SCU_CLOCK_GetExternalOutputClockSource(); + + if (clksrc == XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL) + { + frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); + + frequency = (uint32_t)((frequency / ((((SCU_CLK->EXTCLKCR) & SCU_CLK_EXTCLKCR_ECKDIV_Msk) >> + SCU_CLK_EXTCLKCR_ECKDIV_Pos)+ 1UL))); + } + else if (clksrc == XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS) + { + frequency = XMC_SCU_CLOCK_GetSystemClockFrequency(); + } + else if (clksrc == XMC_SCU_CLOCK_EXTOUTCLKSRC_USB) + { + frequency = XMC_SCU_CLOCK_GetUsbPllClockFrequency(); + + frequency = (uint32_t)((frequency / ((((SCU_CLK->EXTCLKCR) & SCU_CLK_EXTCLKCR_ECKDIV_Msk) >> + SCU_CLK_EXTCLKCR_ECKDIV_Pos)+ 1UL))); + } + else + { + + } + + return (frequency); +} + +/* + * API to retrieve clock frequency of peripherals on the peripheral bus using a shared functional clock + */ +uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void) +{ + return (uint32_t)(XMC_SCU_CLOCK_GetCpuClockFrequency() >> + ((SCU_CLK->PBCLKCR & SCU_CLK_PBCLKCR_PBDIV_Msk) >> SCU_CLK_PBCLKCR_PBDIV_Pos)); +} + +/* API to select fSYS */ +void XMC_SCU_CLOCK_SetSystemClockSource(const XMC_SCU_CLOCK_SYSCLKSRC_t source) +{ + SCU_CLK->SYSCLKCR = (SCU_CLK->SYSCLKCR & ((uint32_t)~SCU_CLK_SYSCLKCR_SYSSEL_Msk)) | + ((uint32_t)source); +} + +/* API to select fUSB */ +void XMC_SCU_CLOCK_SetUsbClockSource(const XMC_SCU_CLOCK_USBCLKSRC_t source) +{ + SCU_CLK->USBCLKCR = (SCU_CLK->USBCLKCR & ((uint32_t)~SCU_CLK_USBCLKCR_USBSEL_Msk)) | + ((uint32_t)source); +} + +/* API to select fWDT */ +void XMC_SCU_CLOCK_SetWdtClockSource(const XMC_SCU_CLOCK_WDTCLKSRC_t source) +{ + SCU_CLK->WDTCLKCR = (SCU_CLK->WDTCLKCR & ((uint32_t)~SCU_CLK_WDTCLKCR_WDTSEL_Msk)) | + ((uint32_t)source); +} + +/* API to select fEXT */ +void XMC_SCU_CLOCK_SetExternalOutputClockSource(const XMC_SCU_CLOCK_EXTOUTCLKSRC_t source) +{ + SCU_CLK->EXTCLKCR = (SCU_CLK->EXTCLKCR & ((uint32_t)~SCU_CLK_EXTCLKCR_ECKSEL_Msk)) | + ((uint32_t)source); +} + +/* API to select fPLL */ +void XMC_SCU_CLOCK_SetSystemPllClockSource(const XMC_SCU_CLOCK_SYSPLLCLKSRC_t source) +{ + /* Check input clock */ + if (source == XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP) /* Select PLLClockSource */ + { + SCU_PLL->PLLCON2 &= (uint32_t)~(SCU_PLL_PLLCON2_PINSEL_Msk | SCU_PLL_PLLCON2_K1INSEL_Msk); + } + else + { + SCU_PLL->PLLCON2 |= (uint32_t)(SCU_PLL_PLLCON2_PINSEL_Msk | SCU_PLL_PLLCON2_K1INSEL_Msk); + } +} + +/* API to select fRTC */ +void XMC_SCU_HIB_SetRtcClockSource(const XMC_SCU_HIB_RTCCLKSRC_t source) +{ + /* Wait until the update of HDCR register in hibernate domain is completed */ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + } + + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ((uint32_t)~SCU_HIBERNATE_HDCR_RCS_Msk)) | + ((uint32_t)source); +} + +/* API to select fSTDBY */ +void XMC_SCU_HIB_SetStandbyClockSource(const XMC_SCU_HIB_STDBYCLKSRC_t source) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ((uint32_t)~SCU_HIBERNATE_HDCR_STDBYSEL_Msk)) | + ((uint32_t)source); +} + +/* API to program the divider placed between fsys and its parent */ +void XMC_SCU_CLOCK_SetSystemClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetSystemClockDivider:Wrong clock divider value", + (divider <= (SCU_CLK_SYSCLKCR_SYSDIV_Msk + 1UL)) ); + + SCU_CLK->SYSCLKCR = (SCU_CLK->SYSCLKCR & ((uint32_t)~SCU_CLK_SYSCLKCR_SYSDIV_Msk)) | + ((uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_SYSCLKCR_SYSDIV_Pos)); +} + +/* API to program the divider placed between fccu and its parent */ +void XMC_SCU_CLOCK_SetCcuClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetCapcomClockDivider:Wrong clock divider value", (divider <= 2UL) ); + + SCU_CLK->CCUCLKCR = (SCU_CLK->CCUCLKCR & ((uint32_t)~SCU_CLK_CCUCLKCR_CCUDIV_Msk)) | + (uint32_t)((uint32_t)(divider - 1UL) << SCU_CLK_CCUCLKCR_CCUDIV_Pos); +} + +/* API to program the divider placed between fcpu and its parent */ +void XMC_SCU_CLOCK_SetCpuClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetCpuClockDivider:Wrong clock divider value", (divider <= 2UL) ); + + SCU_CLK->CPUCLKCR = (SCU_CLK->CPUCLKCR & ((uint32_t)~SCU_CLK_CPUCLKCR_CPUDIV_Msk)) | + (uint32_t)((uint32_t)(divider - 1UL) << SCU_CLK_CPUCLKCR_CPUDIV_Pos); +} + +/* API to program the divider placed between fperiph and its parent */ +void XMC_SCU_CLOCK_SetPeripheralClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetPeripheralClockDivider:Wrong clock divider value", (divider <= 2UL) ); + + SCU_CLK->PBCLKCR = (SCU_CLK->PBCLKCR & ((uint32_t)~SCU_CLK_PBCLKCR_PBDIV_Msk)) | + ((uint32_t)((uint32_t)(divider - 1UL) << SCU_CLK_PBCLKCR_PBDIV_Pos)); +} + +/* API to program the divider placed between fsdmmc and its parent */ +void XMC_SCU_CLOCK_SetUsbClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetSdmmcClockDivider:Wrong clock divider value", + (divider <= (SCU_CLK_USBCLKCR_USBDIV_Msk + 1UL)) ); + + SCU_CLK->USBCLKCR = (SCU_CLK->USBCLKCR & ((uint32_t)~SCU_CLK_USBCLKCR_USBDIV_Msk)) | + (uint32_t)((uint32_t)(divider - 1UL) << SCU_CLK_USBCLKCR_USBDIV_Pos); +} + +#if defined(EBU) +/* API to program the divider placed between febu and its parent */ +void XMC_SCU_CLOCK_SetEbuClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetEbuClockDivider:Wrong clock divider value", + (divider <= (SCU_CLK_EBUCLKCR_EBUDIV_Msk + 1UL) ) ); + + SCU_CLK->EBUCLKCR = (SCU_CLK->EBUCLKCR & ((uint32_t)~SCU_CLK_EBUCLKCR_EBUDIV_Msk)) | + (uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_EBUCLKCR_EBUDIV_Pos); +} +#endif + +/* API to program the divider placed between fwdt and its parent */ +void XMC_SCU_CLOCK_SetWdtClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetWdtClockDivider:Wrong clock divider value", + (divider <= (SCU_CLK_WDTCLKCR_WDTDIV_Msk + 1UL) ) ); + + SCU_CLK->WDTCLKCR = (SCU_CLK->WDTCLKCR & ((uint32_t)~SCU_CLK_WDTCLKCR_WDTDIV_Msk)) | + (uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_WDTCLKCR_WDTDIV_Pos); +} + +/* API to program the divider placed between fext and its parent */ +void XMC_SCU_CLOCK_SetExternalOutputClockDivider(const uint32_t divider) +{ + XMC_ASSERT("XMC_SCU_CLOCK_SetExternalOutputClockDivider:Wrong clock divider value", + (divider <= (SCU_CLK_EXTCLKCR_ECKDIV_Msk + 1UL) ) ); + + SCU_CLK->EXTCLKCR = (SCU_CLK->EXTCLKCR & ((uint32_t)~SCU_CLK_EXTCLKCR_ECKDIV_Msk)) | + (uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_EXTCLKCR_ECKDIV_Pos); +} + +#if defined(ECAT0) +/* API to configure the ECAT clock by setting the clock divider for the ECAT clock source */ +void XMC_SCU_CLOCK_SetECATClockDivider(const uint32_t divider) +{ + SCU_CLK->ECATCLKCR = (SCU_CLK->ECATCLKCR & ~SCU_CLK_ECATCLKCR_ECADIV_Msk) | + (uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_ECATCLKCR_ECADIV_Pos); +} +#endif + +/* API to enable a given module clock */ +void XMC_SCU_CLOCK_EnableClock(const XMC_SCU_CLOCK_t clock) +{ + SCU_CLK->CLKSET = ((uint32_t)clock); +} + +/* API to disable a given module clock */ +void XMC_SCU_CLOCK_DisableClock(const XMC_SCU_CLOCK_t clock) +{ + SCU_CLK->CLKCLR = ((uint32_t)clock); +} + +/* API to determine if module clock of the given peripheral is enabled */ +bool XMC_SCU_CLOCK_IsClockEnabled(const XMC_SCU_CLOCK_t clock) +{ + return (bool)(SCU_CLK->CLKSTAT & ((uint32_t)clock)); +} + +#if defined(CLOCK_GATING_SUPPORTED) +/* API to gate a given module clock */ +void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral) +{ + uint32_t index = (peripheral & 0xf0000000UL) >> 28UL; + uint32_t mask = (peripheral & (uint32_t)~0xf0000000UL); + + *(uint32_t *)((&(SCU_CLK->CGATSET0)) + (index * 3U)) = (uint32_t)mask; +} + +/* API to ungate a given module clock */ +void XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral) +{ + uint32_t index = (uint32_t)((peripheral & 0xf0000000UL) >> 28UL); + uint32_t mask = (peripheral & (uint32_t)~0xf0000000UL); + + *(uint32_t *)(&(SCU_CLK->CGATCLR0) + (index * 3U)) = (uint32_t)mask; +} + +/* API to ungate a given module clock */ +bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral) +{ + uint32_t index = ((peripheral & 0xf0000000UL) >> 28UL); + uint32_t mask = (peripheral & (uint32_t)~0xf0000000UL); + + return ((*(uint32_t *)(&(SCU_CLK->CGATSTAT0) + (index * 3U)) & mask) != 0U); +} +#endif + +float XMC_SCU_POWER_GetEVR13Voltage(void) +{ + return (SCU_POWER->EVRVADCSTAT & SCU_POWER_EVRVADCSTAT_VADC13V_Msk) * XMC_SCU_POWER_LSB13V; +} + +float XMC_SCU_POWER_GetEVR33Voltage(void) +{ + return ((SCU_POWER->EVRVADCSTAT & SCU_POWER_EVRVADCSTAT_VADC33V_Msk) >> SCU_POWER_EVRVADCSTAT_VADC33V_Pos) * XMC_SCU_POWER_LSB33V; +} + +/* API to enable USB PLL for USB clock */ +void XMC_SCU_CLOCK_EnableUsbPll(void) +{ + SCU_PLL->USBPLLCON &= (uint32_t)~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* API to disable USB PLL for USB clock */ +void XMC_SCU_CLOCK_DisableUsbPll(void) +{ + SCU_PLL->USBPLLCON |= (uint32_t)(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* API to configure USB PLL */ +void XMC_SCU_CLOCK_StartUsbPll(uint32_t pdiv, uint32_t ndiv) +{ + /* Go to bypass the USB PLL */ + SCU_PLL->USBPLLCON |= (uint32_t)SCU_PLL_USBPLLCON_VCOBYP_Msk; + + /* disconnect Oscillator from USB PLL */ + SCU_PLL->USBPLLCON |= (uint32_t)SCU_PLL_USBPLLCON_FINDIS_Msk; + + /* Setup Divider settings for USB PLL */ + SCU_PLL->USBPLLCON = (uint32_t)((uint32_t)((ndiv -1U) << SCU_PLL_USBPLLCON_NDIV_Pos) | + (uint32_t)((pdiv - 1U) << SCU_PLL_USBPLLCON_PDIV_Pos)); + + /* Set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= (uint32_t)SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + + /* connect Oscillator to USB PLL */ + SCU_PLL->USBPLLCON &= (uint32_t)~SCU_PLL_USBPLLCON_FINDIS_Msk; + + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= (uint32_t)SCU_PLL_USBPLLCON_RESLD_Msk; + + while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U) + { + /* wait for PLL Lock */ + } + +} + +/* API to disable USB PLL operation */ +void XMC_SCU_CLOCK_StopUsbPll(void) +{ + SCU_PLL->USBPLLCON = (uint32_t)(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk | + SCU_PLL_USBPLLCON_VCOBYP_Msk); +} + +/* API to onfigure the calibration mode for internal oscillator */ +void XMC_SCU_CLOCK_SetBackupClockCalibrationMode(XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t mode) +{ + /* Enable factory calibration based trimming */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_FOTR_Msk; + + if (mode == XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC) + { + /* Disable factory calibration based trimming */ + SCU_PLL->PLLCON0 &= (uint32_t)~SCU_PLL_PLLCON0_FOTR_Msk; + XMC_SCU_lDelay(100UL); + + /* Enable automatic calibration */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_AOTREN_Msk; + } + + XMC_SCU_lDelay(100UL); +} + + + +/* API to enable USB Phy and comparator */ +void XMC_SCU_POWER_EnableUsb(void) +{ +#if defined(USB_OTG_SUPPORTED) + SCU_POWER->PWRSET = (uint32_t)(SCU_POWER_PWRSET_USBOTGEN_Msk | SCU_POWER_PWRSET_USBPHYPDQ_Msk); +#else + SCU_POWER->PWRSET = (uint32_t)SCU_POWER_PWRSET_USBPHYPDQ_Msk; +#endif +} + +/* API to power down USB Phy and comparator */ +void XMC_SCU_POWER_DisableUsb(void) +{ +#if defined(USB_OTG_SUPPORTED) + SCU_POWER->PWRCLR = (uint32_t)(SCU_POWER_PWRCLR_USBOTGEN_Msk | SCU_POWER_PWRSET_USBPHYPDQ_Msk); +#else + SCU_POWER->PWRCLR = (uint32_t)SCU_POWER_PWRCLR_USBPHYPDQ_Msk; +#endif +} + +/* API to check USB PLL is locked or not */ +bool XMC_SCU_CLOCK_IsUsbPllLocked(void) +{ + return (bool)((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) != 0UL); +} + +/* API to power up the hibernation domain */ +void XMC_SCU_HIB_EnableHibernateDomain(void) +{ + /* Power up HIB domain if and only if it is currently powered down */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0UL) + { + SCU_POWER->PWRSET = (uint32_t)SCU_POWER_PWRSET_HIB_Msk; + + while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0UL) + { + /* wait until HIB domain is enabled */ + } + } + + /* Remove the reset only if HIB domain were in a state of reset */ + if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) + { + SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_HIBRS_Msk; + while((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk) != 0UL) + { + /* wait until HIB domain is enabled */ + } + } +} + +/* API to power down the hibernation domain */ +void XMC_SCU_HIB_DisableHibernateDomain(void) +{ + /* Disable hibernate domain */ + SCU_POWER->PWRCLR = (uint32_t)SCU_POWER_PWRCLR_HIB_Msk; + /* Reset of hibernate domain reset */ + SCU_RESET->RSTSET = (uint32_t)SCU_RESET_RSTSET_HIBRS_Msk; +} + +/* API to check the hibernation domain is enabled or not */ +bool XMC_SCU_HIB_IsHibernateDomainEnabled(void) +{ + return ((bool)(SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) && + !(bool)(SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)); +} + +/* API to enable internal slow clock - fOSI (32.768kHz) in hibernate domain */ +void XMC_SCU_HIB_EnableInternalSlowClock(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk) + { + /* Wait until OSCSICTRL register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->OSCSICTRL &= (uint32_t)~(SCU_HIBERNATE_OSCSICTRL_PWD_Msk); +} + +/* API to disable internal slow clock - fOSI (32.768kHz) in hibernate domain */ +void XMC_SCU_HIB_DisableInternalSlowClock(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk) + { + /* Wait until OSCSICTRL register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->OSCSICTRL |= (uint32_t)SCU_HIBERNATE_OSCSICTRL_PWD_Msk; +} + +void XMC_SCU_HIB_ClearEventStatus(int32_t event) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCLR_Msk) + { + /* Wait until HDCLR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCLR = event; +} + +void XMC_SCU_HIB_TriggerEvent(int32_t event) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDSET_Msk) + { + /* Wait until HDSET register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDSET = event; +} + +void XMC_SCU_HIB_EnableEvent(int32_t event) +{ +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + event = ((event & XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE) << (SCU_HIBERNATE_HDCR_VBATHI_Pos - SCU_HIBERNATE_HDSTAT_VBATPEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE) << (SCU_HIBERNATE_HDCR_VBATLO_Pos - SCU_HIBERNATE_HDSTAT_VBATNEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE); +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO1HI_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO1LO_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE); +#endif +#endif + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR |= event; +} + +void XMC_SCU_HIB_DisableEvent(int32_t event) +{ +#if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + event = ((event & XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE) << (SCU_HIBERNATE_HDCR_VBATHI_Pos - SCU_HIBERNATE_HDSTAT_VBATPEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE) << (SCU_HIBERNATE_HDCR_VBATLO_Pos - SCU_HIBERNATE_HDSTAT_VBATNEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE); +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO1HI_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE); + event = ((event & XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE) << (SCU_HIBERNATE_HDCR_AHIBIO1LO_Pos - SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Pos)) | (event & (uint32_t)~XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE); +#endif +#endif + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR &= ~event; +} + +void XMC_SCU_HIB_EnterHibernateState(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_HIB_Msk; +} + +void XMC_SCU_HIB_EnterHibernateStateEx(XMC_SCU_HIB_HIBERNATE_MODE_t mode) +{ + if (mode == XMC_SCU_HIB_HIBERNATE_MODE_EXTERNAL) + { + XMC_SCU_HIB_EnterHibernateState(); + } +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + if (mode == XMC_SCU_HIB_HIBERNATE_MODE_INTERNAL) + { + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HINTSET_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HINTSET = SCU_HIBERNATE_HINTSET_HIBNINT_Msk; + } +#endif +} + +void XMC_SCU_HIB_SetWakeupTriggerInput(XMC_SCU_HIB_IO_t pin) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + if (pin == XMC_SCU_HIB_IO_0) + { + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_WKUPSEL_Msk; + } + else + { + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_WKUPSEL_Msk; + } +} + +void XMC_SCU_HIB_SetPinMode(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_PIN_MODE_t mode) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ~(SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk << (SCU_HIBERNATE_HDCR_HIBIOSEL_Size * pin))) | + (mode << (SCU_HIBERNATE_HDCR_HIBIOSEL_Size * pin)); +} + +void XMC_SCU_HIB_SetPinOutputLevel(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_IO_OUTPUT_LEVEL_t level) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ~(SCU_HIBERNATE_HDCR_HIBIO0POL_Msk << pin)) | + (level << pin); +} + +void XMC_SCU_HIB_SetInput0(XMC_SCU_HIB_IO_t pin) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + if (pin == XMC_SCU_HIB_IO_0) + { + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_GPI0SEL_Msk; + } + else + { + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_GPI0SEL_Msk; + } +} + +void XMC_SCU_HIB_SetSR0Input(XMC_SCU_HIB_SR0_INPUT_t input) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI0SEL_Msk | SCU_HIBERNATE_HDCR_ADIG0SEL_Msk)) | +#else + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI0SEL_Msk)) | +#endif + input; +} + +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) + +#if ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)) +void XMC_SCU_HIB_SetSR1Input(XMC_SCU_HIB_SR1_INPUT_t input) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI0SEL_Msk | SCU_HIBERNATE_HDCR_ADIG0SEL_Msk | SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk)) | + input; +} +#endif + +void XMC_SCU_HIB_LPAC_SetInput(XMC_SCU_HIB_LPAC_INPUT_t input) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->LPACCONF = (SCU_HIBERNATE->LPACCONF & (uint32_t)~SCU_HIBERNATE_LPACCONF_CMPEN_Msk) | + input; +} + +void XMC_SCU_HIB_LPAC_SetTrigger(XMC_SCU_HIB_LPAC_TRIGGER_t trigger) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->LPACCONF = (SCU_HIBERNATE->LPACCONF & (uint32_t)~SCU_HIBERNATE_LPACCONF_TRIGSEL_Msk) | + trigger; +} + +void XMC_SCU_HIB_LPAC_SetTiming(bool enable_delay, uint16_t interval_count, uint8_t settle_count) +{ + uint32_t config = 0; + + if (enable_delay) + { + config = SCU_HIBERNATE_LPACCONF_CONVDEL_Msk; + } + + config |= interval_count << SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos; + config |= settle_count << SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos; + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + SCU_HIBERNATE->LPACCONF = (SCU_HIBERNATE->LPACCONF & (uint32_t)~(SCU_HIBERNATE_LPACCONF_CONVDEL_Msk | + SCU_HIBERNATE_LPACCONF_INTERVCNT_Msk | + SCU_HIBERNATE_LPACCONF_SETTLECNT_Msk)) | + config; + +} + +void XMC_SCU_HIB_LPAC_SetVBATThresholds(uint8_t lower, uint8_t upper) +{ + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH0_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + SCU_HIBERNATE->LPACTH0 = (lower << SCU_HIBERNATE_LPACTH0_VBATLO_Pos) | (upper << SCU_HIBERNATE_LPACTH0_VBATHI_Pos); + + + +} + +void XMC_SCU_HIB_LPAC_SetHIBIO0Thresholds(uint8_t lower, uint8_t upper) +{ + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH1_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + SCU_HIBERNATE->LPACTH1 = (SCU_HIBERNATE->LPACTH1 & (uint32_t)~(SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Msk | SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Msk)) | + (lower << SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Pos) | + (upper << SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Pos); + +} +#if ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)) +void XMC_SCU_HIB_LPAC_SetHIBIO1Thresholds(uint8_t lower, uint8_t upper) +{ + + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH1_Msk) + { + /* Wait until HDCR register in hibernate domain is ready to accept a write */ + } + + SCU_HIBERNATE->LPACTH1 = (SCU_HIBERNATE->LPACTH1 & (uint32_t)~(SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Msk | SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Msk)) | + (lower << SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Pos) | + (upper << SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Pos); + +} +#endif +int32_t XMC_SCU_HIB_LPAC_GetStatus(void) +{ + return SCU_HIBERNATE->LPACST; +} + +void XMC_SCU_HIB_LPAC_ClearStatus(int32_t status) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCLR_Msk) + { + /* Wait until LPACCLR register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->LPACCLR = status;; +} + +void XMC_SCU_HIB_LPAC_TriggerCompare(XMC_SCU_HIB_LPAC_INPUT_t input) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACSET_Msk) + { + /* Wait until LPACSET register in hibernate domain is ready to accept a write */ + } + + SCU_HIBERNATE->LPACSET = input; +} + +#endif + +bool XMC_SCU_CLOCK_IsLowPowerOscillatorStable(void) +{ + return ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) == 0UL); +} + +/* API to configure the 32khz Ultra Low Power oscillator */ +void XMC_SCU_CLOCK_EnableLowPowerOscillator(void) +{ + /* Enable OSC_ULP */ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + { + /* Wait until the update of OSCULCTRL register in hibernate domain is completed */ + } + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; + + /* Enable OSC_ULP Oscillator Watchdog*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCR |= (uint32_t)SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + + /* Enable OSC_ULP Oscillator Watchdog*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDSET_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDSET = (uint32_t)SCU_HIBERNATE_HDSET_ULPWDG_Msk; +} + +/* API to configure the 32khz Ultra Low Power oscillator */ +void XMC_SCU_CLOCK_DisableLowPowerOscillator(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + { + /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->OSCULCTRL |= (uint32_t)SCU_HIBERNATE_OSCULCTRL_MODE_Msk; +} + +void XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + { + /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->OSCULCTRL |= SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk | SCU_HIBERNATE_OSCULCTRL_MODE_Msk; +} + +void XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(void) +{ + while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + { + /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ + } + SCU_HIBERNATE->OSCULCTRL = (SCU_HIBERNATE->OSCULCTRL & ~(uint32_t)(SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk | SCU_HIBERNATE_OSCULCTRL_MODE_Msk)) | + (SCU_HIBERNATE_OSCULCTRL_MODE_OSC_POWER_DOWN << SCU_HIBERNATE_OSCULCTRL_MODE_Pos); +} + +uint32_t XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus(void) +{ + return (SCU_HIBERNATE->OSCULSTAT & SCU_HIBERNATE_OSCULSTAT_X1D_Msk); +} + +/* API to enable High Precision High Speed oscillator */ +void XMC_SCU_CLOCK_EnableHighPerformanceOscillator(void) +{ + SCU_PLL->PLLCON0 &= (uint32_t)~SCU_PLL_PLLCON0_PLLPWD_Msk; + + SCU_OSC->OSCHPCTRL = (uint32_t)((SCU_OSC->OSCHPCTRL & ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk)) | + (((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos)); + + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= (uint32_t)~SCU_PLL_PLLCON0_OSCRES_Msk; +} + +bool XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable(void) +{ + return ((SCU_PLL->PLLSTAT & XMC_SCU_PLL_PLLSTAT_OSC_USABLE) == XMC_SCU_PLL_PLLSTAT_OSC_USABLE); +} + +/* API to disable High Precision High Speed oscillator */ +void XMC_SCU_CLOCK_DisableHighPerformanceOscillator(void) +{ + SCU_OSC->OSCHPCTRL |= (uint32_t)SCU_OSC_OSCHPCTRL_MODE_Msk; +} + +void XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(void) +{ + SCU_OSC->OSCHPCTRL |= SCU_OSC_OSCHPCTRL_X1DEN_Msk; +} + +void XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(void) +{ + SCU_OSC->OSCHPCTRL &= ~SCU_OSC_OSCHPCTRL_X1DEN_Msk; +} + +uint32_t XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus(void) +{ + return (SCU_OSC->OSCHPSTAT & SCU_OSC_OSCHPSTAT_X1D_Msk); +} + +/* API to enable main PLL */ +void XMC_SCU_CLOCK_EnableSystemPll(void) +{ + SCU_PLL->PLLCON0 &= (uint32_t)~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); +} + +/* API to disable main PLL */ +void XMC_SCU_CLOCK_DisableSystemPll(void) +{ + SCU_PLL->PLLCON0 |= (uint32_t)(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); +} + +/* API to configure main PLL */ +void XMC_SCU_CLOCK_StartSystemPll(XMC_SCU_CLOCK_SYSPLLCLKSRC_t source, + XMC_SCU_CLOCK_SYSPLL_MODE_t mode, + uint32_t pdiv, + uint32_t ndiv, + uint32_t kdiv) +{ + + uint32_t vco_frequency; /* Q10.22, max VCO frequency = 520MHz */ + uint32_t kdiv_temp; + + XMC_SCU_CLOCK_SetSystemPllClockSource(source); + + if (mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL) + { + /* Calculate initial step to be close to fOFI */ + if (source == XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP) + { + vco_frequency = (OSCHP_GetFrequency() / 1000000U) << 22; + } + else + { + vco_frequency = (OFI_FREQUENCY / 1000000U) << 22; + } + vco_frequency = ((vco_frequency * ndiv) / pdiv); + kdiv_temp = (vco_frequency / (OFI_FREQUENCY / 1000000U)) >> 22; + + /* Switch to prescaler mode */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_VCOBYP_Msk; + + /* disconnect Oscillator from PLL */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_FINDIS_Msk; + + /* Setup divider settings for main PLL */ + SCU_PLL->PLLCON1 = (uint32_t)((SCU_PLL->PLLCON1 & ~(SCU_PLL_PLLCON1_NDIV_Msk | SCU_PLL_PLLCON1_K2DIV_Msk | + SCU_PLL_PLLCON1_PDIV_Msk)) | ((ndiv - 1UL) << SCU_PLL_PLLCON1_NDIV_Pos) | + ((kdiv_temp - 1UL) << SCU_PLL_PLLCON1_K2DIV_Pos) | + ((pdiv - 1UL)<< SCU_PLL_PLLCON1_PDIV_Pos)); + + /* Set OSCDISCDIS, OSC clock remains connected to the VCO in case of loss of lock */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + /* connect Oscillator to PLL */ + SCU_PLL->PLLCON0 &= (uint32_t)~SCU_PLL_PLLCON0_FINDIS_Msk; + + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_RESLD_Msk; + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U) + { + /* wait for PLL Lock */ + } + + /* Switch to normal mode */ + SCU_PLL->PLLCON0 &= (uint32_t)~SCU_PLL_PLLCON0_VCOBYP_Msk; + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U) + { + /* wait for normal mode */ + } + + /* Ramp up PLL frequency in steps */ + kdiv_temp = (vco_frequency / 60UL) >> 22; + if (kdiv < kdiv_temp) + { + XMC_SCU_CLOCK_StepSystemPllFrequency(kdiv_temp); + } + + kdiv_temp = (vco_frequency / 90UL) >> 22; + if (kdiv < kdiv_temp) + { + XMC_SCU_CLOCK_StepSystemPllFrequency(kdiv_temp); + } + + XMC_SCU_CLOCK_StepSystemPllFrequency(kdiv); + } + else + { + SCU_PLL->PLLCON1 = (uint32_t)((SCU_PLL->PLLCON1 & ~SCU_PLL_PLLCON1_K1DIV_Msk) | + ((kdiv -1UL) << SCU_PLL_PLLCON1_K1DIV_Pos)); + + /* Switch to prescaler mode */ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_VCOBYP_Msk; + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) == 0U) + { + /* wait for prescaler mode */ + } + } +} + +/* API to stop main PLL operation */ +void XMC_SCU_CLOCK_StopSystemPll(void) +{ + SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_PLLPWD_Msk; +} + +/* API to step up/down the main PLL frequency */ +void XMC_SCU_CLOCK_StepSystemPllFrequency(uint32_t kdiv) +{ + SCU_PLL->PLLCON1 = (uint32_t)((SCU_PLL->PLLCON1 & ~SCU_PLL_PLLCON1_K2DIV_Msk) | + ((kdiv - 1UL) << SCU_PLL_PLLCON1_K2DIV_Pos)); + + XMC_SCU_lDelay(50U); +} + +/* API to check main PLL is locked or not */ +bool XMC_SCU_CLOCK_IsSystemPllLocked(void) +{ + return (bool)((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) != 0UL); +} + +/* + * API to assign the event handler function to be executed on occurrence of the selected event. + */ +XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t event, + const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler) +{ + uint32_t index; + XMC_SCU_STATUS_t status; + + index = 0U; + while (((event & ((XMC_SCU_INTERRUPT_EVENT_t)1 << index)) == 0U) && (index < XMC_SCU_INTERRUPT_EVENT_MAX)) + { + index++; + } + + if (index == XMC_SCU_INTERRUPT_EVENT_MAX) + { + status = XMC_SCU_STATUS_ERROR; + } + else + { + event_handler_list[index] = handler; + status = XMC_SCU_STATUS_OK; + } + + return (status); +} + +/* + * API to execute callback functions for multiple events. + */ +void XMC_SCU_IRQHandler(uint32_t sr_num) +{ + uint32_t index; + XMC_SCU_INTERRUPT_EVENT_t event; + XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler; + + XMC_UNUSED_ARG(sr_num); + + index = 0U; + event = XMC_SCU_INTERUPT_GetEventStatus(); + while (index < XMC_SCU_INTERRUPT_EVENT_MAX) + { + if ((event & ((XMC_SCU_INTERRUPT_EVENT_t)1 << index)) != 0U) + { + event_handler = event_handler_list[index]; + if (event_handler != NULL) + { + (event_handler)(); + } + + XMC_SCU_INTERRUPT_ClearEventStatus((uint32_t)(1UL << index)); + + break; + } + index++; + } +} + +#endif /* UC_FAMILY == XMC4 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_can.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_can.c new file mode 100644 index 00000000..547ebc39 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_can.c @@ -0,0 +1,744 @@ +/** + * @file xmc_can.c + * @date 2016-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * + * 2015-05-20: + * - New API added: XMC_CAN_MO_ReceiveData()
+ * - XMC_CAN_MO_Config() signature has changed
+ * - Minor fix in XMC_CAN_TXFIFO_ConfigMOSlaveObject().
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-09-01: + * - Removed fCANB clock support
+ * + * 2015-09-08: + * - Fixed bug in XMC_CAN_Init()
+ * + * 2016-06-07: + * - Changed XMC_CAN_AllocateMOtoNodeList to wait for ready status of list controller + * + * 2015-06-20: + * - Fixed bug in XMC_CAN_MO_Config()
+ * @endcond + * + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#include "xmc_can.h" + +#if defined(CAN) +#include "xmc_scu.h" + +__STATIC_INLINE uint32_t max(uint32_t a, uint32_t b) +{ + return (a > b) ? a : b; +} + +__STATIC_INLINE uint32_t min(uint32_t a, uint32_t b) +{ + return (a < b) ? a : b; +} + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +/* Baudrate Configuration */ +void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const can_bit_time) +{ + uint32_t temp_brp = 12U ; + uint32_t temp_tseg1 = 12U; + uint32_t best_brp = 0U; + uint32_t best_tseg1 = 1U; + uint32_t best_tseg2 = 0U; + uint32_t best_tbaud = 0U; + uint32_t best_error = 10000U; + + XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: rate not supported", (can_bit_time->baudrate < 1000000U) || + (can_bit_time->baudrate >= 100000U)); + XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: fCAN not supported", + can_bit_time->can_frequency <= 120000000U); + XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: fCAN not supported", + can_bit_time->can_frequency > 5000000U); + XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: sample point not supported", + (can_bit_time->sample_point < 10000U) && ((can_bit_time->sample_point > 0U))); + + /* + * Bit timing & sampling + * Tq = (BRP+1)/Fcan if DIV8 = 0 + * Tq = 8*(BRP+1)/Fcan if DIV8 = 1 + * TSync = 1.Tq + * TSeg1 = (TSEG1+1)*Tq >= 3Tq + * TSeg2 = (TSEG2+1)*Tq >= 2Tq + * Bit Time = TSync + TSeg1 + TSeg2 >= 8Tq + * + * Resynchronization: + * + * Tsjw = (SJW + 1)*Tq + * TSeg1 >= Tsjw + Tprop + * TSeg2 >= Tsjw + */ + /* search for best baudrate */ + for (temp_brp = 1U; temp_brp <= 64U; temp_brp++) + { + + uint32_t f_quanta = (uint32_t)((can_bit_time->can_frequency * 10U) / temp_brp); + uint32_t temp_tbaud = (uint32_t)(f_quanta / (can_bit_time->baudrate)); + uint32_t temp_baudrate; + uint32_t error; + + if((temp_tbaud % 10U) > 5U) + { + temp_tbaud = (uint32_t)(temp_tbaud / 10U); + temp_tbaud++; + } + else + { + temp_tbaud = (uint32_t)(temp_tbaud / 10U); + } + + if(temp_tbaud > 0U) + { + temp_baudrate = (uint32_t) (f_quanta / (temp_tbaud * 10U)); + } + else + { + temp_baudrate = f_quanta / 10U; + temp_tbaud = 1; + } + + if(temp_baudrate >= can_bit_time->baudrate) + { + error = temp_baudrate - can_bit_time->baudrate; + } + else + { + error = can_bit_time->baudrate - temp_baudrate; + } + + if ((temp_tbaud <= 20U) && (best_error > error)) + { + best_brp = temp_brp; + best_tbaud = temp_tbaud; + best_error = (error); + + if (error < 1000U) + { + break; + } + } + } + /* search for best sample point */ + best_error = 10000U; + + for (temp_tseg1 = 64U; temp_tseg1 >= 3U; temp_tseg1--) + { + uint32_t tempSamplePoint = ((temp_tseg1 + 1U) * 10000U) / best_tbaud; + uint32_t error; + if (tempSamplePoint >= can_bit_time->sample_point) + { + error = tempSamplePoint - can_bit_time->sample_point; + } + else + { + error = can_bit_time->sample_point - tempSamplePoint; + } + if (best_error > error) + { + best_tseg1 = temp_tseg1; + best_error = error; + } + if (tempSamplePoint < (can_bit_time->sample_point)) + { + break; + } + } + + best_tseg2 = best_tbaud - best_tseg1 - 1U; + + XMC_CAN_NODE_EnableConfigurationChange(can_node); + /* Configure bit timing register */ + can_node->NBTR = (((uint32_t)(best_tseg2 - 1u) << CAN_NODE_NBTR_TSEG2_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG2_Msk) | + ((((uint32_t)((uint32_t)(can_bit_time->sjw)-1U) << CAN_NODE_NBTR_SJW_Pos)) & (uint32_t)CAN_NODE_NBTR_SJW_Msk)| + (((uint32_t)(best_tseg1-1U) << CAN_NODE_NBTR_TSEG1_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG1_Msk)| + (((uint32_t)(best_brp - 1U) << CAN_NODE_NBTR_BRP_Pos) & (uint32_t)CAN_NODE_NBTR_BRP_Msk)| + (((uint32_t)0U << CAN_NODE_NBTR_DIV8_Pos) & (uint32_t)CAN_NODE_NBTR_DIV8_Msk); + XMC_CAN_NODE_DisableConfigurationChange(can_node); +} +/* Function to allocate message object from free list to node list */ +void XMC_CAN_AllocateMOtoNodeList(XMC_CAN_t *const obj, const uint8_t node_num, const uint8_t mo_num) +{ + /* wait while panel operation is in progress. */ + while (XMC_CAN_IsPanelControlReady(obj) == false) + { + /*Do nothing*/ + }; + + /* Panel Command for allocation of MO to node list */ + XMC_CAN_PanelControl(obj, XMC_CAN_PANCMD_STATIC_ALLOCATE,mo_num,(node_num + 1U)); +} + +/* Disable XMC_CAN Peripheral */ +void XMC_CAN_Disable(XMC_CAN_t *const obj) +{ + /* Disable CAN Module */ + obj->CLC = CAN_CLC_DISR_Msk; +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_MCAN); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_MCAN); +#endif +} + +/* Enable XMC_CAN Peripheral */ +void XMC_CAN_Enable(XMC_CAN_t *const obj) +{ +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_MCAN); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_MCAN); +#endif + /* Enable CAN Module */ + obj->CLC &= ~(uint32_t)CAN_CLC_DISR_Msk; + while (obj->CLC & CAN_CLC_DISS_Msk) + { + /*Do nothing*/ + }; +} +#if defined(MULTICAN_PLUS) +uint32_t XMC_CAN_GetBaudrateClockFrequency(XMC_CAN_t *const obj) +{ + uint32_t frequency; + + switch(XMC_CAN_GetBaudrateClockSource(obj)) + { +#if UC_FAMILY == XMC4 + case XMC_CAN_CANCLKSRC_FPERI: + frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + break; +#else + case XMC_CAN_CANCLKSRC_MCLK: + frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + break; +#endif + case XMC_CAN_CANCLKSRC_FOHP: + frequency = OSCHP_GetFrequency(); + break; + + default: + frequency = 0; + break; + } + + return frequency; +} + +void XMC_CAN_Init(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can_frequency) +{ + uint32_t step_n, step_f; + bool normal_divider; + uint32_t freq_n, freq_f; + uint32_t step; + uint32_t can_frequency_khz; + uint32_t peripheral_frequency_khz; + XMC_CAN_DM_t can_divider_mode; + + uint32_t peripheral_frequency; + /*Enabling the module*/ + XMC_CAN_Enable(obj); + + XMC_CAN_SetBaudrateClockSource(obj, clksrc); + + peripheral_frequency = XMC_CAN_GetBaudrateClockFrequency(obj); + + XMC_ASSERT("XMC_CAN_Init: frequency not supported", can_frequency <= peripheral_frequency); + + /* Normal divider mode */ + step_n = (uint32_t)min(max(0U, (1024U - (peripheral_frequency / can_frequency))), 1023U); + freq_n = (uint32_t) (peripheral_frequency / (1024U - step_n)); + + /* Fractional divider mode */ + can_frequency_khz = (uint32_t) (can_frequency >> 6); + peripheral_frequency_khz = (uint32_t)(peripheral_frequency >> 6); + + step_f = (uint32_t)(min( (((1024U * can_frequency_khz) / peripheral_frequency_khz) ), 1023U )); + freq_f = (uint32_t)((peripheral_frequency_khz * step_f) / 1024U); + freq_f = freq_f << 6; + + normal_divider = (uint32_t)(can_frequency - freq_n) <= (can_frequency - freq_f); + + step = (normal_divider != 0U) ? step_n : step_f; + can_divider_mode = (normal_divider != 0U) ? XMC_CAN_DM_NORMAL : XMC_CAN_DM_FRACTIONAL; + + obj->FDR &= (uint32_t) ~(CAN_FDR_DM_Msk | CAN_FDR_STEP_Msk); + obj->FDR |= ((uint32_t)can_divider_mode << CAN_FDR_DM_Pos) | ((uint32_t)step << CAN_FDR_STEP_Pos); + +} + +void XMC_CAN_SetBaudrateClockSource(XMC_CAN_t *const obj,const XMC_CAN_CANCLKSRC_t source) +{ + obj->MCR = (obj->MCR & ~CAN_MCR_CLKSEL_Msk) | source ; +} + +XMC_CAN_CANCLKSRC_t XMC_CAN_GetBaudrateClockSource(XMC_CAN_t *const obj) +{ + return ((XMC_CAN_CANCLKSRC_t)((obj->MCR & CAN_MCR_CLKSEL_Msk) >> CAN_MCR_CLKSEL_Pos)); +} + +#else +/* Initialization of XMC_CAN GLOBAL Object */ +void XMC_CAN_Init(XMC_CAN_t *const obj, uint32_t can_frequency) +{ + uint32_t step_n, step_f; + bool normal_divider; + uint32_t freq_n, freq_f; + uint32_t step; + uint32_t can_frequency_khz; + uint32_t peripheral_frequency_khz; + XMC_CAN_DM_t can_divider_mode; + + uint32_t peripheral_frequency = (XMC_SCU_CLOCK_GetPeripheralClockFrequency()); + + XMC_ASSERT("XMC_CAN_Init: frequency not supported", can_frequency <= peripheral_frequency); + + /*Enabling the module*/ + XMC_CAN_Enable(obj); + + /* Normal divider mode */ + step_n = (uint32_t)min(max(0U, (1024U - (peripheral_frequency / can_frequency))), 1023U); + freq_n = (uint32_t) (peripheral_frequency / (1024U - step_n)); + + /* Fractional divider mode */ + can_frequency_khz = (uint32_t) (can_frequency >> 6); + peripheral_frequency_khz = (uint32_t)(peripheral_frequency >> 6); + + step_f = (uint32_t)(min( (((1024U * can_frequency_khz) / peripheral_frequency_khz) ), 1023U )); + freq_f = (uint32_t)((peripheral_frequency_khz * step_f) / 1024U); + freq_f = freq_f << 6; + + normal_divider = (uint32_t)(can_frequency - freq_n) <= (can_frequency - freq_f); + + step = (normal_divider != 0U) ? step_n : step_f; + can_divider_mode = (normal_divider != 0U) ? XMC_CAN_DM_NORMAL : XMC_CAN_DM_FRACTIONAL; + + obj->FDR &= (uint32_t) ~(CAN_FDR_DM_Msk | CAN_FDR_STEP_Msk); + obj->FDR |= ((uint32_t)can_divider_mode << CAN_FDR_DM_Pos) | ((uint32_t)step << CAN_FDR_STEP_Pos); +} +#endif + +/* Sets the Identifier of the MO */ +void XMC_CAN_MO_SetIdentifier(XMC_CAN_MO_t *const can_mo, const uint32_t can_identifier) +{ + if ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk) + { + can_mo->can_mo_ptr->MOAR = ((can_mo->can_mo_ptr->MOAR) & ~(uint32_t)(CAN_MO_MOAR_ID_Msk)) | + ((can_identifier << XMC_CAN_MO_MOAR_STDID_Pos) & (uint32_t)CAN_MO_MOAR_ID_Msk); + } + else + { + can_mo->can_mo_ptr->MOAR = ((can_mo->can_mo_ptr->MOAR) & ~(uint32_t)(CAN_MO_MOAR_ID_Msk)) | + (can_identifier & (uint32_t)CAN_MO_MOAR_ID_Msk); + } + can_mo->can_identifier = can_identifier; +} + + +/* Gets the Identifier of the MO */ +uint32_t XMC_CAN_MO_GetIdentifier(const XMC_CAN_MO_t *const can_mo) +{ + uint32_t identifier; + if ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk) + { + identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk)) >> XMC_CAN_MO_MOAR_STDID_Pos; + } + else + { + identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk)); + } + return identifier; +} + +/* Gets the acceptance mask for the CAN MO. */ +uint32_t XMC_CAN_MO_GetAcceptanceMask(const XMC_CAN_MO_t *const can_mo) +{ + uint32_t identifier_mask; + if (((can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) != (uint32_t)CAN_MO_MOAMR_MIDE_Msk) + && ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk)) + { + identifier_mask = ((can_mo->can_mo_ptr->MOAMR) & (uint32_t)(CAN_MO_MOAMR_AM_Msk)) >> XMC_CAN_MO_MOAR_STDID_Pos; + } + else + { + identifier_mask = ((can_mo->can_mo_ptr->MOAMR) & (uint32_t)(CAN_MO_MOAMR_AM_Msk)); + } + return identifier_mask; +} + +/* Gets the acceptance mask of the MO */ +void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo,const uint32_t can_id_mask) +{ + if (((can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) != (uint32_t)CAN_MO_MOAMR_MIDE_Msk) + && ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk)) + { + can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) | + (can_id_mask << XMC_CAN_MO_MOAR_STDID_Pos); + } + else + { + can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) | + (can_id_mask & (uint32_t)CAN_MO_MOAMR_AM_Msk); + } + can_mo->can_id_mask = can_id_mask; +} + +/* Initialization of XMC_CAN MO Object */ +void XMC_CAN_MO_Config(const XMC_CAN_MO_t *const can_mo) +{ + uint32_t reg; + + /* Configure MPN */ + uint32_t num = ((uint32_t)(can_mo->can_mo_ptr) - CAN_BASE - 0x1000U)/0x0020U; + uint32_t set = (((uint32_t)(num/32) << (CAN_MO_MOIPR_MPN_Pos + 5U)) | ((uint32_t)(num%32) << CAN_MO_MOIPR_MPN_Pos)); + can_mo->can_mo_ptr->MOIPR &= ~(CAN_MO_MOIPR_MPN_Msk); + can_mo->can_mo_ptr->MOIPR |= set; + + if (((can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_STANDARD_11BITS) && + (can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_EXTENDED_29BITS)) || + ((can_mo->can_mo_type != XMC_CAN_MO_TYPE_RECMSGOBJ) && + (can_mo->can_mo_type != XMC_CAN_MO_TYPE_TRANSMSGOBJ))) + { + ; /*Do nothing*/ + } + else + { + + /* Disable Message object */ + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESMSGVAL_Msk; + if (can_mo->can_id_mode == (uint32_t)XMC_CAN_FRAME_TYPE_STANDARD_11BITS) + { + reg = can_mo->mo_ar; + reg &= (uint32_t) ~(CAN_MO_MOAR_ID_Msk); + reg |= (can_mo->can_identifier << XMC_CAN_MO_MOAR_STDID_Pos); + can_mo->can_mo_ptr->MOAR = reg; + + reg = can_mo->mo_amr; + reg &= (uint32_t) ~(CAN_MO_MOAMR_AM_Msk); + reg |= (can_mo->can_id_mask << XMC_CAN_MO_MOAR_STDID_Pos); + can_mo->can_mo_ptr->MOAMR = reg; + } + else + { + can_mo->can_mo_ptr->MOAR = can_mo->mo_ar; + can_mo->can_mo_ptr->MOAMR = can_mo->mo_amr; + } + /* Check whether message object is transmit message object */ + if (can_mo->can_mo_type == XMC_CAN_MO_TYPE_TRANSMSGOBJ) + { + /* Set MO as Transmit message object */ + XMC_CAN_MO_UpdateData(can_mo); + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_SETDIR_Msk; + } + else + { + /* Set MO as Receive message object and set RXEN bit */ + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESDIR_Msk; + } + + /* Reset RTSEL and Set MSGVAL ,TXEN0 and TXEN1 bits */ + can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk | CAN_MO_MOCTR_SETMSGVAL_Msk | + CAN_MO_MOCTR_SETRXEN_Msk | CAN_MO_MOCTR_RESRTSEL_Msk); + } +} + +/* Update of XMC_CAN Object */ +XMC_CAN_STATUS_t XMC_CAN_MO_UpdateData(const XMC_CAN_MO_t *const can_mo) +{ + XMC_CAN_STATUS_t error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE; + /* Check whether message object is transmit message object */ + if (can_mo->can_mo_type == XMC_CAN_MO_TYPE_TRANSMSGOBJ) + { + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESMSGVAL_Msk; + /* Configure data length */ + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR) & ~(uint32_t)(CAN_MO_MOFCR_DLC_Msk)) | + (((uint32_t) can_mo->can_data_length << CAN_MO_MOFCR_DLC_Pos) & (uint32_t)CAN_MO_MOFCR_DLC_Msk); + /* Configure Data registers*/ + can_mo->can_mo_ptr->MODATAL = can_mo->can_data[0]; + can_mo->can_mo_ptr->MODATAH = can_mo->can_data[1]; + /* Reset RTSEL and Set MSGVAL ,TXEN0 and TXEN1 bits */ + can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETNEWDAT_Msk| CAN_MO_MOCTR_SETMSGVAL_Msk |CAN_MO_MOCTR_RESRTSEL_Msk); + error = XMC_CAN_STATUS_SUCCESS; + } + else + { + error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE; + } + return error; +} + +/* This function is will put a transmit request to transmit message object */ +XMC_CAN_STATUS_t XMC_CAN_MO_Transmit(const XMC_CAN_MO_t *const can_mo) +{ + XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR; + uint32_t mo_type = (uint32_t)(((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_MSGVAL_Msk) >> CAN_MO_MOSTAT_MSGVAL_Pos); + uint32_t mo_transmission_ongoing = (uint32_t) ((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_TXRQ_Msk) >> CAN_MO_MOSTAT_TXRQ_Pos; + /* check if message is disabled */ + if (mo_type == 0U) + { + error = XMC_CAN_STATUS_MO_DISABLED; + } + /* check if transmission is ongoing on message object */ + else if (mo_transmission_ongoing == 1U) + { + error = XMC_CAN_STATUS_BUSY; + } + else + { + /* set TXRQ bit */ + can_mo->can_mo_ptr-> MOCTR = CAN_MO_MOCTR_SETTXRQ_Msk | CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk; + error = XMC_CAN_STATUS_SUCCESS; + } + return error; +} + +/* This function is will read the message object data bytes */ +XMC_CAN_STATUS_t XMC_CAN_MO_ReceiveData (XMC_CAN_MO_t *can_mo) +{ + XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR; + uint8_t rx_pnd = 0U; + uint8_t new_data = 0U; + uint32_t mo_type = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_DIR_Msk) >> CAN_MO_MOSTAT_DIR_Pos; + uint32_t mo_recepcion_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos; + /* check if message object is a receive message object */ + if (mo_type != (uint32_t)XMC_CAN_MO_TYPE_RECMSGOBJ) + { + error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE; + } + /* check if reception is ongoing on message object */ + else if (mo_recepcion_ongoing == 1U) + { + error = XMC_CAN_STATUS_BUSY; + } + else + { + /* read message parameters */ + do + { + can_mo->can_data[0] = can_mo->can_mo_ptr->MODATAL; + can_mo->can_data[1] = can_mo->can_mo_ptr->MODATAH; + + rx_pnd = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos); + new_data = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_NEWDAT_Msk) >> CAN_MO_MOSTAT_NEWDAT_Pos); + } while ((rx_pnd != 0U) && (new_data != 0U)); + + error = XMC_CAN_STATUS_SUCCESS; + } + return error; +} + + +/* This function is will read the message object data bytes */ +XMC_CAN_STATUS_t XMC_CAN_MO_Receive (XMC_CAN_MO_t *can_mo) +{ + XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR; + uint8_t rx_pnd = 0U; + uint8_t new_data = 0U; + uint32_t mo_type = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_DIR_Msk) >> CAN_MO_MOSTAT_DIR_Pos; + uint32_t mo_recepcion_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos; + /* check if message object is a receive message object */ + if (mo_type != (uint32_t)XMC_CAN_MO_TYPE_RECMSGOBJ) + { + error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE; + } + /* check if reception is ongoing on message object */ + else if (mo_recepcion_ongoing == 1U) + { + error = XMC_CAN_STATUS_BUSY; + } + else + { + /* read message parameters */ + do + { + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESNEWDAT_Msk; + if ((((can_mo->can_mo_ptr->MOAR) & CAN_MO_MOAR_IDE_Msk) >> CAN_MO_MOAR_IDE_Pos) == 0U) + { + can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_STANDARD_11BITS; + can_mo->can_identifier = (can_mo->can_mo_ptr->MOAR & XMC_CAN_MO_MOAR_STDID_Msk) >> XMC_CAN_MO_MOAR_STDID_Pos; + can_mo->can_ide_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) >> CAN_MO_MOAMR_MIDE_Pos; + if(can_mo->can_ide_mask == 1U) + { + can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & XMC_CAN_MO_MOAR_STDID_Msk) >> XMC_CAN_MO_MOAR_STDID_Pos; + } + else + { + can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_AM_Msk); + } + } + else + { + can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_EXTENDED_29BITS; + can_mo->can_identifier = (can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_ID_Msk); + can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_AM_Msk); + can_mo->can_ide_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) >> CAN_MO_MOAMR_MIDE_Pos; + } + can_mo->can_data_length = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOFCR) & CAN_MO_MOFCR_DLC_Msk) >> CAN_MO_MOFCR_DLC_Pos); + + can_mo->can_data[0] = can_mo->can_mo_ptr->MODATAL; + can_mo->can_data[1] = can_mo->can_mo_ptr->MODATAH; + + rx_pnd = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos); + new_data = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_NEWDAT_Msk) >> CAN_MO_MOSTAT_NEWDAT_Pos); + } while ((rx_pnd != 0U) && (new_data != 0U)); + + can_mo->can_mo_type = XMC_CAN_MO_TYPE_RECMSGOBJ; + error = XMC_CAN_STATUS_SUCCESS; + } + return error; +} + +/* Function to enable node event */ +void XMC_CAN_NODE_EnableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event) +{ + if(event != XMC_CAN_NODE_EVENT_CFCIE) + { + can_node->NCR |= (uint32_t)event; + } + else + { + can_node->NFCR |= (uint32_t)event; + } +} + +/* Function to disable node event */ +void XMC_CAN_NODE_DisableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event) +{ + if(event != XMC_CAN_NODE_EVENT_CFCIE) + { + can_node->NCR &= ~(uint32_t)event; + } + else + { + can_node->NFCR &= ~(uint32_t)event; + } +} +/* Function to transmit MO from the FIFO */ +XMC_CAN_STATUS_t XMC_CAN_TXFIFO_Transmit(const XMC_CAN_MO_t *const can_mo) +{ + XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR; + uint32_t mo_type = ((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_MSGVAL_Msk) >> CAN_MO_MOSTAT_MSGVAL_Pos); + uint32_t mo_transmission_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_TXRQ_Msk) >> CAN_MO_MOSTAT_TXRQ_Pos; + uint32_t mo_cur = (uint32_t)(can_mo->can_mo_ptr-> MOFGPR & CAN_MO_MOFGPR_CUR_Msk) >> CAN_MO_MOFGPR_CUR_Pos; + CAN_MO_TypeDef* mo = (CAN_MO_TypeDef *)(CAN_BASE + 0x1000UL + (mo_cur * 0x0020UL)); + /* check if message is disabled */ + if (mo_type == 0U) + { + error = XMC_CAN_STATUS_MO_DISABLED; + } + /* check if transmission is ongoing on message object */ + else if (mo_transmission_ongoing == 1U) + { + error = XMC_CAN_STATUS_BUSY; + } + else + { + mo->MOCTR = CAN_MO_MOCTR_SETTXRQ_Msk | CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk; + error = XMC_CAN_STATUS_SUCCESS; + } + return error; +} + +/* Function to initialize the transmit FIFO MO base object */ +void XMC_CAN_TXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo) +{ + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) | + (((uint32_t)0x2U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk); + can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_BOT_Msk | + CAN_MO_MOFGPR_TOP_Msk | + CAN_MO_MOFGPR_CUR_Msk)) | + (((uint32_t)can_fifo.fifo_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) | + (((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t) CAN_MO_MOFGPR_CUR_Msk) | + (((uint32_t)can_fifo.fifo_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t) CAN_MO_MOFGPR_TOP_Msk); +} +/* Function to Initialize the receive FIFO MO base object */ +void XMC_CAN_RXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo) +{ + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) | + (((uint32_t)0x1U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk); + can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~( uint32_t)(CAN_MO_MOFGPR_BOT_Msk | + CAN_MO_MOFGPR_TOP_Msk | + CAN_MO_MOFGPR_CUR_Msk)) | + (((uint32_t)can_fifo.fifo_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) | + (((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk) | + (((uint32_t)can_fifo.fifo_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t)CAN_MO_MOFGPR_TOP_Msk); +} + +/* Function to Initialize the FIFO MO slave object */ +void XMC_CAN_TXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo) +{ + can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) | + (((uint32_t)0x3U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk); + can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_CUR_Msk)) | + (((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk); + + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_SETTXEN0_Msk| + CAN_MO_MOCTR_RESTXEN1_Msk; +} + +/* Function to Initialize the Gateway Source Object */ +void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_GATEWAY_CONFIG_t can_gateway) +{ + can_mo->can_mo_ptr->MOFCR = (((uint32_t)0x4U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk) | + ((((uint32_t)can_gateway.gateway_data_frame_send) << CAN_MO_MOFCR_GDFS_Pos) & (uint32_t)CAN_MO_MOFCR_GDFS_Msk) | + ((((uint32_t)can_gateway.gateway_data_length_code_copy) << CAN_MO_MOFCR_DLCC_Pos) & (uint32_t)CAN_MO_MOFCR_DLCC_Msk) | + ((((uint32_t)can_gateway.gateway_identifier_copy) << CAN_MO_MOFCR_IDC_Pos) & (uint32_t)CAN_MO_MOFCR_IDC_Msk) | + ((((uint32_t)can_gateway.gateway_data_copy) << CAN_MO_MOFCR_DATC_Pos) & (uint32_t)CAN_MO_MOFCR_DATC_Msk) ; + can_mo->can_mo_ptr->MOFGPR = (uint32_t)((((uint32_t)can_gateway.gateway_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) | + (((uint32_t)can_gateway.gateway_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk) | + (((uint32_t)can_gateway.gateway_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t)CAN_MO_MOFGPR_TOP_Msk)); +} + +#endif /* XMC_CAN_H */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ccu4.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ccu4.c new file mode 100644 index 00000000..c0f3868c --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ccu4.c @@ -0,0 +1,1136 @@ +/** + * @file xmc_ccu4.c + * @date 2017-02-25 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API
+ * + * 2015-07-01: + * - In XMC_CCU4_SLICE_StartConfig(), Options in XMC_ASSERT check for start mode is corrected.
+ * + * 2015-07-24: + * - XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
+ * + * 2015-08-17: + * - Start of prescaler XMC_CCU4_StartPrescaler() is invoked in XMC_CCU4_Init() API.
+ * - Bug fix XMC_CCU4_SLICE_ConfigureEvent() during the level setting for XMC14 devices.
+ * - XMC_CCU4_EnableShadowTransfer() definition is removed, since the API is made as inline.
+ * + * 2015-10-07: + * - XMC_CCU4_SLICE_GetEvent() is made as inline. + * - DOC updates for the newly added APIs. + * + * 2017-02-25: + * - XMC_CCU4_lAssertReset(), XMC_CCU4_lDeassertReset(), XMC_CCU4_lGateClock() and XMC_CCU4_lUngateClock() fix compilation warnings. + * + * @endcond + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_ccu4.h" + +#if defined(CCU40) +#include "xmc_scu.h" +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_CCU4_NUM_SLICES_PER_MODULE (4U) +#define XMC_CCU4_SLICE_DITHER_PERIOD_MASK (1U) +#define XMC_CCU4_SLICE_DITHER_DUTYCYCLE_MASK (2U) +#define XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK (3U) +#define XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK (1U) +#define XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK (3U) +#if defined(CCU4V3) /* Defined for XMC1400 devices only */ +#define XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK CCU4_CC4_INS1_EV0IS_Msk +#else +#define XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK CCU4_CC4_INS_EV0IS_Msk +#endif +#define XMC_CCU4_GIDLC_CLOCK_MASK (15U) +#define XMC_CCU4_GCSS_SLICE0_MASK (1U) +#define XMC_CCU4_GCSS_SLICE1_MASK (16U) +#define XMC_CCU4_GCSS_SLICE2_MASK (256U) +#define XMC_CCU4_GCSS_SLICE3_MASK (4096U) + +/** Macro to check if the clock selected enum passed is valid */ +#define XMC_CCU4_SLICE_CHECK_CLOCK(clock) \ + ((clock == XMC_CCU4_CLOCK_SCU) || \ + (clock == XMC_CCU4_CLOCK_EXTERNAL_A) || \ + (clock == XMC_CCU4_CLOCK_EXTERNAL_B) || \ + (clock == XMC_CCU4_CLOCK_EXTERNAL_C)) + +/** Macro used to check if the event ID is valid*/ +#define XMC_CCU4_SLICE_CHECK_EVENT_ID(event_id) \ + ((event_id == XMC_CCU4_SLICE_EVENT_NONE)|| \ + (event_id == XMC_CCU4_SLICE_EVENT_0) || \ + (event_id == XMC_CCU4_SLICE_EVENT_1) || \ + (event_id == XMC_CCU4_SLICE_EVENT_2)) + +/** Macro used to check if the edge sensitivity is valid*/ +#define XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(edge) \ + ((edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE) || \ + (edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE) || \ + (edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE)|| \ + (edge == XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE)) + +/** Macro used to check if the filter clock cycles are valid */ +#define XMC_CCU4_SLICE_CHECK_EVENT_FILTER(cycles) \ + ((cycles == XMC_CCU4_SLICE_EVENT_FILTER_DISABLED) || \ + (cycles == XMC_CCU4_SLICE_EVENT_FILTER_3_CYCLES) || \ + (cycles == XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES) || \ + (cycles == XMC_CCU4_SLICE_EVENT_FILTER_7_CYCLES)) + +/** Macro used to check if the Multi-channel input related action is valid*/ +#define XMC_CCU4_SLICE_CHECK_MCS_ACTION(mcs_action) \ + ((mcs_action == XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR) || \ + (mcs_action == XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP) || \ + (mcs_action == XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT)) + +/** Macro used to check if the SR line is valid*/ +#define XMC_CCU4_SLICE_CHECK_SR_ID(id) \ + ((id == XMC_CCU4_SLICE_SR_ID_0) || \ + (id == XMC_CCU4_SLICE_SR_ID_1) || \ + (id == XMC_CCU4_SLICE_SR_ID_2) || \ + (id == XMC_CCU4_SLICE_SR_ID_3)) + +/** Macro to check if the end mode enum passed is valid */ +#define XMC_CCU4_CHECK_END_MODE(end_mode) \ + ((end_mode == XMC_CCU4_SLICE_END_MODE_TIMER_STOP) || \ + (end_mode == XMC_CCU4_SLICE_END_MODE_TIMER_CLEAR) || \ + (end_mode == XMC_CCU4_SLICE_END_MODE_TIMER_STOP_CLEAR)) + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ +#if defined(PERIPHERAL_RESET_SUPPORTED) +__STATIC_INLINE void XMC_CCU4_lAssertReset(const XMC_CCU4_MODULE_t *const module) +{ + if (module == CCU40) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU40); + } +#if defined(CCU41) + else if (module == CCU41) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU41); + } +#endif +#if defined(CCU42) + else if (module == CCU42) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU42); + } +#endif +#if defined(CCU43) + else if (module == CCU43) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU43); + } +#endif + else + { + XMC_ASSERT("XMC_CCU4_lAssertReset:Invalid Module Pointer", 0); + } +} + +__STATIC_INLINE void XMC_CCU4_lDeassertReset(const XMC_CCU4_MODULE_t *const module) +{ + if (module == CCU40) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU40); + } +#if defined(CCU41) + else if (module == CCU41) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU41); + } +#endif +#if defined(CCU42) + else if (module == CCU42) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU42); + } +#endif +#if defined(CCU43) + else if (module == CCU43) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU43); + } +#endif + else + { + XMC_ASSERT("XMC_CCU4_lDeassertReset:Invalid Module Pointer", 0); + } +} +#endif + +#if defined(CLOCK_GATING_SUPPORTED) +__STATIC_INLINE void XMC_CCU4_lGateClock(const XMC_CCU4_MODULE_t *const module) +{ + + if (module == CCU40) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU40); + } +#if defined(CCU41) + else if (module == CCU41) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU41); + } +#endif +#if defined(CCU42) + else if (module == CCU42) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU42); + } +#endif +#if defined(CCU43) + else if (module == CCU43) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU43); + } +#endif + else + { + XMC_ASSERT("XMC_CCU4_lGateClock:Invalid Module Pointer", 0); + } +} + +__STATIC_INLINE void XMC_CCU4_lUngateClock(const XMC_CCU4_MODULE_t *const module) +{ + if (module == CCU40) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU40); + } +#if defined(CCU41) + else if (module == CCU41) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU41); + } +#endif +#if defined(CCU42) + else if (module == CCU42) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU42); + } +#endif +#if defined(CCU43) + else if (module == CCU43) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU43); + } +#endif + else + { + XMC_ASSERT("XMC_CCU4_lUngateClock:Invalid Module Pointer", 0); + } +} +#endif + +#if defined (XMC_ASSERT_ENABLE) +__STATIC_INLINE bool XMC_CCU4_SLICE_IsInputvalid(XMC_CCU4_SLICE_INPUT_t input) +{ +#if (UC_SERIES == XMC14) + return (input < 48U); +#else + return (input < 16U); +#endif +} +#endif +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +void XMC_CCU4_EnableModule(XMC_CCU4_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU4_EnableModule:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + +#if UC_FAMILY == XMC4 + /* Enable CCU4 module clock */ + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_CCU4_lUngateClock(module); +#endif + +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_CCU4_lDeassertReset(module); +#endif +} + +void XMC_CCU4_DisableModule(XMC_CCU4_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU4_DisableModule:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_CCU4_lAssertReset(module); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_CCU4_lGateClock(module); +#endif +} + +/* API to initialize CCU4 global resources */ +void XMC_CCU4_Init(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_SLICE_MCMS_ACTION_t mcs_action) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU4_Init:Invalid module pointer", XMC_CCU4_IsValidModule(module)); + XMC_ASSERT("XMC_CCU4_Init:Invalid mcs action", XMC_CCU4_SLICE_CHECK_MCS_ACTION(mcs_action)); + + /* Enable CCU4 module */ + XMC_CCU4_EnableModule(module); + /* Start the prescaler */ + XMC_CCU4_StartPrescaler(module); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t) CCU4_GCTRL_MSDE_Msk); + gctrl |= ((uint32_t) mcs_action) << CCU4_GCTRL_MSDE_Pos; + + module->GCTRL = gctrl; +} + +/* API to select CCU4 module clock */ +void XMC_CCU4_SetModuleClock(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_CLOCK_t clock) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU4_SetModuleClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + XMC_ASSERT("XMC_CCU4_SetModuleClock:Invalid Module Clock", XMC_CCU4_SLICE_CHECK_CLOCK(clock)); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t) CCU4_GCTRL_PCIS_Msk); + gctrl |= ((uint32_t) clock) << CCU4_GCTRL_PCIS_Pos; + + module->GCTRL = gctrl; +} + +/* API to configure the multichannel shadow transfer request via SW and via the CCU4x.MCSS input. */ +void XMC_CCU4_SetMultiChannelShadowTransferMode(XMC_CCU4_MODULE_t *const module, const uint32_t slice_mode_msk) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU4_SetMultiChannelShadowTransferMode:Invalid module Pointer", XMC_CCU4_IsValidModule(module)); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t)slice_mode_msk >> 16U); + gctrl |= ((uint32_t)slice_mode_msk & 0xFFFFU); + module->GCTRL = gctrl; +} + +/* API to configure CC4 Slice as Timer */ +void XMC_CCU4_SLICE_CompareInit(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_COMPARE_CONFIG_t *const compare_init) +{ + XMC_ASSERT("XMC_CCU4_SLICE_CompareInit:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_CompareInit:Compare Init Pointer is NULL", + (XMC_CCU4_SLICE_COMPARE_CONFIG_t *) NULL != compare_init); + + /* Program the timer mode */ + slice->TC = compare_init->tc; + /* Enable the timer concatenation */ + slice->CMC = ((uint32_t) compare_init->timer_concatenation << CCU4_CC4_CMC_TCE_Pos); + /* Program initial prescaler divider value */ + slice->PSC = (uint32_t) compare_init->prescaler_initval; + /* Program the dither compare value */ + slice->DITS = (uint32_t) compare_init->dither_limit; + /* Program timer output passive level */ + slice->PSL = (uint32_t) compare_init->passive_level; + /* Program floating prescaler compare value */ + slice->FPCS = (uint32_t) compare_init->float_limit; +} + +/* API to configure CC4 Slice for Capture */ +void XMC_CCU4_SLICE_CaptureInit(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAPTURE_CONFIG_t *const capture_init) +{ + XMC_ASSERT("XMC_CCU4_SLICE_CaptureInit:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_CaptureInit:Capture Init Pointer is NULL", + (XMC_CCU4_SLICE_CAPTURE_CONFIG_t *) NULL != capture_init); + + /* Program the capture mode */ + slice->TC = capture_init->tc; + /* Enable the timer concatenation */ + slice->CMC = ((uint32_t)capture_init->timer_concatenation << CCU4_CC4_CMC_TCE_Pos); + /* Program initial prescaler divider value */ + slice->PSC = (uint32_t) capture_init->prescaler_initval; + /* Program initial floating prescaler compare value */ + slice->FPCS = (uint32_t) capture_init->float_limit; +} + + +/* API to configure the Start trigger function of a slice */ +void XMC_CCU4_SLICE_StartConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_START_MODE_t start_mode) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU4_SLICE_StartConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_StartConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU4_SLICE_StartConfig:Invalid Start Mode", + ((start_mode == XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR) ||\ + (start_mode == XMC_CCU4_SLICE_START_MODE_TIMER_START))); + /* First, Bind the event with the stop function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_STRTS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_STRTS_Pos; + + slice->CMC = cmc; + + tc = slice->TC; + /* Next, Configure the start mode */ + if (start_mode == XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR) + { + tc |= (uint32_t)CCU4_CC4_TC_STRM_Msk; + } + else + { + tc &= ~((uint32_t)CCU4_CC4_TC_STRM_Msk); + } + + slice->TC = tc; +} + +/* API to configure the Stop trigger function of a slice */ +void XMC_CCU4_SLICE_StopConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_END_MODE_t end_mode) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU4_SLICE_StopConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_StopConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU4_SLICE_StopConfig:Invalid Start Mode", XMC_CCU4_CHECK_END_MODE(end_mode)); + + /* First, Bind the event with the stop function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_ENDS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_ENDS_Pos; + + slice->CMC = cmc; + + /* Next, Configure the stop mode */ + tc = slice->TC; + tc &= ~((uint32_t) CCU4_CC4_TC_ENDM_Msk); + tc |= ((uint32_t) end_mode) << CCU4_CC4_TC_ENDM_Pos; + + slice->TC = tc; +} + +/* API to configure the Load trigger function of a slice */ +void XMC_CCU4_SLICE_LoadConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_LoadConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_LoadConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the load function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_LDS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_LDS_Pos; + + slice->CMC = cmc; +} + +/* API to configure the slice modulation function */ +void XMC_CCU4_SLICE_ModulationConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_MODULATION_MODE_t mod_mode, + const bool synch_with_pwm) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU4_SLICE_ModulationConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_ModulationConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU4_SLICE_ModulationConfig:Invalid Modulation Mode", + ((mod_mode == XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT) ||\ + (mod_mode == XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_ST_OUT))); + + tc = slice->TC; + cmc = slice->CMC; + + /* First, Bind the event with the modulation function */ + cmc &= ~((uint32_t) CCU4_CC4_CMC_MOS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_MOS_Pos; + slice->CMC = cmc; + + /* Next, Modulation mode */ + if (mod_mode == XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT) + { + tc |= (uint32_t) CCU4_CC4_TC_EMT_Msk; + } + else + { + tc &= ~((uint32_t) CCU4_CC4_TC_EMT_Msk); + } + + /* Synchronization of modulation effect with PWM cycle */ + if (synch_with_pwm == (bool) true) + { + tc |= (uint32_t) CCU4_CC4_TC_EMS_Msk; + } + else + { + tc &= ~((uint32_t) CCU4_CC4_TC_EMS_Msk); + } + + slice->TC = tc; +} + +/* API to configure the slice count function */ +void XMC_CCU4_SLICE_CountConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_CountConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_CountConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the count function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_CNTS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_CNTS_Pos; + + slice->CMC = cmc; +} + +/* API to configure slice gate function */ +void XMC_CCU4_SLICE_GateConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_GateConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_GateConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the gate function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_GATES_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_GATES_Pos; + + slice->CMC = cmc; +} + +/* API to configure Capture-0 function */ +void XMC_CCU4_SLICE_Capture0Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_Capture0Config:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_Capture0Config:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the gate function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_CAP0S_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_CAP0S_Pos; + + slice->CMC = cmc; +} + +/* API to configure Capture-1 function */ +void XMC_CCU4_SLICE_Capture1Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_Capture1Config:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_Capture1Config:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the gate function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_CAP1S_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_CAP1S_Pos; + + slice->CMC = cmc; +} + +/* API to configure direction function */ +void XMC_CCU4_SLICE_DirectionConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_DirectionConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_DirectionConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + + /* Bind the event with the direction function */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_UDS_Msk); + cmc |= ((uint32_t) event) << CCU4_CC4_CMC_UDS_Pos; + + slice->CMC = cmc; +} + +/* API to configure slice status bit override function */ +void XMC_CCU4_SLICE_StatusBitOverrideConfig(XMC_CCU4_SLICE_t *const slice) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU4_SLICE_StatusBitOverrideConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + + /* Bind the event with the override function */ + cmc = slice->CMC; + /* Map status bit trigger override to Event 1 & + status bit value override to Event 2 */ + cmc &= ~((uint32_t) CCU4_CC4_CMC_OFS_Msk); + cmc |= ((uint32_t) 1) << CCU4_CC4_CMC_OFS_Pos; + + slice->CMC = cmc; +} + +/* API to configure trap function */ +void XMC_CCU4_SLICE_TrapConfig(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_TRAP_EXIT_MODE_t exit_mode, + const bool synch_with_pwm) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU4_SLICE_TrapConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_TrapConfig:Invalid Exit Mode", ((exit_mode == XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC) ||\ + (exit_mode == XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW))); + + /* First, Map trap function to Event 2 */ + cmc = slice->CMC; + cmc &= ~((uint32_t) CCU4_CC4_CMC_TS_Msk); + cmc |= ((uint32_t) 1) << CCU4_CC4_CMC_TS_Pos; + slice->CMC = cmc; + + /* Next, Configure synchronization option */ + tc = slice->TC; + + if (synch_with_pwm == (bool) true) + { + tc |= (uint32_t) CCU4_CC4_TC_TRPSE_Msk; + } + else + { + tc &= ~((uint32_t) CCU4_CC4_TC_TRPSE_Msk); + } + + /* Configure exit mode */ + if (exit_mode == XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW) + { + tc |= (uint32_t) CCU4_CC4_TC_TRPSW_Msk; + } + else + { + tc &= ~((uint32_t) CCU4_CC4_TC_TRPSW_Msk); + } + + slice->TC = tc; +} + +/* API to configure a slice Status Bit Override event */ +void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev2_config) +{ + uint32_t ins; + + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", + XMC_CCU4_SLICE_IsInputvalid(ev1_config->mapped_input)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", + XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(ev1_config->edge)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", + ((ev1_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (ev1_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", + XMC_CCU4_SLICE_CHECK_EVENT_FILTER(ev1_config->duration)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", + XMC_CCU4_SLICE_IsInputvalid(ev2_config->mapped_input)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", + XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(ev2_config->edge)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", + ((ev2_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (ev2_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", + XMC_CCU4_SLICE_CHECK_EVENT_FILTER(ev2_config->duration)); +#if defined(CCU4V3) /* Defined for XMC1400 devices only */ + ins = slice->INS2; + + /* Configure the edge sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS2_EV1EM_Pos); + ins |= ((uint32_t) ev1_config->edge) << CCU4_CC4_INS2_EV1EM_Pos; + + /* Configure the edge sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS2_EV2EM_Pos); + ins |= ((uint32_t) ev2_config->edge) << CCU4_CC4_INS2_EV2EM_Pos; + + /* Configure the level sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS2_EV1LM_Pos); + ins |= ((uint32_t) ev1_config->level) << CCU4_CC4_INS2_EV1LM_Pos; + + /* Configure the level sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS2_EV2LM_Pos); + ins |= ((uint32_t) ev2_config->level) << CCU4_CC4_INS2_EV2LM_Pos; + + /* Configure the debounce filter for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS2_LPF1M_Pos); + ins |= ((uint32_t) ev1_config->duration) << CCU4_CC4_INS2_LPF1M_Pos; + + /* Configure the debounce filter for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS2_LPF2M_Pos); + ins |= ((uint32_t) ev2_config->duration) << CCU4_CC4_INS2_LPF2M_Pos; + + slice->INS2 = ins; + + ins = slice->INS1; + + /* Next, the input for Event1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS1_EV1IS_Pos); + ins |= ((uint32_t) ev1_config->mapped_input) << CCU4_CC4_INS1_EV1IS_Pos; + + /* Finally, the input for Event2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS1_EV2IS_Pos); + ins |= ((uint32_t) ev2_config->mapped_input) << CCU4_CC4_INS1_EV2IS_Pos; + + slice->INS1 = ins; +#else + ins = slice->INS; + + /* Configure the edge sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS_EV1EM_Pos); + ins |= ((uint32_t) ev1_config->edge) << CCU4_CC4_INS_EV1EM_Pos; + + /* Configure the edge sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS_EV2EM_Pos); + ins |= ((uint32_t) ev2_config->edge) << CCU4_CC4_INS_EV2EM_Pos; + + /* Configure the level sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS_EV1LM_Pos); + ins |= ((uint32_t) ev1_config->level) << CCU4_CC4_INS_EV1LM_Pos; + + /* Configure the level sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS_EV2LM_Pos); + ins |= ((uint32_t) ev2_config->level) << CCU4_CC4_INS_EV2LM_Pos; + + /* Configure the debounce filter for event 1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS_LPF1M_Pos); + ins |= ((uint32_t) ev1_config->duration) << CCU4_CC4_INS_LPF1M_Pos; + + /* Configure the debounce filter for event 2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS_LPF2M_Pos); + ins |= ((uint32_t) ev2_config->duration) << CCU4_CC4_INS_LPF2M_Pos; + + /* Next, the input for Event1 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS_EV1IS_Pos); + ins |= ((uint32_t) ev1_config->mapped_input) << CCU4_CC4_INS_EV1IS_Pos; + + /* Finally, the input for Event2 */ + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS_EV2IS_Pos); + ins |= ((uint32_t) ev2_config->mapped_input) << CCU4_CC4_INS_EV2IS_Pos; + + slice->INS = ins; +#endif +} + +/* API to configure a slice trigger event */ +void XMC_CCU4_SLICE_ConfigureEvent(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const config) +{ + uint32_t ins; + uint8_t pos; + uint8_t offset; + + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Input", XMC_CCU4_SLICE_IsInputvalid(config->mapped_input)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Edge Sensitivity", + XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(config->edge)); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Level Sensitivity", + ((config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Debounce Period", + XMC_CCU4_SLICE_CHECK_EVENT_FILTER(config->duration)); + /* Calculate offset with reference to event */ + offset = ((uint8_t) event) - 1U; + +#if defined(CCU4V3) /* Defined for XMC1400 devices only */ + ins = slice->INS2; + + /* First, configure the edge sensitivity */ + pos = ((uint8_t) CCU4_CC4_INS2_EV0EM_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->edge) << pos; + + /* Next, the level */ + pos = ((uint8_t) CCU4_CC4_INS2_EV0LM_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->level) << pos; + + /* Next, the debounce filter */ + pos = ((uint8_t) CCU4_CC4_INS2_LPF0M_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->duration) << pos; + + slice->INS2 = ins; + + ins = slice->INS1; + + /* Finally the input */ + pos = ((uint8_t) CCU4_CC4_INS1_EV0IS_Pos) + (uint8_t)(offset << 3U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->mapped_input) << pos; + + slice->INS1 = ins; + +#else + ins = slice->INS; + + /* First, configure the edge sensitivity */ + pos = ((uint8_t) CCU4_CC4_INS_EV0EM_Pos) + (uint8_t)(offset << 1U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->edge) << pos; + + /* Next, the level */ + pos = ((uint8_t) CCU4_CC4_INS_EV0LM_Pos) + offset; + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->level) << pos; + + /* Next, the debounce filter */ + pos = ((uint8_t) CCU4_CC4_INS_LPF0M_Pos) + (uint8_t)(offset << 1U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->duration) << pos; + + /* Finally the input */ + pos = ((uint8_t) CCU4_CC4_INS_EV0IS_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->mapped_input) << pos; + + slice->INS = ins; +#endif +} + +/* API to bind an input to a slice trigger event */ +void XMC_CCU4_SLICE_SetInput(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_INPUT_t input) +{ + uint32_t ins; + uint8_t pos; + uint8_t offset; + + XMC_ASSERT("XMC_CCU4_SLICE_SetInput:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetInput:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU4_SLICE_SetInput:Invalid Input", XMC_CCU4_SLICE_IsInputvalid(input)); + + /* Calculate offset with reference to event */ + offset = ((uint8_t) event) - 1U; + +#if defined(CCU4V3) /* Defined for XMC1400 devices only */ + pos = ((uint8_t) CCU4_CC4_INS1_EV0IS_Pos) + (uint8_t) (offset << 3U); + + ins = slice->INS1; + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) input) << pos; + + slice->INS1 = ins; +#else + pos = ((uint8_t) CCU4_CC4_INS_EV0IS_Pos) + (uint8_t) (offset << 2U); + + ins = slice->INS; + ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) input) << pos; + + slice->INS = ins; +#endif +} + +/* API to program timer repeat mode - Single shot vs repeat */ +void XMC_CCU4_SLICE_SetTimerRepeatMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t mode) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerRepeatMode:Invalid Timer Repeat Mode", + ((mode == XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT) ||\ + (mode == XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE))); + + if (XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT == mode) + { + slice->TC &= ~((uint32_t) CCU4_CC4_TC_TSSM_Msk); + } + else + { + slice->TC |= (uint32_t) CCU4_CC4_TC_TSSM_Msk; + } +} + +/* Programs timer counting mode */ +void XMC_CCU4_SLICE_SetTimerCountingMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_COUNT_MODE_t mode) +{ + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerCountingMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerCountingMode:Invalid Timer Count Mode", ((mode == XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA) ||\ + (mode == XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA))); + + if (XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA == mode) + { + slice->TC &= ~((uint32_t) CCU4_CC4_TC_TCM_Msk); + } + else + { + slice->TC |= (uint32_t) CCU4_CC4_TC_TCM_Msk; + } +} + +/* Retrieves desired capture register value */ +uint32_t XMC_CCU4_SLICE_GetCaptureRegisterValue(const XMC_CCU4_SLICE_t *const slice, const uint8_t reg_num) +{ + XMC_ASSERT("XMC_CCU4_SLICE_GetCaptureRegisterValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_GetCaptureRegisterValue:Invalid register number", (reg_num < 4U)); + return(slice->CV[reg_num]); +} + +/* @brief Retrieves the latest captured timer value */ +XMC_CCU4_STATUS_t XMC_CCU4_SLICE_GetLastCapturedTimerValue(const XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr) +{ + XMC_CCU4_STATUS_t retval; + uint8_t i; + uint8_t start; + uint8_t end; + + XMC_ASSERT("XMC_CCU4_SLICE_GetLastCapturedTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_GetLastCapturedTimerValue:Invalid Register Set", ((set == XMC_CCU4_SLICE_CAP_REG_SET_LOW) ||\ + (set == XMC_CCU4_SLICE_CAP_REG_SET_HIGH))); + + retval = XMC_CCU4_STATUS_ERROR; + + /* First check if extended capture mode is enabled */ + if ((slice->TC) & CCU4_CC4_TC_ECM_Msk) + { + /* Extended capture mode has been enabled. So start with the lowest capture register and work your way up */ + start = 0U; + end = XMC_CCU4_NUM_SLICES_PER_MODULE; + } + else + { + /* Extended capture mode is not enabled */ + if (set == XMC_CCU4_SLICE_CAP_REG_SET_HIGH) + { + start = ((uint8_t) XMC_CCU4_NUM_SLICES_PER_MODULE) >> 1U; + end = (uint8_t) XMC_CCU4_NUM_SLICES_PER_MODULE; + } + else + { + start = 0U; + end = ((uint8_t) XMC_CCU4_NUM_SLICES_PER_MODULE) >> 1U; + } + } + + for(i=start; i < end; i++) + { + if ( (slice->CV[i]) & CCU4_CC4_CV_FFL_Msk ) + { + *val_ptr = slice->CV[i]; + retval = XMC_CCU4_STATUS_OK; + break; + } + } + + return retval; +} + +/* Retrieves timer capture value from a FIFO made of capture registers */ +#if defined(CCU4V1) /* Defined for XMC4500, XMC400, XMC4200, XMC4100 devices only */ +int32_t XMC_CCU4_GetCapturedValueFromFifo(const XMC_CCU4_MODULE_t *const module, const uint8_t slice_number) +{ + int32_t cap; + uint32_t extracted_slice; + + XMC_ASSERT("XMC_CCU4_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU4_IsValidModule(module)); + + /* First read the global fifo register */ + cap = (int32_t) module->ECRD; + + extracted_slice = (((uint32_t) cap) & ((uint32_t) CCU4_ECRD_SPTR_Msk)) >> CCU4_ECRD_SPTR_Pos; + + /* Return captured result only if it were applicable to this slice */ + if(extracted_slice != ((uint32_t)slice_number)) + { + cap = -1; + } + + return (cap); +} +#else +uint32_t XMC_CCU4_SLICE_GetCapturedValueFromFifo(const XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_CAP_REG_SET_t set) +{ + uint32_t cap; + + XMC_ASSERT("XMC_CCU4_SLICE_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_GetCapturedValueFromFifo:Invalid Register Set", + ((set == XMC_CCU4_SLICE_CAP_REG_SET_LOW) ||\ + (set == XMC_CCU4_SLICE_CAP_REG_SET_HIGH))); + + if(XMC_CCU4_SLICE_CAP_REG_SET_LOW == set) + { + cap = slice->ECRD0; + } + else + { + cap = slice->ECRD1; + } + + return cap; +} +#endif + +/* Enables PWM dithering feature */ +void XMC_CCU4_SLICE_EnableDithering(XMC_CCU4_SLICE_t *const slice, + const bool period_dither, + const bool duty_dither, + const uint8_t spread) +{ + uint32_t tc; + + XMC_ASSERT("XMC_CCU4_SLICE_EnableDithering:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + + tc = slice->TC; + tc &= ~((uint32_t) CCU4_CC4_TC_DITHE_Msk); + + if ((bool) true == period_dither) + { + tc |= (((uint32_t) XMC_CCU4_SLICE_DITHER_PERIOD_MASK) << CCU4_CC4_TC_DITHE_Pos); + } + if ((bool) true == duty_dither) + { + tc |= (((uint32_t) XMC_CCU4_SLICE_DITHER_DUTYCYCLE_MASK) << CCU4_CC4_TC_DITHE_Pos); + } + + slice->TC = tc; + + XMC_CCU4_SLICE_SetDitherCompareValue((XMC_CCU4_SLICE_t *)slice, (uint8_t)spread); +} + +/* Programs Pre-scalar divider */ +void XMC_CCU4_SLICE_SetPrescaler(XMC_CCU4_SLICE_t *const slice, const uint8_t div_val) +{ + uint32_t fpc; + + XMC_ASSERT("XMC_CCU4_SLICE_SetPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + + fpc = slice->FPC; + fpc &= ~((uint32_t) CCU4_CC4_FPC_PVAL_Msk); + fpc |= ((uint32_t) div_val) << CCU4_CC4_FPC_PVAL_Pos; + slice->FPC = fpc; + /* + * In any case, update the initial value of the divider which is to be loaded once the prescaler increments to the + * compare value. + */ + slice->PSC = (uint32_t) div_val; +} + +/* Binds a capcom event to an NVIC node */ +void XMC_CCU4_SLICE_SetInterruptNode(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_IRQ_ID_t event, + const XMC_CCU4_SLICE_SR_ID_t sr) +{ + uint32_t srs; + uint32_t pos; + uint32_t mask; + + XMC_ASSERT("XMC_CCU4_SLICE_SetInterruptNode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetInterruptNode:Invalid SR ID ", XMC_CCU4_SLICE_CHECK_SR_ID(sr)); + XMC_ASSERT("XMC_CCU4_SLICE_SetInterruptNode:Invalid event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); + + srs = slice->SRS; + + switch(event) + { + case XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH: + case XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH: + mask = ((uint32_t) CCU4_CC4_SRS_POSR_Msk); + pos = CCU4_CC4_SRS_POSR_Pos; + break; + + case XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP: + case XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN: + mask = ((uint32_t) CCU4_CC4_SRS_CMSR_Msk); + pos = CCU4_CC4_SRS_CMSR_Pos; + break; + + case XMC_CCU4_SLICE_IRQ_ID_EVENT0: + mask = ((uint32_t) CCU4_CC4_SRS_E0SR_Msk); + pos = CCU4_CC4_SRS_E0SR_Pos; + break; + + case XMC_CCU4_SLICE_IRQ_ID_EVENT1: + mask = ((uint32_t) CCU4_CC4_SRS_E1SR_Msk); + pos = CCU4_CC4_SRS_E1SR_Pos; + break; + + default: + mask = ((uint32_t) CCU4_CC4_SRS_E2SR_Msk); + pos = CCU4_CC4_SRS_E2SR_Pos; + break; + } + + srs &= ~mask; + srs |= (uint32_t)sr << pos; + slice->SRS = srs; +} + +/* Asserts passive level for the slice output */ +void XMC_CCU4_SLICE_SetPassiveLevel(XMC_CCU4_SLICE_t *const slice, + const XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t level) +{ + uint32_t psl; + + XMC_ASSERT("XMC_CCU4_SLICE_SetPassiveLevel:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU4_SLICE_SetPassiveLevel:Invalid Passive level", ((level == XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW) ||\ + (level == XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH))); + + psl = slice->PSL; + psl &= ~((uint32_t) CCU4_CC4_PSL_PSL_Msk); + psl |= (uint32_t) level; + + /* Program CC4 slice output passive level */ + slice->PSL = psl; +} + +#endif /* CCU40 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ccu8.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ccu8.c new file mode 100644 index 00000000..e5ece680 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ccu8.c @@ -0,0 +1,1320 @@ +/** + * @file xmc_ccu8.c + * @date 2017-02-25 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API
+ * - Added XMC_CCU8_SLICE_LoadSelector() API, to select which compare register value has to be loaded + * during external load event. + * + * 2015-07-24: + * - XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
+ * + * 2015-08-17: + * - XMC_CCU8_SLICE_CHC_CONFIG_MASK is not applicable to XMC14 devices.
+ * - Start of prescaler XMC_CCU8_StartPrescaler() is invoked in XMC_CCU8_Init() API.
+ * - In XMC_CCU8_SLICE_CompareInit(), CHC register is updated according to the device.
+ * - Bug fix XMC_CCU8_SLICE_ConfigureEvent() during the level setting for XMC14 devices.
+ * - XMC_CCU8_EnableShadowTransfer() definition is removed, since the API is made as inline.
+ * + * 2015-10-07: + * - XMC_CCU8_SLICE_GetEvent() is made as inline. + * - DOC updates for the newly added APIs. + * + * 2017-02-25: + * - XMC_CCU8_lAssertReset(), XMC_CCU8_lDeassertReset(), XMC_CCU8_lGateClock() and XMC_CCU8_lUngateClock() fix compilation warnings. + * + * @endcond + */ +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_ccu8.h" + +#if defined(CCU80) +#include "xmc_scu.h" + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_CCU8_NUM_SLICES_PER_MODULE (4U) +#define XMC_CCU8_SLICE_DITHER_PERIOD_MASK (1U) +#define XMC_CCU8_SLICE_DITHER_DUTYCYCLE_MASK (2U) +#define XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK (3U) +#define XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK (1U) +#define XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK (3U) +#if defined(CCU8V3) /* Defined for XMC1400 devices */ +#define XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK CCU8_CC8_INS1_EV0IS_Msk +#else +#define XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK CCU8_CC8_INS_EV0IS_Msk +#endif +#define XMC_CCU8_GIDLC_CLOCK_MASK (15U) +#define XMC_CCU8_GCSS_SLICE0_MASK (1U) +#define XMC_CCU8_GCSS_SLICE1_MASK (16U) +#define XMC_CCU8_GCSS_SLICE2_MASK (256U) +#define XMC_CCU8_GCSS_SLICE3_MASK (4096U) +#define XMC_CCU8_SLICE_DEAD_TIME_CONFIG_MASK (63U) +#if !defined(CCU8V3) /* Defined for all devices except XMC1400 */ +#define XMC_CCU8_SLICE_CHC_CONFIG_MASK (20U) +#endif + +#define XMC_CCU8_SLICE_CHECK_DTC_DIV(div) \ + ((div == XMC_CCU8_SLICE_DTC_DIV_1) || \ + (div == XMC_CCU8_SLICE_DTC_DIV_2) || \ + (div == XMC_CCU8_SLICE_DTC_DIV_4) || \ + (div == XMC_CCU8_SLICE_DTC_DIV_8)) + +#define XMC_CCU8_SLICE_CHECK_CLOCK(clock) \ + ((clock == XMC_CCU8_CLOCK_SCU) || \ + (clock == XMC_CCU8_CLOCK_EXTERNAL_A) || \ + (clock == XMC_CCU8_CLOCK_EXTERNAL_B) || \ + (clock == XMC_CCU8_CLOCK_EXTERNAL_C)) + +#define XMC_CCU8_SLICE_CHECK_OUTPUT(out) \ + ((out == XMC_CCU8_SLICE_OUTPUT_0) || \ + (out == XMC_CCU8_SLICE_OUTPUT_1) || \ + (out == XMC_CCU8_SLICE_OUTPUT_2) || \ + (out == XMC_CCU8_SLICE_OUTPUT_3)) + +#define XMC_CCU8_SLICE_CHECK_END_MODE(end_mode) \ + ((end_mode == XMC_CCU8_SLICE_END_MODE_TIMER_STOP) || \ + (end_mode == XMC_CCU8_SLICE_END_MODE_TIMER_CLEAR) || \ + (end_mode == XMC_CCU8_SLICE_END_MODE_TIMER_STOP_CLEAR)) + +#define XMC_CCU8_SLICE_CHECK_EVENT_ID(event_id) \ + ((event_id == XMC_CCU8_SLICE_EVENT_NONE)|| \ + (event_id == XMC_CCU8_SLICE_EVENT_0) || \ + (event_id == XMC_CCU8_SLICE_EVENT_1) || \ + (event_id == XMC_CCU8_SLICE_EVENT_2)) + +#define XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(edge) \ + ((edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_NONE) || \ + (edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE) || \ + (edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE)|| \ + (edge == XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE)) + +#define XMC_CCU8_SLICE_CHECK_EVENT_FILTER(cycles) \ + ((cycles == XMC_CCU8_SLICE_EVENT_FILTER_DISABLED) || \ + (cycles == XMC_CCU8_SLICE_EVENT_FILTER_3_CYCLES) || \ + (cycles == XMC_CCU8_SLICE_EVENT_FILTER_5_CYCLES) || \ + (cycles == XMC_CCU8_SLICE_EVENT_FILTER_7_CYCLES)) + +#define XMC_CCU8_SLICE_CHECK_CAP_TIMER_CLEAR_MODE(mode) \ + ((mode == XMC_CCU8_SLICE_TIMER_CLEAR_MODE_NEVER) || \ + (mode == XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_HIGH)|| \ + (mode == XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_LOW) || \ + (mode == XMC_CCU8_SLICE_TIMER_CLEAR_MODE_ALWAYS)) + +#define XMC_CCU8_SLICE_CHECK_MCS_ACTION(mcs_action) \ + ((mcs_action == XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR) || \ + (mcs_action == XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP) || \ + (mcs_action == XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT)) + +#define XMC_CCU8_SLICE_CHECK_SR_ID(id) \ + ((id == XMC_CCU8_SLICE_SR_ID_0) || \ + (id == XMC_CCU8_SLICE_SR_ID_1) || \ + (id == XMC_CCU8_SLICE_SR_ID_2) || \ + (id == XMC_CCU8_SLICE_SR_ID_3)) + +#define XMC_CCU8_SLICE_CHECK_MODULATION_CHANNEL(channel) \ + ((channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_NONE) || \ + (channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_1) || \ + (channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_2) || \ + (channel == XMC_CCU8_SLICE_MODULATION_CHANNEL_1_AND_2)) + +#if((UC_SERIES == XMC13) || (UC_SERIES == XMC14)) +#define XMC_CCU8_SLICE_CHECK_SLICE_STATUS(channel) \ + ((channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1) || \ + (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_2) || \ + (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1_AND_2) || \ + (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1_OR_2)) +#else +#define XMC_CCU8_SLICE_CHECK_SLICE_STATUS(channel) \ + ((channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1) || \ + (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_2) || \ + (channel == XMC_CCU8_SLICE_STATUS_CHANNEL_1_AND_2)) +#endif + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ +#if defined(PERIPHERAL_RESET_SUPPORTED) +__STATIC_INLINE void XMC_CCU8_lAssertReset(const XMC_CCU8_MODULE_t *const module) +{ + if (module == CCU80) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU80); + } +#if defined(CCU81) + else if (module == CCU81) + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU81); + } +#endif + else + { + XMC_ASSERT("XMC_CCU8_lAssertReset:Invalid Module Pointer", 0); + } +} + +__STATIC_INLINE void XMC_CCU8_lDeassertReset(const XMC_CCU8_MODULE_t *const module) +{ + if (module == CCU80) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU80); + } +#if defined(CCU81) + else if (module == CCU81) + { + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU81); + } +#endif + else + { + XMC_ASSERT("XMC_CCU8_lDeassertReset:Invalid Module Pointer", 0); + } +} +#endif + +#if defined(CLOCK_GATING_SUPPORTED) +__STATIC_INLINE void XMC_CCU8_lGateClock(XMC_CCU8_MODULE_t *const module) +{ + if (module == CCU80) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU80); + } +#if defined(CCU81) + else if (module == CCU81) + { + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU81); + } +#endif + else + { + XMC_ASSERT("XMC_CCU8_lGateClock:Invalid Module Pointer", 0); + } +} + +__STATIC_INLINE void XMC_CCU8_lUngateClock(XMC_CCU8_MODULE_t *const module) +{ + if (module == CCU80) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU80); + } +#if defined(CCU81) + else if (module == CCU81) + { + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_CCU81); + } +#endif + else + { + XMC_ASSERT("XMC_CCU8_lUngateClock:Invalid Module Pointer", 0); + } +} +#endif + +#if defined (XMC_ASSERT_ENABLE) +__STATIC_INLINE bool XMC_CCU8_SLICE_IsInputvalid(XMC_CCU8_SLICE_INPUT_t input) +{ +#if (UC_SERIES == XMC14) + return (input < 48U); +#else + return (input < 16U); +#endif +} +#endif +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/* API to set the CCU8 module as active and enable the clock */ +void XMC_CCU8_EnableModule(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_EnableModule:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + +#if (UC_FAMILY == XMC4) + /* Enable CCU8 module clock */ + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_CCU8_lUngateClock(module); +#endif + +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_CCU8_lDeassertReset(module); +#endif +} + +/* API to set the CCU8 module as idle and disable the clock */ +void XMC_CCU8_DisableModule(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_DisableModule:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_CCU8_lAssertReset(module); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_CCU8_lGateClock(module); +#endif +} + +/* API to initialize CCU8 global resources */ +void XMC_CCU8_Init(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_SLICE_MCMS_ACTION_t mcs_action) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU8_Init:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_Init:Invalid mcs action", XMC_CCU8_SLICE_CHECK_MCS_ACTION(mcs_action)); + + /* Enable CCU8 module */ + XMC_CCU8_EnableModule(module); + /* Start the prescaler */ + XMC_CCU8_StartPrescaler(module); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t) CCU8_GCTRL_MSDE_Msk); + gctrl |= (uint32_t)mcs_action << CCU8_GCTRL_MSDE_Pos; + + module->GCTRL = gctrl; +} + +/* API to select CCU8 module clock */ +void XMC_CCU8_SetModuleClock(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_CLOCK_t clock) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU8_SetModuleClock:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_SetModuleClock:Invalid Module Clock", XMC_CCU8_SLICE_CHECK_CLOCK(clock)); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t) CCU8_GCTRL_PCIS_Msk); + gctrl |= ((uint32_t) clock) << CCU8_GCTRL_PCIS_Pos; + + module->GCTRL = gctrl; +} + +/* API to configure CC8 Slice in Compare mode */ +void XMC_CCU8_SLICE_CompareInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CONFIG_t *const compare_init) +{ + XMC_ASSERT("XMC_CCU8_SLICE_CompareInit:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_CompareInit:Timer Init Pointer is NULL", + (XMC_CCU8_SLICE_COMPARE_CONFIG_t *) NULL != compare_init); + /* Stops the timer */ + XMC_CCU8_SLICE_StopTimer(slice); + /* Program the timer mode */ + slice->TC = compare_init->tc; + /* Enable the timer concatenation */ + slice->CMC = (uint32_t)compare_init->timer_concatenation << CCU8_CC8_CMC_TCE_Pos; + /* Program initial prescaler divider value */ + slice->PSC = (uint32_t) compare_init->prescaler_initval; + /* Program floating prescaler compare value */ + slice->FPCS = (uint32_t) compare_init->float_limit; + /* Program the dither compare value */ + slice->DITS = (uint32_t) compare_init->dither_limit; + /* Program timer output passive level */ + slice->PSL = (uint32_t) compare_init->psl; + /* Asymmetric PWM and Slice output routing configuration */ +#if defined(CCU8V3) /* Defined for XMC1400 devices only */ + slice->CHC = (uint32_t) compare_init->chc; +#else + slice->CHC = (uint32_t)((uint32_t)compare_init->chc ^ XMC_CCU8_SLICE_CHC_CONFIG_MASK); +#endif +} + +/* API to configure CC8 Slice in Capture mode */ +void XMC_CCU8_SLICE_CaptureInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_CAPTURE_CONFIG_t *const capture_init) +{ + XMC_ASSERT("XMC_CCU8_SLICE_CaptureInit:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_CaptureInit:Capture Init Pointer is NULL", + (XMC_CCU8_SLICE_CAPTURE_CONFIG_t *) NULL != capture_init); + /* Stops the timer */ + XMC_CCU8_SLICE_StopTimer(slice); + /* Capture mode configuration */ + slice->TC = capture_init->tc; + /* Enable the timer concatenation */ + slice->CMC = (uint32_t)capture_init->timer_concatenation << CCU8_CC8_CMC_TCE_Pos; + /* Program floating prescaler compare value */ + slice->FPCS = (uint32_t) capture_init->float_limit; + /* Program initial prescaler divider value */ + slice->PSC = (uint32_t) capture_init->prescaler_initval; +} + +/* API to configure the each output of the slice with either STx or inverted STx. */ +void XMC_CCU8_SLICE_SetOutPath(XMC_CCU8_SLICE_t *const slice, const uint32_t out_path_msk) +{ + uint32_t chc; + XMC_ASSERT("XMC_CCU8_SLICE_SetOutPath:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + chc = slice->CHC; +#if !defined(CCU8V3) /* Defined for all devices except XMC1400 */ + chc &= ~((uint32_t)out_path_msk >> 16U); + chc |= ((uint32_t)out_path_msk & 0xFFFFU); +#else + chc &= ~((uint32_t)((uint32_t)(out_path_msk & 0xCCCC0U) >> 2U)); + chc |= ((uint32_t)out_path_msk & 0x33330U); +#endif + slice->CHC = chc; +} + +/* API to configure the multichannel shadow transfer request via SW and via the CCU8x.MCSS input. */ +void XMC_CCU8_SetMultiChannelShadowTransferMode(XMC_CCU8_MODULE_t *const module, const uint32_t slice_mode_msk) +{ + uint32_t gctrl; + + XMC_ASSERT("XMC_CCU8_SetMultiChannelShadowTransferMode:Invalid module Pointer", XMC_CCU8_IsValidModule(module)); + + gctrl = module->GCTRL; + gctrl &= ~((uint32_t)slice_mode_msk >> 16U); + gctrl |= ((uint32_t)slice_mode_msk & 0xFFFFU); + module->GCTRL = gctrl; +} + + +/* API to configure the Start trigger function of a slice*/ +void XMC_CCU8_SLICE_StartConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_START_MODE_t start_mode) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_StartConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_StartConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU8_SLICE_StartConfig:Invalid Start Mode", + ((start_mode == XMC_CCU8_SLICE_START_MODE_TIMER_START) ||\ + (start_mode == XMC_CCU8_SLICE_START_MODE_TIMER_START_CLEAR))); + cmc = slice->CMC; + + cmc &= ~((uint32_t) CCU8_CC8_CMC_STRTS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_STRTS_Pos; + + slice->CMC = cmc; + + tc = slice->TC; + + if(start_mode == XMC_CCU8_SLICE_START_MODE_TIMER_START_CLEAR) + { + tc |= (uint32_t) CCU8_CC8_TC_STRM_Msk; + } + else + { + tc &= ~((uint32_t) CCU8_CC8_TC_STRM_Msk); + } + + slice->TC = tc; +} + +/* API to configure the Stop trigger function of a slice */ +void XMC_CCU8_SLICE_StopConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_END_MODE_t end_mode) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_StopConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_StopConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU8_SLICE_StopConfig:Invalid End Mode", XMC_CCU8_SLICE_CHECK_END_MODE(end_mode)); + + cmc = slice->CMC; + /* First, Bind the event with the stop function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_ENDS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_ENDS_Pos; + + slice->CMC = cmc; + + /* Configure the stop mode */ + tc = slice->TC; + tc &= ~((uint32_t) CCU8_CC8_TC_ENDM_Msk); + tc |= ((uint32_t) end_mode) << CCU8_CC8_TC_ENDM_Pos; + + slice->TC = tc; +} + +/* API to configure the Load trigger function of a slice*/ +void XMC_CCU8_SLICE_LoadConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_LoadConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_LoadConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + cmc = slice->CMC; + + /* First, Bind the event with the load function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_LDS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_LDS_Pos; + + slice->CMC = cmc; +} + +/* API to configure, which compare register value has to be loaded during external load event */ +void XMC_CCU8_SLICE_LoadSelector(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num) +{ + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_LoadSelector:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_LoadSelector:Invalid Channel number", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(ch_num)); + + tc = slice->TC; + + /* First, Bind the event with the load function */ + tc &= ~((uint32_t) CCU8_CC8_TC_TLS_Msk); + tc |= (uint32_t)ch_num << CCU8_CC8_TC_TLS_Pos; + + slice->TC = tc; +} + +/* API to configure the slice modulation function */ +void XMC_CCU8_SLICE_ModulationConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_MODULATION_MODE_t mod_mode, + const XMC_CCU8_SLICE_MODULATION_CHANNEL_t channel, + const bool synch_with_pwm) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid channel for modulation", + XMC_CCU8_SLICE_CHECK_MODULATION_CHANNEL(channel)); + XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid Modulation Mode", + ((mod_mode == XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_ST_OUT) ||\ + (mod_mode == XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_OUT))); + + cmc = slice->CMC; + + /* First, Bind the event with the modulation function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_MOS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_MOS_Pos; + + slice->CMC = cmc; + + tc = slice->TC; + + /* Next, Modulation mode */ + if(mod_mode == XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_OUT) + { + tc |= (uint32_t) CCU8_CC8_TC_EMT_Msk; + } + else + { + tc &= ~((uint32_t) CCU8_CC8_TC_EMT_Msk); + } + + /* Synchronization of modulation effect with PWM cycle */ + if(synch_with_pwm == true) + { + tc |= (uint32_t) CCU8_CC8_TC_EMS_Msk; + } + else + { + tc &= ~((uint32_t) CCU8_CC8_TC_EMS_Msk); + } + + /* Configure on which channel external modulation to be applied */ + tc &= ~((uint32_t) CCU8_CC8_TC_EME_Msk); + tc |= (uint32_t)channel << CCU8_CC8_TC_EME_Pos; + + slice->TC = tc; +} + +/* API to configure the slice count function */ +void XMC_CCU8_SLICE_CountConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_CountConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_CountConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + cmc = slice->CMC; + + /* First, Bind the event with the count function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_CNTS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_CNTS_Pos; + + slice->CMC = cmc; +} + +/* API to configure slice gate function */ +void XMC_CCU8_SLICE_GateConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_GateConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GateConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + cmc = slice->CMC; + + /* First, Bind the event with the gate function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_GATES_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_GATES_Pos; + + slice->CMC = cmc; +} + +/* API to configure Capture-0 function */ +void XMC_CCU8_SLICE_Capture0Config(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_Capture0Config:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_Capture0Config:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + cmc = slice->CMC; + + /* First, Bind the event with the gate function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_CAP0S_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_CAP0S_Pos; + + slice->CMC = cmc; +} + +/* API to configure Capture-1 function */ +void XMC_CCU8_SLICE_Capture1Config(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_Capture1Config:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_Capture1Config:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + + cmc = slice->CMC; + + /* First, Bind the event with the gate function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_CAP1S_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_CAP1S_Pos; + + slice->CMC = cmc; +} + +/* API to configure direction function */ +void XMC_CCU8_SLICE_DirectionConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_DirectionConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_DirectionConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + + cmc = slice->CMC; + + /* First, Bind the event with the direction function */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_UDS_Msk); + cmc |= ((uint32_t) event) << CCU8_CC8_CMC_UDS_Pos; + + slice->CMC = cmc; +} + +/* API to configure slice status bit override function */ +void XMC_CCU8_SLICE_StatusBitOverrideConfig(XMC_CCU8_SLICE_t *const slice) +{ + uint32_t cmc; + + XMC_ASSERT("XMC_CCU8_SLICE_StatusBitOverrideConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + + cmc = slice->CMC; + + /* Map status bit trigger override to Event 1 & + status bit value override to Event 2 */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_OFS_Msk); + cmc |= ((uint32_t) 1) << CCU8_CC8_CMC_OFS_Pos; + + slice->CMC = cmc; +} + +/* API to configure trap function*/ +void XMC_CCU8_SLICE_TrapConfig(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_TRAP_EXIT_MODE_t exit_mode, + const bool synch_with_pwm) +{ + uint32_t cmc; + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_TrapConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_TrapConfig:Invalid Exit Mode", ((exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_AUTOMATIC) ||\ + (exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW))); + + cmc = slice->CMC; + + /* Map trap function to Event 2 */ + cmc &= ~((uint32_t) CCU8_CC8_CMC_TS_Msk); + cmc |= ((uint32_t) 1) << CCU8_CC8_CMC_TS_Pos; + + slice->CMC = cmc; + + tc = slice->TC; + + /* Configure synchronization option */ + if(synch_with_pwm == true) + { + tc |= (uint32_t) CCU8_CC8_TC_TRPSE_Msk; + } + else + { + tc &= ~((uint32_t) CCU8_CC8_TC_TRPSE_Msk); + } + + /* Configure exit mode */ + if(exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW) + { + tc |= (uint32_t) CCU8_CC8_TC_TRPSW_Msk; + } + else + { + tc &= ~((uint32_t) CCU8_CC8_TC_TRPSW_Msk); + } + + slice->TC = tc; +} + +/* API to configure a slice Status Bit Override event */ +void XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev2_config) +{ + uint32_t ins; + + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", + XMC_CCU8_SLICE_IsInputvalid(ev1_config->mapped_input)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", + XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(ev1_config->edge)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", + ((ev1_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (ev1_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", + XMC_CCU8_SLICE_CHECK_EVENT_FILTER(ev1_config->duration)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", + XMC_CCU8_SLICE_IsInputvalid(ev2_config->mapped_input)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", + XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(ev2_config->edge)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", + ((ev2_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (ev2_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", + XMC_CCU8_SLICE_CHECK_EVENT_FILTER(ev2_config->duration)); + +#if defined(CCU8V3) /* Defined for XMC1400 devices only */ + ins = slice->INS2; + + /* Configure the edge sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU8_CC8_INS2_EV1EM_Pos); + ins |= ((uint32_t) ev1_config->edge) << CCU8_CC8_INS2_EV1EM_Pos; + + /* Configure the edge sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU8_CC8_INS2_EV2EM_Pos); + ins |= ((uint32_t) ev2_config->edge) << CCU8_CC8_INS2_EV2EM_Pos; + + /* Configure the level sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU8_CC8_INS2_EV1LM_Pos); + ins |= ((uint32_t) ev1_config->level) << CCU8_CC8_INS2_EV1LM_Pos; + + /* Configure the level sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU8_CC8_INS2_EV2LM_Pos); + ins |= ((uint32_t) ev2_config->level) << CCU8_CC8_INS2_EV2LM_Pos; + + /* Configure the debounce filter for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU8_CC8_INS2_LPF1M_Pos); + ins |= ((uint32_t) ev1_config->duration) << CCU8_CC8_INS2_LPF1M_Pos; + + /* Configure the debounce filter for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU8_CC8_INS2_LPF2M_Pos); + ins |= ((uint32_t) ev2_config->duration) << CCU8_CC8_INS2_LPF2M_Pos; + + slice->INS2 = ins; + + ins = slice->INS1; + /* Next, the input for Event1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU8_CC8_INS1_EV1IS_Pos); + ins |= ((uint32_t) ev1_config->mapped_input) << CCU8_CC8_INS1_EV1IS_Pos; + + /* Finally, the input for Event2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU8_CC8_INS1_EV2IS_Pos); + ins |= ((uint32_t) ev2_config->mapped_input) << CCU8_CC8_INS1_EV2IS_Pos; + + slice->INS1 = ins; +#else + ins = slice->INS; + + /* Configure the edge sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU8_CC8_INS_EV1EM_Pos); + ins |= ((uint32_t) ev1_config->edge) << CCU8_CC8_INS_EV1EM_Pos; + + /* Configure the edge sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU8_CC8_INS_EV2EM_Pos); + ins |= ((uint32_t) ev2_config->edge) << CCU8_CC8_INS_EV2EM_Pos; + + /* Configure the level sensitivity for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU8_CC8_INS_EV1LM_Pos); + ins |= ((uint32_t) ev1_config->level) << CCU8_CC8_INS_EV1LM_Pos; + + /* Configure the level sensitivity for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU8_CC8_INS_EV2LM_Pos); + ins |= ((uint32_t) ev2_config->level) << CCU8_CC8_INS_EV2LM_Pos; + + /* Configure the debounce filter for event 1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU8_CC8_INS_LPF1M_Pos); + ins |= ((uint32_t) ev1_config->duration) << CCU8_CC8_INS_LPF1M_Pos; + + /* Configure the debounce filter for event 2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU8_CC8_INS_LPF2M_Pos); + ins |= ((uint32_t) ev2_config->duration) << CCU8_CC8_INS_LPF2M_Pos; + + /* Next, the input for Event1 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU8_CC8_INS_EV1IS_Pos); + ins |= ((uint32_t) ev1_config->mapped_input) << CCU8_CC8_INS_EV1IS_Pos; + + /* Finally, the input for Event2 */ + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU8_CC8_INS_EV2IS_Pos); + ins |= ((uint32_t) ev2_config->mapped_input) << CCU8_CC8_INS_EV2IS_Pos; + + slice->INS = ins; +#endif +} + +/* API to configure a slice trigger event */ +void XMC_CCU8_SLICE_ConfigureEvent(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const config) +{ + uint32_t ins; + uint8_t pos; + uint8_t offset; + + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Input", XMC_CCU8_SLICE_IsInputvalid(config->mapped_input)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Edge Sensitivity", + XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(config->edge)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Level Sensitivity", + ((config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + (config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Debounce Period", + XMC_CCU8_SLICE_CHECK_EVENT_FILTER(config->duration)); + + /* Calculate offset with reference to event */ + offset = ((uint8_t) event) - 1U; + +#if defined(CCU8V3) /* Defined for XMC1400 devices only */ + ins = slice->INS2; + + /* First, configure the edge sensitivity */ + pos = ((uint8_t) CCU8_CC8_INS2_EV0EM_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->edge) << pos; + + /* Next, the level */ + pos = ((uint8_t) CCU8_CC8_INS2_EV0LM_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << pos); + ins |= ((uint32_t) (config->level)) << pos; + + /* Next, the debounce filter */ + pos = ((uint8_t) CCU8_CC8_INS2_LPF0M_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->duration) << pos; + + slice->INS2 = ins; + + ins = slice->INS1; + + /* Finally the input */ + pos = ((uint8_t) CCU8_CC8_INS1_EV0IS_Pos) + (uint8_t)(offset << 3U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->mapped_input) << pos; + + slice->INS1 = ins; + +#else + ins = slice->INS; + + /* First, configure the edge sensitivity */ + pos = ((uint8_t) CCU8_CC8_INS_EV0EM_Pos) + (uint8_t)(offset << 1U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_EDGE_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->edge) << pos; + + /* Next, the level */ + pos = ((uint8_t) CCU8_CC8_INS_EV0LM_Pos) + offset; + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_LEVEL_CONFIG_MASK) << pos); + ins |= ((uint32_t) (config->level)) << pos; + + /* Next, the debounce filter */ + pos = ((uint8_t) CCU8_CC8_INS_LPF0M_Pos) + (uint8_t)(offset << 1U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->duration) << pos; + + /* Finally the input */ + pos = ((uint8_t) CCU8_CC8_INS_EV0IS_Pos) + (uint8_t)(offset << 2U); + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) config->mapped_input) << pos; + + slice->INS = ins; +#endif +} + +/* API to bind an input to a slice trigger event */ +void XMC_CCU8_SLICE_SetInput(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_INPUT_t input) +{ + uint32_t ins; + uint8_t pos; + uint8_t offset; + + XMC_ASSERT("XMC_CCU8_SLICE_SetInput:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetInput:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); + XMC_ASSERT("XMC_CCU8_SLICE_SetInput:Invalid Input", XMC_CCU8_SLICE_IsInputvalid(input)); + + /* Calculate offset with reference to event */ + offset = ((uint8_t) event) - 1U; + +#if defined(CCU8V3) /* Defined for XMC1400 devices only */ + pos = ((uint8_t) CCU8_CC8_INS1_EV0IS_Pos) + (uint8_t) (offset << 3U); + ins = slice->INS1; + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) input) << pos; + + slice->INS1 = ins; +#else + + pos = ((uint8_t) CCU8_CC8_INS_EV0IS_Pos) + (uint8_t) (offset << 2U); + ins = slice->INS; + ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << pos); + ins |= ((uint32_t) input) << pos; + + slice->INS = ins; +#endif +} + +/* API to program timer repeat mode - Single shot vs repeat */ +void XMC_CCU8_SLICE_SetTimerRepeatMode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t mode) +{ + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerRepeatMode:Invalid Timer Repeat Mode", + ((mode == XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT) ||\ + (mode == (mode == XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT)))); + + tc = slice->TC; + + if(XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT == mode) + { + tc &= ~((uint32_t) CCU8_CC8_TC_TSSM_Msk); + } + else + { + tc |= (uint32_t) CCU8_CC8_TC_TSSM_Msk; + } + + slice->TC = tc; +} + +/* Programs timer counting mode */ +void XMC_CCU8_SLICE_SetTimerCountingMode(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_TIMER_COUNT_MODE_t mode) +{ + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCountingMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCountingMode:Invalid Timer Count Mode", + ((mode == XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA) ||\ + (mode == XMC_CCU8_SLICE_TIMER_COUNT_MODE_CA))); + + tc = slice->TC; + + if(XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA == mode) + { + tc &= ~((uint32_t) CCU8_CC8_TC_TCM_Msk); + } + else + { + tc |= (uint32_t) CCU8_CC8_TC_TCM_Msk; + } + + slice->TC = tc; +} + +/* Programs period match value of the timer */ +void XMC_CCU8_SLICE_SetTimerPeriodMatch(XMC_CCU8_SLICE_t *const slice, const uint16_t period_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + slice->PRS = (uint32_t) period_val; +} + +/* Retrieves desired capture register value */ +uint32_t XMC_CCU8_SLICE_GetCaptureRegisterValue(const XMC_CCU8_SLICE_t *const slice, const uint8_t reg_num) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetCaptureRegisterValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GetCaptureRegisterValue:Invalid register number", (reg_num < 4U)); + return(slice->CV[reg_num]); +} + +/* @brief Retrieves the latest captured timer value */ +XMC_CCU8_STATUS_t XMC_CCU8_SLICE_GetLastCapturedTimerValue(const XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr) +{ + + XMC_CCU8_STATUS_t retval; + uint8_t i; + uint8_t start; + uint8_t end; + + XMC_ASSERT("XMC_CCU8_SLICE_GetLastCapturedTimerValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GetLastCapturedTimerValue:Invalid Register Set", + ((set == XMC_CCU8_SLICE_CAP_REG_SET_LOW) ||\ + (set == XMC_CCU8_SLICE_CAP_REG_SET_HIGH))); + + retval = XMC_CCU8_STATUS_ERROR; + + /* First check if extended capture mode is enabled */ + if((slice->TC) & CCU8_CC8_TC_ECM_Msk) + { + /* Extended capture mode has been enabled. So start with the lowest capture register and work your way up */ + start = 0U; + end = XMC_CCU8_NUM_SLICES_PER_MODULE; + } + else + { + /* Extended capture mode is not enabled */ + if(set == XMC_CCU8_SLICE_CAP_REG_SET_HIGH) + { + start = ((uint8_t) XMC_CCU8_NUM_SLICES_PER_MODULE) >> 1U; + end = (uint8_t) XMC_CCU8_NUM_SLICES_PER_MODULE; + } + else + { + start = 0U; + end = ((uint8_t) XMC_CCU8_NUM_SLICES_PER_MODULE) >> 1U; + } + } + + for(i=start; iCV[i]) & CCU8_CC8_CV_FFL_Msk ) + { + *val_ptr = slice->CV[i]; + retval = XMC_CCU8_STATUS_OK; + break; + } + } + + return retval; +} +/* Retrieves timer capture value from a FIFO made of capture registers */ +#if defined(CCU8V1) /* Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only */ +int32_t XMC_CCU8_GetCapturedValueFromFifo(const XMC_CCU8_MODULE_t *const module, const uint8_t slice_number) +{ + int32_t cap; + uint32_t extracted_slice; + + XMC_ASSERT("XMC_CCU8_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU8_IsValidModule(module)); + + /* First read the global fifo register */ + cap = (int32_t) module->ECRD; + + extracted_slice = (((uint32_t) cap) & ((uint32_t) CCU8_ECRD_SPTR_Msk)) >> CCU8_ECRD_SPTR_Pos; + + /* Return captured result only if it were applicable to this slice */ + if(extracted_slice != ((uint32_t)slice_number)) + { + cap = -1; + } + + return (cap); +} +#else +/* Retrieves timer capture value from a FIFO made of capture registers */ +uint32_t XMC_CCU8_SLICE_GetCapturedValueFromFifo(const XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_CAP_REG_SET_t set) +{ + uint32_t cap; + + XMC_ASSERT("XMC_CCU8_SLICE_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GetCapturedValueFromFifo:Invalid Register Set", + ((set == XMC_CCU8_SLICE_CAP_REG_SET_LOW) ||\ + (set == XMC_CCU8_SLICE_CAP_REG_SET_HIGH))); + + if(XMC_CCU8_SLICE_CAP_REG_SET_LOW == set) + { + cap = slice->ECRD0; + } + else + { + cap = slice->ECRD1; + } + + return cap; +} +#endif + +/* Enables PWM dithering feature */ +void XMC_CCU8_SLICE_EnableDithering(XMC_CCU8_SLICE_t *const slice, + const bool period_dither, + const bool duty_dither, + const uint8_t spread) +{ + uint32_t tc; + + XMC_ASSERT("XMC_CCU8_SLICE_EnableDithering:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + + tc = slice->TC; + tc &= ~((uint32_t) CCU8_CC8_TC_DITHE_Msk); + + if(true == period_dither) + { + tc |= (((uint32_t) XMC_CCU8_SLICE_DITHER_PERIOD_MASK) << CCU8_CC8_TC_DITHE_Pos); + } + if(true == duty_dither) + { + tc |= (((uint32_t) XMC_CCU8_SLICE_DITHER_DUTYCYCLE_MASK) << CCU8_CC8_TC_DITHE_Pos); + } + + slice->TC = tc; + + XMC_CCU8_SLICE_SetDitherCompareValue((XMC_CCU8_SLICE_t *)slice, (uint8_t)spread); +} + +/* Programs Pre-scaler divider */ +void XMC_CCU8_SLICE_SetPrescaler(XMC_CCU8_SLICE_t *const slice, const uint8_t div_val) +{ + uint32_t fpc; + + XMC_ASSERT("XMC_CCU8_SLICE_SetPrescaler:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + + /* If the prescaler is not running, update directly the divider*/ + fpc = slice->FPC; + fpc &= ~((uint32_t) CCU8_CC8_FPC_PVAL_Msk); + fpc |= ((uint32_t) div_val) << CCU8_CC8_FPC_PVAL_Pos; + slice->FPC = fpc; + + /* + * In any case, update the initial value of the divider which is to be loaded once the prescaler increments to the + * compare value. + */ + slice->PSC = (uint32_t) div_val; +} + +/* Programs timer compare match value for channel 1 or 2 */ +void XMC_CCU8_SLICE_SetTimerCompareMatch(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, + const uint16_t compare_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCompareMatch:Invalid channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(channel)); + + if (XMC_CCU8_SLICE_COMPARE_CHANNEL_1 == channel) + { + slice->CR1S = (uint32_t) compare_val; + } + else + { + slice->CR2S = (uint32_t) compare_val; + } +} + +/* Returns the timer compare match value for channel 1 or 2 */ +uint16_t XMC_CCU8_SLICE_GetTimerCompareMatch(const XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel) +{ + uint16_t compare_value; + + XMC_ASSERT("XMC_CCU8_SLICE_GetCompareMatch:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_GetCompareMatch:Invalid channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(channel)); + + if (XMC_CCU8_SLICE_COMPARE_CHANNEL_1 == channel) + { + compare_value = (uint16_t) slice->CR1; + } + else + { + compare_value = (uint16_t) slice->CR2; + } + + return(compare_value); +} + +/* Binds a capcom event to an NVIC node */ +void XMC_CCU8_SLICE_SetInterruptNode(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_IRQ_ID_t event, + const XMC_CCU8_SLICE_SR_ID_t sr) +{ + uint32_t srs; + uint32_t mask; + uint32_t pos; + + XMC_ASSERT("XMC_CCU8_SLICE_SetInterruptNode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetInterruptNode:Invalid SR ID ", XMC_CCU8_SLICE_CHECK_SR_ID(sr)); + XMC_ASSERT("XMC_CCU8_SLICE_SetInterruptNode:Invalid event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); + + srs = slice->SRS; + + switch(event) + { + case XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH: + case XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH: + mask = ((uint32_t) CCU8_CC8_SRS_POSR_Msk); + pos = CCU8_CC8_SRS_POSR_Pos; + break; + + case XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_1: + case XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_1: + mask = ((uint32_t) CCU8_CC8_SRS_CM1SR_Msk); + pos = CCU8_CC8_SRS_CM1SR_Pos; + break; + + case XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_2: + case XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_2: + mask = ((uint32_t) CCU8_CC8_SRS_CM2SR_Msk); + pos = CCU8_CC8_SRS_CM2SR_Pos; + break; + + case XMC_CCU8_SLICE_IRQ_ID_EVENT0: + mask = ((uint32_t) CCU8_CC8_SRS_E0SR_Msk); + pos = CCU8_CC8_SRS_E0SR_Pos; + break; + + case XMC_CCU8_SLICE_IRQ_ID_EVENT1: + mask = ((uint32_t) CCU8_CC8_SRS_E1SR_Msk); + pos = CCU8_CC8_SRS_E1SR_Pos; + break; + + default: + mask = ((uint32_t) CCU8_CC8_SRS_E2SR_Msk); + pos = CCU8_CC8_SRS_E2SR_Pos; + break; + } + + srs &= ~mask; + srs |= (uint32_t)sr << pos; + + slice->SRS = srs; +} + +/* Asserts passive level for the slice output */ +void XMC_CCU8_SLICE_SetPassiveLevel(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_OUTPUT_t out, + const XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t level) +{ + uint32_t psl; + + XMC_ASSERT("XMC_CCU8_SLICE_SetPassiveLevel:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetPassiveLevel:Invalid Slice Output", XMC_CCU8_SLICE_CHECK_OUTPUT(out)); + XMC_ASSERT("XMC_CCU8_SLICE_SetPassiveLevel:Invalid Passive Level", + ((level == XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_LOW) ||\ + (level == XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH))); + + psl = slice->PSL; + + psl &= ~((uint32_t) out); + psl |= (uint32_t) level << ((uint32_t)out >> 1U); + + /* Program CC8 slice output passive level */ + slice->PSL = psl; +} + +/* Initializes Dead time configuration for the slice outputs */ +void XMC_CCU8_SLICE_DeadTimeInit(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_DEAD_TIME_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureDeadTime:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + + /* Program dead time value for channel 1 */ + slice->DC1R = config->dc1r; + /* Program dead time value for channel 2 */ + slice->DC2R = config->dc2r; + /* Program dead time control configuration */ + slice->DTC = config->dtc; +} + +/* Activates or deactivates dead time for compare channel and ST path */ +void XMC_CCU8_SLICE_ConfigureDeadTime(XMC_CCU8_SLICE_t *const slice, const uint8_t mask) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureDeadTime:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureDeadTime:Invalid Channel", (mask <= XMC_CCU8_SLICE_DEAD_TIME_CONFIG_MASK)); + + slice->DTC &= ~((uint32_t) XMC_CCU8_SLICE_DEAD_TIME_CONFIG_MASK); + slice->DTC |= (uint32_t) mask; +} + +/* Configures rising edge delay and falling edge delay for dead time */ +void XMC_CCU8_SLICE_SetDeadTimeValue(XMC_CCU8_SLICE_t *const slice, + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, + const uint8_t rise_value, + const uint8_t fall_value) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetDeadTimeValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetDeadTimeValue:Invalid channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(channel)); + + if (XMC_CCU8_SLICE_COMPARE_CHANNEL_1 == channel) + { + slice->DC1R = (((uint32_t) fall_value) << CCU8_CC8_DC1R_DT1F_Pos) | ((uint32_t) rise_value); + } + else + { + slice->DC2R = (((uint32_t) fall_value) << CCU8_CC8_DC2R_DT2F_Pos) | ((uint32_t) rise_value); + } +} + +/* Configures clock division factor for dead time */ +void XMC_CCU8_SLICE_SetDeadTimePrescaler(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_DTC_DIV_t div_val) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetDeadTimePrescaler:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_SetDeadTimePrescaler:Invalid divider value", XMC_CCU8_SLICE_CHECK_DTC_DIV(div_val)); + + slice->DTC &= ~((uint32_t) CCU8_CC8_DTC_DTCC_Msk); + slice->DTC |= ((uint32_t) div_val) << CCU8_CC8_DTC_DTCC_Pos; +} + +/* Configures status ST1, ST2 mapping to STy */ +void XMC_CCU8_SLICE_ConfigureStatusBitOutput(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_STATUS_t channel) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOutput:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOutput:Invalid Channel", XMC_CCU8_SLICE_CHECK_SLICE_STATUS(channel)); + + slice->TC &= ~((uint32_t) CCU8_CC8_TC_STOS_Msk); + slice->TC |= ((uint32_t) channel) << CCU8_CC8_TC_STOS_Pos; +} + +#endif /* CCU80 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_common.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_common.c new file mode 100644 index 00000000..73101ee4 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_common.c @@ -0,0 +1,219 @@ +/** + * @file xmc_common.c + * @date 2017-02-25 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2017-02-25: + * - Remove the need to define XMC_USER_ASSERT_FUNCTION + * - XMC_AssertHandler fixed compilation warnings + * + * @endcond + * + */ + +#include "xmc_common.h" + +/******************************************************************************* + * DATA STRUCTURES + *******************************************************************************/ +struct list +{ + struct list *next; +}; + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ +#if defined(XMC_ASSERT_ENABLE) +__WEAK void XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line) +{ + XMC_UNUSED_ARG(msg); + XMC_UNUSED_ARG(file); + XMC_UNUSED_ARG(line); + + while(1) + { + /* Endless loop */ + } +} +#endif + +void XMC_LIST_Init(XMC_LIST_t *list) +{ + *list = NULL; +} + +void *XMC_LIST_GetHead(XMC_LIST_t *list) +{ + return *list; +} + +void *XMC_LIST_GetTail(XMC_LIST_t *list) +{ + struct list *tail; + + if (*list == NULL) + { + tail = NULL; + } + else + { + for (tail = (struct list *)*list; tail->next != NULL; tail = tail->next) + { + /* Loop through the list */ + } + } + + return tail; +} + +void XMC_LIST_Add(XMC_LIST_t *list, void *item) +{ + struct list *tail; + + ((struct list *)item)->next = NULL; + tail = (struct list *)XMC_LIST_GetTail(list); + + if (tail == NULL) + { + *list = item; + } + else + { + tail->next = (struct list *)item; + } +} + +void XMC_LIST_Remove(XMC_LIST_t *list, void *item) +{ + struct list *right, *left; + + if (*list != NULL) + { + left = NULL; + for(right = (struct list *)*list; right != NULL; right = right->next) + { + if(right == item) + { + if(left == NULL) + { + /* First on list */ + *list = right->next; + } + else + { + /* Not first on list */ + left->next = right->next; + } + right->next = NULL; + break; + } + left = right; + } + } +} + +void XMC_LIST_Insert(XMC_LIST_t *list, void *prev_item, void *new_item) +{ + if (prev_item == NULL) + { + ((struct list *)new_item)->next = (struct list *)*list; + *list = new_item; + } + else + { + ((struct list *)new_item)->next = ((struct list *)prev_item)->next; + ((struct list *)prev_item)->next = (struct list *)new_item; + } +} + +void XMC_PRIOARRAY_Init(XMC_PRIOARRAY_t *prioarray) +{ + XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL); + + /* Initialize head, next points to tail, previous to NULL and the priority is MININT */ + prioarray->items[prioarray->size].next = prioarray->size + 1; + prioarray->items[prioarray->size].previous = -1; + prioarray->items[prioarray->size].priority = INT32_MAX; + + /* Initialize tail, next points to NULL, previous is the head and the priority is MAXINT */ + prioarray->items[prioarray->size + 1].next = -1; + prioarray->items[prioarray->size + 1].previous = prioarray->size; + prioarray->items[prioarray->size + 1].priority = INT32_MIN; + +} + +void XMC_PRIOARRAY_Add(XMC_PRIOARRAY_t *prioarray, int32_t item, int32_t priority) +{ + int32_t next; + int32_t previous; + + XMC_ASSERT("XMC_PRIOARRAY_Add: item out of range", (item >= 0) && (item < prioarray->size)); + + next = XMC_PRIOARRAY_GetHead(prioarray); + while (XMC_PRIOARRAY_GetItemPriority(prioarray, next) > priority) + { + next = XMC_PRIOARRAY_GetItemNext(prioarray, next); + } + + previous = prioarray->items[next].previous; + + prioarray->items[item].next = next; + prioarray->items[item].previous = previous; + prioarray->items[item].priority = priority; + + prioarray->items[previous].next = item; + prioarray->items[next].previous = item; +} + +void XMC_PRIOARRAY_Remove(XMC_PRIOARRAY_t *prioarray, int32_t item) +{ + int32_t next; + int32_t previous; + + XMC_ASSERT("XMC_PRIOARRAY_Add: item out of range", (item >= 0) && (item < prioarray->size)); + + next = prioarray->items[item].next; + previous = prioarray->items[item].previous; + + prioarray->items[previous].next = next; + prioarray->items[next].previous = previous; +} + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_dac.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_dac.c new file mode 100644 index 00000000..20e5291e --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_dac.c @@ -0,0 +1,339 @@ +/** + * @file xmc_dac.c + * @date 2015-06-19 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Initial version + * + * 2015-06-19: + * - Removed GetDriverVersion API + * @endcond + * + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include +#include + +/* DAC peripheral is not available on XMC1X devices. */ +#if defined(DAC) + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define XMC_DAC_MIN_FREQ_DIVIDER (16U) +#define XMC_DAC_MAX_FREQ_DIVIDER (1048576U) +#define XMC_DAC_DAC0PATL_PAT_BITSIZE (5U) + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +/* API to enable the DAC module */ +void XMC_DAC_Enable(XMC_DAC_t *const dac) +{ + XMC_UNUSED_ARG(dac); + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DAC); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DAC); +} + +/* API to disable the DAC module */ +void XMC_DAC_Disable(XMC_DAC_t *const dac) +{ + XMC_UNUSED_ARG(dac); + + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DAC); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DAC); +#endif +} + +/* API to check whether DAC is enabled */ +bool XMC_DAC_IsEnabled(const XMC_DAC_t *const dac) +{ + bool status; + + XMC_UNUSED_ARG(dac); + + status = XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DAC); + if(status == true) + { + status = false; + } + else + { + status = true; + } + return (status); +} + +/* API to initialize DAC channel configuration */ +void XMC_DAC_CH_Init(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_CONFIG_t *const config) +{ + XMC_DAC_Enable(dac); + + dac->DACCFG[channel].low = config->cfg0; + dac->DACCFG[channel].high = config->cfg1; + if (channel < XMC_DAC_NO_CHANNELS) + { + XMC_DAC_CH_EnableOutput(dac, channel); + } +} + +/* API to set the waveform frequency except in Ramp and Pattern generation mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetFrequency(XMC_DAC_t *const dac, + const uint8_t channel, + const uint32_t frequency) +{ + uint32_t divider; + XMC_DAC_CH_STATUS_t status; + + XMC_ASSERT("XMC_DAC_CH_SetFrequency: frequency must be greater than zero", frequency > 0U); + + divider = XMC_SCU_CLOCK_GetPeripheralClockFrequency() / frequency; + + if (divider < XMC_DAC_MIN_FREQ_DIVIDER) + { + status = XMC_DAC_CH_STATUS_ERROR_FREQ2HIGH; + } + else if (divider >= XMC_DAC_MAX_FREQ_DIVIDER) + { + status = XMC_DAC_CH_STATUS_ERROR_FREQ2LOW; + } + else { + dac->DACCFG[channel].low = (dac->DACCFG[channel].low & (uint32_t)(~DAC_DAC0CFG0_FREQ_Msk)) | + (divider << DAC_DAC0CFG0_FREQ_Pos); + status = XMC_DAC_CH_STATUS_OK; + } + + return status; +} + +/* API to set the waveform frequency in Ramp Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetRampFrequency(XMC_DAC_t *const dac, + const uint8_t channel, + const uint32_t frequency) +{ + uint32_t stop; + uint32_t start; + + start = dac->DACDATA[channel]; + stop = (dac->DAC01DATA >> (channel * DAC_DAC01DATA_DATA1_Pos)) & (uint32_t)DAC_DAC01DATA_DATA0_Msk; + + return XMC_DAC_CH_SetFrequency(dac, channel, frequency * ((stop - start) + 1U)); +} + +/* API to start the operation in Single Value Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartSingleValueMode(XMC_DAC_t *const dac, const uint8_t channel) +{ + XMC_ASSERT("XMC_DAC_CH_StartSingleValueMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_StartSingleValueMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_StartSingleValueMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_SINGLE); + + return XMC_DAC_CH_STATUS_OK; +} + +/* API to start the operation in Data Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartDataMode(XMC_DAC_t *const dac, + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) +{ + XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; + + XMC_ASSERT("XMC_DAC_CH_StartDataMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_StartDataMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_StartDataMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE); + + if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL) + { + status = XMC_DAC_CH_SetFrequency(dac, channel, frequency); + } + + if (status == XMC_DAC_CH_STATUS_OK) + { + XMC_DAC_CH_SetTrigger(dac, channel, trigger); + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_DATA); + } + + return status; +} + +/* API to start the operation in Ramp Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartRampMode(XMC_DAC_t *const dac, + const uint8_t channel, + const uint16_t start, + const uint16_t stop, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) +{ + XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; + + XMC_ASSERT("XMC_DAC_CH_StartRampMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_StartRampMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_StartRampMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE); + + XMC_DAC_CH_SetRampStart(dac, channel, start); + XMC_DAC_CH_SetRampStop(dac, channel, stop); + XMC_DAC_CH_SetTrigger(dac, channel, trigger); + + if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL) + { + status = XMC_DAC_CH_SetRampFrequency(dac, channel, frequency); + } + + if (status == XMC_DAC_CH_STATUS_OK) + { + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_RAMP); + } + + return status; +} + +/* API to start the operation in Pattern Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartPatternMode(XMC_DAC_t *const dac, + const uint8_t channel, + const uint8_t *const pattern, + const XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t sign_output, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) +{ + XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; + + XMC_ASSERT("XMC_DAC_CH_StartPatternMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_StartPatternMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_StartPatternMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE); + + if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL) + { + status = XMC_DAC_CH_SetFrequency(dac, channel, frequency * XMC_DAC_SAMPLES_PER_PERIOD); + } + + if (status == XMC_DAC_CH_STATUS_OK) + { + XMC_DAC_CH_SetPattern(dac, channel, pattern); + if (XMC_DAC_CH_PATTERN_SIGN_OUTPUT_ENABLED == sign_output) + { + XMC_DAC_CH_EnablePatternSignOutput(dac, channel); + } + else + { + XMC_DAC_CH_DisablePatternSignOutput(dac, channel); + } + XMC_DAC_CH_SetTrigger(dac, channel, trigger); + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_PATTERN); + } + + return status; +} + +/* API to start the operation in Noise Mode. */ +XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartNoiseMode(XMC_DAC_t *const dac, + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) +{ + XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; + + XMC_ASSERT("XMC_DAC_CH_StartNoiseMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_StartNoiseMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_StartNoiseMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE); + + if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL) + { + status = XMC_DAC_CH_SetFrequency(dac, channel, frequency); + } + + if (status == XMC_DAC_CH_STATUS_OK) + { + XMC_DAC_CH_SetTrigger(dac, channel, trigger); + XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_NOISE); + } + + return status; +} + +/* API to write the pattern data table. */ +void XMC_DAC_CH_SetPattern(XMC_DAC_t *const dac, uint8_t channel, const uint8_t *const data) +{ + uint32_t index; + uint32_t temp; + + XMC_ASSERT("XMC_DAC_CH_SetPattern: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); + XMC_ASSERT("XMC_DAC_CH_SetPattern: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); + XMC_ASSERT("XMC_DAC_CH_SetPattern: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); + + temp = data[0U]; + for(index = 1U; index < 6U; ++index) + { + temp |= (uint32_t)data[index] << (index * XMC_DAC_DAC0PATL_PAT_BITSIZE); + } + dac->DACPAT[channel].low = temp; + + temp = data[6U]; + for(index = 1U; index < 6U; ++index) + { + temp |= (uint32_t)data[index + 6U] << (index * XMC_DAC_DAC0PATL_PAT_BITSIZE); + } + dac->DACPAT[channel].high = temp; +} + +#endif /* defined(DAC) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_dma.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_dma.c new file mode 100644 index 00000000..06f2fb96 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_dma.c @@ -0,0 +1,798 @@ + +/** + * @file xmc_dma.c + * @date 2016-04-08 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - Add the declarations for the following APIs:
+ * XMC_DMA_DisableRequestLine, XMC_DMA_ClearRequestLine,
+ * XMC_DMA_CH_ClearSourcePeripheralRequest,
+ * XMC_DMA_CH_ClearDestinationPeripheralRequest
+ * - Remove PRIOARRAY
+ * - Documentation updates
+ * + * 2015-06-20: + * - Removed GetDriverVersion API
+ * - Updated XMC_DMA_CH_Init() to support scatter/gather functionality (only + * on advanced DMA channels)
+ * - Updated XMC_DMA_CH_Disable()
+ * + * 2016-03-09: + * - Optimize write only registers + * + * 2016-04-08: + * - Update XMC_DMA_CH_EnableEvent and XMC_DMA_CH_DisableEvent. + * Write optimization of MASKCHEV + * - Fix XMC_DMA_IRQHandler, clear channel event status before processing the event handler. + * It corrects event losses if the DMA triggered in the event handler finished before returning from handler. + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_dma.h" + +#if defined (GPDMA0) + +#include "xmc_scu.h" + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define DLR_SRSEL_RS_MSK (0xfUL) +#define DLR_SRSEL_RS_BITSIZE (4UL) +#define DMA_EVENT_MAX (5UL) +#define GPDMA_CH_CFGH_DEST_PER_Pos GPDMA0_CH_CFGH_DEST_PER_Pos +#define GPDMA_CH_CFGH_SRC_PER_Pos GPDMA0_CH_CFGH_SRC_PER_Pos +#define GPDMA0_CH_CFGH_PER_Msk (0x7U) +#define GPDMA1_CH_CFGH_PER_Msk (0x3U) +#define GPDMA_CH_CFGH_PER_BITSIZE (4U) +#define GPDMA_CH_CTLL_INT_EN_Msk GPDMA0_CH_CTLL_INT_EN_Msk + +/******************************************************************************* + * LOCAL DATA + *******************************************************************************/ + +#if defined (GPDMA0) +XMC_DMA_CH_EVENT_HANDLER_t dma0_event_handlers[XMC_DMA0_NUM_CHANNELS]; +#endif + +#if defined (GPDMA1) +XMC_DMA_CH_EVENT_HANDLER_t dma1_event_handlers[XMC_DMA1_NUM_CHANNELS]; +#endif + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +/* Initialize GPDMA */ +void XMC_DMA_Init(XMC_DMA_t *const dma) +{ + XMC_DMA_Enable(dma); +} + +/* Enable GPDMA module */ +void XMC_DMA_Enable(XMC_DMA_t *const dma) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA0); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA0); +#if defined(GPDMA1) + } + else + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA1); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA1); + } +#endif + + dma->DMACFGREG = 0x1U; +} + +/* Disable GPDMA module */ +void XMC_DMA_Disable(XMC_DMA_t *const dma) +{ + dma->DMACFGREG = 0x0U; + +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA0); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA0); +#endif +#if defined(GPDMA1) + } + else + { + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA1); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA1); +#endif + } +#endif +} + +/* Check is the GPDMA peripheral is enabled */ +bool XMC_DMA_IsEnabled(const XMC_DMA_t *const dma) +{ + bool status; + +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + status = !XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_GPDMA0); +#if defined(CLOCK_GATING_SUPPORTED) + status = status && !XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_GPDMA0); +#endif +#if defined(GPDMA1) + } + else + { + status = !XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_GPDMA1); +#if defined(CLOCK_GATING_SUPPORTED) + status = status && !XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_GPDMA1); +#endif + } +#endif + + /* DMA reset is not asserted and peripheral clock is not gated */ + if (status == true) + { + status = status && (dma->DMACFGREG != 0U); + } + + return status; +} + +/* Enable request line */ +void XMC_DMA_EnableRequestLine(XMC_DMA_t *const dma, uint8_t line, uint8_t peripheral) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + DLR->SRSEL0 = ((DLR->SRSEL0 & (uint32_t)~(DLR_SRSEL_RS_MSK << (line * DLR_SRSEL_RS_BITSIZE))) | + ((uint32_t)peripheral << (line * DLR_SRSEL_RS_BITSIZE))); + DLR->LNEN |= (0x1UL << (line & GPDMA0_CH_CFGH_PER_Msk)); +#if defined(GPDMA1) + } + else + { + DLR->SRSEL1 = ((DLR->SRSEL1 & (uint32_t)~(DLR_SRSEL_RS_MSK << (line * DLR_SRSEL_RS_BITSIZE))) | + ((uint32_t)peripheral << (line * DLR_SRSEL_RS_BITSIZE))); + DLR->LNEN |= (0x100UL << line); + } +#endif +} + +void XMC_DMA_DisableRequestLine(XMC_DMA_t *const dma, uint8_t line) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + DLR->LNEN &= ~(0x1UL << line); +#if defined(GPDMA1) + } + else + { + DLR->LNEN &= ~(0x100UL << line); + } +#endif +} + +void XMC_DMA_ClearRequestLine(XMC_DMA_t *const dma, uint8_t line) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + DLR->LNEN &= ~(0x1UL << line); + DLR->LNEN |= 0x1UL << line; +#if defined(GPDMA1) + } + else + { + DLR->LNEN &= ~(0x100UL << line); + DLR->LNEN |= 0x100UL << line; + } +#endif +} + +/* Get DMA DLR overrun status */ +bool XMC_DMA_GetOverrunStatus(XMC_DMA_t *const dma, uint8_t line) +{ + bool status; + +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + status = (bool)(DLR->OVRSTAT & (0x1UL << line)); +#if defined(GPDMA1) + } + else + { + status = (bool)(DLR->OVRSTAT & (0x100UL << line)); + } +#endif + + return status; +} + +/* Clear DMA DLR overrun status */ +void XMC_DMA_ClearOverrunStatus(XMC_DMA_t *const dma, const uint8_t line) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + DLR->OVRCLR = (uint32_t)(0x1UL << line); +#if defined(GPDMA1) + } + else + { + DLR->OVRCLR = (uint32_t)(0x100UL << line); + } +#endif +} + +/* Disable DMA channel */ +void XMC_DMA_CH_Disable(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CHENREG = (uint32_t)(0x100UL << channel); + while((dma->CHENREG & (uint32_t)(0x1UL << channel)) != 0U) + { + /* wait until channel is disabled */ + } +} + +/* Check if a DMA channel is enabled */ +bool XMC_DMA_CH_IsEnabled(XMC_DMA_t *const dma, const uint8_t channel) +{ + return (bool)(dma->CHENREG & ((uint32_t)1U << channel)); +} + +/* Initialize DMA channel */ +XMC_DMA_CH_STATUS_t XMC_DMA_CH_Init(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_CONFIG_t *const config) +{ + XMC_DMA_CH_STATUS_t status; + uint8_t line; + uint8_t peripheral; + + if (XMC_DMA_IsEnabled(dma) == true) + { + if (XMC_DMA_CH_IsEnabled(dma, channel) == false) + { + dma->CH[channel].SAR = config->src_addr; + dma->CH[channel].DAR = config->dst_addr; + dma->CH[channel].LLP = (uint32_t)config->linked_list_pointer; + dma->CH[channel].CTLH = (uint32_t)config->block_size; + dma->CH[channel].CTLL = config->control; + + dma->CH[channel].CFGL = (uint32_t)((uint32_t)config->priority | + (uint32_t)GPDMA0_CH_CFGL_HS_SEL_SRC_Msk | + (uint32_t)GPDMA0_CH_CFGL_HS_SEL_DST_Msk); + + if ((dma == XMC_DMA0) && (channel < (uint8_t)2)) + { + /* Configure scatter and gather */ + dma->CH[channel].SGR = config->src_gather_control; + dma->CH[channel].DSR = config->dst_scatter_control; + } + + if (config->dst_handshaking == XMC_DMA_CH_DST_HANDSHAKING_HARDWARE) + { + /* Hardware handshaking interface configuration */ + if ((config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA) || + (config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA)) + { +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + line = config->dst_peripheral_request & GPDMA0_CH_CFGH_PER_Msk; +#if defined(GPDMA1) + } + else + { + line = config->dst_peripheral_request & GPDMA1_CH_CFGH_PER_Msk; + } +#endif + peripheral = config->dst_peripheral_request >> GPDMA_CH_CFGH_PER_BITSIZE; + + dma->CH[channel].CFGH |= (uint32_t)((uint32_t)line << GPDMA0_CH_CFGH_DEST_PER_Pos); + XMC_DMA_EnableRequestLine(dma, line, peripheral); + dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_HS_SEL_DST_Msk; + } + } + + + if (config->src_handshaking == XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE) + { + if ((config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA) || + (config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA)) + { +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + line = config->src_peripheral_request & GPDMA0_CH_CFGH_PER_Msk; +#if defined(GPDMA1) + } + else + { + line = config->src_peripheral_request & GPDMA1_CH_CFGH_PER_Msk; + } +#endif + peripheral = config->src_peripheral_request >> GPDMA_CH_CFGH_PER_BITSIZE; + + dma->CH[channel].CFGH |= (uint32_t)((uint32_t)line << GPDMA0_CH_CFGH_SRC_PER_Pos); + XMC_DMA_EnableRequestLine(dma, line, peripheral); + dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_HS_SEL_SRC_Msk; + } + } + + XMC_DMA_CH_ClearEventStatus(dma, channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_ERROR)); + + switch (config->transfer_type) + { + case XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK: + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_RELOAD: + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_CONTIGUOUS: + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD: + dma->CH[channel].CFGL |= (uint32_t)((uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk | + (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk); + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_LINKED: + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED: + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk; + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_CONTIGUOUS: + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_RELOAD: + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk; + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk; + break; + + case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED: + dma->CH[channel].CTLL |= (uint32_t)((uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk | + (uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk); + break; + + default: + break; + } + + status = XMC_DMA_CH_STATUS_OK; + + } + else + { + status = XMC_DMA_CH_STATUS_BUSY; + } + } + else + { + status = XMC_DMA_CH_STATUS_ERROR; + } + + return status; +} + +/* Suspend DMA channel transfer */ +void XMC_DMA_CH_Suspend(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_CH_SUSP_Msk; +} + +/* Resume DMA channel transfer */ +void XMC_DMA_CH_Resume(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_CH_SUSP_Msk; +} + +/* Check if a DMA channel is suspended */ +bool XMC_DMA_CH_IsSuspended(XMC_DMA_t *const dma, const uint8_t channel) +{ + return (bool)(dma->CH[channel].CFGL & (uint32_t)GPDMA0_CH_CFGL_CH_SUSP_Msk); +} + +/* Enable GPDMA event */ +void XMC_DMA_CH_EnableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event) +{ + uint32_t event_idx; + + for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + { + if (event & ((uint32_t)0x1UL << event_idx)) + { + dma->MASKCHEV[event_idx * 2UL] = ((uint32_t)0x101UL << channel); + } + } +} + +/* Disable GPDMA event */ +void XMC_DMA_CH_DisableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event) +{ + uint32_t event_idx; + + for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + { + if (event & ((uint32_t)0x1UL << event_idx)) + { + dma->MASKCHEV[event_idx * 2UL] = ((uint32_t)0x100UL << channel); + } + } +} + +/* Clear GPDMA event */ +void XMC_DMA_CH_ClearEventStatus(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event) +{ + uint32_t event_idx; + + for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + { + if (event & (uint32_t)((uint32_t)0x1UL << event_idx)) + { + dma->CLEARCHEV[event_idx * 2UL] = ((uint32_t)0x1UL << channel); + } + } + +} + +/* Get GPDMA event status */ +uint32_t XMC_DMA_CH_GetEventStatus(XMC_DMA_t *const dma, const uint8_t channel) +{ + uint32_t event_idx; + uint32_t status = 0UL; + + for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + { + status |= (uint32_t)((dma->STATUSCHEV[event_idx * 2UL] & (uint32_t)((uint32_t)0x1UL << (uint32_t)channel)) ? + ((uint32_t)0x1UL << event_idx) : (uint32_t)0UL); + } + + return status; +} + +/* Enable source gather */ +void XMC_DMA_CH_EnableSourceGather(XMC_DMA_t *const dma, const uint8_t channel, uint32_t interval, uint16_t count) +{ + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk; + dma->CH[channel].SGR = ((uint32_t)interval << GPDMA0_CH_SGR_SGI_Pos) | ((uint32_t)count << GPDMA0_CH_SGR_SGC_Pos); +} + +/* Disable source gather */ +void XMC_DMA_CH_DisableSourceGather(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CTLL &= (uint32_t)~GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk; +} + +/* Enable destination scatter */ +void XMC_DMA_CH_EnableDestinationScatter(XMC_DMA_t *const dma, const uint8_t channel, uint32_t interval, uint16_t count) +{ + dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk; + dma->CH[channel].DSR = ((uint32_t)interval << GPDMA0_CH_DSR_DSI_Pos) | ((uint32_t)count << GPDMA0_CH_DSR_DSC_Pos); +} + +/* Disable destination scatter */ +void XMC_DMA_CH_DisableDestinationScatter(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CTLL &= (uint32_t)~GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk; +} + +/* Trigger source request */ +void XMC_DMA_CH_TriggerSourceRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last) +{ + if ((uint32_t)type == (uint32_t)XMC_DMA_CH_TRANSACTION_TYPE_SINGLE) + { + dma->SGLREQSRCREG = ((uint32_t)0x101UL << channel); + } + + if (last == true) + { + dma->LSTSRCREG = (uint32_t)0x101UL << channel; + } + + dma->REQSRCREG = (uint32_t)0x101UL << channel; +} + +/* Trigger destination request */ +void XMC_DMA_CH_TriggerDestinationRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last) +{ + if(type == XMC_DMA_CH_TRANSACTION_TYPE_SINGLE) + { + dma->SGLREQDSTREG = (uint32_t)0x101UL << channel; + } + + if (last == true) + { + dma->LSTDSTREG = (uint32_t)0x101UL << channel; + } + + dma->REQDSTREG = (uint32_t)0x101UL << channel; +} + +/* Enable source address reload */ +void XMC_DMA_CH_EnableSourceAddressReload(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk; +} + +/* Disable source address reload */ +void XMC_DMA_CH_DisableSourceAddressReload(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_RELOAD_SRC_Msk; +} + +/* Enable destination address reload */ +void XMC_DMA_CH_EnableDestinationAddressReload(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk; +} + +/* Disable destination address reload */ +void XMC_DMA_CH_DisableDestinationAddressReload(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_RELOAD_DST_Msk; +} + +/* Request last multi-block transfer */ +void XMC_DMA_CH_RequestLastMultiblockTransfer(XMC_DMA_t *const dma, const uint8_t channel) +{ + dma->CH[channel].CFGL &= (uint32_t)~(GPDMA0_CH_CFGL_RELOAD_SRC_Msk | GPDMA0_CH_CFGL_RELOAD_DST_Msk); +} + +/* Set event handler */ +void XMC_DMA_CH_SetEventHandler(XMC_DMA_t *const dma, const uint8_t channel, XMC_DMA_CH_EVENT_HANDLER_t event_handler) +{ +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + dma0_event_handlers[channel] = event_handler; +#if defined(GPDMA1) + } + else + { + dma1_event_handlers[channel] = event_handler; + } +#endif +} + +void XMC_DMA_CH_ClearSourcePeripheralRequest(XMC_DMA_t *const dma, uint8_t channel) +{ + uint32_t line; + line = (dma->CH[channel].CFGH & GPDMA0_CH_CFGH_SRC_PER_Msk) >> GPDMA0_CH_CFGH_SRC_PER_Pos; + + XMC_DMA_ClearRequestLine(dma, (uint8_t)line); +} + +void XMC_DMA_CH_ClearDestinationPeripheralRequest(XMC_DMA_t *const dma, uint8_t channel) +{ + uint32_t line; + line = (dma->CH[channel].CFGH & GPDMA0_CH_CFGH_DEST_PER_Msk) >> GPDMA0_CH_CFGH_DEST_PER_Pos; + + XMC_DMA_ClearRequestLine(dma, (uint8_t)line); +} + +/* Default DMA IRQ handler */ +void XMC_DMA_IRQHandler(XMC_DMA_t *const dma) +{ + uint32_t event; + int32_t channel; + uint32_t mask; + XMC_DMA_CH_EVENT_HANDLER_t *dma_event_handlers; + XMC_DMA_CH_EVENT_HANDLER_t event_handler; + +#if defined(GPDMA1) + if (dma == XMC_DMA0) + { +#endif + dma_event_handlers = dma0_event_handlers; +#if defined(GPDMA1) + } + else + { + dma_event_handlers = dma1_event_handlers; + } +#endif + + event = XMC_DMA_GetEventStatus(dma); + channel = 0; + + if ((event & (uint32_t)XMC_DMA_CH_EVENT_ERROR) != (uint32_t)0UL) + { + event = XMC_DMA_GetChannelsErrorStatus(dma); + while (event != 0) + { + mask = (uint32_t)1U << channel; + if ((event & mask) != 0) + { + XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_ERROR); + + /* Call user callback to handle event */ + event_handler = dma_event_handlers[channel]; + if (event_handler != NULL) + { + event_handler(XMC_DMA_CH_EVENT_ERROR); + } + + break; + } + ++channel; + } + } + else if ((event & (uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE) != (uint32_t)0UL) + { + event = XMC_DMA_GetChannelsTransferCompleteStatus(dma); + while (event != 0) + { + mask = (uint32_t)1U << channel; + if (event & mask) + { + XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE)); + + /* Call user callback to handle event */ + event_handler = dma_event_handlers[channel]; + if (event_handler != NULL) + { + event_handler(XMC_DMA_CH_EVENT_TRANSFER_COMPLETE); + } + + break; + } + ++channel; + } + } + else if ((event & (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE) != (uint32_t)0UL) + { + event = XMC_DMA_GetChannelsBlockCompleteStatus(dma); + while (event != 0) + { + mask = (uint32_t)1U << channel; + if (event & mask) + { + XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE)); + + /* Call user callback to handle event */ + event_handler = dma_event_handlers[channel]; + if (event_handler != NULL) + { + event_handler(XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE); + } + + break; + } + ++channel; + } + } + else if ((event & (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE) != (uint32_t)0UL) + { + event = XMC_DMA_GetChannelsSourceTransactionCompleteStatus(dma); + while (event != 0) + { + mask = (uint32_t)1U << channel; + if (event & mask) + { + XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE); + + /* Call user callback to handle event */ + event_handler = dma_event_handlers[channel]; + if (event_handler != NULL) + { + event_handler(XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE); + } + + break; + } + ++channel; + } + } + else if ((event & (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE) != (uint32_t)0UL) + { + event = XMC_DMA_GetChannelsDestinationTransactionCompleteStatus(dma); + while (event != 0) + { + mask = (uint32_t)1U << channel; + if (event & mask) + { + XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE); + + /* Call user callback to handle event */ + event_handler = dma_event_handlers[channel]; + if (event_handler != NULL) + { + event_handler(XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE); + } + + break; + } + ++channel; + } + } + else + { + /* no active interrupt was found? */ + } + +} + +#endif /* GPDMA0 */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_dsd.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_dsd.c new file mode 100644 index 00000000..2c45a23f --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_dsd.c @@ -0,0 +1,369 @@ +/** + * @file xmc_dsd.c + * @date 2015-09-18 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-03-30: + * - Initial version + * + * 2015-06-19: + * - Removed GetDriverVersion API
+ * + * 2015-09-18: + * - Support added for XMC4800 microcontroller family
+ * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_dsd.h" + +#if defined(DSD) + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#define XMC_DSD_MIN_FILTER_START (4U) +#define XMC_DSD_MIN_DECIMATION_FACTOR (4U) +#define XMC_DSD_MAX_DECIMATION_FACTOR (256U) +#define XMC_DSD_MAX_DECIMATION_FACTOR_AUX (32U) + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/*Enable the DSD Module*/ +void XMC_DSD_Enable(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_Enable:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_UNUSED_ARG(dsd); + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DSD); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DSD); +} + +/*Disable the DSD Module*/ +void XMC_DSD_Disable(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_Disable:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_UNUSED_ARG(dsd); + + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DSD); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DSD); +#endif +} + +/* Enable the module clock*/ +void XMC_DSD_EnableClock(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_EnableClock:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + /* Enable the module clock */ + dsd->CLC &= ~(uint32_t)DSD_CLC_DISR_Msk; + /* enable internal module clock */ + dsd ->GLOBCFG |= (uint32_t)0x01; +} + +void XMC_DSD_DisableClock(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_DisableClock:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + + /* disable internal module clock */ + dsd->GLOBCFG &= ~(uint32_t)DSD_GLOBCFG_MCSEL_Msk; + + /* stop the module clock */ + dsd->CLC |= (uint32_t)DSD_CLC_DISR_Msk; + +} + +/* Enable the DSD module and clock */ +void XMC_DSD_Init(XMC_DSD_t *const dsd) +{ + XMC_ASSERT("XMC_DSD_Init:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_DSD_Enable(dsd); + XMC_DSD_EnableClock(dsd); +} + +bool XMC_DSD_IsEnabled(XMC_DSD_t *const dsd) +{ + bool status; + XMC_ASSERT("XMC_DSD_Disable:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_UNUSED_ARG(dsd); + + #if ((UC_SERIES == XMC44) || (UC_SERIES == XMC48)||(UC_SERIES == XMC47)) + if(XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DSD) == false) + { + if(XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_DSD) == false) + { + status = true; + } + else + { + status = false; + } + } + else + { + status = false; + } + #else + if(XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DSD) == false) + { + status = true; + } + else + { + status = false; + } + #endif + + return (status); +} + +/*Initializes the Waveform Generator*/ +void XMC_DSD_Generator_Init(XMC_DSD_t *const dsd, const XMC_DSD_GENERATOR_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_DSD_GENERATOR_Init:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); + XMC_ASSERT("XMC_DSD_GENERATOR_Init:NULL Pointer", (config != (XMC_DSD_GENERATOR_CONFIG_t *)NULL) ); + /* Reset Generator */ + dsd ->CGCFG &= ~((uint32_t)DSD_CGCFG_CGMOD_Msk | (uint32_t)DSD_CGCFG_BREV_Msk | (uint32_t)DSD_CGCFG_SIGPOL_Msk | (uint32_t)DSD_CGCFG_DIVCG_Msk); + + /* Generator configuration */ + dsd ->CGCFG = config->generator_conf; +} + +/* Initialize main filter,auxiliary filter,integrator, rectifier and timestamp of DSD*/ +XMC_DSD_STATUS_t XMC_DSD_CH_Init( XMC_DSD_CH_t *const channel, const XMC_DSD_CH_CONFIG_t *const config) +{ + XMC_DSD_STATUS_t status; + + XMC_ASSERT("XMC_DSD_CH_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_CH_Init:NULL Pointer", (config != (XMC_DSD_CH_CONFIG_t *)NULL) ); + + if (config->filter != (XMC_DSD_CH_FILTER_CONFIG_t*)NULL) + { + XMC_DSD_CH_MainFilter_Init(channel, config->filter); + + if (config->aux != (XMC_DSD_CH_AUX_FILTER_CONFIG_t*)NULL) + { + XMC_DSD_CH_AuxFilter_Init(channel, config->aux); + } + if (config->integrator != (XMC_DSD_CH_INTEGRATOR_CONFIG_t*)NULL) + { + XMC_DSD_CH_Integrator_Init(channel, config->integrator); + } + if (config->rectify != (XMC_DSD_CH_RECTIFY_CONFIG_t*)NULL) + { + XMC_DSD_CH_Rectify_Init(channel, config->rectify); + } + if (config->timestamp != (XMC_DSD_CH_TIMESTAMP_CONFIG_t*)NULL) + { + XMC_DSD_CH_Timestamp_Init(channel, config->timestamp); + } + status = XMC_DSD_STATUS_OK; + } + else + { + status = XMC_DSD_STATUS_ERROR; + } + return (status); + +} + +/* Initialize main filter of DSD */ +void XMC_DSD_CH_MainFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_FILTER_CONFIG_t *const config) +{ + uint32_t decimation_factor_temp; + uint32_t filter_start_value_temp; + + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:NULL Pointer", (config != (XMC_DSD_CH_FILTER_CONFIG_t *)NULL) ); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Filter Start Value", (config->filter_start_value >= XMC_DSD_MIN_FILTER_START)); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Filter Start Value", (config->filter_start_value <= config->decimation_factor)); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Decimation Factor", + ((config->decimation_factor >= XMC_DSD_MIN_DECIMATION_FACTOR) && (config->decimation_factor <= XMC_DSD_MAX_DECIMATION_FACTOR))); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid divider",(((uint32_t)config->clock_divider <= XMC_DSD_CH_CLK_DIV_32))); + + /*Set Channel frequency*/ + channel->MODCFG = ((uint32_t)config->clock_divider << DSD_CH_MODCFG_DIVM_Pos) | (uint32_t)DSD_CH_MODCFG_DWC_Msk; + + /* Input Data/Clk */ + channel->DICFG = config->demodulator_conf | (uint32_t)DSD_CH_DICFG_DSWC_Msk | (uint32_t)DSD_CH_DICFG_SCWC_Msk; + + /*The decimation factor of the Main CIC filter is CFMDF + 1.*/ + decimation_factor_temp = config->decimation_factor-1U; + filter_start_value_temp = config->filter_start_value-1U; + + /* Filter setup*/ + channel->FCFGC = (decimation_factor_temp | + (filter_start_value_temp << (uint32_t)DSD_CH_FCFGC_CFMSV_Pos)| + config->main_filter_conf| + (uint32_t)DSD_CH_FCFGC_CFEN_Msk); + + /* Offset */ + channel->OFFM = (uint16_t)config->offset; +} + +/* Initialize timestamp mode of DSD */ +void XMC_DSD_CH_Timestamp_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_TIMESTAMP_CONFIG_t *const config) +{ + uint32_t temp; + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:NULL Pointer", (config != (XMC_DSD_CH_TIMESTAMP_CONFIG_t *)NULL) ); + + temp = (channel->DICFG | (uint32_t)DSD_CH_DICFG_TRWC_Msk); + temp &= ~((uint32_t)DSD_CH_DICFG_TSTRMODE_Msk|(uint32_t)DSD_CH_DICFG_TRSEL_Msk); + temp |= config->timestamp_conf; + channel->DICFG = temp; +} + +/* Initialize auxiliary filter of DSD */ +void XMC_DSD_CH_AuxFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_AUX_FILTER_CONFIG_t *const config) +{ + uint32_t decimation_factor_temp; + + XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:NULL Pointer", (config != (XMC_DSD_CH_AUX_FILTER_CONFIG_t *)NULL) ); + XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:Invalid Decimation Factor", + ((config->decimation_factor >= XMC_DSD_MIN_DECIMATION_FACTOR) && (config->decimation_factor <= XMC_DSD_MAX_DECIMATION_FACTOR_AUX))); + + channel->BOUNDSEL = config->boundary_conf; + /*The decimation factor of the Aux CIC filter is CFMDF + 1.*/ + decimation_factor_temp = config->decimation_factor-1U; + channel->FCFGA = (decimation_factor_temp | config->aux_filter_conf); +} + +/* Integrator initialization of DSD */ +void XMC_DSD_CH_Integrator_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_INTEGRATOR_CONFIG_t *const config) +{ + uint32_t temp; + XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:NULL Pointer", (config != (XMC_DSD_CH_INTEGRATOR_CONFIG_t *)NULL) ); + XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:Invalid integration_loop", (config->integration_loop > 0U )); + XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:Invalid counted_values", (config->counted_values > 0U )); + + channel->IWCTR = ((config->integration_loop - 1U) << DSD_CH_IWCTR_REPVAL_Pos) + | (config->discarded_values << DSD_CH_IWCTR_NVALDIS_Pos) + | (config->stop_condition << DSD_CH_IWCTR_IWS_Pos) + | ((config->counted_values - 1U) << DSD_CH_IWCTR_NVALINT_Pos); + + /*To ensure proper operation, ensure that bit field ITRMODE is zero before selecting any other trigger mode.*/ + temp = (channel->DICFG & ~((uint32_t)DSD_CH_DICFG_ITRMODE_Msk|(uint32_t)DSD_CH_DICFG_TRSEL_Msk)) | (uint32_t)DSD_CH_DICFG_TRWC_Msk; + + channel->DICFG = temp; + + temp |= config->integrator_trigger; + channel->DICFG = temp; +} + +/* Rectifier initialization of DSD */ +void XMC_DSD_CH_Rectify_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_RECTIFY_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_DSD_RECTIFY_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); + XMC_ASSERT("XMC_DSD_RECTIFY_Init:NULL Pointer", (config != (XMC_DSD_CH_RECTIFY_CONFIG_t *)NULL)); + XMC_ASSERT("XMC_DSD_RECTIFY_Init:NULL Pointer", (((uint16_t)config->delay + (uint16_t)config->half_cycle) <= 0xFF)); + + channel->RECTCFG = config->rectify_config | (uint32_t)DSD_CH_RECTCFG_RFEN_Msk; + channel->CGSYNC = (((uint32_t) config->delay << (uint32_t)DSD_CH_CGSYNC_SDPOS_Pos) + | (((uint32_t)config->delay + (uint32_t)config->half_cycle) << (uint32_t)DSD_CH_CGSYNC_SDNEG_Pos)); +} + +/* API to get the result of the last conversion */ +void XMC_DSD_CH_GetResult_TS(XMC_DSD_CH_t* const channel, + int16_t* dsd_result, + uint8_t* dsd_filter_count, + uint8_t* dsd_integration_count) +{ + uint32_t timestamp; + uint16_t result; + + timestamp = channel->TSTMP; + result = (uint16_t)((uint32_t)timestamp & DSD_CH_TSTMP_RESULT_Msk); + *dsd_result = (int16_t)(result); + *dsd_filter_count = (uint8_t) ((timestamp & (uint32_t)DSD_CH_TSTMP_CFMDCNT_Msk)>>(uint32_t)DSD_CH_TSTMP_CFMDCNT_Pos); + *dsd_integration_count = (uint8_t) ((timestamp & (uint32_t)DSD_CH_TSTMP_NVALCNT_Msk)>>(uint32_t)DSD_CH_TSTMP_NVALCNT_Pos); +} + +/* API to get the result of the last conversion with the time */ +void XMC_DSD_CH_GetResult_TS_Time(XMC_DSD_CH_t* const channel, int16_t* dsd_Result, uint32_t* time) +{ + uint32_t timestamp; + uint16_t filter_count; + uint16_t integrator_count; + uint16_t decimation; + uint16_t result; + + timestamp = channel->TSTMP; + decimation = (uint16_t)(channel->FCFGC & DSD_CH_FCFGC_CFMDF_Msk); + filter_count = (uint16_t)((timestamp & DSD_CH_TSTMP_CFMDCNT_Msk)>>DSD_CH_TSTMP_CFMDCNT_Pos); + + /* Integration enabled? */ + if ((channel->IWCTR & DSD_CH_IWCTR_INTEN_Msk)) + { + integrator_count = (uint16_t) ((timestamp & DSD_CH_TSTMP_NVALCNT_Msk)>>DSD_CH_TSTMP_NVALCNT_Pos); + + /*See Errata number: xxyy */ + if (filter_count == decimation) + { + integrator_count++; + } + *time = (uint32_t)(((uint32_t) integrator_count * ((uint32_t) decimation + 1U)) + (uint32_t) ((uint32_t)decimation - filter_count)); + } + else + { + *time = (uint32_t) ((uint32_t)decimation - filter_count); + } + result = (uint16_t)((uint32_t)timestamp & DSD_CH_TSTMP_RESULT_Msk); + *dsd_Result = (int16_t)(result); +} + + + +#endif /*DSD*/ + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ebu.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ebu.c new file mode 100644 index 00000000..d04d7d81 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ebu.c @@ -0,0 +1,122 @@ +/** + * @file xmc_ebu.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed GetDriverVersion API + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ + +#include + +#if defined(EBU) + +/********************************************************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ + +/* + * Initialize the EBU peripheral + */ +XMC_EBU_STATUS_t XMC_EBU_Init(XMC_EBU_t *const ebu,const XMC_EBU_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + XMC_ASSERT("XMC_EBU_Init:Null Pointer", (config != (XMC_EBU_CONFIG_t *)NULL)); + + /* Enable EBU */ + XMC_EBU_Enable(ebu); + + /* Clock configuration */ + ebu->CLC = config->ebu_clk_config.raw0; + + /*EBU Mode Configuration */ + ebu->MODCON = config->ebu_mode_config.raw0; + + /* Address Bits available for GPIO function */ + ebu->USERCON = config->ebu_free_pins_to_gpio.raw0; + + return XMC_EBU_STATUS_OK; +} + +/* + * Configures the SDRAM with operating modes and refresh parameters + */ +void XMC_EBU_ConfigureSdram(XMC_EBU_t *const ebu,const XMC_EBU_SDRAM_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + XMC_ASSERT("XMC_EBU_Init:Null Pointer", (config != (XMC_EBU_SDRAM_CONFIG_t *)NULL)); + + /* EBU SDRAM Refresh Configuration Parameters */ + ebu->SDRMREF = config->raw2; + /* EBU SDRAM General Configuration Parameters */ + ebu->SDRMCON = config->raw0; + /* EBU SDRAM Operation Mode Configuration Parameters */ + ebu->SDRMOD = config->raw1; +} + +/* + * Configures the SDRAM region for read and write operation + */ +void XMC_EBU_ConfigureRegion(XMC_EBU_t *const ebu,const XMC_EBU_REGION_t *const region) +{ + + XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); + XMC_ASSERT("XMC_EBU_Init:Null Pointer", (region != (XMC_EBU_REGION_t *)NULL)); + + /* Read configuration of the region*/ + ebu->BUS[region->read_config.ebu_region_no].RDCON = region->read_config.ebu_bus_read_config.raw0; + + /* Read parameters of the region*/ + ebu->BUS[region->read_config.ebu_region_no].RDAPR = region->read_config.ebu_bus_read_config.raw1; + + /* Write configuration of the region*/ + ebu->BUS[region->write_config.ebu_region_no].WRCON = region->write_config.ebu_bus_write_config.raw0; + + /* Write parameters of the region*/ + ebu->BUS[region->write_config.ebu_region_no].WRAPR = region->write_config.ebu_bus_write_config.raw1; +} + + +#endif /* defined(EBU) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ecat.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ecat.c new file mode 100644 index 00000000..91ac2773 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ecat.c @@ -0,0 +1,198 @@ + +/** + * @file xmc_ecat.c + * @date 2015-10-21 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-12-27: + * - Add clock gating control in enable/disable APIs + * + * 2015-10-21: + * - Initial Version + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include + +#if defined (ECAT0) + +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ +/* The function defines the access state to the MII management for the PDI interface*/ +__STATIC_INLINE void XMC_ECAT_lRequestPhyAccessToMII(void) +{ + ECAT0->MII_PDI_ACS_STATE |= 0x01; +} + +/* EtherCAT module clock ungating and deassert reset API (Enables ECAT) */ +void XMC_ECAT_Enable(void) +{ + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0); + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0); + + while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == true){} +} + +/* EtherCAT module clock gating and assert reset API (Disables ECAT)*/ +void XMC_ECAT_Disable(void) +{ + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0); + while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == false){} + + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0); +} + +/* EtherCAT initialization function */ +void XMC_ECAT_Init(XMC_ECAT_CONFIG_t *const config) +{ + XMC_ECAT_Enable(); + + /* The process memory is not accessible until the ESC Configuration Area is loaded successfully. */ + + /* words 0x0-0x3 */ + ECAT0->EEP_DATA[0U] = config->dword[0U]; + ECAT0->EEP_DATA[1U] = config->dword[1U]; + ECAT0->EEP_CONT_STAT |= (uint16_t)((uint16_t)0x4U << (uint16_t)ECAT_EEP_CONT_STAT_CMD_REG_Pos); + + /* words 0x4-0x7 */ + ECAT0->EEP_DATA[0U] = config->dword[2U]; + ECAT0->EEP_DATA[1U] = config->dword[3U]; + ECAT0->EEP_CONT_STAT |= (uint16_t)((uint16_t)0x4U << (uint16_t)ECAT_EEP_CONT_STAT_CMD_REG_Pos); + + while (ECAT0->EEP_CONT_STAT & ECAT_EEP_CONT_STAT_L_STAT_Msk) + { + /* Wait until the EEPROM_Loaded signal is active */ + } + +} + +/* EtherCAT application event enable API */ +void XMC_ECAT_EnableEvent(uint32_t event) +{ + ECAT0->AL_EVENT_MASK |= event; +} +/* EtherCAT application event disable API */ +void XMC_ECAT_DisableEvent(uint32_t event) +{ + ECAT0->AL_EVENT_MASK &= ~event; +} + +/* EtherCAT application event status reading API */ +uint32_t XMC_ECAT_GetEventStatus(void) +{ + return (ECAT0->AL_EVENT_REQ); +} + +/* EtherCAT SyncManager channel disable function*/ +void XMC_ECAT_DisableSyncManChannel(const uint8_t channel) +{ + ((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR |= 0x1U; +} + +/* EtherCAT SyncManager channel enable function*/ +void XMC_ECAT_EnableSyncManChannel(const uint8_t channel) +{ + ((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR &= (uint8_t)(~0x1U); +} + + +/* EtherCAT PHY register read function*/ +XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) +{ + XMC_ECAT_STATUS_t status; + + XMC_ECAT_lRequestPhyAccessToMII(); + + ECAT0->MII_PHY_ADR = phy_addr; + ECAT0->MII_PHY_REG_ADR = reg_addr; + + ECAT0->MII_CONT_STAT |= 0x0100U; /* read instruction */ + while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){} + + if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U) + { + ECAT0->MII_CONT_STAT &= ~ECAT_MII_CONT_STAT_CMD_REG_Msk; /* Clear error */ + status = XMC_ECAT_STATUS_ERROR; + } + else + { + *data = (uint16_t)ECAT0->MII_PHY_DATA; + status = XMC_ECAT_STATUS_OK; + } + + return status; +} + +/* EtherCAT PHY register write function*/ +XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t data) +{ + XMC_ECAT_STATUS_t status; + + XMC_ECAT_lRequestPhyAccessToMII(); + + ECAT0->MII_PHY_ADR = phy_addr; + ECAT0->MII_PHY_REG_ADR = reg_addr; + ECAT0->MII_PHY_DATA = data; + + ECAT0->MII_CONT_STAT |= 0x0200U; /* write instruction */ + while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){} + + if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U) + { + ECAT0->MII_CONT_STAT &= ~ECAT_MII_CONT_STAT_CMD_REG_Msk; /* Clear error */ + status = XMC_ECAT_STATUS_ERROR; + } + else + { + status = XMC_ECAT_STATUS_OK; + } + + return status; +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eru.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eru.c new file mode 100644 index 00000000..9141b9b2 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eru.c @@ -0,0 +1,295 @@ +/** + * @file xmc_eru.c + * @date 2016-03-10 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API
+ * + * 2016-03-10: + * - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation.
+ * + * @endcond + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include "xmc_eru.h" + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ + +#define ERU_EXISEL_BITSIZE (4UL) /* Used to set the input for path A and path B based on the channel */ +#define ERU_EXISEL_INPUT_BITSIZE (2UL) + +#define XMC_ERU_ETL_CHECK_INPUT_A(input) \ + ((input == XMC_ERU_ETL_INPUT_A0) || \ + (input == XMC_ERU_ETL_INPUT_A1) || \ + (input == XMC_ERU_ETL_INPUT_A2) || \ + (input == XMC_ERU_ETL_INPUT_A3)) + +#define XMC_ERU_ETL_CHECK_INPUT_B(input) \ + ((input == XMC_ERU_ETL_INPUT_B0) || \ + (input == XMC_ERU_ETL_INPUT_B1) || \ + (input == XMC_ERU_ETL_INPUT_B2) || \ + (input == XMC_ERU_ETL_INPUT_B3)) + +#define XMC_ERU_ETL_CHECK_STATUS_FLAG_MODE(mode) \ + ((mode == XMC_ERU_ETL_STATUS_FLAG_MODE_SWCTRL) || \ + (mode == XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL)) + +#define XMC_ERU_ETL_CHECK_EVENT_SOURCE(source) \ + ((source == XMC_ERU_ETL_SOURCE_A) || \ + (source == XMC_ERU_ETL_SOURCE_B) || \ + (source == XMC_ERU_ETL_SOURCE_A_OR_B) || \ + (source == XMC_ERU_ETL_SOURCE_A_AND_B) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_A) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_A_OR_B) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_A_AND_B) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_B) || \ + (source == XMC_ERU_ETL_SOURCE_A_OR_NOT_B) || \ + (source == XMC_ERU_ETL_SOURCE_A_AND_NOT_B) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_A_OR_NOT_B) || \ + (source == XMC_ERU_ETL_SOURCE_NOT_A_AND_NOT_B)) + +#define XMC_ERU_ETL_CHECK_TRIGGER_EDGE(edge) \ + ((edge == XMC_ERU_ETL_EDGE_DETECTION_DISABLED) || \ + (edge == XMC_ERU_ETL_EDGE_DETECTION_RISING) || \ + (edge == XMC_ERU_ETL_EDGE_DETECTION_FALLING) || \ + (edge == XMC_ERU_ETL_EDGE_DETECTION_BOTH)) + +#define XMC_ERU_ETL_CHECK_TRIGGER_CHANNEL(channel) \ + ((channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0) || \ + (channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL1) || \ + (channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL2) || \ + (channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL3)) + +#define XMC_ERU_OGU_CHECK_PATTERN_INPUT(input) \ + ((input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT0) || \ + (input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT1) || \ + (input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT2) || \ + (input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT3)) + +#define XMC_ERU_OGU_CHECK_PERIPHERAL_TRIGGER(trigger) \ + ((trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER1) || \ + (trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER2) || \ + (trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER3)) + +#define XMC_ERU_OGU_CHECK_SERIVCE_REQUEST(service) \ + ((service == XMC_ERU_OGU_SERVICE_REQUEST_DISABLED) || \ + (service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER) || \ + (service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH) || \ + (service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH)) + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ +/* Initializes the selected ERU_ETLx channel with the config structure. */ +void XMC_ERU_ETL_Init(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_ERU_ETL_Init:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_Init:Invalid Channel Number", (channel < 4U)); + + XMC_ERU_Enable(eru); + + eru->EXISEL = (eru->EXISEL & + ~((uint32_t)(ERU_EXISEL_EXS0A_Msk | ERU_EXISEL_EXS0B_Msk) << (channel * ERU_EXISEL_BITSIZE))) | + (config->input << (channel * (uint32_t)ERU_EXISEL_BITSIZE)); + + eru->EXICON[channel] = config->raw; +} + +/* Initializes the selected ERU_OGUy channel with the config structure. */ +void XMC_ERU_OGU_Init(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_ERU_OGU_Init:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_Init:Invalid Channel Number", (channel < 4U)); + + XMC_ERU_Enable(eru); + + eru->EXOCON[channel] = config->raw; +} + +/* Configures the event source for path A and path B, with selected input_a and input_b respectively.*/ +void XMC_ERU_ETL_SetInput(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_INPUT_A_t input_a, + const XMC_ERU_ETL_INPUT_B_t input_b) +{ + XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid A", XMC_ERU_ETL_CHECK_INPUT_A(input_a)); + XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid B", XMC_ERU_ETL_CHECK_INPUT_B(input_b)); + + eru->EXISEL = (eru->EXISEL & ~((uint32_t)(ERU_EXISEL_EXS0A_Msk | ERU_EXISEL_EXS0B_Msk) << (channel * ERU_EXISEL_BITSIZE))) | + (((uint32_t)input_a | (uint32_t)(input_b << ERU_EXISEL_INPUT_BITSIZE)) << (channel * ERU_EXISEL_BITSIZE)); +} + +/* Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits of + EXICONx(x = [0 to 3]) register */ +void XMC_ERU_ETL_SetSource(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_SOURCE_t source) +{ + XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Source", XMC_ERU_ETL_CHECK_EVENT_SOURCE(source)); + + eru->EXICON_b[channel].SS = (uint8_t)source; +} + +/* Configure event trigger edge/s by setting (RE, FE) bits of EXICONx(x = [0 to 3]) register.*/ +void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_EDGE_DETECTION_t edge_detection) +{ + XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Trigger Edge", XMC_ERU_ETL_CHECK_TRIGGER_EDGE(edge_detection)); + + eru->EXICON_b[channel].ED = (uint8_t)edge_detection; +} + +/* Returns the configured event trigger edge/s by reading (RE, FE) bits of EXICONx(x = [0 to 3]) register. */ +XMC_ERU_ETL_EDGE_DETECTION_t XMC_ERU_ETL_GetEdgeDetection(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_ETL_GetEdgeDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_GetEdgeDetection:Invalid Channel Number", (channel < 4U)); + return ((XMC_ERU_ETL_EDGE_DETECTION_t)(eru->EXICON_b[channel].ED)); +} + +/* Set the status flag bit(FL) in EXICONx(x = [0 to 3]). */ +void XMC_ERU_ETL_SetStatusFlagMode(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_STATUS_FLAG_MODE_t mode) +{ + XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Status Flag Mode", XMC_ERU_ETL_CHECK_STATUS_FLAG_MODE(mode)); + + eru->EXICON_b[channel].LD = (uint8_t)mode; +} + +/* Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by + * ETLx(Event Trigger Logic, x = [0 to 3]) by setting (OCS and PE) bit fields. */ +void XMC_ERU_ETL_EnableOutputTrigger(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t trigger) +{ + XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Output Channel", XMC_ERU_ETL_CHECK_TRIGGER_CHANNEL(trigger)); + + eru->EXICON_b[channel].OCS = (uint8_t)trigger; + eru->EXICON_b[channel].PE = (uint8_t)true; +} + +/* Disables the trigger pulse generation by clearing the (PE) of the EXICONx(x = [0 to 3]). */ +void XMC_ERU_ETL_DisableOutputTrigger(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_ETL_DisableOutputTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_ETL_DisableOutputTrigger:Invalid Channel Number", (channel < 4U)); + + eru->EXICON_b[channel].PE = false; +} + +/* Configures ERU_ETLx(x = [0 to 3]) for pattern match detection by setting IPENx(x = [0 to 3) and GEEN bits. */ +void XMC_ERU_OGU_EnablePatternDetection(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t input) +{ + XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Pattern input", XMC_ERU_OGU_CHECK_PATTERN_INPUT(input)); + + eru->EXOCON_b[channel].IPEN = (uint8_t)input; + eru->EXOCON_b[channel].GEEN = true; +} + +/* Disable the pattern detection by clearing (GEEN) bit. */ +void XMC_ERU_OGU_DisablePatternDetection(XMC_ERU_t *const eru, const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_OGU_DisablePatternDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_DisablePatternDetection:Invalid Channel Number", (channel < 4U)); + + eru->EXOCON_b[channel].GEEN = false; +} + +/* Configures peripheral trigger input, by setting (ISS) bit. */ +void XMC_ERU_OGU_EnablePeripheralTrigger(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger) +{ + XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Peripheral Trigger Input", + XMC_ERU_OGU_CHECK_PERIPHERAL_TRIGGER(peripheral_trigger)); + + eru->EXOCON_b[channel].ISS = (uint8_t)peripheral_trigger; +} + +/* Disables event generation based on peripheral trigger by clearing (ISS) bit. */ +void XMC_ERU_OGU_DisablePeripheralTrigger(XMC_ERU_t *const eru, + const uint8_t channel) +{ + XMC_ASSERT("XMC_ERU_OGU_DisablePeripheralTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_DisablePeripheralTrigger:Invalid Channel Number", (channel < 4U)); + + eru->EXOCON_b[channel].ISS = (uint8_t)0; +} + +/* Configures the gating scheme for service request generation by setting (GP) bit. */ +void XMC_ERU_OGU_SetServiceRequestMode(XMC_ERU_t *const eru, + const uint8_t channel, + const XMC_ERU_OGU_SERVICE_REQUEST_t mode) +{ + XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); + XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Channel Number", (channel < 4U)); + XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Service Request Mode", XMC_ERU_OGU_CHECK_SERIVCE_REQUEST(mode)); + + eru->EXOCON_b[channel].GP = (uint8_t)mode; + +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_mac.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_mac.c new file mode 100644 index 00000000..f673cd55 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_mac.c @@ -0,0 +1,929 @@ + +/** + * @file xmc_eth_mac.c + * @date 2017-04-17 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * + * 2015-09-01: + * - Add clock gating control in enable/disable APIs + * - Add transmit polling if run out of buffers + * + * 2015-11-30: + * - Fix XMC_ETH_MAC_GetRxFrameSize return value in case of errors + * + * 2016-03-16: + * - Fix XMC_ETH_MAC_DisableEvent + * + * 2016-05-19: + * - Changed XMC_ETH_MAC_ReturnTxDescriptor and XMC_ETH_MAC_ReturnRxDescriptor + * + * 2016-08-30: + * - Changed XMC_ETH_MAC_Init() to disable MMC interrupt events + * + * 2016-11-22: + * - Changed XMC_ETH_MAC_Init() to optimize access to bus + * + * 2017-02-25: + * - XMC_ETH_MAC_Enable() and XMC_ETH_MAC_Disable(), fixed compilation warnings + * + * 2017-03-27: + * - Changed XMC_ETH_MAC_Init() to disable PMT and timestamp interrupt events + * + * 2017-04-02: + * - Added XMC_ETH_MAC_InitPTPEx() + * - Added XMC_ETH_MAC_SetPTPTime() + * - Added XMC_ETH_MAC_UpdateAddend() + * - Fixed XMC_ETH_MAC_InitPTP(), XMC_ETH_MAC_UpdatePTPTime(), XMC_ETH_MAC_SetPTPAlarm() + * - nanoseconds initializazion + * - added polling to wait for setup + * + * 2017-04-04: + * - Changed XMC_ETH_MAC_Init() to disable MMC IPC receive interrupt events + * + * 2017-04-11: + * - Fixed XMC_ETH_MAC_SetPTPAlarm() nanoseconds conversion + * + * 2017-04-17: + * - Changed XMC_ETH_MAC_GetTxTimeStamp() and XMC_ETH_MAC_GetRxTimeStamp() return the timestamp depending on status bit in descriptor + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#include + +#if defined (ETH0) + +#include +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/** + * ETH MAC clock speed + */ +#define XMC_ETH_MAC_CLK_SPEED_35MHZ (35000000U) /**< ETH MAC clock speed 35 MHZ */ +#define XMC_ETH_MAC_CLK_SPEED_60MHZ (60000000U) /**< ETH MAC clock speed 60 MHZ */ +#define XMC_ETH_MAC_CLK_SPEED_100MHZ (100000000U) /**< ETH MAC clock speed 100 MHZ */ +#define XMC_ETH_MAC_CLK_SPEED_150MHZ (150000000U) /**< ETH MAC clock speed 150 MHZ */ +#define XMC_ETH_MAC_CLK_SPEED_200MHZ (200000000U) /**< ETH MAC clock speed 200 MHZ */ +#define XMC_ETH_MAC_CLK_SPEED_250MHZ (250000000U) /**< ETH MAC clock speed 250 MHZ */ + +/** + * ETH MAC MDC divider + */ +#define XMC_ETH_MAC_MDC_DIVIDER_16 (2U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/16 */ +#define XMC_ETH_MAC_MDC_DIVIDER_26 (3U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/26 */ +#define XMC_ETH_MAC_MDC_DIVIDER_42 (0U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/42 */ +#define XMC_ETH_MAC_MDC_DIVIDER_62 (1U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/62 */ +#define XMC_ETH_MAC_MDC_DIVIDER_102 (4U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/102 */ +#define XMC_ETH_MAC_MDC_DIVIDER_124 (5U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/124 */ + + +/** + * RDES1 Descriptor RX Packet Control + */ +#define ETH_MAC_DMA_RDES1_RBS2 (0x1FFF0000U) /**< Receive buffer 2 size */ +#define ETH_MAC_DMA_RDES1_RER (0x00008000U) /**< Receive end of ring */ +#define ETH_MAC_DMA_RDES1_RCH (0x00004000U) /**< Second address chained */ +#define ETH_MAC_DMA_RDES1_RBS1 (0x00001FFFU) /**< Receive buffer 1 size */ + +/** + * Interrupt masking + */ +#define ETH_MAC_DISABLE_MMC_INTERRUPT_MSK (0x03ffffffU) /**< Bit mask to disable MMMC transmit and receive interrupts */ +#define ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK (0x3fff3fffU) /**< Bit mask to disable MMC IPC Receive Checksum Offload Interrupt Mask */ + +/** + * Normal MAC events + */ +#define ETH_MAC_EVENT_NORMAL (XMC_ETH_MAC_EVENT_TRANSMIT |\ + XMC_ETH_MAC_EVENT_TRANSMIT_BUFFER_UNAVAILABLE |\ + XMC_ETH_MAC_EVENT_RECEIVE |\ + XMC_ETH_MAC_EVENT_EARLY_RECEIVE) + +/** + * Abnormal MAC events + */ +#define ETH_MAC_EVENT_ABNORMAL (XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED |\ + XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT |\ + XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW |\ + XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW |\ + XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE |\ + XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED |\ + XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT |\ + XMC_ETH_MAC_EVENT_EARLY_TRANSMIT |\ + XMC_ETH_MAC_EVENT_BUS_ERROR) + +/* Definition needed in case of device header file previous to v1.5.1*/ +#ifndef ETH_BUS_MODE_ATDS_Msk +#define ETH_BUS_MODE_ATDS_Msk (0x00000080UL) +#endif +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +/* Check if the event passed is a normal event */ +__STATIC_INLINE bool XCM_ETH_MAC_IsNormalEvent(uint32_t event) +{ + return (bool)((event & ((uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT | + (uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_BUFFER_UNAVAILABLE | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE | + (uint32_t)XMC_ETH_MAC_EVENT_EARLY_RECEIVE)) != (uint32_t)0); +} + +/* Check if the event passed is an abnormal event */ +__STATIC_INLINE bool XCM_ETH_MAC_IsAbnormalEvent(uint32_t event) +{ + return (bool)((event & ((uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED | + (uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW | + (uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT | + (uint32_t)XMC_ETH_MAC_EVENT_EARLY_TRANSMIT | + (uint32_t)XMC_ETH_MAC_EVENT_BUS_ERROR)) != (uint32_t)0); + } + +#ifdef XMC_ASSERT_ENABLE + +/* Check if the passed argument is a valid ETH module */ +__STATIC_INLINE bool XMC_ETH_MAC_IsValidModule(ETH_GLOBAL_TypeDef *const eth) +{ + return (eth == ETH0); +} + +#endif + +/* ETH MAC initialize */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_Init(XMC_ETH_MAC_t *const eth_mac) +{ + XMC_ETH_MAC_STATUS_t status; + + XMC_ASSERT("XMC_ETH_MAC_Init: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + XMC_ETH_MAC_Enable(eth_mac); + XMC_ETH_MAC_Reset(eth_mac); + + status = XMC_ETH_MAC_SetManagmentClockDivider(eth_mac); + + XMC_ETH_MAC_SetAddress(eth_mac, eth_mac->address); + + /* Initialize MAC configuration */ + eth_mac->regs->MAC_CONFIGURATION = (uint32_t)ETH_MAC_CONFIGURATION_IPC_Msk; + + /* Initialize Filter registers */ + eth_mac->regs->FLOW_CONTROL = ETH_FLOW_CONTROL_DZPQ_Msk; /* Disable Zero Quanta Pause */ + + eth_mac->regs->OPERATION_MODE = (uint32_t)ETH_OPERATION_MODE_RSF_Msk | + (uint32_t)ETH_OPERATION_MODE_TSF_Msk | + (uint32_t)ETH_OPERATION_MODE_OSF_Msk; + + /* Increase enhanced descriptor to 8 WORDS, required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled */ + eth_mac->regs->BUS_MODE = (uint32_t)ETH_BUS_MODE_ATDS_Msk | + (uint32_t)ETH_BUS_MODE_AAL_Msk | /* the AHB interface generates all bursts aligned to the start address LS bits */ + (uint32_t)ETH_BUS_MODE_FB_Msk | /* DMA attempts to execute fixed-length Burst transfers on the AHB Master interface */ + (uint32_t)(0x20 << ETH_BUS_MODE_PBL_Pos); /* maximum Burst length */ + + /* Initialize DMA Descriptors */ + XMC_ETH_MAC_InitRxDescriptors(eth_mac); + XMC_ETH_MAC_InitTxDescriptors(eth_mac); + + /* Clear interrupts */ + eth_mac->regs->STATUS = 0xFFFFFFFFUL; + + /* Disable MMC interrupt events */ + eth_mac->regs->MMC_TRANSMIT_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_INTERRUPT_MSK; + eth_mac->regs->MMC_RECEIVE_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_INTERRUPT_MSK; + eth_mac->regs->MMC_IPC_RECEIVE_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK; + + /* Disable PMT and timestamp interrupt events */ + eth_mac->regs->INTERRUPT_MASK = ETH_INTERRUPT_MASK_PMTIM_Msk | ETH_INTERRUPT_MASK_TSIM_Msk; + + eth_mac->frame_end = NULL; + + return status; +} + +/* Initialize RX descriptors */ +void XMC_ETH_MAC_InitRxDescriptors(XMC_ETH_MAC_t *const eth_mac) +{ + uint32_t i; + uint32_t next; + + XMC_ASSERT("XMC_ETH_MAC_InitRxDescriptors: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + /* + * Chained structure (ETH_MAC_DMA_RDES1_RCH), second address in the descriptor + * (buffer2) is the next descriptor address + */ + for (i = 0U; i < eth_mac->num_rx_buf; ++i) + { + eth_mac->rx_desc[i].status = (uint32_t)ETH_MAC_DMA_RDES0_OWN; + eth_mac->rx_desc[i].length = (uint32_t)ETH_MAC_DMA_RDES1_RCH | (uint32_t)XMC_ETH_MAC_BUF_SIZE; + eth_mac->rx_desc[i].buffer1 = (uint32_t)&(eth_mac->rx_buf[i * XMC_ETH_MAC_BUF_SIZE]); + next = i + 1U; + if (next == eth_mac->num_rx_buf) + { + next = 0U; + } + eth_mac->rx_desc[i].buffer2 = (uint32_t)&(eth_mac->rx_desc[next]); + } + eth_mac->regs->RECEIVE_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&(eth_mac->rx_desc[0]); + eth_mac->rx_index = 0U; +} + +/* Initialize TX descriptors */ +void XMC_ETH_MAC_InitTxDescriptors(XMC_ETH_MAC_t *const eth_mac) +{ + uint32_t i; + uint32_t next; + + XMC_ASSERT("XMC_ETH_MAC_InitTxDescriptors: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + /* Chained structure (ETH_MAC_DMA_TDES0_TCH), second address in the descriptor (buffer2) is the next descriptor address */ + for (i = 0U; i < eth_mac->num_tx_buf; ++i) + { + eth_mac->tx_desc[i].status = ETH_MAC_DMA_TDES0_TCH | ETH_MAC_DMA_TDES0_LS | ETH_MAC_DMA_TDES0_FS; + eth_mac->tx_desc[i].buffer1 = (uint32_t)&(eth_mac->tx_buf[i * XMC_ETH_MAC_BUF_SIZE]); + next = i + 1U; + if (next == eth_mac->num_tx_buf) + { + next = 0U; + } + eth_mac->tx_desc[i].buffer2 = (uint32_t)&(eth_mac->tx_desc[next]); + } + eth_mac->regs->TRANSMIT_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&(eth_mac->tx_desc[0]); + eth_mac->tx_index = 0U; +} + +/* Set address perfect filter */ +void XMC_ETH_MAC_SetAddressPerfectFilter(XMC_ETH_MAC_t *const eth_mac, + uint8_t index, + const uint64_t addr, + uint32_t flags) +{ + __IO uint32_t *reg; + + XMC_ASSERT("XMC_ETH_MAC_SetAddressPerfectFilter: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_SetAddressFilter: index is out of range", ((index > 0) && (index < 4))); + + reg = &(eth_mac->regs->MAC_ADDRESS0_HIGH); + reg[index] = (uint32_t)(addr >> 32U) | flags; + reg[index + 1U] = (uint32_t)addr; +} + +/* Set address hash filter */ +void XMC_ETH_MAC_SetAddressHashFilter(XMC_ETH_MAC_t *const eth_mac, const uint64_t hash) +{ + eth_mac->regs->HASH_TABLE_HIGH = (uint32_t)(hash >> 32); + eth_mac->regs->HASH_TABLE_LOW = (uint32_t)hash; +} + +/* Send frame */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SendFrame(XMC_ETH_MAC_t *const eth_mac, const uint8_t *frame, uint32_t len, uint32_t flags) +{ + XMC_ETH_MAC_STATUS_t status; + uint8_t *dst; + uint32_t ctrl; + + XMC_ASSERT("XMC_ETH_MAC_SendFrame:", eth_mac != NULL); + XMC_ASSERT("XMC_ETH_MAC_SendFrame:", eth_mac->regs == ETH0); + XMC_ASSERT("XMC_ETH_MAC_SendFrame:", (frame != NULL) && (len > 0)); + + dst = eth_mac->frame_end; + + if (eth_mac->tx_desc[eth_mac->tx_index].status & ETH_MAC_DMA_TDES0_OWN) + { + /* Transmitter is busy, wait */ + status = XMC_ETH_MAC_STATUS_BUSY; + if (eth_mac->regs->STATUS & ETH_STATUS_TU_Msk) + { + /* Receive buffer unavailable, resume DMA */ + eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_TU_Msk; + eth_mac->regs->TRANSMIT_POLL_DEMAND = 0U; + } + + } + else + { + if (dst == NULL) + { + /* Start of a new transmit frame */ + dst = (uint8_t *)eth_mac->tx_desc[eth_mac->tx_index].buffer1; + eth_mac->tx_desc[eth_mac->tx_index].length = len; + } + else + { + /* Sending data fragments in progress */ + eth_mac->tx_desc[eth_mac->tx_index].length += len; + } + + memcpy(dst, frame, len); + + if (flags & (uint32_t)XMC_ETH_MAC_TX_FRAME_FRAGMENT) + { + /* More data to come, remember current write position */ + eth_mac->frame_end = dst; + } + else + { + /* Frame is now ready, send it to DMA */ + ctrl = eth_mac->tx_desc[eth_mac->tx_index].status | ETH_MAC_DMA_TDES0_CIC; + ctrl &= ~(ETH_MAC_DMA_TDES0_IC | ETH_MAC_DMA_TDES0_TTSE); + + if (flags & (uint32_t)XMC_ETH_MAC_TX_FRAME_EVENT) + { + ctrl |= ETH_MAC_DMA_TDES0_IC; + } + + if (flags & (uint32_t)XMC_ETH_MAC_TX_FRAME_TIMESTAMP) + { + ctrl |= ETH_MAC_DMA_TDES0_TTSE; + } + eth_mac->tx_ts_index = eth_mac->tx_index; + + eth_mac->tx_desc[eth_mac->tx_index].status = ctrl | ETH_MAC_DMA_TDES0_OWN; + + eth_mac->tx_index++; + if (eth_mac->tx_index == eth_mac->num_tx_buf) + { + eth_mac->tx_index = 0U; + } + eth_mac->frame_end = NULL; + + /* Start frame transmission */ + eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_TPS_Msk; + eth_mac->regs->TRANSMIT_POLL_DEMAND = 0U; + } + status = XMC_ETH_MAC_STATUS_OK; + } + + return status; +} + +/* Read frame */ +uint32_t XMC_ETH_MAC_ReadFrame(XMC_ETH_MAC_t *const eth_mac, uint8_t *frame, uint32_t len) +{ + uint8_t const *src; + + XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", eth_mac != NULL); + XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", eth_mac->regs == ETH0); + XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", (frame != NULL) && (len > 0)); + + /* Fast-copy data to packet buffer */ + src = (uint8_t const *)eth_mac->rx_desc[eth_mac->rx_index].buffer1; + + memcpy(frame, src, len); + + /* Return this block back to DMA */ + eth_mac->rx_desc[eth_mac->rx_index].status = ETH_MAC_DMA_RDES0_OWN; + + eth_mac->rx_index++; + if (eth_mac->rx_index == eth_mac->num_rx_buf) + { + eth_mac->rx_index = 0U; + } + + if (eth_mac->regs->STATUS & ETH_STATUS_RU_Msk) + { + /* Receive buffer unavailable, resume DMA */ + eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_RU_Msk; + eth_mac->regs->RECEIVE_POLL_DEMAND = 0U; + } + + return (len); +} + +/* Get RX frame size */ +uint32_t XMC_ETH_MAC_GetRxFrameSize(XMC_ETH_MAC_t *const eth_mac) +{ + uint32_t status; + uint32_t len = 0U; + + status = eth_mac->rx_desc[eth_mac->rx_index].status; + + if (status & ETH_MAC_DMA_RDES0_OWN) + { + /* Owned by DMA */ + len = 0U; + } + else if (((status & ETH_MAC_DMA_RDES0_ES) != 0U) || + ((status & ETH_MAC_DMA_RDES0_FS) == 0U) || + ((status & ETH_MAC_DMA_RDES0_LS) == 0U)) + { + /* Error, this block is invalid */ + len = 0xFFFFFFFFU; + } + else + { + /* Subtract CRC */ + len = ((status & ETH_MAC_DMA_RDES0_FL) >> 16U) - 4U; + } + + return len; +} + +/* Set management clock divider */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SetManagmentClockDivider(XMC_ETH_MAC_t *const eth_mac) +{ + uint32_t eth_mac_clk; + XMC_ETH_MAC_STATUS_t status; + __IO uint32_t *reg; + + eth_mac_clk = XMC_SCU_CLOCK_GetEthernetClockFrequency(); + status = XMC_ETH_MAC_STATUS_OK; + + reg = &(eth_mac->regs->GMII_ADDRESS); + if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_35MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_16; + } + else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_60MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_26; + } + else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_100MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_42; + } + else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_150MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_62; + } + else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_200MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_102; + } + else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_250MHZ) + { + *reg = XMC_ETH_MAC_MDC_DIVIDER_124; + } + else + { + status = XMC_ETH_MAC_STATUS_ERROR; + } + + return status; +} + +/* ETH MAC enable */ +void XMC_ETH_MAC_Enable(XMC_ETH_MAC_t *const eth_mac) +{ + XMC_UNUSED_ARG(eth_mac); + + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_ETH); +#if UC_DEVICE != XMC4500 + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ETH0); +#endif + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ETH0); +} + +/* ETH MAC disable */ +void XMC_ETH_MAC_Disable(XMC_ETH_MAC_t *const eth_mac) +{ + XMC_UNUSED_ARG(eth_mac); + + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ETH0); +#if UC_DEVICE != XMC4500 + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ETH0); +#endif + XMC_SCU_CLOCK_DisableClock(XMC_SCU_CLOCK_ETH); +} + +/* Read physical layer and obtain status */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_ReadPhy(XMC_ETH_MAC_t *eth_mac, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) +{ + uint32_t retries; + + XMC_ASSERT("XMC_ETH_MAC_PhyRead: Parameter error", data != NULL); + + eth_mac->regs->GMII_ADDRESS = (uint32_t)((eth_mac->regs->GMII_ADDRESS & (uint32_t)ETH_GMII_ADDRESS_CR_Msk) | + (uint32_t)ETH_GMII_ADDRESS_MB_Msk | + (uint32_t)((uint32_t)phy_addr << ETH_GMII_ADDRESS_PA_Pos) | + (uint32_t)((uint32_t)reg_addr << ETH_GMII_ADDRESS_MR_Pos)); + + /* Poll busy bit during max PHY_TIMEOUT time */ + retries = 0U; + do + { + if ((eth_mac->regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) == 0U) + { + *data = (uint16_t)(eth_mac->regs->GMII_DATA & ETH_GMII_DATA_MD_Msk); + return XMC_ETH_MAC_STATUS_OK; + } + ++retries; + } while (retries < XMC_ETH_MAC_PHY_MAX_RETRIES); + + return XMC_ETH_MAC_STATUS_ERROR; +} + +/* Write physical layer and return status */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_WritePhy(XMC_ETH_MAC_t *eth_mac, uint8_t phy_addr, uint8_t reg_addr, uint16_t data) +{ + uint32_t retries; + + eth_mac->regs->GMII_DATA = data; + eth_mac->regs->GMII_ADDRESS = (uint32_t)((eth_mac->regs->GMII_ADDRESS & (uint32_t)ETH_GMII_ADDRESS_CR_Msk) | + (uint32_t)ETH_GMII_ADDRESS_MB_Msk | + (uint32_t)ETH_GMII_ADDRESS_MW_Msk | + (uint32_t)((uint32_t)phy_addr << ETH_GMII_ADDRESS_PA_Pos) | + (uint32_t)((uint32_t)reg_addr << ETH_GMII_ADDRESS_MR_Pos)); + + /* Poll busy bit during max PHY_TIMEOUT time */ + retries = 0U; + do + { + if ((eth_mac->regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) == 0U) + { + return XMC_ETH_MAC_STATUS_OK; + } + ++retries; + } while (retries < XMC_ETH_MAC_PHY_MAX_RETRIES); + + return XMC_ETH_MAC_STATUS_ERROR; +} + +/* Flush TX */ +void XMC_ETH_MAC_FlushTx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->OPERATION_MODE &= (uint32_t)~ETH_OPERATION_MODE_ST_Msk; + XMC_ETH_MAC_InitTxDescriptors(eth_mac); + eth_mac->regs->OPERATION_MODE |= (uint32_t)ETH_OPERATION_MODE_ST_Msk; +} + +/* Flush RX */ +void XMC_ETH_MAC_FlushRx(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->regs->OPERATION_MODE &= (uint32_t)~ETH_OPERATION_MODE_SR_Msk; + XMC_ETH_MAC_InitRxDescriptors(eth_mac); + eth_mac->regs->OPERATION_MODE |= (uint32_t)ETH_OPERATION_MODE_SR_Msk; +} + +/* Set wakeup frame filter */ +void XMC_ETH_MAC_SetWakeUpFrameFilter(XMC_ETH_MAC_t *const eth_mac, + const uint32_t (*const filter)[XMC_ETH_WAKEUP_REGISTER_LENGTH]) +{ + uint32_t i = 0U; + + /* Fill Remote Wake-up frame filter register with buffer data */ + for (i = 0U; i < XMC_ETH_WAKEUP_REGISTER_LENGTH; i++) + { + /* Write each time to the same register */ + eth_mac->regs->REMOTE_WAKE_UP_FRAME_FILTER = (*filter)[i]; + } +} + +/* Enable event */ +void XMC_ETH_MAC_EnableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event) +{ + XMC_ASSERT("XMC_ETH_MAC_EnableDMAEvent: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + eth_mac->regs->INTERRUPT_MASK &= ~(event >> 16U); + + event &= (uint16_t)0x7fffU; + if (XCM_ETH_MAC_IsNormalEvent(event)) + { + event |= (uint32_t)ETH_INTERRUPT_ENABLE_NIE_Msk; + } + + if (XCM_ETH_MAC_IsAbnormalEvent(event)) + { + event |= (uint32_t)ETH_INTERRUPT_ENABLE_AIE_Msk; + } + + eth_mac->regs->INTERRUPT_ENABLE |= event; +} + +/* Disable event */ +void XMC_ETH_MAC_DisableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event) +{ + XMC_ASSERT("XMC_ETH_MAC_DisableDMAEvent: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + eth_mac->regs->INTERRUPT_MASK |= event >> 16U; + + event &= 0x7fffU; + eth_mac->regs->INTERRUPT_ENABLE &= ~event; +} + +/* Clear event status */ +void XMC_ETH_MAC_ClearEventStatus(XMC_ETH_MAC_t *const eth_mac, uint32_t event) +{ + XMC_ASSERT("XMC_ETH_MAC_ClearEventStatus: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + if ((eth_mac->regs->STATUS & ETH_STATUS_NIS_Msk) != 0U) + { + event |= (uint32_t)ETH_STATUS_NIS_Msk; + } + + if ((eth_mac->regs->STATUS & ETH_STATUS_AIS_Msk) != 0U) + { + event |= (uint32_t)ETH_STATUS_AIS_Msk; + } + + eth_mac->regs->STATUS = event & 0x0001FFFFU; +} + +/* Obtain event status */ +uint32_t XMC_ETH_MAC_GetEventStatus(const XMC_ETH_MAC_t *const eth_mac) +{ + uint32_t temp_status = 0; + XMC_ASSERT("XMC_ETH_MAC_GetEventStatus: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + temp_status = (eth_mac->regs->STATUS & (uint32_t)0x7ffUL); + + return ((uint32_t)((eth_mac->regs->INTERRUPT_STATUS & (ETH_INTERRUPT_MASK_PMTIM_Msk | ETH_INTERRUPT_MASK_TSIM_Msk)) << 16U) | + temp_status); +} + +/* Return RX descriptor */ +void XMC_ETH_MAC_ReturnRxDescriptor(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->rx_desc[eth_mac->rx_index].status |= ETH_MAC_DMA_RDES0_OWN; + eth_mac->rx_index++; + if (eth_mac->rx_index == eth_mac->num_rx_buf) + { + eth_mac->rx_index = 0U; + } +} + +/* Return TX descriptor */ +void XMC_ETH_MAC_ReturnTxDescriptor(XMC_ETH_MAC_t *const eth_mac) +{ + eth_mac->tx_ts_index = eth_mac->tx_index; + + eth_mac->tx_desc[eth_mac->tx_index].status |= ETH_MAC_DMA_TDES0_CIC |ETH_MAC_DMA_TDES0_OWN; + eth_mac->tx_index++; + if (eth_mac->tx_index == eth_mac->num_tx_buf) + { + eth_mac->tx_index = 0U; + } + + eth_mac->frame_end = NULL; +} + +/* Set VLAN tag */ +void XMC_ETH_MAC_SetVLANTag(XMC_ETH_MAC_t *const eth_mac, uint16_t tag) +{ + XMC_ASSERT("XMC_ETH_MAC_SetVLANTag: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + eth_mac->regs->VLAN_TAG = (uint32_t)tag; +} + +/* Initialize PTP */ +void XMC_ETH_MAC_InitPTP(XMC_ETH_MAC_t *const eth_mac, uint32_t config) +{ + XMC_ASSERT("XMC_ETH_MAC_InitPTP: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + /* Mask the time stamp interrupt */ + eth_mac->regs->INTERRUPT_MASK |= (uint32_t)ETH_INTERRUPT_MASK_TSIM_Msk; + + /* Enable time stamp */ + eth_mac->regs->TIMESTAMP_CONTROL = ETH_TIMESTAMP_CONTROL_TSENA_Msk; + + /* Program sub-second increment register based on PTP clock frequency = fSYS/2 */ + /* the nanoseconds register has a resolution of ~0.465ns. */ + eth_mac->regs->SUB_SECOND_INCREMENT = (uint32_t)((0x80000000U / (float)(XMC_SCU_CLOCK_GetSystemClockFrequency() / 2)) + 0.5F); + + if ((config & (uint32_t)XMC_ETH_MAC_TIMESTAMP_CONFIG_FINE_UPDATE) != 0U) + { + /* Program addend register to obtain fSYS/2 from reference clock (fSYS) */ + eth_mac->regs->TIMESTAMP_ADDEND = (uint32_t)0x80000000U; + /* Addend register update */ + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk; + /* Poll the Timestamp Control register until the bit TSADDREG is cleared */ + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk); + } + + eth_mac->regs->TIMESTAMP_CONTROL |= config | (uint32_t)ETH_TIMESTAMP_CONTROL_TSINIT_Msk; + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk); +} + +/* Initialize PTP using a given time */ +void XMC_ETH_MAC_InitPTPEx(XMC_ETH_MAC_t *const eth_mac, uint32_t config, XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ASSERT("XMC_ETH_MAC_InitPTP: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + /* Mask the time stamp interrupt */ + eth_mac->regs->INTERRUPT_MASK |= (uint32_t)ETH_INTERRUPT_MASK_TSIM_Msk; + + /* Enable time stamp */ + eth_mac->regs->TIMESTAMP_CONTROL = ETH_TIMESTAMP_CONTROL_TSENA_Msk; + + /* Program sub-second increment register based on PTP clock frequency = fSYS/2 */ + /* the nanoseconds register has a resolution of ~0.465ns. */ + eth_mac->regs->SUB_SECOND_INCREMENT = (uint32_t)((0x80000000U / (float)(XMC_SCU_CLOCK_GetSystemClockFrequency() / 2)) + 0.5F); + + if ((config & (uint32_t)XMC_ETH_MAC_TIMESTAMP_CONFIG_FINE_UPDATE) != 0U) + { + /* Program addend register to obtain fSYS/2 from reference clock (fSYS) */ + eth_mac->regs->TIMESTAMP_ADDEND = (uint32_t)0x80000000U; + /* Addend register update */ + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk; + /* Poll the Timestamp Control register until the bit TSADDREG is cleared */ + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk); + } + + /* Initialize the system time */ + eth_mac->regs->SYSTEM_TIME_NANOSECONDS_UPDATE = time->nanoseconds; + eth_mac->regs->SYSTEM_TIME_SECONDS_UPDATE = time->seconds; + + eth_mac->regs->TIMESTAMP_CONTROL |= config | (uint32_t)ETH_TIMESTAMP_CONTROL_TSINIT_Msk; + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk); +} + +/* Get PTP time */ +void XMC_ETH_MAC_GetPTPTime(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ASSERT("XMC_ETH_MAC_GetPTPTime: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + time->nanoseconds = (uint32_t)(eth_mac->regs->SYSTEM_TIME_NANOSECONDS * (1000000000.0F / 0x80000000U)); /* accuracy of 0.46 ns */ + time->seconds = eth_mac->regs->SYSTEM_TIME_SECONDS; +} + +/* Set PTP time */ +void XMC_ETH_MAC_SetPTPTime(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ASSERT("XMC_ETH_MAC_GetPTPTime: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + eth_mac->regs->SYSTEM_TIME_SECONDS_UPDATE = time->seconds; + eth_mac->regs->SYSTEM_TIME_NANOSECONDS_UPDATE = time->nanoseconds; + + /* Initialize precision timer */ + ETH0->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSINIT_Msk; + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk); +} + +/* Update PTP time */ +void XMC_ETH_MAC_UpdatePTPTime(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_TIME_t *const time) +{ + uint32_t temp; + + XMC_ASSERT("XMC_ETH_MAC_UpdatePTPTime: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_UpdatePTPTime: time.time_stamp_nanoseconds not in range", (time->nanoseconds < 1000000000.0F)); + + temp = (uint32_t)(abs(time->nanoseconds) * (0x80000000U / 1000000000.0F)); + if (time->nanoseconds < 0) + { + temp |= (uint32_t)ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk; + } + + eth_mac->regs->SYSTEM_TIME_NANOSECONDS_UPDATE = temp; + eth_mac->regs->SYSTEM_TIME_SECONDS_UPDATE = time->seconds; + + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSUPDT_Msk; +} + +/* Set PTP alarm */ +void XMC_ETH_MAC_SetPTPAlarm(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ASSERT("XMC_ETH_MAC_SetPTPAlarm: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_SetPTPAlarm: time.time_stamp_nanoseconds not in range", (time->nanoseconds < 1000000000.0F)); + + eth_mac->regs->TARGET_TIME_NANOSECONDS = (uint32_t)(time->nanoseconds * (0x80000000U / 1000000000.0F)); + eth_mac->regs->TARGET_TIME_SECONDS = time->seconds; +} + +/* Adjust PTP clock */ +void XMC_ETH_MAC_AdjustPTPClock(XMC_ETH_MAC_t *const eth_mac, uint32_t correction) +{ + XMC_ASSERT("XMC_ETH_MAC_AdjustPTPClock: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + /* Correction factor is Q31 (0x80000000 = 1.000000000) */ + eth_mac->regs->TIMESTAMP_ADDEND = (uint32_t)(((uint64_t)correction * eth_mac->regs->TIMESTAMP_ADDEND) >> 31U); + + /* Update addend register */ + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk; + + /* Poll the Timestamp Control register until the bit TSADDREG is cleared */ + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk); +} + +/* Update Addend */ +void XMC_ETH_MAC_UpdateAddend(XMC_ETH_MAC_t *const eth_mac, uint32_t addend) +{ + XMC_ASSERT("XMC_ETH_MAC_AdjustPTPClock: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + eth_mac->regs->TIMESTAMP_ADDEND = addend; + + /* Update addend register */ + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk; + + /* Poll the Timestamp Control register until the bit TSADDREG is cleared */ + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk); +} + +/* Set PTP status */ +uint32_t XMC_ETH_MAC_GetPTPStatus(const XMC_ETH_MAC_t *const eth_mac) +{ + XMC_ASSERT("XMC_ETH_MAC_GetPTPStatus: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + return (eth_mac->regs->TIMESTAMP_STATUS); +} + +/* Get TX time-stamp */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_GetRxTimeStamp(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ETH_MAC_DMA_DESC_t *rx_desc; + XMC_ETH_MAC_STATUS_t status; + + XMC_ASSERT("XMC_ETH_MAC_GetRxTimeStamp: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_GetRxTimeStamp: time is invalid", time != NULL); + + rx_desc = ð_mac->rx_desc[eth_mac->rx_index]; + if (rx_desc->status & ETH_MAC_DMA_RDES0_OWN) + { + status = XMC_ETH_MAC_STATUS_BUSY; + } + else + { + if ((rx_desc->status & (ETH_MAC_DMA_RDES0_TSA | ETH_MAC_DMA_RDES0_LS)) == (ETH_MAC_DMA_RDES0_TSA | ETH_MAC_DMA_RDES0_LS)) + { + time->nanoseconds = (int32_t)rx_desc->time_stamp_nanoseconds; + time->seconds = rx_desc->time_stamp_seconds; + + status = XMC_ETH_MAC_STATUS_OK; + } + else + { + status = XMC_ETH_MAC_STATUS_ERROR; + } + } + + return status; +} + +/* Get TX time-stamp */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_GetTxTimeStamp(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time) +{ + XMC_ETH_MAC_DMA_DESC_t *tx_desc; + XMC_ETH_MAC_STATUS_t status; + + XMC_ASSERT("XMC_ETH_MAC_GetTxTimeStamp: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_GetTxTimeStamp: time is invalid", time != NULL); + + tx_desc = ð_mac->tx_desc[eth_mac->tx_ts_index]; + if (tx_desc->status & ETH_MAC_DMA_TDES0_OWN) + { + status = XMC_ETH_MAC_STATUS_BUSY; + } + else + { + if ((tx_desc->status & (ETH_MAC_DMA_TDES0_TTSS | ETH_MAC_DMA_TDES0_LS)) == (ETH_MAC_DMA_TDES0_TTSS | ETH_MAC_DMA_TDES0_LS)) + { + time->nanoseconds = (int32_t)tx_desc->time_stamp_nanoseconds; + time->seconds = tx_desc->time_stamp_seconds; + + status = XMC_ETH_MAC_STATUS_OK; + } + else + { + status = XMC_ETH_MAC_STATUS_ERROR; + } + } + + return status; +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_phy_dp83848.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_phy_dp83848.c new file mode 100644 index 00000000..12be26c1 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_phy_dp83848.c @@ -0,0 +1,299 @@ +/** + * @file xmc_eth_phy_dp83848.c + * @date 2015-12-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial
+ * + * 2015-12-15: + * - Added Reset and exit power down + * - Reset function called in Init function + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#if defined(XMC_ETH_PHY_DP83848C) +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/* Basic Registers */ +#define REG_BMCR (0x00U) /* Basic Mode Control Register */ +#define REG_BMSR (0x01U) /* Basic Mode Status Register */ +#define REG_PHYIDR1 (0x02U) /* PHY Identifier 1 */ +#define REG_PHYIDR2 (0x03U) /* PHY Identifier 2 */ +#define REG_ANAR (0x04U) /* Auto-Negotiation Advertisement */ +#define REG_ANLPAR (0x05U) /* Auto-Neg. Link Partner Abitily */ +#define REG_ANER (0x06U) /* Auto-Neg. Expansion Register */ +#define REG_ANNPTR (0x07U) /* Auto-Neg. Next Page TX */ +#define REG_RBR (0x17U) /* RMII and Bypass Register */ + +/* Extended Registers */ +#define REG_PHYSTS (0x10U) /* Status Register */ + +/* Basic Mode Control Register */ +#define BMCR_RESET (0x8000U) /* Software Reset */ +#define BMCR_LOOPBACK (0x4000U) /* Loopback mode */ +#define BMCR_SPEED_SEL (0x2000U) /* Speed Select (1=100Mb/s) */ +#define BMCR_ANEG_EN (0x1000U) /* Auto Negotiation Enable */ +#define BMCR_POWER_DOWN (0x0800U) /* Power Down */ +#define BMCR_ISOLATE (0x0400U) /* Isolate Media interface */ +#define BMCR_REST_ANEG (0x0200U) /* Restart Auto Negotiation */ +#define BMCR_DUPLEX (0x0100U) /* Duplex Mode (1=Full duplex) */ +#define BMCR_COL_TEST (0x0080U) /* Collision Test */ + +/* Basic Mode Status Register */ +#define BMSR_100B_T4 (0x8000U) /* 100BASE-T4 Capable */ +#define BMSR_100B_TX_FD (0x4000U) /* 100BASE-TX Full Duplex Capable */ +#define BMSR_100B_TX_HD (0x2000U) /* 100BASE-TX Half Duplex Capable */ +#define BMSR_10B_T_FD (0x1000U) /* 10BASE-T Full Duplex Capable */ +#define BMSR_10B_T_HD (0x0800U) /* 10BASE-T Half Duplex Capable */ +#define BMSR_MF_PRE_SUP (0x0040U) /* Preamble suppression Capable */ +#define BMSR_ANEG_COMPL (0x0020U) /* Auto Negotiation Complete */ +#define BMSR_REM_FAULT (0x0010U) /* Remote Fault */ +#define BMSR_ANEG_ABIL (0x0008U) /* Auto Negotiation Ability */ +#define BMSR_LINK_STAT (0x0004U) /* Link Status (1=established) */ +#define BMSR_JABBER_DET (0x0002U) /* Jaber Detect */ +#define BMSR_EXT_CAPAB (0x0001U) /* Extended Capability */ + +/* RMII and Bypass Register */ +#define RBR_RMII_MODE (0x0020U) /* Reduced MII Mode */ + +/* PHY Identifier Registers */ +#define PHY_ID1 0x2000 /* DP83848C Device Identifier MSB */ +#define PHY_ID2 0x5C90 /* DP83848C Device Identifier LSB */ + +/* PHY Status Register */ +#define PHYSTS_MDI_X 0x4000 /* MDI-X mode enabled by Auto-Negot. */ +#define PHYSTS_REC_ERR 0x2000 /* Receive Error Latch */ +#define PHYSTS_POL_STAT 0x1000 /* Polarity Status */ +#define PHYSTS_FC_SENSE 0x0800 /* False Carrier Sense Latch */ +#define PHYSTS_SIG_DET 0x0400 /* 100Base-TX Signal Detect */ +#define PHYSTS_DES_LOCK 0x0200 /* 100Base-TX Descrambler Lock */ +#define PHYSTS_PAGE_REC 0x0100 /* Link Code Word Page Received */ +#define PHYSTS_MII_INT 0x0080 /* MII Interrupt Pending */ +#define PHYSTS_REM_FAULT 0x0040 /* Remote Fault */ +#define PHYSTS_JABBER_DET 0x0020 /* Jabber Detect */ +#define PHYSTS_ANEG_COMPL 0x0010 /* Auto Negotiation Complete */ +#define PHYSTS_LOOPBACK 0x0008 /* Loopback Status */ +#define PHYSTS_DUPLEX 0x0004 /* Duplex Status (1=Full duplex) */ +#define PHYSTS_SPEED 0x0002 /* Speed10 Status (1=10MBit/s) */ +#define PHYSTS_LINK_STAT 0x0001 /* Link Status (1=established) */ + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + + /* Check if the device identifier is valid */ +static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t phy_id1; + uint16_t phy_id2; + XMC_ETH_PHY_STATUS_t status; + + /* Check Device Identification. */ + if ((XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR1, &phy_id1) == XMC_ETH_MAC_STATUS_OK) && + (XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR2, &phy_id2) == XMC_ETH_MAC_STATUS_OK)) + { + if ((phy_id1 == PHY_ID1) && ((phy_id2 & (uint16_t)0xfff0) == PHY_ID2)) + { + status = XMC_ETH_PHY_STATUS_OK; + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID; + } + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_TIMEOUT; + } + + return (int32_t)status; +} + +/* PHY initialize */ +int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config) +{ + int32_t status; + uint16_t reg_val; + + status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + status = XMC_ETH_PHY_Reset(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_val = 0U; + if (config->speed == XMC_ETH_LINK_SPEED_100M) + { + reg_val |= BMCR_SPEED_SEL; + } + + if (config->duplex == XMC_ETH_LINK_DUPLEX_FULL) + { + reg_val |= BMCR_DUPLEX; + } + + if (config->enable_auto_negotiate == true) + { + reg_val |= BMCR_ANEG_EN; + } + + if (config->enable_loop_back == true) + { + reg_val |= BMCR_LOOPBACK; + } + + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_val); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + /* Configure interface mode */ + switch (config->interface) + { + case XMC_ETH_LINK_INTERFACE_MII: + reg_val = 0x0001; + break; + case XMC_ETH_LINK_INTERFACE_RMII: + reg_val = RBR_RMII_MODE | 0x0001; + break; + } + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_RBR, reg_val); + } + } + } + + return status; +} + +/* Reset */ +int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + /* Reset PHY*/ + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + /* Wait for the reset to complete */ + do + { + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + } while ((reg_bmcr & BMCR_RESET) != 0); + } + + return status; +} + +/* Initiate power down */ +int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr |= BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Exit power down */ +int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr &= ~BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Get link status */ +XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + + return (XMC_ETH_LINK_STATUS_t)((val & BMSR_LINK_STAT) ? XMC_ETH_LINK_STATUS_UP : XMC_ETH_LINK_STATUS_DOWN); +} + +/* Get link speed */ +XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYSTS, &val); + + return (XMC_ETH_LINK_SPEED_t)((val & PHYSTS_SPEED) ? XMC_ETH_LINK_SPEED_10M : XMC_ETH_LINK_SPEED_100M); +} + +/* Get link duplex settings */ +XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYSTS, &val); + + return (XMC_ETH_LINK_DUPLEX_t)((val & PHYSTS_DUPLEX) ? XMC_ETH_LINK_DUPLEX_FULL : XMC_ETH_LINK_DUPLEX_HALF); +} + +bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + return ((val & BMSR_ANEG_COMPL) == BMSR_ANEG_COMPL); +} + +#endif // defined(XMC_ETH_PHY_DP83848C) diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_phy_ksz8031rnl.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_phy_ksz8031rnl.c new file mode 100644 index 00000000..e0c912d3 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_phy_ksz8031rnl.c @@ -0,0 +1,267 @@ +/** + * @file xmc_eth_phy_ksz8031ml.c + * @date 2015-12-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * + * 2015-12-15: + * - Added Reset and exit power down + * - Reset function called in Init function + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#if defined(XMC_ETH_PHY_KSZ8031RNL) +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/* Basic Registers */ +#define REG_BMCR (0x00U) /* Basic Mode Control Register */ +#define REG_BMSR (0x01U) /* Basic Mode Status Register */ +#define REG_PHYIDR1 (0x02U) /* PHY Identifier 1 */ +#define REG_PHYIDR2 (0x03U) /* PHY Identifier 2 */ +#define REG_ANAR (0x04U) /* Auto-Negotiation Advertisement */ +#define REG_ANLPAR (0x05U) /* Auto-Neg. Link Partner Abitily */ +#define REG_ANER (0x06U) /* Auto-Neg. Expansion Register */ +#define REG_ANNPTR (0x07U) /* Auto-Neg. Next Page TX */ + +/* Extended Registers */ +#define REG_PHYCTRL1 (0x1eU) /* PHY control 1 Register */ + +/* Basic Mode Control Register */ +#define BMCR_RESET (0x8000U) /* Software Reset */ +#define BMCR_LOOPBACK (0x4000U) /* Loopback mode */ +#define BMCR_SPEED_SEL (0x2000U) /* Speed Select (1=100Mb/s) */ +#define BMCR_ANEG_EN (0x1000U) /* Auto Negotiation Enable */ +#define BMCR_POWER_DOWN (0x0800U) /* Power Down */ +#define BMCR_ISOLATE (0x0400U) /* Isolate Media interface */ +#define BMCR_REST_ANEG (0x0200U) /* Restart Auto Negotiation */ +#define BMCR_DUPLEX (0x0100U) /* Duplex Mode (1=Full duplex) */ +#define BMCR_COL_TEST (0x0080U) /* Collision Test */ + +/* Basic Mode Status Register */ +#define BMSR_100B_T4 (0x8000U) /* 100BASE-T4 Capable */ +#define BMSR_100B_TX_FD (0x4000U) /* 100BASE-TX Full Duplex Capable */ +#define BMSR_100B_TX_HD (0x2000U) /* 100BASE-TX Half Duplex Capable */ +#define BMSR_10B_T_FD (0x1000U) /* 10BASE-T Full Duplex Capable */ +#define BMSR_10B_T_HD (0x0800U) /* 10BASE-T Half Duplex Capable */ +#define BMSR_MF_PRE_SUP (0x0040U) /* Preamble suppression Capable */ +#define BMSR_ANEG_COMPL (0x0020U) /* Auto Negotiation Complete */ +#define BMSR_REM_FAULT (0x0010U) /* Remote Fault */ +#define BMSR_ANEG_ABIL (0x0008U) /* Auto Negotiation Ability */ +#define BMSR_LINK_STAT (0x0004U) /* Link Status (1=established) */ +#define BMSR_JABBER_DET (0x0002U) /* Jaber Detect */ +#define BMSR_EXT_CAPAB (0x0001U) /* Extended Capability */ + +/* PHY control 1 Register */ +#define PHYCTRL1_OPMODE_SPEED (0x0003U) +#define PHYCTRL1_OPMODE_DUPLEX (0x0004U) + +/* PHY Identifier Registers */ +#define PHY_ID1 (0x0022U) /* KSZ8031 Device Identifier MSB */ +#define PHY_ID2 (0x1550U) /* KSZ8031 Device Identifier LSB */ + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + + /* Check if the device identifier is valid */ +static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t phy_id1; + uint16_t phy_id2; + XMC_ETH_PHY_STATUS_t status; + + /* Check Device Identification. */ + if ((XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR1, &phy_id1) == XMC_ETH_MAC_STATUS_OK) && + (XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR2, &phy_id2) == XMC_ETH_MAC_STATUS_OK)) + { + if ((phy_id1 == PHY_ID1) && ((phy_id2 & (uint16_t)0xfff0) == PHY_ID2)) + { + status = XMC_ETH_PHY_STATUS_OK; + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID; + } + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_TIMEOUT; + } + + return (int32_t)status; +} + +/* PHY initialize */ +int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + status = XMC_ETH_PHY_Reset(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr = 0U; + if (config->speed == XMC_ETH_LINK_SPEED_100M) + { + reg_bmcr |= BMCR_SPEED_SEL; + } + + if (config->duplex == XMC_ETH_LINK_DUPLEX_FULL) + { + reg_bmcr |= BMCR_DUPLEX; + } + + if (config->enable_auto_negotiate == true) + { + reg_bmcr |= BMCR_ANEG_EN; + } + + if (config->enable_loop_back == true) + { + reg_bmcr |= BMCR_LOOPBACK; + } + + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + } + + return status; +} + +/* Reset */ +int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + /* Reset PHY*/ + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + /* Wait for the reset to complete */ + do + { + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + } while ((reg_bmcr & BMCR_RESET) != 0); + } + + return status; +} + +/* Initiate power down */ +int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr |= BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Exit power down */ +int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr &= ~BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Get link status */ +XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + + return (XMC_ETH_LINK_STATUS_t)((val & BMSR_LINK_STAT) ? XMC_ETH_LINK_STATUS_UP : XMC_ETH_LINK_STATUS_DOWN); +} + +/* Get link speed */ +XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val); + + return (XMC_ETH_LINK_SPEED_t)(((val & PHYCTRL1_OPMODE_SPEED) - 1U) ? XMC_ETH_LINK_SPEED_100M : XMC_ETH_LINK_SPEED_10M); +} + +/* Get link duplex settings */ +XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val); + + return (XMC_ETH_LINK_DUPLEX_t)((val & PHYCTRL1_OPMODE_DUPLEX) ? XMC_ETH_LINK_DUPLEX_FULL : XMC_ETH_LINK_DUPLEX_HALF); +} + +bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + return ((val & BMSR_ANEG_COMPL) == BMSR_ANEG_COMPL); +} + +#endif // defined(XMC_ETH_PHY_KSZ8031RNL) diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_phy_ksz8081rnb.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_phy_ksz8081rnb.c new file mode 100644 index 00000000..05c3077c --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_eth_phy_ksz8081rnb.c @@ -0,0 +1,266 @@ +/** + * @file xmc_eth_phy_ksz8081rnb.c + * @date 2015-12-15 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-06-20: + * - Initial + * + * 2015-12-15: + * - Added Reset and exit power down + * - Reset function called in Init function + * + * @endcond + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#if defined(XMC_ETH_PHY_KSZ8081RNB) +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/* Basic Registers */ +#define REG_BMCR (0x00U) /* Basic Mode Control Register */ +#define REG_BMSR (0x01U) /* Basic Mode Status Register */ +#define REG_PHYIDR1 (0x02U) /* PHY Identifier 1 */ +#define REG_PHYIDR2 (0x03U) /* PHY Identifier 2 */ +#define REG_ANAR (0x04U) /* Auto-Negotiation Advertisement */ +#define REG_ANLPAR (0x05U) /* Auto-Neg. Link Partner Abitily */ +#define REG_ANER (0x06U) /* Auto-Neg. Expansion Register */ +#define REG_ANNPTR (0x07U) /* Auto-Neg. Next Page TX */ + +/* Extended Registers */ +#define REG_PHYCTRL1 (0x1eU) /* PHY control 1 Register */ + +/* Basic Mode Control Register */ +#define BMCR_RESET (0x8000U) /* Software Reset */ +#define BMCR_LOOPBACK (0x4000U) /* Loopback mode */ +#define BMCR_SPEED_SEL (0x2000U) /* Speed Select (1=100Mb/s) */ +#define BMCR_ANEG_EN (0x1000U) /* Auto Negotiation Enable */ +#define BMCR_POWER_DOWN (0x0800U) /* Power Down */ +#define BMCR_ISOLATE (0x0400U) /* Isolate Media interface */ +#define BMCR_REST_ANEG (0x0200U) /* Restart Auto Negotiation */ +#define BMCR_DUPLEX (0x0100U) /* Duplex Mode (1=Full duplex) */ +#define BMCR_COL_TEST (0x0080U) /* Collision Test */ + +/* Basic Mode Status Register */ +#define BMSR_100B_T4 (0x8000U) /* 100BASE-T4 Capable */ +#define BMSR_100B_TX_FD (0x4000U) /* 100BASE-TX Full Duplex Capable */ +#define BMSR_100B_TX_HD (0x2000U) /* 100BASE-TX Half Duplex Capable */ +#define BMSR_10B_T_FD (0x1000U) /* 10BASE-T Full Duplex Capable */ +#define BMSR_10B_T_HD (0x0800U) /* 10BASE-T Half Duplex Capable */ +#define BMSR_MF_PRE_SUP (0x0040U) /* Preamble suppression Capable */ +#define BMSR_ANEG_COMPL (0x0020U) /* Auto Negotiation Complete */ +#define BMSR_REM_FAULT (0x0010U) /* Remote Fault */ +#define BMSR_ANEG_ABIL (0x0008U) /* Auto Negotiation Ability */ +#define BMSR_LINK_STAT (0x0004U) /* Link Status (1=established) */ +#define BMSR_JABBER_DET (0x0002U) /* Jaber Detect */ +#define BMSR_EXT_CAPAB (0x0001U) /* Extended Capability */ + +/* PHY control 1 Register */ +#define PHYCTRL1_OPMODE_SPEED (0x0003U) +#define PHYCTRL1_OPMODE_DUPLEX (0x0004U) + +/* PHY Identifier Registers */ +#define PHY_ID1 (0x0022U) /* KSZ8031 Device Identifier MSB */ +#define PHY_ID2 (0x1560U) /* KSZ8031 Device Identifier LSB */ + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + + /* Check if the device identifier is valid */ +static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t phy_id1; + uint16_t phy_id2; + XMC_ETH_PHY_STATUS_t status; + + /* Check Device Identification. */ + if ((XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR1, &phy_id1) == XMC_ETH_MAC_STATUS_OK) && + (XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR2, &phy_id2) == XMC_ETH_MAC_STATUS_OK)) + { + if ((phy_id1 == PHY_ID1) && ((phy_id2 & (uint16_t)0xfff0) == PHY_ID2)) + { + status = XMC_ETH_PHY_STATUS_OK; + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID; + } + } + else + { + status = XMC_ETH_PHY_STATUS_ERROR_TIMEOUT; + } + + return (int32_t)status; +} + +/* PHY initialize */ +int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + status = XMC_ETH_PHY_Reset(eth_mac, phy_addr); + + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr = 0U; + if (config->speed == XMC_ETH_LINK_SPEED_100M) + { + reg_bmcr |= BMCR_SPEED_SEL; + } + + if (config->duplex == XMC_ETH_LINK_DUPLEX_FULL) + { + reg_bmcr |= BMCR_DUPLEX; + } + + if (config->enable_auto_negotiate == true) + { + reg_bmcr |= BMCR_ANEG_EN; + } + + if (config->enable_loop_back == true) + { + reg_bmcr |= BMCR_LOOPBACK; + } + + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + } + + return status; +} + +/* Reset */ +int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + /* Reset PHY*/ + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + /* Wait for the reset to complete */ + do + { + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + } while ((reg_bmcr & BMCR_RESET) != 0); + } + + return status; +} + +/* Initiate power down */ +int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr |= BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Exit power down */ +int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + int32_t status; + uint16_t reg_bmcr; + + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) + { + reg_bmcr &= ~BMCR_POWER_DOWN; + status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); + } + return status; +} + +/* Get link status */ +XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + + return (XMC_ETH_LINK_STATUS_t)((val & BMSR_LINK_STAT) ? XMC_ETH_LINK_STATUS_UP : XMC_ETH_LINK_STATUS_DOWN); +} + +/* Get link speed */ +XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val); + + return (XMC_ETH_LINK_SPEED_t)(((val & PHYCTRL1_OPMODE_SPEED) - 1U) ? XMC_ETH_LINK_SPEED_100M : XMC_ETH_LINK_SPEED_10M); +} + +/* Get link duplex settings */ +XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val); + + return (XMC_ETH_LINK_DUPLEX_t)((val & PHYCTRL1_OPMODE_DUPLEX) ? XMC_ETH_LINK_DUPLEX_FULL : XMC_ETH_LINK_DUPLEX_HALF); +} + +bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) +{ + uint16_t val; + + XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val); + return ((val & BMSR_ANEG_COMPL) == BMSR_ANEG_COMPL); +} +#endif // XMC_ETH_PHY_KSZ8081RNB diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_fce.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_fce.c new file mode 100644 index 00000000..09ac2f13 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_fce.c @@ -0,0 +1,258 @@ +/** + * @file xmc_fce.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed GetDriverVersion API + * @endcond + * + */ + +/********************************************************************************************************************** + * HEADER FILES + *********************************************************************************************************************/ +#include + +#if defined (FCE) +#include + +/******************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ + +/* + * Initialize the FCE peripheral: + * Update FCE configuration and initialize seed value + */ +XMC_FCE_STATUS_t XMC_FCE_Init(const XMC_FCE_t *const engine) +{ + engine->kernel_ptr->CFG = engine->fce_cfg_update.regval; + engine->kernel_ptr->CRC = engine->seedvalue; + + return XMC_FCE_STATUS_OK; +} + +/* Disable FCE */ +void XMC_FCE_Disable(void) +{ + FCE->CLC |= (uint32_t)FCE_CLC_DISR_Msk; + + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_FCE); + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_FCE); +#endif + +} + +/* Enable FCE */ +void XMC_FCE_Enable(void) +{ +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_FCE); +#endif + + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_FCE); + + FCE->CLC &= (uint32_t)~FCE_CLC_DISR_Msk; +} + +/* Calculate and return the SAE J1850 CRC8 checksum */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine, + const uint8_t *data, + uint32_t length, + uint8_t *result) +{ + XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK; + + XMC_ASSERT("XMC_FCE_CalculateCRC8: Wrong FCE kernel used", (engine -> kernel_ptr == XMC_FCE_CRC8)); + + if (length == 0UL) + { + status = XMC_FCE_STATUS_ERROR; + } + else + { + while (0UL != length) + { + engine->kernel_ptr->IR = *data; + data++; + length -= 1U; + } + + *result = (uint8_t)engine->kernel_ptr->CRC; + } + + return status; +} + +/* Calculate and return calculated CCITT CRC16 checksum */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine, + const uint16_t *data, + uint32_t length, + uint16_t *result) +{ + XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK; + + XMC_ASSERT("XMC_FCE_CalculateCRC16: Wrong FCE kernel used", (engine -> kernel_ptr == XMC_FCE_CRC16)); + XMC_ASSERT("XMC_FCE_CalculateCRC16: Length field is empty", (length != 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC16: Length is not aligned", ((length & 0x01) == 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC16: Buffer is not aligned", (((uint32_t)data % 2U) == 0)); + + /* Check if data and length are word aligned */ + if (((length & 0x01U) != 0U) || (((uint32_t)length % 2U) != 0U)) + { + status = XMC_FCE_STATUS_ERROR; + } + else + { + while (0UL != length) + { + engine->kernel_ptr->IR = *data; + data++; + length -= 2U; + } + + *result = (uint16_t)engine->kernel_ptr->CRC; + } + + return status; +} + +/* Calculate and return the IEEE 802.3 Ethernet CRC32 checksum */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine, + const uint32_t *data, + uint32_t length, + uint32_t *result) +{ + XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK; + + XMC_ASSERT("XMC_FCE_CalculateCRC32: Wrong FCE kernel used", ((engine->kernel_ptr == XMC_FCE_CRC32_0) || + (engine->kernel_ptr == XMC_FCE_CRC32_1))); + XMC_ASSERT("XMC_FCE_CalculateCRC32: Length field is empty", (length != 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC32: Length is not aligned", ((length & 0x03) == 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC32: Buffer is not aligned", (((uint32_t)data % 4U) == 0)); + + /* Check if data and length are word aligned */ + if (((length & 0x03U) != 0U) || (((uint32_t)length % 4U) != 0U)) + { + status = XMC_FCE_STATUS_ERROR; + } + else + { + while (0UL != length) + { + engine->kernel_ptr->IR = *data; + data++; + length -= 4U; + } + + *result = engine->kernel_ptr->CRC; + } + + return status; +} + +/* Trigger mismatch in the CRC registers */ +void XMC_FCE_TriggerMismatch(const XMC_FCE_t *const engine, XMC_FCE_CTR_TEST_t test) +{ + /* Create a 0 to 1 transition and clear to 0 once it is done */ + engine->kernel_ptr->CTR &= ~((uint32_t)test); + engine->kernel_ptr->CTR |= (uint32_t)test; + engine->kernel_ptr->CTR &= ~((uint32_t)test); +} + +/* Change endianness of 16-bit input buffer */ +void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t length) +{ + uint16_t counter = 0U; + uint16_t bytecounter = 0U; + + if ((length & 0x01U) == 0) + { + for (counter = 0U; counter < (length >> 1); counter++) + { + outbuffer[counter] = 0U; + } + + outbuffer[counter] = 0U; + counter = 0U; + + while (length) + { + outbuffer[counter] = ((uint16_t)((uint16_t)inbuffer[bytecounter] << 8U) | + (inbuffer[bytecounter + 1U])); + counter += 1U; + bytecounter += 2U; + length -= 2U; + } + } +} + +/* Change endianness of 32-bit input buffer */ +void XMC_FCE_LittleEndian32bit(uint8_t* inbuffer, uint32_t* outbuffer, uint16_t length) +{ + uint16_t counter = 0U; + uint16_t bytecounter = 0U; + + if ((length & 0x03U) == 0) + { + for (counter = 0U; counter < (length >> 2U); counter++) + { + outbuffer[counter] = 0U; + } + + outbuffer[counter] = 0U; + counter = 0U; + + while (length) + { + outbuffer[counter] = ((uint32_t)inbuffer[bytecounter] << 24U) | + ((uint32_t)inbuffer[bytecounter + 1U] << 16U) | + ((uint32_t)inbuffer[bytecounter + 2U] << 8U) | + (inbuffer[bytecounter + 3U]); + counter += 1U; + bytecounter += 4U; + length -= 4U; + } + } +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_gpio.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_gpio.c new file mode 100644 index 00000000..208b32dd --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_gpio.c @@ -0,0 +1,81 @@ +/** + * @file xmc_gpio.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * @endcond + * + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define PORT_HWSEL_Msk PORT0_HWSEL_HW0_Msk + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +void XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode) +{ + XMC_ASSERT("XMC_GPIO_SetMode: Invalid port", XMC_GPIO_CHECK_PORT(port)); + XMC_ASSERT("XMC_GPIO_SetMode: Invalid mode", XMC_GPIO_IsModeValid(mode)); + + port->IOCR[(uint32_t)pin >> 2U] &= ~(uint32_t)((uint32_t)PORT_IOCR_PC_Msk << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U))); + port->IOCR[(uint32_t)pin >> 2U] |= (uint32_t)mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U)); +} + +void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl) +{ + XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid port", XMC_GPIO_CHECK_PORT(port)); + XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid hwctrl", XMC_GPIO_CHECK_HWCTRL(hwctrl)); + + port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U)); + port->HWSEL |= (uint32_t)hwctrl << ((uint32_t)pin << 1U); +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_hrpwm.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_hrpwm.c new file mode 100644 index 00000000..e015b879 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_hrpwm.c @@ -0,0 +1,591 @@ + +/** + * @file xmc_hrpwm.c + * @date 2015-07-14 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Variable g_hrpwm_char_data[] defined in startup file is used in place of trim data macro
+ * + * 2015-05-12: + * - XMC_HRPWM_CSG_SelClampingInput() api is added to select the clamping input.
+ * - In XMC_HRPWM_Init() api macros used to check 'ccu_clock' frequency are renamed for readability
+ * - 80MHz HRC operation would need a minimum of 70 Mhz CCU clock.
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * - Updated copyright and change history section.
+ * + * 2015-07-06: + * - CSG trimming data assignment is corrected.
+ * + * 2015-07-14: + * - Redundant code removed in XMC_HRPWM_HRC_ConfigSourceSelect0() and XMC_HRPWM_HRC_ConfigSourceSelect1() API's.
+ * - Enums and masks are type casted to uint32_t type. + * + * @endcond + * + */ + +/** + * + * @brief HRPWM low level driver API prototype definition for XMC family of microcontrollers
+ * + * Detailed description of file
+ * APIs provided in this file cover the following functional blocks of HRPWM:
+ * -- High Resolution Channel (APIs prefixed with XMC_HRPWM_HRC_)
+ * -- Comparator and Slope Generator (APIs prefixed with XMC_HRPWM_CSG_)
+ * + */ + +/*********************************************************************************************************************** + * HEADER FILES + **********************************************************************************************************************/ +#include + +#if defined(HRPWM0) +#include + +/*********************************************************************************************************************** + * MACROS + **********************************************************************************************************************/ +/* 70MHz is considered as the minimum range for 80MHz HRC operation */ +#define XMC_HRPWM_70MHZ_FREQUENCY 70000000U + +/* 100MHz is considered as the maximum range for 80MHz HRC operation */ +#define XMC_HRPWM_100MHZ_FREQUENCY 100000000U + +/* 150MHz is considered as the maximum range for 120MHz HRC operation */ +#define XMC_HRPWM_150MHZ_FREQUENCY 150000000U + +/* 200MHz is considered as the maximum range for 180MHz HRC operation */ +#define XMC_HRPWM_200MHZ_FREQUENCY 200000000U + +#if (UC_SERIES == XMC44) +#define XMC_HRPWM_DELAY_CNT (28800U) /* Provides ~2.8 msec delay @ 220MHz frequency */ + +#elif (UC_SERIES == XMC42) +#define XMC_HRPWM_DELAY_CNT (19200U) /* Provides ~2.8 msec delay @ 150MHz frequency */ + +#else +#define XMC_HRPWM_DELAY_CNT (36000U) /* Provides ~5.3 msec delay @ 150MHz frequency */ +#endif + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ + static void XMC_HRPWM_lDelay(void); + +/*********************************************************************************************************************** + * API IMPLEMENTATION - GENERAL + **********************************************************************************************************************/ + +/* Delay */ +void XMC_HRPWM_lDelay(void) +{ + volatile uint32_t i; + + for (i = 0U; i <= XMC_HRPWM_DELAY_CNT; i++) /* Wait more than 2 microseconds */ + { + __NOP(); + } +} + +/*********************************************************************************************************************** + * API IMPLEMENTATION - HRPWM GLOBAL + **********************************************************************************************************************/ +/* Initializes HRPWM global registers */ +XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm) +{ + uint32_t *csg_memory; + uint32_t ccu_clock; + uint32_t clkc; + XMC_HRPWM_STATUS_t status; + + XMC_ASSERT("XMC_HRPWM_Init:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + status = XMC_HRPWM_STATUS_ERROR; + + /* Apply reset to HRPWM module */ + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0); + + /* Release reset for HRPWM module */ + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0); + + /* Ungate clock */ + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_HRPWM0); + + hrpwm->GLBANA = (uint32_t)0x00004A4E; /* Initialization sequence */ + + hrpwm->HRBSC |= (uint32_t)HRPWM0_HRBSC_HRBE_Msk; /* Enable Bias Generator of HRPWM */ + + /* Update CSG0 memory data */ + csg_memory = (uint32_t *)XMC_HRPWM_CSG0_MEMORY_ADDRESS; + *csg_memory = g_hrpwm_char_data[0]; + /* write csg memory bits[14:11] with 0b1100 */ + *csg_memory &= (uint32_t)(0xFFFF87FF); + *csg_memory |= (uint32_t)(0x00006000); + + /* Update CSG1 trimming data */ + csg_memory = (uint32_t *)XMC_HRPWM_CSG1_MEMORY_ADDRESS; + *csg_memory = g_hrpwm_char_data[1]; + /* write csg memory bits[14:11] with 0b1100 */ + *csg_memory &= (uint32_t)(0xFFFF87FF); + *csg_memory |= (uint32_t)(0x00006000); + + /* Update CSG2 trimming data */ + csg_memory = (uint32_t *)XMC_HRPWM_CSG2_MEMORY_ADDRESS; + *csg_memory = g_hrpwm_char_data[2]; + /* write csg memory bits[14:11] with 0b1100 */ + *csg_memory &= (uint32_t)(0xFFFF87FF); + *csg_memory |= (uint32_t)(0x00006000); + + /* Set CSG units to high speed mode */ + hrpwm->CSGCFG = (uint32_t)(0x0000003F); + + /* Read CCU clock frequency */ + ccu_clock = XMC_SCU_CLOCK_GetCcuClockFrequency(); + + if ((ccu_clock > XMC_HRPWM_70MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_100MHZ_FREQUENCY)) + { + clkc = 3U; /* Clock frequency range 70MHz+ - 100MHz is considered as 80MHz HRC operation */ + } + else if ((ccu_clock > XMC_HRPWM_100MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_150MHZ_FREQUENCY)) + { + clkc = 2U; /* Clock frequency range 100MHz+ - 150MHz is considered as 120MHz HRC operation */ + } + else if ((ccu_clock > XMC_HRPWM_150MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_200MHZ_FREQUENCY)) + { + clkc = 1U; /* Clock frequency range 150MHz+ - 200MHz is considered as 180MHz HRC operation */ + } + else + { + clkc = 0U; /* Invalid frequency for HRC operation: Clock frequency <= 60MHz & Clock frequency > 200MHz */ + } + + if (clkc != 0U) /* Enter the loop only if the clock frequency is valid */ + { + /* Program HRC clock configuration with clock frequency information */ + hrpwm->HRCCFG |= (clkc << HRPWM0_HRCCFG_CLKC_Pos); + + hrpwm->HRCCFG |= (uint32_t)HRPWM0_HRCCFG_HRCPM_Msk; /* Release HR generation from power down mode */ + + XMC_HRPWM_lDelay(); /* As per Initialization sequence */ + + /* Enable global high resolution generation / Force charge pump down */ + hrpwm->GLBANA |= (uint32_t)HRPWM0_GLBANA_GHREN_Msk; + + XMC_HRPWM_lDelay(); + + /* Check High resolution ready bit field */ + if ((hrpwm->HRGHRS & HRPWM0_HRGHRS_HRGR_Msk) == 1U) + { + /* High resolution logic unit is ready */ + status = XMC_HRPWM_STATUS_OK; + } + } + else + { + status = XMC_HRPWM_STATUS_ERROR; /* Clock frequency is invalid */ + } + + return (status); +} + +/* Enable global high resolution generation */ +void XMC_HRPWM_EnableGlobalHR(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_EnableGlobalHR:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + /* Enable global high resolution generation / Force charge pump down */ + hrpwm->GLBANA |= (uint32_t)HRPWM0_GLBANA_GHREN_Msk; + + XMC_HRPWM_lDelay(); /* Elapse startup time */ +} + +/* Disable global high resolution generation */ +void XMC_HRPWM_DisableGlobalHR(XMC_HRPWM_t *const hrpwm) +{ + XMC_ASSERT("XMC_HRPWM_DisableGlobalHR:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + /* Enable global high resolution generation / Force charge pump down */ + hrpwm->GLBANA &= ~((uint32_t)HRPWM0_GLBANA_GHREN_Msk); +} + +/*********************************************************************************************************************** + * API IMPLEMENTATION - HRPWM HRC GLOBAL + **********************************************************************************************************************/ +/* Checks and returns high resolution generation working status */ +XMC_HRPWM_HR_LOGIC_t XMC_HRPWM_GetHRGenReadyStatus(XMC_HRPWM_t *const hrpwm) +{ + XMC_HRPWM_HR_LOGIC_t status; + + XMC_ASSERT("XMC_HRPWM_GetHRGenReadyStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); + + if (hrpwm->HRGHRS) + { + status = XMC_HRPWM_HR_LOGIC_WORKING; + } + else + { + status = XMC_HRPWM_HR_LOGIC_NOT_WORKING; + } + return status; +} + +/*********************************************************************************************************************** + * API IMPLEMENTATION - HRPWM HRC CHANNEL + **********************************************************************************************************************/ +/* Initialize HRPWM HRC channel */ +void XMC_HRPWM_HRC_Init(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_HRC_Init:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + + /* Setting of HRCy mode configuration */ + hrc->GC = config->gc; + + /* Passive level configuration */ + hrc->PL = config->psl; +} + +/* Configure Source selector 0 */ +void XMC_HRPWM_HRC_ConfigSourceSelect0(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_HRPWM_HRC_ConfigSourceSelect0:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + + /* HRC mode config for source selector 0 */ + hrc->GC &= ~((uint32_t)HRPWM0_HRC_GC_HRM0_Msk); + hrc->GC |= ((uint32_t)config->high_res_mode) << HRPWM0_HRC_GC_HRM0_Pos; + + /***************************************************************************** + * HRCy global control selection (HRCyGSEL) + ****************************************************************************/ + reg = 0U; + + if(config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) + { + reg = ((uint32_t)config->cmp_set) << HRPWM0_HRC_GSEL_C0SS_Pos; + reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_S0M_Pos; /* comparator output controls the set config */ + } + + if (config->clear_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) + { + reg |= ((uint32_t)config->cmp_clear) << HRPWM0_HRC_GSEL_C0CS_Pos; + reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_C0M_Pos; /* comparator output controls the clear config */ + } + + reg |= ((uint32_t)config->set_edge_config) << HRPWM0_HRC_GSEL_S0ES_Pos; + reg |= ((uint32_t)config->clear_edge_config) << HRPWM0_HRC_GSEL_C0ES_Pos; + hrc->GSEL &= (uint32_t)0xFFFF0000; + hrc->GSEL |= reg; + + /***************************************************************************** + * HRCy timer selection (HRCyTSEL) + ****************************************************************************/ + reg = (uint32_t)config->timer_sel; + reg |= ((uint32_t)config->src_trap_enable) << HRPWM0_HRC_TSEL_TS0E_Pos; + hrc->TSEL &= (uint32_t)0xFFFEFFF8; + hrc->TSEL |= reg; +} + +/* Configure Source selector 1 */ +void XMC_HRPWM_HRC_ConfigSourceSelect1(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_HRPWM_HRC_ConfigSourceSelect1:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); + + /* HRC mode config for source selector 1 */ + hrc->GC &= ~((uint32_t)HRPWM0_HRC_GC_HRM1_Msk); + hrc->GC |= ((uint32_t)config->high_res_mode) << HRPWM0_HRC_GC_HRM1_Pos; + + /***************************************************************************** + * HRCy global control selection (HRCyGSEL) + ****************************************************************************/ + reg = 0U; + + if(config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) + { + reg = ((uint32_t)config->cmp_set) << HRPWM0_HRC_GSEL_C1SS_Pos; + reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_S1M_Pos; /* comparator output controls the set config*/ + } + + if (config->clear_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) + { + reg |= ((uint32_t)config->cmp_clear) << HRPWM0_HRC_GSEL_C1CS_Pos; + reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_C1M_Pos; /* comparator output controls the clear config */ + } + + reg |= ((uint32_t)config->set_edge_config) << HRPWM0_HRC_GSEL_S1ES_Pos; + reg |= ((uint32_t)config->clear_edge_config) << HRPWM0_HRC_GSEL_C1ES_Pos; + hrc->GSEL &= (uint32_t)0x0000FFFF; + hrc->GSEL |= reg; + + /***************************************************************************** + * HRCy timer selection (HRCyTSEL) + ****************************************************************************/ + reg = (uint32_t)config->timer_sel; + reg |= ((uint32_t)config->src_trap_enable) << HRPWM0_HRC_TSEL_TS1E_Pos; + hrc->TSEL &= (uint32_t)0xFFFDFFC7; + hrc->TSEL |= reg; +} + +/*********************************************************************************************************************** + * API IMPLEMENTATION - HRPWM CSG GLOBAL + **********************************************************************************************************************/ +/* No api's for CSG GLOBAL in xmc_hrpwm.c file */ + +/*********************************************************************************************************************** + * API IMPLEMENTATION - HRPWM CSG SLICE + **********************************************************************************************************************/ +/* Initialization of CSG slice */ +void XMC_HRPWM_CSG_Init(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CONFIG_t *const config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_HRPWM_CSG_Init:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + /* Passive level configuration */ + csg->PLC = config->cmp_config.plc; + + /* DAC Reference values */ + csg->SDSV1 = config->dac_config.dac_dsv1; + csg->DSV2 = config->dac_config.dac_dsv2; + + /* Pulse Swallow value */ + csg->SPC = config->sgen_config.pulse_swallow_val; + + /* Slope generation control (CSGySC) */ + if(config->sgen_config.ctrl_mode != (uint32_t) XMC_HRPWM_CSG_SLOPE_CTRL_MODE_STATIC) + { + /* Dynamic Slope Generation */ + csg->SC = config->sgen_config.sc; + } + else + { + /* Static Mode */ + csg->SC = ((uint32_t)config->sgen_config.static_mode_ist_enable) << HRPWM0_CSG_SC_IST_Pos; + } + reg = ((uint32_t)config->dac_config.start_mode) << HRPWM0_CSG_SC_SWSM_Pos; + csg->SC |= reg; + + /* Comparator Initialization */ + csg->CC = config->cmp_config.cc; + + /* Blanking value */ + csg->BLV = config->cmp_config.blanking_val; +} + +/* Set either CINA or CINB as inverting input of the comparator */ +void XMC_HRPWM_CSG_SetCMPInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CMP_INPUT_t input) +{ + XMC_ASSERT("XMC_HRPWM_CSG_SetCMPInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + if (input == XMC_HRPWM_CSG_CMP_INPUT_CINA) + { + /* Inverting comparator input connected to CINA */ + csg->CC &= ~((uint32_t)HRPWM0_CSG_CC_IMCS_Msk); + } + else + { + /* Inverting comparator input connected to CINB */ + csg->CC |= (uint32_t)HRPWM0_CSG_CC_IMCS_Msk; + } +} + +/* Configure input selection for Blanking function */ +void XMC_HRPWM_CSG_SelBlankingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_HRPWM_CSG_SelBlankingInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + reg = csg->CC; + + if ((reg & HRPWM0_CSG_CC_EBE_Msk) != 0U) /* external blanking trigger enabled? */ + { + reg &= ~((uint32_t)HRPWM0_CSG_CC_IBS_Msk); + reg |= (uint32_t) config->mapped_input; + } + + reg &= ~((uint32_t)HRPWM0_CSG_CC_BLMC_Msk); + reg |= ((uint32_t) config->edge) << HRPWM0_CSG_CC_BLMC_Pos; + + csg->CC = reg; +} + +/* Configure input selection for Clamping */ +void XMC_HRPWM_CSG_SelClampingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_HRPWM_CSG_SelClampingInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + reg = csg->PLC; + + reg &= ~((uint32_t)HRPWM0_CSG_PLC_IPLS_Msk); + reg |= (uint32_t) config->mapped_input; + + reg &= ~((uint32_t)HRPWM0_CSG_PLC_PLCL_Msk); + reg |= ((uint32_t) config->level) << HRPWM0_CSG_PLC_PLCL_Pos; + + csg->PLC = reg; +} + +/* Configure input selection to start slope generation function */ +void XMC_HRPWM_CSG_StartSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_CSG_StartSlopeGenConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STRIS_Msk); + csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STRIS_Pos; + csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STRES_Msk); + csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STRES_Pos; +} + +/* Configure input selection to stop slope generation function */ +void XMC_HRPWM_CSG_StopSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_CSG_StopSlopeGenConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STPIS_Msk); + csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STPIS_Pos; + csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STPES_Msk); + csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STPES_Pos; +} + +/* Configure input selection for triggering DAC conversion */ +void XMC_HRPWM_CSG_TriggerDACConvConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_CSG_TriggerDACConvConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_TRGIS_Msk); + csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_TRGIS_Pos; + csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_TRGES_Msk); + csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_TRGES_Pos; +} + +/* Configure input selection for triggering shadow transfer */ +void XMC_HRPWM_CSG_TriggerShadowXferConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_CSG_TriggerShadowXferConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STIS_Msk); + csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STIS_Pos; + csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STES_Msk); + csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STES_Pos; +} + +/* Configure input selection to trigger a switch in DAC reference value. This is only applicable to DAC in static mode */ +void XMC_HRPWM_CSG_DACRefValSwitchingConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_HRPWM_CSG_DACRefValSwitchingConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_SVIS_Msk); + csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_SVIS_Pos; + csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_SVLS_Msk); + csg->IES |= ((uint32_t)config->level) << HRPWM0_CSG_IES_SVLS_Pos; +} + +/* Configure input selection for clock selection used in slope generation */ +void XMC_HRPWM_CSG_SelSlopeGenClkInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CLK_INPUT_t input_clk) +{ + XMC_ASSERT("XMC_HRPWM_CSG_SelSlopeGenClkInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_SCS_Msk); + csg->DCI |= ((uint32_t)input_clk) << HRPWM0_CSG0_DCI_SCS_Pos; +} + +/* Set the service request interrupt node */ +void XMC_HRPWM_CSG_SetSRNode(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_IRQ_ID_t event, + const XMC_HRPWM_CSG_IRQ_SR_LINE_t sr) +{ + XMC_ASSERT("XMC_HRPWM_CSG_SetSRNode:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); + + switch (event) + { + case (XMC_HRPWM_CSG_IRQ_ID_VLS1): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_VLS1S_Msk); + csg->SRS |= (uint32_t)sr; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_VLS2): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_VLS2S_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_VLS2S_Pos; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_TRGS): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_TRLS_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_TRLS_Pos; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_STRS): + case (XMC_HRPWM_CSG_IRQ_ID_STPS): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_SSLS_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_SSLS_Pos; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_STD): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_STLS_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_STLS_Pos; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_CRSE): + case (XMC_HRPWM_CSG_IRQ_ID_CFSE): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_CRFLS_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_CRFLS_Pos; + break; + + case (XMC_HRPWM_CSG_IRQ_ID_CSEE): + csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_CSLS_Msk); + csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_CSLS_Pos; + break; + + default: + break; + } +} + +#endif /* #if defined(HRPWM0) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_i2c.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_i2c.c new file mode 100644 index 00000000..7d9e3802 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_i2c.c @@ -0,0 +1,402 @@ +/** + * @file xmc_i2c.c + * @date 2015-10-02 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + - Modified XMC_I2C_CH_Stop() API for not setting to IDLE the channel if it is busy
+ * + * 2015-06-20: + * - Removed GetDriverVersion API
+ * + * 2015-08-14: + * - updated the XMC_I2C_CH_SetBaudrate API to support dynamic change from 400K to low frequencies
+ * + * 2015-09-01: + * - Modified XMC_I2C_CH_EnableEvent() and XMC_I2C_CH_DisableEvent() for supporting multiple events configuration
+ * + * 2015-10-02: + * - Fixed 10bit addressing + * + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ +#include + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ +#define XMC_I2C_7BIT_ADDR_Pos (8U) /**< 7-bit address position */ +#define TRANSMISSION_MODE (3U) /**< The shift control signal is considered active + without referring to the actual signal level. Data + frame transfer is possible after each edge of the signal.*/ +#define WORDLENGTH (7U) /**< Word length */ +#define SET_TDV (1U) /**< Transmission data valid */ +#define XMC_I2C_10BIT_ADDR_MASK (0x7C00U) /**< Address mask for 10-bit mode */ + +/********************************************************************************************************************* + * ENUMS + *********************************************************************************************************************/ + +typedef enum XMC_I2C_CH_TDF +{ + XMC_I2C_CH_TDF_MASTER_SEND = 0U, + XMC_I2C_CH_TDF_SLAVE_SEND = (uint32_t)1U << 8U, + XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK = (uint32_t)2U << 8U, + XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK = (uint32_t)3U << 8U, + XMC_I2C_CH_TDF_MASTER_START = (uint32_t)4U << 8U, + XMC_I2C_CH_TDF_MASTER_RESTART = (uint32_t)5U << 8U, + XMC_I2C_CH_TDF_MASTER_STOP = (uint32_t)6U << 8U +} XMC_I2C_CH_TDF_t; + +typedef enum XMC_I2C_CH_MAX_SPEED +{ + XMC_I2C_CH_MAX_SPEED_STANDARD = 100000U, + XMC_I2C_CH_MAX_SPEED_FAST = 400000U +} XMC_I2C_CH_MAX_SPEED_t; + +typedef enum XMC_I2C_CH_CLOCK_OVERSAMPLING +{ + XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD = 10U, + XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST = 25U +} XMC_I2C_CH_CLOCK_OVERSAMPLINGS_t; + +/********************************************************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ +/* Initializes the USIC channel by setting the data format, slave address, baudrate, transfer buffer */ +void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config) +{ + XMC_USIC_CH_Enable(channel); + + /* Data format configuration */ + channel->SCTR = ((uint32_t)TRANSMISSION_MODE << (uint32_t)USIC_CH_SCTR_TRM_Pos) | /* Transmision mode */ + ((uint32_t)WORDLENGTH << (uint32_t)USIC_CH_SCTR_WLE_Pos) | /* 8 data bits */ + USIC_CH_SCTR_FLE_Msk | /* unlimited data flow */ + USIC_CH_SCTR_SDIR_Msk | /* MSB shifted first */ + USIC_CH_SCTR_PDL_Msk; /* Passive Data Level */ + + XMC_I2C_CH_SetSlaveAddress(channel, config->address); + (void)XMC_I2C_CH_SetBaudrate(channel, config->baudrate); + + /* Enable transfer buffer */ + channel->TCSR = ((uint32_t)SET_TDV << (uint32_t)USIC_CH_TCSR_TDEN_Pos) | USIC_CH_TCSR_TDSSM_Msk; + + /* Clear status flags */ + channel->PSCR = 0xFFFFFFFFU; + + /* Disable parity generation */ + channel->CCR = 0x0U; +} +/* Sets the slave address */ +void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t address) +{ + if ((address & XMC_I2C_10BIT_ADDR_MASK) == XMC_I2C_10BIT_ADDR_GROUP) + { + channel->PCR_IICMode = (address & 0xffU) | ((address << 1) & 0xfe00U); + } + else + { + channel->PCR_IICMode = ((uint32_t)address) << XMC_I2C_7BIT_ADDR_Pos; + } +} +/* Read the slave address */ +uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel) +{ + uint32_t address = channel->PCR_IICMode & (uint32_t)USIC_CH_PCR_IICMode_SLAD_Msk; + + if ((address & 0xffU) == 0U) + { + address = address >> XMC_I2C_7BIT_ADDR_Pos; + } + else + { + address = (address & 0xffU) | ((address >> 1) & 0x0300U); + } + + return (uint16_t)address; +} +/* Sets the baudrate and oversampling based on standard speed or fast speed */ +XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate) +{ + XMC_I2C_CH_STATUS_t status; + + status = XMC_I2C_CH_STATUS_ERROR; + + if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_STANDARD) + { + channel->PCR_IICMode &= (uint32_t)~USIC_CH_PCR_IICMode_STIM_Msk; + if (XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD) == XMC_USIC_CH_STATUS_OK) + { + status = XMC_I2C_CH_STATUS_OK; + } + } + else if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_FAST) + { + channel->PCR_IICMode |= (uint32_t)USIC_CH_PCR_IICMode_STIM_Msk; + if (XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST) == XMC_USIC_CH_STATUS_OK) + { + status = XMC_I2C_CH_STATUS_OK; + } + } + else + { + status = XMC_I2C_CH_STATUS_ERROR; + } + + return status; +} +/* Sends master start condition along with read/write command to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command) +{ + uint32_t temp; + + temp = addr | (uint32_t)XMC_I2C_CH_TDF_MASTER_START; + if (command == XMC_I2C_CH_CMD_READ) + { + temp |= 0x1U; + } + + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = temp; + } + else + { + channel->IN[0U] = temp; + } +} +/* Sends master repeated start condition along with read/write command to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterRepeatedStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command) +{ + uint32_t tmp; + tmp = addr | (uint32_t)XMC_I2C_CH_TDF_MASTER_RESTART; + if (command == XMC_I2C_CH_CMD_READ) + { + tmp |= 0x1U; + } + + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = tmp; + } + else + { + channel->IN[0U] = tmp; + } +} + +/* Sends master stop command to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterStop(XMC_USIC_CH_t *const channel) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_STOP; + } + else + { + channel->IN[0U] = (uint32_t)XMC_I2C_CH_TDF_MASTER_STOP; + } +} + +/* Sends master send command along with data to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterTransmit(XMC_USIC_CH_t *const channel, const uint8_t data) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_SEND | data; + } + else + { + channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_SEND | data; + } +} + +/* Sends slave send command along with data to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_SlaveTransmit(XMC_USIC_CH_t *const channel, const uint8_t data) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_SLAVE_SEND | data; + } + else + { + channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_SLAVE_SEND | data; + } +} + +/* Sends master receive ack command to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterReceiveAck(XMC_USIC_CH_t *const channel) +{ +/* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK; + } + else + { + channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK; + } +} + +/* Sends master receive nack command to IN/TBUF register based on FIFO/non-FIFO modes. */ +void XMC_I2C_CH_MasterReceiveNack(XMC_USIC_CH_t *const channel) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + /* check TDV, wait until TBUF is ready */ + } + + /* clear PSR_TBIF */ + XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK; + } + else + { + channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK; + } +} + +/* Reads the data from RBUF if FIFO size is 0 otherwise from OUTR. */ +uint8_t XMC_I2C_CH_GetReceivedData(const XMC_USIC_CH_t *const channel) +{ + uint8_t retval; + + /* Check FIFO size */ + if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U) + { + retval = (uint8_t)channel->RBUF; + } + else + { + retval = (uint8_t)channel->OUTR; + } + + return retval; +} + +/* Sets the operating mode of USIC to IDLE */ +XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel) +{ + XMC_I2C_CH_STATUS_t status = XMC_I2C_CH_STATUS_OK; + + if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) + { + status = XMC_I2C_CH_STATUS_BUSY; + } + else + { + /* USIC channel in IDLE mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE); + } + return status; +} + +void XMC_I2C_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR |= (event&0x1fc00U); + channel->PCR_IICMode |= ((event) & 0x41fc0000U); +} + +void XMC_I2C_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR &= (uint32_t)~(event&0x1fc00U); + channel->PCR_IICMode &= (uint32_t)~((event) & 0x41fc0000U); +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_i2s.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_i2s.c new file mode 100644 index 00000000..332195e3 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_i2s.c @@ -0,0 +1,268 @@ +/** + * @file xmc_i2s.c + * @date 2015-06-30 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-08-21: + * - Initial
+ * + * 2015-09-01: + * - Modified XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent() for supporting multiple events configuration
+ * + * 2015-09-14: + * - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length. + * - Removed parity configuration
+ * + * 2015-09-28: + * - Fixed bugs in the XMC_I2S_CH_Init() and in the ASSERTs
+ * + * 2015-11-04: + * - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_I2S_CH_Transmit() API
+ * + * 2016-06-30: + * - Modified XMC_I2S_CH_Init: + * + change default passive level to 0 + * + Call XMC_I2S_CH_SetSystemWordLength() to set the system frame length equal to the frame length. + * - Modified XMC_I2S_CH_SetBaudrate: + * + Optional Master clock output signal generated with a fixed phase relation to SCLK. + * + * @endcond + * + */ +/** + * + * @brief I2S driver for XMC microcontroller family + * + */ +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include +#include + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +/* To take into account the SCLK divider by 2 and the PPPEN divider (see Divider Mode Counter figure in RM) */ +#define XMC_I2S_CH_OVERSAMPLING (4UL) + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/* Initializes the selected I2S channel with the config structure. */ +void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(config->data_delayed_sclk_periods > 0U) && + (config->data_delayed_sclk_periods < config->frame_length)); + XMC_USIC_CH_Enable(channel); + + if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER) + { + /* Configure baud rate */ + (void)XMC_I2S_CH_SetBaudrate(channel, config->baudrate); + } + /* Configuration of USIC Shift Control */ + /* Transmission Mode (TRM) = 1 */ + channel->SCTR = (uint32_t)(0x3UL << USIC_CH_SCTR_TRM_Pos) | + (uint32_t)((config->frame_length -1U) << USIC_CH_SCTR_FLE_Pos) | + (uint32_t)((config->data_bits - 1U) << USIC_CH_SCTR_WLE_Pos) | + USIC_CH_SCTR_SDIR_Msk; + + /* Configuration of USIC Transmit Control/Status Register */ + /* TBUF Data Enable (TDEN) = 1 */ + /* TBUF Data Single Shot Mode (TDSSM) = 1 */ + /* WA mode enabled(WAMD) = 1 */ + channel->TCSR = (uint32_t)((channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk | + USIC_CH_TCSR_SELMD_Msk | + USIC_CH_TCSR_FLEMD_Msk | + USIC_CH_TCSR_HPCMD_Msk))) | + USIC_CH_TCSR_WAMD_Msk | + (0x01UL << USIC_CH_TCSR_TDEN_Pos) | + USIC_CH_TCSR_TDSSM_Msk); + + if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER) + { + /* Configuration of Protocol Control Register */ + channel->PCR_IISMode = (uint32_t)USIC_CH_PCR_IISMode_WAGEN_Msk; + } + + /* Configuration of Protocol Control Register */ + channel->PCR_IISMode |= (uint32_t)(USIC_CH_PCR_IISMode_DTEN_Msk | + (uint32_t)config->wa_inversion) | + ((uint32_t)((uint32_t)config->data_delayed_sclk_periods - 1U) << USIC_CH_PCR_IISMode_TDEL_Pos); + + XMC_I2S_CH_SetSystemWordLength(channel, config->frame_length); + + /* Clear protocol status */ + channel->PSCR = 0xFFFFFFFFUL; +} + + +XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate) +{ + XMC_I2S_CH_STATUS_t status; + + status = XMC_I2S_CH_STATUS_ERROR; + + if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U)) + { + if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_I2S_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK) + { + channel->BRG = (uint32_t)((channel->BRG & ~(USIC_CH_BRG_CTQSEL_Msk)) | + (0x2UL << USIC_CH_BRG_CTQSEL_Pos)) | + USIC_CH_BRG_PPPEN_Msk; + + status = XMC_I2S_CH_STATUS_OK; + } + + } + return status; +} + +void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length) +{ + uint32_t sclk_cycles_system_word_length_temp; + uint8_t dctq_temp; + uint8_t pctq_temp; + uint8_t dctq = 1U; + uint8_t pctq = 1U; + uint8_t best_error = 64U; + uint8_t error; + XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(sclk_cycles_system_word_length > 0U) && (sclk_cycles_system_word_length < 65U)); + + + for (dctq_temp =1U; dctq_temp < 33U ; dctq_temp++) + { + for (pctq_temp =1U; pctq_temp < 5U ; pctq_temp++) + { + sclk_cycles_system_word_length_temp = ((uint32_t)dctq_temp) * ((uint32_t)pctq_temp); + if(sclk_cycles_system_word_length_temp == sclk_cycles_system_word_length) + { + dctq = dctq_temp; + pctq = pctq_temp; + break; + } + if (sclk_cycles_system_word_length_temp > sclk_cycles_system_word_length) + { + error = (uint8_t)(sclk_cycles_system_word_length_temp - sclk_cycles_system_word_length); + } + else + { + error = (uint8_t)(sclk_cycles_system_word_length - sclk_cycles_system_word_length_temp); + } + + if(error < best_error) + { + best_error = error; + dctq = dctq_temp; + pctq = pctq_temp; + } + } + } + channel->BRG = (uint32_t)((channel->BRG & ~((uint32_t)(USIC_CH_BRG_DCTQ_Msk | + USIC_CH_BRG_PCTQ_Msk))) | + (uint32_t)((uint32_t)((uint32_t)((uint32_t)dctq- 1U) << USIC_CH_BRG_DCTQ_Pos) | + (uint32_t)((uint32_t)((uint32_t)pctq- 1U) << USIC_CH_BRG_PCTQ_Pos))); +} + +/* Puts the data into FIFO if FIFO mode is enabled or else into standard buffers, by setting the proper mode. */ +void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNEL_t channel_number) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) + { + } + + XMC_I2S_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[(uint32_t)channel_number << 4] = data; + } + else + { + channel->IN[(uint32_t)channel_number << 4] = data; + } +} + +/* Reads the data from the buffers based on the FIFO mode selection. */ +uint16_t XMC_I2S_CH_GetReceivedData(XMC_USIC_CH_t *const channel) +{ + uint16_t retval; + + /* Check FIFO size */ + if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U) + { + retval = (uint16_t)channel->RBUF; + } + else + { + retval = (uint16_t)channel->OUTR; + } + + return retval; +} + +XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel) +{ + XMC_I2S_CH_STATUS_t status = XMC_I2S_CH_STATUS_OK; + + if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) + { + status = XMC_I2S_CH_STATUS_BUSY; + } + else + { + /* USIC channel in IDLE mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE); + } + + return status; +} + +void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR |= (event&0x1fc00U); + channel->PCR_IISMode |= ((event >> 2U) & 0x8070U); +} + +void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR &= (uint32_t)~(event&0x1fc00U); + channel->PCR_IISMode &= (uint32_t)~((event >> 2U) & 0x8070U); +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ledts.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ledts.c new file mode 100644 index 00000000..72ac5cd6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_ledts.c @@ -0,0 +1,383 @@ +/** + * @file xmc_ledts.c + * @date 2017-02-25 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * - New API added: XMC_LEDTS_SetActivePADNo()
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2017-02-25: + * - XMC_LEDTS_InitGlobal() fixed compilation warnings + * + * Detailed description of file:
+ * APIs for the functional blocks of LEDTS have been defined:
+ * -- GLOBAL (APIs prefixed with LEDTS_GLOBAL_)
+ * -- Clock configuration, Function/Event configuration, Interrupt configuration + * + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +#if defined(LEDTS0) +#include "xmc_scu.h" + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_LEDTS_CLOCK_NOT_RUNNING 0U + +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * GLOBAL DATA + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * LOCAL/UTILITY ROUTINES + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/** + * Initialization of global register + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitGlobal(XMC_LEDTS_t *const ledts, const XMC_LEDTS_GLOBAL_CONFIG_t *config) +{ + XMC_ASSERT("XMC_LEDTS_InitGlobal:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + XMC_ASSERT("XMC_LEDTS_InitGlobal:Null Pointer", (config != (XMC_LEDTS_GLOBAL_CONFIG_t *)NULL)); + + if (ledts == XMC_LEDTS0) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS0); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS0); +#endif + } +#if defined(LEDTS1) + else if (ledts == XMC_LEDTS1) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS1); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS1); +#endif + } +#endif +#if defined(LEDTS2) + else if (ledts == XMC_LEDTS2) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS2); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS2); +#endif + } +#endif + else + { + XMC_ASSERT("XMC_LEDTS_InitGlobal:Invalid Module Pointer", 0); + } + + if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + { + return XMC_LEDTS_STATUS_RUNNING; + } + + ledts->GLOBCTL = config->globctl; + + return XMC_LEDTS_STATUS_SUCCESS; +} + +/** + * Initialization of registers for LED-driving function + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitLED(XMC_LEDTS_t *const ledts, const XMC_LEDTS_LED_CONFIG_t *config) +{ + XMC_ASSERT("XMC_LEDTS_LED_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + XMC_ASSERT("XMC_LEDTS_LED_Init:Null Pointer", (config != (XMC_LEDTS_LED_CONFIG_t *)NULL)); + + if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + { + return XMC_LEDTS_STATUS_RUNNING; + } + + ledts->FNCTL &= ~(LEDTS_FNCTL_COLLEV_Msk | LEDTS_FNCTL_NR_LEDCOL_Msk); + ledts->FNCTL |= (config->fnctl); + + /* Enable LED function */ + ledts->GLOBCTL |= LEDTS_GLOBCTL_LD_EN_Msk; + + return XMC_LEDTS_STATUS_SUCCESS; +} + +/** + * Initialization of registers for basic Touch-Sense control function + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSBasic(XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_BASIC_t *config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_LEDTS_TS_Basic_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + XMC_ASSERT("XMC_LEDTS_TS_Basic_Init:Null Pointer", (config != (XMC_LEDTS_TS_CONFIG_BASIC_t *)NULL)); + + if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + { + return XMC_LEDTS_STATUS_RUNNING; + } + + reg = ~(LEDTS_FNCTL_ACCCNT_Msk | LEDTS_FNCTL_TSCCMP_Msk | LEDTS_FNCTL_TSCTRR_Msk | LEDTS_FNCTL_TSCTRSAT_Msk | + LEDTS_FNCTL_NR_TSIN_Msk); + ledts->FNCTL &= (reg); + ledts->FNCTL |= (config->fnctl); + + /* Enable TS function */ + ledts->GLOBCTL |= LEDTS_GLOBCTL_TS_EN_Msk; + + return XMC_LEDTS_STATUS_SUCCESS; +} + +/** + * Initialization of registers for advanced Touch-Sense control function + */ +XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSAdvanced (XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_ADVANCED_t *config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_LEDTS_TS_Advanced_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + XMC_ASSERT("XMC_LEDTS_TS_Advanced_Init:Null Pointer", (config != (XMC_LEDTS_TS_CONFIG_ADVANCED_t *)NULL)); + + if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + { + return XMC_LEDTS_STATUS_RUNNING; + } + + reg = ~(LEDTS_GLOBCTL_MASKVAL_Msk | LEDTS_GLOBCTL_FENVAL_Msk); + ledts->GLOBCTL &= (reg); + ledts->GLOBCTL |= (config->globctl); + + reg = ~(LEDTS_FNCTL_PADT_Msk | LEDTS_FNCTL_PADTSW_Msk | LEDTS_FNCTL_EPULL_Msk | LEDTS_FNCTL_TSOEXT_Msk); + ledts->FNCTL &= (reg); + ledts->FNCTL |= (config->fnctl); + + return XMC_LEDTS_STATUS_SUCCESS; +} + +/** + * Starts LEDTS-counter + */ +void XMC_LEDTS_StartCounter(XMC_LEDTS_t *const ledts, const uint16_t prescaler) +{ + XMC_ASSERT("XMC_LEDTS_Start_Counter:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->GLOBCTL |= prescaler<<16U; +} + +/** + * Stops LEDTS-counter + */ +void XMC_LEDTS_StopCounter(XMC_LEDTS_t *const ledts) +{ + XMC_ASSERT("XMC_LEDTS_Stop_Counter:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->GLOBCTL &= 0x0000FFFF; +} + +/** + * Reads time interrupt flags + */ +uint32_t XMC_LEDTS_ReadInterruptFlag(XMC_LEDTS_t *const ledts) +{ + XMC_ASSERT("XMC_LEDTS_ReadInterruptFlag:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + return (ledts->EVFR & 0xF); +} + +/** + * Set the active pad number + */ +void XMC_LEDTS_SetActivePADNo(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t pad_num) +{ + uint32_t reg; + + XMC_ASSERT("XMC_LEDTS_SetActivePADNo:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + reg = ledts->FNCTL; + reg &= ~(LEDTS_FNCTL_PADT_Msk); + reg |= (uint32_t)pad_num; + ledts->FNCTL = reg; +} + +/** + * Clears interrupt indication flags + */ +void XMC_LEDTS_ClearInterruptFlag(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask) +{ + XMC_ASSERT("XMC_LEDTS_ClearInterruptFlag:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->EVFR = (interrupt_mask << LEDTS_EVFR_CTSF_Pos); +} + +/** + * Programming of registers to output pattern on an LED column in LED matrix + */ +void XMC_LEDTS_SetLEDLinePattern(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t pattern) +{ + uint32_t reg; + uint8_t reg_index = ((uint8_t)column) >> 2; + uint8_t bit_shift_count = ((uint8_t)column & 0x03) * 8; + + XMC_ASSERT("XMC_LEDTS_Set_LED_Line_Pattern:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + reg = ledts->LINE[reg_index]; + reg &= (~(0xff << bit_shift_count)); + reg |= pattern << bit_shift_count; + ledts->LINE[reg_index] = reg; + +} + +/** + * Programming of registers to adjust brightness of an LED column in LED matrix + */ +void XMC_LEDTS_SetColumnBrightness(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t brightness) +{ + uint32_t reg; + uint8_t reg_index = ((uint8_t)column) >> 2; + uint8_t bit_shift_count = ((uint8_t)column & 0x03) * 8; + + XMC_ASSERT("XMC_LEDTS_Set_Column_Brightness:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + reg = ledts->LDCMP[reg_index]; + reg &= (~(0xff << bit_shift_count)); + reg |= brightness << bit_shift_count; + ledts->LDCMP[reg_index] = reg; +} + +/** + * Programming of registers to set common oscillation window size for touch-sense inputs + */ +void XMC_LEDTS_SetCommonOscillationWindow(XMC_LEDTS_t *const ledts, const uint8_t common_size) +{ + uint32_t reg; + + XMC_ASSERT("XMC_LEDTS_Set_Common_Oscillation_Window:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + reg = ledts->LDCMP[1]; + reg &= ~LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk; + reg |= (common_size << LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos); + ledts->LDCMP[1] = reg; +} + +/** + * Checking the previous active function or LED column status + */ +uint32_t XMC_LEDTS_ReadFNCOL(XMC_LEDTS_t *const ledts) +{ + uint32_t fncol_read; + + XMC_ASSERT("XMC_LEDTS_Read_FNCOL:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + fncol_read = ledts->FNCTL & LEDTS_FNCTL_FNCOL_Msk; + fncol_read >>= LEDTS_FNCTL_FNCOL_Pos; + + return fncol_read; +} + +/** + * Set the number of LED column Enabled + */ +void XMC_LEDTS_SetNumOfLEDColumns(XMC_LEDTS_t *const ledts, uint8_t count) +{ + + XMC_ASSERT("XMC_LEDTS_SetNumOfLEDColumns:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + ledts->FNCTL &= ~(LEDTS_FNCTL_NR_LEDCOL_Msk); + ledts->FNCTL |= (count << LEDTS_FNCTL_NR_LEDCOL_Pos); +} + +/** + * Reading recorded number of oscillation counts + */ +uint16_t XMC_LEDTS_ReadTSVAL(XMC_LEDTS_t *const ledts) +{ + uint16_t no_of_oscillations; + + XMC_ASSERT("XMC_LEDTS_Read_TSVAL:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + no_of_oscillations = (ledts->TSVAL & 0xFFFF); + + return no_of_oscillations; +} + +/** + * Programming of registers to adjust the size of oscillation window + */ +void XMC_LEDTS_SetOscillationWindow(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t touchpad, const uint8_t size) +{ + uint32_t reg; + uint8_t reg_index = ((uint8_t)touchpad) >> 2; + uint8_t bit_shift_count = ((uint8_t)touchpad & 0x03) * 8; + + XMC_ASSERT("XMC_LEDTS_Set_Oscillation_Window:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); + + reg = ledts->TSCMP[reg_index]; + reg &= (~(0xff << bit_shift_count)); + reg |= size << bit_shift_count; + ledts->TSCMP[reg_index] = reg; +} + +#endif /* LEDTS0 */ + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_posif.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_posif.c new file mode 100644 index 00000000..a8b50a22 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_posif.c @@ -0,0 +1,275 @@ +/** + * @file xmc_posif.c + * @date 2017-02-25 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-18: + * - Initial version + * + * 2015-02-20: + * - Driver description added
+ * + * 2015-04-30: + * - XMC_POSIF_Enable and XMC_POSIF_Disable APIs updated for POSIF1 peripheral check
+ * + * 2015-06-19: + * - Removed GetDriverVersion API
+ * + * 2017-02-25: + * - XMC_POSIF_Enable() and XMC_POSIF_Disable() fixed compilation warnings + * + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +/* POSIF is not available on XMC1100 and XMC1200 */ +#if defined(POSIF0) +#include + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_POSIF_PCONF_INSEL_Msk (0x3fUL << POSIF_PCONF_INSEL0_Pos) /*< Mask for input pins selection */ +#define XMC_POSIF_INSEL_MAX (4U) /*< Maximum possible input selector */ + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ +#ifdef XMC_ASSERT_ENABLE +__STATIC_INLINE bool XMC_POSIF_IsPeripheralValid(const XMC_POSIF_t *const peripheral) +{ + bool tmp; + + tmp = (peripheral == POSIF0); +#if defined(POSIF1) + tmp |= (peripheral == POSIF1); +#endif + + return tmp; +} +#endif +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/* API to enable the POSIF module */ +void XMC_POSIF_Enable(XMC_POSIF_t *const peripheral) +{ +#if UC_FAMILY == XMC4 + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU); +#endif + + if (peripheral == POSIF0) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0); +#endif + } +#if defined(POSIF1) + else if (peripheral == POSIF1) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1); +#endif + } +#endif + else + { + XMC_ASSERT("XMC_POSIF_Disable:Invalid module pointer", 0); + } +} + +/* API to disable the POSIF module */ +void XMC_POSIF_Disable(XMC_POSIF_t *const peripheral) +{ + if (peripheral == POSIF0) + { +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0); +#endif + } +#if defined(POSIF1) + else if (peripheral == POSIF1) + { +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1); +#endif + } +#endif + else + { + XMC_ASSERT("XMC_POSIF_Disable:Invalid module pointer", 0); + } +} + +/* API to initialize POSIF global resources */ +void XMC_POSIF_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_CONFIG_t *const config) +{ + XMC_ASSERT("XMC_POSIF_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_Init:NULL Pointer", (config != (XMC_POSIF_CONFIG_t *)NULL) ); + + /* Enable the POSIF module */ + XMC_POSIF_Enable(peripheral); + + /* Stop POSIF */ + XMC_POSIF_Stop(peripheral); + + /* Program the operational mode, input selectors and debounce filter */ + peripheral->PCONF = config->pconf; +} + +/* API to initialize hall sensor interface */ +XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_HSC_CONFIG_t * const config) +{ + XMC_POSIF_STATUS_t retval; + + XMC_ASSERT("XMC_POSIF_HSC_Init:Invalid module pointer\n", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_HSC_Init:NULL Pointer\n", (config != (XMC_POSIF_HSC_CONFIG_t *)NULL) ); + + if (XMC_POSIF_MODE_HALL_SENSOR == (XMC_POSIF_MODE_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk) ) + { + peripheral->PCONF |= config->hall_config; + retval = XMC_POSIF_STATUS_OK; + } + else + { + retval = XMC_POSIF_STATUS_ERROR; + } + return retval; +} + +/* API to initialize quadrature decoder interface */ +XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_QD_CONFIG_t * const config) +{ + uint8_t reg; + XMC_POSIF_STATUS_t retval; + + XMC_ASSERT("XMC_POSIF_QD_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_QD_Init:NULL Pointer", (config != (XMC_POSIF_QD_CONFIG_t *)NULL) ); + + reg = (uint8_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk); + if (((uint32_t)XMC_POSIF_MODE_QD == reg) || ((uint32_t)XMC_POSIF_MODE_MCM_QD == reg)) + { + /* Program the quadrature mode */ + peripheral->PCONF |= (uint32_t)(config->mode) << POSIF_PCONF_QDCM_Pos; + peripheral->QDC = config->qdc; + retval = XMC_POSIF_STATUS_OK; + } + else + { + retval = XMC_POSIF_STATUS_ERROR; + } + + return retval; +} + +/* API to initialize multi-channel mode. + * This is used in Hall mode, standalone multi-channel mode and quadrature with multi-channel mode + */ +XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_MCM_CONFIG_t * const config) +{ + XMC_POSIF_STATUS_t retval; + + XMC_ASSERT("XMC_POSIF_MCM_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_MCM_Init:NULL Pointer", (config != (XMC_POSIF_MCM_CONFIG_t *)NULL) ); + + if ((XMC_POSIF_MODE_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk) != XMC_POSIF_MODE_QD) + { + peripheral->PCONF |= config->mcm_config; + retval = XMC_POSIF_STATUS_OK; + } + else + { + retval = XMC_POSIF_STATUS_ERROR; + } + return retval; +} + +/* API to configure input source */ +void XMC_POSIF_SelectInputSource (XMC_POSIF_t *const peripheral, const XMC_POSIF_INPUT_PORT_t input0, + const XMC_POSIF_INPUT_PORT_t input1, const XMC_POSIF_INPUT_PORT_t input2) +{ + uint32_t reg; + XMC_ASSERT("XMC_POSIF_SelectInputSource:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input0", (input0 < XMC_POSIF_INSEL_MAX)); + XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input1", (input1 < XMC_POSIF_INSEL_MAX)); + XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input2", (input2 < XMC_POSIF_INSEL_MAX)); + + reg = (uint32_t)((((uint32_t)input0 << POSIF_PCONF_INSEL0_Pos) & (uint32_t)POSIF_PCONF_INSEL0_Msk) | + (((uint32_t)input1 << POSIF_PCONF_INSEL1_Pos) & (uint32_t)POSIF_PCONF_INSEL1_Msk) | + (((uint32_t)input2 << POSIF_PCONF_INSEL2_Pos) & (uint32_t)POSIF_PCONF_INSEL2_Msk)); + peripheral->PCONF = ((peripheral->PCONF & ~(uint32_t)XMC_POSIF_PCONF_INSEL_Msk) | reg); +} + +/* API to select an interrupt node */ +void XMC_POSIF_SetInterruptNode(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event, const XMC_POSIF_SR_ID_t sr) +{ + uint32_t reg; + + XMC_ASSERT("XMC_POSIF_SetInterruptNode:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); + XMC_ASSERT("XMC_POSIF_SetInterruptNode:Wrong IRQ event", (event <= XMC_POSIF_IRQ_EVENT_PCLK) ); + XMC_ASSERT("XMC_POSIF_SetInterruptNode:Wrong SR ID", (sr <= XMC_POSIF_SR_ID_1) ); + + reg = peripheral->PFLGE; + reg &= ~((uint32_t)1 << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos)); + reg |= (uint32_t)sr << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos); + peripheral->PFLGE = reg; +} +#endif /* #if defined(POSIF0) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_rtc.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_rtc.c new file mode 100644 index 00000000..6a115952 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_rtc.c @@ -0,0 +1,298 @@ +/** + * @file xmc_rtc.c + * @date 2015-05-19 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed GetDriverVersion API + * + * 2016-05-19: + * - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat() + * + * @endcond + * + */ + +/** + * + * @brief RTC driver for XMC microcontroller family. + * + */ + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ + +#include "xmc_scu.h" +#include "xmc_rtc.h" + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ + +#define XMC_RTC_MAXSECONDS (59U) /**< RTC time : Maximum seconds */ +#define XMC_RTC_MAXMINUTES (59U) /**< RTC time : Maximum minutes */ +#define XMC_RTC_MAXHOURS (23U) /**< RTC time : Maximum hours */ +#define XMC_RTC_MAXDAYS (31U) /**< RTC time : Maximum days */ +#define XMC_RTC_MAXDAYSOFWEEK (7U) /**< RTC time : Maximum days of week */ +#define XMC_RTC_MAXMONTH (12U) /**< RTC time : Maximum month */ +#define XMC_RTC_MAXYEAR (0xFFFFU) /**< RTC time : Maximum year */ +#define XMC_RTC_MAXPRESCALER (0xFFFFU) /**< RTC time : Maximum prescaler */ +#define XMC_RTC_YEAR_OFFSET (1900U) /**< RTC year offset : Year offset */ + +#if (UC_FAMILY == XMC4) +#define XMC_RTC_INIT_SEQUENCE (1U) +#endif +#if (UC_FAMILY == XMC1) +#define XMC_RTC_INIT_SEQUENCE (0U) +#endif + +/********************************************************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ + +/* + * Enables RTC peripheral to start counting time + */ +void XMC_RTC_Start(void) +{ + while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->CTR |= (uint32_t)RTC_CTR_ENB_Msk; +} + +/* + * Disables RTC peripheral to start counting time + */ +void XMC_RTC_Stop(void) +{ + while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->CTR &= ~(uint32_t)RTC_CTR_ENB_Msk; +} + +/* + * Sets the RTC module prescaler value + */ +void XMC_RTC_SetPrescaler(uint16_t prescaler) +{ + XMC_ASSERT("XMC_RTC_SetPrescaler:Wrong prescaler value", (prescaler < XMC_RTC_MAXPRESCALER)); + + while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->CTR = (RTC->CTR & ~(uint32_t)RTC_CTR_DIV_Msk) | + ((uint32_t)prescaler << (uint32_t)RTC_CTR_DIV_Pos); +} + +/* + * Sets the RTC_TIM0, RTC_TIM1 registers with time values + */ +void XMC_RTC_SetTime(const XMC_RTC_TIME_t *const time) +{ + XMC_ASSERT("XMC_RTC_SetTime:Wrong seconds value", ((uint32_t)time->seconds < XMC_RTC_MAXSECONDS)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong minutes value", ((uint32_t)time->minutes < XMC_RTC_MAXMINUTES)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong hours value", ((uint32_t)time->hours < XMC_RTC_MAXHOURS)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong month day value", ((uint32_t)time->days < XMC_RTC_MAXDAYS)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong week day value", ((uint32_t)time->daysofweek < XMC_RTC_MAXDAYSOFWEEK)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong month value", ((uint32_t)time->month < XMC_RTC_MAXMONTH)); + XMC_ASSERT("XMC_RTC_SetTime:Wrong year value", ((uint32_t)time->year < XMC_RTC_MAXYEAR)); + + #if (XMC_RTC_INIT_SEQUENCE == 1U) + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM0 = time->raw0; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM1 = time->raw1; + #endif + #if (XMC_RTC_INIT_SEQUENCE == 0U) + while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk)) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM0 = time->raw0; + RTC->TIM1 = time->raw1; ; + #endif +} + +/* + * Gets the RTC module time value + */ +void XMC_RTC_GetTime(XMC_RTC_TIME_t *const time) +{ + time->raw0 = RTC->TIM0; + time->raw1 = RTC->TIM1; +} + +/* + * Sets the RTC module time values in standard format + */ +void XMC_RTC_SetTimeStdFormat(const struct tm *const stdtime) +{ + + XMC_RTC_TIME_t time; + + time.seconds = stdtime->tm_sec; + time.minutes = stdtime->tm_min; + time.hours = stdtime->tm_hour; + time.days = stdtime->tm_mday - 1; + time.month = stdtime->tm_mon; + time.year = stdtime->tm_year + XMC_RTC_YEAR_OFFSET; + time.daysofweek = stdtime->tm_wday; + + XMC_RTC_SetTime(&time); +} + +/* + * Gets the RTC module time values in standard format + */ +void XMC_RTC_GetTimeStdFormat(struct tm *const stdtime) +{ + XMC_RTC_TIME_t time; + time.raw0 = RTC->TIM0; + time.raw1 = RTC->TIM1; + + stdtime->tm_sec = (int8_t)time.seconds; + stdtime->tm_min = (int8_t)time.minutes; + stdtime->tm_hour = (int8_t)time.hours; + stdtime->tm_mday = ((int8_t)time.days + (int8_t)1); + stdtime->tm_mon = (int8_t)time.month; + stdtime->tm_year = (int32_t)time.year - (int32_t)XMC_RTC_YEAR_OFFSET; + stdtime->tm_wday = (int8_t)time.daysofweek; +} + +/* + * Sets the RTC module alarm time value + */ +void XMC_RTC_SetAlarm(const XMC_RTC_ALARM_t *const alarm) +{ + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong seconds value", ((uint32_t)alarm->seconds < XMC_RTC_MAXSECONDS)); + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong minutes value", ((uint32_t)alarm->minutes < XMC_RTC_MAXMINUTES)); + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong hours value", ((uint32_t)alarm->hours < XMC_RTC_MAXHOURS)); + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong days value", ((uint32_t)alarm->days < XMC_RTC_MAXDAYS)); + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong month value", ((uint32_t)alarm->month < XMC_RTC_MAXMONTH)); + XMC_ASSERT("XMC_RTC_SetAlarm:Wrong year value", ((uint32_t)alarm->year < XMC_RTC_MAXYEAR)); + + #if (XMC_RTC_INIT_SEQUENCE == 1U) + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM0 = alarm->raw0; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM1 = alarm->raw1; + #endif + #if (XMC_RTC_INIT_SEQUENCE == 0U) + while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk)) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM0 = alarm->raw0; + RTC->ATIM1 = alarm->raw1; + #endif +} + +/* + * Gets the RTC module alarm time value + */ +void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm) +{ + alarm->raw0 = RTC->ATIM0; + alarm->raw1 = RTC->ATIM1; +} + + +/* + * Sets the RTC module alarm time value in standard format + */ +void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime) +{ + XMC_RTC_ALARM_t alarm; + + + alarm.seconds = stdtime->tm_sec; + alarm.minutes = stdtime->tm_min; + alarm.hours = stdtime->tm_hour; + alarm.days = stdtime->tm_mday - 1; + alarm.month = stdtime->tm_mon; + alarm.year = stdtime->tm_year + XMC_RTC_YEAR_OFFSET; + + XMC_RTC_SetAlarm(&alarm); +} + +/* + * Gets the RTC module alarm time value in standard format + */ +void XMC_RTC_GetAlarmStdFormat(struct tm *const stdtime) +{ + XMC_RTC_ALARM_t alarm; + + alarm.raw0 = RTC->ATIM0; + alarm.raw1 = RTC->ATIM1; + + stdtime->tm_sec = (int8_t)alarm.seconds; + stdtime->tm_min = (int8_t)alarm.minutes; + stdtime->tm_hour = (int8_t)alarm.hours; + stdtime->tm_mday = ((int8_t)alarm.days + (int8_t)1); + stdtime->tm_mon = (int8_t)alarm.month; + stdtime->tm_year = (int32_t)alarm.year - (int32_t)XMC_RTC_YEAR_OFFSET; +} + +/* + * Gets the RTC periodic and alarm event(s) status + */ +uint32_t XMC_RTC_GetEventStatus(void) +{ + return RTC->STSSR; +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_sdmmc.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_sdmmc.c new file mode 100644 index 00000000..db99fdd7 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_sdmmc.c @@ -0,0 +1,350 @@ + +/** + * @file xmc_sdmmc.c + * @date 2016-07-11 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * - Removed GetDriverVersion API
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API
+ * + * 2016-03-14: + * - Values are directly assigned to the int status registers
+ * + * 2016-07-11: + * - XMC_SDMMC_SetDataTransferMode() shall not invoke SetDateLineTimeout()
+ * + * @endcond + */ + +/** + * @addtogroup XMClib + * @{ + */ + +/** + * @addtogroup SDMMC + * @brief SDMMC driver + * @{ + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_sdmmc.h" + +/* + * The SDMMC peripheral is only available on the + * XMC4500. The SDMMC definition can be found in + * the XMC4500.h (device header file). + */ +#if defined (SDMMC) +#include "xmc_scu.h" + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +/* + * Check for valid SDMMC error events
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_ERROR_EVENT(e)\ + ((e == XMC_SDMMC_CMD_TIMEOUT_ERR) ||\ + (e == XMC_SDMMC_CMD_CRC_ERR) ||\ + (e == XMC_SDMMC_CMD_END_BIT_ERR) ||\ + (e == XMC_SDMMC_CMD_IND_ERR) ||\ + (e == XMC_SDMMC_DATA_TIMEOUT_ERR) ||\ + (e == XMC_SDMMC_DATA_CRC_ERR) ||\ + (e == XMC_SDMMC_DATA_END_BIT_ERR) ||\ + (e == XMC_SDMMC_CURRENT_LIMIT_ERR) ||\ + (e == XMC_SDMMC_ACMD_ERR) ||\ + (e == XMC_SDMMC_TARGET_RESP_ERR)) + +/* + * Check for valid SDMMC normal events
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_NORMAL_EVENT(e)\ + ((e == XMC_SDMMC_CMD_COMPLETE) ||\ + (e == XMC_SDMMC_TX_COMPLETE) ||\ + (e == XMC_SDMMC_BLOCK_GAP_EVENT) ||\ + (e == XMC_SDMMC_BUFFER_WRITE_READY) ||\ + (e == XMC_SDMMC_BUFFER_READ_READY) ||\ + (e == XMC_SDMMC_CARD_INS) ||\ + (e == XMC_SDMMC_CARD_REMOVAL) ||\ + (e == XMC_SDMMC_CARD_INT)) + +/* + * Check for both normal and error events
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_EVENT(e)\ + ((XMC_SDMMC_CHECK_NORMAL_EVENT(e)) ||\ + (XMC_SDMMC_CHECK_ERROR_EVENT(e))) + +/* + * Check for valid SDMMC wakeup events
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_WAKEUP_EVENT(w)\ + ((w == XMC_SDMMC_WAKEUP_EN_CARD_INT) ||\ + (w == XMC_SDMMC_WAKEUP_EN_CARD_INS) ||\ + (w == XMC_SDMMC_WAKEUP_EN_CARD_REM)) + +/* + * Check for valid SDMMC software reset modes
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_SW_RESET_MODE(m)\ + ((m == XMC_SDMMC_SW_RESET_ALL) ||\ + (m == XMC_SDMMC_SW_RST_CMD_LINE) ||\ + (m == XMC_SDMMC_SW_RST_DAT_LINE)) + +/* + * Check for valid SDMMC transfer modes
+ * + * This macro is used in the LLD for assertion checks (XMC_ASSERT). + */ +#define XMC_SDMMC_CHECK_TRANSFER_MODE(m)\ + ((m == XMC_SDMMC_TRANSFER_MODE_TYPE_SINGLE) ||\ + (m == XMC_SDMMC_TRANSFER_MODE_TYPE_INFINITE) ||\ + (m == XMC_SDMMC_TRANSFER_MODE_TYPE_MULTIPLE) ||\ + (m == XMC_SDMMC_TRANSFER_MODE_TYPE_STOP_MULTIPLE)) + + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +/* Get power status of the SDMMC peripheral */ +bool XMC_SDMMC_GetPowerStatus(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_GetPowerStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + return (bool)(sdmmc->POWER_CTRL & SDMMC_POWER_CTRL_SD_BUS_POWER_Msk); +} + +/* + * De-assert the peripheral reset. The SDMMC peripheral + * needs to be initialized + */ +void XMC_SDMMC_Enable(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_Enable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_SDMMC); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_SDMMC); +#endif +} + +/* Assert the peripheral reset */ +void XMC_SDMMC_Disable(XMC_SDMMC_t *const sdmmc) +{ + XMC_ASSERT("XMC_SDMMC_Disable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_SDMMC); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_SDMMC); +#endif +} + +/* Initialize SDMMC peripheral */ +XMC_SDMMC_STATUS_t XMC_SDMMC_Init(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_CONFIG_t *config) +{ + XMC_ASSERT("XMC_SDMMC_Init: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_Init: Invalid clock divider value", XMC_SDMMC_CHECK_SDCLK_FREQ(config->clock_divider)); + XMC_ASSERT("XMC_SDMMC_Init: Invalid bus width", XMC_SDMMC_CHECK_DATA_LINES(config->bus_width)); + + /* Enable SDMMC peripheral */ + XMC_SDMMC_Enable(sdmmc); + + /* Write internal clock divider register */ + sdmmc->CLOCK_CTRL |= (uint16_t)((uint32_t)config->clock_divider << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos); + + /* Set bus width */ + sdmmc->HOST_CTRL = (uint8_t)((sdmmc->HOST_CTRL & (uint8_t)~SDMMC_HOST_CTRL_DATA_TX_WIDTH_Msk) | + ((uint8_t)config->bus_width << SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos)); + + return XMC_SDMMC_STATUS_SUCCESS; +} + +/* Enable event status */ +void XMC_SDMMC_EnableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_EnableEventStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + /* Set INT status enable register */ + sdmmc->EN_INT_STATUS_NORM |= (uint16_t)event; + sdmmc->EN_INT_STATUS_ERR |= (uint16_t)(event >> 16U); +} + +/* Disable event status */ +void XMC_SDMMC_DisableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_DisableEventStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + /* Clear INT status enable register */ + sdmmc->EN_INT_STATUS_NORM &= (uint16_t)~event; + sdmmc->EN_INT_STATUS_ERR &= (uint16_t)~(event >> 16U); +} + +/* Enable SDMMC event */ +void XMC_SDMMC_EnableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_EnableEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + XMC_SDMMC_EnableEventStatus(sdmmc, event); + + sdmmc->EN_INT_SIGNAL_NORM |= (uint16_t)event; + sdmmc->EN_INT_SIGNAL_ERR |= (uint16_t)(event >> 16U); +} + +/* Disable SDMMC event without disabling event status */ +void XMC_SDMMC_DisableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_DisableEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + /* Clear INT signal enable register */ + sdmmc->EN_INT_SIGNAL_NORM &= (uint16_t)~event; + sdmmc->EN_INT_SIGNAL_ERR &= (uint16_t)~(event >> 16U); +} + +/* Clear SDMMC event(s) */ +void XMC_SDMMC_ClearEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) +{ + XMC_ASSERT("XMC_SDMMC_ClearEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_ClearEvent: Invalid bit-field", !(event & XMC_SDMMC_TARGET_RESP_ERR)); + + sdmmc->INT_STATUS_NORM = (uint16_t)event; + sdmmc->INT_STATUS_ERR = (uint16_t)(event >> 16U); +} + +/* Get the status of an SDMMC event */ +bool XMC_SDMMC_GetEvent(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_EVENT_t event) +{ + bool status; + + XMC_ASSERT("XMC_SDMMC_GetEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_GetEvent: Invalid SDMMC event", XMC_SDMMC_CHECK_EVENT(event)); + + if (event < XMC_SDMMC_CMD_TIMEOUT_ERR) + { + status = (bool)(sdmmc->INT_STATUS_NORM & (uint16_t)event); + } + else + { + status = (bool)(sdmmc->INT_STATUS_ERR & (uint16_t)((uint32_t)event >> 16U)); + } + + return status; +} + +/* Read R2 response (CID, CSD register) */ +void XMC_SDMMC_GetR2Response(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_RESPONSE_t *const response) +{ + XMC_ASSERT("XMC_SDMMC_GetR2Response: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + response->response_0 = sdmmc->RESPONSE[0]; + response->response_2 = sdmmc->RESPONSE[1]; + response->response_4 = sdmmc->RESPONSE[2]; + response->response_6 = sdmmc->RESPONSE[3]; +} + +/* Send SDMMC command */ +XMC_SDMMC_STATUS_t XMC_SDMMC_SendCommand(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_COMMAND_t *cmd, uint32_t arg) +{ + XMC_ASSERT("XMC_SDMMC_SendCommand: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + + sdmmc->ARGUMENT1 = arg; + sdmmc->COMMAND = (uint16_t)(*(uint16_t *)cmd); + + return XMC_SDMMC_STATUS_SUCCESS; +} + +/* Set data transfer mode */ +void XMC_SDMMC_SetDataTransferMode(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_TRANSFER_MODE_t *const response) +{ + XMC_ASSERT("XMC_SDMMC_SetDataTransferMode: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetDataTransferMode: Invalid transfer type", XMC_SDMMC_CHECK_TRANSFER_MODE(response->type)); + + /* Block size */ + sdmmc->BLOCK_SIZE = (uint16_t)(response->block_size); + + /* Number of blocks */ + sdmmc->BLOCK_COUNT = (uint16_t)(response->num_blocks); + + /* Type of data transfer: single, infinite, multiple or stop multiple */ + sdmmc->TRANSFER_MODE = (uint16_t)((sdmmc->TRANSFER_MODE & (uint16_t)~SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Msk) | + ((uint16_t)response->type)); + + /* + * Clear block count enable bit; that's only valid for + * a multi-block transfer + */ + if (response->type == XMC_SDMMC_TRANSFER_MODE_TYPE_SINGLE) + { + sdmmc->TRANSFER_MODE &= (uint16_t)~SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Msk; + } + + /* Auto CMD configuration */ + sdmmc->TRANSFER_MODE = (uint16_t)((sdmmc->TRANSFER_MODE & (uint16_t)~SDMMC_TRANSFER_MODE_ACMD_EN_Msk) | + ((uint16_t)response->auto_cmd << SDMMC_TRANSFER_MODE_ACMD_EN_Pos)); +} + +#endif /* #if defined (SDMMC) */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_spi.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_spi.c new file mode 100644 index 00000000..8d324a32 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_spi.c @@ -0,0 +1,279 @@ +/** + * @file xmc_spi.c + * @date 2015-11-04 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - Modified XMC_SPI_CH_Stop() API for not setting to IDLE the channel if it is busy + * - Modified XMC_SPI_CH_SetInterwordDelay() implementation in order to gain accuracy
+ * + * 2015-06-20: + * - Removed GetDriverVersion API
+ * + * 2015-09-01: + * - Modified XMC_SPI_CH_EnableEvent() and XMC_SPI_CH_DisableEvent() for supporting multiple events configuration
+ * + * 2015-11-04: + * - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_SPI_CH_Transmit() flag
+ * @endcond + * + */ +/** + * + * @brief SPI driver for XMC microcontroller family + * + */ +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ + +#include +#include + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_SPI_CH_OVERSAMPLING (2UL) + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/* Initializes the selected SPI channel with the config structure. */ +void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config) +{ + XMC_USIC_CH_Enable(channel); + + if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER) + { + /* Configure baud rate */ + (void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, XMC_SPI_CH_OVERSAMPLING); + } + + /* Configuration of USIC Shift Control */ + /* Transmission Mode (TRM) = 1 */ + /* Passive Data Level (PDL) = 1 */ + channel->SCTR = USIC_CH_SCTR_PDL_Msk | + (0x1UL << USIC_CH_SCTR_TRM_Pos) | + (0x3fUL << USIC_CH_SCTR_FLE_Pos)| + (0x7UL << USIC_CH_SCTR_WLE_Pos); + + /* Configuration of USIC Transmit Control/Status Register */ + /* TBUF Data Enable (TDEN) = 1 */ + /* TBUF Data Single Shot Mode (TDSSM) = 1 */ + channel->TCSR = (uint32_t)(USIC_CH_TCSR_HPCMD_Msk | + (0x01UL << USIC_CH_TCSR_TDEN_Pos) | + USIC_CH_TCSR_TDSSM_Msk); + + if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER) + { + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode = (uint32_t)(USIC_CH_PCR_SSCMode_MSLSEN_Msk | + USIC_CH_PCR_SSCMode_SELCTR_Msk | + (uint32_t)config->selo_inversion | + USIC_CH_PCR_SSCMode_FEM_Msk); + } + + /* Clear protocol status */ + channel->PSCR = 0xFFFFFFFFUL; + + /* Set parity settings */ + channel->CCR = (uint32_t)config->parity_mode; +} + +XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate) +{ + XMC_SPI_CH_STATUS_t status; + + status = XMC_SPI_CH_STATUS_ERROR; + + if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U)) + { + if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_SPI_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK) + { + status = XMC_SPI_CH_STATUS_OK; + } + } + return status; +} + +/* Enable the selected slave signal by setting (SELO) bits in PCR register. */ +void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SELECT_t slave) +{ + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SELO_Msk; + channel->PCR_SSCMode |= (uint32_t)slave; +} + +/* Disable the slave signals by clearing (SELO) bits in PCR register. */ +void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel) +{ + XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_MSLS); + + /* Configuration of Protocol Control Register */ + channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SELO_Msk; +} + +/* Puts the data into FIFO if FIFO mode is enabled or else into standard buffers, by setting the proper mode. */ +void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_SPI_CH_MODE_t mode) +{ + + channel->CCR = (channel->CCR & (uint32_t)(~USIC_CH_CCR_HPCEN_Msk)) | + (((uint32_t) mode << USIC_CH_CCR_HPCEN_Pos) & (uint32_t)USIC_CH_CCR_HPCEN_Msk); + + + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) + { + while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) + { + } + + XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + channel->TBUF[mode] = data; + } + else + { + channel->IN[mode] = data; + } +} + +/* Reads the data from the buffers based on the FIFO mode selection. */ +uint16_t XMC_SPI_CH_GetReceivedData(XMC_USIC_CH_t *const channel) +{ + uint16_t retval; + + /* Check FIFO size */ + if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U) + { + retval = (uint16_t)channel->RBUF; + } + else + { + retval = (uint16_t)channel->OUTR; + } + + return retval; +} + +/* Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields. */ +void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterword_delay_us) +{ + uint32_t peripheral_clock; + uint32_t pdiv; + uint32_t step; + uint32_t fFD; + uint32_t fpdiv; + uint32_t divider_factor1 = 0U; + uint32_t divider_factor2 = 32U; + uint32_t divider_factor1_int = 0U; + uint32_t divider_factor1_int_min = 4U; + uint32_t divider_factor1_frac_min =100U; + uint32_t divider_factor1_frac = 0U; + uint32_t divider_factor2_temp = 0U; + peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + pdiv = (uint32_t)(channel->BRG & USIC_CH_BRG_PDIV_Msk) >> USIC_CH_BRG_PDIV_Pos; + step = (uint32_t)(channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos; + fFD = (uint32_t)((peripheral_clock >> 10U) * step); + fpdiv= fFD/(1U+pdiv); + + if(tinterword_delay_us < (128000000/fpdiv)) + { + for(divider_factor2_temp = 32U; divider_factor2_temp > 0U; --divider_factor2_temp) + { + + divider_factor1 = (tinterword_delay_us*fpdiv)/(divider_factor2_temp*10000); + divider_factor1_frac = divider_factor1%100U; + + if(divider_factor1_frac > 50) + { + divider_factor1_int = (divider_factor1/100U)+1; + divider_factor1_frac = (divider_factor1_int*100)-divider_factor1; + } + else + { + divider_factor1_int = (divider_factor1/100U); + } + + if ((divider_factor1_int < 5U) && (divider_factor1_int > 0) && (divider_factor1_frac < divider_factor1_frac_min)) + { + divider_factor1_frac_min = divider_factor1_frac; + divider_factor1_int_min = divider_factor1_int; + divider_factor2= divider_factor2_temp; + } + } + } + + channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode) & (~(USIC_CH_PCR_SSCMode_DCTQ1_Msk | + USIC_CH_PCR_SSCMode_PCTQ1_Msk | + USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) | + (((divider_factor1_int_min - 1) << USIC_CH_PCR_SSCMode_PCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_PCTQ1_Msk) | + (((divider_factor2 - 1 ) << USIC_CH_PCR_SSCMode_DCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_DCTQ1_Msk); +} + +XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel) +{ + XMC_SPI_CH_STATUS_t status = XMC_SPI_CH_STATUS_OK; + + if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) + { + status = XMC_SPI_CH_STATUS_BUSY; + } + else + { + + /* USIC channel in IDLE mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE); + } + + return status; +} + +void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR |= (event&0x1fc00U); + channel->PCR_SSCMode |= ((event << 13U) & 0xe000U); +} + +void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR &= (uint32_t)~(event&0x1fc00U); + channel->PCR_SSCMode &= (uint32_t)~((event << 13U) & 0xe000U); +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_uart.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_uart.c new file mode 100644 index 00000000..3641315a --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_uart.c @@ -0,0 +1,216 @@ +/** + * @file xmc_uart.c + * @date 2016-07-22 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-05-20: + * - xmc_uart_ch_stop API implementation corrected. + * - Modified XMC_UART_CH_Stop() API for not setting to IDLE the channel if it is busy
+ * + * 2015-06-20: + * - Removed GetDriverVersion API
+ * + * 2015-09-01: + * - Modified XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent() for supporting multiple events configuration
+ * + * 2016-07-22: + * - Modified XMC_UART_CH_Init() to enable transfer status BUSY + * - Modified XMC_UART_CH_Stop() to check for transfer status + * + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + *********************************************************************************************************************/ + +#include +#include + +/********************************************************************************************************************* + * MACROS + *********************************************************************************************************************/ + +#define XMC_UART_CH_OVERSAMPLING (16UL) +#define XMC_UART_CH_OVERSAMPLING_MIN_VAL (4UL) + +/********************************************************************************************************************* + * API IMPLEMENTATION + *********************************************************************************************************************/ + +void XMC_UART_CH_Init(XMC_USIC_CH_t *channel, const XMC_UART_CH_CONFIG_t *const config) +{ + uint32_t oversampling = XMC_UART_CH_OVERSAMPLING; + + /* USIC channel switched on*/ + XMC_USIC_CH_Enable(channel); + + if(config->oversampling != 0U) + { + oversampling = (uint32_t)config->oversampling; + } + + /* Configure baud rate */ + (void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, oversampling); + + /* Configure frame format + * Configure the number of stop bits + * Pulse length is set to 0 to have standard UART signaling, + * i.e. the 0 level is signaled during the complete bit time + * Sampling point set equal to the half of the oversampling period + * Enable Sample Majority Decision + * Enable Transfer Status BUSY + */ + channel->PCR_ASCMode = (uint32_t)(((config->stop_bits - 1UL) << USIC_CH_PCR_ASCMode_STPB_Pos) | + (((oversampling >> 1UL) + 1UL) << USIC_CH_PCR_ASCMode_SP_Pos) | + USIC_CH_PCR_ASCMode_SMD_Msk | + USIC_CH_PCR_ASCMode_RSTEN_Msk | USIC_CH_PCR_ASCMode_TSTEN_Msk); + + /* Set passive data level, high + Set word length. Data bits - 1 + If frame length is > 0, frame_lemgth-1; else, FLE = WLE (Data bits - 1) + Transmission Mode: The shift control signal is considered active if it + is at 1-level. This is the setting to be programmed to allow data transfers */ + channel->SCTR = (uint32_t)((((uint32_t)config->data_bits - 1UL) << USIC_CH_SCTR_WLE_Pos) | + ((0x1UL << USIC_CH_SCTR_TRM_Pos) | USIC_CH_SCTR_PDL_Msk)); + + if (config->frame_length != 0U) + { + channel->SCTR |= (uint32_t)(((uint32_t)config->frame_length - 1UL) << USIC_CH_SCTR_FLE_Pos); + } + else + { + channel->SCTR |= (uint32_t)(((uint32_t)config->data_bits - 1UL) << USIC_CH_SCTR_FLE_Pos); + } + + /* Enable transfer buffer */ + channel->TCSR = (0x1UL << USIC_CH_TCSR_TDEN_Pos) | + USIC_CH_TCSR_TDSSM_Msk; + + /* Clear protocol status */ + channel->PSCR = 0xFFFFFFFFUL; + + /* Set parity settings */ + channel->CCR = (uint32_t)config->parity_mode; +} + +XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling) +{ + XMC_UART_CH_STATUS_t status; + + status = XMC_UART_CH_STATUS_ERROR; + + if ((rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 2U)) && (oversampling >= XMC_UART_CH_OVERSAMPLING_MIN_VAL)) + { + if (XMC_USIC_CH_SetBaudrate(channel, rate, oversampling) == XMC_USIC_CH_STATUS_OK) + { + status = XMC_UART_CH_STATUS_OK; + } + } + return status; +} + +void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data) +{ + /* Check FIFO size */ + if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0UL) + { + /* Wait till the Transmit Buffer is free for transmission */ + while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { + } + + /* Clear the Transmit Buffer indication flag */ + XMC_UART_CH_ClearStatusFlag(channel, (uint32_t)XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); + + /*Transmit data */ + channel->TBUF[0U] = data; + } + else + { + channel->IN[0U] = data; + } +} + +uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel) +{ + uint16_t retval; + + /* Check FIFO size */ + if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U) + { + retval = (uint16_t)channel->RBUF; + } + else + { + retval = (uint16_t)channel->OUTR; + } + + return retval; +} + +XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel) +{ + XMC_UART_CH_STATUS_t status = XMC_UART_CH_STATUS_OK; + + if (((XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t) XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) || + ((XMC_UART_CH_GetStatusFlag(channel) & XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY) != 0)) + { + status = XMC_UART_CH_STATUS_BUSY; + } + else + { + /* USIC channel in IDLE mode */ + XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE); + } + return status; +} + +void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR |= (event&0x1fc00U); + channel->PCR_ASCMode |= (event&0xf8U); +} + +void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) +{ + channel->CCR &= (uint32_t)~(event&0x1fc00U); + channel->PCR_ASCMode &= (uint32_t)~(event&0xf8U); +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_usbd.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_usbd.c new file mode 100644 index 00000000..e2e977db --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_usbd.c @@ -0,0 +1,1627 @@ +/** + * @file xmc_usbd.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * dave@infineon.com). + ********************************************************************************** + * + * Change History + * -------------- + * + * 2015-02-16: + * - Initial Version.
+ * 2015-03-18: + * - Updated the XMC_USBD_EndpointStall() to fix issue on USB clear stall.
+ * - Updated the XMC_USBD_EndpointConfigure() to fix issue in EP0 configuration.
+ * - Updated the XMC_USBD_IRQHandler()(Removed the DAVE_CE check on SOF event).
+ * 2015-06-20: + * - Removed GetDriverVersion API.
+ * - Updated the XMC_USBD_IsEnumDone() API.
+ * - Updated the copy right in the file header.
+ * - Updated the XMC_USBD_Disable() API to gate the clock after programming the SCU registers.
+ * + * @endcond + * + */ + + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#include + +#if defined(USB0) + +/**< macro to check the maximum number of endpoints used*/ +#define XMC_USBD_CHECK_INPUT_MAX_NUM_EPS(usbd_max_num_eps) \ + ((usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_1 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_2 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_3 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_4 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_5 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_6 ) || \ + (usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_7 )) + +/******************************************************************************* + *GLOBAL DATA + *******************************************************************************/ +/* + * Endpoint Out Fifo Size + */ +uint32_t XMC_USBD_EP_OUT_BUFFERSIZE[7] = {0U,0U,0U,0U,0U,0U,0U}; +/* + * Endpoint In Fifo Size + */ +uint32_t XMC_USBD_EP_IN_BUFFERSIZE[7] = {0U,0U,0U,0U,0U,0U,0U}; +/* + * Device definition + */ + XMC_USBD_DEVICE_t xmc_device; +#ifdef __GNUC__ /*GCC*/ +/* + * Endpoint Out Fifo + */ +static __attribute__((aligned(4))) uint8_t XMC_USBD_EP_OUT_BUFFER[7][256] __attribute__((section("USB_RAM"))); +/* + * Endpoint In Fifo + */ +static __attribute__((aligned(4))) uint8_t XMC_USBD_EP_IN_BUFFER[7][256] __attribute__((section("USB_RAM"))); +#endif +#if defined(__ICCARM__) +#pragma data_alignment=4 +/* + * Endpoint Out Fifo + */ +static uint8_t XMC_USBD_EP_OUT_BUFFER[7][256] @ ".dram"; +/* + * Endpoint In Fifo + */ +#pragma data_alignment=4 +static uint8_t XMC_USBD_EP_IN_BUFFER[7][256] @ ".dram"; +#endif +#if defined(__CC_ARM) +/* + * Endpoint Out Fifo + */ +static __attribute__((aligned(4))) uint8_t XMC_USBD_EP_OUT_BUFFER[7][256] __attribute__((section ("RW_IRAM1"))); +/* + * Endpoint In Fifo + */ +static __attribute__((aligned(4))) uint8_t XMC_USBD_EP_IN_BUFFER[7][256] __attribute__((section ("RW_IRAM1"))); +#endif +XMC_USBD_t *usbd_init; + +/******************************************************************************* + *LOCAL ROUTINES + *******************************************************************************/ +/*Local routines prototypes*/ +uint8_t XMC_USBD_lDeviceActive(const XMC_USBD_t *const obj); +static void XMC_USBD_lReadFifo(const uint32_t ep_num,const uint32_t byte_count); +static uint32_t XMC_USBD_lWriteFifo(XMC_USBD_EP_t *ep); +static void XMC_USBD_lFlushTXFifo(const uint8_t fifo_num); +static void XMC_USBD_lFlushRXFifo(void); +static uint8_t XMC_USBD_lAssignTXFifo(void); +static void XMC_USBD_lStartReadXfer(XMC_USBD_EP_t *const ep); +static void XMC_USBD_lStartWriteXfer(XMC_USBD_EP_t *const ep); +static void XMC_USBD_lHandleEnumDone(void); +static void XMC_USBD_lHandleOEPInt(const XMC_USBD_t *const obj); +static void XMC_USBD_lHandleRxFLvl(void); +static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj); +static void XMC_USBD_lUnassignFifo(const uint8_t fifo_nr); +static void XMC_USBD_lHandleUSBReset(const XMC_USBD_t *const obj); +static void XMC_USBD_lHandleOTGInt(void); +static void XMC_USBD_lClearEventOTG(uint32_t event); + +/** + * The device driver + */ +const XMC_USBD_DRIVER_t Driver_USBD0 = +{ + .GetCapabilities = XMC_USBD_GetCapabilities, + .Initialize = XMC_USBD_Init, + .Uninitialize = XMC_USBD_Uninitialize, + .DeviceConnect = XMC_USBD_DeviceConnect, + .DeviceDisconnect = XMC_USBD_DeviceDisconnect, + .DeviceGetState = XMC_USBD_DeviceGetState, + .DeviceSetAddress = XMC_USBD_DeviceSetAddress, + .EndpointConfigure = XMC_USBD_EndpointConfigure, + .EndpointUnconfigure = XMC_USBD_EndpointUnconfigure, + .EndpointStall = XMC_USBD_EndpointStall, + .EndpointReadStart = XMC_USBD_EndpointReadStart, + .EndpointRead = XMC_USBD_EndpointRead, + .EndpointWrite = XMC_USBD_EndpointWrite, + .EndpointAbort = XMC_USBD_EndpointAbort, + .GetFrameNumber = XMC_USBD_GetFrameNumber, + .IsEnumDone = XMC_USBD_IsEnumDone +}; + +/** + * @brief Checks if device is active + * + * Therefore the endpoint inInUse flag are checked and if one endpoint is in use, 1 is returned, + * else 0 is returned. + * @return 1 if an endpoint is active else 0 + */ +uint8_t XMC_USBD_lDeviceActive(const XMC_USBD_t *const obj) +{ + uint8_t i; + uint8_t result = 0U; + for (i = 0U; i < (uint8_t)obj->usbd_max_num_eps; i++) + { + if (xmc_device.ep[i].inInUse || xmc_device.ep[i].outInUse) + { + result = 1U; + } + } + return result; +} + + +/** + * @brief Read data from the rx fifo + * + * The data from the fifo is copied in to the buffer specified by @ref xfer_buffer and + * the transfer values get updated. If the endpoint is disabled or the buffer not existent + * the function exits. + * + * @arg ep_num the endpoint to read for + * @arg byte_count the byte count to read + */ +static void XMC_USBD_lReadFifo(const uint32_t ep_num,const uint32_t byte_count) +{ + XMC_USBD_EP_t * ep = &xmc_device.ep[ep_num]; + uint32_t word_count; + uint32_t temp_data; + uint32_t temp_word_count; + volatile uint32_t *fifo = xmc_device.fifo[0U]; + uint32_t i; + depctl_data_t data; + data.d32 = xmc_device.endpoint_out_register[ep_num]->doepctl; + word_count = (byte_count >> 2U ); + temp_word_count = (word_count << 2U); + /* Check if ep is enabled and has buffer */ + if (!data.b.usbactep) + { + /*Do Nothing*/ + } + else if (ep->xferBuffer == NULL) + { + /*Do Nothing*/ + } + else + { + /* store the data */ + for (i = 0U;i < word_count; i++) + { + *(((uint32_t*)ep->xferBuffer)+i) = *fifo; + } + /* space is not devidable by 4 */ + if (byte_count!=temp_word_count) + { + temp_data = *fifo; + for (i = 0U;(temp_word_count + i) < byte_count;i++) + { + ep->xferBuffer[(word_count << 2)+i] = (uint8_t)((temp_data & ((uint32_t)0xFFU << (i * 8U))) >> (i * 8U)); + } + } + + /* save the amount of data */ + ep->xferCount += byte_count; + ep->xferBuffer += byte_count; + } +} + +/** + * @brief Write data to an endpoint fifo + * + * The data from the @ref xfer_buffer gets copied in to the tx fifo of the endpoint until the buffer has been read + *completely or the tx fifo is full. The transfer values are not updated. + * + * @arg[in] ep the endpoint to use + * @return the number of bytes written to the fifo + */ +static uint32_t XMC_USBD_lWriteFifo(XMC_USBD_EP_t *const ep) +{ + dtxfsts_data_t freeSpace; + volatile uint32_t *fifo; + uint32_t byte_count; + uint32_t word_count; + uint32_t result; + uint32_t i; + fifo = xmc_device.fifo[ep->address_u.address_st.number]; /* fifo */ + freeSpace.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->dtxfsts; + /* calculate the length and the amount of dwords to copy based on the fifo status */ + byte_count = ep->xferLength - ep->xferCount; + if (!byte_count) + { + result = 0U; + } + else + { + /* add the unaligned bytes to the word count to compare with the fifo space */ + word_count = ((uint32_t)byte_count + 3U) >> 2U; + if (word_count > (uint32_t)freeSpace.b.txfspcavail ) + { + word_count = (uint32_t)freeSpace.b.txfspcavail; + byte_count = (uint32_t)word_count << (uint32_t)2U; + } + + /* copy data dword wise */ + for (i = 0U; i < word_count;ep->xferBuffer+= 4U) + { + *fifo = *(uint32_t*)ep->xferBuffer; + i++; + } + result=byte_count; + } + return result; +} + +/** + * @brief Flush a tx fifo + * + * @param[in] fifo_num Fifo number to flush + * + * @note Use 0x10 as parameter to flush all tx fifos. + */ +static void XMC_USBD_lFlushTXFifo(const uint8_t fifo_num) +{ + volatile grstctl_t data; + uint32_t count; + data.d32 = 0U; + /*flush fifo */ + data.b.txfflsh = 1U; + data.b.txfnum = fifo_num; + xmc_device.global_register->grstctl = data.d32; + for (count = 0U;count < 1000U; count++){} + do + { + data.d32 = xmc_device.global_register->grstctl; + } while (data.b.txfflsh); + count = 0U; + while (count++ < 1000U) + { + /* wait 3 phy clocks */ + } +} + +/** + * @brief Flush the rx fifo + */ +static void XMC_USBD_lFlushRXFifo(void) +{ + volatile grstctl_t data; + uint32_t count; + + data.d32 = 0U; + data.b.rxfflsh = 1U; + /* flush FIFO */ + xmc_device.global_register->grstctl = data.d32; + do + { + for (count = 0U; count < 1000U; count++){} + data.d32 = xmc_device.global_register->grstctl; + } while (data.b.rxfflsh); + count = 0U; + while (count++ < 1000U) + { + /* wait 3 phy clocks */ + } +} + +/* + * Support Functions + */ + +/** + * @brief Assign a free tx fifo + * + * A free tx fifo will be searched and the number will be returned. + * + * @return Fifo number for a free fifo + */ +static uint8_t XMC_USBD_lAssignTXFifo(void) +{ + uint16_t mask = 1U; + uint8_t i = 0U; + uint8_t result = 0U; + while( (i < (uint8_t)XMC_USBD_NUM_TX_FIFOS)&&((xmc_device.txfifomsk & mask) != 0U)) + { + mask = (uint16_t)(mask << 1U); + i++; + } + if ((xmc_device.txfifomsk & mask) == 0U) + { + xmc_device.txfifomsk |= mask; + result=i; + } + return result; +} + +/** + * @brief Free a tx fifo + * + * Mark an used tx fifo as free. + * @param[in] fifo_nr Fifo number to free + */ +static void XMC_USBD_lUnassignFifo(const uint8_t fifo_nr) +{ + xmc_device.txfifomsk = (uint16_t)((uint32_t)xmc_device.txfifomsk & (uint32_t)(~((uint32_t)((uint32_t)1U << fifo_nr)))); +} + +/** + * @brief Start a transfer for an out endpoint + * + * Based on the transfer values of the endpoint, the out endpoint registers will be programmed + * to start a new out transfer. + * + * @note No checking of the transfer values are done in this function. Be sure, + * that the transfer values are reasonable (e.g. buffer size is not exceeded). + * + * @param[in] ep Endpoint to start the transfer + */ +static void XMC_USBD_lStartReadXfer(XMC_USBD_EP_t *const ep) +{ + deptsiz_data_t data; + depctl_data_t epctl; + + data.d32 = 0U; + if ((ep->xferTotal - ep->xferLength) > ep->maxTransferSize) + { + ep->xferLength += ep->maxTransferSize; + } + else + { + ep->xferLength = ep->xferTotal; + } + if (ep->address_u.address_st.number == 0U) + { + /* Setup the endpoint to receive 3 setup packages and one normal package.*/ + /* Cast the data pointer to use only one variable */ + deptsiz0_data_t *ep0_data = (deptsiz0_data_t*)&data; + ep0_data->b.pktcnt = 0x1U; + ep0_data->b.supcnt = 0x3U; + ep0_data->b.xfersize = (uint8_t)ep->xferTotal; + } + else + { + /* If requested length is zero, just receive one zero length packet */ + if (ep->xferLength == 0U) + { + data.b.xfersize = 0U; + data.b.pktcnt = 1U; + } + else + { + /* setup endpoint to recive a amount of packages by given size */ + data.b.pktcnt = (uint16_t)(((ep->xferLength - ep->xferCount) + (ep->maxPacketSize -(uint32_t)1U))/ep->maxPacketSize); + data.b.xfersize =(uint32_t)(ep->xferLength - ep->xferCount); + } + } + if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + /* Programm dma address if needed */ + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepdma = (uint32_t)(ep->xferBuffer); + } + /* setup endpoint size and enable endpoint */ + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doeptsiz = data.d32; + + epctl.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; + epctl.b.cnak = 1U; + epctl.b.epena = 1U; + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = epctl.d32; +} + +/** + * @brief Start a new in transfer + * + * Based on the transfer values of the endpoint the in endpoint registers will be programmed + * to start a new in transfer + * + * @param[in] ep Endpoint to start the transfer + */ +static void XMC_USBD_lStartWriteXfer(XMC_USBD_EP_t *const ep) +{ + deptsiz_data_t size; + depctl_data_t ctl; + + size.d32 = 0U; + ctl.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; + + if ((ep->xferTotal - ep->xferLength) < ep->maxTransferSize) + { + ep->xferLength = ep->xferTotal; + } + else + { + ep->xferLength += ep->maxTransferSize; + } + if (ep->xferLength == 0U) + { + size.b.xfersize = 0U; + size.b.pktcnt = 1U; + } + else + { + if (ep->address_u.address_st.number == 0U) + { + size.b.pktcnt = 1U; + /* ep->maxXferSize equals maxPacketSize */ + size.b.xfersize = (uint32_t)(ep->xferLength - ep->xferCount); + } + else + { + size.b.xfersize =(uint32_t)(ep->xferLength - ep->xferCount); + size.b.pktcnt = (uint16_t)(((uint16_t)(ep->xferLength - ep->xferCount) + (uint16_t)((uint16_t)ep->maxPacketSize - 1U))/ + ep->maxPacketSize); + } + if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + /* Program dma*/ + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepdma = (uint32_t)ep->xferBuffer; + } + if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + /* enable fifo empty interrupt */ + xmc_device.device_register->dtknqr4_fifoemptymsk |= (uint32_t)((uint32_t)1U << (uint8_t)ep->address_u.address_st.number); + } + } + + /* Program size of transfer and enable endpoint */ + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->dieptsiz = size.d32; + ctl.b.epena = 1U; + ctl.b.cnak = 1U; + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = ctl.d32; +} + + +/** + * @brief Handles the USBD reset interrupt + * + * When ever the host sets the bus into reset condition the usb otg_core generates + * an interrupt, which is handled by this function. It resets the complete otg_core + * into the default state. + */ +static void XMC_USBD_lHandleUSBReset(const XMC_USBD_t *const obj) +{ + uint32_t i; + depctl_data_t epctl; + dctl_data_t dctl; + fifosize_data_t gnptxfsiz; + daint_data_t daint; + dcfg_data_t dcfg; + + /* Clear the Remote Wakeup Signaling */ + dctl.d32 = xmc_device.device_register->dctl; + dctl.b.rmtwkupsig = 1U; + xmc_device.device_register->dctl = dctl.d32; + + /* enable naks for all eps */ + for (i = 0U;i < (uint8_t)XMC_USBD_NUM_EPS;i++) + { + epctl.d32 = xmc_device.endpoint_out_register[i]->doepctl; + epctl.b.snak = 1U; + epctl.b.stall = 0U; + xmc_device.endpoint_out_register[i]->doepctl = epctl.d32; + } + + /* Configure fifos */ + /* Calculate the size of the rx fifo */ + xmc_device.global_register->grxfsiz = 64U; + /* Calculate the size of the tx fifo for ep 0 */ + gnptxfsiz.d32 = 0U; + gnptxfsiz.b.depth = 16U; + gnptxfsiz.b.startaddr = 64U; + xmc_device.global_register->gnptxfsiz = gnptxfsiz.d32; + /* calculate the size for the rest */ + for (i = 1U;i < (uint8_t)XMC_USBD_NUM_TX_FIFOS;i++) + { + xmc_device.global_register->dtxfsiz[i- 1U] = (uint32_t)(((256U + (i*(64U)))/4U) | ((uint32_t)16U << 16U)); + } + + /* flush the fifos for proper operation */ + XMC_USBD_lFlushTXFifo(0x10U); /* 0x10 == all fifos, see doc */ + XMC_USBD_lFlushTXFifo(0x0U); + XMC_USBD_lFlushRXFifo(); + /* Flush learning queue not needed due to fifo config */ + /* enable ep0 interrupts */ + daint.d32 = 0U; + daint.b.inep0 = 1U; + daint.b.outep0 = 1U; + xmc_device.device_register->daintmsk = daint.d32; + + /* enable endpoint interrupts */ + /* out ep interrupts */ + XMC_USBD_EnableEventOUTEP(((uint32_t)XMC_USBD_EVENT_OUT_EP_TX_COMPLET | (uint32_t)XMC_USBD_EVENT_OUT_EP_DISABLED | + (uint32_t)XMC_USBD_EVENT_OUT_EP_SETUP | (uint32_t)XMC_USBD_EVENT_OUT_EP_AHB_ERROR)); + + /*in ep interrupts */ + XMC_USBD_EnableEventINEP(((uint32_t)XMC_USBD_EVENT_IN_EP_TX_COMPLET | (uint32_t)XMC_USBD_EVENT_IN_EP_DISABLED | + (uint32_t)XMC_USBD_EVENT_IN_EP_AHB_ERROR | (uint32_t)XMC_USBD_EVENT_IN_EP_TIMEOUT)); + + + /* Clear device Address */ + dcfg.d32 = xmc_device.device_register->dcfg; + dcfg.b.devaddr = 0U; + xmc_device.device_register->dcfg = dcfg.d32; + + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + /* Clear Empty interrupt */ + xmc_device.device_register->dtknqr4_fifoemptymsk = 0U; + } + + xmc_device.ep[0U].outInUse = 0U; + xmc_device.ep[0U].inInUse = 0U; + + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_RESET); + + /* clear reset intr */ + XMC_USBD_ClearEvent(XMC_USBD_EVENT_RESET); +} + +/** +* @brief Handle OTG Interrupt +* +* It detects especially connect and disconnect events. +*/ +static void XMC_USBD_lHandleOTGInt(void) +{ + gotgint_data_t data; + data.d32 = xmc_device.global_register->gotgint; + if (data.b.sesenddet) + { + xmc_device.IsPowered = 0U; + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_POWER_OFF); + } + XMC_USBD_lClearEventOTG(data.d32); + +} + +/** + * @brief Interrupt handler for device enumeration done. + * + * Handles the enumeration done from dwc_otg, when the host has enumerated the device. + */ +static void XMC_USBD_lHandleEnumDone(void) +{ + /* Normaly we need to check dctl + * We are always fullspeed, so max it up. */ + depctl_data_t epctl; + gusbcfg_data_t gusbcfg; + + epctl.d32=xmc_device.endpoint_in_register[0U]->diepctl; + epctl.b.mps = 0x00U; /* 64 Byte, this is also automatically set for out ep */ + xmc_device.endpoint_in_register[0U]->diepctl = epctl.d32; + + /* update device connected flag */ + xmc_device.IsConnected = 1U; + xmc_device.IsPowered = 1U; + + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_CONNECT); + + /* Set Trim */ + gusbcfg.d32 = xmc_device.global_register->gusbcfg; + gusbcfg.b.usbtrdtim = 9U; /* default value for LS/FS */ + xmc_device.global_register->gusbcfg = gusbcfg.d32; + + /* clear interrupt */ + XMC_USBD_ClearEvent(XMC_USBD_EVENT_ENUMDONE); +} + + +/** + * @brief Handles all interrupts for all out endpoints + * + * The interrupt handler first checks, which endpoint has caused the interrupt and then + * determines, which interrupt should be handled. + */ +static void XMC_USBD_lHandleOEPInt(const XMC_USBD_t *const obj) +{ + daint_data_t daint; + daint_data_t daintmsk; + doepmsk_data_t doepmsk; + doepint_data_t doepint; + deptsiz_data_t doeptsiz; + XMC_USBD_EP_t *ep; + uint16_t temp; + uint16_t temp1; + uint16_t mask; + uint8_t ep_num; + + daint.d32 = xmc_device.device_register->daint; + + daintmsk.d32 = xmc_device.device_register->daintmsk; + + doepmsk.d32 = xmc_device.device_register->doepmsk; + + mask = daint.ep.out & daintmsk.ep.out; + ep_num = 0U; + doeptsiz.d32 = 0U; + + while ((uint16_t)mask >> ep_num) + { + temp1 = (mask >> (uint16_t)ep_num); + temp = temp1 & 0x1U; + if (temp) + { + /* load register data for endpoint */ + ep = &xmc_device.ep[ep_num]; + doepint.d32 = xmc_device.endpoint_out_register[ep_num]->doepint & doepmsk.d32; + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + doeptsiz.d32 = xmc_device.endpoint_out_register[ep_num]->doeptsiz; + } + /* Setup Phase Complete */ + if (doepint.b.setup) + { + /* ep0 not stalled any more */ + ep->isStalled = 0U; + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + /* calculate size for setup packet */ + ep->outBytesAvailable = (uint32_t)(((uint32_t)XMC_USBD_SETUP_COUNT - + (uint32_t)((deptsiz0_data_t*)&doeptsiz)->b.supcnt)*(uint32_t)XMC_USBD_SETUP_SIZE); + } + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + ep->outBytesAvailable += ep->xferCount; + } + ep->outInUse = 0U; + xmc_device.EndpointEvent_cb(0U,XMC_USBD_EP_EVENT_SETUP); /* signal endpoint event */ + /* clear the interrupt */ + XMC_USBD_ClearEventOUTEP((uint32_t)XMC_USBD_EVENT_OUT_EP_SETUP,ep_num); + } + if (doepint.b.xfercompl) + { + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + uint32_t bytes = (ep->xferLength - ep->xferCount) - doeptsiz.b.xfersize; + ep->xferCount += bytes; + ep->xferBuffer += bytes; + } + if (ep->xferTotal == ep->xferLength) + { + ep->outBytesAvailable = ep->xferCount; + ep->outInUse = 0U; + xmc_device.EndpointEvent_cb(ep_num,XMC_USBD_EP_EVENT_OUT); + } + else + { + XMC_USBD_lStartReadXfer(ep); + } + + } + + XMC_USBD_ClearEventOUTEP(doepint.d32,ep_num); + } + ep_num++; + } + + /* clear interrupt */ + XMC_USBD_ClearEvent(XMC_USBD_EVENT_OUTEP); +} + +/** + * @brief Handles all interrupts for all in endpoints + * + * The interrupt handler first checks, which endpoint has caused the interrupt and then + * determines, which interrupt should be handled. + */ +static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj) +{ + XMC_USBD_EP_t *ep; + daint_data_t daint; + diepmsk_data_t diepmsk; + diepint_data_t diepint; + deptsiz_data_t dieptsiz; + uint16_t temp; + uint16_t temp1; + uint16_t mask; + uint8_t ep_num; + uint32_t inepint; + + daint.d32 = xmc_device.device_register->daint; + + diepmsk.d32 = xmc_device.device_register->diepmsk; + + dieptsiz.d32 = 0U; + mask = daint.ep.in; + ep_num = 0U; + + while ((uint16_t)mask >> ep_num) + { + temp1 = ((uint16_t)mask >> (uint16_t)ep_num); + temp = (uint16_t)temp1 & (uint16_t)0x1U; + if ((uint16_t)temp) + { + ep = &xmc_device.ep[ep_num]; + inepint = (uint32_t)xmc_device.endpoint_in_register[ep_num]->diepint; + diepint.d32 = inepint & + ((((uint32_t)((uint32_t)xmc_device.device_register->dtknqr4_fifoemptymsk >> ep->address_u.address_st.number) & + 0x1U) << 7U) | (uint32_t)diepmsk.d32); + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + dieptsiz.d32 = xmc_device.endpoint_in_register[ep_num]->dieptsiz; + } + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + if (diepint.b.emptyintr) + { + uint32_t bytes; + bytes = XMC_USBD_lWriteFifo(ep); + ep->xferCount += bytes; + ep->xferBuffer += bytes; + } + } + if (diepint.b.xfercompl) + { + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + /* update xfer values */ + if ((dieptsiz.b.pktcnt == 0U) && (dieptsiz.b.xfersize == 0U)) + { + uint32_t Bytes = ep->xferLength - ep->xferCount; + ep->xferCount += Bytes; + ep->xferBuffer += Bytes; + } + } + if (ep->xferTotal==ep->xferLength) + { + ep->inInUse = 0U; + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + /* mask fifo empty interrupt */ + xmc_device.device_register->dtknqr4_fifoemptymsk = + (uint32_t)(xmc_device.device_register->dtknqr4_fifoemptymsk & ~(((uint32_t)1U << ep_num))); + } + xmc_device.EndpointEvent_cb(0x80U | ep_num,XMC_USBD_EP_EVENT_IN); + } + else + { + /* start next step of transfer */ + XMC_USBD_lStartWriteXfer(ep); + } + + } + + XMC_USBD_ClearEventINEP((uint32_t)diepint.d32,ep_num); + } + ep_num++; + } + XMC_USBD_ClearEvent(XMC_USBD_EVENT_INEP); +} + +/** + * @brief RX Fifo interrupt handler + * + * This function handles the interrupt, when the rx fifo is not empty anymore. + */ +static void XMC_USBD_lHandleRxFLvl(void) +{ + device_grxsts_data_t data; + data.d32 = xmc_device.global_register->grxstsp; + + switch (data.b.pktsts) + { + case XMC_USBD_GRXSTS_PKTSTS_GOUTNAK: + break; + case XMC_USBD_GRXSTS_PKTSTS_OUTCMPL: + break; + case XMC_USBD_GRXSTS_PKTSTS_OUTDATA: + XMC_USBD_lReadFifo((uint32_t)data.b.epnum,(uint32_t)data.b.bcnt); + break; + case XMC_USBD_GRXSTS_PKTSTS_SETUP: + XMC_USBD_lReadFifo((uint32_t)data.b.epnum,(uint32_t)data.b.bcnt); + break; + case XMC_USBD_GRXSTS_PKTSTS_SETUPCMPL: + break; + default: + break; + } + /* no need to clear */ +} + +/** + * @brief Global interrupt handler + * + * The handler first checks, which global interrupt has caused the interrupt + * and then dispatches interrupt to the corresponding sub-handler. + */ +void XMC_USBD_IRQHandler(const XMC_USBD_t *const obj) +{ + gintmsk_data_t gintmsk; + gintsts_data_t data; + + gintmsk.d32 = xmc_device.global_register->gintmsk; + data.d32 = xmc_device.global_register->gintsts & gintmsk.d32; + + if (data.b.sofintr) + { + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_SOF); + XMC_USBD_ClearEvent(XMC_USBD_EVENT_SOF); + } + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + if (data.b.rxstsqlvl) + { + /* Masked that interrupt so its only done once */ + gintmsk.b.rxstsqlvl = 0U; + xmc_device.global_register->gintmsk = gintmsk.d32; + XMC_USBD_lHandleRxFLvl(); /* handle the interrupt */ + gintmsk.b.rxstsqlvl = 1U; + xmc_device.global_register->gintmsk = gintmsk.d32; + } + } + if (data.b.erlysuspend) + { + XMC_USBD_ClearEvent(XMC_USBD_EVENT_EARLYSUSPEND); + } + if (data.b.usbsuspend) + { + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_SUSPEND); + XMC_USBD_ClearEvent(XMC_USBD_EVENT_SUSPEND); + } + if (data.b.wkupintr) + { + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_REMOTE_WAKEUP); + XMC_USBD_ClearEvent(XMC_USBD_EVENT_REMOTE_WAKEUP); + } + if (data.b.sessreqintr) + { + xmc_device.IsPowered = 1U; + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_POWER_ON); + XMC_USBD_ClearEvent(XMC_USBD_EVENT_POWER_ON); + } + if (data.b.usbreset) + { + XMC_USBD_lHandleUSBReset(obj); + } + if (data.b.enumdone) + { + XMC_USBD_lHandleEnumDone(); + } + if (data.b.inepint) + { + XMC_USBD_lHandleIEPInt(obj); + } + if (data.b.outepintr) + { + XMC_USBD_lHandleOEPInt(obj); + } + if (data.b.otgintr) + { + XMC_USBD_lHandleOTGInt(); + } + +} + + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ +/** + * Enables the USB0 module + **/ +void XMC_USBD_Enable(void) +{ +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); +#endif + /* Reset and power up */ + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0); + XMC_SCU_POWER_EnableUsb(); +} + +/** + * Disables the USB0 module + **/ +void XMC_USBD_Disable(void) +{ + /* Clear Reset and power up */ + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0); +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); +#endif + XMC_SCU_POWER_DisableUsb(); +} + +/** + * Clear the USB device event + **/ +void XMC_USBD_ClearEvent(const XMC_USBD_EVENT_t event) +{ + gintsts_data_t clear; + clear.d32 = 0U; + switch(event) + { + case (XMC_USBD_EVENT_POWER_ON): + clear.b.sessreqintr = 1U; + break; + case (XMC_USBD_EVENT_RESET): + clear.b.usbreset = 1U; + break; + case (XMC_USBD_EVENT_SUSPEND): + clear.b.usbsuspend = 1U; + break; + case (XMC_USBD_EVENT_RESUME): + clear.b.wkupintr = 1U; + break; + case (XMC_USBD_EVENT_REMOTE_WAKEUP): + clear.b.wkupintr = 1U; + break; + case (XMC_USBD_EVENT_SOF): + clear.b.sofintr = 1U; + break; + case (XMC_USBD_EVENT_EARLYSUSPEND): + clear.b.erlysuspend = 1U; + break; + case (XMC_USBD_EVENT_ENUMDONE): + clear.b.enumdone = 1U; + break; + case (XMC_USBD_EVENT_OUTEP): + clear.b.outepintr = 1U; + break; + default: + break; + } + xmc_device.global_register->gintsts = clear.d32; +} + +/** + * Clear the USB OTG events + **/ +static void XMC_USBD_lClearEventOTG(uint32_t event) +{ + gotgint_data_t clear = { .d32 = 0U}; + clear.d32 = event; + xmc_device.global_register->gotgint = clear.d32; +} + +/** + * Clear the USB IN EP events + **/ +void XMC_USBD_ClearEventINEP(uint32_t event,const uint8_t ep_num) +{ + diepint_data_t clear; + clear.d32 = event; + xmc_device.endpoint_in_register[ep_num]->diepint = clear.d32; +} + +/** + * Clear the USB OUT EP events + **/ +void XMC_USBD_ClearEventOUTEP(uint32_t event,const uint8_t ep_num) +{ + doepint_data_t clear; + clear.d32 = event; + xmc_device.endpoint_out_register[ep_num]->doepint = clear.d32; +} + +/** + * Enable the USB OUT EP events + **/ +void XMC_USBD_EnableEventOUTEP(uint32_t event) +{ + doepint_data_t doepint; + doepint.d32 = event; + xmc_device.device_register->doepmsk |= doepint.d32; +} + +/** + * Enable the USB IN EP events + **/ +void XMC_USBD_EnableEventINEP(uint32_t event) +{ + diepint_data_t diepint; + diepint.d32 = event; + xmc_device.device_register->diepmsk |= diepint.d32; +} + +/** + * Gets the USB device capabilities + **/ +XMC_USBD_CAPABILITIES_t XMC_USBD_GetCapabilities() +{ + XMC_USBD_CAPABILITIES_t cap={0U}; + cap.event_connect = 1U; + cap.event_disconnect = 1U; +#if UC_SERIES == 45 + cap.event_power_off = 1U; + cap.event_power_on = 1U; +#else + cap.event_power_off = 0U; + cap.event_power_on = 0U; +#endif + cap.event_high_speed = 0U; + cap.event_remote_wakeup = 1U; + cap.event_reset = 1U; + cap.event_resume = 1U; + cap.event_suspend = 1U; + cap.reserved = 0U; + return cap; +} + +/** + * Initializes the USB device + **/ +XMC_USBD_STATUS_t XMC_USBD_Init(XMC_USBD_t *obj) +{ + uint8_t *XMC_USBD_BASE_ADDRESS; + uint32_t i; + gahbcfg_data_t gahbcfg; + gusbcfg_data_t gusbcfg; + dcfg_data_t dcfg; + dctl_data_t dctl; + gintmsk_data_t gintmsk; + + XMC_ASSERT("XMC_USBD_Init: obj.usbd_max_num_eps not of type XMC_USBD_MAX_NUM_EPS_t", + XMC_USBD_CHECK_INPUT_MAX_NUM_EPS(obj->usbd_max_num_eps)) + + XMC_USBD_Enable(); + + usbd_init = obj; + + /* Filling out buffer size */ + for(i = 0U;i < (uint32_t)XMC_USBD_NUM_EPS;i++) + { + XMC_USBD_EP_OUT_BUFFERSIZE[i] = XMC_USBD_EP0_BUFFER_SIZE; + XMC_USBD_EP_IN_BUFFERSIZE[i] = XMC_USBD_EP0_BUFFER_SIZE; + } + + /* clear device status */ + memset((void*)&xmc_device,0x0U,sizeof(XMC_USBD_DEVICE_t)); + + /* assign callbacks */ + xmc_device.DeviceEvent_cb = obj->cb_xmc_device_event; + xmc_device.EndpointEvent_cb = obj->cb_endpoint_event; + XMC_USBD_BASE_ADDRESS = (uint8_t *)(obj->usbd); + /* assign register address */ + xmc_device.global_register = (dwc_otg_core_global_regs_t*)(obj->usbd); + xmc_device.device_register = ((dwc_otg_device_global_regs_t*)(XMC_USBD_BASE_ADDRESS + DWC_DEV_GLOBAL_REG_OFFSET)); + for (i = 0U;i < (uint32_t)XMC_USBD_NUM_EPS;i++) + { + xmc_device.endpoint_in_register[i] = (dwc_otg_dev_in_ep_regs_t*)(XMC_USBD_BASE_ADDRESS + DWC_DEV_IN_EP_REG_OFFSET + + ((uint32_t)DWC_EP_REG_OFFSET*i)); + } + for (i = 0U;i < (uint32_t)XMC_USBD_NUM_EPS;i++) + { + xmc_device.endpoint_out_register[i] = (dwc_otg_dev_out_ep_regs_t*)(XMC_USBD_BASE_ADDRESS + + DWC_DEV_OUT_EP_REG_OFFSET + + ((uint32_t)DWC_EP_REG_OFFSET*i)); + } + for (i = 0U;i < (uint32_t)XMC_USBD_NUM_TX_FIFOS;i++) + { + xmc_device.fifo[i] = (uint32_t*)(XMC_USBD_BASE_ADDRESS + + XMC_USBD_TX_FIFO_REG_OFFSET + + (i * XMC_USBD_TX_FIFO_OFFSET)); + } + /* obj data structure for endpoint 0 */ + /* Done by driver core */ + /* configure ahb details */ + gahbcfg.d32 = xmc_device.global_register->gahbcfg; + gahbcfg.b.glblintrmsk = 1U; /* enable interrupts ( global mask ) */ + gahbcfg.b.nptxfemplvl_txfemplvl = 1U; + if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + { + /* Enable dma if needed */ + gahbcfg.b.dmaenable = 1U; /* enable dma if needed */ + } + else + { + gahbcfg.b.dmaenable = 0U; + } + xmc_device.global_register->gahbcfg = gahbcfg.d32; + /* configure usb details */ + gusbcfg.d32= xmc_device.global_register->gusbcfg; + gusbcfg.b.force_dev_mode = 1U; /* force us into device mode */ + gusbcfg.b.srpcap = 1U; /* enable session request protocoll */ + xmc_device.global_register->gusbcfg = gusbcfg.d32; + + /* Device init */ + /* configure device speed */ + dcfg.d32 = xmc_device.device_register->dcfg; + dcfg.b.devspd = XMC_USBD_DCFG_DEVSPD_FS; + dcfg.b.descdma = 0U; + xmc_device.device_register->dcfg = dcfg.d32; + /* configure device functions */ + dctl.d32 = xmc_device.device_register->dctl; + dctl.b.sftdiscon = 1U; /* disconnect the device until its connected by the user */ + /* all other config is done by default register value */ + xmc_device.device_register->dctl = dctl.d32; + /* flush the fifos for proper operation */ + XMC_USBD_lFlushTXFifo((uint8_t)0x10U); /* 0x10 == all fifos, see doc */ + XMC_USBD_lFlushRXFifo(); + /* Enable Global Interrupts */ + /* clear interrupt status bits prior to unmasking */ + xmc_device.global_register->gintmsk = 0U; /* disable all interrupts */ + xmc_device.global_register->gintsts = 0xFFFFFFFFU; /* clear all interrupts */ + + gintmsk.d32 = 0U; + /* enable common interrupts */ + gintmsk.b.modemismatch = 1U; + gintmsk.b.otgintr = 1U; + gintmsk.b.sessreqintr = 1U; + /* enable device interrupts */ + gintmsk.b.usbreset = 1U; + gintmsk.b.enumdone = 1U; + gintmsk.b.erlysuspend = 1U; + gintmsk.b.usbsuspend = 1U; + gintmsk.b.wkupintr = 1U; + gintmsk.b.sofintr = 1U; + if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + gintmsk.b.rxstsqlvl = 1U; + } + gintmsk.b.outepintr = 1U; + gintmsk.b.inepintr = 1U; + xmc_device.global_register->gintmsk = gintmsk.d32; + return XMC_USBD_STATUS_OK; +} + +/** + * Uninitializes the USB device + **/ +XMC_USBD_STATUS_t XMC_USBD_Uninitialize() +{ + /* Disconnect the device */ + dctl_data_t dctl; + dctl.d32 = xmc_device.device_register->dctl; + dctl.b.sftdiscon = 1U; + xmc_device.device_register->dctl = dctl.d32; + /* clean up */ + memset((void*)&xmc_device,0U,sizeof(xmc_device)); + return XMC_USBD_STATUS_OK; +} + +/** + * Connects the USB device to host + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceConnect() +{ + /* Just disable softdisconnect */ + dctl_data_t dctl; + dctl.d32 = xmc_device.device_register->dctl; + dctl.b.sftdiscon = 0U; + xmc_device.device_register->dctl = dctl.d32; + return XMC_USBD_STATUS_OK; +} + +/** + * Disconnects the USB device from host + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceDisconnect() +{ + dctl_data_t dctl; + dctl.d32 = xmc_device.device_register->dctl; + dctl.b.sftdiscon = 1U; + xmc_device.device_register->dctl = dctl.d32; + return XMC_USBD_STATUS_OK; +} + +/** + * Gets the USB device state. + **/ +XMC_USBD_STATE_t XMC_USBD_DeviceGetState(const XMC_USBD_t *const obj) +{ + XMC_USBD_STATE_t state={0U}; + state.speed = XMC_USBD_SPEED_FULL; + state.connected = xmc_device.IsConnected; + state.active = XMC_USBD_lDeviceActive(obj); + state.powered = xmc_device.IsPowered; + return state; +} + +/** + * Prepares the endpoint to read next OUT packet + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointReadStart(const uint8_t ep_addr, uint32_t size) +{ + XMC_USBD_EP_t *ep = &xmc_device.ep[ep_addr & (uint8_t)XMC_USBD_EP_NUM_MASK]; + XMC_USBD_STATUS_t result; + + if (ep->outInUse || !ep->isConfigured) + { + result = XMC_USBD_STATUS_ERROR; + } + else + { + /* short the length to buffer size if needed */ + if (size > ep->outBufferSize) + { + size = ep->outBufferSize; + } + /* set ep values */ + ep->xferTotal = size; + ep->xferCount = 0U; + ep->xferLength = 0U; + ep->xferBuffer = ep->outBuffer; + ep->outBytesAvailable = 0U; + XMC_USBD_lStartReadXfer(ep); + result= XMC_USBD_STATUS_OK; + } + return result; +} + +/** + * Reads the number of bytes from the USB OUT endpoint + **/ +int32_t XMC_USBD_EndpointRead(const uint8_t ep_num,uint8_t * buffer,uint32_t length) +{ + XMC_USBD_EP_t *ep = &xmc_device.ep[ep_num]; + if (length > ep->outBytesAvailable) + { + length = ep->outBytesAvailable; + } + memcpy(buffer,&ep->outBuffer[ep->outOffset],length); + ep->outBytesAvailable -= length; + if (ep->outBytesAvailable) + { + ep->outOffset += length; + } + else + { + ep->outOffset = 0U; + } + return (int32_t)length; +} + +/** + * Writes number of bytes in to the USB IN endpoint. + **/ +int32_t XMC_USBD_EndpointWrite(const uint8_t ep_num,const uint8_t * buffer,uint32_t length) +{ + XMC_USBD_EP_t * ep = &xmc_device.ep[ep_num & (uint8_t)XMC_USBD_EP_NUM_MASK]; + int32_t result; + if (!ep->isConfigured) + { + result = (int32_t)XMC_USBD_STATUS_ERROR; + } + else if (ep->inInUse == 1U) + { + result=(int32_t)0; + } + else + { + if (length > ep->inBufferSize) + { + length = ep->inBufferSize; + } + /* copy data into input buffer for DMA and FIFO mode */ + memcpy(ep->inBuffer,(const void *)buffer,length); + ep->xferBuffer = ep->inBuffer; + ep->xferTotal = length; + /* set transfer values */ + ep->xferLength = 0U; + ep->xferCount = 0U; + ep->inInUse = 1U; + /* start the transfer */ + XMC_USBD_lStartWriteXfer(ep); + result=(int32_t)ep->xferTotal; + } + return result; +} + +/** + * Sets the USB device address. + **/ +XMC_USBD_STATUS_t XMC_USBD_DeviceSetAddress(const uint8_t address,const XMC_USBD_SET_ADDRESS_STAGE_t stage) +{ + dcfg_data_t data; + data.d32 = xmc_device.device_register->dcfg; + if (stage == XMC_USBD_SET_ADDRESS_STAGE_SETUP) + { + data.b.devaddr = address; + xmc_device.device_register->dcfg = data.d32; + } + return XMC_USBD_STATUS_OK; +} + +/** + * Set/clear stall on the selected endpoint. + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointStall(const uint8_t ep_addr, const bool stall) +{ + depctl_data_t data; + XMC_USBD_EP_t *ep = &xmc_device.ep[(ep_addr & (uint8_t)XMC_USBD_EP_NUM_MASK)]; + if (stall) + { + if (ep_addr & (uint8_t)XMC_USBD_ENDPOINT_DIRECTION_MASK) + { + /*set stall bit */ + data.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; + data.b.stall = 1U; + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; + } + else + { + /*set stall bit */ + data.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; + data.b.stall = 1U; + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; + } + ep->isStalled = 1U; + } + else + { + /* just clear stall bit */ + if (ep_addr & (uint8_t)XMC_USBD_ENDPOINT_DIRECTION_MASK) + { + data.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; + data.b.stall = 0U; + data.b.setd0pid = 1U; /* reset pid to 0 */ + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; + } + else + { + data.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; + data.b.stall = 0U; + data.b.setd0pid = 1U; /* reset pid to 0 */ + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; + } + ep->isStalled = 0U; + } + return XMC_USBD_STATUS_OK; +} + +/** + * Aborts the data transfer on the selected endpoint + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointAbort(const uint8_t ep_addr) { + XMC_USBD_EP_t *ep = &xmc_device.ep[ep_addr & (uint8_t)XMC_USBD_ENDPOINT_NUMBER_MASK]; + if (ep->address_u.address_st.direction) + { + ep->inInUse = 0U; + } + if (!ep->address_u.address_st.direction) + { + ep->outInUse = 0U; + } + ep->isStalled = 0U; + ep->outBytesAvailable = 0U; + ep->outOffset = 0U; + ep->xferLength = 0U; + ep->xferCount = 0U; + ep->xferTotal = 0U; + + return XMC_USBD_STATUS_OK; +} + +/** + * Configures the given endpoint + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointConfigure(const uint8_t ep_addr, + const XMC_USBD_ENDPOINT_TYPE_t ep_type, + const uint16_t ep_max_packet_size) +{ + daint_data_t daintmsk; + XMC_USBD_EP_t *ep; + daintmsk.d32 = xmc_device.device_register->daintmsk; + ep =&xmc_device.ep[ep_addr & (uint32_t)XMC_USBD_ENDPOINT_NUMBER_MASK]; + memset((void*)ep,0x0U,sizeof(XMC_USBD_EP_t)); /* clear endpoint structure */ + /* do ep configuration */ + ep->address_u.address = ep_addr; + ep->isConfigured = 1U; + ep->maxPacketSize = (uint8_t)ep_max_packet_size; + if (ep->address_u.address != 0U) + { + ep->maxTransferSize = (uint32_t)XMC_USBD_MAX_TRANSFER_SIZE; + } + else + { + ep->maxTransferSize = (uint32_t)XMC_USBD_MAX_TRANSFER_SIZE_EP0; + } + /* transfer buffer */ + ep->inBuffer = XMC_USBD_EP_IN_BUFFER[ep->address_u.address_st.number]; + ep->outBuffer = XMC_USBD_EP_OUT_BUFFER[ep->address_u.address_st.number]; + /* buffer size*/ + ep->inBufferSize = XMC_USBD_EP_IN_BUFFERSIZE[ep->address_u.address_st.number]; + ep->outBufferSize = XMC_USBD_EP_OUT_BUFFERSIZE[ep->address_u.address_st.number]; + /* is in */ + if ((ep->address_u.address_st.direction == 1U) || (ep_type == XMC_USBD_ENDPOINT_TYPE_CONTROL)) + { + depctl_data_t data; + data.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; + /*enable endpoint */ + data.b.usbactep = 1U; + /* set ep type */ + data.b.eptype = (uint8_t)ep_type; + /* set mps */ + if (ep_type == XMC_USBD_ENDPOINT_TYPE_CONTROL) + { + switch(ep_max_packet_size) + { + case (64U): + data.b.mps = 0x0U; + break; + case (32U): + data.b.mps = 0x1U; + break; + case (16U): + data.b.mps = 0x2U; + break; + case (8U): + data.b.mps = 0x3U; + break; + default: + break; + } + } + else + { + data.b.mps = ep_max_packet_size; + } + /* set first data0 pid */ + data.b.setd0pid = 1U; + /* clear stall */ + data.b.stall = 0U; + /* set tx fifo */ + ep->txFifoNum = XMC_USBD_lAssignTXFifo(); /* get tx fifo */ + data.b.txfnum = ep->txFifoNum; + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; /* configure endpoint */ + daintmsk.ep.in |= (uint16_t)((uint16_t)1U << (uint8_t)ep->address_u.address_st.number); /* enable interrupts for endpoint */ + } + if ((ep->address_u.address_st.direction == 0U) || (ep_type == XMC_USBD_ENDPOINT_TYPE_CONTROL)) + { + /* is out */ + depctl_data_t data; + data.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; + /*enable endpoint */ + data.b.usbactep = 1U; + /* set ep type */ + data.b.eptype = (uint8_t)ep_type; + /* set mps */ + if (ep_type == XMC_USBD_ENDPOINT_TYPE_CONTROL) + { + switch(ep_max_packet_size) + { + case (64U): + data.b.mps = 0x0U; + break; + case (32U): + data.b.mps = 0x1U; + break; + case (16U): + data.b.mps = 0x2U; + break; + case (8U): + data.b.mps = 0x3U; + break; + default: + break; + } + } + else + { + data.b.mps = ep_max_packet_size; + } + /* set first data0 pid */ + data.b.setd0pid = 1U; + /* clear stall */ + data.b.stall =(uint8_t) 0U; + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; /* configure endpoint */ + daintmsk.ep.out |=(uint16_t) ((uint16_t)1U << (uint8_t)ep->address_u.address_st.number); /* enable interrupts */ + } + xmc_device.device_register->daintmsk = daintmsk.d32; + return XMC_USBD_STATUS_OK; +} + +/** + * Unconfigure the selected endpoint. + **/ +XMC_USBD_STATUS_t XMC_USBD_EndpointUnconfigure(const uint8_t ep_addr) +{ + XMC_USBD_EP_t *ep = &xmc_device.ep[ep_addr & (uint8_t)XMC_USBD_ENDPOINT_NUMBER_MASK]; + depctl_data_t data; + daint_data_t daintmsk; + XMC_USBD_STATUS_t result; + uint32_t number_temp; + data.d32 = 0U; + daintmsk.d32 = xmc_device.device_register->daintmsk; + number_temp = (uint32_t)((uint32_t)1U << (uint8_t)ep->address_u.address_st.number); + /* if not configured return an error */ + if (!ep->isConfigured) + { + result = XMC_USBD_STATUS_ERROR; + } + else + { + /* disable the endpoint, deactivate it and only send naks */ + data.b.usbactep = 0U; + data.b.epdis = 1U; + data.b.snak = 1U; + data.b.stall = 0U; + ep->isConfigured = 0U; + ep->isStalled = 0U; + ep->outInUse = 0U; + ep->inInUse = 0U; + /* chose register based on the direction. Control Endpoint need both */ + if ((ep->address_u.address_st.direction == 1U) || (ep->type == (uint8_t)XMC_USBD_ENDPOINT_TYPE_CONTROL)) + { + /* disable endpoint configuration */ + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; + /* disable interrupts */ + daintmsk.ep.in = (uint16_t)((uint32_t)daintmsk.ep.in & (~(uint32_t)number_temp)); + } + if ((ep->address_u.address_st.direction == 0U) || (ep->type == (uint8_t)XMC_USBD_ENDPOINT_TYPE_CONTROL)) + { + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; + daintmsk.ep.out = (uint16_t)((uint32_t)daintmsk.ep.out & (~(uint32_t)number_temp)); + if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + xmc_device.device_register->dtknqr4_fifoemptymsk &= ~number_temp; + } + } + xmc_device.device_register->daintmsk = daintmsk.d32; + XMC_USBD_lUnassignFifo(ep->txFifoNum); /* free fifo */ + result = XMC_USBD_STATUS_OK; + } + return result; +} + +/** + * Gets the current USB frame number + **/ +uint16_t XMC_USBD_GetFrameNumber(void) +{ + uint16_t result; + dsts_data_t dsts; + dsts.d32 = xmc_device.device_register->dsts; + result = (uint16_t)dsts.b.soffn; + return result; +} + +/** + * Gets the USB speed enumeration completion status. + * This should not be used for the actual USB enumeration completion status. For the actual USB enumeration status, + * the application layer should check for the completion of USB standard request Set configuration. + **/ +uint32_t XMC_USBD_IsEnumDone(void) +{ + return (uint32_t)((uint8_t)xmc_device.IsConnected && (uint8_t)xmc_device.IsPowered); +} + +/*** + * MISRA C 2004 Deviations + * + * 1. cast from pointer to pointer [MISRA 2004 Rule 11.4] + * 2. cast from pointer to unsigned int [Encompasses MISRA 2004 Rule 11.1], [MISRA 2004 Rule 11.3] + * 3. call to function 'memset()' not made in the presence of a prototype [MISRA 2004 Rule 8.1] + * 4. No explicit type for symbol '_Bool', int assumed + */ +#endif /* defined(USB0) */ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_usbh.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_usbh.c new file mode 100644 index 00000000..f3e5aeb6 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_usbh.c @@ -0,0 +1,1487 @@ +/** + * @file xmc_usbh.c + * @date 2016-06-30 + * + * @cond + ********************************************************************************** + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * (To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + * + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2016-06-30: + * - Initial
+ * 2016-09-01: + * - Removed Keil specific exclusion
+ * + * @endcond + * + */ + +#include +#include + +#include "xmc_usbh.h" + +#if((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC43) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48)) + +/*Function provides transfer result*/ +static uint32_t XMC_USBH_PipeTransferGetResult (XMC_USBH_PIPE_HANDLE pipe_hndl); +/*Updates the power state of the driver*/ +static int32_t XMC_USBH_PowerControl (XMC_USBH_POWER_STATE_t state); + +/*********************************************************** USBH Driver ***************************************************************** */ + +/*Macro to represent USB host driver version*/ +#define XMC_USBH_DRV_VERSION ((uint16_t)((uint16_t)XMC_LIB_MINOR_VERSION << 8U)|XMC_LIB_PATCH_VERSION) +/*Macro used to gate PHY clock and AHB clock*/ +#define XMC_USBH_PHY_CLK_STOP (0x03U) +/*Macro used to ungate PHY clock and AHB clock*/ +#define XMC_USBH_PHY_CLK_UNGATE (0x100U) + +/* Driver Version */ +static const XMC_USBH_DRIVER_VERSION_t xmc_usbh_driver_version = { XMC_USBH_API_VERSION, XMC_USBH_DRV_VERSION }; + +/*Variables to hold selected VBUS port pin*/ +XMC_GPIO_PORT_t * VBUS_port = XMC_GPIO_PORT3; +uint32_t VBUS_pin = 2U; + +/*Array to track nack events on each pipe*/ +bool is_nack[USBH0_MAX_PIPE_NUM]; + +/* Driver Capabilities */ +static const XMC_USBH_CAPABILITIES_t xmc_usbh_driver_capabilities = { + 0x0001U, /* Root HUB available Ports Mask */ + 0U, /* Automatic SPLIT packet handling */ + 1U, /* Signal Connect event */ + 1U, /* Signal Disconnect event */ + 0U /* Signal Overcurrent event */ +}; +/* Driver state and registers */ +static XMC_USBH0_DEVICE_t XMC_USBH0_device/* __attribute__((section ("RW_IRAM1")))*/ = { + (USB0_GLOBAL_TypeDef *)(USB0_BASE), /** Global register interface */ + ((USB0_CH_TypeDef *)(USB0_CH0_BASE)), /** Host channel interface */ + 0, /** Port event callback; set during init */ + 0, /** Pipe event callback; set during init */ + false, /** init status */ + XMC_USBH_POWER_OFF, /** USB Power status */ + false /** Port reset state */ +}; + +/*USB host pipe information. The array stores information related to packet id, data toggle, + * pending data transfer information, periodic transfer interval, received data size etc for each + * pipe.*/ +volatile XMC_USBH0_pipe_t pipe[USBH0_MAX_PIPE_NUM]; + +/* FIFO sizes in bytes (total available memory for FIFOs is 1.25 kB) */ +#define RX_FIFO_SIZE (1128U) /* RxFIFO size */ +#define TX_FIFO_SIZE_NON_PERI (64U) /* Non-periodic Tx FIFO size */ +#define TX_FIFO_SIZE_PERI (1024U) /* Periodic Tx FIFO size */ + +/*Stores data FIFO pointer for each pipe*/ +static uint32_t *XMC_USBH0_dfifo_ptr[USBH0_MAX_PIPE_NUM]; + +/* Local functions */ +/** + * @param enable Enable (XMC_USBH_CLOCK_GATING_ENABLE) or disable(XMC_USBH_CLOCK_GATING_DISABLE) clock gating + * @return None + * \parDescription:
+ * Enable/disable clock gating depending if feature is supported. +*/ +__INLINE static void XMC_lClockGating(uint8_t enable) +{ +#if defined(CLOCK_GATING_SUPPORTED) +if (enable == XMC_USBH_CLOCK_GATING_ENABLE) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); + if (enable == XMC_USBH_CLOCK_GATING_DISABLE) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); +#endif + return; +} + +/** + * @param ptr_ch Pointer to Channel + * @return None + * \parDescription:
+ * Triggers halt of a channel. +*/ +__INLINE static void XMC_lTriggerHaltChannel(USB0_CH_TypeDef *ptr_ch) +{ + ptr_ch->HCINTMSK = USB_CH_HCINT_ChHltd_Msk; /* Enable halt interrupt */ + ptr_ch->HCCHAR |= (uint32_t)(USB_CH_HCCHAR_ChEna_Msk | USB_CH_HCCHAR_ChDis_Msk); + return; +} + +/** + * @param ptr_pipe Pointer to Pipe + * @param ptr_ch Pointer to Channel + * @return bool \n + * true = success,\n + * false = fail + * \parDescription:
+ * Start transfer on Pipe. The function uses transfer complete interrupts to transfer data more than maximum + * packet size. It takes care of updating data toggle information in subsequent packets related to the same data transfer. +*/ +static bool XMC_lStartTransfer (XMC_USBH0_pipe_t *ptr_pipe, USB0_CH_TypeDef *ptr_ch) { + uint32_t hcchar; + uint32_t hctsiz; + uint32_t hcintmsk; + uint32_t num_remaining_transfer; + uint32_t num_remaining_fifo; + uint32_t num_remaining_queue; + uint32_t txsts = 0U; + uint32_t pckt_num; + uint32_t max_pckt_size; + uint8_t *ptr_src = ptr_pipe->data; + uint32_t *ptr_dest = NULL; + uint16_t cnt; + uint32_t loc_index; + bool status; + + if (!(XMC_USBH0_device.global_register->HPRT & USB_HPRT_PrtConnSts_Msk)) + { + status = false; + } + else + { + /* Save channel characteristic register to local variable */ + hcchar = ptr_ch->HCCHAR; + /* Save transfer size register to local variable */ + hctsiz = ptr_ch->HCTSIZ_BUFFERMODE; + hcintmsk = 0U; + cnt = 0U; + + /* Prepare transfer */ + /* Reset EPDir (transfer direction = output) and enable channel */ + hcchar &= (uint32_t)(~(uint32_t)(USB_CH_HCCHAR_EPDir_Msk | USB_CH_HCCHAR_ChDis_Msk)); + hcchar |= (uint32_t)USB_CH_HCCHAR_ChEna_Msk; + + /* Enable default interrupts needed for all transfers */ + hcintmsk = (USB_CH_HCINTMSK_XactErrMsk_Msk | + USB_CH_HCINTMSK_XferComplMsk_Msk | + USB_CH_HCINTMSK_NakMsk_Msk | + USB_CH_HCINTMSK_StallMsk_Msk) ; + /* Keep PID */ + hctsiz &= (uint32_t)USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk; + + /* Packet specific setup */ + switch (ptr_pipe->packet & XMC_USBH_PACKET_TOKEN_Msk) { + case XMC_USBH_PACKET_IN: + /* set transfer direction to input */ + hcchar |= (uint32_t)USB_CH_HCCHAR_EPDir_Msk; + /* Enable IN transfer specific interrupts */ + hcintmsk |= (uint32_t)( USB_CH_HCINTMSK_DataTglErrMsk_Msk | + USB_CH_HCINTMSK_BblErrMsk_Msk | + USB_CH_HCINTMSK_AckMsk_Msk | + USB_CH_HCINTMSK_NakMsk_Msk ) ; + break; + case XMC_USBH_PACKET_OUT: + break; + case XMC_USBH_PACKET_SETUP: + hctsiz &= (uint32_t)~USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk ; + hctsiz |= (uint32_t)USB_CH_HCTSIZx_DPID_MDATA; + break; + default: + break; + } + /* Prepare PID */ + switch (ptr_pipe->packet & XMC_USBH_PACKET_DATA_Msk) { + case XMC_USBH_PACKET_DATA0: + hctsiz &= (uint32_t)~USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk; + hctsiz |= (uint32_t)USB_CH_HCTSIZx_DPID_DATA0; + break; + case XMC_USBH_PACKET_DATA1: + hctsiz &= (uint32_t)~USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk; + hctsiz |= (uint32_t)USB_CH_HCTSIZx_DPID_DATA1; + break; + default: + break; + } + + /* Prepare odd/even frame */ + if ((XMC_USBH0_device.global_register->HFNUM & 1U) != 0U) { + hcchar &= (uint32_t)~USB_CH_HCCHAR_OddFrm_Msk; + } else { + hcchar |= (uint32_t)USB_CH_HCCHAR_OddFrm_Msk; + } + + /* Get transfer type specific status */ + switch (ptr_pipe->ep_type) { + case XMC_USBH_ENDPOINT_CONTROL: + case XMC_USBH_ENDPOINT_BULK: + if (!(hcchar & USB_CH_HCCHAR_EPDir_Msk)) { + txsts = XMC_USBH0_device.global_register->GNPTXSTS; + } + break; + case XMC_USBH_ENDPOINT_ISOCHRONOUS: + case XMC_USBH_ENDPOINT_INTERRUPT: + if (!(hcchar & USB_CH_HCCHAR_EPDir_Msk)) { + txsts = XMC_USBH0_device.global_register->HPTXSTS; + } + break; + default: + break; + } + + /* Calculate remaining transfer size */ + num_remaining_transfer = ptr_pipe->num - ptr_pipe->num_transferred_total; + /* Limit transfer to available space inside fifo/queue if OUT transaction */ + if ((uint32_t)(hcchar & USB_CH_HCCHAR_EPDir_Msk) == 0U) { + max_pckt_size = ptr_pipe->ep_max_packet_size; + num_remaining_fifo = (uint32_t)((uint32_t)(txsts & 0x0000FFFFU) << 2); + num_remaining_queue = (uint32_t)((uint32_t)(txsts & 0x00FF0000U) >> 16); + if (num_remaining_transfer > num_remaining_fifo) { + num_remaining_transfer = num_remaining_fifo; + } + pckt_num = (uint32_t)((num_remaining_transfer + (max_pckt_size - 1U)) / max_pckt_size); + if (pckt_num > num_remaining_queue) { + pckt_num = num_remaining_queue; + } + if (num_remaining_transfer > (pckt_num * max_pckt_size)) { + num_remaining_transfer = pckt_num * max_pckt_size; + } + cnt = (uint16_t)((num_remaining_transfer + 3U) / 4U); + ptr_src = ptr_pipe->data + ptr_pipe->num_transferred_total; + loc_index = ((USB0_CH_TypeDef *)ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers)); + ptr_dest = (uint32_t *)XMC_USBH0_dfifo_ptr[loc_index]; + /* For OUT/SETUP transfer num_transferring represents num of bytes to be sent */ + ptr_pipe->num_transferring = num_remaining_transfer; + } + else { + /* For IN transfer num_transferring is zero */ + ptr_pipe->num_transferring = 0U; + } + /* Set packet count and transfer size */ + if (num_remaining_transfer != 0U) { + hctsiz |= (((num_remaining_transfer + ptr_pipe->ep_max_packet_size) - 1U) / ptr_pipe->ep_max_packet_size) << 19U; + hctsiz |= num_remaining_transfer; + } else { /* Zero length packet */ + hctsiz |= ((uint32_t)1U << USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos); /* Packet count = 1 */ + hctsiz |= 0U; /* Transfer size = 0 */ + } + NVIC_DisableIRQ (USB0_0_IRQn); + ptr_ch->HCINTMSK = hcintmsk; /* Enable channel interrupts */ + ptr_ch->HCTSIZ_BUFFERMODE = hctsiz; /* Write ch transfer size */ + ptr_ch->HCCHAR = hcchar; /* Write ch characteristics */ + while (cnt != 0U) { /* Load data */ +#if defined __TASKING__/*tasking*/ + *ptr_dest = *((__unaligned uint32_t *)ptr_src); +#else/* defined (__GNUC__) || defined (__CC_ARM) || defined (__ICCARM__)*/ + *ptr_dest = *((__packed uint32_t *)ptr_src); +#endif + ptr_src += 4U; + cnt--; + } + NVIC_EnableIRQ (USB0_0_IRQn); /* Enable OTG interrupt */ + status = true; + } + return status; +} + +/* USB driver API functions */ +/** + * @return \ref XMC_USBH_DRIVER_VERSION_t + * \parDescription:
+ * Get driver version. +*/ +static XMC_USBH_DRIVER_VERSION_t XMC_USBH_GetVersion (void) { return xmc_usbh_driver_version; } + +/** + * @return \ref XMC_USBH_CAPABILITIES_t + * \parDescription:
+ * Get driver capabilities. +*/ +static XMC_USBH_CAPABILITIES_t XMC_USBH_GetCapabilities (void) { return xmc_usbh_driver_capabilities; } + +/** + * @param cb_port_event Pointer to port event callback function \ref ARM_USBH_SignalPortEvent + * @param cb_pipe_event Pointer to pipe event callback function \ref ARM_USBH_SignalPipeEvent + * @return int32_t \ref Execution_status. 0 if execution is successful. + * + * \parDescription:
+ * Initialize USB Host Interface. Registers callback functions to be executed on port event and pipe event. + * Initializes FIFO address for each pipe. Configures P3.2 as the VBUS charge pump enable pin.\n + * + * \parRelated APIs:
+ * XMC_USBH_Select_VBUS(), XMC_USBH_Uninitialize() \n +*/ +static int32_t XMC_USBH_Initialize (XMC_USBH_SignalPortEvent_t cb_port_event, + XMC_USBH_SignalPipeEvent_t cb_pipe_event) { + + uint32_t channel; + int32_t status = XMC_USBH_DRIVER_OK; + if (XMC_USBH0_device.init_done == true) + { + /*return ok since initialized*/ + } + else + { + /* assign callbacks */ + XMC_USBH0_device.SignalPortEvent_cb = cb_port_event; + XMC_USBH0_device.SignalPipeEvent_cb = cb_pipe_event; + + /* assign fifo start addresses */ + for (channel = 0U; channel < USBH0_MAX_PIPE_NUM; channel++) { + XMC_USBH0_dfifo_ptr[channel] = (uint32_t *)((uint32_t)USB0_BASE + ((channel + 1U) * 0x01000U)); + } + + XMC_GPIO_SetMode(VBUS_port, (uint8_t)VBUS_pin, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1); + + XMC_USBH0_device.init_done = true; + } + return status; +} + +/** + * @return int32_t \ref Execution_status. Returns 0 to indicate success. + * \parDescription:
+ * De-initialize USB Host Interface. Sets the driver power state as powered off. Disables VBUS.\n + * + * \parRelated APIs:
+ * XMC_USBH_Select_VBUS(), XMC_USBH_Initialize(), XMC_USBH_PortVbusOnOff() \n +*/ +static int32_t XMC_USBH_Uninitialize (void) { + XMC_USBH0_device.init_done = false; + (void)XMC_USBH_PowerControl(XMC_USBH_POWER_OFF); + return XMC_USBH_DRIVER_OK; +} + +/** + * @param state Power state. \ref XMC_USBH_POWER_STATE_t + * @return int32_t \ref Execution_status. Returns 0 if successful. + * \parDescription:
+ * Control USB Host Interface Power. If power state is set to \ref XMC_USBH_POWER_FULL, + * it initializes the peripheral and enables VBUS. If power state is set to \ref XMC_USBH_POWER_OFF, + * disables the peripheral and the VBUS.\n + * + * \parRelated APIs:
+ * XMC_USBH_Select_VBUS(), XMC_USBH_Initialize(), XMC_USBH_PortVbusOnOff(), XMC_USBH_Uninitialize() \n +*/ +static int32_t XMC_USBH_PowerControl (XMC_USBH_POWER_STATE_t state) { + int32_t status = XMC_USBH_DRIVER_OK; + uint32_t loc_value; + switch (state) { + case XMC_USBH_POWER_LOW: + status = XMC_USBH_DRIVER_ERROR_UNSUPPORTED; + break; + case XMC_USBH_POWER_OFF: + NVIC_DisableIRQ (USB0_0_IRQn); + NVIC_ClearPendingIRQ (USB0_0_IRQn); /* Clear pending interrupt */ + XMC_USBH0_device.power_state = state; /* Clear powered flag */ + XMC_USBH0_device.global_register->GAHBCFG &= (uint32_t)(~USB_GAHBCFG_GlblIntrMsk_Msk); /* Disable USB interrupts */ + XMC_lClockGating((uint8_t)XMC_USBH_CLOCK_GATING_ENABLE); /* Enable Clock Gating */ + XMC_USBH0_device.global_register->PCGCCTL |= (uint32_t)USB_PCGCCTL_StopPclk_Msk; /* Stop PHY clock */ + XMC_SCU_POWER_DisableUsb(); /* Disable Power USB */ + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0); /* reset USB */ + XMC_USBH0_device.port_reset_active = false; /* Reset variables */ + memset((void *)(pipe), 0, (USBH0_MAX_PIPE_NUM * sizeof(XMC_USBH0_pipe_t))); + break; + case XMC_USBH_POWER_FULL: + if (XMC_USBH0_device.init_done == false) + { + status = XMC_USBH_DRIVER_ERROR; + break; + } /* not initialized */ + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_FULL) + { + status = XMC_USBH_DRIVER_OK; + break; + } /* already powered */ + XMC_lClockGating((uint8_t)XMC_USBH_CLOCK_GATING_DISABLE); /* disable clock gating */ + (void)XMC_USBH_osDelay(2U); + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0); /* deassert reset USB */ + (void)XMC_USBH_osDelay(2U); + (void)XMC_USBH_osDelay(100U); + XMC_SCU_POWER_EnableUsb(); /* Enable Power USB */ + + /* On-chip Full-speed PHY */ + XMC_USBH0_device.global_register->PCGCCTL &= (uint32_t)~USB_PCGCCTL_StopPclk_Msk; /* Start PHY clock */ + XMC_USBH0_device.global_register->GUSBCFG |= (uint32_t)USB_GUSBCFG_PHYSel_Msk; /* Full-speed transceiver */ + + while ((XMC_USBH0_device.global_register->GRSTCTL & USB_GRSTCTL_AHBIdle_Msk) == 0U) /* wait until AHB master state machine is idle */ + { + /*Wait*/ + } + + XMC_USBH0_device.global_register->GRSTCTL |= (uint32_t)USB_GRSTCTL_CSftRst_Msk; /* Core soft reset */ + + while ((XMC_USBH0_device.global_register->GRSTCTL & USB_GRSTCTL_CSftRst_Msk) != 0U) /* wait soft reset confirmation */ + { + /*Wait*/ + } + (void)XMC_USBH_osDelay(100U); + + XMC_USBH0_device.port_reset_active = false; /* Reset variables */ + memset((void *)(pipe), 0, (USBH0_MAX_PIPE_NUM * sizeof(XMC_USBH0_pipe_t))); + + /*Created local copy of GUSBCFG to avoid side effects*/ + loc_value = XMC_USBH0_device.global_register->GUSBCFG; + if (((loc_value & USB_GUSBCFG_ForceHstMode_Msk) == 0U) || \ + ((loc_value & USB_GUSBCFG_ForceDevMode_Msk) != 0U)) + { + XMC_USBH0_device.global_register->GUSBCFG &= (uint32_t)~USB_GUSBCFG_ForceDevMode_Msk; /* Clear force device mode */ + XMC_USBH0_device.global_register->GUSBCFG |= (uint32_t)USB_GUSBCFG_ForceHstMode_Msk; /* Force host mode */ + (void)XMC_USBH_osDelay(100U); + } + + /* FS only, even if HS is supported */ + XMC_USBH0_device.global_register->HCFG |= (uint32_t)(0x200U | USB_CH_HCFG_FSLSSUP(1)); + + /* Rx FIFO setting */ + XMC_USBH0_device.global_register->GRXFSIZ = (RX_FIFO_SIZE/4U); + /* Non-periodic Tx FIFO setting */ + XMC_USBH0_device.global_register->GNPTXFSIZ_HOSTMODE = (((uint32_t)(TX_FIFO_SIZE_NON_PERI/4U) << 16) | (RX_FIFO_SIZE / 4U)); + /* Periodic Tx FIFO setting */ + XMC_USBH0_device.global_register->HPTXFSIZ = ((uint32_t)(TX_FIFO_SIZE_PERI / 4U) << 16U) | ((RX_FIFO_SIZE + TX_FIFO_SIZE_NON_PERI) / 4U); + /* Enable channel interrupts */ + XMC_USBH0_device.global_register->HAINTMSK = ((uint32_t)1U << USBH0_MAX_PIPE_NUM) - 1U; + /* Unmask interrupts */ + XMC_USBH0_device.global_register->GINTMSK_HOSTMODE = ( + USB_GINTSTS_HOSTMODE_DisconnInt_Msk | + USB_GINTMSK_HOSTMODE_HChIntMsk_Msk | + USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk | + USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk | + USB_GINTMSK_HOSTMODE_SofMsk_Msk | + USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk + ) ; + /* Set powered state */ + XMC_USBH0_device.power_state = state; + /* Enable interrupts */ + XMC_USBH0_device.global_register->GAHBCFG |= (uint32_t)USB_GAHBCFG_GlblIntrMsk_Msk; + /* Set highest interrupt priority */ + NVIC_SetPriority (USB0_0_IRQn, 0U); + NVIC_EnableIRQ (USB0_0_IRQn); + break; + default: + status = XMC_USBH_DRIVER_ERROR_UNSUPPORTED; + } + return status; +} + +/** + * @param port Root HUB Port Number. Only one port(0) is supported. + * @param vbus VBUS state - \n + * - \b false VBUS off + * - \b true VBUS on + * @return int32_t \ref Execution_status. Returns 0 if successful. + * + * \parDescription:
+ * Set USB port VBUS on/off. +*/ +static int32_t XMC_USBH_PortVbusOnOff (uint8_t port, bool vbus) { + int32_t status = XMC_USBH_DRIVER_OK; + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (port != 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + if (vbus != 0U) { + /* Port power on */ + XMC_USBH0_device.global_register->HPRT |= (uint32_t)USB_HPRT_PrtPwr_Msk; + XMC_GPIO_SetMode(VBUS_port, (uint8_t)VBUS_pin, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1); + } else { + /* Port power off */ + XMC_USBH0_device.global_register->HPRT &= (uint32_t)~USB_HPRT_PrtPwr_Msk; + XMC_GPIO_SetMode(VBUS_port, (uint8_t)VBUS_pin, XMC_GPIO_MODE_INPUT_TRISTATE); + } + } + } + return status; +} + +/** + * @param port Root HUB Port Number. Only one port(0) is supported. + * @return int32_t Execution status. \ref Execution_status + * \parDescription:
+ * Do USB port reset. Port reset should honor the requirement of 50ms delay before enabling. + * The function depends on implementation of XMC_USBH_osDelay() for 1ms delay to achieve required delay. + * +*/ +static int32_t XMC_USBH_PortReset (uint8_t port) { + uint32_t hprt; + int32_t status = XMC_USBH_DRIVER_OK; + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (port != 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + + XMC_USBH0_device.port_reset_active = true; + hprt = XMC_USBH0_device.global_register->HPRT; + hprt &= (uint32_t)~USB_HPRT_PrtEna_Msk; /* Disable port */ + hprt |= (uint32_t)USB_HPRT_PrtRst_Msk; /* Port reset */ + XMC_USBH0_device.global_register->HPRT = hprt; + (void)XMC_USBH_osDelay(50U); /* wait at least 50ms */ + hprt &= (uint32_t)~USB_HPRT_PrtRst_Msk; /* Clear port reset */ + XMC_USBH0_device.global_register->HPRT = hprt; + (void)XMC_USBH_osDelay(50U); /* wait for ISR */ + + /*Wait for the port to be enabled*/ + while ((XMC_USBH0_device.global_register->HPRT & USB_HPRT_PrtEna_Msk) == 0U) + { + /*wait*/ + } + + if (XMC_USBH0_device.port_reset_active == true) + { + XMC_USBH0_device.port_reset_active = false; + status = XMC_USBH_DRIVER_ERROR; /* reset not confirmed inside ISR */ + } + } + + return status; +} + +/** + * @param port USB port number. Only one port(0) is supported. + * @return \ref Execution_status + * \parDescription:
+ * Suspend USB Port (stop generating SOFs).\n + * + * \parRelated APIs:
+ * XMC_USBH_PortResume() \n +*/ +static int32_t XMC_USBH_PortSuspend (uint8_t port) +{ + int32_t status = XMC_USBH_DRIVER_OK; + uint32_t hprt; + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (port != 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + hprt = XMC_USBH0_device.global_register->HPRT; + hprt &= (uint32_t)~(USB_HPRT_PrtEna_Msk); + hprt |= (uint32_t)USB_HPRT_PrtSusp_Msk; + XMC_USBH0_device.global_register->HPRT = hprt; + /* Stop PHY clock after suspending the bus*/ + XMC_USBH0_device.global_register->PCGCCTL |= XMC_USBH_PHY_CLK_STOP; + + } + } + return status; +} + +/** + * @param port USB port number. Only one port(0) is supported. + * @return \ref Execution_status + * \parDescription:
+ * Resume suspended USB port (start generating SOFs).\n + * + * \parRelated APIs:
+ * XMC_USBH_PortSuspend() \n +*/ +static int32_t XMC_USBH_PortResume (uint8_t port) +{ + int32_t status = XMC_USBH_DRIVER_OK; + uint32_t hprt; + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (port != 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + /*Ungate PHY clock*/ + XMC_USBH0_device.global_register->PCGCCTL = XMC_USBH_PHY_CLK_UNGATE; + /*Set resume bit*/ + hprt = XMC_USBH0_device.global_register->HPRT; + hprt &= (uint32_t)~(USB_HPRT_PrtEna_Msk); + hprt |= (uint32_t)USB_HPRT_PrtRes_Msk; + XMC_USBH0_device.global_register->HPRT = hprt; + + (void)XMC_USBH_osDelay(20U); + + hprt = XMC_USBH0_device.global_register->HPRT; + hprt &= (uint32_t)~(USB_HPRT_PrtEna_Msk); + hprt &= (uint32_t)~((uint32_t)USB_HPRT_PrtRes_Msk); + XMC_USBH0_device.global_register->HPRT = hprt; + } + } + + return status; +} + +/** + * @param port USB port number. Only one port(0) is supported. + * @return XMC_USBH_PORT_STATE_t Port State + * + * \parDescription:
+ * Get current USB port state. The state indicates if the port is connected, port speed + * and port overcurrent status. +*/ +static XMC_USBH_PORT_STATE_t XMC_USBH_PortGetState (uint8_t port) +{ + XMC_USBH_PORT_STATE_t port_state = { 0U, 0U, 0U }; + uint32_t hprt; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + /*Do not update the port state*/ + } + else + { + if (port != 0U) + { + /*Do not update the port state*/ + } + else + { + hprt = XMC_USBH0_device.global_register->HPRT; + if(((hprt & USB_HPRT_PrtConnSts_Msk) != 0U)) + { + port_state.connected = 1U; + } + else + { + port_state.connected = 0U; + } + port_state.overcurrent = 0U; + + switch ((uint32_t)((uint32_t)(hprt & USB_HPRT_PrtSpd_Msk) >> USB_HPRT_PrtSpd_Pos)) { + case 1U: /* Full speed */ + port_state.speed = XMC_USBH_SPEED_FULL; + break; + default: + break; + } + } + } + return port_state; +} + +/** + * @param dev_addr Device address + * @param dev_speed Device speed + * @param hub_addr Hub address. This value should be 0 since hub is not supported. + * @param hub_port USB port number. Only one port(0) is supported. + * @param ep_addr Device endpoint address \n + * - ep_addr.0..3: Address \n + * - ep_addr.7: Direction\n + * @param ep_type Endpoint type (ARM_USB_ENDPOINT_xxx) + * @param ep_max_packet_size Endpoint maximum packet size + * @param ep_interval Endpoint polling interval + * @return XMC_USBH_PIPE_HANDLE Pipe handle is a pointer to pipe hardware base address. + * + * \parDescription:
+ * Create/allocate a pipe configured with input parameters. The function looks for an unused pipe and configures with input parameters. + * + * \parRelated APIs:
+ * XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeReset(), XMC_USBH_PipeTransfer() \n +*/ +static XMC_USBH_PIPE_HANDLE XMC_USBH_PipeCreate (uint8_t dev_addr, uint8_t dev_speed, uint8_t hub_addr, uint8_t hub_port, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_max_packet_size, uint8_t ep_interval) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + uint32_t i; + uint32_t loc_val; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + ptr_ch = (USB0_CH_TypeDef *)NULL; + } + else + { + /* get first free pipe available */ + ptr_ch = (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers); + + for (i = 0U; i < USBH0_MAX_PIPE_NUM; i++) { + if ((ptr_ch->HCCHAR & 0x3FFFFFFFU) == 0U) + { + break; + } + ptr_ch++; + } + + /* free pipe found? */ + if (i == USBH0_MAX_PIPE_NUM) + { + ptr_ch = (USB0_CH_TypeDef *)NULL; + } + else + { + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + + memset((void *)ptr_pipe, 0, sizeof(XMC_USBH0_pipe_t)); /* Initialize pipe structure */ + + /* Fill in all fields of Endpoint Descriptor */ + /*Get the end point direction from the MSB of address*/ + loc_val = 0U; + if (((ep_addr >> 7U) & 0x1U) == 0U) + { + loc_val = 1U; + } + ptr_ch->HCCHAR = ((uint32_t)(USB_CH_HCCHARx_MPS(ep_max_packet_size))| + USB_CH_HCCHARx_EPNUM(ep_addr)) | + (uint32_t)(USB_CH_HCCHAR_EPDir_Msk * loc_val) | + (USB_CH_HCCHARx_EPTYPE (ep_type) ) | + (USB_CH_HCCHARx_DEVADDR (dev_addr) ) ; + /* Store Pipe settings */ + ptr_pipe->ep_max_packet_size = ep_max_packet_size; + ptr_pipe->ep_type = ep_type; + switch (ep_type) { + case XMC_USBH_ENDPOINT_CONTROL: + case XMC_USBH_ENDPOINT_BULK: + break; + case XMC_USBH_ENDPOINT_ISOCHRONOUS: + case XMC_USBH_ENDPOINT_INTERRUPT: + if (ep_interval > 0U) { + ptr_pipe->interval_reload = ep_interval; + } + ptr_pipe->interval = ptr_pipe->interval_reload; + loc_val = ((((uint32_t)ep_max_packet_size >> 11U) + 1U) & 3U); + ptr_ch->HCCHAR |= (uint32_t)USB_CH_HCCHARx_MCEC(loc_val); + break; + default: + break; + } + } + } + return ((XMC_USBH_EP_HANDLE)ptr_ch); +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @param dev_addr Device address to be configured for the pipe. + * @param dev_speed Device speed class. + * @param hub_addr Hub address. It should be 0 since hub is not supported. + * @param hub_port USB port number. Only one port(0) is supported. + * @param ep_max_packet_size Endpoint maximum packet size + * @return Execution_status + * + * \parDescription:
+ * Modify an existing pipe with input parameters. It can be used to configure the pipe after receiving configuration details from the device. + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeDelete(), XMC_USBH_PipeReset(), XMC_USBH_PipeTransfer() \n +*/ +static int32_t XMC_USBH_PipeModify (XMC_USBH_PIPE_HANDLE pipe_hndl, uint8_t dev_addr, uint8_t dev_speed, uint8_t hub_addr, uint8_t hub_port, uint16_t ep_max_packet_size) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + uint32_t hcchar; + int32_t status = XMC_USBH_DRIVER_OK; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (pipe_hndl == 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + ptr_ch = (USB0_CH_TypeDef *)(pipe_hndl); + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + if (ptr_pipe->in_use != 0U) + { + status = XMC_USBH_DRIVER_ERROR_BUSY; + } + else + { + /* Fill in all fields of channel */ + hcchar = ptr_ch->HCCHAR; + /* Clear fields */ + hcchar &= (uint32_t)~(USB_CH_HCCHAR_MPS_Msk | USB_CH_HCCHAR_DevAddr_Msk) ; + /* Set fields */ + hcchar |= (uint32_t)(USB_CH_HCCHARx_MPS(ep_max_packet_size) | (USB_CH_HCCHARx_DEVADDR(dev_addr))); + ptr_ch->HCCHAR = hcchar; + + ptr_pipe->ep_max_packet_size = ep_max_packet_size; + } + } + } + + return status; +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @return Execution_status + * + * \parDescription:
+ * Delete pipe from active pipes list. After it is deleted, it can be assigned to new pipe request. + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeReset(), XMC_USBH_PipeTransfer() \n +*/ +static int32_t XMC_USBH_PipeDelete (XMC_USBH_PIPE_HANDLE pipe_hndl) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + int32_t status = XMC_USBH_DRIVER_OK; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (pipe_hndl == 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + ptr_ch = (USB0_CH_TypeDef *)(pipe_hndl); + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + if (ptr_pipe->in_use != 0U) + { + status = XMC_USBH_DRIVER_ERROR_BUSY; + } + else + { + ptr_ch->HCCHAR = 0U; + ptr_ch->HCINT = 0U; + ptr_ch->HCINTMSK = 0U; + ptr_ch->HCTSIZ_BUFFERMODE = 0U; + + memset((void *)ptr_pipe, 0, sizeof(XMC_USBH0_pipe_t)); + } + } + } + + return status; +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @return Execution_status + * \parDescription:
+ * Reset pipe by clearing the interrupt mask and resetting the transfer control register.\n + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeTransfer() \n +*/ +static int32_t XMC_USBH_PipeReset (XMC_USBH_PIPE_HANDLE pipe_hndl) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + int32_t status = XMC_USBH_DRIVER_OK; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + if (pipe_hndl == 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + ptr_ch = (USB0_CH_TypeDef *)(pipe_hndl); + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + if (ptr_pipe->in_use != 0U) + { + status = XMC_USBH_DRIVER_ERROR_BUSY; + } + else + { + ptr_ch->HCINT = 0U; + ptr_ch->HCINTMSK = 0U; + ptr_ch->HCTSIZ_BUFFERMODE = 0U; + } + } + } + return status; +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @param packet Packet information with bit masks to represent packet data toggle information and packet type.\n + * \ref XMC_USBH_PACKET_DATA0 / \ref XMC_USBH_PACKET_DATA1, \ref XMC_USBH_PACKET_SETUP / + * \ref XMC_USBH_PACKET_OUT / \ref XMC_USBH_PACKET_IN + * @param data Pointer to buffer with data to send or for received data to be stored. + * @param num Number of data bytes to transfer + * @return Execution_status + * + * \parDescription:
+ * Transfer packets through USB Pipe. Handles transfer of multiple packets using the pipe transfer complete event. + * The pipe event callback function will be called when the transfer is completed.\n + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeReset() \n +*/ +static int32_t XMC_USBH_PipeTransfer (XMC_USBH_PIPE_HANDLE pipe_hndl, uint32_t packet, uint8_t *data, uint32_t num) { + XMC_USBH0_pipe_t *ptr_pipe; + int32_t status = XMC_USBH_DRIVER_OK; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + + if(!(((((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_OUT) || + ((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_IN))) || + ((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_SETUP ))) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + if (pipe_hndl == 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + if ((XMC_USBH0_device.global_register->HPRT & USB_HPRT_PrtConnSts_Msk) == 0U) + { + status = XMC_USBH_DRIVER_ERROR; + } + else + { + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[((USB0_CH_TypeDef *)pipe_hndl - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + if (ptr_pipe->in_use != 0U) + { + status = XMC_USBH_DRIVER_ERROR_BUSY; + } + else + { + /* Prepare transfer information */ + ptr_pipe->packet = packet; + ptr_pipe->data = data; + ptr_pipe->num = num; + ptr_pipe->num_transferred_total = 0U; + ptr_pipe->num_transferring = 0U; + ptr_pipe->in_use = 0U; + ptr_pipe->transfer_active = 0U; + ptr_pipe->interrupt_triggered = 0U; + ptr_pipe->event = 0U; + + if ((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) && (ptr_pipe->interval != 0U)) { + ptr_pipe->in_use = 1U; /* transfer will be started inside interrupt (SOF) */ + } else { + ptr_pipe->transfer_active = 1U; + ptr_pipe->in_use = 1U; + if(XMC_lStartTransfer (ptr_pipe, (USB0_CH_TypeDef *)pipe_hndl) == false) + { + status = XMC_USBH_DRIVER_ERROR; + } + } + } + } + } + } + } + return status; +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @return uint32_t Number of successfully transferred data bytes + * + * \parDescription:
+ * Get result of USB Pipe transfer. + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeTransfer() \n +*/ +static uint32_t XMC_USBH_PipeTransferGetResult (XMC_USBH_PIPE_HANDLE pipe_hndl) { + uint32_t status; + if (pipe_hndl == 0U) + { + status = 0U; + } + else + { + status = (pipe[((USB0_CH_TypeDef *)pipe_hndl - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))].num_transferred_total); + } + return status; +} + +/** + * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. + * @return Execution_status + * + * \parDescription:
+ * Abort current USB Pipe transfer.\n + * + * \parRelated APIs:
+ * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeTransfer() \n +*/ +static int32_t XMC_USBH_PipeTransferAbort (XMC_USBH_PIPE_HANDLE pipe_hndl) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + uint32_t timeout; + int32_t status = XMC_USBH_DRIVER_ERROR; + + ptr_ch = (USB0_CH_TypeDef *) pipe_hndl; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + /*Error in power state*/ + } + else + { + if (pipe_hndl == 0U) + { + status = XMC_USBH_DRIVER_ERROR_PARAMETER; + } + else + { + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + + if (ptr_pipe->in_use != 0U) { + ptr_pipe->in_use = 0U; + /* Disable channel if not yet halted */ + if ((ptr_ch->HCINT & USB_CH_HCINT_ChHltd_Msk) == 0U) + { + if (ptr_ch->HCCHAR & USB_CH_HCCHAR_ChEna_Msk) + { + ptr_ch->HCINTMSK = 0U; + (void)XMC_USBH_osDelay(1U); + if (ptr_ch->HCINT & USB_CH_HCINT_NAK_Msk) { + ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* Clear all interrupts */ + status = XMC_USBH_DRIVER_OK; + } + else + { + ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* Clear all interrupts */ + ptr_ch->HCCHAR = (uint32_t)(ptr_ch->HCCHAR | USB_CH_HCCHAR_ChEna_Msk | USB_CH_HCCHAR_ChDis_Msk); + + /* wait until channel is halted */ + for (timeout = 0U; timeout < 5000U; timeout++) { + if (ptr_ch->HCINT & USB_CH_HCINT_ChHltd_Msk) { + ptr_ch->HCINT = USB_CH_HCINTx_ALL; + status = XMC_USBH_DRIVER_OK; + } + } + } + } + } + } + } + } + + return status; +} + +/** + * @return Frame number. + * + * \parDescription:
+ * Get current USB Frame Number. +*/ +static uint16_t XMC_USBH_GetFrameNumber (void) +{ + uint16_t status; + + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) + { + status = 0U; + } + else + { + status = (uint16_t)((XMC_USBH0_device.global_register->HFNUM) & 0xFFFU); + } + return status; +} + +/** + * @param gintsts USB port interrupt status flag. + * + * \parDescription:
+ * USB host interrupt handler. It updates port and pipe state information based on different events + * generated by the peripheral. It propagates the port events to the callback function registered by the user + * during initialization. When a pipe transfer complete event is detected, it checks if any further data is available + * to be transmitted on the same pipe and continues transmission until data is available. A pipe event is also propagated + * to the user provided pipe event callback function. A transfer complete event will be propagated only when all the data + * is transmitted for an OUT transaction. + * +*/ +void XMC_USBH_HandleIrq (uint32_t gintsts) { + XMC_USBH0_pipe_t *ptr_pipe; + USB0_CH_TypeDef *ptr_ch; + uint32_t hprt, haint, hcint, pktcnt, mpsiz; + uint32_t ch; + uint8_t *ptr_data; + uint32_t *dfifo; + uint32_t grxsts, bcnt, dat, len, len_rest; + + /* Host port interrupt */ + if ((gintsts & USB_GINTSTS_HOSTMODE_PrtInt_Msk) != 0U) { + hprt = XMC_USBH0_device.global_register->HPRT; + /* Clear port enable */ + XMC_USBH0_device.global_register->HPRT = hprt & (uint32_t)(~USB_HPRT_PrtEna_Msk); + if ((hprt & USB_HPRT_PrtConnDet_Msk) != 0U) { + XMC_USBH0_device.global_register->HCFG = (0x200U | (USB_CH_HCFG_FSLSPCS(1) | + USB_CH_HCFG_FSLSSUP(1))); + /* Ignore connect under reset */ + if (XMC_USBH0_device.port_reset_active == false) { + XMC_USBH0_device.SignalPortEvent_cb(0U, XMC_USBH_EVENT_CONNECT); + } + } + if ((hprt & USB_HPRT_PrtEnChng_Msk) != 0U) { /* If port enable changed */ + if ((hprt & USB_HPRT_PrtEna_Msk) != 0U) { /* If device connected */ + if (XMC_USBH0_device.port_reset_active == true) { + XMC_USBH0_device.port_reset_active = false; + XMC_USBH0_device.SignalPortEvent_cb(0U, XMC_USBH_EVENT_RESET); + } + } + } + } + + /* Disconnect interrupt */ + if ((gintsts & USB_GINTSTS_HOSTMODE_DisconnInt_Msk) != 0U) { + XMC_USBH0_device.global_register->GINTSTS_HOSTMODE = USB_GINTSTS_HOSTMODE_DisconnInt_Msk; /* Clear disconnect interrupt */ + /* Ignore disconnect under reset */ + if ( XMC_USBH0_device.port_reset_active == false) { + ptr_ch = (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers); + ptr_pipe = (XMC_USBH0_pipe_t *)(pipe); + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { + if (ptr_pipe->in_use != 0U) { + ptr_pipe->in_use = 0U; + ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* Clear all interrupts */ + ptr_ch->HCINTMSK = USB_CH_HCINT_ChHltd_Msk; /* Enable halt interrupt */ + ptr_ch->HCCHAR |= (uint32_t)(USB_CH_HCCHAR_ChEna_Msk | USB_CH_HCCHAR_ChDis_Msk); /* Activate Halt */ + XMC_USBH0_device.SignalPipeEvent_cb((XMC_USBH_EP_HANDLE)ptr_ch, XMC_USBH_EVENT_BUS_ERROR); + } + ptr_ch++; + ptr_pipe++; + } + XMC_USBH0_device.SignalPortEvent_cb(0U, XMC_USBH_EVENT_DISCONNECT); + } + } + /* Handle receive fifo not-empty interrupt */ + if ((gintsts & USB_GINTSTS_HOSTMODE_RxFLvl_Msk) != 0U) { + XMC_USBH0_device.global_register->GINTMSK_HOSTMODE &= (uint32_t)~USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk; + grxsts = (XMC_USBH0_device.global_register->GRXSTSP_HOSTMODE); + /* IN Data Packet received ? */ + if ((uint32_t)((grxsts >> 17U) & 0x0FU) == (uint32_t)USB_GRXSTSR_HOSTMODE_PktSts_IN_DATA_PKT) { + ch = (uint32_t)(grxsts & USB_GRXSTSR_DEVICEMODE_EPNum_Msk); + bcnt = ((uint32_t)(grxsts & USB_GRXSTSR_DEVICEMODE_BCnt_Msk) >> USB_GRXSTSR_DEVICEMODE_BCnt_Pos); + dfifo = (uint32_t *)XMC_USBH0_dfifo_ptr[ch]; + ptr_data = pipe[ch].data + pipe[ch].num_transferred_total; + len = bcnt / 4U; /* Received number of 32-bit data */ + len_rest = bcnt & 3U; /* Number of bytes left */ + /* Read data from fifo */ + /* Read 32 bit sized data */ + while (len != 0U) { +#if defined __TASKING__/*tasking*/ + *((__unaligned uint32_t *)ptr_data) = *dfifo; +#else /* defined (__GNUC__) || defined (__CC_ARM) || defined (__ICCARM__)*/ + *((__packed uint32_t *)ptr_data) = *dfifo; +#endif + + ptr_data += 4U; + len--; + } + /* Read 8 bit sized data */ + if (len_rest != 0U) { +#if defined __TASKING__/*tasking*/ + dat = *((__unaligned uint32_t *)dfifo); +#else /* defined (__GNUC__) || defined (__CC_ARM) || defined (__ICCARM__)*/ + dat = *((__packed uint32_t *)dfifo); +#endif + while (len_rest != 0U) { + *ptr_data = (uint8_t)dat; + ptr_data++; + dat >>= 8; + len_rest--; + } + } + pipe[ch].num_transferring += bcnt; + pipe[ch].num_transferred_total += bcnt; + } + XMC_USBH0_device.global_register->GINTMSK_HOSTMODE |= (uint32_t)USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk; + } + + /* Handle sof interrupt */ + if ((gintsts & USB_GINTSTS_HOSTMODE_Sof_Msk) != 0U) { /* If start of frame interrupt */ + XMC_USBH0_device.global_register->GINTSTS_HOSTMODE = USB_GINTSTS_HOSTMODE_Sof_Msk; /* Clear SOF interrupt */ + ptr_pipe = (XMC_USBH0_pipe_t *)(pipe); + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { + /* If interrupt transfer is active handle period (interval) */ + if ((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) && (ptr_pipe->in_use == 1U)) { + if (ptr_pipe->interval != 0U) + { + ptr_pipe->interval--; + if (ptr_pipe->interval == 0U) + { + ptr_pipe->interval = ptr_pipe->interval_reload; + ptr_pipe->interrupt_triggered = 1U; + } + } + } + ptr_pipe++; + } + } + + /* Handle host ctrl interrupt */ + if ((gintsts & USB_GINTSTS_HOSTMODE_HChInt_Msk) != 0U) { + haint = XMC_USBH0_device.global_register->HAINT; + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { + /* Check for interrupt of all channels */ + if ((haint & (uint32_t)((uint32_t)1U << ch)) != 0U) { + haint &= (uint32_t)~((uint32_t)1U << ch); + ptr_ch = (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers) + ch; + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[ch]); + /*Local variable for HCINT*/ + dat = ptr_ch->HCINT; + hcint = (uint32_t)(dat & ptr_ch->HCINTMSK); + if ((hcint & USB_CH_HCINT_ChHltd_Msk) != 0U) { /* channel halted ? */ + ptr_ch->HCINTMSK = 0U; /* disable all channel interrupts */ + ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* clear all interrupts */ + ptr_pipe->transfer_active = 0U; /* set status transfer not active */ + hcint = 0U; + } + if ((hcint & USB_CH_HCINT_XferCompl_Msk) != 0U) { /* data transfer finished ? */ + ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* clear all interrupts */ + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) == 0U) { /* endpoint OUT ? */ + ptr_ch->HCINTMSK = 0U; /* disable all channel interrupts */ + ptr_pipe->transfer_active = 0U; /* transfer not in progress */ + ptr_pipe->num_transferred_total += ptr_pipe->num_transferring; /* admin OUT transfer status */ + ptr_pipe->num_transferring = 0U; /* admin OUT transfer status */ + if (ptr_pipe->num_transferred_total == ptr_pipe->num) { /* all bytes transferred ? */ + ptr_pipe->in_use = 0U; /* release pipe */ + ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_TRANSFER_COMPLETE; /* prepare event notification */ + } + hcint = 0U; + } + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) { /* endpoint IN ? */ + ptr_pipe->in_use = 0U; /* release pipe */ + ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_TRANSFER_COMPLETE; /* prepare event notification */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + } + } + if ((hcint & USB_CH_HCINTMSK_AckMsk_Msk) != 0U) { /* ACK received ? */ + ptr_ch->HCINT = USB_CH_HCINTMSK_AckMsk_Msk; /* clear ACK interrupt */ + is_nack[ch] = false; + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) { /* endpoint IN ? */ + if ((ptr_pipe->num != ptr_pipe->num_transferred_total) && /* if all data was not transferred */ + (ptr_pipe->num_transferring != 0U) && /* if zero-length packet was not received */ + ((ptr_pipe->num_transferred_total%ptr_pipe->ep_max_packet_size) == 0U)){ /* if short packet was not received */ + ptr_ch->HCCHAR |= (uint32_t)USB_CH_HCCHAR_ChEna_Msk; /* trigger next transfer */ + } + } else { /* endpoint OUT */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + } + hcint = 0U; + } + /*local variable for HCCHAR*/ + dat = ptr_ch->HCCHAR; + if (((hcint & (USB_CH_HCINTMSK_StallMsk_Msk | /* STALL */ + USB_CH_HCINTMSK_NakMsk_Msk | /* or NAK */ + USB_CH_HCINTx_ERRORS )) != 0U) && /* or transaction error */ + ((dat & USB_CH_HCCHAR_EPDir_Msk) == 0U)) + { /* and endpoint OUT */ + + pktcnt = (uint32_t)((ptr_ch->HCTSIZ_BUFFERMODE & USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk) /* administrate OUT transfer status */ + >> USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos); + mpsiz = (ptr_ch->HCCHAR ) & 0x000007FFU; + if ((ptr_pipe->num_transferring >= mpsiz) && (pktcnt > 0U)) { + ptr_pipe->num_transferred_total += (uint32_t)(ptr_pipe->num_transferring - (mpsiz * pktcnt)); + } + ptr_pipe->num_transferring = 0U; + } + + if ((hcint & USB_CH_HCINTMSK_NakMsk_Msk)!=0U) { /* if NAK */ + is_nack[ch] = true; + ptr_pipe->event |= (uint8_t)XMC_USBH_EVENT_HANDSHAKE_NAK; + ptr_ch->HCINT = USB_CH_HCINTMSK_NakMsk_Msk; /* clear NAK interrupt */ + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) { /* endpoint IN ? */ + if (ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) { /* is endpoint of type interrupt ? */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt (after halted will be restarted in next sof) */ + } else { /* is endpoint not of type interrupt ?*/ + ptr_ch->HCCHAR |= (uint32_t)USB_CH_HCCHAR_ChEna_Msk; /* trigger next transfer */ + } + } else { /* If endpoint OUT */ /* endpoint OUT ? */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + } + hcint = 0U; + } + + if ((hcint & USB_CH_HCINTMSK_StallMsk_Msk) != 0U) { /* if STALL */ + /*Reset the packet data toggle*/ + ptr_ch->HCINT = USB_CH_HCINTMSK_StallMsk_Msk; /* clear STALL interrupt */ + ptr_pipe->in_use = 0U; /* release pipe */ + ptr_pipe->packet &= (uint32_t)(~XMC_USBH_PACKET_DATA_Msk); + ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA0; + ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_HANDSHAKE_STALL; /* prepare event notification */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + hcint = 0U; + } + if ((hcint & USB_CH_HCINTx_ERRORS) != 0U) { /* if transaction error */ + ptr_ch->HCINT = USB_CH_HCINTx_ERRORS; /* clear all error interrupt */ + ptr_pipe->in_use = 0U; /* release pipe */ + ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_BUS_ERROR; /* prepare event notification */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + hcint = 0U; + } + if ((ptr_pipe->transfer_active == 0U) && (ptr_pipe->in_use == 0U) && (ptr_pipe->event != 0U)) { + XMC_USBH0_device.SignalPipeEvent_cb((XMC_USBH_EP_HANDLE)ptr_ch, (uint32_t)ptr_pipe->event); + ptr_pipe->event = 0U; + } + } + } + } + /*Check if remote wakeup event detected*/ + if ((gintsts & USB_GINTSTS_HOSTMODE_WkUpInt_Msk) != 0U) + { + XMC_USBH0_device.global_register->GINTSTS_HOSTMODE = USB_GINTSTS_HOSTMODE_WkUpInt_Msk; /* Clear wakeup interrupt */ + /*Recover PHY clock*/ + XMC_USBH0_device.global_register->PCGCCTL = XMC_USBH_PHY_CLK_UNGATE; + /*Callback function execution*/ + XMC_USBH0_device.SignalPortEvent_cb(0U, XMC_USBH_EVENT_REMOTE_WAKEUP); + } + + /* Handle restarts of unfinished transfers (due to NAK or ACK) */ + ptr_pipe = (XMC_USBH0_pipe_t *)(pipe); + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { + if ((ptr_pipe->in_use == 1U) && (ptr_pipe->transfer_active == 0U)) { + /* Restart periodic transfer if not in progress and interval expired */ + if (ptr_pipe->ep_type != (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) + { + /*Data toggle if NACK not received*/ + if (!is_nack[ch]) + { + switch (ptr_pipe->packet & (uint32_t)XMC_USBH_PACKET_DATA_Msk) + { + case XMC_USBH_PACKET_DATA0: + ptr_pipe->packet &= (uint32_t)~XMC_USBH_PACKET_DATA_Msk; + ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA1; + break; + case XMC_USBH_PACKET_DATA1: + ptr_pipe->packet &= (uint32_t)~XMC_USBH_PACKET_DATA_Msk; + ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA0; + break; + default: + break; + } + } + else + { + is_nack[ch] = false; + } + } + if (((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT)&&(ptr_pipe->interrupt_triggered == 1U))|| + (ptr_pipe->ep_type != (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT)) + { + ptr_pipe->interrupt_triggered = 0U; + ptr_pipe->transfer_active = 1U; + (void)XMC_lStartTransfer (ptr_pipe, (((USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers)) + ch)); + } + } + ptr_pipe++; + } +} + +/*Function provides host mode interrupt status*/ +uint32_t XMC_USBH_GetInterruptStatus(void) +{ + return XMC_USBH0_device.global_register->GINTSTS_HOSTMODE; +} + +/*Function selects the port pin used as DRIVEVBUS*/ +void XMC_USBH_Select_VBUS(XMC_GPIO_PORT_t* port, uint32_t pin) +{ + VBUS_port = port; + VBUS_pin = pin; + + /*Configure the port pin alternate function*/ + XMC_GPIO_SetMode(VBUS_port, (uint8_t)VBUS_pin, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1); +} + +/*Function asserts the remote wakeup request by device by clearing the resume bit*/ +void XMC_USBH_TurnOffResumeBit(void) +{ + uint32_t hprt; + /*Clear resume bit*/ + hprt = XMC_USBH0_device.global_register->HPRT; + hprt &= (uint32_t)~(USB_HPRT_PrtEna_Msk); + hprt &= (uint32_t)~((uint32_t)USB_HPRT_PrtRes_Msk); + XMC_USBH0_device.global_register->HPRT = hprt; +} + + + +/*USB host driver assembling all the implementation into a single CMSIS compliant structure type*/ +XMC_USBH_DRIVER_t Driver_USBH0 = { + XMC_USBH_GetVersion, + XMC_USBH_GetCapabilities, + XMC_USBH_Initialize, + XMC_USBH_Uninitialize, + XMC_USBH_PowerControl, + XMC_USBH_PortVbusOnOff, + XMC_USBH_PortReset, + XMC_USBH_PortSuspend, + XMC_USBH_PortResume, + XMC_USBH_PortGetState, + XMC_USBH_PipeCreate, + XMC_USBH_PipeModify, + XMC_USBH_PipeDelete, + XMC_USBH_PipeReset, + XMC_USBH_PipeTransfer, + XMC_USBH_PipeTransferGetResult, + XMC_USBH_PipeTransferAbort, + XMC_USBH_GetFrameNumber +}; + + +/*Weak definition of delay function*/ +__WEAK uint8_t XMC_USBH_osDelay(uint32_t MS) +{ + /*A precise time delay implementation for this function has to be provided*/ + while (1) + { + /*Wait*/ + } +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_usic.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_usic.c new file mode 100644 index 00000000..d6f3b0c7 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_usic.c @@ -0,0 +1,373 @@ +/** + * @file xmc_usic.c + * @date 2015-09-01 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial draft
+ * - Documentation improved
+ * + * 2015-05-08: + * - Clearing bit fields PDIV, PCTQ, PPPEN in XMC_USIC_CH_SetBaudrate() API
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API
+ * + * 2015-08-27: + * - Added APIs for external input for BRG configuration:XMC_USIC_CH_ConfigExternalInputSignalToBRG()
+ * + * 2015-08-28: + * - Added asserts to XMC_USIC_CH_ConfigExternalInputSignalToBRG()
+ * + * 2015-09-01: + * - Fixed warning in the asserts
+ * + * @endcond + * + */ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include "xmc_usic.h" +#include "xmc_scu.h" + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define USIC_CH_INPR_Msk (0x7UL) + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel) +{ + XMC_ASSERT("XMC_USIC_CH_Enable: channel not valid", XMC_USIC_IsChannelValid(channel)); + + if ((channel == XMC_USIC0_CH0) || (channel == XMC_USIC0_CH1)) + { + XMC_USIC_Enable(XMC_USIC0); + } +#if defined(USIC1) + else if((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1)) + { + XMC_USIC_Enable(XMC_USIC1); + } +#endif +#if defined(USIC2) + else if((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1)) + { + XMC_USIC_Enable(XMC_USIC2); + } +#endif + else + { + XMC_ASSERT("USIC module not available", 0U/*Always*/); + } + + /* USIC channel switched on*/ + channel->KSCFG = (USIC_CH_KSCFG_MODEN_Msk | USIC_CH_KSCFG_BPMODEN_Msk); + while ((channel->KSCFG & USIC_CH_KSCFG_MODEN_Msk) == 0U) + { + /* Wait till the channel is enabled */ + } + + /* Set USIC channel in IDLE mode */ + channel->CCR &= (uint32_t)~USIC_CH_CCR_MODE_Msk; +} + +void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel) +{ + channel->KSCFG = (uint32_t)((channel->KSCFG & (~USIC_CH_KSCFG_MODEN_Msk)) | USIC_CH_KSCFG_BPMODEN_Msk); +} + +XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling) +{ + XMC_USIC_CH_STATUS_t status; + + uint32_t peripheral_clock; + + uint32_t clock_divider; + uint32_t clock_divider_min; + + uint32_t pdiv; + uint32_t pdiv_int; + uint32_t pdiv_int_min; + + uint32_t pdiv_frac; + uint32_t pdiv_frac_min; + + /* The rate and peripheral clock are divided by 100 to be able to use only 32bit arithmetic */ + if ((rate >= 100U) && (oversampling != 0U)) + { + peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency() / 100U; + rate = rate / 100U; + + clock_divider_min = 1U; + pdiv_int_min = 1U; + pdiv_frac_min = 0x3ffU; + + for(clock_divider = 1023U; clock_divider > 0U; --clock_divider) + { + pdiv = ((peripheral_clock * clock_divider) / (rate * oversampling)); + pdiv_int = pdiv >> 10U; + pdiv_frac = pdiv & 0x3ffU; + + if ((pdiv_int < 1024U) && (pdiv_frac < pdiv_frac_min)) + { + pdiv_frac_min = pdiv_frac; + pdiv_int_min = pdiv_int; + clock_divider_min = clock_divider; + } + } + + channel->FDR = XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL | + (clock_divider_min << USIC_CH_FDR_STEP_Pos); + + channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk | + USIC_CH_BRG_PDIV_Msk | + USIC_CH_BRG_PCTQ_Msk | + USIC_CH_BRG_PPPEN_Msk)) | + ((oversampling - 1U) << USIC_CH_BRG_DCTQ_Pos) | + ((pdiv_int_min - 1U) << USIC_CH_BRG_PDIV_Pos); + + status = XMC_USIC_CH_STATUS_OK; + } + else + { + status = XMC_USIC_CH_STATUS_ERROR; + } + + return status; +} + +void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, + const uint16_t pdiv, + const uint32_t oversampling, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) +{ + XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Divider out of range", ((1U < pdiv) || (pdiv < 1024U))); + XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Oversampling out of range", ((1U < oversampling) || (oversampling < 32U))); + + /* Setting the external input frequency source through DX1 */ + XMC_USIC_CH_SetBRGInputClockSource(channel, XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T); + + /* Setting the trigger combination mode */ + XMC_USIC_CH_SetInputTriggerCombinationMode(channel,XMC_USIC_CH_INPUT_DX1,combination_mode); + + /* Configuring the dividers and oversampling */ + channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk | + USIC_CH_BRG_PDIV_Msk | + USIC_CH_BRG_PCTQ_Msk | + USIC_CH_BRG_PPPEN_Msk)) | + (((oversampling) - 1U) << USIC_CH_BRG_DCTQ_Pos) | + (((pdiv) - 1U) << USIC_CH_BRG_PDIV_Pos); +} + +void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel, + const uint32_t data_pointer, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit) +{ + /* Disable FIFO */ + channel->TBCTR &= (uint32_t)~USIC_CH_TBCTR_SIZE_Msk; + + /* LOF = 0, A standard transmit buffer event occurs when the filling level equals the limit value and gets + * lower due to transmission of a data word + * STBTEN = 0, the trigger of the standard transmit buffer event is based on the transition of the fill level + * from equal to below the limit, not the fact being below + */ + channel->TBCTR = (uint32_t)(channel->TBCTR & (uint32_t)~(USIC_CH_TBCTR_LIMIT_Msk | + USIC_CH_TBCTR_DPTR_Msk | + USIC_CH_TBCTR_SIZE_Msk)) | + (uint32_t)((limit << USIC_CH_TBCTR_LIMIT_Pos) | + (data_pointer << USIC_CH_TBCTR_DPTR_Pos) | + ((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos)); +} + + +void XMC_USIC_CH_RXFIFO_Configure(XMC_USIC_CH_t *const channel, + const uint32_t data_pointer, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit) +{ + /* Disable FIFO */ + channel->RBCTR &= (uint32_t)~USIC_CH_RBCTR_SIZE_Msk; + + /* LOF = 1, A standard receive buffer event occurs when the filling level equals the limit value and gets bigger + * due to the reception of a new data word + */ + channel->RBCTR = (uint32_t)((channel->RBCTR & (uint32_t)~(USIC_CH_RBCTR_LIMIT_Msk | + USIC_CH_RBCTR_DPTR_Msk | + USIC_CH_RBCTR_LOF_Msk)) | + ((limit << USIC_CH_RBCTR_LIMIT_Pos) | + (data_pointer << USIC_CH_RBCTR_DPTR_Pos) | + ((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos) | + (uint32_t)USIC_CH_RBCTR_LOF_Msk)); +} + +void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit) +{ + /* Disable FIFO */ + channel->TBCTR &= (uint32_t)~USIC_CH_TBCTR_SIZE_Msk; + + /* STBTEN = 0, the trigger of the standard transmit buffer event is based on the transition of the fill level + * from equal to below the limit, not the fact being below + */ + channel->TBCTR = (uint32_t)((uint32_t)(channel->TBCTR & (uint32_t)~USIC_CH_TBCTR_LIMIT_Msk) | + (limit << USIC_CH_TBCTR_LIMIT_Pos) | + ((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos)); +} + +void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit) +{ + /* Disable FIFO */ + channel->RBCTR &= (uint32_t)~USIC_CH_RBCTR_SIZE_Msk; + + channel->RBCTR = (uint32_t)((uint32_t)(channel->RBCTR & (uint32_t)~USIC_CH_RBCTR_LIMIT_Msk) | + (limit << USIC_CH_RBCTR_LIMIT_Pos) | + ((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos)); +} + +void XMC_USIC_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + channel->INPR = (uint32_t)((channel->INPR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) | + (service_request << (uint32_t)interrupt_node)); +} + +void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + channel->TBCTR = (uint32_t)((channel->TBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) | + (service_request << (uint32_t)interrupt_node)); +} + +void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, + const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) +{ + channel->RBCTR = (uint32_t)((channel->RBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) | + (service_request << (uint32_t)interrupt_node)); +} + +void XMC_USIC_Enable(XMC_USIC_t *const usic) +{ + if (usic == USIC0) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0); +#endif + } +#if defined(USIC1) + else if (usic == USIC1) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1); +#endif + } +#endif +#if defined(USIC2) + else if (usic == USIC2) + { +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2); +#endif + } +#endif + else + { + XMC_ASSERT("USIC module not available", 0/*Always*/); + } +} + +void XMC_USIC_Disable(XMC_USIC_t *const usic) +{ + if (usic == (XMC_USIC_t *)USIC0) + { +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0); +#endif + } +#if defined(USIC1) + else if (usic == (XMC_USIC_t *)USIC1) + { +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1); +#endif + } +#endif +#if defined(USIC2) + else if (usic == (XMC_USIC_t *)USIC2) + { +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2); +#endif + } +#endif + else + { + XMC_ASSERT("USIC module not available", 0/*Always*/); + } + +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_vadc.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_vadc.c new file mode 100644 index 00000000..30298969 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_vadc.c @@ -0,0 +1,2121 @@ +/** + * @file xmc_vadc.c + * @date 2016-06-17 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-15: + * - Initial
+ * + * 2015-02-20: + * - Revised for XMC1201 device.
+ * + * 2015-04-27: + * - Added new APIs for SHS.
+ * - Added New APIs for trigger edge selection.
+ * - Added new APIs for Queue flush entries, boundary selection, Boundary node pointer.
+ * - Revised GatingMode APIs and EMUX Control Init API.
+ * + * 2015-06-20: + * - Removed version macros and declaration of GetDriverVersion API + * + * 2015-06-25: + * - BFL configuration in channel initialization fixed. + * + * 2015-07-28: + * - CLOCK_GATING_SUPPORTED and PERIPHERAL_RESET_SUPPORTED macros used + * - Clubbed the macro definitions for XMC13 XMC12 and XMC14 + * - Clubbed the macro definitions for XMC44 XMC47 and XMC48 + * - New APIs Created. + * - XMC_VADC_GLOBAL_SetIndividualBoundary + * - XMC_VADC_GROUP_SetIndividualBoundary + * - XMC_VADC_GROUP_GetAlias + * - XMC_VADC_GROUP_GetInputClass + * - XMC_VADC_GROUP_ChannelSetIclass + * - XMC_VADC_GROUP_ChannelGetResultAlignment + * - XMC_VADC_GROUP_ChannelGetInputClass + * - XMC_VADC_GROUP_SetResultSubtractionValue + * + * 2015-12-01: + * - Fixed the analog calibration voltage for XMC1100 to external reference upper supply range. + * - Fixed the XMC_VADC_GLOBAL_StartupCalibration() for XMC1100. + * + * 2016-06-17: + * - New macros added XMC_VADC_SHS_FULL_SET_REG, XMC_VADC_RESULT_PRIORITY_AVAILABLE + * and XMC_VADC_SYNCTR_START_LOCATION + * - New Enum added XMC_VADC_SHS_GAIN_LEVEL_t and XMC_VADC_SYNCTR_EVAL_t + * - Fixed the EVAL configuration in API XMC_VADC_GROUP_CheckSlaveReadiness and XMC_VADC_GROUP_IgnoreSlaveReadiness + * - New APIs added are: + * - XMC_VADC_GROUP_SetSyncSlaveReadySignal + * - XMC_VADC_GROUP_ChannelGetAssertedEvents + * - XMC_VADC_GROUP_GetAssertedResultEvents + * - XMC_VADC_GROUP_SetResultRegPriority + * - XMC_VADC_GROUP_SetSyncReadySignal + * - XMC_VADC_GROUP_GetSyncReadySignal + * - XMC_VADC_GROUP_GetResultRegPriority + * + * 2017-01-11: + * - Fix assertion in XMC_VADC_GROUP_CheckSlaveReadiness() and XMC_VADC_GROUP_IgnoreSlaveReadiness() checking the slave_group parameter + * + * @endcond + * + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include + +/********************************************************************************************************************* + * MACROS + ********************************************************************************************************************/ +#define XMC_VADC_MAX_ICLASS_SET (2U) /**< Defines the maximum number of conversion parameter sets */ +#define XMC_VADC_NUM_EMUX_INTERFACES (2U) /**< Defines the maximum number of external multiplexer interfaces */ + +#define XMC_VADC_RESULT_LEFT_ALIGN_10BIT (2U) /**< Defines the 10 bit converted result register left align mask. It \ + is used in the XMC_VADC_GLOBAL_SetCompareValue() API */ + +#define XMC_VADC_SYNCTR_START_LOCATION (3U) /**< Defines the location in SYNCTR needed for calculations*/ +/********************************************************************************************************************* + * ENUMS + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * DATA STRUCTURES + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * GLOBAL DATA + ********************************************************************************************************************/ + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) + +#if (XMC_VADC_MAXIMUM_NUM_GROUPS == 4U) +static VADC_G_TypeDef *const g_xmc_vadc_group_array[XMC_VADC_MAXIMUM_NUM_GROUPS] = {(VADC_G_TypeDef*)(void*)VADC_G0, + (VADC_G_TypeDef*)(void*)VADC_G1, + (VADC_G_TypeDef*)(void*)VADC_G2, + (VADC_G_TypeDef*)(void*)VADC_G3 }; +#else +static VADC_G_TypeDef *const g_xmc_vadc_group_array[XMC_VADC_MAXIMUM_NUM_GROUPS] = {(VADC_G_TypeDef* )(void *) VADC_G0, + (VADC_G_TypeDef* )(void *)VADC_G1 }; +#endif + +#endif + +/********************************************************************************************************************* + * LOCAL ROUTINES + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/*API to enable the VADC Module*/ +void XMC_VADC_GLOBAL_EnableModule(void) +{ + /* + * Enable Out of Range Comparator for ADC channels pins P2.2to P2.9. This hack is applicable only for XMC1xxx devices + * and in particular the G11 step. + * + * Please refer to the XMC1000 Errata sheet V1.4 released 2014-06 Errata ID : ADC_AI.003 Additonal bit to enable ADC + * function + */ + +#if defined (COMPARATOR) + COMPARATOR->ORCCTRL = (uint32_t)0xFF; +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_VADC); +#endif + +#if defined(PERIPHERAL_RESET_SUPPORTED) + /* Reset the Hardware */ + XMC_SCU_RESET_DeassertPeripheralReset((XMC_SCU_PERIPHERAL_RESET_t)XMC_SCU_PERIPHERAL_RESET_VADC ); +#endif +} + +/*API to Disable the VADC Module*/ +void XMC_VADC_GLOBAL_DisableModule(void) +{ +#if defined(PERIPHERAL_RESET_SUPPORTED) + /* Reset the Hardware */ + XMC_SCU_RESET_AssertPeripheralReset((XMC_SCU_PERIPHERAL_RESET_t)XMC_SCU_PERIPHERAL_RESET_VADC ); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_VADC); +#endif + +} + + +/* API to initialize global resources */ +void XMC_VADC_GLOBAL_Init(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CONFIG_t *config) +{ +#if (XMC_VADC_GROUP_AVAILABLE == 0U) + uint32_t reg; +#endif + XMC_ASSERT("XMC_VADC_GLOBAL_Init:Wrong Module Pointer", (global_ptr == VADC)) + + /* Enable the VADC module*/ + XMC_VADC_GLOBAL_EnableModule(); + + global_ptr->CLC = (uint32_t)(config->clc); + + /* Clock configuration */ + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) + global_ptr->GLOBCFG = (uint32_t)(config->clock_config.globcfg | (uint32_t)(VADC_GLOBCFG_DIVWC_Msk)); +#endif + + /* ICLASS-0 configuration */ + global_ptr->GLOBICLASS[0] = (uint32_t)(config->class0.globiclass); + + /* ICLASS-1 configuration */ + global_ptr->GLOBICLASS[1] = (uint32_t)(config->class1.globiclass); + + + /*Result generation related configuration */ + global_ptr->GLOBRCR = (uint32_t)(config->globrcr); + +#if (XMC_VADC_BOUNDARY_AVAILABLE == 1U) + + /* Boundaries */ + global_ptr->GLOBBOUND = (uint32_t)(config->globbound); + +#endif + + /* Configure the SHS register that are needed for XMC11xx devices*/ +#if (XMC_VADC_GROUP_AVAILABLE == 0U) + + /* Enabling the Analog part of the converter*/ + reg = SHS0->SHSCFG | SHS_SHSCFG_SCWC_Msk; + reg &= ~(SHS_SHSCFG_ANOFF_Msk); + SHS0->SHSCFG = reg; + + /* From the Errata sheet of XMC1100 V1.7*/ + XMC_VADC_CONV_ENABLE_FOR_XMC11 = 1U; +#endif + +} + +/* API to Set the Global IClass registers*/ +void XMC_VADC_GLOBAL_InputClassInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CLASS_t config, + const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num) +{ + + XMC_ASSERT("XMC_VADC_GLOBAL_InputClassInit:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_InputClassInit:Wrong Conversion Type", ((conv_type) <= XMC_VADC_GROUP_CONV_EMUX)) + XMC_ASSERT("XMC_VADC_GLOBAL_InputClassInit:Wrong ICLASS set number", (set_num < XMC_VADC_MAX_ICLASS_SET)) + +#if(XMC_VADC_EMUX_AVAILABLE == 1U) + if (conv_type == XMC_VADC_GROUP_CONV_STD ) + { +#endif + global_ptr->GLOBICLASS[set_num] = config.globiclass & + (uint32_t)(VADC_GLOBICLASS_CMS_Msk | VADC_GLOBICLASS_STCS_Msk); +#if(XMC_VADC_EMUX_AVAILABLE == 1U) + } + else + { + global_ptr->GLOBICLASS[set_num] = config.globiclass & (uint32_t)(VADC_GLOBICLASS_CME_Msk | VADC_GLOBICLASS_STCE_Msk); + } +#endif +} + +/* API to enable startup calibration feature */ +void XMC_VADC_GLOBAL_StartupCalibration(XMC_VADC_GLOBAL_t *const global_ptr) +{ +#if (XMC_VADC_GROUP_AVAILABLE == 1U) + uint8_t i; + VADC_G_TypeDef *group_ptr; +#endif + + XMC_ASSERT("XMC_VADC_GLOBAL_StartupCalibration:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->GLOBCFG |= (uint32_t)VADC_GLOBCFG_SUCAL_Msk; + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) + /* Loop until all active groups finish calibration */ + for(i=0U; iARBCFG) & (uint32_t)VADC_G_ARBCFG_ANONS_Msk) + { + /* This group is active. Loop until it finishes calibration */ + while((group_ptr->ARBCFG) & (uint32_t)VADC_G_ARBCFG_CAL_Msk) + { + /* NOP */ + } + } + } +#else + /* Loop until it finishes calibration */ + while ((((SHS0->SHSCFG) & (uint32_t)SHS_SHSCFG_STATE_Msk) >> (uint32_t)SHS_SHSCFG_STATE_Pos) == + XMC_VADC_SHS_START_UP_CAL_ACTIVE ) + { + /* NOP */ + } +#endif +} + +/* API to set boudaries for result of conversion. Should the boundaries be violated, interrupts are generated */ +#if (XMC_VADC_BOUNDARY_AVAILABLE == 1U) +void XMC_VADC_GLOBAL_SetBoundaries(XMC_VADC_GLOBAL_t *const global_ptr, + const uint32_t boundary0, + const uint32_t boundary1) +{ + uint32_t globbound; + + XMC_ASSERT("XMC_VADC_GLOBAL_SetBoundaries:Wrong Module Pointer", (global_ptr == VADC)) + + globbound = 0U; + globbound |= (uint32_t) (boundary0 << VADC_GLOBBOUND_BOUNDARY0_Pos); + globbound |= (uint32_t) (boundary1 << VADC_GLOBBOUND_BOUNDARY1_Pos); + + global_ptr->GLOBBOUND = globbound; +} + +/* API to set an individual boundary for conversion results */ +void XMC_VADC_GLOBAL_SetIndividualBoundary(XMC_VADC_GLOBAL_t *const global_ptr, + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value) +{ + + uint32_t globbound; + + XMC_ASSERT("XMC_VADC_GLOBAL_SetBoundaries:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_SetBoundaries:Wrong Boundary Selection", + ((XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND0 == selection) || + (XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND1 == selection))) + + /* Program the Boundary registers */ + globbound = global_ptr->GLOBBOUND; + + if (XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND0 == selection) + { + globbound &= ~((uint32_t) VADC_GLOBBOUND_BOUNDARY0_Msk); + globbound |= (uint32_t) ((uint32_t) boundary_value << VADC_GLOBBOUND_BOUNDARY0_Pos); + } + else if (XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND1 == selection) + { + globbound &= ~((uint32_t) VADC_GLOBBOUND_BOUNDARY1_Msk); + globbound |= (uint32_t) ((uint32_t) boundary_value << VADC_GLOBBOUND_BOUNDARY1_Pos); + } + else + { + /* For MISRA*/ + } + global_ptr->GLOBBOUND = globbound; + +} + +#endif + +/* API to set compare value for the result register. Result of conversion is compared against this compare value */ +void XMC_VADC_GLOBAL_SetCompareValue(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_RESULT_SIZE_t compare_val) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SetCompareValue:Wrong Module Pointer", (global_ptr == VADC)) + + global_ptr->GLOBRES &= ~((uint32_t)VADC_GLOBRES_RESULT_Msk); + global_ptr->GLOBRES |= (uint32_t)((uint32_t)compare_val << XMC_VADC_RESULT_LEFT_ALIGN_10BIT); +} + +/* API to retrieve the result of comparison */ +XMC_VADC_FAST_COMPARE_t XMC_VADC_GLOBAL_GetCompareResult(XMC_VADC_GLOBAL_t *const global_ptr) +{ + XMC_VADC_FAST_COMPARE_t result; + uint32_t res; + + XMC_ASSERT("XMC_VADC_GLOBAL_GetCompareResult:Wrong Module Pointer", (global_ptr == VADC)) + + res = global_ptr->GLOBRES; + + if (res & (uint32_t)VADC_GLOBRES_VF_Msk) + { + result = (XMC_VADC_FAST_COMPARE_t)((uint32_t)(res >> (uint32_t)VADC_GLOBRES_FCR_Pos) & (uint32_t)1); + } + else + { + result = XMC_VADC_FAST_COMPARE_UNKNOWN; + } + + return result; +} + +/* Bind one of the four groups to one of the two EMUX interfaces */ +#if (XMC_VADC_EMUX_AVAILABLE == 1U) +void XMC_VADC_GLOBAL_BindGroupToEMux(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t emuxif, const uint32_t group) +{ + uint32_t mask; + uint32_t pos; + + XMC_ASSERT("XMC_VADC_GLOBAL_BindGroupToEMux:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BindGroupToEMux:Wrong EMUX Group", (emuxif < XMC_VADC_NUM_EMUX_INTERFACES)) + XMC_ASSERT("XMC_VADC_GLOBAL_BindGroupToEMux:Wrong VADC Group", (group < XMC_VADC_MAXIMUM_NUM_GROUPS)) + + if (0U == emuxif) + { + pos = (uint32_t)VADC_EMUXSEL_EMUXGRP0_Pos; + mask = (uint32_t)VADC_EMUXSEL_EMUXGRP0_Msk; + } + else + { + pos = (uint32_t)VADC_EMUXSEL_EMUXGRP1_Pos; + mask = (uint32_t)VADC_EMUXSEL_EMUXGRP1_Msk; + } + + global_ptr->EMUXSEL &= ~(mask); + global_ptr->EMUXSEL |= (uint32_t) (group << pos); + +} +#endif + +/* API to bind result event with a service request line */ +void XMC_VADC_GLOBAL_SetResultEventInterruptNode(XMC_VADC_GLOBAL_t *const global_ptr, XMC_VADC_SR_t sr) +{ + uint32_t node; + + XMC_ASSERT("XMC_VADC_GLOBAL_SetResultEventInterruptNode:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_SetResultEventInterruptNode:Wrong SR Number", (sr <= XMC_VADC_SR_SHARED_SR3)) + + if (sr >= XMC_VADC_SR_SHARED_SR0) + { + node = (uint32_t)sr - (uint32_t)XMC_VADC_SR_SHARED_SR0; + } + else + { + node = (uint32_t)sr; + } + + global_ptr->GLOBEVNP &= ~((uint32_t)VADC_GLOBEVNP_REV0NP_Msk); + global_ptr->GLOBEVNP |= (uint32_t)(node << VADC_GLOBEVNP_REV0NP_Pos); +} + +/* API to bind request source event with a service request line */ +void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *const global_ptr, XMC_VADC_SR_t sr) +{ + uint32_t node; + + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode:Wrong Module Pointer", (global_ptr == VADC)) + + if (sr >= XMC_VADC_SR_SHARED_SR0) + { + node = (uint32_t)sr - (uint32_t)XMC_VADC_SR_SHARED_SR0; + } + else + { + node = (uint32_t)sr; + } + + global_ptr->GLOBEVNP &= ~((uint32_t)VADC_GLOBEVNP_SEV0NP_Msk); + global_ptr->GLOBEVNP |= (uint32_t) (node << VADC_GLOBEVNP_SEV0NP_Pos); +} + +/* API to initialize an instance of group of VADC hardware */ +#if (XMC_VADC_GROUP_AVAILABLE == 1U) +void XMC_VADC_GROUP_Init( XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_CONFIG_t *config) +{ + XMC_ASSERT("XMC_VADC_GROUP_Init:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Program the input classes */ + XMC_VADC_GROUP_InputClassInit(group_ptr, config->class0, XMC_VADC_GROUP_CONV_STD, 0U); + XMC_VADC_GROUP_InputClassInit(group_ptr, config->class0, XMC_VADC_GROUP_CONV_EMUX, 0U); + XMC_VADC_GROUP_InputClassInit(group_ptr, config->class1, XMC_VADC_GROUP_CONV_STD, 1U); + XMC_VADC_GROUP_InputClassInit(group_ptr, config->class1, XMC_VADC_GROUP_CONV_EMUX, 1U); + + group_ptr->ARBCFG = config->g_arbcfg; + + group_ptr->BOUND = config->g_bound; + + /* External mux configuration */ + XMC_VADC_GROUP_ExternalMuxControlInit(group_ptr,config->emux_config); + +} + +/* API to program conversion characteristics */ +void XMC_VADC_GROUP_InputClassInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_CLASS_t config, + const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num) +{ + uint32_t conv_class; + uint32_t conv_mode_pos; + uint32_t sample_time_pos; + uint32_t conv_mode_mask; + uint32_t sample_time_mask; + uint32_t sample_time; + XMC_VADC_CONVMODE_t conv_mode; + + XMC_ASSERT("XMC_VADC_GROUP_InputClassInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_InputClassInit:Wrong Conversion Type", ((conv_type) <= XMC_VADC_GROUP_CONV_EMUX)) + XMC_ASSERT("XMC_VADC_GROUP_InputClassInit:Wrong ICLASS set number", (set_num < XMC_VADC_MAX_ICLASS_SET)) + + /* + * Obtain the mask and position macros of the parameters based on what is being requested - Standard channels vs + * external mux channels. + */ + if (XMC_VADC_GROUP_CONV_STD == conv_type) + { + conv_mode_pos = (uint32_t) VADC_G_ICLASS_CMS_Pos; + conv_mode_mask = (uint32_t) VADC_G_ICLASS_CMS_Msk; + sample_time_pos = (uint32_t) VADC_G_ICLASS_STCS_Pos; + sample_time_mask = (uint32_t) VADC_G_ICLASS_STCS_Msk; + sample_time = (uint32_t) config.sample_time_std_conv; + conv_mode = (XMC_VADC_CONVMODE_t)config.conversion_mode_standard; + } + else + { + conv_mode_pos = (uint32_t) VADC_G_ICLASS_CME_Pos; + conv_mode_mask = (uint32_t) VADC_G_ICLASS_CME_Msk; + sample_time_pos = (uint32_t) VADC_G_ICLASS_STCE_Pos; + sample_time_mask = (uint32_t) VADC_G_ICLASS_STCE_Msk; + sample_time = (uint32_t) config.sampling_phase_emux_channel; + conv_mode = (XMC_VADC_CONVMODE_t)config.conversion_mode_emux; + } + + /* Determine the class */ + conv_class = group_ptr->ICLASS[set_num]; + + /* Program the class register */ + conv_class &= ~(conv_mode_mask); + conv_class |= (uint32_t)((uint32_t) conv_mode << conv_mode_pos); + conv_class &= ~(sample_time_mask); + conv_class |= (uint32_t)(sample_time << sample_time_pos); + group_ptr->ICLASS[set_num] = conv_class; +} + +/* API which sets the power mode of analog converter of a VADC group */ +void XMC_VADC_GROUP_SetPowerMode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_POWERMODE_t power_mode) +{ + uint32_t arbcfg; + + XMC_ASSERT("XMC_VADC_GROUP_SetPowerMode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetPowerMode:Wrong Power Mode", (power_mode <= XMC_VADC_GROUP_POWERMODE_NORMAL)) + + arbcfg = group_ptr->ARBCFG; + + arbcfg &= ~((uint32_t)VADC_G_ARBCFG_ANONC_Msk); + arbcfg |= (uint32_t)power_mode; + + group_ptr->ARBCFG = arbcfg; +} + +/* API which programs a group as a slave group during sync conversions */ +void XMC_VADC_GROUP_SetSyncSlave(XMC_VADC_GROUP_t *const group_ptr, uint32_t master_grp, uint32_t slave_grp) +{ + uint32_t synctr; + #if (XMC_VADC_MULTIPLE_SLAVEGROUPS == 1U ) + #endif + XMC_ASSERT("XMC_VADC_GROUP_SetSyncSlave:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + #if (XMC_VADC_MULTIPLE_SLAVEGROUPS == 1U ) + + /* Determine the coding of SYNCTR */ + if (slave_grp > master_grp) + { + master_grp = master_grp + 1U; + } + #endif + + /* Program SYNCTR */ + synctr = group_ptr->SYNCTR; + synctr &= ~((uint32_t)VADC_G_SYNCTR_STSEL_Msk); + synctr |= master_grp; + group_ptr->SYNCTR = synctr; +} + +/* API which programs a group as a master group during sync conversions */ +void XMC_VADC_GROUP_SetSyncMaster(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t synctr; + + XMC_ASSERT("XMC_VADC_GROUP_SetSyncMaster:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + synctr = group_ptr->SYNCTR; + synctr &= ~((uint32_t)VADC_G_SYNCTR_STSEL_Msk); + group_ptr->SYNCTR = synctr; +} + +/* API to enable checking of readiness of slaves before a synchronous conversion request is issued */ +void XMC_VADC_GROUP_CheckSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group) +{ + uint32_t i,master_grp_num; + XMC_ASSERT("XMC_VADC_GROUP_CheckSlaveReadiness:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_CheckSlaveReadiness:Wrong Slave group", ((slave_group >= 0) && (slave_group <= (XMC_VADC_MAXIMUM_NUM_GROUPS - 1)))) + + master_grp_num =0; + for(i=0; iSYNCTR |= (1U << (slave_group + XMC_VADC_SYNCTR_START_LOCATION)); +} + +/* API to disable checking of readiness of slaves during synchronous conversions */ +void XMC_VADC_GROUP_IgnoreSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group) +{ + uint32_t i,master_grp_num; + XMC_ASSERT("XMC_VADC_GROUP_IgnoreSlaveReadiness:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_IgnoreSlaveReadiness:Wrong Slave group", ((slave_group >= 0) && (slave_group <= (XMC_VADC_MAXIMUM_NUM_GROUPS - 1)))) + + master_grp_num =0; + for(i=0; iSYNCTR &= ~(1U << (slave_group + XMC_VADC_SYNCTR_START_LOCATION)); +} + +/* API to configure EVAL bit in the slave groups*/ +void XMC_VADC_GROUP_SetSyncSlaveReadySignal(XMC_VADC_GROUP_t *const group_ptr, + uint32_t eval_waiting_group, + uint32_t eval_origin_group) +{ + XMC_ASSERT("XMC_VADC_GROUP_SetSyncSlaveReadySignal:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetSyncSlaveReadySignal:Wrong Group numbers", (eval_waiting_group == eval_origin_group )) + + if(eval_origin_group < eval_waiting_group) + { + eval_origin_group++; + } + group_ptr->SYNCTR |= (1U << (eval_origin_group + XMC_VADC_SYNCTR_START_LOCATION)); +} + + +/* API to enable the synchronous conversion feature - Applicable only to kernel configured as master */ +void XMC_VADC_GROUP_EnableChannelSyncRequest(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + uint32_t synctr; + + XMC_ASSERT("XMC_VADC_GROUP_EnableChannelSyncRequest:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_EnableChannelSyncRequest:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + synctr = group_ptr->SYNCTR; + + if (!(synctr & (uint32_t)VADC_G_SYNCTR_STSEL_Msk)) + { + group_ptr->CHCTR[ch_num] |= (uint32_t)((uint32_t)1 << VADC_G_CHCTR_SYNC_Pos); + } +} + +/* API to disable synchronous conversion feature */ +void XMC_VADC_GROUP_DisableChannelSyncRequest(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + uint32_t synctr; + + XMC_ASSERT("XMC_VADC_GROUP_DisableChannelSyncRequest:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_DisableChannelSyncRequest:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + synctr = group_ptr->SYNCTR; + + if (synctr & (uint32_t)VADC_G_SYNCTR_STSEL_Msk) + { + group_ptr->CHCTR[ch_num] &= ~((uint32_t)VADC_G_CHCTR_SYNC_Msk); + } +} + +/* API to retrieve the converter state - Idle vs Busy */ +XMC_VADC_GROUP_STATE_t XMC_VADC_GROUP_IsConverterBusy(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t arbcfg; + + XMC_ASSERT("XMC_VADC_GROUP_IsConverterBusy:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + arbcfg = group_ptr->ARBCFG; + arbcfg &= (uint32_t)VADC_G_ARBCFG_BUSY_Msk; + arbcfg = arbcfg >> VADC_G_ARBCFG_BUSY_Pos; + + return( (XMC_VADC_GROUP_STATE_t)arbcfg); +} + +/* API to set boundaries for conversion results */ +void XMC_VADC_GROUP_SetBoundaries(XMC_VADC_GROUP_t *const group_ptr, const uint32_t boundary0, const uint32_t boundary1) +{ + uint32_t bound; + + XMC_ASSERT("XMC_VADC_GROUP_SetBoundaries:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Program the Boundary registers */ + bound = group_ptr->BOUND; + bound &= ~((uint32_t) VADC_G_BOUND_BOUNDARY0_Msk); + bound &= ~((uint32_t) VADC_G_BOUND_BOUNDARY1_Msk); + bound |= (uint32_t) ((uint32_t) boundary0 << VADC_G_BOUND_BOUNDARY0_Pos); + bound |= (uint32_t) ((uint32_t) boundary1 << VADC_G_BOUND_BOUNDARY1_Pos); + group_ptr->BOUND = bound; +} + +/* API to set an individual boundary for conversion results */ +void XMC_VADC_GROUP_SetIndividualBoundary(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value) +{ + + uint32_t bound; + + XMC_ASSERT("XMC_VADC_GROUP_SetIndividualBoundary:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetIndividualBoundary:Wrong Boundary Selection", + ((XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0 == selection) || + (XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND1 == selection))) + + /* Program the Boundary registers */ + bound = group_ptr->BOUND; + if (XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0 == selection) + { + bound &= ~((uint32_t) VADC_G_BOUND_BOUNDARY0_Msk); + bound |= (uint32_t) ((uint32_t) boundary_value << VADC_G_BOUND_BOUNDARY0_Pos); + } + else if (XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND1 == selection) + { + bound &= ~((uint32_t) VADC_G_BOUND_BOUNDARY1_Msk); + bound |= (uint32_t) ((uint32_t) boundary_value << VADC_G_BOUND_BOUNDARY1_Pos); + } + else + { + /* For MISRA*/ + } + group_ptr->BOUND = bound; + +} + +/* Manually assert service request (Interrupt) to NVIC */ +void XMC_VADC_GROUP_TriggerServiceRequest(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t sr_num, + const XMC_VADC_GROUP_IRQ_t type) +{ + uint32_t sract; + + XMC_ASSERT("XMC_VADC_GROUP_TriggerServiceRequest:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_TriggerServiceRequest:Wrong SR number", (sr_num <= XMC_VADC_SR_SHARED_SR3)) + XMC_ASSERT("XMC_VADC_GROUP_TriggerServiceRequest:Wrong SR type", ((type)<= XMC_VADC_GROUP_IRQ_SHARED)) + + sract = group_ptr->SRACT; + + if (XMC_VADC_GROUP_IRQ_KERNEL == type) + { + sract |= (uint32_t)((uint32_t)1 << sr_num); + } + else + { + sract |= (uint32_t)((uint32_t)1 << (sr_num + (uint32_t)8)); + } + + group_ptr->SRACT = sract; +} + +#if XMC_VADC_BOUNDARY_FLAG_SELECT == 1U + +/* API to set the SR line for the Boundary flag node pointer*/ +void XMC_VADC_GROUP_SetBoundaryEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint8_t boundary_flag_num, + const XMC_VADC_BOUNDARY_NODE_t sr) +{ + uint32_t flag_pos; + XMC_ASSERT("XMC_VADC_GROUP_SetBoundaryEventInterruptNode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Program the GxBFLNP */ + flag_pos = (uint32_t)boundary_flag_num << (uint32_t)2; + group_ptr->BFLNP &= ~((uint32_t)VADC_G_BFLNP_BFL0NP_Msk << flag_pos); + group_ptr->BFLNP |= (uint32_t)sr << flag_pos; +} + +#endif + +#endif + +#if(XMC_VADC_SHS_AVAILABLE == 1U) + +/* API to Initialize the Sample and hold features*/ +void XMC_VADC_GLOBAL_SHS_Init(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, const XMC_VADC_GLOBAL_SHS_CONFIG_t *config) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_Init:Wrong SHS Pointer", (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_Init:Wrong Index number",(config == (XMC_VADC_GLOBAL_SHS_CONFIG_t*)NULL)) + + /* Initialize the SHS Configuration register*/ + shs_ptr->SHSCFG = (uint32_t)((uint32_t)config->shscfg | (uint32_t)SHS_SHSCFG_SCWC_Msk); + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) + /* Select the Calibration order*/ + shs_ptr->CALCTR &= ~((uint32_t)SHS_CALCTR_CALORD_Msk); + shs_ptr->CALCTR |= (uint32_t) ((uint32_t)config->calibration_order << SHS_CALCTR_CALORD_Pos); +#endif +} + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/* API to enable the accelerated mode of conversion */ +void XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, XMC_VADC_GROUP_INDEX_t group_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) + + /* Set the converted to Accelerated mode from compatible mode*/ + if (group_num == XMC_VADC_GROUP_INDEX_0 ) + { + shs_ptr->TIMCFG0 |= (uint32_t)SHS_TIMCFG0_AT_Msk; + } + else if (group_num == XMC_VADC_GROUP_INDEX_1 ) + { + shs_ptr->TIMCFG1 |= (uint32_t)SHS_TIMCFG1_AT_Msk; + } + else + { + /* for MISRA*/ + } +} + +/* API to disable the accelerated mode of conversion */ +void XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, XMC_VADC_GROUP_INDEX_t group_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) + + /* Set the converted to Accelerated mode from compatible mode*/ + if (group_num == XMC_VADC_GROUP_INDEX_0 ) + { + shs_ptr->TIMCFG0 &= ~(uint32_t)SHS_TIMCFG0_AT_Msk; + } + else if (group_num == XMC_VADC_GROUP_INDEX_1 ) + { + shs_ptr->TIMCFG1 &= ~(uint32_t)SHS_TIMCFG1_AT_Msk; + } + else + { + /* for MISRA*/ + } +} + +/* API to set the Short sample time of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_SetShortSampleTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + uint8_t sst_value) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetShortSampleTime:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetShortSampleTime:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetShortSampleTime:Wrong SST value",(sst_value < 64U)) + + /* Set the short sample time for the Accelerated mode of operation*/ + if (group_num == XMC_VADC_GROUP_INDEX_0 ) + { + shs_ptr->TIMCFG0 &= ~((uint32_t)SHS_TIMCFG0_SST_Msk); + shs_ptr->TIMCFG0 |= (uint32_t)((uint32_t)sst_value << SHS_TIMCFG0_SST_Pos ); + } + else if (group_num == XMC_VADC_GROUP_INDEX_1 ) + { + shs_ptr->TIMCFG1 &= ~((uint32_t)SHS_TIMCFG1_SST_Msk); + shs_ptr->TIMCFG1 |= (uint32_t)((uint32_t)sst_value << SHS_TIMCFG1_SST_Pos ); + } + else + { + /* for MISRA*/ + } +} +#endif + +/* API to set the gain factor of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_SetGainFactor(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + uint8_t gain_value, + XMC_VADC_GROUP_INDEX_t group_num, + uint8_t ch_num) +{ + uint32_t ch_mask; + + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetGainFactor:Wrong SHS Pointer", (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetGainFactor:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) + + /*Calculate location of channel bit-field*/ + ch_mask = ((uint32_t)ch_num << (uint32_t)2); + if (group_num == XMC_VADC_GROUP_INDEX_0 ) + { + shs_ptr->GNCTR00 &= ~((uint32_t)SHS_GNCTR00_GAIN0_Msk << ch_mask) ; + shs_ptr->GNCTR00 |= ((uint32_t)gain_value << ch_mask); + } + else if (group_num == XMC_VADC_GROUP_INDEX_1 ) + { + shs_ptr->GNCTR10 &= ~((uint32_t)SHS_GNCTR10_GAIN0_Msk << ch_mask); + shs_ptr->GNCTR10 |= ((uint32_t)gain_value << ch_mask); + } + else + { + /* for MISRA*/ + } +} + +#if(XMC_VADC_SHS_FULL_SET_REG == 1U) +/* API to enable the gain and offset calibration of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations:Wrong group selected", + (group_num <= (uint32_t)XMC_VADC_GROUP_INDEX_1)) + + /* Enable gain and offset calibration*/ + if ( XMC_VADC_GROUP_INDEX_0 == group_num) + { + shs_ptr->CALOC0 &= ~((uint32_t)SHS_CALOC0_DISCAL_Msk); + } + else if ( XMC_VADC_GROUP_INDEX_1 == group_num) + { + shs_ptr->CALOC1 &= ~((uint32_t)SHS_CALOC1_DISCAL_Msk); + } + else + { + /* for MISRA */ + } +} + +/* API to enable the gain and offset calibration of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations:Wrong group selected", + (group_num <= (uint32_t)XMC_VADC_GROUP_INDEX_1)) + + if ( XMC_VADC_GROUP_INDEX_0 == group_num) + { + shs_ptr->CALOC0 |= (uint32_t)SHS_CALOC0_DISCAL_Msk; + } + else if ( XMC_VADC_GROUP_INDEX_1 == group_num) + { + shs_ptr->CALOC1 |= (uint32_t)SHS_CALOC1_DISCAL_Msk; + } + else + { + /* for MISRA */ + } +} + +/* API to get the offset calibration value of the Sample and hold module*/ +uint8_t XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level) +{ + uint32_t calibration_value; + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue:Wrong Group number selected", + (group_num == XMC_VADC_GROUP_INDEX_0)||(group_num == XMC_VADC_GROUP_INDEX_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue:Wrong gain level selected", + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_0)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_1)|| + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_2)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_3)) + + calibration_value = 0U; + if ( XMC_VADC_GROUP_INDEX_0 == group_num) + { + calibration_value = (shs_ptr->CALOC0 >> (uint32_t)gain_level) & (uint32_t)SHS_CALOC0_CALOFFVAL0_Msk; + } + else if ( XMC_VADC_GROUP_INDEX_1 == group_num) + { + calibration_value = (shs_ptr->CALOC1 >> (uint32_t)gain_level) & (uint32_t)SHS_CALOC1_CALOFFVAL0_Msk; + } + else + { + /* for MISRA */ + } + return ((uint8_t)calibration_value); +} + +/* API to set the offset calibration value of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level, + uint8_t offset_calibration_value) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue:Wrong Group number selected", + (group_num == XMC_VADC_GROUP_INDEX_0)||(group_num == XMC_VADC_GROUP_INDEX_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue:Wrong gain level selected", + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_0)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_1)|| + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_2)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_3)) + + if ( XMC_VADC_GROUP_INDEX_0 == group_num) + { + shs_ptr->CALOC0 = (shs_ptr->CALOC0 & ~((uint32_t)SHS_CALOC0_CALOFFVAL0_Msk << (uint32_t)gain_level)) | + (uint32_t)SHS_CALOC0_OFFWC_Msk; + shs_ptr->CALOC0 |= ((uint32_t)offset_calibration_value << (uint32_t)gain_level) | (uint32_t)SHS_CALOC0_OFFWC_Msk; + } + else if ( XMC_VADC_GROUP_INDEX_1 == group_num) + { + shs_ptr->CALOC1 = (shs_ptr->CALOC1 & ~((uint32_t)SHS_CALOC1_CALOFFVAL0_Msk << (uint32_t)gain_level)) | + (uint32_t)SHS_CALOC1_OFFWC_Msk; + shs_ptr->CALOC1 |= ((uint32_t)offset_calibration_value << (uint32_t)gain_level) | (uint32_t)SHS_CALOC1_OFFWC_Msk; + } + else + { + /* for MISRA */ + } +} +#endif + +/* API to set the values of sigma delta loop of the Sample and hold module*/ +void XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_LOOP_CH_t loop_select, + uint8_t ch_num) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong SHS Pointer", + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong Group number selected", + (group_num == XMC_VADC_GROUP_INDEX_0)||(group_num == XMC_VADC_GROUP_INDEX_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong Delta sigma loop selected", + (loop_select == XMC_VADC_SHS_LOOP_CH_0)||(loop_select == XMC_VADC_SHS_LOOP_CH_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + shs_ptr->LOOP &= ~(((uint32_t)SHS_LOOP_LPCH0_Msk | (uint32_t)SHS_LOOP_LPSH0_Msk | (uint32_t)SHS_LOOP_LPEN0_Msk) + << (uint32_t)loop_select); + shs_ptr->LOOP |= ((uint32_t)ch_num | ((uint32_t)group_num << (uint32_t)SHS_LOOP_LPSH0_Pos)) << (uint32_t)loop_select; + +} + +#endif + +#if (XMC_VADC_GSCAN_AVAILABLE == 1U) +/* API to initialize the group scan hardware of a kernel */ +void XMC_VADC_GROUP_ScanInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SCAN_CONFIG_t *config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_VADC_GROUP_ScanInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* All configurations have to be performed with the arbitration slot disabled */ + XMC_VADC_GROUP_ScanDisableArbitrationSlot(group_ptr); + + /* Read in the existing contents of arbitration priority register */ + reg = group_ptr->ARBPR; + + /* Program the priority of the request source */ + reg &= ~(uint32_t)VADC_G_ARBPR_PRIO1_Msk; + reg |= (uint32_t)((uint32_t)config->req_src_priority << VADC_G_ARBPR_PRIO1_Pos); + + /* Program the start mode */ + if (XMC_VADC_STARTMODE_WFS != (XMC_VADC_STARTMODE_t)(config->conv_start_mode)) + { + reg |= (uint32_t)(VADC_G_ARBPR_CSM1_Msk); + } + + group_ptr->ARBPR = reg; + + group_ptr->ASCTRL = (uint32_t)(config->asctrl |(VADC_G_ASCTRL_XTWC_Msk) |(VADC_G_ASCTRL_GTWC_Msk) | + (VADC_G_ASCTRL_TMWC_Msk)); + + group_ptr->ASMR = (uint32_t)((config->asmr)| (uint32_t)((uint32_t)XMC_VADC_GATEMODE_IGNORE << VADC_G_ASMR_ENGT_Pos)); + + if (XMC_VADC_STARTMODE_CNR == (XMC_VADC_STARTMODE_t)(config->conv_start_mode)) + { + group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_RPTDIS_Msk; + } + + /* Enable arbitration slot now */ + XMC_VADC_GROUP_ScanEnableArbitrationSlot(group_ptr); + +} + +/* API to select one of the 16 inputs as a trigger input for Group Scan request source */ +void XMC_VADC_GROUP_ScanSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_TRIGGER_INPUT_SELECT_t trigger_input) +{ + uint32_t scanctrl; + + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTrigger:Wrong Trigger Port", ((trigger_input)< XMC_VADC_NUM_PORTS)) + + scanctrl = group_ptr->ASCTRL; + scanctrl |= (uint32_t) VADC_G_ASCTRL_XTWC_Msk; + scanctrl &= ~((uint32_t)VADC_G_ASCTRL_XTSEL_Msk); + scanctrl |= (uint32_t)((uint32_t)trigger_input << VADC_G_ASCTRL_XTSEL_Pos); + group_ptr->ASCTRL = scanctrl; +} + +/* Select a trigger edge*/ +void XMC_VADC_GROUP_ScanSelectTriggerEdge(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_TRIGGER_EDGE_t trigger_edge) +{ + uint32_t scanctrl; + + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTriggerEdge:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTriggerEdge:Wrong Trigger Port", ((trigger_edge)<= XMC_VADC_TRIGGER_EDGE_ANY)) + + scanctrl = group_ptr->ASCTRL; + scanctrl |= (uint32_t) VADC_G_ASCTRL_XTWC_Msk; + scanctrl &= ~((uint32_t)VADC_G_ASCTRL_XTMODE_Msk); + scanctrl |= (uint32_t)((uint32_t)trigger_edge << VADC_G_ASCTRL_XTMODE_Pos); + group_ptr->ASCTRL = scanctrl; +} + +/* API to select one of the 16 inputs as a trigger gating input for Group Scan request source */ +void XMC_VADC_GROUP_ScanSelectGating(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC_GATE_INPUT_SELECT_t gating_input) +{ + uint32_t scanctrl; + + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectGating:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectGating:Wrong Gating Port", ((gating_input)< XMC_VADC_NUM_PORTS)) + + scanctrl = group_ptr->ASCTRL; + scanctrl |= (uint32_t)VADC_G_ASCTRL_GTWC_Msk; + scanctrl &= ~((uint32_t)VADC_G_ASCTRL_GTSEL_Msk); + scanctrl |= (uint32_t)((uint32_t)gating_input << VADC_G_ASCTRL_GTSEL_Pos); + group_ptr->ASCTRL = scanctrl; +} + +/* API to stop an ongoing conversion of a sequence */ +void XMC_VADC_GROUP_ScanSequenceAbort(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t asctrl; + bool arbitration_status; + + XMC_ASSERT("XMC_VADC_GROUP_ScanSequenceAbort:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* To disable trigger and gating before abort*/ + asctrl = group_ptr->ASCTRL; + + group_ptr->ASCTRL =(0U | (uint32_t)VADC_G_ASCTRL_XTWC_Msk | + (uint32_t)VADC_G_ASCTRL_GTWC_Msk | (uint32_t)VADC_G_ASCTRL_TMWC_Msk ); + + /* To disable Arbitration before abort*/ + arbitration_status = (bool)((uint32_t)(group_ptr->ARBPR >> VADC_G_ARBPR_ASEN1_Pos) & 1U); + XMC_VADC_GROUP_ScanDisableArbitrationSlot(group_ptr); + + group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_ENGT_Msk); + group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_CLRPND_Msk; + + /* Enable the arbitration slot 1*/ + group_ptr->ARBPR |= (uint32_t)((uint32_t)arbitration_status << VADC_G_ARBPR_ASEN1_Pos); + + /* Enable any disabled gating*/ + group_ptr->ASCTRL =(asctrl | (uint32_t)VADC_G_ASCTRL_XTWC_Msk | + (uint32_t)VADC_G_ASCTRL_GTWC_Msk | (uint32_t)VADC_G_ASCTRL_TMWC_Msk ); +} + +/* API to find out number of channels awaiting conversion */ +uint32_t XMC_VADC_GROUP_ScanGetNumChannelsPending(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t reg; + uint32_t i; + uint32_t count; + + XMC_ASSERT("XMC_VADC_GROUP_ScanGetNumChannelsPending:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + + count = 0U; + + if (group_ptr->ASPND) + { + reg = group_ptr->ASPND; + + for(i=0U;i> (uint32_t)1); + } + } + + return count; +} + +/* API to select a service request line (NVIC Node) for request source event */ +void XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SR_t sr) +{ + uint32_t sevnp; + sevnp = group_ptr->SEVNP; + + XMC_ASSERT("XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode:Wrong Service Request", ((sr) <= XMC_VADC_SR_SHARED_SR3)) + + sevnp &= ~((uint32_t)VADC_G_SEVNP_SEV1NP_Msk); + sevnp |= (uint32_t)((uint32_t)sr << VADC_G_SEVNP_SEV1NP_Pos); + + group_ptr->SEVNP = sevnp; +} + +/* Removes the selected channel from conversion*/ +void XMC_VADC_GROUP_ScanRemoveChannel(XMC_VADC_GROUP_t *const group_ptr, const uint32_t channel_num) +{ + uint32_t assel; + + XMC_ASSERT("XMC_VADC_GROUP_ScanRemoveChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ScanRemoveChannel:Wrong channel number", ((channel_num)< XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + assel = group_ptr->ASSEL; + assel &= (~( 1 << channel_num)); + group_ptr->ASSEL = assel; +} +#endif + +/* API to initialize background scan request source hardware */ +void XMC_VADC_GLOBAL_BackgroundInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_BACKGROUND_CONFIG_t *config) +{ + #if (XMC_VADC_GROUP_AVAILABLE ==1U) + uint8_t i; + uint32_t reg; + uint32_t conv_start_mask; + #endif + + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundInit:Wrong Module Pointer", (global_ptr == VADC)) + + #if (XMC_VADC_GROUP_AVAILABLE ==1U) + for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + XMC_VADC_GROUP_BackgroundDisableArbitrationSlot((XMC_VADC_GROUP_t *)g_xmc_vadc_group_array[i]); + } + + conv_start_mask = (uint32_t) 0; + if (XMC_VADC_STARTMODE_WFS != (XMC_VADC_STARTMODE_t)config->conv_start_mode) + { + conv_start_mask = (uint32_t)VADC_G_ARBPR_CSM2_Msk; + } + + for(i=0U; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + reg = g_xmc_vadc_group_array[i]->ARBPR; + + reg &= ~(uint32_t)(VADC_G_ARBPR_PRIO2_Msk); + + /* Program the priority of the request source */ + reg |= (uint32_t)((uint32_t)config->req_src_priority << VADC_G_ARBPR_PRIO2_Pos); + + /* Program the start mode */ + reg |= conv_start_mask; + + g_xmc_vadc_group_array[i]->ARBPR = reg; + + } + #endif + + /* program BRSCTRL register */ + global_ptr->BRSCTRL = (uint32_t)(config->asctrl | (uint32_t)VADC_BRSCTRL_XTWC_Msk | (uint32_t)VADC_BRSCTRL_GTWC_Msk); + + /* program BRSMR register */ + global_ptr->BRSMR = (uint32_t)((config->asmr)| (uint32_t)((uint32_t)XMC_VADC_GATEMODE_IGNORE << VADC_BRSMR_ENGT_Pos)); + +#if (XMC_VADC_GROUP_AVAILABLE ==1U) + if (XMC_VADC_STARTMODE_CNR == (XMC_VADC_STARTMODE_t)(config->conv_start_mode)) + { + global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_RPTDIS_Msk; + } +#endif + + #if (XMC_VADC_GROUP_AVAILABLE ==1U) + for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + XMC_VADC_GROUP_BackgroundEnableArbitrationSlot((XMC_VADC_GROUP_t *)g_xmc_vadc_group_array[i]); + } + #endif + +} + +/* API to select one of the 16 inputs as a trigger for background scan request source */ +void XMC_VADC_GLOBAL_BackgroundSelectTrigger(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t input_num) +{ + uint32_t scanctrl; + + XMC_ASSERT("VADC_BCKGND_SelectTriggerInput:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectTrigger:Wrong Trigger Port", ((input_num)< XMC_VADC_NUM_PORTS)) + + + scanctrl = global_ptr->BRSCTRL; + scanctrl |= (uint32_t)VADC_BRSCTRL_XTWC_Msk; + scanctrl &= ~((uint32_t)VADC_BRSCTRL_XTSEL_Msk); + scanctrl |= (uint32_t)(input_num << VADC_BRSCTRL_XTSEL_Pos); + global_ptr->BRSCTRL = scanctrl; +} + +/* Select a trigger edge*/ +void XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge(XMC_VADC_GLOBAL_t *const global_ptr, + const XMC_VADC_TRIGGER_EDGE_t trigger_edge) +{ + uint32_t scanctrl; + + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge:Wrong Global Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge:Wrong Trigger Port", + ((trigger_edge)<= XMC_VADC_TRIGGER_EDGE_ANY)) + + scanctrl = global_ptr->BRSCTRL; + scanctrl |= (uint32_t) VADC_BRSCTRL_XTWC_Msk; + scanctrl &= ~((uint32_t)VADC_BRSCTRL_XTMODE_Msk); + scanctrl |= (uint32_t)((uint32_t)trigger_edge << VADC_BRSCTRL_XTMODE_Pos); + global_ptr->BRSCTRL = scanctrl; +} + + +/* API to select one of the 16 inputs as a trigger gate for background scan request source */ +void XMC_VADC_GLOBAL_BackgroundSelectGating(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t input_num) +{ + uint32_t scanctrl; + + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectGating:Wrong Module Pointer", (global_ptr == VADC)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectGating:Wrong Gating Port", ((input_num)< XMC_VADC_NUM_PORTS)) + + scanctrl = global_ptr->BRSCTRL; + scanctrl |= (uint32_t)VADC_BRSCTRL_GTWC_Msk; + scanctrl &= ~((uint32_t)VADC_BRSCTRL_GTSEL_Msk); + scanctrl |= (uint32_t)(input_num << VADC_BRSCTRL_GTSEL_Pos); + global_ptr->BRSCTRL = scanctrl; +} + +/* API to abort ongoing conversion of a sequence */ +void XMC_VADC_GLOBAL_BackgroundAbortSequence(XMC_VADC_GLOBAL_t *const global_ptr) +{ + uint32_t brsctrl; +#if (XMC_VADC_GROUP_AVAILABLE ==1U) + uint32_t i; + uint8_t grp_asen2_flag[XMC_VADC_MAXIMUM_NUM_GROUPS]; +#endif + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAbortSequence:Wrong Module Pointer", (global_ptr == VADC)) + + /* To disable trigger and gating before abort*/ + brsctrl = global_ptr->BRSCTRL; + + global_ptr->BRSCTRL =(0U | (uint32_t)VADC_BRSCTRL_XTWC_Msk | (uint32_t)VADC_BRSCTRL_GTWC_Msk); + + /* Disable Background Request source */ + +#if (XMC_VADC_GROUP_AVAILABLE ==1U) + for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + grp_asen2_flag[i] = (uint8_t)(g_xmc_vadc_group_array[i]->ARBPR >> VADC_G_ARBPR_ASEN2_Pos); + XMC_VADC_GROUP_BackgroundDisableArbitrationSlot((XMC_VADC_GROUP_t *)g_xmc_vadc_group_array[i]); + } +#endif + + /* Abort the ongoing sequence */ + global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_CLRPND_Msk; + +#if (XMC_VADC_GROUP_AVAILABLE ==1U) + /* Enable Background Request source */ + for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + if ((uint8_t)1 == grp_asen2_flag[i]) + { + XMC_VADC_GROUP_BackgroundEnableArbitrationSlot((XMC_VADC_GROUP_t*)g_xmc_vadc_group_array[i]); + } + } +#endif + + /* Re-enable any disabled trigger and gating*/ + global_ptr->BRSCTRL =(brsctrl | (uint32_t)VADC_BRSCTRL_XTWC_Msk | (uint32_t)VADC_BRSCTRL_GTWC_Msk); +} + +/* API to determine how many channels are awaiting conversion */ +uint32_t XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending(XMC_VADC_GLOBAL_t *const global_ptr) +{ + uint32_t reg; + uint32_t i; + uint32_t j; + uint32_t count; + + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending:Wrong Module Pointer", (global_ptr == VADC)) + + count = 0U; + + /* Loop through all groups and find out who is awaiting conversion */ + for(i = 0U; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + { + if (global_ptr->BRSSEL[i]) + { + reg = global_ptr->BRSPND[i]; + + for(j=0U;j> 1U; + } + } + } + + return count; +} + +#if (XMC_VADC_QUEUE_AVAILABLE == 1U) +/* API to initialize queue request source */ +void XMC_VADC_GROUP_QueueInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_QUEUE_CONFIG_t *config) +{ + uint32_t reg; + + XMC_ASSERT("XMC_VADC_GROUP_QueueInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Disable arbitration slot of the queue request source */ + XMC_VADC_GROUP_QueueDisableArbitrationSlot(group_ptr); + + reg = group_ptr->ARBPR; + + /* Request Source priority */ + reg &= ~((uint32_t)VADC_G_ARBPR_PRIO0_Msk); + reg |= (uint32_t) ((uint32_t)config->req_src_priority << VADC_G_ARBPR_PRIO0_Pos); + + /* Conversion Start mode */ + if (XMC_VADC_STARTMODE_WFS != (XMC_VADC_STARTMODE_t)config->conv_start_mode) + { + reg |= (uint32_t)(VADC_G_ARBPR_CSM0_Msk); + } + + group_ptr->ARBPR = reg; + + + group_ptr->QCTRL0 = (uint32_t)((config->qctrl0)|(uint32_t)(VADC_G_QCTRL0_XTWC_Msk)| + (uint32_t)(VADC_G_QCTRL0_TMWC_Msk)| + (uint32_t)(VADC_G_QCTRL0_GTWC_Msk)); + + /* Gating mode */ + group_ptr->QMR0 = ((uint32_t)(config->qmr0) | (uint32_t)((uint32_t)XMC_VADC_GATEMODE_IGNORE << VADC_G_QMR0_ENGT_Pos)); + + if (XMC_VADC_STARTMODE_CNR == (XMC_VADC_STARTMODE_t)(config->conv_start_mode) ) + { + group_ptr->QMR0 |= (uint32_t)((uint32_t)1 << VADC_G_QMR0_RPTDIS_Pos); + } + /* Enable arbitration slot for the queue request source */ + XMC_VADC_GROUP_QueueEnableArbitrationSlot(group_ptr); + +} + +/* API to select one of the 16 possible triggers as a conversion trigger for queue request source */ +void XMC_VADC_GROUP_QueueSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, + const XMC_VADC_TRIGGER_INPUT_SELECT_t input_num) +{ + uint32_t qctrl; + + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTrigger:Wrong Trigger Port", ((input_num)< XMC_VADC_NUM_PORTS)) + + + /* Now select the conversion trigger */ + qctrl = group_ptr->QCTRL0; + qctrl |= (uint32_t)VADC_G_QCTRL0_XTWC_Msk; + qctrl &= ~((uint32_t)VADC_G_QCTRL0_XTSEL_Msk); + qctrl |= (uint32_t)((uint32_t)input_num << VADC_G_QCTRL0_XTSEL_Pos); + group_ptr->QCTRL0 = qctrl; +} + +/* Select a trigger edge*/ +void XMC_VADC_GROUP_QueueSelectTriggerEdge(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_TRIGGER_EDGE_t trigger_edge) +{ + uint32_t qctrl; + + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTriggerEdge:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTriggerEdge:Wrong Gating Port", ((trigger_edge)<= XMC_VADC_TRIGGER_EDGE_ANY)) + + /* Now select the gating input */ + qctrl = group_ptr->QCTRL0; + qctrl |= (uint32_t)VADC_G_QCTRL0_XTWC_Msk; + qctrl &= ~((uint32_t)VADC_G_QCTRL0_XTMODE_Msk); + qctrl |= (uint32_t)((uint32_t)trigger_edge << VADC_G_QCTRL0_XTMODE_Pos); + group_ptr->QCTRL0 = qctrl; +} + +/* API to select one of the 16 possible trigger gates as a trigger gating signal for queue request source */ +void XMC_VADC_GROUP_QueueSelectGating(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GATE_INPUT_SELECT_t input_num) +{ + uint32_t qctrl; + + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectGating:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectGating:Wrong Gating Port", ((input_num)< XMC_VADC_NUM_PORTS)) + + /* Now select the gating input */ + qctrl = group_ptr->QCTRL0; + qctrl |= (uint32_t)VADC_G_QCTRL0_GTWC_Msk; + qctrl &= ~((uint32_t)VADC_G_QCTRL0_GTSEL_Msk); + qctrl |= (uint32_t)((uint32_t)input_num << VADC_G_QCTRL0_GTSEL_Pos); + group_ptr->QCTRL0 = qctrl; +} + +/* API to determine the number of channels in the queue (length includes the valid channel in the Backup register)*/ +uint32_t XMC_VADC_GROUP_QueueGetLength(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t qsr; + uint32_t qbur0; + uint32_t length; + + XMC_ASSERT("XMC_VADC_GROUP_QueueGetLength:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + qsr = group_ptr->QSR0; + qbur0 = group_ptr->QBUR0; + + if (qsr & (uint32_t)VADC_G_QSR0_EMPTY_Msk) + { + length = 0U; + } + else + { + length = (qsr & (uint32_t)VADC_G_QSR0_FILL_Msk) + 1U; + } + + if (qbur0 & (uint32_t)VADC_G_QBUR0_V_Msk ) + { + length++; + } + + return length; +} + +/* API to abort ongoing conversion of a channel sequence */ +void XMC_VADC_GROUP_QueueAbortSequence(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t qctrl0; + bool arbitration_status; + + XMC_ASSERT("XMC_VADC_GROUP_QueueAbortSequence:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Disable any gating if present*/ + qctrl0 = group_ptr->QCTRL0; + + group_ptr->QCTRL0 =(0U | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); + + /* Disable the Arbitration 0 in the group before abort*/ + arbitration_status = (bool)((uint32_t)(group_ptr->ARBPR >> VADC_G_ARBPR_ASEN0_Pos) & 1U); + XMC_VADC_GROUP_QueueDisableArbitrationSlot(group_ptr); + + /* Flush the Entries from queue*/ + XMC_VADC_GROUP_QueueFlushEntries(group_ptr); + + /* Enable the arbitration slot 0*/ + group_ptr->ARBPR |= (uint32_t)((uint32_t)arbitration_status << VADC_G_ARBPR_ASEN0_Pos); + + /* Enable any disabled gating*/ + group_ptr->QCTRL0 = (qctrl0 | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); +} + +/* API to abort conversion of the channel queued up next */ +void XMC_VADC_GROUP_QueueRemoveChannel(XMC_VADC_GROUP_t *const group_ptr) +{ + uint32_t length_before_abort; + uint32_t length_after_abort; + uint32_t qctrl0; + bool arbitration_status; + + XMC_ASSERT("XMC_VADC_GROUP_QueueRemoveChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* Disable any gating if present*/ + qctrl0= group_ptr->QCTRL0; + + group_ptr->QCTRL0 =(0U | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); + + /* Disable the Arbitration 0 in the group before abort*/ + arbitration_status = (bool)((uint32_t)(group_ptr->ARBPR >> VADC_G_ARBPR_ASEN0_Pos) & 1U); + XMC_VADC_GROUP_QueueDisableArbitrationSlot(group_ptr); + + length_before_abort = XMC_VADC_GROUP_QueueGetLength(group_ptr); + + if (length_before_abort) + { + /* Remove the first entry of the queue */ + group_ptr->QMR0 |= (uint32_t)VADC_G_QMR0_CLRV_Msk; + + length_after_abort = XMC_VADC_GROUP_QueueGetLength(group_ptr); + + /* Loop until a reduction in queue length is assessed */ + while(length_after_abort == length_before_abort) + { + length_after_abort = XMC_VADC_GROUP_QueueGetLength(group_ptr); + } + } + /* Enable the arbitration slot 0*/ + group_ptr->ARBPR |= (uint32_t)((uint32_t)arbitration_status << VADC_G_ARBPR_ASEN0_Pos); + + /* Enable any disabled gating*/ + group_ptr->QCTRL0 = (qctrl0 | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); +} + +/* Get details of channel meant to be converted right after the ongoing conversion */ +int32_t XMC_VADC_GROUP_QueueGetNextChannel(XMC_VADC_GROUP_t *const group_ptr) +{ + int32_t ch_num; + + XMC_ASSERT("XMC_VADC_GROUP_QueueGetNextChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + /* + * Check if there is something in the backup stage. If not, read queue-0 + * entry. + */ + if ( (group_ptr->QBUR0) & (uint32_t)VADC_G_QBUR0_V_Msk) + { + ch_num = (int32_t)(group_ptr->QBUR0 & (uint32_t)VADC_G_QBUR0_REQCHNR_Msk); + } + else if ( (group_ptr->Q0R0) & (uint32_t)VADC_G_Q0R0_V_Msk) + { + ch_num = (int32_t)(group_ptr->Q0R0 & (uint32_t)VADC_G_Q0R0_REQCHNR_Msk); + } + else + { + /* Nothing is pending */ + ch_num = -1; + } + + return ch_num; +} + +/* Get the channel number of the channel whose conversion had been interrupted */ +int32_t XMC_VADC_GROUP_QueueGetInterruptedChannel(XMC_VADC_GROUP_t *const group_ptr) +{ + int32_t ch_num; + + XMC_ASSERT("XMC_VADC_GROUP_QueueGetInterruptedChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + if ((group_ptr->QBUR0) & (uint32_t)VADC_G_QBUR0_V_Msk) + { + ch_num = (int32_t)(group_ptr->QBUR0 & (uint32_t)VADC_G_QBUR0_REQCHNR_Msk); + } + else + { + /* No such channel */ + ch_num = -1; + } + + return ch_num; +} + +/* Select a Service Request line for the request source event */ +void XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SR_t sr) +{ + uint32_t sevnp; + + XMC_ASSERT("XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode:Wrong Service Request", ((sr) <= XMC_VADC_SR_SHARED_SR3)) + + sevnp = group_ptr->SEVNP; + + sevnp &= ~((uint32_t)VADC_G_SEVNP_SEV0NP_Msk); + sevnp |= (uint32_t)((uint32_t)sr << VADC_G_SEVNP_SEV0NP_Pos); + + group_ptr->SEVNP = sevnp; + +} +#endif + +#if (XMC_VADC_GROUP_AVAILABLE ==1U) +/* API to initialize a channel unit */ +void XMC_VADC_GROUP_ChannelInit(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num, + const XMC_VADC_CHANNEL_CONFIG_t *config) +{ + uint32_t prio; + uint32_t ch_assign; + uint32_t mask; + + + XMC_ASSERT("XMC_VADC_GROUP_ChannelInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelInit:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + prio = (uint32_t)config->channel_priority; + + /* Priority channel */ + ch_assign = group_ptr->CHASS; + ch_assign &= ~((uint32_t)((uint32_t)1 << ch_num)); + ch_assign |= (uint32_t)(prio << ch_num); + group_ptr->CHASS = ch_assign; + + /* Alias channel */ + if (config->alias_channel >= (int32_t)0) + { + mask = (uint32_t)0; + if ((uint32_t)1 == ch_num) + { + mask = VADC_G_ALIAS_ALIAS1_Pos; + group_ptr->ALIAS &= ~(uint32_t)(VADC_G_ALIAS_ALIAS1_Msk); + } + else if ((uint32_t)0 == ch_num) + { + mask = VADC_G_ALIAS_ALIAS0_Pos; + group_ptr->ALIAS &= ~(uint32_t)(VADC_G_ALIAS_ALIAS0_Msk); + } + + group_ptr->ALIAS |= (uint32_t)(config->alias_channel << mask); + } + + group_ptr->BFL |= config->bfl; + +#if (XMC_VADC_BOUNDARY_FLAG_SELECT == 1U) + group_ptr->BFLC |= config->bflc; +#endif + /* Program the CHCTR register */ + group_ptr->CHCTR[ch_num] = config->chctr; + +} + +/* API to set an alias channel for channels numbered 2 through 7 */ +void XMC_VADC_GROUP_SetChannelAlias(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t src_ch_num, + const uint32_t alias_ch_num) +{ + uint32_t alias; + uint32_t mask; + uint32_t pos; + + XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Alias Channel", ((alias_ch_num == 0)|| (alias_ch_num == 1U))) + XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Aliased Channel", ((src_ch_num < 8U))) + + alias = group_ptr->ALIAS; + + if (0U == alias_ch_num) + { + mask = (uint32_t) VADC_G_ALIAS_ALIAS0_Msk; + pos = (uint32_t) VADC_G_ALIAS_ALIAS0_Pos; + } + else + { + mask = (uint32_t) VADC_G_ALIAS_ALIAS1_Msk; + pos = (uint32_t) VADC_G_ALIAS_ALIAS1_Pos; + } + alias &= ~mask; + alias |= (uint32_t)(src_ch_num << pos); + + group_ptr->ALIAS = alias; +} + +/* API to determine whether input to a channel has violated boundary conditions */ +bool XMC_VADC_GROUP_ChannelIsResultOutOfBounds(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + bool retval; + uint32_t chctr; + uint32_t ceflag; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelIsResultOutOfBounds:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelIsResultOutOfBounds:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + retval = (bool)false; + /* + Check if the Channel event is configured to be generated in the event of + boundary violation and if affirmative, check if the channel event is set. + */ + /* Extract CHEVMODE for requested channel */ + chctr = group_ptr->CHCTR[ch_num]; + chctr = (uint32_t)(chctr >> (uint32_t)VADC_G_CHCTR_CHEVMODE_Pos)& (uint32_t)0x3; + + /* Extract CEFLAG for the requested channel */ + ceflag = group_ptr->CEFLAG; + ceflag = ceflag & ((uint32_t)((uint32_t)1 << ch_num) ); + + /* Check what was the channel event generation criteria */ + if ( (( (uint32_t)XMC_VADC_CHANNEL_EVGEN_INBOUND == chctr) \ + || ((uint32_t) XMC_VADC_CHANNEL_EVGEN_OUTBOUND == chctr)) && (ceflag) ) + { + retval = (bool)true; + } + + return retval; +} + +/* Set a reference voltage for conversion */ +void XMC_VADC_GROUP_ChannelSetInputReference(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_CHANNEL_REF_t ref) +{ + uint32_t chctr; + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetInputReference:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetInputReference:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetInputReference:Wrong Voltage Reference", ((ref)<= XMC_VADC_CHANNEL_REF_ALT_CH0)) + + chctr = group_ptr->CHCTR[ch_num]; + chctr &= ~((uint32_t)VADC_G_CHCTR_REFSEL_Msk); + chctr |= (uint32_t)((uint32_t)ref << VADC_G_CHCTR_REFSEL_Pos); + + group_ptr->CHCTR[ch_num] = chctr; +} + +/* API to select one of the available 16 registers for storing the channel result */ +void XMC_VADC_GROUP_ChannelSetResultRegister(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const uint32_t result_reg_num) +{ + uint32_t chctr; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetResultRegister:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetResultRegister:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetResultRegister:Wrong Result Register", + ((result_reg_num) < XMC_VADC_NUM_RESULT_REGISTERS)) + + chctr = group_ptr->CHCTR[ch_num]; + chctr &= ~((uint32_t)VADC_G_CHCTR_RESREG_Msk); + chctr |= (uint32_t)(result_reg_num << VADC_G_CHCTR_RESREG_Pos); + + group_ptr->CHCTR[ch_num] = chctr; +} + +/* API to select one of the available 4 class conversion */ +void XMC_VADC_GROUP_ChannelSetIclass(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_CHANNEL_CONV_t conversion_class) +{ + + uint32_t chctr; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetIclass:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetIclass:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetIclass:Wrong input class ", + (XMC_VADC_CHANNEL_CONV_GLOBAL_CLASS1 >= conversion_class)) + + chctr = group_ptr->CHCTR[ch_num]; + chctr &= ~((uint32_t)VADC_G_CHCTR_ICLSEL_Msk); + chctr |= (uint32_t)((uint32_t)conversion_class << (uint32_t)VADC_G_CHCTR_ICLSEL_Pos); + + group_ptr->CHCTR[ch_num] = chctr; + +} + +/* API to retrieve the result register bound with specified channel */ +uint8_t XMC_VADC_GROUP_ChannelGetResultRegister(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + uint8_t resreg; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetResultRegister:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelGetResultRegister:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + resreg = (uint8_t)((group_ptr->CHCTR[ch_num] & (uint32_t)VADC_G_CHCTR_RESREG_Msk) >> VADC_G_CHCTR_RESREG_Pos) ; + + return resreg; +} + +/* API to manually assert channel event */ +void XMC_VADC_GROUP_ChannelTriggerEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) +{ + uint32_t ceflag; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelTriggerEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelTriggerEvent:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + ceflag = group_ptr->CEFLAG; + ceflag |= (uint32_t)((uint32_t)1 << ch_num); + group_ptr->CEFLAG = ceflag; +} + +/* API to bind channel event with a service request (NVIC Node) */ +void XMC_VADC_GROUP_ChannelSetEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_SR_t sr) +{ + uint32_t route_mask; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetEventInterruptNode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetEventInterruptNode:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetEventInterruptNode:Wrong Service Request", ((sr) <= XMC_VADC_SR_SHARED_SR3)) + + route_mask = group_ptr->CEVNP0; + route_mask &= ~((uint32_t)15 << (ch_num * (uint32_t)4)); + route_mask |= (uint32_t)( (uint32_t)sr << (ch_num * (uint32_t)4)); + group_ptr->CEVNP0 = route_mask; +} + +/* API to configure conditions for generation of channel event */ +void XMC_VADC_GROUP_ChannelTriggerEventGenCriteria( XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + const XMC_VADC_CHANNEL_EVGEN_t criteria) +{ + uint32_t chctr; + + XMC_ASSERT("XMC_VADC_GROUP_ChannelTriggerEventGenCriteria:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelTriggerEventGenCriteria:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelTriggerEventGenCriteria:Wrong Event Generation Criteria", + ((criteria) <= XMC_VADC_CHANNEL_EVGEN_ALWAYS)) + + chctr = group_ptr->CHCTR[ch_num]; + chctr &= ~((uint32_t)VADC_G_CHCTR_CHEVMODE_Msk); + chctr |= (uint32_t)((uint32_t)criteria << VADC_G_CHCTR_CHEVMODE_Pos); + group_ptr->CHCTR[ch_num] = chctr; +} + +/* API to configure the boundary selection */ +void XMC_VADC_GROUP_ChannelSetBoundarySelection(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t ch_num, + XMC_VADC_BOUNDARY_SELECT_t boundary_sel, + XMC_VADC_CHANNEL_BOUNDARY_t selection) +{ + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetBoundarySelection:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetBoundarySelection:Wrong Channel Number", + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + + group_ptr->CHCTR[ch_num] &= ~((uint32_t)VADC_G_CHCTR_BNDSELL_Msk << boundary_sel); + group_ptr->CHCTR[ch_num] |= (selection<< ((uint32_t)VADC_G_CHCTR_BNDSELL_Pos + (uint32_t)boundary_sel)); +} + +/* Make the specified result register part of Result FIFO */ +void XMC_VADC_GROUP_AddResultToFifo(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + uint32_t fen; + + XMC_ASSERT("XMC_VADC_GROUP_AddResultToFifo:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_AddResultToFifo:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + /* Extract and clear the FIFO enable field */ + fen = group_ptr->RCR[res_reg]; + fen &= ~((uint32_t)VADC_G_RCR_FEN_Msk); + /* Set this register up as a FIFO member */ + fen |= (uint32_t)((uint32_t)1 << VADC_G_RCR_FEN_Pos); + group_ptr->RCR[res_reg] = fen; +} + + +/* Applicable to fast compare mode, this API sets up the value which is to be compared against conversion result */ +void XMC_VADC_GROUP_SetResultFastCompareValue(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg, + const XMC_VADC_RESULT_SIZE_t compare_val) +{ + uint32_t res = group_ptr->RES[res_reg]; + + XMC_ASSERT("XMC_VADC_GROUP_SetResultFastCompareValue:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetResultFastCompareValue:Wrong Result Register", + ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + res &= ~((uint32_t)VADC_G_RES_RESULT_Msk); + res |= (uint32_t)((uint32_t)compare_val << XMC_VADC_RESULT_LEFT_ALIGN_10BIT); + group_ptr->RES[res_reg] = res; +} + +/* API to retrieve the result of fast mode comparison */ +XMC_VADC_FAST_COMPARE_t XMC_VADC_GROUP_GetFastCompareResult(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + XMC_VADC_FAST_COMPARE_t result; + uint32_t res; + + XMC_ASSERT("XMC_VADC_GROUP_GetFastCompareResult:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetFastCompareResult:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + res = group_ptr->RES[res_reg]; + + if (res & (uint32_t)VADC_G_RES_VF_Msk) + { + result = (XMC_VADC_FAST_COMPARE_t)((uint32_t)(res >> (uint32_t)VADC_G_RES_FCR_Pos) & (uint32_t)1); + } + else + { + result = XMC_VADC_FAST_COMPARE_UNKNOWN; + } + + return result; +} + +/* Applicable to fast compare mode, this API sets up the value which is to be compared against conversion result */ +void XMC_VADC_GROUP_SetResultSubtractionValue(XMC_VADC_GROUP_t *const group_ptr, + const uint16_t subtraction_val) +{ + uint32_t res; + + XMC_ASSERT("XMC_VADC_GROUP_SetResultSubtractionValue:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + + res = group_ptr->RES[0]; + res &= ~((uint32_t)VADC_G_RES_RESULT_Msk); + res |= (uint32_t)subtraction_val; + group_ptr->RES[0] = res; +} + + +/* API to select a service request line (NVIC Node) for result event of specified unit of result hardware */ +void XMC_VADC_GROUP_SetResultInterruptNode(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg, + const XMC_VADC_SR_t sr) +{ + uint32_t route_mask; + + XMC_ASSERT("XMC_VADC_GROUP_SetResultInterruptNode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetResultInterruptNode:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + XMC_ASSERT("XMC_VADC_GROUP_SetResultInterruptNode:Wrong Service Request", ((sr) <= XMC_VADC_SR_SHARED_SR3)) + + if (res_reg <= 7U) + { + route_mask = group_ptr->REVNP0; + route_mask &= ~((uint32_t)((uint32_t)15 << (res_reg * (uint32_t)4) )); + route_mask |= (uint32_t)((uint32_t)sr << (res_reg * (uint32_t)4)); + group_ptr->REVNP0 = route_mask; + } + else + { + route_mask = group_ptr->REVNP1; + route_mask &= ~((uint32_t)((uint32_t)15 << (( res_reg - (uint32_t)8) * (uint32_t)4) )); + route_mask |= (uint32_t)((uint32_t)sr << ((res_reg - (uint32_t)8) * (uint32_t)4)); + group_ptr->REVNP1 = route_mask; + } +} + +/* API to retrieve the tail of the fifo which the specified result register is a part of */ +uint32_t XMC_VADC_GROUP_GetResultFifoTail(XMC_VADC_GROUP_t *const group_ptr, uint32_t res_reg) +{ + uint32_t tail; + uint32_t rcr; + int32_t i; + bool exit_flag; + + XMC_ASSERT("XMC_VADC_GROUP_GetResultFifoTail:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetResultFifoTail:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + tail = 0U; + exit_flag= (bool)false; + + if ((bool)true == XMC_VADC_GROUP_IsResultRegisterFifoHead(group_ptr, res_reg)) + { + res_reg = res_reg - 1U; + } + + /* Border condition */ + if (0U == res_reg) + { + tail = 0U; + } + else + { + /* Stop either at a node that does not have FEN set or at Node-0 */ + for(i = (int32_t)res_reg; i >= (int32_t)0; i--) + { + rcr = group_ptr->RCR[i]; + rcr &= (uint32_t)VADC_G_RCR_FEN_Msk; + + if (rcr) + { + if ((int32_t)0 == i) + { + /* No more nodes. Stop here */ + tail = (uint32_t)0; + exit_flag = (bool)true; + } + } + else + { + /* The preceding register forms the tail of the FIFO */ + tail = (uint32_t)i + (uint32_t)1; + exit_flag = (bool)true; + } + if (exit_flag) + { + break; + } + } + } + return tail; +} + +/* API to retrieve the head of the fifo which the specified result register is a part of */ +uint32_t XMC_VADC_GROUP_GetResultFifoHead(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + uint32_t head; + uint32_t rcr; + uint32_t i; + + XMC_ASSERT("XMC_VADC_GROUP_GetResultFifoHead:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_GetResultFifoHead:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + if ((bool)true == XMC_VADC_GROUP_IsResultRegisterFifoHead(group_ptr, res_reg)) + { + head = res_reg; + } + else + { + head = XMC_VADC_NUM_RESULT_REGISTERS - (uint32_t)1; + + for(i = res_reg; i < XMC_VADC_NUM_RESULT_REGISTERS ; i++) + { + rcr = group_ptr->RCR[i]; + rcr &= (uint32_t)VADC_G_RCR_FEN_Msk; + + if (!rcr) + { + /* This node forms the head of the FIFO */ + head = i ; + break; + } + } + } + return head; +} + +/* API to determine if the specified result register is the head of a result fifo */ +bool XMC_VADC_GROUP_IsResultRegisterFifoHead(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) +{ + bool ret_val; + uint32_t rcr_head; + uint32_t rcr_next; + + XMC_ASSERT("XMC_VADC_GROUP_IsResultRegisterFifoHead:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_IsResultRegisterFifoHead:Wrong Result Register", + ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + + rcr_head = group_ptr->RCR[res_reg]; + rcr_head &= (uint32_t)VADC_G_RCR_FEN_Msk; + rcr_next = group_ptr->RCR[res_reg - (uint32_t)1]; + rcr_next &= (uint32_t)VADC_G_RCR_FEN_Msk; + + if (rcr_head) + { + ret_val = (bool)false; + } + else if (rcr_next) + { + ret_val = (bool)true; + } + else + { + ret_val = (bool)false; + } + + return ret_val; +} + +#endif diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_wdt.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_wdt.c new file mode 100644 index 00000000..43018b1d --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Libraries/XMCLib/src/xmc_wdt.c @@ -0,0 +1,94 @@ +/** + * @file xmc_wdt.c + * @date 2015-06-20 + * + * @cond + ********************************************************************************************************************* + * XMClib v2.1.12 - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-02-20: + * - Initial
+ * + * 2015-06-20: + * - Removed definition of GetDriverVersion API
+ * + * @endcond + */ + +/********************************************************************************************************************* + * HEADER FILES + ********************************************************************************************************************/ +#include "xmc_wdt.h" +#include "xmc_scu.h" + +/********************************************************************************************************************* + * API IMPLEMENTATION + ********************************************************************************************************************/ + +/* Enables watchdog clock and releases watchdog reset. */ +void XMC_WDT_Enable(void) +{ +#if UC_FAMILY == XMC4 + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_WDT); +#endif + +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_WDT); +#endif +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_WDT); +#endif +} + +/* Disables watchdog clock and resets watchdog. */ +void XMC_WDT_Disable(void) +{ +#if defined(PERIPHERAL_RESET_SUPPORTED) + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_WDT); +#endif +#if defined(CLOCK_GATING_SUPPORTED) + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_WDT); +#endif + +#if UC_FAMILY == XMC4 + XMC_SCU_CLOCK_DisableClock(XMC_SCU_CLOCK_WDT); +#endif +} +/* Initializes and configures watchdog with configuration data pointed by \a config. */ +void XMC_WDT_Init(const XMC_WDT_CONFIG_t *const config) +{ + XMC_WDT_Enable(); + WDT->CTR = config->wdt_ctr; + WDT->WLB = config->window_lower_bound; + WDT->WUB = config->window_upper_bound; +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Startup/startup_XMC4700.S b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Startup/startup_XMC4700.S new file mode 100644 index 00000000..1130ec50 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Startup/startup_XMC4700.S @@ -0,0 +1,432 @@ +/********************************************************************************************************************* + * @file startup_XMC4700.S + * @brief CMSIS Core Device Startup File for Infineon XMC4700 Device Series + * @version V1.1 + * @date 05 Jan 2016 + * + * @cond + ********************************************************************************************************************* + * Copyright (c) 2015-2016, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + **************************** Change history ******************************** + * V1.0,Sep, 03, 2015 JFT:Initial version + * V1.1,Jan, 05, 2016 JFT:Fix .reset section attributes + * + * @endcond + */ + +/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ + +.macro Entry Handler + .long \Handler +.endm + +.macro Insert_ExceptionHandler Handler_Func + .weak \Handler_Func + .thumb_set \Handler_Func, Default_Handler +.endm + +/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */ + +/* ================== START OF VECTOR TABLE DEFINITION ====================== */ +/* Vector Table - This gets programed into VTOR register by onchip BootROM */ + .syntax unified + + .section .reset, "a", %progbits + + .align 2 + .globl __Vectors + .type __Vectors, %object +__Vectors: + .long __initial_sp /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + + Entry NMI_Handler /* NMI Handler */ + Entry HardFault_Handler /* Hard Fault Handler */ + Entry MemManage_Handler /* MPU Fault Handler */ + Entry BusFault_Handler /* Bus Fault Handler */ + Entry UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + Entry SVC_Handler /* SVCall Handler */ + Entry DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + Entry PendSV_Handler /* PendSV Handler */ + Entry SysTick_Handler /* SysTick Handler */ + + /* Interrupt Handlers for Service Requests (SR) from XMC4700 Peripherals */ + Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */ + Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */ + Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */ + Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */ + Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */ + Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */ + Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */ + Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */ + Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */ + .long 0 /* Not Available */ + Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */ + Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */ + Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */ + Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */ + Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */ + Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */ + Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */ + Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */ + Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */ + Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */ + Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */ + Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */ + Entry VADC0_G2_0_IRQHandler /* Handler name for SR VADC0_G2_0 */ + Entry VADC0_G2_1_IRQHandler /* Handler name for SR VADC0_G2_1 */ + Entry VADC0_G2_2_IRQHandler /* Handler name for SR VADC0_G2_2 */ + Entry VADC0_G2_3_IRQHandler /* Handler name for SR VADC0_G2_3 */ + Entry VADC0_G3_0_IRQHandler /* Handler name for SR VADC0_G3_0 */ + Entry VADC0_G3_1_IRQHandler /* Handler name for SR VADC0_G3_1 */ + Entry VADC0_G3_2_IRQHandler /* Handler name for SR VADC0_G3_2 */ + Entry VADC0_G3_3_IRQHandler /* Handler name for SR VADC0_G3_3 */ + Entry DSD0_0_IRQHandler /* Handler name for SR DSD0_0 */ + Entry DSD0_1_IRQHandler /* Handler name for SR DSD0_1 */ + Entry DSD0_2_IRQHandler /* Handler name for SR DSD0_2 */ + Entry DSD0_3_IRQHandler /* Handler name for SR DSD0_3 */ + Entry DSD0_4_IRQHandler /* Handler name for SR DSD0_4 */ + Entry DSD0_5_IRQHandler /* Handler name for SR DSD0_5 */ + Entry DSD0_6_IRQHandler /* Handler name for SR DSD0_6 */ + Entry DSD0_7_IRQHandler /* Handler name for SR DSD0_7 */ + Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */ + Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_0 */ + Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */ + Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */ + Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */ + Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */ + Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */ + Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */ + Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */ + Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */ + Entry CCU42_0_IRQHandler /* Handler name for SR CCU42_0 */ + Entry CCU42_1_IRQHandler /* Handler name for SR CCU42_1 */ + Entry CCU42_2_IRQHandler /* Handler name for SR CCU42_2 */ + Entry CCU42_3_IRQHandler /* Handler name for SR CCU42_3 */ + Entry CCU43_0_IRQHandler /* Handler name for SR CCU43_0 */ + Entry CCU43_1_IRQHandler /* Handler name for SR CCU43_1 */ + Entry CCU43_2_IRQHandler /* Handler name for SR CCU43_2 */ + Entry CCU43_3_IRQHandler /* Handler name for SR CCU43_3 */ + Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */ + Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */ + Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */ + Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */ + Entry CCU81_0_IRQHandler /* Handler name for SR CCU81_0 */ + Entry CCU81_1_IRQHandler /* Handler name for SR CCU81_1 */ + Entry CCU81_2_IRQHandler /* Handler name for SR CCU81_2 */ + Entry CCU81_3_IRQHandler /* Handler name for SR CCU81_3 */ + Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */ + Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */ + Entry POSIF1_0_IRQHandler /* Handler name for SR POSIF1_0 */ + Entry POSIF1_1_IRQHandler /* Handler name for SR POSIF1_1 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */ + Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */ + Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */ + Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */ + Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */ + Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */ + Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */ + Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */ + Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */ + Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */ + Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */ + Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */ + Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */ + Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */ + Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */ + Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */ + Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */ + Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */ + Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */ + Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */ + Entry USIC2_0_IRQHandler /* Handler name for SR USIC2_0 */ + Entry USIC2_1_IRQHandler /* Handler name for SR USIC2_1 */ + Entry USIC2_2_IRQHandler /* Handler name for SR USIC2_2 */ + Entry USIC2_3_IRQHandler /* Handler name for SR USIC2_3 */ + Entry USIC2_4_IRQHandler /* Handler name for SR USIC2_4 */ + Entry USIC2_5_IRQHandler /* Handler name for SR USIC2_5 */ + Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */ + .long 0 /* Not Available */ + Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */ + Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */ + Entry SDMMC0_0_IRQHandler /* Handler name for SR SDMMC0_0 */ + Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */ + Entry ETH0_0_IRQHandler /* Handler name for SR ETH0_0 */ + .long 0 /* Not Available */ + Entry GPDMA1_0_IRQHandler /* Handler name for SR GPDMA1_0 */ + .long 0 /* Not Available */ + .long 0x55AA11EE /* Reserved for OpenBLT checksum */ + + .size __Vectors, . - __Vectors +/* ================== END OF VECTOR TABLE DEFINITION ======================= */ + +/* ================== START OF VECTOR ROUTINES ============================= */ + + .align 1 + .thumb + +/* Reset Handler */ + .thumb_func + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp,=__initial_sp + +#ifndef __SKIP_SYSTEM_INIT + ldr r0, =SystemInit + blx r0 +#endif + +/* Initialize data + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: + +/* Zero initialized data + * Between symbol address __zero_table_start__ and __zero_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + * + * Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup. + */ +#ifndef __SKIP_BSS_CLEAR + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#endif /* __SKIP_BSS_CLEAR */ + +#ifndef __SKIP_LIBC_INIT_ARRAY + ldr r0, =__libc_init_array + blx r0 +#endif + + ldr r0, =main + blx r0 + +.align 2 +__copy_table_start__: + .long __data_load, __data_start, __data_size + .long __ram_code_load, __ram_code_start, __ram_code_size +__copy_table_end__: + +__zero_table_start__: + .long __bss_start, __bss_size + .long USB_RAM_start, USB_RAM_size + .long ETH_RAM_start, ETH_RAM_size +__zero_table_end__: + + .pool + .size Reset_Handler,.-Reset_Handler + +/* ======================================================================== */ +/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ + +/* Default exception Handlers - Users may override this default functionality by + defining handlers of the same name in their C code */ + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + Insert_ExceptionHandler NMI_Handler + Insert_ExceptionHandler HardFault_Handler + Insert_ExceptionHandler MemManage_Handler + Insert_ExceptionHandler BusFault_Handler + Insert_ExceptionHandler UsageFault_Handler + Insert_ExceptionHandler SVC_Handler + Insert_ExceptionHandler DebugMon_Handler + Insert_ExceptionHandler PendSV_Handler + Insert_ExceptionHandler SysTick_Handler + + Insert_ExceptionHandler SCU_0_IRQHandler + Insert_ExceptionHandler ERU0_0_IRQHandler + Insert_ExceptionHandler ERU0_1_IRQHandler + Insert_ExceptionHandler ERU0_2_IRQHandler + Insert_ExceptionHandler ERU0_3_IRQHandler + Insert_ExceptionHandler ERU1_0_IRQHandler + Insert_ExceptionHandler ERU1_1_IRQHandler + Insert_ExceptionHandler ERU1_2_IRQHandler + Insert_ExceptionHandler ERU1_3_IRQHandler + Insert_ExceptionHandler PMU0_0_IRQHandler + Insert_ExceptionHandler VADC0_C0_0_IRQHandler + Insert_ExceptionHandler VADC0_C0_1_IRQHandler + Insert_ExceptionHandler VADC0_C0_2_IRQHandler + Insert_ExceptionHandler VADC0_C0_3_IRQHandler + Insert_ExceptionHandler VADC0_G0_0_IRQHandler + Insert_ExceptionHandler VADC0_G0_1_IRQHandler + Insert_ExceptionHandler VADC0_G0_2_IRQHandler + Insert_ExceptionHandler VADC0_G0_3_IRQHandler + Insert_ExceptionHandler VADC0_G1_0_IRQHandler + Insert_ExceptionHandler VADC0_G1_1_IRQHandler + Insert_ExceptionHandler VADC0_G1_2_IRQHandler + Insert_ExceptionHandler VADC0_G1_3_IRQHandler + Insert_ExceptionHandler VADC0_G2_0_IRQHandler + Insert_ExceptionHandler VADC0_G2_1_IRQHandler + Insert_ExceptionHandler VADC0_G2_2_IRQHandler + Insert_ExceptionHandler VADC0_G2_3_IRQHandler + Insert_ExceptionHandler VADC0_G3_0_IRQHandler + Insert_ExceptionHandler VADC0_G3_1_IRQHandler + Insert_ExceptionHandler VADC0_G3_2_IRQHandler + Insert_ExceptionHandler VADC0_G3_3_IRQHandler + Insert_ExceptionHandler DSD0_0_IRQHandler + Insert_ExceptionHandler DSD0_1_IRQHandler + Insert_ExceptionHandler DSD0_2_IRQHandler + Insert_ExceptionHandler DSD0_3_IRQHandler + Insert_ExceptionHandler DSD0_4_IRQHandler + Insert_ExceptionHandler DSD0_5_IRQHandler + Insert_ExceptionHandler DSD0_6_IRQHandler + Insert_ExceptionHandler DSD0_7_IRQHandler + Insert_ExceptionHandler DAC0_0_IRQHandler + Insert_ExceptionHandler DAC0_1_IRQHandler + Insert_ExceptionHandler CCU40_0_IRQHandler + Insert_ExceptionHandler CCU40_1_IRQHandler + Insert_ExceptionHandler CCU40_2_IRQHandler + Insert_ExceptionHandler CCU40_3_IRQHandler + Insert_ExceptionHandler CCU41_0_IRQHandler + Insert_ExceptionHandler CCU41_1_IRQHandler + Insert_ExceptionHandler CCU41_2_IRQHandler + Insert_ExceptionHandler CCU41_3_IRQHandler + Insert_ExceptionHandler CCU42_0_IRQHandler + Insert_ExceptionHandler CCU42_1_IRQHandler + Insert_ExceptionHandler CCU42_2_IRQHandler + Insert_ExceptionHandler CCU42_3_IRQHandler + Insert_ExceptionHandler CCU43_0_IRQHandler + Insert_ExceptionHandler CCU43_1_IRQHandler + Insert_ExceptionHandler CCU43_2_IRQHandler + Insert_ExceptionHandler CCU43_3_IRQHandler + Insert_ExceptionHandler CCU80_0_IRQHandler + Insert_ExceptionHandler CCU80_1_IRQHandler + Insert_ExceptionHandler CCU80_2_IRQHandler + Insert_ExceptionHandler CCU80_3_IRQHandler + Insert_ExceptionHandler CCU81_0_IRQHandler + Insert_ExceptionHandler CCU81_1_IRQHandler + Insert_ExceptionHandler CCU81_2_IRQHandler + Insert_ExceptionHandler CCU81_3_IRQHandler + Insert_ExceptionHandler POSIF0_0_IRQHandler + Insert_ExceptionHandler POSIF0_1_IRQHandler + Insert_ExceptionHandler POSIF1_0_IRQHandler + Insert_ExceptionHandler POSIF1_1_IRQHandler + Insert_ExceptionHandler CAN0_0_IRQHandler + Insert_ExceptionHandler CAN0_1_IRQHandler + Insert_ExceptionHandler CAN0_2_IRQHandler + Insert_ExceptionHandler CAN0_3_IRQHandler + Insert_ExceptionHandler CAN0_4_IRQHandler + Insert_ExceptionHandler CAN0_5_IRQHandler + Insert_ExceptionHandler CAN0_6_IRQHandler + Insert_ExceptionHandler CAN0_7_IRQHandler + Insert_ExceptionHandler USIC0_0_IRQHandler + Insert_ExceptionHandler USIC0_1_IRQHandler + Insert_ExceptionHandler USIC0_2_IRQHandler + Insert_ExceptionHandler USIC0_3_IRQHandler + Insert_ExceptionHandler USIC0_4_IRQHandler + Insert_ExceptionHandler USIC0_5_IRQHandler + Insert_ExceptionHandler USIC1_0_IRQHandler + Insert_ExceptionHandler USIC1_1_IRQHandler + Insert_ExceptionHandler USIC1_2_IRQHandler + Insert_ExceptionHandler USIC1_3_IRQHandler + Insert_ExceptionHandler USIC1_4_IRQHandler + Insert_ExceptionHandler USIC1_5_IRQHandler + Insert_ExceptionHandler USIC2_0_IRQHandler + Insert_ExceptionHandler USIC2_1_IRQHandler + Insert_ExceptionHandler USIC2_2_IRQHandler + Insert_ExceptionHandler USIC2_3_IRQHandler + Insert_ExceptionHandler USIC2_4_IRQHandler + Insert_ExceptionHandler USIC2_5_IRQHandler + Insert_ExceptionHandler LEDTS0_0_IRQHandler + Insert_ExceptionHandler FCE0_0_IRQHandler + Insert_ExceptionHandler GPDMA0_0_IRQHandler + Insert_ExceptionHandler SDMMC0_0_IRQHandler + Insert_ExceptionHandler USB0_0_IRQHandler + Insert_ExceptionHandler ETH0_0_IRQHandler + Insert_ExceptionHandler GPDMA1_0_IRQHandler + +/* ============= END OF INTERRUPT HANDLER DEFINITION ====================== */ + + .end diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Startup/system_XMC4700.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Startup/system_XMC4700.c new file mode 100644 index 00000000..a95e951b --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/Startup/system_XMC4700.c @@ -0,0 +1,734 @@ +/********************************************************************************************************************* + * @file system_XMC4700.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the Infineon XMC4700 Device Series + * @version V1.0.3 + * @date 09. Feb 2017 + * + * @cond + ********************************************************************************************************************* + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + ********************** Version History *************************************** + * V1.0.0, 03. Sep 2015, Initial version + * V1.0.1, 26. Jan 2016, Disable trap generation from clock unit + * V1.0.2, 01. Jun 2016, Fix masking of OSCHPCTRL value + * V1.0.3, 09. Feb 2017, Fix activation of USBPLL when SDMMC clock is enabled + ****************************************************************************** + * @endcond + */ + +/******************************************************************************* + * Default clock initialization + * fPLL = 288MHz => fSYS = 144MHz => fCPU = 144MHz + * => fPB = 144MHz + * => fCCU = 144MHz + * => fETH = 72MHz + * => fUSB = 48MHz + * => fEBU = 72MHz + * + * fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected + * + * fOFI = 24MHz => fWDT = 24MHz + *******************************************************************************/ + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#include + +#include +#include "system_XMC4700.h" + +/******************************************************************************* + * MACROS + *******************************************************************************/ + +#define CHIPID_LOC ((uint8_t *)0x20000000UL) + +/* Define WEAK attribute */ +#if !defined(__WEAK) +#if defined ( __CC_ARM ) +#define __WEAK __attribute__ ((weak)) +#elif defined ( __ICCARM__ ) +#define __WEAK __weak +#elif defined ( __GNUC__ ) +#define __WEAK __attribute__ ((weak)) +#elif defined ( __TASKING__ ) +#define __WEAK __attribute__ ((weak)) +#endif +#endif + +#define PMU_FLASH_WS (0x4U) + +#define FOSCREF (2500000U) + +#define DELAY_CNT_50US_50MHZ (2500UL) +#define DELAY_CNT_150US_50MHZ (7500UL) +#define DELAY_CNT_50US_48MHZ (2400UL) +#define DELAY_CNT_50US_72MHZ (3600UL) +#define DELAY_CNT_50US_96MHZ (4800UL) +#define DELAY_CNT_50US_120MHZ (6000UL) +#define DELAY_CNT_50US_144MHZ (7200UL) + +#define SCU_PLL_PLLSTAT_OSC_USABLE (SCU_PLL_PLLSTAT_PLLHV_Msk | \ + SCU_PLL_PLLSTAT_PLLLV_Msk | \ + SCU_PLL_PLLSTAT_PLLSP_Msk) + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/* +// Clock configuration +*/ + +/* +// External crystal frequency [Hz] +// <8000000=> 8MHz +// <12000000=> 12MHz +// <16000000=> 16MHz +// Defines external crystal frequency +// Default: 8MHz +*/ +#define OSCHP_FREQUENCY (12000000U) + +/* USB PLL settings, fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz */ +/* Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and fUSBPLLVCO <= 520 MHz*/ +#if OSCHP_FREQUENCY == 8000000U +#define USB_PDIV (1U) +#define USB_NDIV (95U) + +#elif OSCHP_FREQUENCY == 12000000U +#define USB_PDIV (1U) +#define USB_NDIV (63U) + +#elif OSCHP_FREQUENCY == 16000000U +#define USB_PDIV (1U) +#define USB_NDIV (47U) + +#else +#error "External crystal frequency not supported" + +#endif + +/* +// Backup clock calibration mode +// <0=> Factory calibration +// <1=> Automatic calibration +// Default: Automatic calibration +*/ +#define FOFI_CALIBRATION_MODE 1 +#define FOFI_CALIBRATION_MODE_FACTORY 0 +#define FOFI_CALIBRATION_MODE_AUTOMATIC 1 + +/* +// Standby clock (fSTDBY) source selection +// <0=> Internal slow oscillator (32768Hz) +// <1=> External crystal (32768Hz) +// Default: Internal slow oscillator (32768Hz) +*/ +#define STDBY_CLOCK_SRC 0 +#define STDBY_CLOCK_SRC_OSI 0 +#define STDBY_CLOCK_SRC_OSCULP 1 + +/* +// PLL clock source selection +// <0=> External crystal +// <1=> Internal fast oscillator +// Default: External crystal +*/ +#define PLL_CLOCK_SRC 0 +#define PLL_CLOCK_SRC_EXT_XTAL 0 +#define PLL_CLOCK_SRC_OFI 1 + +/* PLL settings, fPLL = 288MHz */ +#if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL +#if OSCHP_FREQUENCY == 8000000U +#define PLL_PDIV (1U) +#define PLL_NDIV (71U) +#define PLL_K2DIV (0U) + +#elif OSCHP_FREQUENCY == 12000000U +#define PLL_PDIV (1U) +#define PLL_NDIV (47U) +#define PLL_K2DIV (0U) + +#elif OSCHP_FREQUENCY == 16000000U +#define PLL_PDIV (1U) +#define PLL_NDIV (35U) +#define PLL_K2DIV (0U) + +#else +#error "External crystal frequency not supported" + +#endif + +#define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL)) + +#else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */ +#define PLL_PDIV (1U) +#define PLL_NDIV (23U) +#define PLL_K2DIV (0U) + +#define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL)) + +#endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */ + +#define PLL_K2DIV_24MHZ ((VCO / OFI_FREQUENCY) - 1UL) +#define PLL_K2DIV_48MHZ ((VCO / 48000000U) - 1UL) +#define PLL_K2DIV_72MHZ ((VCO / 72000000U) - 1UL) +#define PLL_K2DIV_96MHZ ((VCO / 96000000U) - 1UL) +#define PLL_K2DIV_120MHZ ((VCO / 120000000U) - 1UL) + +#define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_MMCCLK SCU_CLK_CLKCLR_MMCCDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_ETHCLK SCU_CLK_CLKCLR_ETH0CDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_EBUCLK SCU_CLK_CLKCLR_EBUCDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk + +#define SCU_CLK_SYSCLKCR_SYSSEL_OFI (0U << SCU_CLK_SYSCLKCR_SYSSEL_Pos) +#define SCU_CLK_SYSCLKCR_SYSSEL_PLL (1U << SCU_CLK_SYSCLKCR_SYSSEL_Pos) + +#define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos) +#define SCU_CLK_USBCLKCR_USBSEL_PLL (1U << SCU_CLK_USBCLKCR_USBSEL_Pos) + +#define SCU_CLK_WDTCLKCR_WDTSEL_OFI (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) +#define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) +#define SCU_CLK_WDTCLKCR_WDTSEL_PLL (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) + +#define SCU_CLK_EXTCLKCR_ECKSEL_SYS (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) +#define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) +#define SCU_CLK_EXTCLKCR_ECKSEL_PLL (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) + +#define EXTCLK_PIN_P0_8 (1) +#define EXTCLK_PIN_P1_15 (2) + +/* +// Clock tree +// System clock source selection +// <0=> fOFI +// <1=> fPLL +// Default: fPLL +// System clock divider <1-256><#-1> +// Default: 2 +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Default: fCPU = fSYS +// Peripheral clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// Default: fPB = fCPU +// CCU clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// Default: fCCU = fCPU +// Enable WDT clock +// WDT clock source <0=> fOFI +// <1=> fSTDBY +// <2=> fPLL +// Default: fOFI +// WDT clock divider <1-256><#-1> +// Default: 1 +// +// Enable EBU clock +// EBU clock divider <1-64><#-1> +// Default: 4 +// +// Enable ETH clock +// +// Enable MMC clock +// +// Enable USB clock +// USB clock source <0=> fUSBPLL +// <1=> fPLL +// Default: fPLL +// +// Enable external clock +// External Clock Source Selection +// <0=> fSYS +// <2=> fUSB +// <3=> fPLL +// Default: fPLL +// External Clock divider <1-512><#-1> +// Default: 288 +// Only valid for USB PLL and PLL clocks +// External Clock Pin Selection +// <0=> Disabled +// <1=> P0.8 +// <2=> P1.15 +// Default: Disabled +// +// +*/ +#define __CLKSET (0x00000000UL) +#define __SYSCLKCR (0x00010001UL) +#define __CPUCLKCR (0x00000000UL) +#define __PBCLKCR (0x00000000UL) +#define __CCUCLKCR (0x00000000UL) +#define __WDTCLKCR (0x00000000UL) +#define __EBUCLKCR (0x00000003UL) +#define __USBCLKCR (0x00010000UL) + +#define __EXTCLKCR (0x01200003UL) +#define __EXTCLKPIN (0U) + +/* +// +*/ + +/* +//-------- <<< end of configuration section >>> ------------------ +*/ + +#define ENABLE_PLL \ + (((__SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) == SCU_CLK_SYSCLKCR_SYSSEL_PLL) || \ + ((__CLKSET & SCU_CLK_CLKSET_EBUCEN_Msk) != 0) || \ + (((__CLKSET & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \ + (((__CLKSET & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && ((__WDTCLKCR & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL))) + +#define ENABLE_USBPLL \ + ((((__CLKSET & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL)) || \ + (((__CLKSET & SCU_CLK_CLKSET_MMCCEN_Msk) != 0) && ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL))) + +#if ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL) +#define USB_DIV (3U) +#else +#define USB_DIV (5U) +#endif + +/******************************************************************************* + * GLOBAL VARIABLES + *******************************************************************************/ +#if defined ( __CC_ARM ) +#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) +uint32_t SystemCoreClock __attribute__((at(0x2003FFC0))); +uint8_t g_chipid[16] __attribute__((at(0x2003FFC4))); +#elif defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536) +uint32_t SystemCoreClock __attribute__((at(0x2002CFC0))); +uint8_t g_chipid[16] __attribute__((at(0x2002CFC4))); +#else +#error "system_XMC4700.c: device not supported" +#endif +#elif defined ( __ICCARM__ ) +#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) || \ + defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536) +__no_init uint32_t SystemCoreClock; +__no_init uint8_t g_chipid[16]; +#else +#error "system_XMC4700.c: device not supported" +#endif +#elif defined ( __GNUC__ ) +#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) || \ + defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536) +uint32_t SystemCoreClock __attribute__((section(".no_init"))); +uint8_t g_chipid[16] __attribute__((section(".no_init"))); +#else +#error "system_XMC4700.c: device not supported" +#endif +#elif defined ( __TASKING__ ) +#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) +uint32_t SystemCoreClock __at( 0x2003FFC0 ); +uint8_t g_chipid[16] __at( 0x2003FFC4 ); +#elif defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536) +uint32_t SystemCoreClock __at( 0x2002CFC0 ); +uint8_t g_chipid[16] __at( 0x2002CFC4 ); +#else +#error "system_XMC4700.c: device not supported" +#endif +#else +#error "system_XMC4700.c: compiler not supported" +#endif + +extern uint32_t __Vectors; + +/******************************************************************************* + * LOCAL FUNCTIONS + *******************************************************************************/ +static void delay(uint32_t cycles) +{ + volatile uint32_t i; + + for(i = 0UL; i < cycles ;++i) + { + __NOP(); + } +} + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +__WEAK void SystemInit(void) +{ + memcpy(g_chipid, CHIPID_LOC, 16); + + SystemCoreSetup(); + SystemCoreClockSetup(); +} + +__WEAK void SystemCoreSetup(void) +{ + uint32_t temp; + + /* relocate vector table */ + __disable_irq(); + SCB->VTOR = (uint32_t)(&__Vectors); + __DSB(); + __enable_irq(); + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + + /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ + SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + + temp = FLASH0->FCON; + temp &= ~FLASH_FCON_WSPFLASH_Msk; + temp |= PMU_FLASH_WS; + FLASH0->FCON = temp; +} + +__WEAK void SystemCoreClockSetup(void) +{ +#if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY + /* Enable factory calibration */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk; +#else + /* Automatic calibration uses the fSTDBY */ + + /* Enable HIB domain */ + /* Power up HIB domain if and only if it is currently powered down */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + { + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; + + while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + { + /* wait until HIB domain is enabled */ + } + } + + /* Remove the reset only if HIB domain were in a state of reset */ + if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) + { + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; + delay(DELAY_CNT_150US_50MHZ); + } + +#if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP + /* Enable OSC_ULP */ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL) + { + /*enable OSC_ULP*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; + + /* Check if the clock is OK using OSCULP Oscillator Watchdog*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + + /* wait till clock is stable */ + do + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + + delay(DELAY_CNT_50US_50MHZ); + + } while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL); + + } + + /* now OSC_ULP is running and can be used*/ + /* Select OSC_ULP as the clock source for RTC and STDBY*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk; +#endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */ + + /* Enable automatic calibration of internal fast oscillator */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; +#endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */ + + delay(DELAY_CNT_50US_50MHZ); + +#if ENABLE_PLL + + /* enable PLL */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +#if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI + /* enable OSC_HP */ + if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U) + { + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk); + SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos; + + /* select OSC_HP clock as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE) + { + /* wait till OSC_HP output frequency is usable */ + } + } +#else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */ + + /* select backup clock as PLL input */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; +#endif + + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + + /* disconnect Oscillator from PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + + /* Setup divider settings for main PLL */ + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_24MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + /* Set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + /* connect Oscillator to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U) + { + /* wait for PLL Lock at 24MHz*/ + } + + /* Disable bypass- put PLL clock back */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U) + { + /* wait for normal mode */ + } +#endif /* ENABLE_PLL */ + + /* Before scaling to final frequency we need to setup the clock dividers */ + SCU_CLK->SYSCLKCR = __SYSCLKCR; + SCU_CLK->PBCLKCR = __PBCLKCR; + SCU_CLK->CPUCLKCR = __CPUCLKCR; + SCU_CLK->CCUCLKCR = __CCUCLKCR; + SCU_CLK->WDTCLKCR = __WDTCLKCR; + SCU_CLK->EBUCLKCR = __EBUCLKCR; + SCU_CLK->USBCLKCR = __USBCLKCR | USB_DIV; + SCU_CLK->EXTCLKCR = __EXTCLKCR; + +#if ENABLE_PLL + /* PLL frequency stepping...*/ + /* Reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_48MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + delay(DELAY_CNT_50US_48MHZ); + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_72MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + delay(DELAY_CNT_50US_72MHZ); + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_96MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + delay(DELAY_CNT_50US_96MHZ); + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_120MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + delay(DELAY_CNT_50US_120MHZ); + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + delay(DELAY_CNT_50US_144MHZ); + +#endif /* ENABLE_PLL */ + +#if ENABLE_USBPLL + /* enable USB PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); + + /* USB PLL uses as clock input the OSC_HP */ + /* check and if not already running enable OSC_HP */ + if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U) + { + /* check if Main PLL is switched on for OSC WDG*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL) + { + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk); + SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos; + + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE) + { + /* wait till OSC_HP output frequency is usable */ + } + } + + + /* Setup USB PLL */ + /* Go to bypass the USB PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + + /* disconnect Oscillator from USB PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + + /* Setup Divider settings for USB PLL */ + SCU_PLL->USBPLLCON = ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) | + (USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos)); + + /* Set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + + /* connect Oscillator to USB PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + + while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U) + { + /* wait for PLL Lock */ + } +#endif + + + /* Enable selected clocks */ + SCU_CLK->CLKSET = __CLKSET; + +#if __EXTCLKPIN != 0 +#if __EXTCLKPIN == EXTCLK_PIN_P1_15 + /* P1.15 */ + PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk; + PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT0_IOCR12_PC15_Msk) | (0x11U << PORT0_IOCR12_PC15_Pos); +#else + /* P0.8 */ + PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk; + PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk; + PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos); +#endif +#endif /* ENABLE_EXTCLK == 1 */ + + SystemCoreClockUpdate(); +} + +__WEAK void SystemCoreClockUpdate(void) +{ + uint32_t pdiv; + uint32_t ndiv; + uint32_t kdiv; + uint32_t temp; + + if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) + { + /* fPLL is clock source for fSYS */ + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk) + { + /* PLL input clock is the backup clock (fOFI) */ + temp = OFI_FREQUENCY; + } + else + { + /* PLL input clock is the high performance osicllator (fOSCHP) */ + temp = OSCHP_GetFrequency(); + } + + /* check if PLL is locked */ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* PLL normal mode */ + /* read back divider settings */ + pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1; + ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1; + kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1; + + temp = (temp / (pdiv * kdiv)) * ndiv; + } + else + { + /* PLL prescalar mode */ + /* read back divider settings */ + kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1; + + temp = (temp / kdiv); + } + } + else + { + /* fOFI is clock source for fSYS */ + temp = OFI_FREQUENCY; + } + + temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1); + temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1); + + SystemCoreClock = temp; +} + +__WEAK uint32_t OSCHP_GetFrequency(void) +{ + return OSCHP_FREQUENCY; +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/boot.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/boot.c new file mode 100644 index 00000000..6cddf4f0 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/boot.c @@ -0,0 +1,357 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Prog\boot.c +* \brief Demo program bootloader interface source file. +* \ingroup Prog_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ +#include "xmc_gpio.h" /* GPIO module */ +#include "xmc_uart.h" /* UART driver header */ +#include "xmc_can.h" /* CAN driver header */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +#if (BOOT_COM_UART_ENABLE > 0) +static void BootComUartInit(void); +static void BootComUartCheckActivationRequest(void); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) +static void BootComCanInit(void); +static void BootComCanCheckActivationRequest(void); +#endif + +/************************************************************************************//** +** \brief Initializes the communication interface. +** \return none. +** +****************************************************************************************/ +void BootComInit(void) +{ +#if (BOOT_COM_UART_ENABLE > 0) + BootComUartInit(); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + BootComCanInit(); +#endif +} /*** end of BootComInit ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +void BootComCheckActivationRequest(void) +{ +#if (BOOT_COM_UART_ENABLE > 0) + BootComUartCheckActivationRequest(); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + BootComCanCheckActivationRequest(); +#endif +} /*** end of BootComCheckActivationRequest ***/ + + +/************************************************************************************//** +** \brief Bootloader activation function. +** \return none. +** +****************************************************************************************/ +void BootActivate(void) +{ + /* perform software reset to activate the bootoader again */ + NVIC_SystemReset(); +} /*** end of BootActivate ***/ + + +#if (BOOT_COM_UART_ENABLE > 0) +/**************************************************************************************** +* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E +****************************************************************************************/ + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static unsigned char UartReceiveByte(unsigned char *data); + + +/************************************************************************************//** +** \brief Initializes the UART communication interface. +** \return none. +** +****************************************************************************************/ +static void BootComUartInit(void) +{ + XMC_GPIO_CONFIG_t rx_config; + XMC_GPIO_CONFIG_t tx_config; + XMC_UART_CH_CONFIG_t uart_config; + + /* set configuration and initialize UART channel */ + uart_config.baudrate = BOOT_COM_UART_BAUDRATE; + uart_config.data_bits = 8; + uart_config.frame_length = 8; + uart_config.stop_bits = 1; + uart_config.oversampling = 16; + uart_config.parity_mode = XMC_USIC_CH_PARITY_MODE_NONE; + XMC_UART_CH_Init(XMC_UART0_CH0, &uart_config); + /* initialize UART Rx pin */ + rx_config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; + rx_config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; + rx_config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE; + XMC_GPIO_Init(P1_4, &rx_config); + /* initialize UART Tx pin */ + tx_config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2; + tx_config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; + tx_config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE; + XMC_GPIO_Init(P1_5, &tx_config); + /* set input source path to DXnB to connect P1_4 to ASC Receive. note that this + * function must be called after XMC_UART_CH_Init(), which is called when initializing + * the bootloader core with BootInit(). + */ + XMC_USIC_CH_SetInputSource(XMC_UART0_CH0, XMC_USIC_CH_INPUT_DX0, 1U); + /* configure small transmit and receive FIFO */ + XMC_USIC_CH_TXFIFO_Configure(XMC_UART0_CH0, 16U, XMC_USIC_CH_FIFO_SIZE_16WORDS, 1U); + XMC_USIC_CH_RXFIFO_Configure(XMC_UART0_CH0, 0U, XMC_USIC_CH_FIFO_SIZE_16WORDS, 1U); + /* start UART */ + XMC_UART_CH_Start(XMC_UART0_CH0); +} /*** end of BootComUartInit ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +static void BootComUartCheckActivationRequest(void) +{ + static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1]; + static unsigned char xcpCtoRxLength; + static unsigned char xcpCtoRxInProgress = 0; + + /* start of cto packet received? */ + if (xcpCtoRxInProgress == 0) + { + /* store the message length when received */ + if (UartReceiveByte(&xcpCtoReqPacket[0]) == 1) + { + /* indicate that a cto packet is being received */ + xcpCtoRxInProgress = 1; + + /* reset packet data count */ + xcpCtoRxLength = 0; + } + } + else + { + /* store the next packet byte */ + if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1) + { + /* increment the packet data count */ + xcpCtoRxLength++; + + /* check to see if the entire packet was received */ + if (xcpCtoRxLength == xcpCtoReqPacket[0]) + { + /* done with cto packet reception */ + xcpCtoRxInProgress = 0; + + /* check if this was an XCP CONNECT command */ + if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00)) + { + /* connection request received so start the bootloader */ + BootActivate(); + } + } + } + } +} /*** end of BootComUartCheckActivationRequest ***/ + + +/************************************************************************************//** +** \brief Receives a communication interface byte if one is present. +** \param data Pointer to byte where the data is to be stored. +** \return 1 if a byte was received, 0 otherwise. +** +****************************************************************************************/ +static unsigned char UartReceiveByte(unsigned char *data) +{ + if (XMC_USIC_CH_RXFIFO_IsEmpty(XMC_UART0_CH0) == 0) + { + /* retrieve and store the newly received byte */ + *data = (unsigned char)XMC_UART_CH_GetReceivedData(XMC_UART0_CH0); + /* all done */ + return 1; + } + /* still here to no new byte received */ + return 0; +} /*** end of UartReceiveByte ***/ +#endif /* BOOT_COM_UART_ENABLE > 0 */ + + +#if (BOOT_COM_CAN_ENABLE > 0) +/**************************************************************************************** +* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E +****************************************************************************************/ + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Receive message object data structure. */ +static XMC_CAN_MO_t receiveMsgObj; + + +/************************************************************************************//** +** \brief Initializes the CAN communication interface. +** \return none. +** +****************************************************************************************/ +static void BootComCanInit(void) +{ + XMC_GPIO_CONFIG_t rx_can_config; + XMC_GPIO_CONFIG_t tx_can_config; + unsigned char byteIdx; + unsigned long canModuleFreqHz; + XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t baud; + + /* decide on fCAN frequency. it should be in the 5-120MHz range. according to the + * datasheet, it must be at least 12MHz if 1 node (channel) is used with up to + * 16 message objects. This is sufficient for this CAN driver. + */ + canModuleFreqHz = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + /* increase if too low */ + while (canModuleFreqHz < 12000000) + { + canModuleFreqHz *= 2; + } + /* decrease if too high */ + while (canModuleFreqHz > 120000000) + { + canModuleFreqHz /= 2; + } + + /* configure CAN module*/ + XMC_CAN_Init(CAN, XMC_CAN_CANCLKSRC_FPERI, canModuleFreqHz); + + /* configure CAN node baudrate */ + baud.can_frequency = canModuleFreqHz; + baud.baudrate = BOOT_COM_CAN_BAUDRATE; + baud.sample_point = 8000; + baud.sjw = 1, + XMC_CAN_NODE_NominalBitTimeConfigure(CAN_NODE1, &baud); + + /* set CCE and INIT bit NCR for node configuration */ + XMC_CAN_NODE_EnableConfigurationChange(CAN_NODE1); + XMC_CAN_NODE_SetInitBit(CAN_NODE1); + + /* configure the receive message object */ + receiveMsgObj.can_mo_ptr = CAN_MO1; + receiveMsgObj.can_priority = XMC_CAN_ARBITRATION_MODE_IDE_DIR_BASED_PRIO_2; + receiveMsgObj.can_identifier = BOOT_COM_CAN_RX_MSG_ID; + receiveMsgObj.can_id_mask= BOOT_COM_CAN_RX_MSG_ID; + receiveMsgObj.can_id_mode = XMC_CAN_FRAME_TYPE_STANDARD_11BITS; + receiveMsgObj.can_ide_mask = 1; + receiveMsgObj.can_data_length = BOOT_COM_CAN_RX_MAX_DATA; + for (byteIdx=0; byteIdx 0 */ + + +/*********************************** end of boot.c *************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/boot.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/boot.h new file mode 100644 index 00000000..f0cb9950 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/boot.h @@ -0,0 +1,40 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Prog\boot.h +* \brief Demo program bootloader interface header file. +* \ingroup Prog_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef BOOT_H +#define BOOT_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void BootComInit(void); +void BootComCheckActivationRequest(void); +void BootActivate(void); + + +#endif /* BOOT_H */ +/*********************************** end of boot.h *************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/demoprog_xmc4700.launch b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/demoprog_xmc4700.launch new file mode 100644 index 00000000..47403739 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/demoprog_xmc4700.launch @@ -0,0 +1,85 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/header.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/header.h new file mode 100644 index 00000000..5c0503a0 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/header.h @@ -0,0 +1,42 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Prog\header.h +* \brief Generic header file. +* \ingroup Prog_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef HEADER_H +#define HEADER_H + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "../Boot/blt_conf.h" /* bootloader configuration */ +#include "XMC4700.h" /* XMC4700 peripheral access */ +#include "boot.h" /* bootloader interface driver */ +#include "led.h" /* LED driver */ +#include "timer.h" /* Timer driver */ + + +#endif /* HEADER_H */ +/*********************************** end of header.h ***********************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/led.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/led.c new file mode 100644 index 00000000..78c66aa9 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/led.c @@ -0,0 +1,96 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Prog\led.c +* \brief LED driver source file. +* \ingroup Prog_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ +#include "xmc_gpio.h" /* GPIO module */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Toggle interval time in milliseconds. */ +#define LED_TOGGLE_MS (500) + + +/************************************************************************************//** +** \brief Initializes the LED. The board doesn't have a dedicted LED so an +** indicator on the LCD is used instead. +** \return none. +** +****************************************************************************************/ +void LedInit(void) +{ + /* initialize LED2 on P5.8 as digital output */ + XMC_GPIO_SetMode(P5_8, XMC_GPIO_MODE_OUTPUT_PUSH_PULL); + /* turn off LED2 */ + XMC_GPIO_SetOutputLevel(P5_8, XMC_GPIO_OUTPUT_LEVEL_LOW); +} /*** end of LedInit ***/ + + +/************************************************************************************//** +** \brief Toggles the LED at a fixed time interval. +** \return none. +** +****************************************************************************************/ +void LedToggle(void) +{ + static unsigned char led_toggle_state = 0; + static unsigned long timer_counter_last = 0; + unsigned long timer_counter_now; + + /* check if toggle interval time passed */ + timer_counter_now = TimerGet(); + if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS) + { + /* not yet time to toggle */ + return; + } + + /* determine toggle action */ + if (led_toggle_state == 0) + { + led_toggle_state = 1; + /* turn the LED on */ + XMC_GPIO_SetOutputLevel(P5_8, XMC_GPIO_OUTPUT_LEVEL_HIGH); + } + else + { + led_toggle_state = 0; + /* turn the LED off */ + XMC_GPIO_SetOutputLevel(P5_8, XMC_GPIO_OUTPUT_LEVEL_LOW); + } + + /* store toggle time to determine next toggle interval */ + timer_counter_last = timer_counter_now; +} /*** end of LedToggle ***/ + + +/*********************************** end of led.c **************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/led.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/led.h new file mode 100644 index 00000000..4821143f --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/led.h @@ -0,0 +1,39 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Prog\led.h +* \brief LED driver header file. +* \ingroup Prog_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef LED_H +#define LED_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void LedInit(void); +void LedToggle(void); + + +#endif /* LED_H */ +/*********************************** end of led.h **************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/linker_script.ld b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/linker_script.ld new file mode 100644 index 00000000..85ec3194 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/linker_script.ld @@ -0,0 +1,288 @@ +/** + * @file XMC4700x2048.ld + * @date 2017-04-20 + * + * @cond + ********************************************************************************************************************* + * Linker file for the GNU C Compiler v1.3 + * Supported devices: XMC4700-E196x2048 + * XMC4700-F144x2048 + * XMC4700-F100x2048 + * + * Copyright (c) 2015-2017, Infineon Technologies AG + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the + * following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with + * Infineon Technologies AG dave@infineon.com). + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-09-03: + * - Initial version + * + * 2016-03-08: + * - Fix size of BSS and DATA sections to be multiple of 4 + * - Add assertion to check that region SRAM_combined does not overflowed no_init section + * + * 2017-04-07: + * - Added new symbols __text_size and eText + * + * 2017-04-20: + * - Change vtable location to flash area to save ram + * + * @endcond + * + */ + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Reset_Handler) + +stack_size = DEFINED(stack_size) ? stack_size : 2048; +no_init_size = 64; + +MEMORY +{ + FLASH_1_cached(RX) : ORIGIN = 0x08004000, LENGTH = 0x00200000 - 16K + FLASH_1_uncached(RX) : ORIGIN = 0x0C004000, LENGTH = 0x00200000 - 16K + PSRAM_1(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x18000 + DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x20000 + DSRAM_2_comm(!RX) : ORIGIN = 0x20020000, LENGTH = 0x20000 + SRAM_combined(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x00058000 +} + +SECTIONS +{ + /* TEXT section */ + + .text : + { + sText = .; + KEEP(*(.reset)); + *(.text .text.* .gnu.linkonce.t.*); + + /* C++ Support */ + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata .rodata.*) + *(.gnu.linkonce.r*) + + *(vtable) + . = ALIGN(4); + } > FLASH_1_cached AT > FLASH_1_uncached + + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + } > FLASH_1_cached AT > FLASH_1_uncached + + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) + } > FLASH_1_cached AT > FLASH_1_uncached + + /* Exception handling, exidx needs a dedicated section */ + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH_1_cached AT > FLASH_1_uncached + + . = ALIGN(4); + __exidx_start = .; + .ARM.exidx : ALIGN(4) + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH_1_cached AT > FLASH_1_uncached + __exidx_end = .; + . = ALIGN(4); + + /* DSRAM layout (Lowest to highest)*/ + Stack (NOLOAD) : + { + __stack_start = .; + . = . + stack_size; + __stack_end = .; + __initial_sp = .; + } > SRAM_combined + + /* functions with __attribute__((section(".ram_code"))) */ + .ram_code : + { + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __ram_code_start = .; + *(.ram_code) + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __ram_code_end = .; + } > SRAM_combined AT > FLASH_1_uncached + __ram_code_load = LOADADDR (.ram_code); + __ram_code_size = __ram_code_end - __ram_code_start; + + /* Standard DATA and user defined DATA/BSS/CONST sections */ + .data : + { + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __data_start = .; + * (.data); + * (.data*); + *(*.data); + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __data_end = .; + } > SRAM_combined AT > FLASH_1_uncached + __data_load = LOADADDR (.data); + __data_size = __data_end - __data_start; + + __text_size = (__exidx_end - sText) + __data_size + __ram_code_size; + eText = sText + __text_size; + + /* BSS section */ + .bss (NOLOAD) : + { + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __bss_start = .; + * (.bss); + * (.bss*); + * (COMMON); + *(.gnu.linkonce.b*) + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __bss_end = .; + } > SRAM_combined + __bss_size = __bss_end - __bss_start; + + /* Shift location counter, so that ETH_RAM and USB_RAM are located above DSRAM_1_system */ + __shift_loc = (__bss_end >= ORIGIN(DSRAM_1_system)) ? 0 : (ORIGIN(DSRAM_1_system) - __bss_end); + + USB_RAM (__bss_end + __shift_loc) (NOLOAD) : + { + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + USB_RAM_start = .; + *(USB_RAM) + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + USB_RAM_end = .; + } > SRAM_combined + USB_RAM_size = USB_RAM_end - USB_RAM_start; + + ETH_RAM (USB_RAM_end) (NOLOAD) : + { + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + ETH_RAM_start = .; + *(ETH_RAM) + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + ETH_RAM_end = .; + . = ALIGN(8); + Heap_Bank1_Start = .; + } > SRAM_combined + ETH_RAM_size = ETH_RAM_end - ETH_RAM_start; + + /* .no_init section contains chipid, SystemCoreClock and trimming data. See system.c file*/ + .no_init ORIGIN(SRAM_combined) + LENGTH(SRAM_combined) - no_init_size (NOLOAD) : + { + Heap_Bank1_End = .; + * (.no_init); + } > SRAM_combined + + /* Heap - Bank1*/ + Heap_Bank1_Size = Heap_Bank1_End - Heap_Bank1_Start; + + ASSERT(Heap_Bank1_Start <= Heap_Bank1_End, "region SRAM_combined overflowed no_init section") + + /DISCARD/ : + { + *(.comment) + } + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_pubtypes 0 : { *(.debug_pubtypes) } + + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* Build attributes */ + .build_attributes 0 : { *(.ARM.attributes) } +} diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/main.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/main.c new file mode 100644 index 00000000..16052b68 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/main.c @@ -0,0 +1,83 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Prog\main.c +* \brief Demo program application source file. +* \ingroup Prog_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static void Init(void); + + +/************************************************************************************//** +** \brief This is the entry point for the bootloader application and is called +** by the reset interrupt vector after the C-startup routines executed. +** \return none. +** +****************************************************************************************/ +int main(void) +{ + /* initialize the microcontroller */ + Init(); + /* initialize the bootloader interface */ + BootComInit(); + + /* start the infinite program loop */ + while (1) + { + /* toggle LED with a fixed frequency */ + LedToggle(); + /* check for bootloader activation request */ + BootComCheckActivationRequest(); + } + /* set program exit code. note that the program should never get here */ + return 0; +} /*** end of main ***/ + + +/************************************************************************************//** +** \brief Initializes the microcontroller. +** \return none. +** +****************************************************************************************/ +static void Init(void) +{ + /* ensure that SystemCoreClock variable is set */ + SystemCoreClockUpdate(); + /* init the led driver */ + LedInit(); + /* init the timer driver */ + TimerInit(); +} /*** end of Init ***/ + + +/*********************************** end of main.c *************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/prog.dox b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/prog.dox new file mode 100644 index 00000000..4f6c8714 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/prog.dox @@ -0,0 +1,7 @@ +/** +\defgroup Prog_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC User Program +\brief User Program. +\ingroup ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +*/ + + diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/timer.c b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/timer.c new file mode 100644 index 00000000..2c6df2cb --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/timer.c @@ -0,0 +1,106 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Prog\timer.c +* \brief Timer driver source file. +* \ingroup Prog_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Local variable for storing the number of milliseconds that have elapsed since + * startup. + */ +static unsigned long millisecond_counter; + + +/************************************************************************************//** +** \brief Initializes the timer. +** \return none. +** +****************************************************************************************/ +void TimerInit(void) +{ + /* configure the SysTick timer for 1 ms period */ + SysTick_Config(SystemCoreClock / 1000); + /* reset the millisecond counter */ + TimerSet(0); +} /*** end of TimerInit ***/ + + +/************************************************************************************//** +** \brief Stops and disables the timer. +** \return none. +** +****************************************************************************************/ +void TimerDeinit(void) +{ + SysTick->CTRL = 0; +} /*** end of TimerDeinit ***/ + + +/************************************************************************************//** +** \brief Sets the initial counter value of the millisecond timer. +** \param timer_value initialize value of the millisecond timer. +** \return none. +** +****************************************************************************************/ +void TimerSet(unsigned long timer_value) +{ + /* set the millisecond counter */ + millisecond_counter = timer_value; +} /*** end of TimerSet ***/ + + +/************************************************************************************//** +** \brief Obtains the counter value of the millisecond timer. +** \return Current value of the millisecond timer. +** +****************************************************************************************/ +unsigned long TimerGet(void) +{ + /* read and return the millisecond counter value */ + return millisecond_counter; +} /*** end of TimerGet ***/ + + +/************************************************************************************//** +** \brief Interrupt service routine of the timer. +** \return none. +** +****************************************************************************************/ +void SysTick_Handler(void) +{ + /* increment the millisecond counter */ + millisecond_counter++; +} /*** end of SysTick_Handler ***/ + + +/*********************************** end of timer.c ************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/timer.h b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/timer.h new file mode 100644 index 00000000..74f8fb39 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Prog/timer.h @@ -0,0 +1,40 @@ +/************************************************************************************//** +* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Prog\timer.h +* \brief Timer driver header file. +* \ingroup Prog_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef TIMER_H +#define TIMER_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void TimerInit(void); +void TimerDeinit(void); +void TimerSet(unsigned long timer_value); +unsigned long TimerGet(void); + +#endif /* TIMER_H */ +/*********************************** end of timer.h ************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/demo.dox b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/demo.dox new file mode 100644 index 00000000..ae78bb68 --- /dev/null +++ b/Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/demo.dox @@ -0,0 +1,9 @@ +/** +\defgroup ARMCM4_XMC4_XMC4700_Relax_Kit_GCC Demo for XMC4700 Relax Kit/GCC +\brief Preconfigured programs for the Infineon XMC4700 Relax Kit board and the Dave 4 + development environment, which is based on the ARM GCC toolchain. +\details Refer to http://feaser.com/openblt/doku.php?id=manual:demos + for detailed getting started instructions. +*/ + +