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Refs #816. Reintegrating branch where the S32K14 port was developed. 

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@762 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2020-03-20 09:31:39 +00:00
parent e117009d0e
commit eca185dd01
70 changed files with 37200 additions and 2 deletions
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170
Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/.cproject Normal file
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280
Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/S32K144_64_flash.ld Normal file
View File

@ -0,0 +1,280 @@
/*
** ###################################################################
** Processor: S32K144 with 64 KB SRAM
** Compiler: GNU C Compiler
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
** Copyright 2017 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
/*
To use "new" operator with EWL in C++ project the following symbol shall be defined
*/
/*EXTERN(_ZN10__cxxabiv119__terminate_handlerE)*/
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000400;
/* If symbol __flash_vector_table__=1 is defined at link time
* the interrupt vector will not be copied to RAM.
* Warning: Using the interrupt vector from Flash will not allow
* INT_SYS_InstallHandler because the section is Read Only.
*/
M_VECTOR_RAM_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : 0x0400;
/* Specify the memory areas */
MEMORY
{
/* Flash */
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x00001BF0
/* SRAM_L */
m_data (RW) : ORIGIN = 0x1FFF8000, LENGTH = 0x00008000
/* SRAM_U */
m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007000
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into internal flash */
.interrupts :
{
__VECTOR_TABLE = .;
__interrupts_start__ = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
__interrupts_end__ = .;
. = ALIGN(4);
} > m_interrupts
.flash_config :
{
. = ALIGN(4);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
. = ALIGN(4);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* Define a global symbol at end of code. */
__DATA_ROM = .; /* Symbol is used by startup for data initialization. */
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__RAM_START = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start. */
*(.m_interrupts_ram) /* This is a user defined section. */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end. */
} > m_data
__VECTOR_RAM = DEFINED(__flash_vector_table__) ? ORIGIN(m_interrupts) : __VECTOR_RAM__ ;
__RAM_VECTOR_TABLE_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : (__interrupts_ram_end__ - __interrupts_ram_start__) ;
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* Create a global symbol at data start. */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* Define a global symbol at data end. */
} > m_data
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
__CODE_ROM = __DATA_END; /* Symbol is used by code initialization. */
.code : AT(__CODE_ROM)
{
. = ALIGN(4);
__CODE_RAM = .;
__code_start__ = .; /* Create a global symbol at code start. */
__code_ram_start__ = .;
*(.code_ram) /* Custom section for storing code in RAM */
. = ALIGN(4);
__code_end__ = .; /* Define a global symbol at code end. */
__code_ram_end__ = .;
} > m_data
__CODE_END = __CODE_ROM + (__code_end__ - __code_start__);
__CUSTOM_ROM = __CODE_END;
/* Custom Section Block that can be used to place data at absolute address. */
/* Use __attribute__((section (".customSection"))) to place data here. */
.customSectionBlock ORIGIN(m_data_2) : AT(__CUSTOM_ROM)
{
__customSection_start__ = .;
KEEP(*(.customSection)) /* Keep section even if not referenced. */
__customSection_end__ = .;
} > m_data_2
__CUSTOM_END = __CUSTOM_ROM + (__customSection_end__ - __customSection_start__);
/* Uninitialized data section. */
.bss :
{
/* This is used by the startup in order to initialize the .bss section. */
. = ALIGN(4);
__BSS_START = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__BSS_END = .;
} > m_data_2
.heap :
{
. = ALIGN(8);
__end__ = .;
__heap_start__ = .;
PROVIDE(end = .);
PROVIDE(_end = .);
PROVIDE(__end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .;
__heap_end__ = .;
} > m_data_2
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
__RAM_END = __StackTop;
.stack __StackLimit :
{
. = ALIGN(8);
__stack_start__ = .;
. += STACK_SIZE;
__stack_end__ = .;
} > m_data_2
/* Labels required by EWL */
__START_BSS = __BSS_START;
__END_BSS = __BSS_END;
__SP_INIT = __StackTop;
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
}

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/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/blt_conf.h
* \brief Bootloader configuration header file.
* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BLT_CONF_H
#define BLT_CONF_H
/****************************************************************************************
* C P U D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* To properly initialize the baudrate clocks of the communication interface, typically
* the speed of the crystal oscillator and/or the speed at which the system runs is
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
* little endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
/** \brief Frequency of the external crystal oscillator. */
#define BOOT_CPU_XTAL_SPEED_KHZ (8000)
/** \brief Desired system speed. */
#define BOOT_CPU_SYSTEM_SPEED_KHZ (80000)
/** \brief Motorola or Intel style byte ordering. */
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
/** \brief Enable/disable hook function call right before user program start. */
#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)
/****************************************************************************************
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
****************************************************************************************/
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
* in bits/second. The maximum amount of data bytes in a message for data transmission
* and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
* respectively. It is common for a microcontroller to have more than 1 UART interface
* on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
*
*/
/** \brief Enable/disable UART transport layer. */
#define BOOT_COM_RS232_ENABLE (1)
/** \brief Configure the desired communication speed. */
#define BOOT_COM_RS232_BAUDRATE (57600)
/** \brief Configure number of bytes in the target->host data packet. */
#define BOOT_COM_RS232_TX_MAX_DATA (64)
/** \brief Configure number of bytes in the host->target data packet. */
#define BOOT_COM_RS232_RX_MAX_DATA (64)
/** \brief Select the desired UART peripheral as a zero based index. */
#define BOOT_COM_RS232_CHANNEL_INDEX (1)
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
* in bits/second. Two CAN messages are reserved for communication with the host. The
* message identifier for sending data from the target to the host is configured with
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
* BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by
* OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
* CAN controller channel.
*
*/
/** \brief Enable/disable CAN transport layer. */
#define BOOT_COM_CAN_ENABLE (1)
/** \brief Configure the desired CAN baudrate. */
#define BOOT_COM_CAN_BAUDRATE (500000)
/** \brief Configure CAN message ID target->host. */
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1 /*| 0x80000000*/)
/** \brief Configure number of bytes in the target->host CAN message. */
#define BOOT_COM_CAN_TX_MAX_DATA (8)
/** \brief Configure CAN message ID host->target. */
#define BOOT_COM_CAN_RX_MSG_ID (0x667 /*| 0x80000000*/)
/** \brief Configure number of bytes in the host->target CAN message. */
#define BOOT_COM_CAN_RX_MAX_DATA (8)
/** \brief Select the desired CAN peripheral as a zero based index. */
#define BOOT_COM_CAN_CHANNEL_INDEX (0)
/****************************************************************************************
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
****************************************************************************************/
/* It is possible to implement an application specific method to force the bootloader to
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
* situations where the user program does not run properly and therefore cannot
* reactivate the bootloader. By enabling these hook functions, the application can
* implement the backdoor, which overrides the default backdoor entry that is programmed
* into the bootloader. When desired for security purposes, these hook functions can
* also be implemented in a way that disables the backdoor entry altogether.
*/
/** \brief Enable/disable the backdoor override hook functions. */
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The NVM driver typically supports erase and program operations of the internal memory
* present on the microcontroller. Through these hook functions the NVM driver can be
* extended to support additional memory types such as external flash memory and serial
* eeproms. The size of the internal memory in kilobytes is specified with configurable
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
* be overridden with a application specific method by enabling configuration switch
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
*/
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
#define BOOT_NVM_HOOKS_ENABLE (0)
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
#define BOOT_NVM_SIZE_KB (512)
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
/****************************************************************************************
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The COP driver cannot be configured internally in the bootloader, because its use
* and configuration is application specific. The bootloader does need to service the
* watchdog in case it is used. When the application requires the use of a watchdog,
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
* hook functions.
*/
/** \brief Enable/disable the hook functions for controlling the watchdog. */
#define BOOT_COP_HOOKS_ENABLE (1)
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
****************************************************************************************/
/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
* rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
* operations can be performed, access to this resource need to be unlocked.
* In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
* implements the unlocking algorithm. The demo programs are configured for the (simple)
* algorithm in "libseednkey.dll". The source code for this DLL is available so it can be
* customized to your needs.
* During the unlock sequence, Microboot requests a seed from the bootloader, which is in
* the format of a byte array. Using this seed the unlock algorithm in the DLL computes
* a key, which is also a byte array, and sends this back to the bootloader. The
* bootloader then verifies this key to determine if programming and erase operations are
* permitted.
* After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
* are called by the bootloader to obtain the seed and to verify the key, respectively.
*/
#define BOOT_XCP_SEED_KEY_ENABLE (0)
#endif /* BLT_CONF_H */
/*********************************** end of blt_conf.h *********************************/

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/**
\defgroup Boot_ARMCM4_S32K14_S32K144EVB_GCC Bootloader
\brief Bootloader.
\ingroup ARMCM4_S32K14_S32K144EVB_GCC
*/

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/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/hooks.c
* \brief Bootloader callback source file.
* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "led.h" /* LED driver header */
#include "device_registers.h" /* device registers */
/****************************************************************************************
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Initializes the backdoor entry option.
** \return none.
**
****************************************************************************************/
void BackDoorInitHook(void)
{
} /*** end of BackDoorInitHook ***/
/************************************************************************************//**
** \brief Checks if a backdoor entry is requested.
** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool BackDoorEntryHook(void)
{
/* default implementation always activates the bootloader after a reset */
return BLT_TRUE;
} /*** end of BackDoorEntryHook ***/
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/************************************************************************************//**
** \brief Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* additional and optional backdoor entry through the pushbutton (SW2) on the board. to
* force the bootloader to stay active after reset, keep it pressed during reset.
*/
if ((PTC->PDIR & GPIO_PDIR_PDI(1 << 12U)) != 0U)
{
/* pushbutton pressed, so do not start the user program and keep the
* bootloader active instead.
*/
return BLT_FALSE;
}
/* clean up the LED driver */
LedBlinkExit();
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_COP_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** initialization routine. It can be used to configure and enable the
** watchdog.
** \return none.
**
****************************************************************************************/
void CopInitHook(void)
{
/* this function is called upon initialization. might as well use it to initialize
* the LED driver. It is kind of a visual watchdog anyways.
*/
LedBlinkInit(100);
} /*** end of CopInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** service routine. This gets called upon initialization and during
** potential long lasting loops and routine. It can be used to service
** the watchdog to prevent a watchdog reset.
** \return none.
**
****************************************************************************************/
void CopServiceHook(void)
{
/* run the LED blink task. this is a better place to do it than in the main() program
* loop. certain operations such as flash erase can take a long time, which would cause
* a blink interval to be skipped. this function is also called during such operations,
* so no blink intervals will be skipped when calling the LED blink task here.
*/
LedBlinkTask();
} /*** end of CopServiceHook ***/
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the start of the internal NVM driver
** initialization routine.
** \return none.
**
****************************************************************************************/
void NvmInitHook(void)
{
} /*** end of NvmInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of a firmware update to reinitialize
** the NVM driver.
** \return none.
**
****************************************************************************************/
void NvmReinitHook(void)
{
} /*** end of NvmReinitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver write
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
** been written yet.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the write
** operation failed.
**
****************************************************************************************/
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
{
return BLT_NVM_NOT_IN_RANGE;
} /*** end of NvmWriteHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver erase
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
** hasn't been erased yet.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the erase
** operation failed.
**
****************************************************************************************/
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
{
return BLT_NVM_NOT_IN_RANGE;
} /*** end of NvmEraseHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the NVM programming session.
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmDoneHook(void)
{
return BLT_TRUE;
} /*** end of NvmDoneHook ***/
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Verifies the checksum, which indicates that a valid user program is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmVerifyChecksumHook(void)
{
return BLT_TRUE;
} /*** end of NvmVerifyChecksum ***/
/************************************************************************************//**
** \brief Writes a checksum of the user program to non-volatile memory. This is
** performed once the entire user program has been programmed. Through
** the checksum, the bootloader can check if a valid user programming is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmWriteChecksumHook(void)
{
return BLT_TRUE;
}
#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
/************************************************************************************//**
** \brief Provides a seed to the XCP master that will be used for the key
** generation when the master attempts to unlock the specified resource.
** Called by the GET_SEED command.
** \param resource Resource that the seed if requested for (XCP_RES_XXX).
** \param seed Pointer to byte buffer wher the seed will be stored.
** \return Length of the seed in bytes.
**
****************************************************************************************/
blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
{
/* request seed for unlocking ProGraMming resource */
if ((resource & XCP_RES_PGM) != 0)
{
seed[0] = 0x55;
}
/* return seed length */
return 1;
} /*** end of XcpGetSeedHook ***/
/************************************************************************************//**
** \brief Called by the UNLOCK command and checks if the key to unlock the
** specified resource was correct. If so, then the resource protection
** will be removed.
** \param resource resource to unlock (XCP_RES_XXX).
** \param key pointer to the byte buffer holding the key.
** \param len length of the key in bytes.
** \return 1 if the key was correct, 0 otherwise.
**
****************************************************************************************/
blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
{
/* suppress compiler warning for unused parameter */
len = len;
/* the example key algorithm in "libseednkey.dll" works as follows:
* - PGM will be unlocked if key = seed - 1
*/
/* check key for unlocking ProGraMming resource */
if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
{
/* correct key received for unlocking PGM resource */
return 1;
}
/* still here so key incorrect */
return 0;
} /*** end of XcpVerifyKeyHook ***/
#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
/*********************************** end of hooks.c ************************************/

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/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/led.c
* \brief LED driver source file.
* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "led.h" /* module header */
#include "device_registers.h" /* device registers */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Holds the desired LED blink interval time. */
static blt_int16u ledBlinkIntervalMs;
/************************************************************************************//**
** \brief Initializes the LED blink driver.
** \param interval_ms Specifies the desired LED blink interval time in milliseconds.
** \return none.
**
****************************************************************************************/
void LedBlinkInit(blt_int16u interval_ms)
{
/* LED GPIO pin configuration. PD0 = GPIO, MUX = ALT1. */
PORTD->PCR[0] |= PORT_PCR_MUX(1);
/* configure Port D pin 0 GPIO as digital output */
PTD->PDDR |= GPIO_PDDR_PDD(0x00000001);
/* turn the LED off on Port D pin 0 */
PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001);
/* store the interval time between LED toggles */
ledBlinkIntervalMs = interval_ms;
} /*** end of LedBlinkInit ***/
/************************************************************************************//**
** \brief Task function for blinking the LED as a fixed timer interval.
** \return none.
**
****************************************************************************************/
void LedBlinkTask(void)
{
static blt_bool ledOn = BLT_FALSE;
static blt_int32u nextBlinkEvent = 0;
/* check for blink event */
if (TimerGet() >= nextBlinkEvent)
{
/* toggle the LED state */
if (ledOn == BLT_FALSE)
{
ledOn = BLT_TRUE;
/* Turn the LED on. */
PTD->PCOR |= GPIO_PCOR_PTCO(0x00000001);
}
else
{
ledOn = BLT_FALSE;
/* Turn the LED off. */
PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001);
}
/* schedule the next blink event */
nextBlinkEvent = TimerGet() + ledBlinkIntervalMs;
}
} /*** end of LedBlinkTask ***/
/************************************************************************************//**
** \brief Cleans up the LED blink driver. This is intended to be used upon program
** exit.
** \return none.
**
****************************************************************************************/
void LedBlinkExit(void)
{
/* Turn the LED off. */
PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001);
} /*** end of LedBlinkExit ***/
/*********************************** end of led.c **************************************/

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/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/led.h
* \brief LED driver header file.
* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef LED_H
#define LED_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void LedBlinkInit(blt_int16u interval_ms);
void LedBlinkTask(void);
void LedBlinkExit(void);
#endif /* LED_H */
/*********************************** end of led.h **************************************/

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef DEVASSERT_H
#define DEVASSERT_H
#include <stdbool.h>
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro is defined to be used by drivers to validate input parameters and can be disabled.
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined.
* The macros are used to validate input parameters to driver functions.
*
*/
/**
\page Error_detection_and_reporting Error detection and reporting
S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing
a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on
runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important
to use this mechanism during development.
The validation is performed by using DEV_ASSERT macro.
A default implementation of this macro is provided in this file. However, application developers can provide their own
implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the
project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h")
The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol:
- When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation
performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is
prevented (application spins in an infinite loop)
This configuration is recommended for development environments, as it prevents further execution and allows investigating
potential problems from the point of error detection.
- When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations.
This configuration can be used to eliminate the overhead of development-time checks.
It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to
disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks
in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point
to the file containing the custom implementation.
*/
#if defined (CUSTOM_DEVASSERT)
/* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */
#include CUSTOM_DEVASSERT
#elif defined (DEV_ERROR_DETECT)
/* Implement default assert macro */
static inline void DevAssert(volatile bool x)
{
if(x) { } else { BKPT_ASM; for(;;) {} }
}
#define DEV_ASSERT(x) DevAssert(x)
#else
/* Assert macro does nothing */
#define DEV_ASSERT(x) ((void)0)
#endif
#endif /* DEVASSERT_H */
/*******************************************************************************
* EOF
******************************************************************************/

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/*
** ###################################################################
** Abstract:
** Common include file for CMSIS register access layer headers.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
** ###################################################################
*/
#ifndef DEVICE_REGISTERS_H
#define DEVICE_REGISTERS_H
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro defines the device currently in use and may be used by components for specific checks.
*
*/
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if (defined(CPU_S32K144HFT0VLLT) || defined(CPU_S32K144LFT0MLLT))
#define S32K14x_SERIES
/* Specific core definitions */
#include "s32_core_cm4.h"
#define S32K144_SERIES
/* Register definitions */
#include "S32K144.h"
/* CPU specific feature definitions */
#include "S32K144_features.h"
#else
#error "No valid CPU defined!"
#endif
#include "devassert.h"
#endif /* DEVICE_REGISTERS_H */
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*!
* @file s32_core_cm4.h
*
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
* Function-like macros are used instead of inline functions in order to ensure
* that the performance will not be decreased if the functions will not be
* inlined by the compiler.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced.
* The macros defined are used only on some of the drivers, so this might be reported
* when the analysis is made only on one driver.
*/
/*
* Tool Chains:
* GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version
* __GNUC__ : GNU Compiler Collection
* __ghs__ : Green Hills ARM Compiler
* __ICCARM__ : IAR ARM Compiler
* __DCC__ : Wind River Diab Compiler
* __ARMCC_VERSION: ARM Compiler
*/
#if !defined (CORE_CM4_H)
#define CORE_CM4_H
#ifdef __cplusplus
extern "C" {
#endif
/** \brief BKPT_ASM
*
* Macro to be used to trigger an debug interrupt
*/
#define BKPT_ASM __asm("BKPT #0\n\t")
/** \brief Enable FPU
*
* ENABLE_FPU indicates whether SystemInit will enable the Floating point unit (FPU)
*/
#if defined (__GNUC__) || defined (__ARMCC_VERSION)
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
#define ENABLE_FPU
#endif
#elif defined (__ICCARM__)
#if defined __ARMVFP__
#define ENABLE_FPU
#endif
#elif defined (__ghs__) || defined (__DCC__)
#if defined (__VFP__)
#define ENABLE_FPU
#endif
#endif /* if defined (__GNUC__) */
/** \brief Enable interrupts
*/
#if defined (__GNUC__)
#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory");
#else
#define ENABLE_INTERRUPTS() __asm("cpsie i")
#endif
/** \brief Disable interrupts
*/
#if defined (__GNUC__)
#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory");
#else
#define DISABLE_INTERRUPTS() __asm("cpsid i")
#endif
/** \brief Enter low-power standby state
* WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts.
*/
#if defined (__GNUC__)
#define STANDBY() __asm volatile ("wfi")
#else
#define STANDBY() __asm("wfi")
#endif
/** \brief No-op
*/
#define NOP() __asm volatile ("nop")
/** \brief Reverse byte order in a word.
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION)
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \
| ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U))
#endif
/** \brief Reverse byte order in each halfword independently.
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION)
#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \
| ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U))
#endif
/** \brief Places a function in RAM.
*/
#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION)
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));
#elif defined ( __ghs__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far")
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\
_Pragma("ghs callmode=default")
#elif defined ( __ICCARM__ )
#define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#elif defined ( __DCC__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\"") \
_Pragma("use_section CODE")
#define END_FUNCTION_DECLARATION_RAMSECTION ; \
_Pragma("section CODE \".text\"")
#else
/* Keep compatibility with software analysis tools */
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#endif
/* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when
defining a function, it is enough to specify it at the declaration. This
also enables compatibility with software analysis tools. */
#define START_FUNCTION_DEFINITION_RAMSECTION
#define END_FUNCTION_DEFINITION_RAMSECTION
#if defined (__ICCARM__)
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022")
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022")
#else
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL
#endif
/** \brief Get Core ID
*
* GET_CORE_ID returns the processor identification number for cm4
*/
#define GET_CORE_ID() 0U
/** \brief Data alignment.
*/
#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION)
#define ALIGNED(x) __attribute__((aligned(x)))
#elif defined ( __ICCARM__ )
#define stringify(s) tostring(s)
#define tostring(s) #s
#define ALIGNED(x) _Pragma(stringify(data_alignment=x))
#else
/* Keep compatibility with software analysis tools */
#define ALIGNED(x)
#endif
/** \brief Section placement.
*/
#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION)
#define PLACE_IN_SECTION(x) __attribute__((section(x)))
#elif defined ( __ICCARM__ )
#define PLACE_IN_SECTION(x) _Pragma(stringify(section=x))
#else
/* Keep compatibility with software analysis tools */
#define PLACE_IN_SECTION(x)
#endif
/** \brief Endianness.
*/
#define CORE_LITTLE_ENDIAN
#ifdef __cplusplus
}
#endif
#endif /* CORE_CM4_H */
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2015 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* An object with static storage duration declared at block scope cannot be
* accessed directly from outside the block.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
* between a pointer to object and an integer type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
* between pointer to void and an arithmetic type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
* Function is defined for usage by application code.
*
*/
#include "device_registers.h"
#include "system_S32K144.h"
#include "stdbool.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/*FUNCTION**********************************************************************
*
* Function Name : SystemInit
* Description : This function disables the watchdog, enables FPU
* and the power mode protection if the corresponding feature macro
* is enabled. SystemInit is called from startup_device file.
*
* Implements : SystemInit_Activity
*END**************************************************************************/
void SystemInit(void)
{
/**************************************************************************/
/* FPU ENABLE*/
/**************************************************************************/
#ifdef ENABLE_FPU
/* Enable CP10 and CP11 coprocessors */
S32_SCB->CPACR |= (S32_SCB_CPACR_CP10_MASK | S32_SCB_CPACR_CP11_MASK);
#ifdef ERRATA_E6940
/* Disable lazy context save of floating point state by clearing LSPEN bit
* Workaround for errata e6940 */
S32_SCB->FPCCR &= ~(S32_SCB_FPCCR_LSPEN_MASK);
#endif
#endif /* ENABLE_FPU */
/**************************************************************************/
/* WDOG DISABLE*/
/**************************************************************************/
#if (DISABLE_WDOG)
/* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/
WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE;
/* The dummy read is used in order to make sure that the WDOG registers will be configured only
* after the write of the unlock value was completed. */
(void)WDOG->CNT;
/* Initial write of WDOG configuration register:
* enables support for 32-bit refresh/unlock command write words,
* clock select from LPO, update enable, watchdog disabled */
WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) |
(FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) |
(0U << WDOG_CS_EN_SHIFT) |
(1U << WDOG_CS_UPDATE_SHIFT) );
/* Configure timeout */
WDOG->TOVAL = (uint32_t )0xFFFF;
#endif /* (DISABLE_WDOG) */
/**************************************************************************/
/* ENABLE CACHE */
/**************************************************************************/
#if defined(I_CACHE) && (ICACHE_ENABLE == 1)
/* Invalidate and enable code cache */
LMEM->PCCCR = LMEM_PCCCR_INVW0(1) | LMEM_PCCCR_INVW1(1) | LMEM_PCCCR_GO(1) | LMEM_PCCCR_ENCACHE(1);
#endif /* defined(I_CACHE) && (ICACHE_ENABLE == 1) */
}
/*FUNCTION**********************************************************************
*
* Function Name : SystemCoreClockUpdate
* Description : This function must be called whenever the core clock is changed
* during program execution. It evaluates the clock register settings and calculates
* the current core clock.
*
* Implements : SystemCoreClockUpdate_Activity
*END**************************************************************************/
void SystemCoreClockUpdate(void)
{
uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */
uint32_t regValue; /* Temporary variable */
uint32_t divider, prediv, multi;
bool validSystemClockSource = true;
static const uint32_t fircFreq[] = {
FEATURE_SCG_FIRC_FREQ0,
};
divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U;
switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
case 0x1:
/* System OSC */
SCGOUTClock = CPU_XTAL_CLK_HZ;
break;
case 0x2:
/* Slow IRC */
regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT;
if (regValue != 0U)
{
SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ;
}
break;
case 0x3:
/* Fast IRC */
regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT;
SCGOUTClock= fircFreq[regValue];
break;
case 0x6:
/* System PLL */
SCGOUTClock = CPU_XTAL_CLK_HZ;
prediv = ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U;
multi = ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U;
SCGOUTClock = SCGOUTClock * multi / (prediv * 2U);
break;
default:
validSystemClockSource = false;
break;
}
if (validSystemClockSource == true) {
SystemCoreClock = (SCGOUTClock / divider);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : SystemSoftwareReset
* Description : This function is used to initiate a system reset
*
* Implements : SystemSoftwareReset_Activity
*END**************************************************************************/
void SystemSoftwareReset(void)
{
uint32_t regValue;
/* Read Application Interrupt and Reset Control Register */
regValue = S32_SCB->AIRCR;
/* Clear register key */
regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK);
/* Configure System reset request bit and Register Key */
regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY);
regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u);
/* Write computed register value */
S32_SCB->AIRCR = regValue;
}
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2015 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*! @addtogroup soc_support_S32K144*/
/*! @{*/
/*!
* @file system_S32K144.h
* @brief Device specific configuration file for S32K144
*/
#ifndef SYSTEM_S32K144_H_
#define SYSTEM_S32K144_H_ /**< Symbol preventing repeated inclusion */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************
* CPU Settings.
*****************************************************************************/
/* Watchdog disable */
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* Cache enablement */
#ifndef ICACHE_ENABLE
#define ICACHE_ENABLE 0
#endif
/* Value of the external crystal or oscillator clock frequency in Hz */
#ifndef CPU_XTAL_CLK_HZ
#define CPU_XTAL_CLK_HZ 8000000u
#endif
/* Value of the fast internal oscillator clock frequency in Hz */
#ifndef CPU_INT_FAST_CLK_HZ
#define CPU_INT_FAST_CLK_HZ 48000000u
#endif
/* Default System clock value */
#ifndef DEFAULT_SYSTEM_CLOCK
#define DEFAULT_SYSTEM_CLOCK 48000000u
#endif
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the SoC.
*
* This function disables the watchdog, enables FPU.
* if the corresponding feature macro is enabled.
* SystemInit is called from startup_device file.
*/
void SystemInit(void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
* This function must be called when user does not want to use clock manager component.
* If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK
* parameter.
*
*/
void SystemCoreClockUpdate(void);
/**
* @brief Initiates a system reset.
*
* This function is used to initiate a system reset
*/
void SystemSoftwareReset(void);
#ifdef __cplusplus
}
#endif
/*! @}*/
#endif /* #if !defined(SYSTEM_S32K144_H_) */

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/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/main.c
* \brief Bootloader application source file.
* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "device_registers.h" /* device registers */
#include "system_S32K144.h" /* device sconfiguration */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static void Init(void);
static void SystemClockConfig(void);
/************************************************************************************//**
** \brief This is the entry point for the bootloader application and is called
** by the reset interrupt vector after the C-startup routines executed.
** \return Program return code.
**
****************************************************************************************/
int main(void)
{
/* Initialize the microcontroller. */
Init();
/* Initialize the bootloader. */
BootInit();
/* Start the infinite program loop. */
while (1)
{
/* Run the bootloader task. */
BootTask();
}
/* Program should never get here. */
return 0;
} /*** end of main ***/
/************************************************************************************//**
** \brief Initializes the microcontroller.
** \return none.
**
****************************************************************************************/
static void Init(void)
{
/* Configure the system clock. */
SystemClockConfig();
/* Enable the peripheral clock for the ports that are used. */
PCC->PCCn[PCC_PORTC_INDEX] |= PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK;
/* Configure SW2 (PC12) GPIO pin for (optional) backdoor entry input. */
/* Input GPIO pin configuration. PC12 = GPIO, MUX = ALT1. */
PORTC->PCR[12] |= PORT_PCR_MUX(1);
/* Disable pull device, as SW2 already has a pull down resistor on the board. */
PORTC->PCR[12] &= ~PORT_PCR_PE(1);
/* Configure and enable Port C pin 12 GPIO as digital input */
PTC->PDDR &= ~GPIO_PDDR_PDD(1 << 12U);
PTC->PIDR &= ~GPIO_PIDR_PID(1 << 12U);
#if (BOOT_COM_RS232_ENABLE > 0)
/* UART RX GPIO pin configuration. PC6 = UART1 RX, MUX = ALT2. */
PORTC->PCR[6] |= PORT_PCR_MUX(2);
/* UART TX GPIO pin configuration. PC7 = UART1 TX, MUX = ALT2. */
PORTC->PCR[7] |= PORT_PCR_MUX(2);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
/* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */
PORTE->PCR[4] |= PORT_PCR_MUX(5);
/* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */
PORTE->PCR[5] |= PORT_PCR_MUX(5);
#endif
} /*** end of Init ***/
/************************************************************************************//**
** \brief System Clock Configuration. This code was derived from a S32 Design Studio
** example program. It uses the 8 MHz external crystal as a source for the
** PLL and configures the normal RUN mode for the following clock settings:
** - SPLL_CLK = 160 MHz
** - CORE_CLK = 80 MHz
** - SYS_CLK = 80 MHz
** - BUS_CLK = 40 MHz
** - FLASH_CLK = 26.67 MHz
** - SIRCDIV1_CLK = 8 MHz
** - SIRCDIV2_CLK = 8 MHz
** \return none.
**
****************************************************************************************/
static void SystemClockConfig(void)
{
/* --------- SOSC Initialization (8 MHz) ------------------------------------------- */
/* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1);
/* Range=2: Medium freq (SOSC betw 1MHz-8MHz).
* HGO=0: Config xtal osc for low power.
* EREFS=1: Input is external XTAL.
*/
SCG->SOSCCFG = SCG_SOSCCFG_RANGE(2) | SCG_SOSCCFG_EREFS_MASK;
/* Ensure SOSCCSR unlocked. */
while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK)
{
;
}
/* LK=0: SOSCCSR can be written.
* SOSCCMRE=0: OSC CLK monitor IRQ if enabled.
* SOSCCM=0: OSC CLK monitor disabled.
* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled.
* SOSCLPEN=0: Sys OSC disabled in VLP modes.
* SOSCSTEN=0: Sys OSC disabled in Stop modes.
* SOSCEN=1: Enable oscillator.
*/
SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK;
/* Wait for system OSC clock to become valid. */
while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
{
;
}
/* --------- SPLL Initialization (160 MHz) ----------------------------------------- */
/* Ensure SPLLCSR is unlocked. */
while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK)
{
;
}
/* SPLLEN=0: SPLL is disabled (default). */
SCG->SPLLCSR &= ~SCG_SPLLCSR_SPLLEN_MASK;
/* SPLLDIV1 divide by 2 and SPLLDIV2 divide by 4. */
SCG->SPLLDIV |= SCG_SPLLDIV_SPLLDIV1(2) | SCG_SPLLDIV_SPLLDIV2(3);
/* PREDIV=0: Divide SOSC_CLK by 0+1=1.
* MULT=24: Multiply sys pll by 4+24=40.
* SPLL_CLK = 8MHz / 1 * 40 / 2 = 160 MHz.
*/
SCG->SPLLCFG = SCG_SPLLCFG_MULT(24);
/* Ensure SPLLCSR is unlocked. */
while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK)
{
;
}
/* LK=0: SPLLCSR can be written.
* SPLLCMRE=0: SPLL CLK monitor IRQ if enabled.
* SPLLCM=0: SPLL CLK monitor disabled.
* SPLLSTEN=0: SPLL disabled in Stop modes.
* SPLLEN=1: Enable SPLL.
*/
SCG->SPLLCSR |= SCG_SPLLCSR_SPLLEN_MASK;
/* Wait for SPLL to become valid. */
while (!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK))
{
;
}
/* --------- SIRC Initialization --------------------------------------------------- */
/* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and
* SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source.
*/
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1);
/* --------- Change to normal RUN mode with 8MHz SOSC, 80 MHz PLL ------------------ */
/* Note that flash memory should not be programmed or erased when the microcontroller
* is operating in VLPr or HSRUN mode. Therefore normal RUN mode is configured.
*/
/* Select PLL as clock source.
* DIVCORE=1, div. by 2: Core clock = 160/2 MHz = 80 MHz.
* DIVBUS=1, div. by 2: bus clock = 40 MHz.
* DIVSLOW=2, div. by 2: SCG slow, flash clock= 26 2/3 MHz.
*/
SCG->RCCR= SCG_RCCR_SCS(6) | SCG_RCCR_DIVCORE(0b01) | SCG_RCCR_DIVBUS(0b01) |
SCG_RCCR_DIVSLOW(0b10);
/* Wait until system clock source is SPLL. */
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6U)
{
;
}
/* Evaluate the clock register settings and calculates the current core clock. This
* function must be called when the clock manager component is not used.
*/
SystemCoreClockUpdate();
} /*** end of SystemClockConfig ***/
/*********************************** end of main.c *************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* All variables with this problem are defined in the linker files.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage
* is declared, its size should be explicitly specified.
* The size of the arrays can not be explicitly determined.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
* between a pointer to object and an integer type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
* between pointer to void and an arithmetic type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable
* code.
* The condition compares two address defined in linker files that can be different.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
* Function is defined for usage by application code.
*
* @section [global]
* Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed
* to return int.
* This is an e200 Power Architecture Assembly instruction used to retrieve
* the core number.
*
*/
#include "startup.h"
#include <stdint.h>
/*******************************************************************************
* Static Variables
******************************************************************************/
static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS;
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : init_data_bss
* Description : Make necessary initializations for RAM.
* - Copy the vector table from ROM to RAM.
* - Copy initialized data from ROM to RAM.
* - Copy code that should reside in RAM from ROM
* - Clear the zero-initialized data section.
*
* Tool Chains:
* __GNUC__ : GNU Compiler Collection
* __ghs__ : Green Hills ARM Compiler
* __ICCARM__ : IAR ARM Compiler
* __DCC__ : Wind River Diab Compiler
* __ARMCC_VERSION : ARMC Compiler
*
* Implements : init_data_bss_Activity
*END**************************************************************************/
void init_data_bss(void)
{
uint32_t n;
uint8_t coreId;
/* For ARMC we are using the library method of initializing DATA, Custom Section and
* Code RAM sections so the below variables are not needed */
#if !defined(__ARMCC_VERSION)
/* Declare pointers for various data sections. These pointers
* are initialized using values pulled in from the linker file */
uint8_t * data_ram;
uint8_t * code_ram;
uint8_t * bss_start;
uint8_t * custom_ram;
const uint8_t * data_rom, * data_rom_end;
const uint8_t * code_rom, * code_rom_end;
const uint8_t * bss_end;
const uint8_t * custom_rom, * custom_rom_end;
#endif
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__ARMCC_VERSION)
extern uint32_t __RAM_VECTOR_TABLE_SIZE;
extern uint32_t __VECTOR_ROM;
extern uint32_t __VECTOR_RAM;
#else
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#endif
/* Get section information from linker files */
#if defined(__ICCARM__)
/* Data */
data_ram = __section_begin(".data");
data_rom = __section_begin(".data_init");
data_rom_end = __section_end(".data_init");
/* CODE RAM */
#pragma section = "__CODE_ROM"
#pragma section = "__CODE_RAM"
code_ram = __section_begin("__CODE_RAM");
code_rom = __section_begin("__CODE_ROM");
code_rom_end = __section_end("__CODE_ROM");
/* BSS */
bss_start = __section_begin(".bss");
bss_end = __section_end(".bss");
custom_ram = __section_begin(".customSection");
custom_rom = __section_begin(".customSection_init");
custom_rom_end = __section_end(".customSection_init");
#elif defined (__ARMCC_VERSION)
/* VECTOR TABLE*/
uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE;
uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM;
uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM;
#else
extern uint32_t __DATA_ROM[];
extern uint32_t __DATA_RAM[];
extern uint32_t __DATA_END[];
extern uint32_t __CODE_RAM[];
extern uint32_t __CODE_ROM[];
extern uint32_t __CODE_END[];
extern uint32_t __BSS_START[];
extern uint32_t __BSS_END[];
extern uint32_t __CUSTOM_ROM[];
extern uint32_t __CUSTOM_END[];
/* Data */
data_ram = (uint8_t *)__DATA_RAM;
data_rom = (uint8_t *)__DATA_ROM;
data_rom_end = (uint8_t *)__DATA_END;
/* CODE RAM */
code_ram = (uint8_t *)__CODE_RAM;
code_rom = (uint8_t *)__CODE_ROM;
code_rom_end = (uint8_t *)__CODE_END;
/* BSS */
bss_start = (uint8_t *)__BSS_START;
bss_end = (uint8_t *)__BSS_END;
/* Custom section */
custom_ram = CUSTOMSECTION_SECTION_START;
custom_rom = (uint8_t *)__CUSTOM_ROM;
custom_rom_end = (uint8_t *)__CUSTOM_END;
#endif
#if !defined(__ARMCC_VERSION)
/* Copy initialized data from ROM to RAM */
while (data_rom_end != data_rom)
{
*data_ram = *data_rom;
data_ram++;
data_rom++;
}
/* Copy functions from ROM to RAM */
while (code_rom_end != code_rom)
{
*code_ram = *code_rom;
code_ram++;
code_rom++;
}
/* Clear the zero-initialized data section */
while(bss_end != bss_start)
{
*bss_start = 0;
bss_start++;
}
/* Copy customsection rom to ram */
while(custom_rom_end != custom_rom)
{
*custom_ram = *custom_rom;
custom_rom++;
custom_ram++;
}
#endif
coreId = (uint8_t)GET_CORE_ID();
#if defined (__ARMCC_VERSION)
/* Copy the vector table from ROM to RAM */
/* Workaround */
for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++)
{
vector_ram[n] = vector_rom[n];
}
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t) __VECTOR_RAM;
#else
/* Check if VECTOR_TABLE copy is needed */
if (__VECTOR_RAM != __VECTOR_TABLE)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t)__VECTOR_RAM;
}
else
{
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t)__VECTOR_TABLE;
}
#endif
}
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef STARTUP_H
#define STARTUP_H
#include <stdint.h>
#include "device_registers.h"
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced.
* The defined macro is used as include guard.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* All variables with this problem are defined in the linker files.
*
*/
/*******************************************************************************
* API
******************************************************************************/
/*!
* @brief define symbols that specific start and end addres of some basic sections.
*/
#if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) || defined (S32K144W_M4_SERIES)
#if (defined(__ICCARM__))
#define INTERRUPTS_SECTION_START __section_begin(".intvec")
#define INTERRUPTS_SECTION_END __section_end(".intvec")
#define BSS_SECTION_START __section_begin(".bss")
#define BSS_SECTION_END __section_end(".bss")
#define DATA_SECTION_START __section_begin(".data")
#define DATA_SECTION_END __section_end(".data")
#define CUSTOMSECTION_SECTION_START __section_begin(".customSection")
#define CUSTOMSECTION_SECTION_END __section_end(".customSection")
#define CODE_RAM_SECTION_START __section_begin("__CODE_RAM")
#define CODE_RAM_SECTION_END __section_end("__CODE_RAM")
#define DATA_INIT_SECTION_START __section_begin(".data_init")
#define DATA_INIT_SECTION_END __section_end(".data_init")
#define CODE_ROM_SECTION_START __section_begin("__CODE_ROM")
#define CODE_ROM_SECTION_END __section_end("__CODE_ROM")
#elif (defined(__ARMCC_VERSION))
#define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START
#define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END
#define BSS_SECTION_START (uint8_t *)__BSS_START
#define BSS_SECTION_END (uint8_t *)__BSS_END
#define DATA_SECTION_START (uint8_t *)__DATA_RAM_START
#define DATA_SECTION_END (uint8_t *)__DATA_RAM_END
#define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START
#define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END
#define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START
#define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END
extern uint32_t __VECTOR_ROM_START;
extern uint32_t __VECTOR_ROM_END;
extern uint32_t __BSS_START;
extern uint32_t __BSS_END;
extern uint32_t __DATA_RAM_START;
extern uint32_t __DATA_RAM_END;
extern uint32_t __CUSTOM_SECTION_START;
extern uint32_t __CUSTOM_SECTION_END;
extern uint32_t __CODE_RAM_START;
extern uint32_t __CODE_RAM_END;
#else
#define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__
#define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__
#define BSS_SECTION_START (uint8_t *)&__bss_start__
#define BSS_SECTION_END (uint8_t *)&__bss_end__
#define DATA_SECTION_START (uint8_t *)&__data_start__
#define DATA_SECTION_END (uint8_t *)&__data_end__
#define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__
#define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__
#define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__
#define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__
extern uint32_t __interrupts_start__;
extern uint32_t __interrupts_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __customSection_start__;
extern uint32_t __customSection_end__;
extern uint32_t __code_ram_start__;
extern uint32_t __code_ram_end__;
#endif
#endif
#if (defined(__ICCARM__))
#pragma section = ".data"
#pragma section = ".data_init"
#pragma section = ".bss"
#pragma section = ".intvec"
#pragma section = ".customSection"
#pragma section = ".customSection_init"
#pragma section = "__CODE_RAM"
#pragma section = "__CODE_ROM"
#endif
/*!
* @brief Make necessary initializations for RAM.
*
* - Copy initialized data from ROM to RAM.
* - Clear the zero-initialized data section.
* - Copy the vector table from ROM to RAM. This could be an option.
*/
void init_data_bss(void);
#endif /* STARTUP_H*/
/*******************************************************************************
* EOF
******************************************************************************/

531
Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/startup/startup_S32K144.S Normal file
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@ -0,0 +1,531 @@
/* ---------------------------------------------------------------------------------------*/
/* @file: startup_S32K144.s */
/* @purpose: GNU Compiler Collection Startup File */
/* S32K144 */
/* @version: 2.0 */
/* @date: 2017-1-10 */
/* @build: b170107 */
/* ---------------------------------------------------------------------------------------*/
/* */
/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. */
/* Copyright 2016-2017 NXP */
/* All rights reserved. */
/* */
/* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES */
/* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. */
/* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, */
/* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR */
/* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) */
/* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, */
/* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING */
/* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF */
/* THE POSSIBILITY OF SUCH DAMAGE. */
/*****************************************************************************/
/* Version: GNU Compiler Collection */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_IRQHandler /* DMA channel 0 transfer complete*/
.long DMA1_IRQHandler /* DMA channel 1 transfer complete*/
.long DMA2_IRQHandler /* DMA channel 2 transfer complete*/
.long DMA3_IRQHandler /* DMA channel 3 transfer complete*/
.long DMA4_IRQHandler /* DMA channel 4 transfer complete*/
.long DMA5_IRQHandler /* DMA channel 5 transfer complete*/
.long DMA6_IRQHandler /* DMA channel 6 transfer complete*/
.long DMA7_IRQHandler /* DMA channel 7 transfer complete*/
.long DMA8_IRQHandler /* DMA channel 8 transfer complete*/
.long DMA9_IRQHandler /* DMA channel 9 transfer complete*/
.long DMA10_IRQHandler /* DMA channel 10 transfer complete*/
.long DMA11_IRQHandler /* DMA channel 11 transfer complete*/
.long DMA12_IRQHandler /* DMA channel 12 transfer complete*/
.long DMA13_IRQHandler /* DMA channel 13 transfer complete*/
.long DMA14_IRQHandler /* DMA channel 14 transfer complete*/
.long DMA15_IRQHandler /* DMA channel 15 transfer complete*/
.long DMA_Error_IRQHandler /* DMA error interrupt channels 0-15*/
.long MCM_IRQHandler /* FPU sources*/
.long FTFC_IRQHandler /* FTFC Command complete*/
.long Read_Collision_IRQHandler /* FTFC Read collision*/
.long LVD_LVW_IRQHandler /* PMC Low voltage detect interrupt*/
.long FTFC_Fault_IRQHandler /* FTFC Double bit fault detect*/
.long WDOG_EWM_IRQHandler /* Single interrupt vector for WDOG and EWM*/
.long RCM_IRQHandler /* RCM Asynchronous Interrupt*/
.long LPI2C0_Master_IRQHandler /* LPI2C0 Master Interrupt*/
.long LPI2C0_Slave_IRQHandler /* LPI2C0 Slave Interrupt*/
.long LPSPI0_IRQHandler /* LPSPI0 Interrupt*/
.long LPSPI1_IRQHandler /* LPSPI1 Interrupt*/
.long LPSPI2_IRQHandler /* LPSPI2 Interrupt*/
.long Reserved45_IRQHandler /* Reserved Interrupt 45*/
.long Reserved46_IRQHandler /* Reserved Interrupt 46*/
.long LPUART0_RxTx_IRQHandler /* LPUART0 Transmit / Receive Interrupt*/
.long Reserved48_IRQHandler /* Reserved Interrupt 48*/
.long LPUART1_RxTx_IRQHandler /* LPUART1 Transmit / Receive Interrupt*/
.long Reserved50_IRQHandler /* Reserved Interrupt 50*/
.long LPUART2_RxTx_IRQHandler /* LPUART2 Transmit / Receive Interrupt*/
.long Reserved52_IRQHandler /* Reserved Interrupt 52*/
.long Reserved53_IRQHandler /* Reserved Interrupt 53*/
.long Reserved54_IRQHandler /* Reserved Interrupt 54*/
.long ADC0_IRQHandler /* ADC0 interrupt request.*/
.long ADC1_IRQHandler /* ADC1 interrupt request.*/
.long CMP0_IRQHandler /* CMP0 interrupt request*/
.long Reserved58_IRQHandler /* Reserved Interrupt 58*/
.long Reserved59_IRQHandler /* Reserved Interrupt 59*/
.long ERM_single_fault_IRQHandler /* ERM single bit error correction*/
.long ERM_double_fault_IRQHandler /* ERM double bit error non-correctable*/
.long RTC_IRQHandler /* RTC alarm interrupt*/
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
.long LPIT0_Ch0_IRQHandler /* LPIT0 channel 0 overflow interrupt*/
.long LPIT0_Ch1_IRQHandler /* LPIT0 channel 1 overflow interrupt*/
.long LPIT0_Ch2_IRQHandler /* LPIT0 channel 2 overflow interrupt*/
.long LPIT0_Ch3_IRQHandler /* LPIT0 channel 3 overflow interrupt*/
.long PDB0_IRQHandler /* PDB0 interrupt*/
.long Reserved69_IRQHandler /* Reserved Interrupt 69*/
.long Reserved70_IRQHandler /* Reserved Interrupt 70*/
.long Reserved71_IRQHandler /* Reserved Interrupt 71*/
.long Reserved72_IRQHandler /* Reserved Interrupt 72*/
.long SCG_IRQHandler /* SCG bus interrupt request*/
.long LPTMR0_IRQHandler /* LPTIMER interrupt request*/
.long PORTA_IRQHandler /* Port A pin detect interrupt*/
.long PORTB_IRQHandler /* Port B pin detect interrupt*/
.long PORTC_IRQHandler /* Port C pin detect interrupt*/
.long PORTD_IRQHandler /* Port D pin detect interrupt*/
.long PORTE_IRQHandler /* Port E pin detect interrupt*/
.long SWI_IRQHandler /* Software interrupt*/
.long Reserved81_IRQHandler /* Reserved Interrupt 81*/
.long Reserved82_IRQHandler /* Reserved Interrupt 82*/
.long Reserved83_IRQHandler /* Reserved Interrupt 83*/
.long PDB1_IRQHandler /* PDB1 interrupt*/
.long FLEXIO_IRQHandler /* FlexIO Interrupt*/
.long Reserved86_IRQHandler /* Reserved Interrupt 86*/
.long Reserved87_IRQHandler /* Reserved Interrupt 87*/
.long Reserved88_IRQHandler /* Reserved Interrupt 88*/
.long Reserved89_IRQHandler /* Reserved Interrupt 89*/
.long Reserved90_IRQHandler /* Reserved Interrupt 90*/
.long Reserved91_IRQHandler /* Reserved Interrupt 91*/
.long Reserved92_IRQHandler /* Reserved Interrupt 92*/
.long Reserved93_IRQHandler /* Reserved Interrupt 93*/
.long CAN0_ORed_IRQHandler /* CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
.long CAN0_Error_IRQHandler /* CAN0 Interrupt indicating that errors were detected on the CAN bus*/
.long CAN0_Wake_Up_IRQHandler /* CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode*/
.long CAN0_ORed_0_15_MB_IRQHandler /* CAN0 OR'ed Message buffer (0-15)*/
.long CAN0_ORed_16_31_MB_IRQHandler /* CAN0 OR'ed Message buffer (16-31)*/
.long Reserved99_IRQHandler /* Reserved Interrupt 99*/
.long Reserved100_IRQHandler /* Reserved Interrupt 100*/
.long CAN1_ORed_IRQHandler /* CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
.long CAN1_Error_IRQHandler /* CAN1 Interrupt indicating that errors were detected on the CAN bus*/
.long Reserved103_IRQHandler /* Reserved Interrupt 103*/
.long CAN1_ORed_0_15_MB_IRQHandler /* CAN1 OR'ed Interrupt for Message buffer (0-15)*/
.long Reserved105_IRQHandler /* Reserved Interrupt 105*/
.long Reserved106_IRQHandler /* Reserved Interrupt 106*/
.long Reserved107_IRQHandler /* Reserved Interrupt 107*/
.long CAN2_ORed_IRQHandler /* CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
.long CAN2_Error_IRQHandler /* CAN2 Interrupt indicating that errors were detected on the CAN bus*/
.long Reserved110_IRQHandler /* Reserved Interrupt 110*/
.long CAN2_ORed_0_15_MB_IRQHandler /* CAN2 OR'ed Message buffer (0-15)*/
.long Reserved112_IRQHandler /* Reserved Interrupt 112*/
.long Reserved113_IRQHandler /* Reserved Interrupt 113*/
.long Reserved114_IRQHandler /* Reserved Interrupt 114*/
.long FTM0_Ch0_Ch1_IRQHandler /* FTM0 Channel 0 and 1 interrupt*/
.long FTM0_Ch2_Ch3_IRQHandler /* FTM0 Channel 2 and 3 interrupt*/
.long FTM0_Ch4_Ch5_IRQHandler /* FTM0 Channel 4 and 5 interrupt*/
.long FTM0_Ch6_Ch7_IRQHandler /* FTM0 Channel 6 and 7 interrupt*/
.long FTM0_Fault_IRQHandler /* FTM0 Fault interrupt*/
.long FTM0_Ovf_Reload_IRQHandler /* FTM0 Counter overflow and Reload interrupt*/
.long FTM1_Ch0_Ch1_IRQHandler /* FTM1 Channel 0 and 1 interrupt*/
.long FTM1_Ch2_Ch3_IRQHandler /* FTM1 Channel 2 and 3 interrupt*/
.long FTM1_Ch4_Ch5_IRQHandler /* FTM1 Channel 4 and 5 interrupt*/
.long FTM1_Ch6_Ch7_IRQHandler /* FTM1 Channel 6 and 7 interrupt*/
.long FTM1_Fault_IRQHandler /* FTM1 Fault interrupt*/
.long FTM1_Ovf_Reload_IRQHandler /* FTM1 Counter overflow and Reload interrupt*/
.long FTM2_Ch0_Ch1_IRQHandler /* FTM2 Channel 0 and 1 interrupt*/
.long FTM2_Ch2_Ch3_IRQHandler /* FTM2 Channel 2 and 3 interrupt*/
.long FTM2_Ch4_Ch5_IRQHandler /* FTM2 Channel 4 and 5 interrupt*/
.long FTM2_Ch6_Ch7_IRQHandler /* FTM2 Channel 6 and 7 interrupt*/
.long FTM2_Fault_IRQHandler /* FTM2 Fault interrupt*/
.long FTM2_Ovf_Reload_IRQHandler /* FTM2 Counter overflow and Reload interrupt*/
.long FTM3_Ch0_Ch1_IRQHandler /* FTM3 Channel 0 and 1 interrupt*/
.long FTM3_Ch2_Ch3_IRQHandler /* FTM3 Channel 2 and 3 interrupt*/
.long FTM3_Ch4_Ch5_IRQHandler /* FTM3 Channel 4 and 5 interrupt*/
.long FTM3_Ch6_Ch7_IRQHandler /* FTM3 Channel 6 and 7 interrupt*/
.long FTM3_Fault_IRQHandler /* FTM3 Fault interrupt*/
.long FTM3_Ovf_Reload_IRQHandler /* FTM3 Counter overflow and Reload interrupt*/
.long DefaultISR /* 139*/
.long DefaultISR /* 140*/
.long DefaultISR /* 141*/
.long DefaultISR /* 142*/
.long DefaultISR /* 143*/
.long DefaultISR /* 144*/
.long DefaultISR /* 145*/
.long DefaultISR /* 146*/
.long DefaultISR /* 147*/
.long DefaultISR /* 148*/
.long DefaultISR /* 149*/
.long DefaultISR /* 150*/
.long DefaultISR /* 151*/
.long DefaultISR /* 152*/
.long DefaultISR /* 153*/
.long DefaultISR /* 154*/
.long DefaultISR /* 155*/
.long DefaultISR /* 156*/
.long DefaultISR /* 157*/
.long DefaultISR /* 158*/
.long DefaultISR /* 159*/
.long DefaultISR /* 160*/
.long DefaultISR /* 161*/
.long DefaultISR /* 162*/
.long DefaultISR /* 163*/
.long DefaultISR /* 164*/
.long DefaultISR /* 165*/
.long DefaultISR /* 166*/
.long DefaultISR /* 167*/
.long DefaultISR /* 168*/
.long DefaultISR /* 169*/
.long DefaultISR /* 170*/
.long DefaultISR /* 171*/
.long DefaultISR /* 172*/
.long DefaultISR /* 173*/
.long DefaultISR /* 174*/
.long DefaultISR /* 175*/
.long DefaultISR /* 176*/
.long DefaultISR /* 177*/
.long DefaultISR /* 178*/
.long DefaultISR /* 179*/
.long DefaultISR /* 180*/
.long DefaultISR /* 181*/
.long DefaultISR /* 182*/
.long DefaultISR /* 183*/
.long DefaultISR /* 184*/
.long DefaultISR /* 185*/
.long DefaultISR /* 186*/
.long DefaultISR /* 187*/
.long DefaultISR /* 188*/
.long DefaultISR /* 189*/
.long DefaultISR /* 190*/
.long DefaultISR /* 191*/
.long DefaultISR /* 192*/
.long DefaultISR /* 193*/
.long DefaultISR /* 194*/
.long DefaultISR /* 195*/
.long DefaultISR /* 196*/
.long DefaultISR /* 197*/
.long DefaultISR /* 198*/
.long DefaultISR /* 199*/
.long DefaultISR /* 200*/
.long DefaultISR /* 201*/
.long DefaultISR /* 202*/
.long DefaultISR /* 203*/
.long DefaultISR /* 204*/
.long DefaultISR /* 205*/
.long DefaultISR /* 206*/
.long DefaultISR /* 207*/
.long DefaultISR /* 208*/
.long DefaultISR /* 209*/
.long DefaultISR /* 210*/
.long DefaultISR /* 211*/
.long DefaultISR /* 212*/
.long DefaultISR /* 213*/
.long DefaultISR /* 214*/
.long DefaultISR /* 215*/
.long DefaultISR /* 216*/
.long DefaultISR /* 217*/
.long DefaultISR /* 218*/
.long DefaultISR /* 219*/
.long DefaultISR /* 220*/
.long DefaultISR /* 221*/
.long DefaultISR /* 222*/
.long DefaultISR /* 223*/
.long DefaultISR /* 224*/
.long DefaultISR /* 225*/
.long DefaultISR /* 226*/
.long DefaultISR /* 227*/
.long DefaultISR /* 228*/
.long DefaultISR /* 229*/
.long DefaultISR /* 230*/
.long DefaultISR /* 231*/
.long DefaultISR /* 232*/
.long DefaultISR /* 233*/
.long DefaultISR /* 234*/
.long DefaultISR /* 235*/
.long DefaultISR /* 236*/
.long DefaultISR /* 237*/
.long DefaultISR /* 238*/
.long DefaultISR /* 239*/
.long DefaultISR /* 240*/
.long DefaultISR /* 241*/
.long DefaultISR /* 242*/
.long DefaultISR /* 243*/
.long DefaultISR /* 244*/
.long DefaultISR /* 245*/
.long DefaultISR /* 246*/
.long DefaultISR /* 247*/
.long DefaultISR /* 248*/
.long DefaultISR /* 249*/
.long DefaultISR /* 250*/
.long DefaultISR /* 251*/
.long DefaultISR /* 252*/
.long DefaultISR /* 253*/
.long DefaultISR /* 254*/
.long 0xFFFFFFFF /* Reserved for user TRIM value*/
.size __isr_vector, . - __isr_vector
/* Flash Configuration */
.section .FlashConfig, "a"
.long 0xFFFFFFFF /* 8 bytes backdoor comparison key */
.long 0xFFFFFFFF /* */
.long 0xFFFFFFFF /* 4 bytes program flash protection bytes */
.long 0xFFFF7FFE /* FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) */
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
/* Init the rest of the registers */
ldr r1,=0
ldr r2,=0
ldr r3,=0
ldr r4,=0
ldr r5,=0
ldr r6,=0
ldr r7,=0
mov r8,r7
mov r9,r7
mov r10,r7
mov r11,r7
mov r12,r7
#ifdef START_FROM_FLASH
/* Init ECC RAM */
ldr r1, =__RAM_START
ldr r2, =__RAM_END
subs r2, r1
subs r2, #1
ble .LC5
movs r0, 0
movs r3, #4
.LC4:
str r0, [r1]
add r1, r1, r3
subs r2, 4
bge .LC4
.LC5:
#endif
/* Initialize the stack pointer */
ldr r0,=__StackTop
mov r13,r0
#ifndef __NO_SYSTEM_INIT
/* Call the system init routine */
ldr r0,=SystemInit
blx r0
#endif
/* Init .data and .bss sections */
ldr r0,=init_data_bss
blx r0
cpsie i /* Unmask interrupts */
#ifndef __START
#ifdef __EWL__
#define __START __thumb_startup
#else
#define __START _start
#endif
#endif
bl __START
JumpToSelf:
b JumpToSelf
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA0_IRQHandler
def_irq_handler DMA1_IRQHandler
def_irq_handler DMA2_IRQHandler
def_irq_handler DMA3_IRQHandler
def_irq_handler DMA4_IRQHandler
def_irq_handler DMA5_IRQHandler
def_irq_handler DMA6_IRQHandler
def_irq_handler DMA7_IRQHandler
def_irq_handler DMA8_IRQHandler
def_irq_handler DMA9_IRQHandler
def_irq_handler DMA10_IRQHandler
def_irq_handler DMA11_IRQHandler
def_irq_handler DMA12_IRQHandler
def_irq_handler DMA13_IRQHandler
def_irq_handler DMA14_IRQHandler
def_irq_handler DMA15_IRQHandler
def_irq_handler DMA_Error_IRQHandler
def_irq_handler MCM_IRQHandler
def_irq_handler FTFC_IRQHandler
def_irq_handler Read_Collision_IRQHandler
def_irq_handler LVD_LVW_IRQHandler
def_irq_handler FTFC_Fault_IRQHandler
def_irq_handler WDOG_EWM_IRQHandler
def_irq_handler RCM_IRQHandler
def_irq_handler LPI2C0_Master_IRQHandler
def_irq_handler LPI2C0_Slave_IRQHandler
def_irq_handler LPSPI0_IRQHandler
def_irq_handler LPSPI1_IRQHandler
def_irq_handler LPSPI2_IRQHandler
def_irq_handler Reserved45_IRQHandler
def_irq_handler Reserved46_IRQHandler
def_irq_handler LPUART0_RxTx_IRQHandler
def_irq_handler Reserved48_IRQHandler
def_irq_handler LPUART1_RxTx_IRQHandler
def_irq_handler Reserved50_IRQHandler
def_irq_handler LPUART2_RxTx_IRQHandler
def_irq_handler Reserved52_IRQHandler
def_irq_handler Reserved53_IRQHandler
def_irq_handler Reserved54_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler ADC1_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler Reserved58_IRQHandler
def_irq_handler Reserved59_IRQHandler
def_irq_handler ERM_single_fault_IRQHandler
def_irq_handler ERM_double_fault_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler LPIT0_Ch0_IRQHandler
def_irq_handler LPIT0_Ch1_IRQHandler
def_irq_handler LPIT0_Ch2_IRQHandler
def_irq_handler LPIT0_Ch3_IRQHandler
def_irq_handler PDB0_IRQHandler
def_irq_handler Reserved69_IRQHandler
def_irq_handler Reserved70_IRQHandler
def_irq_handler Reserved71_IRQHandler
def_irq_handler Reserved72_IRQHandler
def_irq_handler SCG_IRQHandler
def_irq_handler LPTMR0_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTB_IRQHandler
def_irq_handler PORTC_IRQHandler
def_irq_handler PORTD_IRQHandler
def_irq_handler PORTE_IRQHandler
def_irq_handler SWI_IRQHandler
def_irq_handler Reserved81_IRQHandler
def_irq_handler Reserved82_IRQHandler
def_irq_handler Reserved83_IRQHandler
def_irq_handler PDB1_IRQHandler
def_irq_handler FLEXIO_IRQHandler
def_irq_handler Reserved86_IRQHandler
def_irq_handler Reserved87_IRQHandler
def_irq_handler Reserved88_IRQHandler
def_irq_handler Reserved89_IRQHandler
def_irq_handler Reserved90_IRQHandler
def_irq_handler Reserved91_IRQHandler
def_irq_handler Reserved92_IRQHandler
def_irq_handler Reserved93_IRQHandler
def_irq_handler CAN0_ORed_IRQHandler
def_irq_handler CAN0_Error_IRQHandler
def_irq_handler CAN0_Wake_Up_IRQHandler
def_irq_handler CAN0_ORed_0_15_MB_IRQHandler
def_irq_handler CAN0_ORed_16_31_MB_IRQHandler
def_irq_handler Reserved99_IRQHandler
def_irq_handler Reserved100_IRQHandler
def_irq_handler CAN1_ORed_IRQHandler
def_irq_handler CAN1_Error_IRQHandler
def_irq_handler Reserved103_IRQHandler
def_irq_handler CAN1_ORed_0_15_MB_IRQHandler
def_irq_handler Reserved105_IRQHandler
def_irq_handler Reserved106_IRQHandler
def_irq_handler Reserved107_IRQHandler
def_irq_handler CAN2_ORed_IRQHandler
def_irq_handler CAN2_Error_IRQHandler
def_irq_handler Reserved110_IRQHandler
def_irq_handler CAN2_ORed_0_15_MB_IRQHandler
def_irq_handler Reserved112_IRQHandler
def_irq_handler Reserved113_IRQHandler
def_irq_handler Reserved114_IRQHandler
def_irq_handler FTM0_Ch0_Ch1_IRQHandler
def_irq_handler FTM0_Ch2_Ch3_IRQHandler
def_irq_handler FTM0_Ch4_Ch5_IRQHandler
def_irq_handler FTM0_Ch6_Ch7_IRQHandler
def_irq_handler FTM0_Fault_IRQHandler
def_irq_handler FTM0_Ovf_Reload_IRQHandler
def_irq_handler FTM1_Ch0_Ch1_IRQHandler
def_irq_handler FTM1_Ch2_Ch3_IRQHandler
def_irq_handler FTM1_Ch4_Ch5_IRQHandler
def_irq_handler FTM1_Ch6_Ch7_IRQHandler
def_irq_handler FTM1_Fault_IRQHandler
def_irq_handler FTM1_Ovf_Reload_IRQHandler
def_irq_handler FTM2_Ch0_Ch1_IRQHandler
def_irq_handler FTM2_Ch2_Ch3_IRQHandler
def_irq_handler FTM2_Ch4_Ch5_IRQHandler
def_irq_handler FTM2_Ch6_Ch7_IRQHandler
def_irq_handler FTM2_Fault_IRQHandler
def_irq_handler FTM2_Ovf_Reload_IRQHandler
def_irq_handler FTM3_Ch0_Ch1_IRQHandler
def_irq_handler FTM3_Ch2_Ch3_IRQHandler
def_irq_handler FTM3_Ch4_Ch5_IRQHandler
def_irq_handler FTM3_Ch6_Ch7_IRQHandler
def_irq_handler FTM3_Fault_IRQHandler
def_irq_handler FTM3_Ovf_Reload_IRQHandler
.end

166
Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/.cproject Normal file
View File

@ -0,0 +1,166 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.2040336100">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.2040336100" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.freescale.s32ds.cdt.core.errorParsers.S32DSGNULinkerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="demoprog_s32k144" buildArtefactType="com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" description="" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.2040336100" name="Debug" parent="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug">
<folderInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.2040336100." name="/" resourcePath="">
<toolChain id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.toolchain.debug.458764322" name="ARM Bare-Metal 32-bit Target Binary Toolchain" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.toolchain.debug">
<option defaultValue="true" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize.902597682" name="Print size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize" valueType="boolean"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.libraries.1287224447" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.libraries.newlib_nano_noio" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.abi.103879917" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.abi" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.abi.hard" valueType="enumerated"/>
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Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/Prog_Debug.launch Normal file
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<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;mapping backend_enabled=&amp;quot;true&amp;quot; name=&amp;quot;EWL&amp;quot;&amp;gt;&amp;#13;&amp;#10;&amp;lt;mapEntry memento=&amp;quot;&amp;amp;lt;?xml version=&amp;amp;quot;1.0&amp;amp;quot; encoding=&amp;amp;quot;UTF-8&amp;amp;quot; standalone=&amp;amp;quot;no&amp;amp;quot;?&amp;amp;gt;&amp;amp;#13;&amp;amp;#10;&amp;amp;lt;mapEntry backendPath=&amp;amp;quot;arm32_ewl2&amp;amp;quot; localPath=&amp;amp;quot;C:\NXP\S32DS_ARM_v2.2\S32DS\build_tools\gcc_v6.3\arm32_ewl2&amp;amp;quot;/&amp;amp;gt;&amp;amp;#13;&amp;amp;#10;&amp;quot;/&amp;gt;&amp;#13;&amp;#10;&amp;lt;/mapping&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.cdt.debug.core.containerType.mapping&quot;/&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>

280
Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/S32K144_64_flash.ld Normal file
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@ -0,0 +1,280 @@
/*
** ###################################################################
** Processor: S32K144 with 64 KB SRAM
** Compiler: GNU C Compiler
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
** Copyright 2017 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
/*
To use "new" operator with EWL in C++ project the following symbol shall be defined
*/
/*EXTERN(_ZN10__cxxabiv119__terminate_handlerE)*/
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000400;
/* If symbol __flash_vector_table__=1 is defined at link time
* the interrupt vector will not be copied to RAM.
* Warning: Using the interrupt vector from Flash will not allow
* INT_SYS_InstallHandler because the section is Read Only.
*/
M_VECTOR_RAM_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : 0x0400;
/* Specify the memory areas */
MEMORY
{
/* Flash */
m_interrupts (RX) : ORIGIN = 0x00002000, LENGTH = 0x00000400
m_flash_config (RX) : ORIGIN = 0x00002400, LENGTH = 0x00000010
m_text (RX) : ORIGIN = 0x00002410, LENGTH = 0x0007FBF0 - 0x2000
/* SRAM_L */
m_data (RW) : ORIGIN = 0x1FFF8000, LENGTH = 0x00008000
/* SRAM_U */
m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007000
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into internal flash */
.interrupts :
{
__VECTOR_TABLE = .;
__interrupts_start__ = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
__interrupts_end__ = .;
. = ALIGN(4);
} > m_interrupts
.flash_config :
{
. = ALIGN(4);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
. = ALIGN(4);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* Define a global symbol at end of code. */
__DATA_ROM = .; /* Symbol is used by startup for data initialization. */
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__RAM_START = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start. */
*(.m_interrupts_ram) /* This is a user defined section. */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end. */
} > m_data
__VECTOR_RAM = DEFINED(__flash_vector_table__) ? ORIGIN(m_interrupts) : __VECTOR_RAM__ ;
__RAM_VECTOR_TABLE_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : (__interrupts_ram_end__ - __interrupts_ram_start__) ;
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* Create a global symbol at data start. */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* Define a global symbol at data end. */
} > m_data
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
__CODE_ROM = __DATA_END; /* Symbol is used by code initialization. */
.code : AT(__CODE_ROM)
{
. = ALIGN(4);
__CODE_RAM = .;
__code_start__ = .; /* Create a global symbol at code start. */
__code_ram_start__ = .;
*(.code_ram) /* Custom section for storing code in RAM */
. = ALIGN(4);
__code_end__ = .; /* Define a global symbol at code end. */
__code_ram_end__ = .;
} > m_data
__CODE_END = __CODE_ROM + (__code_end__ - __code_start__);
__CUSTOM_ROM = __CODE_END;
/* Custom Section Block that can be used to place data at absolute address. */
/* Use __attribute__((section (".customSection"))) to place data here. */
.customSectionBlock ORIGIN(m_data_2) : AT(__CUSTOM_ROM)
{
__customSection_start__ = .;
KEEP(*(.customSection)) /* Keep section even if not referenced. */
__customSection_end__ = .;
} > m_data_2
__CUSTOM_END = __CUSTOM_ROM + (__customSection_end__ - __customSection_start__);
/* Uninitialized data section. */
.bss :
{
/* This is used by the startup in order to initialize the .bss section. */
. = ALIGN(4);
__BSS_START = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__BSS_END = .;
} > m_data_2
.heap :
{
. = ALIGN(8);
__end__ = .;
__heap_start__ = .;
PROVIDE(end = .);
PROVIDE(_end = .);
PROVIDE(__end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .;
__heap_end__ = .;
} > m_data_2
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
__RAM_END = __StackTop;
.stack __StackLimit :
{
. = ALIGN(8);
__stack_start__ = .;
. += STACK_SIZE;
__stack_end__ = .;
} > m_data_2
/* Labels required by EWL */
__START_BSS = __BSS_START;
__END_BSS = __BSS_END;
__SP_INIT = __StackTop;
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
}

772
Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/boot.c Normal file
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@ -0,0 +1,772 @@
/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/boot.c
* \brief Demo program bootloader interface source file.
* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
#if (BOOT_COM_RS232_ENABLE > 0)
static void BootComRs232Init(void);
static void BootComRs232CheckActivationRequest(void);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
static void BootComCanInit(void);
static void BootComCanCheckActivationRequest(void);
#endif
/************************************************************************************//**
** \brief Initializes the communication interface.
** \return none.
**
****************************************************************************************/
void BootComInit(void)
{
#if (BOOT_COM_RS232_ENABLE > 0)
BootComRs232Init();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanInit();
#endif
} /*** end of BootComInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
void BootComCheckActivationRequest(void)
{
#if (BOOT_COM_RS232_ENABLE > 0)
BootComRs232CheckActivationRequest();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanCheckActivationRequest();
#endif
} /*** end of BootComCheckActivationRequest ***/
/************************************************************************************//**
** \brief Bootloader activation function.
** \return none.
**
****************************************************************************************/
void BootActivate(void)
{
/* Activate the bootloader by performing a software reset. */
SystemSoftwareReset();
} /*** end of BootActivate ***/
#if (BOOT_COM_RS232_ENABLE > 0)
/****************************************************************************************
* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
* reception of the first packet byte.
*/
#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100u)
/** \brief Set the peripheral LPUART base pointer. */
#define LPUARTx (LPUART1)
/** \brief Set the PCC index offset for LPUART. */
#define PCC_LPUARTx_INDEX (PCC_LPUART1_INDEX)
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static unsigned char Rs232ReceiveByte(unsigned char *data);
/************************************************************************************//**
** \brief Initializes the UART communication interface.
** \return none.
**
****************************************************************************************/
static void BootComRs232Init(void)
{
unsigned long sourceClockFreqHz;
unsigned long div2RegValue;
unsigned short baudrateSbr0_12;
unsigned char const div2DividerLookup[] =
{
0U, /* 0b000. Output disabled. */
1U, /* 0b001. Divide by 1. */
2U, /* 0b010. Divide by 2. */
4U, /* 0b011. Divide by 4. */
8U, /* 0b100. Divide by 8. */
16U, /* 0b101. Divide by 16. */
32U, /* 0b110. Divide by 32. */
64U, /* 0b111. Divide by 64. */
};
/* Make sure the UART peripheral clock is disabled before configuring its source
* clock.
*/
PCC->PCCn[PCC_LPUARTx_INDEX] &= ~PCC_PCCn_CGC_MASK;
/* Select option 2 as the UART peripheral source clock and enable the clock. Option 2
* is the SIRCDIV2_CLK, which is available on all peripherals and configurations.
*/
PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(0b010) | PCC_PCCn_CGC_MASK;
/* Obtain the DIV2 divider value of the SIRC_CLK. */
div2RegValue = (SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT;
/* Check if the DIV2 register value for SIRC is 0. In this case SIRCDIV2_CLK is
* currently disabled.
*/
if (div2RegValue == 0U)
{
/* Configure the DIV2 for a default divide by 1 to make sure the SIRCDIV2_CLK is
* actually enabled.
*/
div2RegValue = 1U;
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(div2RegValue);
}
/* Determine the SIRC clock frequency. If SIRC high range is enabled, it is 8 MHz. If
* SIRC low range is enabled, it is 2 MHz.
*/
sourceClockFreqHz = 8000000U;
if ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) == SCG_SIRCCFG_RANGE(0))
{
sourceClockFreqHz = 2000000U;
}
/* Now process the configured DIV2 divider factor to get the actual frequency of the
* UART peripheral source clock.
*/
sourceClockFreqHz /= div2DividerLookup[div2RegValue];
/* Configure the baudrate from BOOT_COM_RS232_BAUDRATE, taking into account that an
* oversampling of 8 will be configured. Default 8,n,1 format is used. Integer
* rounding is used to get the best value for baudrateSbr0_12. Actual baudrate equals
* sourceClockFreqHz / 8 / baudrateSbr0_12.
*/
baudrateSbr0_12 = (((sourceClockFreqHz / BOOT_COM_RS232_BAUDRATE) + (8U - 1U)) / 8U) &
LPUART_BAUD_SBR_MASK;
/* OSR=7: Over sampling ratio = 7+1=8.
* SBNS=0: One stop bit.
* BOTHEDGE=0: receiver samples only on rising edge.
* M10=0: Rx and Tx use 7 to 9 bit data characters.
* RESYNCDIS=0: Resync during rec'd data word supported.
* LBKDIE, RXEDGIE=0: interrupts disable.
* TDMAE, RDMAE, TDMAE=0: DMA requests disabled.
* MAEN1, MAEN2, MATCFG=0: Match disabled.
*/
LPUARTx->BAUD = LPUART_BAUD_SBR(baudrateSbr0_12) | LPUART_BAUD_OSR(7);
/* Clear the error/interrupt flags */
LPUARTx->STAT = FEATURE_LPUART_STAT_REG_FLAGS_MASK;
/* Reset all features/interrupts by default */
LPUARTx->CTRL = 0x00000000;
/* Reset match addresses */
LPUARTx->MATCH = 0x00000000;
#if FEATURE_LPUART_HAS_MODEM_SUPPORT
/* Reset IrDA modem features */
LPUARTx->MODIR = 0x00000000;
#endif
#if FEATURE_LPUART_FIFO_SIZE > 0U
/* Reset FIFO feature */
LPUARTx->FIFO = FEATURE_LPUART_FIFO_RESET_MASK;
/* Enable the transmit and receive FIFOs. */
LPUARTx->FIFO |= LPUART_FIFO_TXFE(1) | LPUART_FIFO_RXFE(1);
/* Set the reception water mark to 0 and the transmitter water mark to 1. */
LPUARTx->WATER = LPUART_WATER_TXWATER(1) | LPUART_WATER_RXWATER(0);
#endif
/* Enable transmitter and receiver, no parity, 8 bit char:
* RE=1: Receiver enabled.
* TE=1: Transmitter enabled.
* PE,PT=0: No hw parity generation or checking.
* M7,M,R8T9,R9T8=0: 8-bit data characters.
* DOZEEN=0: LPUART enabled in Doze mode.
* ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ.
* TxDIR=0: TxD pin is input if in single-wire mode.
* TXINV=0: Transmit data not inverted.
* RWU,WAKE=0: normal operation; rcvr not in standby.
* IDLCFG=0: one idle character.
* ILT=0: Idle char bit count starts after start bit.
* SBK=0: Normal transmitter operation - no break char.
* LOOPS,RSRC=0: no loop back.
*/
LPUARTx->CTRL = LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK;
} /*** end of BootComRs232Init ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
static void BootComRs232CheckActivationRequest(void)
{
static unsigned char xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1];
static unsigned char xcpCtoRxLength;
static unsigned char xcpCtoRxInProgress = 0;
static unsigned long xcpCtoRxStartTime = 0;
/* start of cto packet received? */
if (xcpCtoRxInProgress == 0)
{
/* store the message length when received */
if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == 1)
{
/* check that the length has a valid value. it should not be 0 */
if ( (xcpCtoReqPacket[0] > 0) &&
(xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) )
{
/* store the start time */
xcpCtoRxStartTime = TimerGet();
/* indicate that a cto packet is being received */
xcpCtoRxInProgress = 1;
/* reset packet data count */
xcpCtoRxLength = 0;
}
}
}
else
{
/* store the next packet byte */
if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
{
/* increment the packet data count */
xcpCtoRxLength++;
/* check to see if the entire packet was received */
if (xcpCtoRxLength == xcpCtoReqPacket[0])
{
/* done with cto packet reception */
xcpCtoRxInProgress = 0;
/* check if this was an XCP CONNECT command */
if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
{
/* connection request received so start the bootloader */
BootActivate();
}
}
}
else
{
/* check packet reception timeout */
if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS))
{
/* cancel cto packet reception due to timeout. note that this automatically
* discards the already received packet bytes, allowing the host to retry.
*/
xcpCtoRxInProgress = 0;
}
}
}
} /*** end of BootComRs232CheckActivationRequest ***/
/************************************************************************************//**
** \brief Receives a communication interface byte if one is present.
** \param data Pointer to byte where the data is to be stored.
** \return 1 if a byte was received, 0 otherwise.
**
****************************************************************************************/
static unsigned char Rs232ReceiveByte(unsigned char *data)
{
unsigned char result = 0;
/* Check if a new byte was received by means of the RDRF-bit. */
if (((LPUARTx->STAT & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_RDRF_SHIFT) != 0U)
{
/* Retrieve and store the newly received byte. */
*data = LPUARTx->DATA;
/* Update the result. */
result = 1;
}
/* Give the result back to the caller. */
return result;
} /*** end of Rs232ReceiveByte ***/
#endif /* BOOT_COM_RS232_ENABLE > 0 */
#if (BOOT_COM_CAN_ENABLE > 0)
/****************************************************************************************
* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */
#define CAN_INIT_TIMEOUT_MS (250U)
/** \brief Set the peripheral CAN0 base pointer. */
#define CANx (CAN0)
/** \brief Set the PCC index offset for CAN0. */
#define PCC_FlexCANx_INDEX (PCC_FlexCAN0_INDEX)
/** \brief Set the number of message boxes supported by CAN0. */
#define CANx_MAX_MB_NUM (FEATURE_CAN0_MAX_MB_NUM)
/** \brief The mailbox used for receiving the XCP command message. */
#define CAN_RX_MSGBOX_NUM (9U)
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Structure type for grouping CAN bus timing related information. */
typedef struct t_can_bus_timing
{
unsigned char timeQuanta; /**< Total number of time quanta */
unsigned char propSeg; /**< CAN propagation segment */
unsigned char phaseSeg1; /**< CAN phase segment 1 */
unsigned char phaseSeg2; /**< CAN phase segment 2 */
} tCanBusTiming;
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief CAN bit timing table for dynamically calculating the bittiming settings.
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + TSEG2)
* * 100%. This array contains possible and valid time quanta configurations
* with a sample point between 68..78%. A visual representation of the TQ in
* a bit is:
* | SYNCSEG | TIME1SEG | TIME2SEG |
* Or with an alternative representation:
* | SYNCSEG | PROPSEG | PHASE1SEG | PHASE2SEG |
* With the alternative representation TIME1SEG = PROPSEG + PHASE1SEG.
*
*/
static const tCanBusTiming canTiming[] =
{
/* Time-Quanta | PROPSEG | PSEG1 | PSEG2 | Sample-Point */
/* ---------------------------------------------------- */
{ 8U, 3U, 2U, 2U }, /*1+3+2+1=8 | 3 | 2 | 2 | 75% */
{ 9U, 3U, 3U, 2U }, /* 9 | 3 | 3 | 2 | 78% */
{ 10U, 3U, 3U, 3U }, /* 10 | 3 | 3 | 3 | 70% */
{ 11U, 4U, 3U, 3U }, /* 11 | 4 | 3 | 3 | 73% */
{ 12U, 4U, 4U, 3U }, /* 12 | 4 | 4 | 3 | 75% */
{ 13U, 5U, 4U, 3U }, /* 13 | 5 | 4 | 3 | 77% */
{ 14U, 5U, 4U, 4U }, /* 14 | 5 | 4 | 4 | 71% */
{ 15U, 6U, 4U, 4U }, /* 15 | 6 | 4 | 4 | 73% */
{ 16U, 6U, 5U, 4U }, /* 16 | 6 | 5 | 4 | 75% */
{ 17U, 7U, 5U, 4U }, /* 17 | 7 | 5 | 4 | 76% */
{ 18U, 7U, 5U, 5U }, /* 18 | 7 | 5 | 5 | 72% */
{ 19U, 8U, 5U, 5U }, /* 19 | 8 | 5 | 5 | 74% */
{ 20U, 8U, 6U, 5U }, /* 20 | 8 | 6 | 5 | 75% */
{ 21U, 8U, 7U, 5U }, /* 21 | 8 | 7 | 5 | 76% */
{ 22U, 8U, 7U, 6U }, /* 22 | 8 | 7 | 6 | 73% */
{ 23U, 8U, 8U, 6U }, /* 23 | 8 | 8 | 6 | 74% */
{ 24U, 8U, 8U, 7U }, /* 24 | 8 | 8 | 7 | 71% */
{ 25U, 8U, 8U, 8U } /* 25 | 8 | 8 | 8 | 68% */
};
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Dummy variable to store the CAN controller's free running timer value in.
* This is needed at the end of a CAN message reception to unlock the mailbox
* again. If this variable is declared locally within the function, it generates
* an unwanted compiler warning about assigning a value and not using it.
* For this reason this dummy variabled is declare here as a module global.
*/
static volatile unsigned long dummyTimerVal;
/************************************************************************************//**
** \brief Search algorithm to match the desired baudrate to a possible bus
** timing configuration.
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
** \param prescaler Pointer to where the value for the prescaler will be stored.
** \param busTimingCfg Pointer to where the bus timing values will be stored.
** \return 1 if the CAN bustiming register values were found, 0 otherwise.
**
****************************************************************************************/
static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short * prescaler,
tCanBusTiming * busTimingCfg)
{
unsigned char cnt;
unsigned long canClockFreqkHz;
unsigned long div2RegValue;
unsigned char const div2DividerLookup[] =
{
0U, /* 0b000. Output disabled. */
1U, /* 0b001. Divide by 1. */
2U, /* 0b010. Divide by 2. */
4U, /* 0b011. Divide by 4. */
8U, /* 0b100. Divide by 8. */
16U, /* 0b101. Divide by 16. */
32U, /* 0b110. Divide by 32. */
64U, /* 0b111. Divide by 64. */
};
/* Obtain the DIV2 divider value of the SOSC_CLK. */
div2RegValue = (SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT;
/* Check if the DIV2 register value for SOSC is 0. In this case SOSCDIV2_CLK is
* currently disabled.
*/
if (div2RegValue == 0U)
{
/* Configure the DIV2 for a default divide by 1 to make sure the SOSCDIV2_CLK is
* actually enabled.
*/
div2RegValue = 1U;
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(div2RegValue);
}
/* Determine the SOSC clock frequency. */
canClockFreqkHz = BOOT_CPU_XTAL_SPEED_KHZ;
/* Now process the configured DIV2 divider factor to get the actual frequency of the
* CAN peripheral source clock.
*/
canClockFreqkHz /= div2DividerLookup[div2RegValue];
/* Loop through all possible time quanta configurations to find a match. */
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
{
if ((canClockFreqkHz % (baud * canTiming[cnt].timeQuanta)) == 0U)
{
/* Compute the prescaler that goes with this TQ configuration. */
*prescaler = canClockFreqkHz/(baud * canTiming[cnt].timeQuanta);
/* Make sure the prescaler is valid. */
if ((*prescaler > 0U) && (*prescaler <= 256U))
{
/* Store the bustiming configuration. */
*busTimingCfg = canTiming[cnt];
/* Found a good bus timing configuration. */
return 1U;
}
}
}
/* Could not find a good bus timing configuration. */
return 0U;
} /*** end of CanGetSpeedConfig ***/
/************************************************************************************//**
** \brief Places the CAN controller in freeze mode. Note that the CAN controller
** can only be placed in freeze mode, if it is actually enabled.
** \return none.
**
****************************************************************************************/
static void CanFreezeModeEnter(void)
{
unsigned long timeout;
/* Request to enter freeze mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(1U);
CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U);
/* Set timeout time for entering freeze mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for freeze mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) == 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CanFreezeModeEnter ***/
/************************************************************************************//**
** \brief Leaves the CAN controller's freeze mode. Note that this operation can
** only be done, if it is actually enabled.
** \return none.
**
****************************************************************************************/
static void CanFreezeModeExit(void)
{
unsigned long timeout;
/* Request to leave freeze mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(0U);
CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(0U);
/* Set timeout time for leaving freeze mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for non freeze mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) != 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CanFreezeModeExit ***/
/************************************************************************************//**
** \brief Places the CAN controller in disabled mode.
** \return none.
**
****************************************************************************************/
static void CanDisabledModeEnter(void)
{
unsigned long timeout;
/* Only continue if the CAN controller is currently enabled. */
if ((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U)
{
/* Request disabled mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(1U);
/* Set timeout time for entering disabled mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for disabled mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) == 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
}
} /*** end of CanDisabledModeEnter ***/
/************************************************************************************//**
** \brief Places the CAN controller in enabled mode.
** \return none.
**
****************************************************************************************/
static void CanDisabledModeExit(void)
{
unsigned long timeout;
/* Only continue if the CAN controller is currently disabled. */
if ((CANx->MCR & CAN_MCR_MDIS_MASK) != 0U)
{
/* Request enabled mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(0U);
/* Set timeout time for leaving disabled mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for disabled mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) != 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
}
} /*** end of CanDisabledModeExit ***/
/************************************************************************************//**
** \brief Initializes the CAN communication interface.
** \return none.
**
****************************************************************************************/
static void BootComCanInit(void)
{
unsigned short prescaler = 0;
tCanBusTiming timingCfg = { 0 };
unsigned char rjw;
unsigned short idx;
unsigned long timeout;
unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
/* Enable the CAN peripheral clock. */
PCC->PCCn[PCC_FlexCANx_INDEX] |= PCC_PCCn_CGC_MASK;
/* The source clock needs to be configured first. For this the CAN controller must be
* in disabled mode, but that can only be entered after first entering freeze mode,
* which in turn can only be in enabled mode. So first enable the module, then goto
* freeze mode and finally enter disabled mode.
*/
CanDisabledModeExit();
CanFreezeModeEnter();
CanDisabledModeEnter();
/* Configure SOSCDIV2 as the source clock. This assumes that an external oscillator
* is available, which is typically the case to meet the clock tolerance requirements
* of the CAN 2.0B secification.
*/
CANx->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK;
/* Leave disabled mode. */
CanDisabledModeExit();
/* Make sure freeze mode is active to be able to initialize the CAN controller. */
CanFreezeModeEnter();
/* Obtain bittiming configuration information. */
(void)CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &timingCfg);
/* Reset the current bittiming configuration. */
CANx->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_PROPSEG_MASK |
CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | CAN_CTRL1_RJW_MASK |
CAN_CTRL1_SMP_MASK);
/* Configure the baudrate prescaler. */
CANx->CTRL1 |= CAN_CTRL1_PRESDIV(prescaler - 1U);
/* Configure the propagation segment. */
CANx->CTRL1 |= CAN_CTRL1_PROPSEG(timingCfg.propSeg - 1U);
/* Configure the phase segments. */
CANx->CTRL1 |= CAN_CTRL1_PSEG1(timingCfg.phaseSeg1 - 1U);
CANx->CTRL1 |= CAN_CTRL1_PSEG2(timingCfg.phaseSeg2 - 1U);
/* The resynchronization jump width (RJW) can be 1 - 4 TQ, yet should never be larger
* than pseg1. Configure the longest possible value for RJW.
*/
rjw = (timingCfg.phaseSeg1 < 4) ? timingCfg.phaseSeg1 : 4;
CANx->CTRL1 |= CAN_CTRL1_RJW(rjw - 1U);
/* All the entries in canTiming[] have a PSEG1 >= 2, so three samples can be used to
* determine the value of the received bit, instead of the default one.
*/
CANx->CTRL1 |= CAN_CTRL1_SMP(1U);
/* Clear the message box RAM. Each message box covers 4 words (1 word = 32-bits. */
for (idx = 0; idx < (CANx_MAX_MB_NUM * 4U); idx++)
{
CANx->RAMn[idx] = 0U;
}
/* Clear the reception mask register for each message box. */
for (idx = 0; idx < CANx_MAX_MB_NUM; idx++)
{
CANx->RXIMR[idx] = 0U;
}
/* Configure the maximum number of message boxes. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(CANx_MAX_MB_NUM - 1U);
/* Disable the self reception feature. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_SRXDIS_MASK) | CAN_MCR_SRXDIS(1U);
/* Enable individual reception masking. This disables the legacy support for the
* global reception mask and the mailbox 14/15 individual reception mask.
*/
CANx->MCR = (CANx->MCR & ~CAN_MCR_IRMQ_MASK) | CAN_MCR_IRMQ(1U);
/* Disable the reception FIFO. This driver only needs to receive one CAN message
* identifier. It is sufficient to use just one dedicated mailbox for this.
*/
CANx->MCR &= ~CAN_MCR_RFEN_MASK;
/* Configure the mask of the invididual message reception mailbox to check all ID bits
* and also the IDE bit.
*/
CANx->RXIMR[CAN_RX_MSGBOX_NUM] = 0x40000000U | 0x1FFFFFFFU;
/* Configure the reception mailbox to receive just the CAN message configured with
* BOOT_COM_CAN_RX_MSG_ID.
* EDL, BRS, ESI=0: CANFD not used.
* CODE=0b0100: mailbox set to active and empty.
* IDE=0: 11-bit CAN identifier.
* SRR, RTR, TIME STAMP=0: not applicable.
*/
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] = 0x04000000;
/* Store the message identifier to receive in the mailbox RAM. */
if ((rxMsgId & 0x80000000U) != 0U)
{
/* It is a 29-bit extended CAN identifier. */
rxMsgId &= ~0x80000000U;
/* Set the IDE bit to configure the message for a 29-bit identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_IDE_MASK;
/* Store the 29-bit CAN identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId);
}
else
{
/* Store the 11-bit CAN identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId << 18U);
}
/* Disable all message box interrupts. */
CANx->IMASK1 = 0U;
/* Clear all mesasge box interrupt flags. */
CANx->IFLAG1 = CAN_IMASK1_BUF31TO0M_MASK;
/* Clear all error interrupt flags */
CANx->ESR1 = CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK |
CAN_ESR1_TWRNINT_MASK | CAN_ESR1_BOFFDONEINT_MASK |
CAN_ESR1_ERRINT_FAST_MASK | CAN_ESR1_ERROVR_MASK;
/* Switch to normal user mode. */
CANx->MCR &= ~CAN_MCR_SUPV_MASK;
CANx->CTRL1 &= ~(CAN_CTRL1_LOM_MASK | CAN_CTRL1_LPB_MASK);
/* Exit freeze mode. */
CanFreezeModeExit();
/* Set timeout time for entering normal user mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for normal user mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_NOTRDY_MASK)) != 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of BootComCanInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
static void BootComCanCheckActivationRequest(void)
{
unsigned char * pMsgBoxData;
unsigned char byteIdx;
unsigned char rxMsgData[8];
unsigned char rxMsgLen;
/* Check if a message was received in the individual mailbox configured to receive
* the BOOT_COM_CAN_RX_MSG_ID message.
*/
if ((CANx->IFLAG1 & (1U << CAN_RX_MSGBOX_NUM)) != 0U)
{
/* Note that there is no need to verify the identifier of the CAN message because the
* mailbox is configured to only receive the BOOT_COM_CAN_TX_MSG_ID message. Start
* by reading out the DLC of the newly received CAN message.
*/
rxMsgLen = (CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] & CAN_WMBn_CS_DLC_MASK) >> CAN_WMBn_CS_DLC_SHIFT;
/* Read the data bytes of the CAN message from the mailbox RAM. */
pMsgBoxData = (unsigned char *)(&CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 2U]);
for (byteIdx = 0; byteIdx < rxMsgLen; byteIdx++)
{
rxMsgData[byteIdx] = pMsgBoxData[((byteIdx) & ~3U) + (3U - ((byteIdx) & 3U))];
}
/* Clear the mailbox interrupt flag by writing a 1 to the corresponding box. */
CANx->IFLAG1 = (1U << CAN_RX_MSGBOX_NUM);
/* Read the free running timer to unlock the mailbox. */
dummyTimerVal = CANx->TIMER;
/* check if this was an XCP CONNECT command */
if ((rxMsgData[0] == 0xff) && (rxMsgLen == 2))
{
/* connection request received so start the bootloader */
BootActivate();
}
}
} /*** end of BootComCanCheckActivationRequest ***/
#endif /* BOOT_COM_CAN_ENABLE > 0 */
/*********************************** end of boot.c *************************************/

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/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/boot.h
* \brief Demo program bootloader interface header file.
* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BOOT_H
#define BOOT_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void BootComInit(void);
void BootComCheckActivationRequest(void);
void BootActivate(void);
#endif /* BOOT_H */
/*********************************** end of boot.h *************************************/

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/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/header.h
* \brief Generic header file.
* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef HEADER_H
#define HEADER_H
/****************************************************************************************
* Include files
****************************************************************************************/
#include "../Boot/blt_conf.h" /* bootloader configuration */
#include "boot.h" /* bootloader interface driver */
#include "led.h" /* LED driver */
#include "timer.h" /* Timer driver */
#include "device_registers.h" /* Device registers */
#include "system_S32K144.h" /* Device sconfiguration */
#endif /* HEADER_H */
/*********************************** end of header.h ***********************************/

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/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/led.c
* \brief LED driver source file.
* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Toggle interval time in milliseconds. */
#define LED_TOGGLE_MS (500U)
/************************************************************************************//**
** \brief Initializes the LED.
** \return none.
**
****************************************************************************************/
void LedInit(void)
{
/* LED GPIO pin configuration. PD0 = GPIO, MUX = ALT1. */
PORTD->PCR[0] |= PORT_PCR_MUX(1);
/* configure Port D pin 0 GPIO as digital output */
PTD->PDDR |= GPIO_PDDR_PDD(0x00000001);
/* turn the LED off on Port D pin 0 */
PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001);
} /*** end of LedInit ***/
/************************************************************************************//**
** \brief Toggles the LED at a fixed time interval.
** \return none.
**
****************************************************************************************/
void LedToggle(void)
{
static unsigned char led_toggle_state = 0;
static unsigned long timer_counter_last = 0;
unsigned long timer_counter_now;
/* Check if toggle interval time passed. */
timer_counter_now = TimerGet();
if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
{
/* Not yet time to toggle. */
return;
}
/* Determine toggle action. */
if (led_toggle_state == 0)
{
led_toggle_state = 1;
/* Turn the LED on. */
PTD->PCOR |= GPIO_PCOR_PTCO(0x00000001);
}
else
{
led_toggle_state = 0;
/* Turn the LED off. */
PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001);
}
/* Store toggle time to determine next toggle interval. */
timer_counter_last = timer_counter_now;
} /*** end of LedToggle ***/
/*********************************** end of led.c **************************************/

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/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/led.h
* \brief LED driver header file.
* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef LED_H
#define LED_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void LedInit(void);
void LedToggle(void);
#endif /* LED_H */
/*********************************** end of led.h **************************************/

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef DEVASSERT_H
#define DEVASSERT_H
#include <stdbool.h>
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro is defined to be used by drivers to validate input parameters and can be disabled.
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined.
* The macros are used to validate input parameters to driver functions.
*
*/
/**
\page Error_detection_and_reporting Error detection and reporting
S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing
a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on
runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important
to use this mechanism during development.
The validation is performed by using DEV_ASSERT macro.
A default implementation of this macro is provided in this file. However, application developers can provide their own
implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the
project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h")
The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol:
- When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation
performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is
prevented (application spins in an infinite loop)
This configuration is recommended for development environments, as it prevents further execution and allows investigating
potential problems from the point of error detection.
- When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations.
This configuration can be used to eliminate the overhead of development-time checks.
It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to
disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks
in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point
to the file containing the custom implementation.
*/
#if defined (CUSTOM_DEVASSERT)
/* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */
#include CUSTOM_DEVASSERT
#elif defined (DEV_ERROR_DETECT)
/* Implement default assert macro */
static inline void DevAssert(volatile bool x)
{
if(x) { } else { BKPT_ASM; for(;;) {} }
}
#define DEV_ASSERT(x) DevAssert(x)
#else
/* Assert macro does nothing */
#define DEV_ASSERT(x) ((void)0)
#endif
#endif /* DEVASSERT_H */
/*******************************************************************************
* EOF
******************************************************************************/

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/*
** ###################################################################
** Abstract:
** Common include file for CMSIS register access layer headers.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
** ###################################################################
*/
#ifndef DEVICE_REGISTERS_H
#define DEVICE_REGISTERS_H
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro defines the device currently in use and may be used by components for specific checks.
*
*/
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if (defined(CPU_S32K144HFT0VLLT) || defined(CPU_S32K144LFT0MLLT))
#define S32K14x_SERIES
/* Specific core definitions */
#include "s32_core_cm4.h"
#define S32K144_SERIES
/* Register definitions */
#include "S32K144.h"
/* CPU specific feature definitions */
#include "S32K144_features.h"
#else
#error "No valid CPU defined!"
#endif
#include "devassert.h"
#endif /* DEVICE_REGISTERS_H */
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*!
* @file s32_core_cm4.h
*
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
* Function-like macros are used instead of inline functions in order to ensure
* that the performance will not be decreased if the functions will not be
* inlined by the compiler.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced.
* The macros defined are used only on some of the drivers, so this might be reported
* when the analysis is made only on one driver.
*/
/*
* Tool Chains:
* GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version
* __GNUC__ : GNU Compiler Collection
* __ghs__ : Green Hills ARM Compiler
* __ICCARM__ : IAR ARM Compiler
* __DCC__ : Wind River Diab Compiler
* __ARMCC_VERSION: ARM Compiler
*/
#if !defined (CORE_CM4_H)
#define CORE_CM4_H
#ifdef __cplusplus
extern "C" {
#endif
/** \brief BKPT_ASM
*
* Macro to be used to trigger an debug interrupt
*/
#define BKPT_ASM __asm("BKPT #0\n\t")
/** \brief Enable FPU
*
* ENABLE_FPU indicates whether SystemInit will enable the Floating point unit (FPU)
*/
#if defined (__GNUC__) || defined (__ARMCC_VERSION)
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
#define ENABLE_FPU
#endif
#elif defined (__ICCARM__)
#if defined __ARMVFP__
#define ENABLE_FPU
#endif
#elif defined (__ghs__) || defined (__DCC__)
#if defined (__VFP__)
#define ENABLE_FPU
#endif
#endif /* if defined (__GNUC__) */
/** \brief Enable interrupts
*/
#if defined (__GNUC__)
#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory");
#else
#define ENABLE_INTERRUPTS() __asm("cpsie i")
#endif
/** \brief Disable interrupts
*/
#if defined (__GNUC__)
#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory");
#else
#define DISABLE_INTERRUPTS() __asm("cpsid i")
#endif
/** \brief Enter low-power standby state
* WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts.
*/
#if defined (__GNUC__)
#define STANDBY() __asm volatile ("wfi")
#else
#define STANDBY() __asm("wfi")
#endif
/** \brief No-op
*/
#define NOP() __asm volatile ("nop")
/** \brief Reverse byte order in a word.
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION)
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \
| ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U))
#endif
/** \brief Reverse byte order in each halfword independently.
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION)
#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \
| ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U))
#endif
/** \brief Places a function in RAM.
*/
#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION)
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));
#elif defined ( __ghs__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far")
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\
_Pragma("ghs callmode=default")
#elif defined ( __ICCARM__ )
#define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#elif defined ( __DCC__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\"") \
_Pragma("use_section CODE")
#define END_FUNCTION_DECLARATION_RAMSECTION ; \
_Pragma("section CODE \".text\"")
#else
/* Keep compatibility with software analysis tools */
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#endif
/* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when
defining a function, it is enough to specify it at the declaration. This
also enables compatibility with software analysis tools. */
#define START_FUNCTION_DEFINITION_RAMSECTION
#define END_FUNCTION_DEFINITION_RAMSECTION
#if defined (__ICCARM__)
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022")
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022")
#else
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL
#endif
/** \brief Get Core ID
*
* GET_CORE_ID returns the processor identification number for cm4
*/
#define GET_CORE_ID() 0U
/** \brief Data alignment.
*/
#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION)
#define ALIGNED(x) __attribute__((aligned(x)))
#elif defined ( __ICCARM__ )
#define stringify(s) tostring(s)
#define tostring(s) #s
#define ALIGNED(x) _Pragma(stringify(data_alignment=x))
#else
/* Keep compatibility with software analysis tools */
#define ALIGNED(x)
#endif
/** \brief Section placement.
*/
#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION)
#define PLACE_IN_SECTION(x) __attribute__((section(x)))
#elif defined ( __ICCARM__ )
#define PLACE_IN_SECTION(x) _Pragma(stringify(section=x))
#else
/* Keep compatibility with software analysis tools */
#define PLACE_IN_SECTION(x)
#endif
/** \brief Endianness.
*/
#define CORE_LITTLE_ENDIAN
#ifdef __cplusplus
}
#endif
#endif /* CORE_CM4_H */
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2015 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* An object with static storage duration declared at block scope cannot be
* accessed directly from outside the block.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
* between a pointer to object and an integer type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
* between pointer to void and an arithmetic type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
* Function is defined for usage by application code.
*
*/
#include "device_registers.h"
#include "system_S32K144.h"
#include "stdbool.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/*FUNCTION**********************************************************************
*
* Function Name : SystemInit
* Description : This function disables the watchdog, enables FPU
* and the power mode protection if the corresponding feature macro
* is enabled. SystemInit is called from startup_device file.
*
* Implements : SystemInit_Activity
*END**************************************************************************/
void SystemInit(void)
{
/**************************************************************************/
/* FPU ENABLE*/
/**************************************************************************/
#ifdef ENABLE_FPU
/* Enable CP10 and CP11 coprocessors */
S32_SCB->CPACR |= (S32_SCB_CPACR_CP10_MASK | S32_SCB_CPACR_CP11_MASK);
#ifdef ERRATA_E6940
/* Disable lazy context save of floating point state by clearing LSPEN bit
* Workaround for errata e6940 */
S32_SCB->FPCCR &= ~(S32_SCB_FPCCR_LSPEN_MASK);
#endif
#endif /* ENABLE_FPU */
/**************************************************************************/
/* WDOG DISABLE*/
/**************************************************************************/
#if (DISABLE_WDOG)
/* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/
WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE;
/* The dummy read is used in order to make sure that the WDOG registers will be configured only
* after the write of the unlock value was completed. */
(void)WDOG->CNT;
/* Initial write of WDOG configuration register:
* enables support for 32-bit refresh/unlock command write words,
* clock select from LPO, update enable, watchdog disabled */
WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) |
(FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) |
(0U << WDOG_CS_EN_SHIFT) |
(1U << WDOG_CS_UPDATE_SHIFT) );
/* Configure timeout */
WDOG->TOVAL = (uint32_t )0xFFFF;
#endif /* (DISABLE_WDOG) */
/**************************************************************************/
/* ENABLE CACHE */
/**************************************************************************/
#if defined(I_CACHE) && (ICACHE_ENABLE == 1)
/* Invalidate and enable code cache */
LMEM->PCCCR = LMEM_PCCCR_INVW0(1) | LMEM_PCCCR_INVW1(1) | LMEM_PCCCR_GO(1) | LMEM_PCCCR_ENCACHE(1);
#endif /* defined(I_CACHE) && (ICACHE_ENABLE == 1) */
}
/*FUNCTION**********************************************************************
*
* Function Name : SystemCoreClockUpdate
* Description : This function must be called whenever the core clock is changed
* during program execution. It evaluates the clock register settings and calculates
* the current core clock.
*
* Implements : SystemCoreClockUpdate_Activity
*END**************************************************************************/
void SystemCoreClockUpdate(void)
{
uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */
uint32_t regValue; /* Temporary variable */
uint32_t divider, prediv, multi;
bool validSystemClockSource = true;
static const uint32_t fircFreq[] = {
FEATURE_SCG_FIRC_FREQ0,
};
divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U;
switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
case 0x1:
/* System OSC */
SCGOUTClock = CPU_XTAL_CLK_HZ;
break;
case 0x2:
/* Slow IRC */
regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT;
if (regValue != 0U)
{
SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ;
}
break;
case 0x3:
/* Fast IRC */
regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT;
SCGOUTClock= fircFreq[regValue];
break;
case 0x6:
/* System PLL */
SCGOUTClock = CPU_XTAL_CLK_HZ;
prediv = ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U;
multi = ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U;
SCGOUTClock = SCGOUTClock * multi / (prediv * 2U);
break;
default:
validSystemClockSource = false;
break;
}
if (validSystemClockSource == true) {
SystemCoreClock = (SCGOUTClock / divider);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : SystemSoftwareReset
* Description : This function is used to initiate a system reset
*
* Implements : SystemSoftwareReset_Activity
*END**************************************************************************/
void SystemSoftwareReset(void)
{
uint32_t regValue;
/* Read Application Interrupt and Reset Control Register */
regValue = S32_SCB->AIRCR;
/* Clear register key */
regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK);
/* Configure System reset request bit and Register Key */
regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY);
regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u);
/* Write computed register value */
S32_SCB->AIRCR = regValue;
}
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2015 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*! @addtogroup soc_support_S32K144*/
/*! @{*/
/*!
* @file system_S32K144.h
* @brief Device specific configuration file for S32K144
*/
#ifndef SYSTEM_S32K144_H_
#define SYSTEM_S32K144_H_ /**< Symbol preventing repeated inclusion */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************
* CPU Settings.
*****************************************************************************/
/* Watchdog disable */
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* Cache enablement */
#ifndef ICACHE_ENABLE
#define ICACHE_ENABLE 0
#endif
/* Value of the external crystal or oscillator clock frequency in Hz */
#ifndef CPU_XTAL_CLK_HZ
#define CPU_XTAL_CLK_HZ 8000000u
#endif
/* Value of the fast internal oscillator clock frequency in Hz */
#ifndef CPU_INT_FAST_CLK_HZ
#define CPU_INT_FAST_CLK_HZ 48000000u
#endif
/* Default System clock value */
#ifndef DEFAULT_SYSTEM_CLOCK
#define DEFAULT_SYSTEM_CLOCK 48000000u
#endif
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the SoC.
*
* This function disables the watchdog, enables FPU.
* if the corresponding feature macro is enabled.
* SystemInit is called from startup_device file.
*/
void SystemInit(void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
* This function must be called when user does not want to use clock manager component.
* If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK
* parameter.
*
*/
void SystemCoreClockUpdate(void);
/**
* @brief Initiates a system reset.
*
* This function is used to initiate a system reset
*/
void SystemSoftwareReset(void);
#ifdef __cplusplus
}
#endif
/*! @}*/
#endif /* #if !defined(SYSTEM_S32K144_H_) */

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/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/main.c
* \brief Demo program application source file.
* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static void Init(void);
static void SystemClockConfig(void);
/************************************************************************************//**
** \brief This is the entry point for the bootloader application and is called
** by the reset interrupt vector after the C-startup routines executed.
** \return Program return code.
**
****************************************************************************************/
int main(void)
{
/* Initialize the microcontroller. */
Init();
/* Initialize the bootloader interface */
BootComInit();
/* Start the infinite program loop. */
while (1)
{
/* Toggle LED with a fixed frequency. */
LedToggle();
/* Check for bootloader activation request */
BootComCheckActivationRequest();
}
/* Program should never get here. */
return 0;
} /*** end of main ***/
/************************************************************************************//**
** \brief Initializes the microcontroller.
** \return none.
**
****************************************************************************************/
static void Init(void)
{
/* Configure the system clock. */
SystemClockConfig();
/* Enable the peripheral clock for the ports that are used. */
PCC->PCCn[PCC_PORTC_INDEX] |= PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK;
#if (BOOT_COM_RS232_ENABLE > 0)
/* UART RX GPIO pin configuration. PC6 = UART1 RX, MUX = ALT2. */
PORTC->PCR[6] |= PORT_PCR_MUX(2);
/* UART TX GPIO pin configuration. PC7 = UART1 TX, MUX = ALT2. */
PORTC->PCR[7] |= PORT_PCR_MUX(2);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
/* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */
PORTE->PCR[4] |= PORT_PCR_MUX(5);
/* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */
PORTE->PCR[5] |= PORT_PCR_MUX(5);
#endif
/* Initialize the timer driver. */
TimerInit();
/* Initialize the led driver. */
LedInit();
/* Enable the global interrupts. */
ENABLE_INTERRUPTS();
} /*** end of Init ***/
/************************************************************************************//**
** \brief System Clock Configuration. This code was derived from a S32 Design Studio
** example program. It uses the 8 MHz external crystal as a source for the
** PLL and configures the normal RUN mode for the following clock settings:
** - SPLL_CLK = 160 MHz
** - CORE_CLK = 80 MHz
** - SYS_CLK = 80 MHz
** - BUS_CLK = 40 MHz
** - FLASH_CLK = 26.67 MHz
** - SIRCDIV1_CLK = 8 MHz
** - SIRCDIV2_CLK = 8 MHz
** \return none.
**
****************************************************************************************/
static void SystemClockConfig(void)
{
/* --------- SOSC Initialization (8 MHz) ------------------------------------------- */
/* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1);
/* Range=2: Medium freq (SOSC betw 1MHz-8MHz).
* HGO=0: Config xtal osc for low power.
* EREFS=1: Input is external XTAL.
*/
SCG->SOSCCFG = SCG_SOSCCFG_RANGE(2) | SCG_SOSCCFG_EREFS_MASK;
/* Ensure SOSCCSR unlocked. */
while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK)
{
;
}
/* LK=0: SOSCCSR can be written.
* SOSCCMRE=0: OSC CLK monitor IRQ if enabled.
* SOSCCM=0: OSC CLK monitor disabled.
* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled.
* SOSCLPEN=0: Sys OSC disabled in VLP modes.
* SOSCSTEN=0: Sys OSC disabled in Stop modes.
* SOSCEN=1: Enable oscillator.
*/
SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK;
/* Wait for system OSC clock to become valid. */
while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
{
;
}
/* --------- SPLL Initialization (160 MHz) ----------------------------------------- */
/* Ensure SPLLCSR is unlocked. */
while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK)
{
;
}
/* SPLLEN=0: SPLL is disabled (default). */
SCG->SPLLCSR &= ~SCG_SPLLCSR_SPLLEN_MASK;
/* SPLLDIV1 divide by 2 and SPLLDIV2 divide by 4. */
SCG->SPLLDIV |= SCG_SPLLDIV_SPLLDIV1(2) | SCG_SPLLDIV_SPLLDIV2(3);
/* PREDIV=0: Divide SOSC_CLK by 0+1=1.
* MULT=24: Multiply sys pll by 4+24=40.
* SPLL_CLK = 8MHz / 1 * 40 / 2 = 160 MHz.
*/
SCG->SPLLCFG = SCG_SPLLCFG_MULT(24);
/* Ensure SPLLCSR is unlocked. */
while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK)
{
;
}
/* LK=0: SPLLCSR can be written.
* SPLLCMRE=0: SPLL CLK monitor IRQ if enabled.
* SPLLCM=0: SPLL CLK monitor disabled.
* SPLLSTEN=0: SPLL disabled in Stop modes.
* SPLLEN=1: Enable SPLL.
*/
SCG->SPLLCSR |= SCG_SPLLCSR_SPLLEN_MASK;
/* Wait for SPLL to become valid. */
while (!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK))
{
;
}
/* --------- SIRC Initialization --------------------------------------------------- */
/* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and
* SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source.
*/
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1);
/* --------- Change to normal RUN mode with 8MHz SOSC, 80 MHz PLL ------------------ */
/* Select PLL as clock source.
* DIVCORE=1, div. by 2: Core clock = 160/2 MHz = 80 MHz.
* DIVBUS=1, div. by 2: bus clock = 40 MHz.
* DIVSLOW=2, div. by 2: SCG slow, flash clock= 26 2/3 MHz.
*/
SCG->RCCR= SCG_RCCR_SCS(6) | SCG_RCCR_DIVCORE(0b01) | SCG_RCCR_DIVBUS(0b01) |
SCG_RCCR_DIVSLOW(0b10);
/* Wait until system clock source is SPLL. */
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6U)
{
;
}
/* Evaluate the clock register settings and calculates the current core clock. This
* function must be called when the clock manager component is not used.
*/
SystemCoreClockUpdate();
} /*** end of SystemClockConfig ***/
/*********************************** end of main.c *************************************/

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/**
\defgroup Prog_ARMCM4_S32K14_S32K144EVB_GCC User Program
\ingroup ARMCM4_S32K14_S32K144EVB_GCC
\brief User Program.
\details The intention of the demo user program is two-fold. (1) To test the
bootloader, you need some sort of firmware to see if you can perform a
firmware update with the bootloader. This program can be used for this
purpose. (2) To make firmware programmable by the bootloader, a few
adjustments to the firmware are required. The demo user program serves as an
example for how these adjustments can be implemented. This demo user program
is a template that can be used as a starting point for creating your own
demo user program.
*/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* All variables with this problem are defined in the linker files.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage
* is declared, its size should be explicitly specified.
* The size of the arrays can not be explicitly determined.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
* between a pointer to object and an integer type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
* between pointer to void and an arithmetic type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable
* code.
* The condition compares two address defined in linker files that can be different.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
* Function is defined for usage by application code.
*
* @section [global]
* Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed
* to return int.
* This is an e200 Power Architecture Assembly instruction used to retrieve
* the core number.
*
*/
#include "startup.h"
#include <stdint.h>
/*******************************************************************************
* Static Variables
******************************************************************************/
static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS;
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : init_data_bss
* Description : Make necessary initializations for RAM.
* - Copy the vector table from ROM to RAM.
* - Copy initialized data from ROM to RAM.
* - Copy code that should reside in RAM from ROM
* - Clear the zero-initialized data section.
*
* Tool Chains:
* __GNUC__ : GNU Compiler Collection
* __ghs__ : Green Hills ARM Compiler
* __ICCARM__ : IAR ARM Compiler
* __DCC__ : Wind River Diab Compiler
* __ARMCC_VERSION : ARMC Compiler
*
* Implements : init_data_bss_Activity
*END**************************************************************************/
void init_data_bss(void)
{
uint32_t n;
uint8_t coreId;
/* For ARMC we are using the library method of initializing DATA, Custom Section and
* Code RAM sections so the below variables are not needed */
#if !defined(__ARMCC_VERSION)
/* Declare pointers for various data sections. These pointers
* are initialized using values pulled in from the linker file */
uint8_t * data_ram;
uint8_t * code_ram;
uint8_t * bss_start;
uint8_t * custom_ram;
const uint8_t * data_rom, * data_rom_end;
const uint8_t * code_rom, * code_rom_end;
const uint8_t * bss_end;
const uint8_t * custom_rom, * custom_rom_end;
#endif
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__ARMCC_VERSION)
extern uint32_t __RAM_VECTOR_TABLE_SIZE;
extern uint32_t __VECTOR_ROM;
extern uint32_t __VECTOR_RAM;
#else
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#endif
/* Get section information from linker files */
#if defined(__ICCARM__)
/* Data */
data_ram = __section_begin(".data");
data_rom = __section_begin(".data_init");
data_rom_end = __section_end(".data_init");
/* CODE RAM */
#pragma section = "__CODE_ROM"
#pragma section = "__CODE_RAM"
code_ram = __section_begin("__CODE_RAM");
code_rom = __section_begin("__CODE_ROM");
code_rom_end = __section_end("__CODE_ROM");
/* BSS */
bss_start = __section_begin(".bss");
bss_end = __section_end(".bss");
custom_ram = __section_begin(".customSection");
custom_rom = __section_begin(".customSection_init");
custom_rom_end = __section_end(".customSection_init");
#elif defined (__ARMCC_VERSION)
/* VECTOR TABLE*/
uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE;
uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM;
uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM;
#else
extern uint32_t __DATA_ROM[];
extern uint32_t __DATA_RAM[];
extern uint32_t __DATA_END[];
extern uint32_t __CODE_RAM[];
extern uint32_t __CODE_ROM[];
extern uint32_t __CODE_END[];
extern uint32_t __BSS_START[];
extern uint32_t __BSS_END[];
extern uint32_t __CUSTOM_ROM[];
extern uint32_t __CUSTOM_END[];
/* Data */
data_ram = (uint8_t *)__DATA_RAM;
data_rom = (uint8_t *)__DATA_ROM;
data_rom_end = (uint8_t *)__DATA_END;
/* CODE RAM */
code_ram = (uint8_t *)__CODE_RAM;
code_rom = (uint8_t *)__CODE_ROM;
code_rom_end = (uint8_t *)__CODE_END;
/* BSS */
bss_start = (uint8_t *)__BSS_START;
bss_end = (uint8_t *)__BSS_END;
/* Custom section */
custom_ram = CUSTOMSECTION_SECTION_START;
custom_rom = (uint8_t *)__CUSTOM_ROM;
custom_rom_end = (uint8_t *)__CUSTOM_END;
#endif
#if !defined(__ARMCC_VERSION)
/* Copy initialized data from ROM to RAM */
while (data_rom_end != data_rom)
{
*data_ram = *data_rom;
data_ram++;
data_rom++;
}
/* Copy functions from ROM to RAM */
while (code_rom_end != code_rom)
{
*code_ram = *code_rom;
code_ram++;
code_rom++;
}
/* Clear the zero-initialized data section */
while(bss_end != bss_start)
{
*bss_start = 0;
bss_start++;
}
/* Copy customsection rom to ram */
while(custom_rom_end != custom_rom)
{
*custom_ram = *custom_rom;
custom_rom++;
custom_ram++;
}
#endif
coreId = (uint8_t)GET_CORE_ID();
#if defined (__ARMCC_VERSION)
/* Copy the vector table from ROM to RAM */
/* Workaround */
for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++)
{
vector_ram[n] = vector_rom[n];
}
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t) __VECTOR_RAM;
#else
/* Check if VECTOR_TABLE copy is needed */
if (__VECTOR_RAM != __VECTOR_TABLE)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t)__VECTOR_RAM;
}
else
{
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t)__VECTOR_TABLE;
}
#endif
}
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef STARTUP_H
#define STARTUP_H
#include <stdint.h>
#include "device_registers.h"
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced.
* The defined macro is used as include guard.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* All variables with this problem are defined in the linker files.
*
*/
/*******************************************************************************
* API
******************************************************************************/
/*!
* @brief define symbols that specific start and end addres of some basic sections.
*/
#if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) || defined (S32K144W_M4_SERIES)
#if (defined(__ICCARM__))
#define INTERRUPTS_SECTION_START __section_begin(".intvec")
#define INTERRUPTS_SECTION_END __section_end(".intvec")
#define BSS_SECTION_START __section_begin(".bss")
#define BSS_SECTION_END __section_end(".bss")
#define DATA_SECTION_START __section_begin(".data")
#define DATA_SECTION_END __section_end(".data")
#define CUSTOMSECTION_SECTION_START __section_begin(".customSection")
#define CUSTOMSECTION_SECTION_END __section_end(".customSection")
#define CODE_RAM_SECTION_START __section_begin("__CODE_RAM")
#define CODE_RAM_SECTION_END __section_end("__CODE_RAM")
#define DATA_INIT_SECTION_START __section_begin(".data_init")
#define DATA_INIT_SECTION_END __section_end(".data_init")
#define CODE_ROM_SECTION_START __section_begin("__CODE_ROM")
#define CODE_ROM_SECTION_END __section_end("__CODE_ROM")
#elif (defined(__ARMCC_VERSION))
#define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START
#define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END
#define BSS_SECTION_START (uint8_t *)__BSS_START
#define BSS_SECTION_END (uint8_t *)__BSS_END
#define DATA_SECTION_START (uint8_t *)__DATA_RAM_START
#define DATA_SECTION_END (uint8_t *)__DATA_RAM_END
#define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START
#define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END
#define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START
#define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END
extern uint32_t __VECTOR_ROM_START;
extern uint32_t __VECTOR_ROM_END;
extern uint32_t __BSS_START;
extern uint32_t __BSS_END;
extern uint32_t __DATA_RAM_START;
extern uint32_t __DATA_RAM_END;
extern uint32_t __CUSTOM_SECTION_START;
extern uint32_t __CUSTOM_SECTION_END;
extern uint32_t __CODE_RAM_START;
extern uint32_t __CODE_RAM_END;
#else
#define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__
#define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__
#define BSS_SECTION_START (uint8_t *)&__bss_start__
#define BSS_SECTION_END (uint8_t *)&__bss_end__
#define DATA_SECTION_START (uint8_t *)&__data_start__
#define DATA_SECTION_END (uint8_t *)&__data_end__
#define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__
#define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__
#define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__
#define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__
extern uint32_t __interrupts_start__;
extern uint32_t __interrupts_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __customSection_start__;
extern uint32_t __customSection_end__;
extern uint32_t __code_ram_start__;
extern uint32_t __code_ram_end__;
#endif
#endif
#if (defined(__ICCARM__))
#pragma section = ".data"
#pragma section = ".data_init"
#pragma section = ".bss"
#pragma section = ".intvec"
#pragma section = ".customSection"
#pragma section = ".customSection_init"
#pragma section = "__CODE_RAM"
#pragma section = "__CODE_ROM"
#endif
/*!
* @brief Make necessary initializations for RAM.
*
* - Copy initialized data from ROM to RAM.
* - Clear the zero-initialized data section.
* - Copy the vector table from ROM to RAM. This could be an option.
*/
void init_data_bss(void);
#endif /* STARTUP_H*/
/*******************************************************************************
* EOF
******************************************************************************/

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/* ---------------------------------------------------------------------------------------*/
/* @file: startup_S32K144.s */
/* @purpose: GNU Compiler Collection Startup File */
/* S32K144 */
/* @version: 2.0 */
/* @date: 2017-1-10 */
/* @build: b170107 */
/* ---------------------------------------------------------------------------------------*/
/* */
/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. */
/* Copyright 2016-2017 NXP */
/* All rights reserved. */
/* */
/* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES */
/* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. */
/* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, */
/* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR */
/* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) */
/* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, */
/* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING */
/* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF */
/* THE POSSIBILITY OF SUCH DAMAGE. */
/*****************************************************************************/
/* Version: GNU Compiler Collection */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_IRQHandler /* DMA channel 0 transfer complete*/
.long DMA1_IRQHandler /* DMA channel 1 transfer complete*/
.long DMA2_IRQHandler /* DMA channel 2 transfer complete*/
.long DMA3_IRQHandler /* DMA channel 3 transfer complete*/
.long DMA4_IRQHandler /* DMA channel 4 transfer complete*/
.long DMA5_IRQHandler /* DMA channel 5 transfer complete*/
.long DMA6_IRQHandler /* DMA channel 6 transfer complete*/
.long DMA7_IRQHandler /* DMA channel 7 transfer complete*/
.long DMA8_IRQHandler /* DMA channel 8 transfer complete*/
.long DMA9_IRQHandler /* DMA channel 9 transfer complete*/
.long DMA10_IRQHandler /* DMA channel 10 transfer complete*/
.long DMA11_IRQHandler /* DMA channel 11 transfer complete*/
.long DMA12_IRQHandler /* DMA channel 12 transfer complete*/
.long DMA13_IRQHandler /* DMA channel 13 transfer complete*/
.long DMA14_IRQHandler /* DMA channel 14 transfer complete*/
.long DMA15_IRQHandler /* DMA channel 15 transfer complete*/
.long DMA_Error_IRQHandler /* DMA error interrupt channels 0-15*/
.long MCM_IRQHandler /* FPU sources*/
.long FTFC_IRQHandler /* FTFC Command complete*/
.long Read_Collision_IRQHandler /* FTFC Read collision*/
.long LVD_LVW_IRQHandler /* PMC Low voltage detect interrupt*/
.long FTFC_Fault_IRQHandler /* FTFC Double bit fault detect*/
.long WDOG_EWM_IRQHandler /* Single interrupt vector for WDOG and EWM*/
.long RCM_IRQHandler /* RCM Asynchronous Interrupt*/
.long LPI2C0_Master_IRQHandler /* LPI2C0 Master Interrupt*/
.long LPI2C0_Slave_IRQHandler /* LPI2C0 Slave Interrupt*/
.long LPSPI0_IRQHandler /* LPSPI0 Interrupt*/
.long LPSPI1_IRQHandler /* LPSPI1 Interrupt*/
.long LPSPI2_IRQHandler /* LPSPI2 Interrupt*/
.long Reserved45_IRQHandler /* Reserved Interrupt 45*/
.long Reserved46_IRQHandler /* Reserved Interrupt 46*/
.long LPUART0_RxTx_IRQHandler /* LPUART0 Transmit / Receive Interrupt*/
.long Reserved48_IRQHandler /* Reserved Interrupt 48*/
.long LPUART1_RxTx_IRQHandler /* LPUART1 Transmit / Receive Interrupt*/
.long Reserved50_IRQHandler /* Reserved Interrupt 50*/
.long LPUART2_RxTx_IRQHandler /* LPUART2 Transmit / Receive Interrupt*/
.long Reserved52_IRQHandler /* Reserved Interrupt 52*/
.long Reserved53_IRQHandler /* Reserved Interrupt 53*/
.long Reserved54_IRQHandler /* Reserved Interrupt 54*/
.long ADC0_IRQHandler /* ADC0 interrupt request.*/
.long ADC1_IRQHandler /* ADC1 interrupt request.*/
.long CMP0_IRQHandler /* CMP0 interrupt request*/
.long Reserved58_IRQHandler /* Reserved Interrupt 58*/
.long Reserved59_IRQHandler /* Reserved Interrupt 59*/
.long ERM_single_fault_IRQHandler /* ERM single bit error correction*/
.long ERM_double_fault_IRQHandler /* ERM double bit error non-correctable*/
.long RTC_IRQHandler /* RTC alarm interrupt*/
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
.long LPIT0_Ch0_IRQHandler /* LPIT0 channel 0 overflow interrupt*/
.long LPIT0_Ch1_IRQHandler /* LPIT0 channel 1 overflow interrupt*/
.long LPIT0_Ch2_IRQHandler /* LPIT0 channel 2 overflow interrupt*/
.long LPIT0_Ch3_IRQHandler /* LPIT0 channel 3 overflow interrupt*/
.long PDB0_IRQHandler /* PDB0 interrupt*/
.long Reserved69_IRQHandler /* Reserved Interrupt 69*/
.long Reserved70_IRQHandler /* Reserved Interrupt 70*/
.long Reserved71_IRQHandler /* Reserved Interrupt 71*/
.long Reserved72_IRQHandler /* Reserved Interrupt 72*/
.long SCG_IRQHandler /* SCG bus interrupt request*/
.long LPTMR0_IRQHandler /* LPTIMER interrupt request*/
.long PORTA_IRQHandler /* Port A pin detect interrupt*/
.long PORTB_IRQHandler /* Port B pin detect interrupt*/
.long PORTC_IRQHandler /* Port C pin detect interrupt*/
.long PORTD_IRQHandler /* Port D pin detect interrupt*/
.long PORTE_IRQHandler /* Port E pin detect interrupt*/
.long SWI_IRQHandler /* Software interrupt*/
.long Reserved81_IRQHandler /* Reserved Interrupt 81*/
.long Reserved82_IRQHandler /* Reserved Interrupt 82*/
.long Reserved83_IRQHandler /* Reserved Interrupt 83*/
.long PDB1_IRQHandler /* PDB1 interrupt*/
.long FLEXIO_IRQHandler /* FlexIO Interrupt*/
.long Reserved86_IRQHandler /* Reserved Interrupt 86*/
.long Reserved87_IRQHandler /* Reserved Interrupt 87*/
.long Reserved88_IRQHandler /* Reserved Interrupt 88*/
.long Reserved89_IRQHandler /* Reserved Interrupt 89*/
.long Reserved90_IRQHandler /* Reserved Interrupt 90*/
.long Reserved91_IRQHandler /* Reserved Interrupt 91*/
.long Reserved92_IRQHandler /* Reserved Interrupt 92*/
.long Reserved93_IRQHandler /* Reserved Interrupt 93*/
.long CAN0_ORed_IRQHandler /* CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
.long CAN0_Error_IRQHandler /* CAN0 Interrupt indicating that errors were detected on the CAN bus*/
.long CAN0_Wake_Up_IRQHandler /* CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode*/
.long CAN0_ORed_0_15_MB_IRQHandler /* CAN0 OR'ed Message buffer (0-15)*/
.long CAN0_ORed_16_31_MB_IRQHandler /* CAN0 OR'ed Message buffer (16-31)*/
.long Reserved99_IRQHandler /* Reserved Interrupt 99*/
.long Reserved100_IRQHandler /* Reserved Interrupt 100*/
.long CAN1_ORed_IRQHandler /* CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
.long CAN1_Error_IRQHandler /* CAN1 Interrupt indicating that errors were detected on the CAN bus*/
.long Reserved103_IRQHandler /* Reserved Interrupt 103*/
.long CAN1_ORed_0_15_MB_IRQHandler /* CAN1 OR'ed Interrupt for Message buffer (0-15)*/
.long Reserved105_IRQHandler /* Reserved Interrupt 105*/
.long Reserved106_IRQHandler /* Reserved Interrupt 106*/
.long Reserved107_IRQHandler /* Reserved Interrupt 107*/
.long CAN2_ORed_IRQHandler /* CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
.long CAN2_Error_IRQHandler /* CAN2 Interrupt indicating that errors were detected on the CAN bus*/
.long Reserved110_IRQHandler /* Reserved Interrupt 110*/
.long CAN2_ORed_0_15_MB_IRQHandler /* CAN2 OR'ed Message buffer (0-15)*/
.long Reserved112_IRQHandler /* Reserved Interrupt 112*/
.long Reserved113_IRQHandler /* Reserved Interrupt 113*/
.long Reserved114_IRQHandler /* Reserved Interrupt 114*/
.long FTM0_Ch0_Ch1_IRQHandler /* FTM0 Channel 0 and 1 interrupt*/
.long FTM0_Ch2_Ch3_IRQHandler /* FTM0 Channel 2 and 3 interrupt*/
.long FTM0_Ch4_Ch5_IRQHandler /* FTM0 Channel 4 and 5 interrupt*/
.long FTM0_Ch6_Ch7_IRQHandler /* FTM0 Channel 6 and 7 interrupt*/
.long FTM0_Fault_IRQHandler /* FTM0 Fault interrupt*/
.long FTM0_Ovf_Reload_IRQHandler /* FTM0 Counter overflow and Reload interrupt*/
.long FTM1_Ch0_Ch1_IRQHandler /* FTM1 Channel 0 and 1 interrupt*/
.long FTM1_Ch2_Ch3_IRQHandler /* FTM1 Channel 2 and 3 interrupt*/
.long FTM1_Ch4_Ch5_IRQHandler /* FTM1 Channel 4 and 5 interrupt*/
.long FTM1_Ch6_Ch7_IRQHandler /* FTM1 Channel 6 and 7 interrupt*/
.long FTM1_Fault_IRQHandler /* FTM1 Fault interrupt*/
.long FTM1_Ovf_Reload_IRQHandler /* FTM1 Counter overflow and Reload interrupt*/
.long FTM2_Ch0_Ch1_IRQHandler /* FTM2 Channel 0 and 1 interrupt*/
.long FTM2_Ch2_Ch3_IRQHandler /* FTM2 Channel 2 and 3 interrupt*/
.long FTM2_Ch4_Ch5_IRQHandler /* FTM2 Channel 4 and 5 interrupt*/
.long FTM2_Ch6_Ch7_IRQHandler /* FTM2 Channel 6 and 7 interrupt*/
.long FTM2_Fault_IRQHandler /* FTM2 Fault interrupt*/
.long FTM2_Ovf_Reload_IRQHandler /* FTM2 Counter overflow and Reload interrupt*/
.long FTM3_Ch0_Ch1_IRQHandler /* FTM3 Channel 0 and 1 interrupt*/
.long FTM3_Ch2_Ch3_IRQHandler /* FTM3 Channel 2 and 3 interrupt*/
.long FTM3_Ch4_Ch5_IRQHandler /* FTM3 Channel 4 and 5 interrupt*/
.long FTM3_Ch6_Ch7_IRQHandler /* FTM3 Channel 6 and 7 interrupt*/
.long FTM3_Fault_IRQHandler /* FTM3 Fault interrupt*/
.long FTM3_Ovf_Reload_IRQHandler /* FTM3 Counter overflow and Reload interrupt*/
.long DefaultISR /* 139*/
.long DefaultISR /* 140*/
.long DefaultISR /* 141*/
.long DefaultISR /* 142*/
.long DefaultISR /* 143*/
.long DefaultISR /* 144*/
.long DefaultISR /* 145*/
.long DefaultISR /* 146*/
.long DefaultISR /* 147*/
.long DefaultISR /* 148*/
.long DefaultISR /* 149*/
.long DefaultISR /* 150*/
.long DefaultISR /* 151*/
.long DefaultISR /* 152*/
.long DefaultISR /* 153*/
.long DefaultISR /* 154*/
.long DefaultISR /* 155*/
.long DefaultISR /* 156*/
.long DefaultISR /* 157*/
.long DefaultISR /* 158*/
.long DefaultISR /* 159*/
.long DefaultISR /* 160*/
.long DefaultISR /* 161*/
.long DefaultISR /* 162*/
.long DefaultISR /* 163*/
.long DefaultISR /* 164*/
.long DefaultISR /* 165*/
.long DefaultISR /* 166*/
.long DefaultISR /* 167*/
.long DefaultISR /* 168*/
.long DefaultISR /* 169*/
.long DefaultISR /* 170*/
.long DefaultISR /* 171*/
.long DefaultISR /* 172*/
.long DefaultISR /* 173*/
.long DefaultISR /* 174*/
.long DefaultISR /* 175*/
.long DefaultISR /* 176*/
.long DefaultISR /* 177*/
.long DefaultISR /* 178*/
.long DefaultISR /* 179*/
.long DefaultISR /* 180*/
.long DefaultISR /* 181*/
.long DefaultISR /* 182*/
.long DefaultISR /* 183*/
.long DefaultISR /* 184*/
.long DefaultISR /* 185*/
.long DefaultISR /* 186*/
.long DefaultISR /* 187*/
.long DefaultISR /* 188*/
.long DefaultISR /* 189*/
.long DefaultISR /* 190*/
.long DefaultISR /* 191*/
.long DefaultISR /* 192*/
.long DefaultISR /* 193*/
.long DefaultISR /* 194*/
.long DefaultISR /* 195*/
.long DefaultISR /* 196*/
.long DefaultISR /* 197*/
.long DefaultISR /* 198*/
.long DefaultISR /* 199*/
.long DefaultISR /* 200*/
.long DefaultISR /* 201*/
.long DefaultISR /* 202*/
.long DefaultISR /* 203*/
.long DefaultISR /* 204*/
.long DefaultISR /* 205*/
.long DefaultISR /* 206*/
.long DefaultISR /* 207*/
.long DefaultISR /* 208*/
.long DefaultISR /* 209*/
.long DefaultISR /* 210*/
.long DefaultISR /* 211*/
.long DefaultISR /* 212*/
.long DefaultISR /* 213*/
.long DefaultISR /* 214*/
.long DefaultISR /* 215*/
.long DefaultISR /* 216*/
.long DefaultISR /* 217*/
.long DefaultISR /* 218*/
.long DefaultISR /* 219*/
.long DefaultISR /* 220*/
.long DefaultISR /* 221*/
.long DefaultISR /* 222*/
.long DefaultISR /* 223*/
.long DefaultISR /* 224*/
.long DefaultISR /* 225*/
.long DefaultISR /* 226*/
.long DefaultISR /* 227*/
.long DefaultISR /* 228*/
.long DefaultISR /* 229*/
.long DefaultISR /* 230*/
.long DefaultISR /* 231*/
.long DefaultISR /* 232*/
.long DefaultISR /* 233*/
.long DefaultISR /* 234*/
.long DefaultISR /* 235*/
.long DefaultISR /* 236*/
.long DefaultISR /* 237*/
.long DefaultISR /* 238*/
.long DefaultISR /* 239*/
.long DefaultISR /* 240*/
.long DefaultISR /* 241*/
.long DefaultISR /* 242*/
.long DefaultISR /* 243*/
.long DefaultISR /* 244*/
.long DefaultISR /* 245*/
.long DefaultISR /* 246*/
.long DefaultISR /* 247*/
.long DefaultISR /* 248*/
.long DefaultISR /* 249*/
.long DefaultISR /* 250*/
.long DefaultISR /* 251*/
.long DefaultISR /* 252*/
.long DefaultISR /* 253*/
.long 0x55AA11EE /* 254 - Reserved for OpenBLT checksum*/
.long 0xFFFFFFFF /* Reserved for user TRIM value*/
.size __isr_vector, . - __isr_vector
/* Flash Configuration */
.section .FlashConfig, "a"
.long 0xFFFFFFFF /* 8 bytes backdoor comparison key */
.long 0xFFFFFFFF /* */
.long 0xFFFFFFFF /* 4 bytes program flash protection bytes */
.long 0xFFFF7FFE /* FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) */
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
/* Init the rest of the registers */
ldr r1,=0
ldr r2,=0
ldr r3,=0
ldr r4,=0
ldr r5,=0
ldr r6,=0
ldr r7,=0
mov r8,r7
mov r9,r7
mov r10,r7
mov r11,r7
mov r12,r7
#ifdef START_FROM_FLASH
/* Init ECC RAM */
ldr r1, =__RAM_START
ldr r2, =__RAM_END
subs r2, r1
subs r2, #1
ble .LC5
movs r0, 0
movs r3, #4
.LC4:
str r0, [r1]
add r1, r1, r3
subs r2, 4
bge .LC4
.LC5:
#endif
/* Initialize the stack pointer */
ldr r0,=__StackTop
mov r13,r0
#ifndef __NO_SYSTEM_INIT
/* Call the system init routine */
ldr r0,=SystemInit
blx r0
#endif
/* Init .data and .bss sections */
ldr r0,=init_data_bss
blx r0
cpsie i /* Unmask interrupts */
#ifndef __START
#ifdef __EWL__
#define __START __thumb_startup
#else
#define __START _start
#endif
#endif
bl __START
JumpToSelf:
b JumpToSelf
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA0_IRQHandler
def_irq_handler DMA1_IRQHandler
def_irq_handler DMA2_IRQHandler
def_irq_handler DMA3_IRQHandler
def_irq_handler DMA4_IRQHandler
def_irq_handler DMA5_IRQHandler
def_irq_handler DMA6_IRQHandler
def_irq_handler DMA7_IRQHandler
def_irq_handler DMA8_IRQHandler
def_irq_handler DMA9_IRQHandler
def_irq_handler DMA10_IRQHandler
def_irq_handler DMA11_IRQHandler
def_irq_handler DMA12_IRQHandler
def_irq_handler DMA13_IRQHandler
def_irq_handler DMA14_IRQHandler
def_irq_handler DMA15_IRQHandler
def_irq_handler DMA_Error_IRQHandler
def_irq_handler MCM_IRQHandler
def_irq_handler FTFC_IRQHandler
def_irq_handler Read_Collision_IRQHandler
def_irq_handler LVD_LVW_IRQHandler
def_irq_handler FTFC_Fault_IRQHandler
def_irq_handler WDOG_EWM_IRQHandler
def_irq_handler RCM_IRQHandler
def_irq_handler LPI2C0_Master_IRQHandler
def_irq_handler LPI2C0_Slave_IRQHandler
def_irq_handler LPSPI0_IRQHandler
def_irq_handler LPSPI1_IRQHandler
def_irq_handler LPSPI2_IRQHandler
def_irq_handler Reserved45_IRQHandler
def_irq_handler Reserved46_IRQHandler
def_irq_handler LPUART0_RxTx_IRQHandler
def_irq_handler Reserved48_IRQHandler
def_irq_handler LPUART1_RxTx_IRQHandler
def_irq_handler Reserved50_IRQHandler
def_irq_handler LPUART2_RxTx_IRQHandler
def_irq_handler Reserved52_IRQHandler
def_irq_handler Reserved53_IRQHandler
def_irq_handler Reserved54_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler ADC1_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler Reserved58_IRQHandler
def_irq_handler Reserved59_IRQHandler
def_irq_handler ERM_single_fault_IRQHandler
def_irq_handler ERM_double_fault_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler LPIT0_Ch0_IRQHandler
def_irq_handler LPIT0_Ch1_IRQHandler
def_irq_handler LPIT0_Ch2_IRQHandler
def_irq_handler LPIT0_Ch3_IRQHandler
def_irq_handler PDB0_IRQHandler
def_irq_handler Reserved69_IRQHandler
def_irq_handler Reserved70_IRQHandler
def_irq_handler Reserved71_IRQHandler
def_irq_handler Reserved72_IRQHandler
def_irq_handler SCG_IRQHandler
def_irq_handler LPTMR0_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTB_IRQHandler
def_irq_handler PORTC_IRQHandler
def_irq_handler PORTD_IRQHandler
def_irq_handler PORTE_IRQHandler
def_irq_handler SWI_IRQHandler
def_irq_handler Reserved81_IRQHandler
def_irq_handler Reserved82_IRQHandler
def_irq_handler Reserved83_IRQHandler
def_irq_handler PDB1_IRQHandler
def_irq_handler FLEXIO_IRQHandler
def_irq_handler Reserved86_IRQHandler
def_irq_handler Reserved87_IRQHandler
def_irq_handler Reserved88_IRQHandler
def_irq_handler Reserved89_IRQHandler
def_irq_handler Reserved90_IRQHandler
def_irq_handler Reserved91_IRQHandler
def_irq_handler Reserved92_IRQHandler
def_irq_handler Reserved93_IRQHandler
def_irq_handler CAN0_ORed_IRQHandler
def_irq_handler CAN0_Error_IRQHandler
def_irq_handler CAN0_Wake_Up_IRQHandler
def_irq_handler CAN0_ORed_0_15_MB_IRQHandler
def_irq_handler CAN0_ORed_16_31_MB_IRQHandler
def_irq_handler Reserved99_IRQHandler
def_irq_handler Reserved100_IRQHandler
def_irq_handler CAN1_ORed_IRQHandler
def_irq_handler CAN1_Error_IRQHandler
def_irq_handler Reserved103_IRQHandler
def_irq_handler CAN1_ORed_0_15_MB_IRQHandler
def_irq_handler Reserved105_IRQHandler
def_irq_handler Reserved106_IRQHandler
def_irq_handler Reserved107_IRQHandler
def_irq_handler CAN2_ORed_IRQHandler
def_irq_handler CAN2_Error_IRQHandler
def_irq_handler Reserved110_IRQHandler
def_irq_handler CAN2_ORed_0_15_MB_IRQHandler
def_irq_handler Reserved112_IRQHandler
def_irq_handler Reserved113_IRQHandler
def_irq_handler Reserved114_IRQHandler
def_irq_handler FTM0_Ch0_Ch1_IRQHandler
def_irq_handler FTM0_Ch2_Ch3_IRQHandler
def_irq_handler FTM0_Ch4_Ch5_IRQHandler
def_irq_handler FTM0_Ch6_Ch7_IRQHandler
def_irq_handler FTM0_Fault_IRQHandler
def_irq_handler FTM0_Ovf_Reload_IRQHandler
def_irq_handler FTM1_Ch0_Ch1_IRQHandler
def_irq_handler FTM1_Ch2_Ch3_IRQHandler
def_irq_handler FTM1_Ch4_Ch5_IRQHandler
def_irq_handler FTM1_Ch6_Ch7_IRQHandler
def_irq_handler FTM1_Fault_IRQHandler
def_irq_handler FTM1_Ovf_Reload_IRQHandler
def_irq_handler FTM2_Ch0_Ch1_IRQHandler
def_irq_handler FTM2_Ch2_Ch3_IRQHandler
def_irq_handler FTM2_Ch4_Ch5_IRQHandler
def_irq_handler FTM2_Ch6_Ch7_IRQHandler
def_irq_handler FTM2_Fault_IRQHandler
def_irq_handler FTM2_Ovf_Reload_IRQHandler
def_irq_handler FTM3_Ch0_Ch1_IRQHandler
def_irq_handler FTM3_Ch2_Ch3_IRQHandler
def_irq_handler FTM3_Ch4_Ch5_IRQHandler
def_irq_handler FTM3_Ch6_Ch7_IRQHandler
def_irq_handler FTM3_Fault_IRQHandler
def_irq_handler FTM3_Ovf_Reload_IRQHandler
.end

88
Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/timer.c Normal file
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@ -0,0 +1,88 @@
/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/timer.c
* \brief Timer driver source file.
* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Local variable for storing the number of milliseconds that have elapsed since
* startup.
*/
static unsigned long millisecond_counter;
/************************************************************************************//**
** \brief Initializes the timer.
** \return none.
**
****************************************************************************************/
void TimerInit(void)
{
/* Configure the systick frequency as a 1 ms event generator. */
S32_SysTick->RVR = (SystemCoreClock / 1000U) - 1U;
/* Reset the current counter value. */
S32_SysTick->CVR = 0U;
/* Select core clock as source and enable the timer. */
S32_SysTick->CSR = S32_SysTick_CSR_ENABLE_MASK |
S32_SysTick_CSR_TICKINT_MASK |
S32_SysTick_CSR_CLKSOURCE_MASK;
/* Reset the millisecond counter value. */
millisecond_counter = 0U;
} /*** end of TimerInit ***/
/************************************************************************************//**
** \brief Obtains the counter value of the millisecond timer.
** \return Current value of the millisecond timer.
**
****************************************************************************************/
unsigned long TimerGet(void)
{
/* Read and return the tick counter value. */
return millisecond_counter;
} /*** end of TimerGet ***/
/************************************************************************************//**
** \brief Interrupt service routine of the timer.
** \return none.
**
****************************************************************************************/
void SysTick_Handler(void)
{
/* Increment the millisecond counter. */
millisecond_counter++;
} /*** end of SysTick_Handler ***/
/*********************************** end of timer.c ************************************/

38
Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/timer.h Normal file
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@ -0,0 +1,38 @@
/************************************************************************************//**
* \file Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/timer.h
* \brief Timer driver header file.
* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef TIMER_H
#define TIMER_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void TimerInit(void);
unsigned long TimerGet(void);
#endif /* TIMER_H */
/*********************************** end of timer.h ************************************/

8
Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/demo.dox Normal file
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@ -0,0 +1,8 @@
/**
\defgroup ARMCM4_S32K14_S32K144EVB_GCC Demo for S32K144EVB/GCC
\ingroup Demos
\brief Preconfigured programs for the NXP S32K144EVB board and the S32 Design Studio
development environment, which is based on the ARM GCC toolchain.
*/

2
Target/Demo/_template/Prog/boot.c
View File

@ -198,7 +198,7 @@ static unsigned char Rs232ReceiveByte(unsigned char *data)
{
unsigned char result = 0;
/* TODO ##Port Check if a new byte was received on the configured channel. This is
/* TODO ##Prog Check if a new byte was received on the configured channel. This is
* typically done by checking the reception register not empty flag. If a new byte
* was received, read it out and store it in '*data'. Next, clear the reception flag
* such that a new byte can be received again. Finally, set 'result' to 1 to indicate

59
Target/Source/ARMCM4_S32K14/GCC/cpu_comp.c Normal file
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/************************************************************************************//**
* \file Source/ARMCM4_S32K14/GCC/cpu_comp.c
* \brief Bootloader cpu module source file.
* \ingroup Target_ARMCM4_S32K14
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
/************************************************************************************//**
** \brief Disable global interrupts.
** \return none.
**
****************************************************************************************/
void CpuIrqDisable(void)
{
/* Disable the global interrupts. */
__asm volatile ("cpsid i" : : : "memory");
} /*** end of CpuIrqDisable ***/
/************************************************************************************//**
** \brief Enable global interrupts.
** \return none.
**
****************************************************************************************/
void CpuIrqEnable(void)
{
/* Enable the global interrupts. */
__asm volatile ("cpsie i" : : : "memory");
} /*** end of CpuIrqEnable ***/
/*********************************** end of cpu_comp.c *********************************/

616
Target/Source/ARMCM4_S32K14/can.c Normal file
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@ -0,0 +1,616 @@
/************************************************************************************//**
* \file Source/ARMCM4_S32K14/can.c
* \brief Bootloader CAN communication interface source file.
* \ingroup Target_ARMCM4_S32K14
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#if (BOOT_COM_CAN_ENABLE > 0)
#include "device_registers.h" /* device registers */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */
#define CAN_INIT_TIMEOUT_MS (250U)
/** \brief Timeout for transmitting a CAN message in milliseconds. */
#define CAN_MSG_TX_TIMEOUT_MS (50U)
#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
/** \brief Set the peripheral CAN0 base pointer. */
#define CANx (CAN0)
/** \brief Set the PCC index offset for CAN0. */
#define PCC_FlexCANx_INDEX (PCC_FlexCAN0_INDEX)
/** \brief Set the number of message boxes supported by CAN0. */
#define CANx_MAX_MB_NUM (FEATURE_CAN0_MAX_MB_NUM)
#elif (BOOT_COM_CAN_CHANNEL_INDEX == 1)
/** \brief Set the peripheral CAN1 base pointer. */
#define CANx (CAN1)
/** \brief Set the PCC index offset for CAN1. */
#define PCC_FlexCANx_INDEX (PCC_FlexCAN1_INDEX)
/** \brief Set the number of message boxes supported by CAN1. */
#define CANx_MAX_MB_NUM (FEATURE_CAN1_MAX_MB_NUM)
#elif (BOOT_COM_CAN_CHANNEL_INDEX == 2)
/** \brief Set the peripheral CAN2 base pointer. */
#define CANx (CAN2)
/** \brief Set the PCC index offset for CAN2. */
#define PCC_FlexCANx_INDEX (PCC_FlexCAN2_INDEX)
/** \brief Set the number of message boxes supported by CAN2. */
#define CANx_MAX_MB_NUM (FEATURE_CAN2_MAX_MB_NUM)
#endif
/** \brief The mailbox used for transmitting the XCP respond message. */
#define CAN_TX_MSGBOX_NUM (8U)
/** \brief The mailbox used for receiving the XCP command message. */
#define CAN_RX_MSGBOX_NUM (9U)
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Structure type for grouping CAN bus timing related information. */
typedef struct t_can_bus_timing
{
blt_int8u timeQuanta; /**< Total number of time quanta */
blt_int8u propSeg; /**< CAN propagation segment */
blt_int8u phaseSeg1; /**< CAN phase segment 1 */
blt_int8u phaseSeg2; /**< CAN phase segment 2 */
} tCanBusTiming;
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief CAN bit timing table for dynamically calculating the bittiming settings.
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + TSEG2)
* * 100%. This array contains possible and valid time quanta configurations
* with a sample point between 68..78%. A visual representation of the TQ in
* a bit is:
* | SYNCSEG | TIME1SEG | TIME2SEG |
* Or with an alternative representation:
* | SYNCSEG | PROPSEG | PHASE1SEG | PHASE2SEG |
* With the alternative representation TIME1SEG = PROPSEG + PHASE1SEG.
*
*/
static const tCanBusTiming canTiming[] =
{
/* Time-Quanta | PROPSEG | PSEG1 | PSEG2 | Sample-Point */
/* ---------------------------------------------------- */
{ 8U, 3U, 2U, 2U }, /*1+3+2+1=8 | 3 | 2 | 2 | 75% */
{ 9U, 3U, 3U, 2U }, /* 9 | 3 | 3 | 2 | 78% */
{ 10U, 3U, 3U, 3U }, /* 10 | 3 | 3 | 3 | 70% */
{ 11U, 4U, 3U, 3U }, /* 11 | 4 | 3 | 3 | 73% */
{ 12U, 4U, 4U, 3U }, /* 12 | 4 | 4 | 3 | 75% */
{ 13U, 5U, 4U, 3U }, /* 13 | 5 | 4 | 3 | 77% */
{ 14U, 5U, 4U, 4U }, /* 14 | 5 | 4 | 4 | 71% */
{ 15U, 6U, 4U, 4U }, /* 15 | 6 | 4 | 4 | 73% */
{ 16U, 6U, 5U, 4U }, /* 16 | 6 | 5 | 4 | 75% */
{ 17U, 7U, 5U, 4U }, /* 17 | 7 | 5 | 4 | 76% */
{ 18U, 7U, 5U, 5U }, /* 18 | 7 | 5 | 5 | 72% */
{ 19U, 8U, 5U, 5U }, /* 19 | 8 | 5 | 5 | 74% */
{ 20U, 8U, 6U, 5U }, /* 20 | 8 | 6 | 5 | 75% */
{ 21U, 8U, 7U, 5U }, /* 21 | 8 | 7 | 5 | 76% */
{ 22U, 8U, 7U, 6U }, /* 22 | 8 | 7 | 6 | 73% */
{ 23U, 8U, 8U, 6U }, /* 23 | 8 | 8 | 6 | 74% */
{ 24U, 8U, 8U, 7U }, /* 24 | 8 | 8 | 7 | 71% */
{ 25U, 8U, 8U, 8U } /* 25 | 8 | 8 | 8 | 68% */
};
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Dummy variable to store the CAN controller's free running timer value in.
* This is needed at the end of a CAN message reception to unlock the mailbox
* again. If this variable is declared locally within the function, it generates
* an unwanted compiler warning about assigning a value and not using it.
* For this reason this dummy variabled is declare here as a module global.
*/
static volatile blt_int32u dummyTimerVal;
/************************************************************************************//**
** \brief Search algorithm to match the desired baudrate to a possible bus
** timing configuration.
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
** \param prescaler Pointer to where the value for the prescaler will be stored.
** \param busTimingCfg Pointer to where the bus timing values will be stored.
** \return BLT_TRUE if the CAN bustiming register values were found, BLT_FALSE
** otherwise.
**
****************************************************************************************/
static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int16u * prescaler,
tCanBusTiming * busTimingCfg)
{
blt_int8u cnt;
blt_int32u canClockFreqkHz;
blt_int32u div2RegValue;
blt_int8u const div2DividerLookup[] =
{
0U, /* 0b000. Output disabled. */
1U, /* 0b001. Divide by 1. */
2U, /* 0b010. Divide by 2. */
4U, /* 0b011. Divide by 4. */
8U, /* 0b100. Divide by 8. */
16U, /* 0b101. Divide by 16. */
32U, /* 0b110. Divide by 32. */
64U, /* 0b111. Divide by 64. */
};
/* Obtain the DIV2 divider value of the SOSC_CLK. */
div2RegValue = (SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT;
/* Check if the DIV2 register value for SOSC is 0. In this case SOSCDIV2_CLK is
* currently disabled.
*/
if (div2RegValue == 0U)
{
/* Configure the DIV2 for a default divide by 1 to make sure the SOSCDIV2_CLK is
* actually enabled.
*/
div2RegValue = 1U;
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(div2RegValue);
}
/* Determine the SOSC clock frequency. */
canClockFreqkHz = BOOT_CPU_XTAL_SPEED_KHZ;
/* Now process the configured DIV2 divider factor to get the actual frequency of the
* CAN peripheral source clock.
*/
canClockFreqkHz /= div2DividerLookup[div2RegValue];
/* Loop through all possible time quanta configurations to find a match. */
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
{
if ((canClockFreqkHz % (baud * canTiming[cnt].timeQuanta)) == 0U)
{
/* Compute the prescaler that goes with this TQ configuration. */
*prescaler = canClockFreqkHz/(baud * canTiming[cnt].timeQuanta);
/* Make sure the prescaler is valid. */
if ((*prescaler > 0U) && (*prescaler <= 256U))
{
/* Store the bustiming configuration. */
*busTimingCfg = canTiming[cnt];
/* Found a good bus timing configuration. */
return BLT_TRUE;
}
}
}
/* Could not find a good bus timing configuration. */
return BLT_FALSE;
} /*** end of CanGetSpeedConfig ***/
/************************************************************************************//**
** \brief Places the CAN controller in freeze mode. Note that the CAN controller
** can only be placed in freeze mode, if it is actually enabled.
** \return none.
**
****************************************************************************************/
static void CanFreezeModeEnter(void)
{
blt_int32u timeout;
/* This function should only be called with the module enabled. */
ASSERT_RT((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U);
/* Request to enter freeze mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(1U);
CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U);
/* Set timeout time for entering freeze mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for freeze mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) == 0U)
{
/* Keep the watchdog happy. */
CopService();
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CanFreezeModeEnter ***/
/************************************************************************************//**
** \brief Leaves the CAN controller's freeze mode. Note that this operation can
** only be done, if it is actually enabled.
** \return none.
**
****************************************************************************************/
static void CanFreezeModeExit(void)
{
blt_int32u timeout;
/* This function should only be called with the module enabled. */
ASSERT_RT((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U);
/* Request to leave freeze mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(0U);
CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(0U);
/* Set timeout time for leaving freeze mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for non freeze mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) != 0U)
{
/* Keep the watchdog happy. */
CopService();
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CanFreezeModeExit ***/
/************************************************************************************//**
** \brief Places the CAN controller in disabled mode.
** \return none.
**
****************************************************************************************/
static void CanDisabledModeEnter(void)
{
blt_int32u timeout;
/* Only continue if the CAN controller is currently enabled. */
if ((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U)
{
/* Request disabled mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(1U);
/* Set timeout time for entering disabled mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for disabled mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) == 0U)
{
/* Keep the watchdog happy. */
CopService();
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
}
} /*** end of CanDisabledModeEnter ***/
/************************************************************************************//**
** \brief Places the CAN controller in enabled mode.
** \return none.
**
****************************************************************************************/
static void CanDisabledModeExit(void)
{
blt_int32u timeout;
/* Only continue if the CAN controller is currently disabled. */
if ((CANx->MCR & CAN_MCR_MDIS_MASK) != 0U)
{
/* Request enabled mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(0U);
/* Set timeout time for leaving disabled mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for disabled mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) != 0U)
{
/* Keep the watchdog happy. */
CopService();
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
}
} /*** end of CanDisabledModeExit ***/
/************************************************************************************//**
** \brief Initializes the CAN controller and synchronizes it to the CAN bus.
** \return none.
**
****************************************************************************************/
void CanInit(void)
{
blt_int16u prescaler = 0;
tCanBusTiming timingCfg = { 0 };
blt_int8u rjw;
blt_int16u idx;
blt_int32u timeout;
blt_int32u rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
/* Perform compile time assertion to check that the configured CAN channel is actually
* supported by this driver.
*/
ASSERT_CT((BOOT_COM_CAN_CHANNEL_INDEX == 0) ||
(BOOT_COM_CAN_CHANNEL_INDEX == 1) ||
(BOOT_COM_CAN_CHANNEL_INDEX == 2));
/* Verify the correct configuration of the transmit and receive mailboxes. */
ASSERT_CT(CAN_TX_MSGBOX_NUM < CANx_MAX_MB_NUM);
ASSERT_CT(CAN_RX_MSGBOX_NUM < CANx_MAX_MB_NUM);
/* Enable the CAN peripheral clock. */
PCC->PCCn[PCC_FlexCANx_INDEX] |= PCC_PCCn_CGC_MASK;
/* The source clock needs to be configured first. For this the CAN controller must be
* in disabled mode, but that can only be entered after first entering freeze mode,
* which in turn can only be in enabled mode. So first enable the module, then goto
* freeze mode and finally enter disabled mode.
*/
CanDisabledModeExit();
CanFreezeModeEnter();
CanDisabledModeEnter();
/* Configure SOSCDIV2 as the source clock. This assumes that an external oscillator
* is available, which is typically the case to meet the clock tolerance requirements
* of the CAN 2.0B secification.
*/
CANx->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK;
/* Leave disabled mode. */
CanDisabledModeExit();
/* Make sure freeze mode is active to be able to initialize the CAN controller. */
CanFreezeModeEnter();
/* Obtain bittiming configuration information. */
if (CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &timingCfg) == BLT_FALSE)
{
/* Incorrect configuration. The specified baudrate is not supported for the given
* clock configuration. Verify the following settings in blt_conf.h:
* - BOOT_COM_CAN_BAUDRATE
* - BOOT_CPU_XTAL_SPEED_KHZ
* - BOOT_CPU_SYSTEM_SPEED_KHZ
*/
ASSERT_RT(BLT_FALSE);
}
/* Reset the current bittiming configuration. */
CANx->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_PROPSEG_MASK |
CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | CAN_CTRL1_RJW_MASK |
CAN_CTRL1_SMP_MASK);
/* Configure the baudrate prescaler. */
CANx->CTRL1 |= CAN_CTRL1_PRESDIV(prescaler - 1U);
/* Configure the propagation segment. */
CANx->CTRL1 |= CAN_CTRL1_PROPSEG(timingCfg.propSeg - 1U);
/* Configure the phase segments. */
CANx->CTRL1 |= CAN_CTRL1_PSEG1(timingCfg.phaseSeg1 - 1U);
CANx->CTRL1 |= CAN_CTRL1_PSEG2(timingCfg.phaseSeg2 - 1U);
/* The resynchronization jump width (RJW) can be 1 - 4 TQ, yet should never be larger
* than pseg1. Configure the longest possible value for RJW.
*/
rjw = (timingCfg.phaseSeg1 < 4) ? timingCfg.phaseSeg1 : 4;
CANx->CTRL1 |= CAN_CTRL1_RJW(rjw - 1U);
/* All the entries in canTiming[] have a PSEG1 >= 2, so three samples can be used to
* determine the value of the received bit, instead of the default one.
*/
CANx->CTRL1 |= CAN_CTRL1_SMP(1U);
/* Clear the message box RAM. Each message box covers 4 words (1 word = 32-bits. */
for (idx = 0; idx < (CANx_MAX_MB_NUM * 4U); idx++)
{
CANx->RAMn[idx] = 0U;
}
/* Clear the reception mask register for each message box. */
for (idx = 0; idx < CANx_MAX_MB_NUM; idx++)
{
CANx->RXIMR[idx] = 0U;
}
/* Configure the maximum number of message boxes. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(CANx_MAX_MB_NUM - 1U);
/* Disable the self reception feature. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_SRXDIS_MASK) | CAN_MCR_SRXDIS(1U);
/* Enable individual reception masking. This disables the legacy support for the
* global reception mask and the mailbox 14/15 individual reception mask.
*/
CANx->MCR = (CANx->MCR & ~CAN_MCR_IRMQ_MASK) | CAN_MCR_IRMQ(1U);
/* Disable the reception FIFO. This driver only needs to receive one CAN message
* identifier. It is sufficient to use just one dedicated mailbox for this.
*/
CANx->MCR &= ~CAN_MCR_RFEN_MASK;
/* Configure the mask of the invididual message reception mailbox to check all ID bits
* and also the IDE bit.
*/
CANx->RXIMR[CAN_RX_MSGBOX_NUM] = 0x40000000U | 0x1FFFFFFFU;
/* Configure the reception mailbox to receive just the CAN message configured with
* BOOT_COM_CAN_RX_MSG_ID.
* EDL, BRS, ESI=0: CANFD not used.
* CODE=0b0100: mailbox set to active and empty.
* IDE=0: 11-bit CAN identifier.
* SRR, RTR, TIME STAMP=0: not applicable.
*/
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] = 0x04000000;
/* Store the message identifier to receive in the mailbox RAM. */
if ((rxMsgId & 0x80000000U) != 0U)
{
/* It is a 29-bit extended CAN identifier. */
rxMsgId &= ~0x80000000U;
/* Set the IDE bit to configure the message for a 29-bit identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_IDE_MASK;
/* Store the 29-bit CAN identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId);
}
else
{
/* Store the 11-bit CAN identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId << 18U);
}
/* Disable all message box interrupts. */
CANx->IMASK1 = 0U;
/* Clear all mesasge box interrupt flags. */
CANx->IFLAG1 = CAN_IMASK1_BUF31TO0M_MASK;
/* Clear all error interrupt flags */
CANx->ESR1 = CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK |
CAN_ESR1_TWRNINT_MASK | CAN_ESR1_BOFFDONEINT_MASK |
CAN_ESR1_ERRINT_FAST_MASK | CAN_ESR1_ERROVR_MASK;
/* Switch to normal user mode. */
CANx->MCR &= ~CAN_MCR_SUPV_MASK;
CANx->CTRL1 &= ~(CAN_CTRL1_LOM_MASK | CAN_CTRL1_LPB_MASK);
/* Exit freeze mode. */
CanFreezeModeExit();
/* Set timeout time for entering normal user mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for normal user mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_NOTRDY_MASK)) != 0U)
{
/* Keep the watchdog happy. */
CopService();
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CanInit ***/
/************************************************************************************//**
** \brief Transmits a packet formatted for the communication interface.
** \param data Pointer to byte array with data that it to be transmitted.
** \param len Number of bytes that are to be transmitted.
** \return none.
**
****************************************************************************************/
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
{
blt_int32u timeout;
blt_bool isExtId = BLT_FALSE;
blt_int32u txMsgId = BOOT_COM_CAN_TX_MSG_ID;
blt_int8u * pMsgBoxData;
blt_int8u byteIdx;
/* Prepare information about the message identifier. */
if ((txMsgId & 0x80000000U) != 0U)
{
/* It is a 29-bit extended CAN identifier. */
txMsgId &= ~0x80000000U;
isExtId = BLT_TRUE;
}
/* Clear the mailbox interrupt flag by writing a 1 to the corresponding box. */
CANx->IFLAG1 = (1U << CAN_TX_MSGBOX_NUM);
/* Prepare the mailbox RAM for a basic CAN message.
* EDL,BRS,ESI=0: CANFD not used.
*/
CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] &= ~0xE0000000U;
/* Configure SRR, IDE, RTR bits for a standard 11-bit transmit frame. */
CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] &= ~(CAN_WMBn_CS_IDE_MASK |
CAN_WMBn_CS_RTR_MASK);
CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_SRR_MASK;
/* Configure the DLC. */
CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] &= ~CAN_WMBn_CS_DLC_MASK;
CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_DLC(len);
/* Write the data bytes of the CAN message to the mailbox RAM. */
pMsgBoxData = (blt_int8u * )(&CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 2U]);
for (byteIdx = 0; byteIdx < len; byteIdx++)
{
pMsgBoxData[((byteIdx) & ~3U) + (3U - ((byteIdx) & 3U))] = data[byteIdx];
}
/* Store the CAN message identifier in the mailbox RAM. */
if (isExtId == BLT_FALSE)
{
/* Store the 11-bit CAN identifier. */
CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(txMsgId << 18U);
}
else
{
/* Set the IDE bit to configure the message for a 29-bit identifier. */
CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_IDE_MASK;
/* Store the 29-bit CAN identifier. */
CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(txMsgId);
}
/* Activate the mailbox to start the transmission by writing 0x0C to the CODE field. */
CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] |= (0x0CU << 24U) & 0x0F000000U;
/* Determine timeout time for the transmit completion. */
timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
/* Poll for completion of the transmit operation. */
while ((CANx->IFLAG1 & (1U << CAN_TX_MSGBOX_NUM)) == 0U)
{
/* Service the watchdog. */
CopService();
/* Break loop upon timeout. this would indicate a hardware failure or no other
* nodes connected to the bus.
*/
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CanTransmitPacket ***/
/************************************************************************************//**
** \brief Receives a communication interface packet if one is present.
** \param data Pointer to byte array where the data is to be stored.
** \param len Pointer where the length of the packet is to be stored.
** \return BLT_TRUE is a packet was received, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool CanReceivePacket(blt_int8u *data, blt_int8u *len)
{
blt_bool result = BLT_FALSE;
blt_int8u * pMsgBoxData;
blt_int8u byteIdx;
/* Check if a message was received in the individual mailbox configured to receive
* the BOOT_COM_CAN_RX_MSG_ID message.
*/
if ((CANx->IFLAG1 & (1U << CAN_RX_MSGBOX_NUM)) != 0U)
{
/* Note that there is no need to verify the identifier of the CAN message because the
* mailbox is configured to only receive the BOOT_COM_CAN_TX_MSG_ID message. Start
* by reading out the DLC of the newly received CAN message.
*/
*len = (CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] & CAN_WMBn_CS_DLC_MASK) >> CAN_WMBn_CS_DLC_SHIFT;
/* Read the data bytes of the CAN message from the mailbox RAM. */
pMsgBoxData = (blt_int8u *)(&CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 2U]);
for (byteIdx = 0; byteIdx < *len; byteIdx++)
{
data[byteIdx] = pMsgBoxData[((byteIdx) & ~3U) + (3U - ((byteIdx) & 3U))];
}
/* Clear the mailbox interrupt flag by writing a 1 to the corresponding box. */
CANx->IFLAG1 = (1U << CAN_RX_MSGBOX_NUM);
/* Read the free running timer to unlock the mailbox. */
dummyTimerVal = CANx->TIMER;
/* Update the result. */
result = BLT_TRUE;
}
/* Give the result back to the caller. */
return result;
} /*** end of CanReceivePacket ***/
#endif /* BOOT_COM_CAN_ENABLE > 0 */
/*********************************** end of can.c **************************************/

192
Target/Source/ARMCM4_S32K14/cpu.c Normal file
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@ -0,0 +1,192 @@
/************************************************************************************//**
* \file Source/ARMCM4_S32K14/cpu.c
* \brief Bootloader cpu module source file.
* \ingroup Target_ARMCM4_S32K14
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "device_registers.h" /* device registers */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Pointer to the user program's reset vector. */
#define CPU_USER_PROGRAM_STARTADDR_PTR ((blt_addr)(NvmGetUserProgBaseAddress() + 0x00000004))
/** \brief Pointer to the user program's vector table. */
#define CPU_USER_PROGRAM_VECTABLE_OFFSET ((blt_addr)NvmGetUserProgBaseAddress())
/****************************************************************************************
* Hook functions
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
extern blt_bool CpuUserProgramStartHook(void);
#endif
/************************************************************************************//**
** \brief Initializes the CPU module.
** \return none.
**
****************************************************************************************/
void CpuInit(void)
{
/* bootloader runs in polling mode so disable the global interrupts. this is done for
* safety reasons. if the bootloader was started from a running user program, it could
* be that the user program did not properly disable the interrupt generation of
* peripherals. */
CpuIrqDisable();
} /*** end of CpuInit ***/
/************************************************************************************//**
** \brief Starts the user program, if one is present. In this case this function
** does not return.
** \return none.
**
****************************************************************************************/
void CpuStartUserProgram(void)
{
void (*pProgResetHandler)(void);
/* check if a user program is present by verifying the checksum */
if (NvmVerifyChecksum() == BLT_FALSE)
{
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
/* bootloader will stay active so perform deferred initialization to make sure
* the communication interface that were not yet initialized are now initialized.
* this is needed to make sure firmware updates via these communication interfaces
* will be possible.
*/
ComDeferredInit();
#endif
/* not a valid user program so it cannot be started */
return;
}
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/* invoke callback */
if (CpuUserProgramStartHook() == BLT_FALSE)
{
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
/* bootloader will stay active so perform deferred initialization to make sure
* the communication interface that were not yet initialized are now initialized.
* this is needed to make sure firmware updates via these communication interfaces
* will be possible.
*/
ComDeferredInit();
#endif
/* callback requests the user program to not be started */
return;
}
#endif
#if (BOOT_COM_ENABLE > 0)
/* release the communication interface */
ComFree();
#endif
/* reset the timer */
TimerReset();
/* remap user program's vector table */
S32_SCB->VTOR = CPU_USER_PROGRAM_VECTABLE_OFFSET & (blt_int32u)0x1FFFFF80;
/* The Cortex-M4 core has interrupts enabled out of reset. the bootloader
* explicitly disables these for security reasons. Enable them here again, so it does
* not have to be done by the user program.
*/
CpuIrqEnable();
/* set the address where the bootloader needs to jump to. this is the address of
* the 2nd entry in the user program's vector table. this address points to the
* user program's reset handler.
*/
pProgResetHandler = (void(*)(void))(*((blt_addr *)CPU_USER_PROGRAM_STARTADDR_PTR));
/* start the user program by calling its reset interrupt service routine */
pProgResetHandler();
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
/* theoretically, the code never gets here because the user program should now be
* running and the previous function call should not return. In case it did return
* for whatever reason, make sure all communication interfaces are initialized so that
* firmware updates can be started.
*/
ComDeferredInit();
#endif
} /*** end of CpuStartUserProgram ***/
/************************************************************************************//**
** \brief Copies data from the source to the destination address.
** \param dest Destination address for the data.
** \param src Source address of the data.
** \param len length of the data in bytes.
** \return none.
**
****************************************************************************************/
void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len)
{
blt_int8u *from, *to;
/* set casted pointers */
from = (blt_int8u *)src;
to = (blt_int8u *)dest;
/* copy all bytes from source address to destination address */
while (len-- > 0)
{
/* store byte value from source to destination */
*to++ = *from++;
/* keep the watchdog happy */
CopService();
}
} /*** end of CpuMemCopy ***/
/************************************************************************************//**
** \brief Sets the bytes at the destination address to the specified value.
** \param dest Destination address for the data.
** \param value Value to write.
** \param len Number of bytes to write.
** \return none.
**
****************************************************************************************/
void CpuMemSet(blt_addr dest, blt_int8u value, blt_int16u len)
{
blt_int8u *to;
/* set casted pointer */
to = (blt_int8u *)dest;
/* set all bytes at the destination address to the specified value */
while (len-- > 0)
{
/* set byte value */
*to++ = value;
/* keep the watchdog happy */
CopService();
}
} /*** end of CpuMemSet ***/
/*********************************** end of cpu.c **************************************/

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/************************************************************************************//**
* \file Source/ARMCM4_S32K14/flash.h
* \brief Bootloader flash driver header file.
* \ingroup Target_ARMCM4_S32K14
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef FLASH_H
#define FLASH_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void FlashInit(void);
void FlashReinit(void);
blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
blt_bool FlashErase(blt_addr addr, blt_int32u len);
blt_bool FlashWriteChecksum(void);
blt_bool FlashVerifyChecksum(void);
blt_bool FlashDone(void);
blt_addr FlashGetUserProgBaseAddress(void);
#endif /* FLASH_H */
/*********************************** end of flash.h ************************************/

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/************************************************************************************//**
* \file Source/ARMCM4_S32K14/nvm.c
* \brief Bootloader non-volatile memory driver source file.
* \ingroup Target_ARMCM4_S32K14
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "flash.h"
/****************************************************************************************
* Hook functions
****************************************************************************************/
#if (BOOT_NVM_HOOKS_ENABLE > 0)
extern void NvmInitHook(void);
extern void NvmReinitHook(void);
extern blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data);
extern blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len);
extern blt_bool NvmDoneHook(void);
#endif
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
extern blt_bool NvmWriteChecksumHook(void);
extern blt_bool NvmVerifyChecksumHook(void);
#endif
/************************************************************************************//**
** \brief Initializes the NVM driver.
** \return none.
**
****************************************************************************************/
void NvmInit(void)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to initialize a driver for operating on NVM
* that is not by default supported by this driver.
*/
NvmInitHook();
#endif
/* init the internal driver */
FlashInit();
} /*** end of NvmInit ***/
/************************************************************************************//**
** \brief Reinitializes the NVM driver. This function is called at the start of each
** firmware update as opposed to NvmInit, which is only called once during
** power on.
** \return none.
**
****************************************************************************************/
void NvmReinit(void)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to re-initialize a driver for operating on NVM
* that is not by default supported by this driver.
*/
NvmReinitHook();
#endif
/* reinitialize the internal driver */
FlashReinit();
} /*** end of NvmReinit ***/
/************************************************************************************//**
** \brief Programs the non-volatile memory.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
blt_int8u result = BLT_NVM_NOT_IN_RANGE;
#endif
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to operate on memory that is not by default supported
* by this driver.
*/
result = NvmWriteHook(addr, len, data);
/* process the return code */
if (result == BLT_NVM_OKAY)
{
/* data was within range of the additionally supported memory and succesfully
* programmed, so we are all done.
*/
return BLT_TRUE;
}
else if (result == BLT_NVM_ERROR)
{
/* data was within range of the additionally supported memory and attempted to be
* programmed, but an error occurred, so we can't continue.
*/
return BLT_FALSE;
}
#endif
/* still here so the internal driver should try and perform the program operation */
return FlashWrite(addr, len, data);
} /*** end of NvmWrite ***/
/************************************************************************************//**
** \brief Erases the non-volatile memory.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmErase(blt_addr addr, blt_int32u len)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
blt_int8u result = BLT_NVM_NOT_IN_RANGE;
#endif
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to operate on memory that is not by default supported
* by this driver.
*/
result = NvmEraseHook(addr, len);
/* process the return code */
if (result == BLT_NVM_OKAY)
{
/* address was within range of the additionally supported memory and succesfully
* erased, so we are all done.
*/
return BLT_TRUE;
}
else if (result == BLT_NVM_ERROR)
{
/* address was within range of the additionally supported memory and attempted to be
* erased, but an error occurred, so we can't continue.
*/
return BLT_FALSE;
}
#endif
/* still here so the internal driver should try and perform the erase operation */
return FlashErase(addr, len);
} /*** end of NvmErase ***/
/************************************************************************************//**
** \brief Verifies the checksum, which indicates that a valid user program is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmVerifyChecksum(void)
{
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/* check checksum using the application specific method. */
return NvmVerifyChecksumHook();
#else
/* check checksum using the interally supported method. */
return FlashVerifyChecksum();
#endif
} /*** end of NvmVerifyChecksum ***/
/************************************************************************************//**
** \brief Obtains the base address of the non-volatile memory available to the user
** program. This is typically that start of the vector table.
** \return Base address.
**
****************************************************************************************/
blt_addr NvmGetUserProgBaseAddress(void)
{
return FlashGetUserProgBaseAddress();
} /*** end of NvmGetUserProgBaseAddress ***/
/************************************************************************************//**
** \brief Once all erase and programming operations are completed, this
** function is called, so at the end of the programming session and
** right before a software reset is performed. It is used to calculate
** a checksum and program this into flash. This checksum is later used
** to determine if a valid user program is present in flash.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmDone(void)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application's NVM driver a chance to finish up */
if (NvmDoneHook() == BLT_FALSE)
{
/* error so no need to continue */
return BLT_FALSE;
}
#endif
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/* compute and write checksum, using the application specific method. */
if (NvmWriteChecksumHook() == BLT_FALSE)
{
return BLT_FALSE;
}
#else
/* compute and write checksum, which is programmed by the internal driver. */
if (FlashWriteChecksum() == BLT_FALSE)
{
return BLT_FALSE;
}
#endif
/* finish up internal driver operations */
return FlashDone();
} /*** end of NvmDone ***/
/*********************************** end of nvm.c **************************************/

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/************************************************************************************//**
* \file Source/ARMCM4_S32K14/uart.c
* \brief Bootloader RS232 communication interface source file.
* \ingroup Target_ARMCM4_S32K14
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#if (BOOT_COM_RS232_ENABLE > 0)
#include "device_registers.h" /* device registers */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
* reception of the first packet byte.
*/
#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100U)
/** \brief Timeout for transmitting a byte in milliseconds. */
#define RS232_BYTE_TX_TIMEOUT_MS (10U)
#if (BOOT_COM_RS232_CHANNEL_INDEX == 0)
/** \brief Set the peripheral LPUART0 base pointer. */
#define LPUARTx (LPUART0)
/** \brief Set the PCC index offset for LPUART0. */
#define PCC_LPUARTx_INDEX (PCC_LPUART0_INDEX)
#elif (BOOT_COM_RS232_CHANNEL_INDEX == 1)
/** \brief Set the peripheral LPUART1 base pointer. */
#define LPUARTx (LPUART1)
/** \brief Set the PCC index offset for LPUART1. */
#define PCC_LPUARTx_INDEX (PCC_LPUART1_INDEX)
#elif (BOOT_COM_RS232_CHANNEL_INDEX == 2)
/** \brief Set the peripheral LPUART2 base pointer. */
#define LPUARTx (LPUART2)
/** \brief Set the PCC index offset for LPUART2. */
#define PCC_LPUARTx_INDEX (PCC_LPUART2_INDEX)
#endif
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static blt_bool Rs232ReceiveByte(blt_int8u *data);
static void Rs232TransmitByte(blt_int8u data);
/************************************************************************************//**
** \brief Initializes the RS232 communication interface.
** \return none.
**
****************************************************************************************/
void Rs232Init(void)
{
blt_int32u sourceClockFreqHz;
blt_int32u div2RegValue;
blt_int16u baudrateSbr0_12;
blt_int8u const div2DividerLookup[] =
{
0U, /* 0b000. Output disabled. */
1U, /* 0b001. Divide by 1. */
2U, /* 0b010. Divide by 2. */
4U, /* 0b011. Divide by 4. */
8U, /* 0b100. Divide by 8. */
16U, /* 0b101. Divide by 16. */
32U, /* 0b110. Divide by 32. */
64U, /* 0b111. Divide by 64. */
};
/* Perform compile time assertion to check that the configured UART channel is actually
* supported by this driver.
*/
ASSERT_CT((BOOT_COM_RS232_CHANNEL_INDEX == 0) ||
(BOOT_COM_RS232_CHANNEL_INDEX == 1) ||
(BOOT_COM_RS232_CHANNEL_INDEX == 2));
/* Make sure the UART peripheral clock is disabled before configuring its source
* clock.
*/
PCC->PCCn[PCC_LPUARTx_INDEX] &= ~PCC_PCCn_CGC_MASK;
/* Select option 2 as the UART peripheral source clock and enable the clock. Option 2
* is the SIRCDIV2_CLK, which is available on all peripherals and configurations.
*/
PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(0b010) | PCC_PCCn_CGC_MASK;
/* Obtain the DIV2 divider value of the SIRC_CLK. */
div2RegValue = (SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT;
/* Check if the DIV2 register value for SIRC is 0. In this case SIRCDIV2_CLK is
* currently disabled.
*/
if (div2RegValue == 0U)
{
/* Configure the DIV2 for a default divide by 1 to make sure the SIRCDIV2_CLK is
* actually enabled.
*/
div2RegValue = 1U;
SCG->SIRCDIV |= SCG_SIRCDIV_SIRCDIV2(div2RegValue);
}
/* Determine the SIRC clock frequency. If SIRC high range is enabled, it is 8 MHz. If
* SIRC low range is enabled, it is 2 MHz.
*/
sourceClockFreqHz = 8000000U;
if ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) == SCG_SIRCCFG_RANGE(0))
{
sourceClockFreqHz = 2000000U;
}
/* Now process the configured DIV2 divider factor to get the actual frequency of the
* UART peripheral source clock.
*/
sourceClockFreqHz /= div2DividerLookup[div2RegValue];
/* Configure the baudrate from BOOT_COM_RS232_BAUDRATE, taking into account that an
* oversampling of 8 will be configured. Default 8,n,1 format is used. Integer
* rounding is used to get the best value for baudrateSbr0_12. Actual baudrate equals
* sourceClockFreqHz / 8 / baudrateSbr0_12.
*/
baudrateSbr0_12 = (((sourceClockFreqHz / BOOT_COM_RS232_BAUDRATE) + (8U - 1U)) / 8U) &
LPUART_BAUD_SBR_MASK;
/* OSR=7: Over sampling ratio = 7+1=8.
* SBNS=0: One stop bit.
* BOTHEDGE=0: receiver samples only on rising edge.
* M10=0: Rx and Tx use 7 to 9 bit data characters.
* RESYNCDIS=0: Resync during rec'd data word supported.
* LBKDIE, RXEDGIE=0: interrupts disable.
* TDMAE, RDMAE, TDMAE=0: DMA requests disabled.
* MAEN1, MAEN2, MATCFG=0: Match disabled.
*/
LPUARTx->BAUD = LPUART_BAUD_SBR(baudrateSbr0_12) | LPUART_BAUD_OSR(7);
/* Clear the error/interrupt flags */
LPUARTx->STAT = FEATURE_LPUART_STAT_REG_FLAGS_MASK;
/* Reset all features/interrupts by default */
LPUARTx->CTRL = 0x00000000;
/* Reset match addresses */
LPUARTx->MATCH = 0x00000000;
#if FEATURE_LPUART_HAS_MODEM_SUPPORT
/* Reset IrDA modem features */
LPUARTx->MODIR = 0x00000000;
#endif
#if FEATURE_LPUART_FIFO_SIZE > 0U
/* Reset FIFO feature */
LPUARTx->FIFO = FEATURE_LPUART_FIFO_RESET_MASK;
/* Enable the transmit and receive FIFOs. */
LPUARTx->FIFO |= LPUART_FIFO_TXFE(1) | LPUART_FIFO_RXFE(1);
/* Set the reception water mark to 0 and the transmitter water mark to 1. */
LPUARTx->WATER = LPUART_WATER_TXWATER(1) | LPUART_WATER_RXWATER(0);
#endif
/* Enable transmitter and receiver, no parity, 8 bit char:
* RE=1: Receiver enabled.
* TE=1: Transmitter enabled.
* PE,PT=0: No hw parity generation or checking.
* M7,M,R8T9,R9T8=0: 8-bit data characters.
* DOZEEN=0: LPUART enabled in Doze mode.
* ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ.
* TxDIR=0: TxD pin is input if in single-wire mode.
* TXINV=0: Transmit data not inverted.
* RWU,WAKE=0: normal operation; rcvr not in standby.
* IDLCFG=0: one idle character.
* ILT=0: Idle char bit count starts after start bit.
* SBK=0: Normal transmitter operation - no break char.
* LOOPS,RSRC=0: no loop back.
*/
LPUARTx->CTRL = LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK;
} /*** end of Rs232Init ***/
/************************************************************************************//**
** \brief Transmits a packet formatted for the communication interface.
** \param data Pointer to byte array with data that it to be transmitted.
** \param len Number of bytes that are to be transmitted.
** \return none.
**
****************************************************************************************/
void Rs232TransmitPacket(blt_int8u *data, blt_int8u len)
{
blt_int16u data_index;
/* Verify validity of the len-paramenter. */
ASSERT_RT(len <= BOOT_COM_RS232_TX_MAX_DATA);
/* First transmit the length of the packet. */
Rs232TransmitByte(len);
/* Transmit all the packet bytes one-by-one. */
for (data_index = 0U; data_index < len; data_index++)
{
/* Keep the watchdog happy. */
CopService();
/* Write byte. */
Rs232TransmitByte(data[data_index]);
}
} /*** end of Rs232TransmitPacket ***/
/************************************************************************************//**
** \brief Receives a communication interface packet if one is present.
** \param data Pointer to byte array where the data is to be stored.
** \param len Pointer where the length of the packet is to be stored.
** \return BLT_TRUE if a packet was received, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool Rs232ReceivePacket(blt_int8u *data, blt_int8u *len)
{
static blt_int8u xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1U]; /* One extra for length. */
static blt_int8u xcpCtoRxLength;
static blt_bool xcpCtoRxInProgress = BLT_FALSE;
static blt_int32u xcpCtoRxStartTime = 0U;
/* Start of cto packet received? */
if (xcpCtoRxInProgress == BLT_FALSE)
{
/* Store the message length when received. */
if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == BLT_TRUE)
{
if ( (xcpCtoReqPacket[0] > 0U) &&
(xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) )
{
/* Store the start time. */
xcpCtoRxStartTime = TimerGet();
/* Reset packet data count. */
xcpCtoRxLength = 0U;
/* Indicate that a cto packet is being received. */
xcpCtoRxInProgress = BLT_TRUE;
}
}
}
else
{
/* Store the next packet byte. */
if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1U]) == BLT_TRUE)
{
/* Increment the packet data count. */
xcpCtoRxLength++;
/* Check to see if the entire packet was received. */
if (xcpCtoRxLength == xcpCtoReqPacket[0])
{
/* Copy the packet data. */
CpuMemCopy((blt_int32u)data, (blt_int32u)&xcpCtoReqPacket[1], xcpCtoRxLength);
/* Done with cto packet reception. */
xcpCtoRxInProgress = BLT_FALSE;
/* Set the packet length. */
*len = xcpCtoRxLength;
/* Packet reception complete. */
return BLT_TRUE;
}
}
else
{
/* Check packet reception timeout. */
if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS))
{
/* Cancel cto packet reception due to timeout. Note that that automaticaly
* discards the already received packet bytes, allowing the host to retry.
*/
xcpCtoRxInProgress = BLT_FALSE;
}
}
}
/* Packet reception not yet complete. */
return BLT_FALSE;
} /*** end of Rs232ReceivePacket ***/
/************************************************************************************//**
** \brief Receives a communication interface byte if one is present.
** \param data Pointer to byte where the data is to be stored.
** \return BLT_TRUE if a byte was received, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool Rs232ReceiveByte(blt_int8u *data)
{
blt_bool result = BLT_FALSE;
/* Check if a new byte was received by means of the RDRF-bit. */
if (((LPUARTx->STAT & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_RDRF_SHIFT) != 0U)
{
/* Retrieve and store the newly received byte. */
*data = LPUARTx->DATA;
/* Update the result. */
result = BLT_TRUE;
}
/* Give the result back to the caller. */
return result;
} /*** end of Rs232ReceiveByte ***/
/************************************************************************************//**
** \brief Transmits a communication interface byte.
** \param data Value of byte that is to be transmitted.
** \return none.
**
****************************************************************************************/
static void Rs232TransmitByte(blt_int8u data)
{
blt_int32u timeout;
/* Write the byte value in 'data' to the transmit register of the UART peripheral such
* that the transmission of the byte value is started.
*/
LPUARTx->DATA = data;
/* Set timeout time to wait for transmit completion. */
timeout = TimerGet() + RS232_BYTE_TX_TIMEOUT_MS;
/* Wait for tx holding register to be empty. */
while (((LPUARTx->STAT & LPUART_STAT_TDRE_MASK) >> LPUART_STAT_TDRE_SHIFT) == 0U)
{
/* Keep the watchdog happy. */
CopService();
/* Break loop upon timeout. this would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of Rs232TransmitByte ***/
#endif /* BOOT_COM_RS232_ENABLE > 0 */
/*********************************** end of rs232.c ************************************/

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/**
\defgroup Target_ARMCM4_S32K14 Target ARMCM4 S32K14
\ingroup Ports
\brief Target dependent code for the NXP ARMCM4 S32K14x microcontroller family.
\details This module implements the bootloader's target dependent part for the
NXP ARMCM4 S32K14x microcontroller family.
*/

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/************************************************************************************//**
* \file Source/ARMCM4_S32K14/timer.c
* \brief Bootloader timer driver source file.
* \ingroup Target_ARMCM4_S32K14
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "device_registers.h" /* device registers */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Local variable for storing the number of milliseconds that have elapsed since
* startup.
*/
static blt_int32u millisecond_counter;
/************************************************************************************//**
** \brief Initializes the polling based millisecond timer driver.
** \return none.
**
****************************************************************************************/
void TimerInit(void)
{
/* Reset the timer configuration. */
TimerReset();
/* Configure the systick frequency as a 1 ms event generator. */
S32_SysTick->RVR = BOOT_CPU_SYSTEM_SPEED_KHZ - 1;
/* Reset the current counter value. */
S32_SysTick->CVR = 0u;
/* Select core clock as source and enable the timer. */
S32_SysTick->CSR = S32_SysTick_CSR_ENABLE_MASK | S32_SysTick_CSR_CLKSOURCE_MASK;
/* Reset the millisecond counter value. */
millisecond_counter = 0;
} /*** end of TimerInit ***/
/************************************************************************************//**
** \brief Reset the timer by placing the timer back into it's default reset
** configuration.
** \return none.
**
****************************************************************************************/
void TimerReset(void)
{
/* Set the systick's status and control register back into the default reset value. */
S32_SysTick->CSR = 0;
} /* end of TimerReset */
/************************************************************************************//**
** \brief Updates the millisecond timer.
** \return none.
**
****************************************************************************************/
void TimerUpdate(void)
{
/* Check if the millisecond event occurred. */
if ((S32_SysTick->CSR & S32_SysTick_CSR_COUNTFLAG_MASK) != 0)
{
/* Increment the millisecond counter. */
millisecond_counter++;
}
} /*** end of TimerUpdate ***/
/************************************************************************************//**
** \brief Obtains the counter value of the millisecond timer.
** \return Current value of the millisecond timer.
**
****************************************************************************************/
blt_int32u TimerGet(void)
{
/* Updating timer here allows this function to be called in a loop with timeout
* detection.
*/
TimerUpdate();
/* Read and return the amount of milliseconds that passed since initialization. */
return millisecond_counter;
} /*** end of TimerGet ***/
/*********************************** end of timer.c ************************************/

57
Target/Source/ARMCM4_S32K14/types.h Normal file
View File

@ -0,0 +1,57 @@
/************************************************************************************//**
* \file Source/ARMCM4_S32K14/types.h
* \brief Bootloader types header file.
* \ingroup Target_ARMCM4_S32K14
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef TYPES_H
#define TYPES_H
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Boolean true value. */
#define BLT_TRUE (1)
/** \brief Boolean false value. */
#define BLT_FALSE (0)
/** \brief NULL pointer value. */
#define BLT_NULL ((void *)0)
/****************************************************************************************
* Type definitions
****************************************************************************************/
typedef unsigned char blt_bool; /**< boolean type */
typedef char blt_char; /**< character type */
typedef unsigned long blt_addr; /**< memory address type */
typedef unsigned char blt_int8u; /**< 8-bit unsigned integer */
typedef signed char blt_int8s; /**< 8-bit signed integer */
typedef unsigned short blt_int16u; /**< 16-bit unsigned integer */
typedef signed short blt_int16s; /**< 16-bit signed integer */
typedef unsigned int blt_int32u; /**< 32-bit unsigned integer */
typedef signed int blt_int32s; /**< 32-bit signed integer */
#endif /* TYPES_H */
/*********************************** end of types.h ************************************/

2
Target/Source/_template/can.c
View File

@ -181,7 +181,7 @@ void CanInit(void)
ASSERT_RT(BLT_FALSE);
}
/* TODO ##Vg Perform the configuration and initialization of the CAN controller. Note
/* TODO ##Port Perform the configuration and initialization of the CAN controller. Note
* that the bittiming related values are already stored in 'prescaler, 'tseg1', and
* 'tseg2'. There values are ready to be used. Typically, the following tasks need
* to be performed: